Avoid creating two TargetLowering objects for each target.

Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57016 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 46b9a19376ed6883e5d15ec735df7a90b3d3fdbf..560be0ad96e21eccbdd19e6958c2dc2b625af4bb 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -39,15 +39,13 @@ namespace {
 class ARMDAGToDAGISel : public SelectionDAGISel {
   ARMTargetMachine &TM;
 
-  ARMTargetLowering ARMLowering;
-
   /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
   /// make the right decision when generating code for different targets.
   const ARMSubtarget *Subtarget;
 
 public:
   explicit ARMDAGToDAGISel(ARMTargetMachine &tm)
-    : SelectionDAGISel(ARMLowering), TM(tm), ARMLowering(tm),
+    : SelectionDAGISel(*tm.getTargetLowering()), TM(tm),
     Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
   }
 

diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 8b298db243c2fb4b20f18e326b70edcd48129a4c..07a0ae2ba93931ca6530e9fc19ac97e8e4036f90 100644 (file)
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -40,8 +40,6 @@ namespace {
   /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
   /// instructions for SelectionDAG operations.
   class AlphaDAGToDAGISel : public SelectionDAGISel {
-    AlphaTargetLowering AlphaLowering;
-
     static const int64_t IMM_LOW  = -32768;
     static const int64_t IMM_HIGH = 32767;
     static const int64_t IMM_MULT = 65536;
@@ -147,8 +145,7 @@ namespace {
 
   public:
     explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
-      : SelectionDAGISel(AlphaLowering), 
-        AlphaLowering(*TM.getTargetLowering())
+      : SelectionDAGISel(*TM.getTargetLowering())
     {}
 
     /// getI64Imm - Return a target constant with the specified value, of type

diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index f79496db77def3f067cb6f26b0c878620022abda..18b9ecf94eda11b31efd6ca1431d7ffd584aa21b 100644 (file)
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -37,11 +37,10 @@ namespace {
   /// instructions for SelectionDAG operations.
   ///
   class IA64DAGToDAGISel : public SelectionDAGISel {
-    IA64TargetLowering IA64Lowering;
     unsigned GlobalBaseReg;
   public:
     explicit IA64DAGToDAGISel(IA64TargetMachine &TM)
-      : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
+      : SelectionDAGISel(*TM.getTargetLowering()) {}
     
     virtual bool runOnFunction(Function &Fn) {
       // Make sure we re-emit a set of the global base reg if necessary

diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp
index a408a9623ca4d3f7d7b27335da65332ea1a6ffca..669f62f9f17111c1c15b4c716cefea1d667827d6 100644 (file)
--- a/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -52,19 +52,14 @@ class VISIBILITY_HIDDEN MipsDAGToDAGISel : public SelectionDAGISel {
   /// TM - Keep a reference to MipsTargetMachine.
   MipsTargetMachine &TM;
 
-  /// MipsLowering - This object fully describes how to lower LLVM code to an
-  /// Mips-specific SelectionDAG.
-  MipsTargetLowering MipsLowering;
-
   /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
   /// make the right decision when generating code for different targets.
   const MipsSubtarget &Subtarget;
  
 public:
   explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
-  SelectionDAGISel(MipsLowering),
-  TM(tm), MipsLowering(*TM.getTargetLowering()), 
-  Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
+  SelectionDAGISel(*tm.getTargetLowering()),
+  TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
   
   virtual void InstructionSelect();
 

diff --git a/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp b/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
index 3fc7c72a61c0c6678579872765d74a5762810f8f..285c5a6355eac13e8ac3be49c26195ce17b03254 100644 (file)
--- a/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
+++ b/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
@@ -51,14 +51,10 @@ class VISIBILITY_HIDDEN PIC16DAGToDAGISel : public SelectionDAGISel {
   /// TM - Keep a reference to PIC16TargetMachine.
   PIC16TargetMachine &TM;
 
-  /// PIC16Lowering - This object fully describes how to lower LLVM code to an
-  /// PIC16-specific SelectionDAG.
-  PIC16TargetLowering PIC16Lowering;
-
 public:
   explicit PIC16DAGToDAGISel(PIC16TargetMachine &tm) : 
-        SelectionDAGISel(PIC16Lowering),
-        TM(tm), PIC16Lowering(*TM.getTargetLowering()) {}
+        SelectionDAGISel(*tm.getTargetLowering()),
+        TM(tm) {}
   
   virtual void InstructionSelect();
 

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 6b2ec4a8904fb9d7962a762f762ac340061168b8..56d6a58591a21b6e0c76c3bb8a3a70caaa7f6dde 100644 (file)
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -41,12 +41,12 @@ namespace {
   ///
   class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel {
     PPCTargetMachine &TM;
-    PPCTargetLowering PPCLowering;
+    PPCTargetLowering &PPCLowering;
     const PPCSubtarget &PPCSubTarget;
     unsigned GlobalBaseReg;
   public:
     explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
-      : SelectionDAGISel(PPCLowering), TM(tm),
+      : SelectionDAGISel(*tm.getTargetLowering()), TM(tm),
         PPCLowering(*TM.getTargetLowering()),
         PPCSubTarget(*TM.getSubtargetImpl()) {}
     

diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h
index 4f02ab87d4f224492b5db2e41c3df81668b1f1c5..1096144e87b7cdb7d7af77107cb9baaeddc915e0 100644 (file)
--- a/lib/Target/Sparc/Sparc.h
+++ b/lib/Target/Sparc/Sparc.h
@@ -21,9 +21,10 @@
 namespace llvm {
   class FunctionPass;
   class TargetMachine;
+  class SparcTargetMachine;
   class raw_ostream;
 
-  FunctionPass *createSparcISelDag(TargetMachine &TM);
+  FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
   FunctionPass *createSparcCodePrinterPass(raw_ostream &OS, TargetMachine &TM);
   FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
   FunctionPass *createSparcFPMoverPass(TargetMachine &TM);

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 4a3ca7fa0669bce837b4cdfe26abb6200ae7b4b7..d7aa08f8ca666c8c907d08fd797d3b0e77780ffb 100644 (file)
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -29,14 +29,12 @@ using namespace llvm;
 ///
 namespace {
 class SparcDAGToDAGISel : public SelectionDAGISel {
-  SparcTargetLowering Lowering;
-
   /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
   /// make the right decision when generating code for different targets.
   const SparcSubtarget &Subtarget;
 public:
-  explicit SparcDAGToDAGISel(TargetMachine &TM)
-    : SelectionDAGISel(Lowering), Lowering(TM),
+  explicit SparcDAGToDAGISel(SparcTargetMachine &TM)
+    : SelectionDAGISel(*TM.getTargetLowering()),
       Subtarget(TM.getSubtarget<SparcSubtarget>()) {
   }
 
@@ -189,6 +187,6 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
 /// createSparcISelDag - This pass converts a legalized DAG into a 
 /// SPARC-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
+FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
   return new SparcDAGToDAGISel(TM);
 }

diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index e0ab42edda179ba27c58b30a38c20e95ae9d695b..cc730f82671b1a6554c852119caae775855c08df 100644 (file)
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -30,7 +30,7 @@ const TargetAsmInfo *SparcTargetMachine::createTargetAsmInfo() const {
 ///
 SparcTargetMachine::SparcTargetMachine(const Module &M, const std::string &FS)
   : DataLayout("E-p:32:32-f128:128:128"),
-    Subtarget(M, FS), InstrInfo(Subtarget),
+    Subtarget(M, FS), TLInfo(*this), InstrInfo(Subtarget),
     FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
 }
 

diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h
index d7c383787ef47106c2edd14659134222c1d9a5a4..eca5f28a80175232b3de25e992f6fa1f1748c188 100644 (file)
--- a/lib/Target/Sparc/SparcTargetMachine.h
+++ b/lib/Target/Sparc/SparcTargetMachine.h
@@ -19,6 +19,7 @@
 #include "llvm/Target/TargetFrameInfo.h"
 #include "SparcInstrInfo.h"
 #include "SparcSubtarget.h"
+#include "SparcISelLowering.h"
 
 namespace llvm {
 
@@ -27,6 +28,7 @@ class Module;
 class SparcTargetMachine : public LLVMTargetMachine {
   const TargetData DataLayout;       // Calculates type size & alignment
   SparcSubtarget Subtarget;
+  SparcTargetLowering TLInfo;
   SparcInstrInfo InstrInfo;
   TargetFrameInfo FrameInfo;
   
@@ -42,6 +44,9 @@ public:
   virtual const SparcRegisterInfo *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }
+  virtual SparcTargetLowering* getTargetLowering() const {
+    return const_cast<SparcTargetLowering*>(&TLInfo);
+  }
   virtual const TargetData       *getTargetData() const { return &DataLayout; }
   static unsigned getModuleMatchQuality(const Module &M);
 

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 06dfc21d07859637033919410dc1d30ab8a59de7..35c5b4224384540a659750b077ba6269ae4cbffd 100644 (file)
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -113,7 +113,7 @@ namespace {
 
     /// X86Lowering - This object fully describes how to lower LLVM code to an
     /// X86-specific SelectionDAG.
-    X86TargetLowering X86Lowering;
+    X86TargetLowering &X86Lowering;
 
     /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
     /// make the right decision when generating code for different targets.
@@ -129,7 +129,7 @@ namespace {
 
   public:
     X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
-      : SelectionDAGISel(X86Lowering, fast),
+      : SelectionDAGISel(*tm.getTargetLowering(), fast),
         TM(tm), X86Lowering(*TM.getTargetLowering()),
         Subtarget(&TM.getSubtarget<X86Subtarget>()),
         OptForSize(false) {}