1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
27 #define DEBUG_TYPE "mips-disassembler"
29 typedef MCDisassembler::DecodeStatus DecodeStatus;
33 /// A disasembler class for Mips.
34 class MipsDisassemblerBase : public MCDisassembler {
36 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
38 : MCDisassembler(STI, Ctx),
39 IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit),
40 IsBigEndian(IsBigEndian) {}
42 virtual ~MipsDisassemblerBase() {}
44 bool isGP64Bit() const { return IsGP64Bit; }
52 /// A disasembler class for Mips32.
53 class MipsDisassembler : public MipsDisassemblerBase {
56 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
57 : MipsDisassemblerBase(STI, Ctx, bigEndian) {
58 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
61 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
62 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
63 bool hasMips32r6() const {
64 return STI.getFeatureBits() & Mips::FeatureMips32r6;
67 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
69 bool hasCOP3() const {
70 // Only present in MIPS-I and MIPS-II
71 return !hasMips32() && !hasMips3();
74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
75 ArrayRef<uint8_t> Bytes, uint64_t Address,
77 raw_ostream &CStream) const override;
80 /// A disasembler class for Mips64.
81 class Mips64Disassembler : public MipsDisassemblerBase {
83 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
85 MipsDisassemblerBase(STI, Ctx, bigEndian) {}
87 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
88 ArrayRef<uint8_t> Bytes, uint64_t Address,
90 raw_ostream &CStream) const override;
93 } // end anonymous namespace
95 // Forward declare these because the autogenerated code will reference them.
96 // Definitions are further down.
97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
100 const void *Decoder);
102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
105 const void *Decoder);
107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
110 const void *Decoder);
112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
115 const void *Decoder);
117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
120 const void *Decoder);
122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
125 const void *Decoder);
127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
130 const void *Decoder);
132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
135 const void *Decoder);
137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
140 const void *Decoder);
142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
145 const void *Decoder);
147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
150 const void *Decoder);
152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
154 const void *Decoder);
156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
159 const void *Decoder);
161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
164 const void *Decoder);
166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
169 const void *Decoder);
171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
174 const void *Decoder);
176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
179 const void *Decoder);
181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
184 const void *Decoder);
186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
189 const void *Decoder);
191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
194 const void *Decoder);
196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
199 const void *Decoder);
201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
204 const void *Decoder);
206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
209 const void *Decoder);
211 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
214 const void *Decoder);
216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
219 const void *Decoder);
221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
224 const void *Decoder);
226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
229 const void *Decoder);
231 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
232 // shifted left by 1 bit.
233 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
236 const void *Decoder);
238 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
239 // shifted left by 1 bit.
240 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
243 const void *Decoder);
245 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
246 // shifted left by 1 bit.
247 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
250 const void *Decoder);
252 static DecodeStatus DecodeMem(MCInst &Inst,
255 const void *Decoder);
257 static DecodeStatus DecodeCacheOp(MCInst &Inst,
260 const void *Decoder);
262 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
265 const void *Decoder);
267 static DecodeStatus DecodeSyncI(MCInst &Inst,
270 const void *Decoder);
272 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
273 uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
278 const void *Decoder);
280 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
283 const void *Decoder);
285 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
288 const void *Decoder);
290 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
293 const void *Decoder);
295 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
297 const void *Decoder);
299 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
301 const void *Decoder);
303 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
305 const void *Decoder);
307 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
309 const void *Decoder);
311 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
314 const void *Decoder);
316 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
319 const void *Decoder);
321 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
324 const void *Decoder);
326 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
329 const void *Decoder);
331 static DecodeStatus DecodeSimm4(MCInst &Inst,
334 const void *Decoder);
336 static DecodeStatus DecodeSimm16(MCInst &Inst,
339 const void *Decoder);
341 // Decode the immediate field of an LSA instruction which
343 static DecodeStatus DecodeLSAImm(MCInst &Inst,
346 const void *Decoder);
348 static DecodeStatus DecodeInsSize(MCInst &Inst,
351 const void *Decoder);
353 static DecodeStatus DecodeExtSize(MCInst &Inst,
356 const void *Decoder);
358 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
359 uint64_t Address, const void *Decoder);
361 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
362 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
365 uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
368 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
371 uint64_t Address, const void *Decoder);
373 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
375 template <typename InsnType>
376 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
377 const void *Decoder);
379 template <typename InsnType>
381 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
382 const void *Decoder);
384 template <typename InsnType>
386 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
387 const void *Decoder);
389 template <typename InsnType>
391 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
392 const void *Decoder);
394 template <typename InsnType>
396 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
397 const void *Decoder);
399 template <typename InsnType>
401 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
402 const void *Decoder);
404 template <typename InsnType>
406 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
407 const void *Decoder);
409 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
411 const void *Decoder);
413 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
415 const void *Decoder);
418 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
422 static MCDisassembler *createMipsDisassembler(
424 const MCSubtargetInfo &STI,
426 return new MipsDisassembler(STI, Ctx, true);
429 static MCDisassembler *createMipselDisassembler(
431 const MCSubtargetInfo &STI,
433 return new MipsDisassembler(STI, Ctx, false);
436 static MCDisassembler *createMips64Disassembler(
438 const MCSubtargetInfo &STI,
440 return new Mips64Disassembler(STI, Ctx, true);
443 static MCDisassembler *createMips64elDisassembler(
445 const MCSubtargetInfo &STI,
447 return new Mips64Disassembler(STI, Ctx, false);
450 extern "C" void LLVMInitializeMipsDisassembler() {
451 // Register the disassembler.
452 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
453 createMipsDisassembler);
454 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
455 createMipselDisassembler);
456 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
457 createMips64Disassembler);
458 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
459 createMips64elDisassembler);
462 #include "MipsGenDisassemblerTables.inc"
464 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
465 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
466 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
467 return *(RegInfo->getRegClass(RC).begin() + RegNo);
470 template <typename InsnType>
471 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
472 const void *Decoder) {
473 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
474 // The size of the n field depends on the element size
475 // The register class also depends on this.
476 InsnType tmp = fieldFromInstruction(insn, 17, 5);
478 DecodeFN RegDecoder = nullptr;
479 if ((tmp & 0x18) == 0x00) { // INSVE_B
481 RegDecoder = DecodeMSA128BRegisterClass;
482 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
484 RegDecoder = DecodeMSA128HRegisterClass;
485 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
487 RegDecoder = DecodeMSA128WRegisterClass;
488 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
490 RegDecoder = DecodeMSA128DRegisterClass;
492 llvm_unreachable("Invalid encoding");
494 assert(NSize != 0 && RegDecoder != nullptr);
497 tmp = fieldFromInstruction(insn, 6, 5);
498 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
499 return MCDisassembler::Fail;
501 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
502 return MCDisassembler::Fail;
504 tmp = fieldFromInstruction(insn, 16, NSize);
505 MI.addOperand(MCOperand::CreateImm(tmp));
507 tmp = fieldFromInstruction(insn, 11, 5);
508 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
509 return MCDisassembler::Fail;
511 MI.addOperand(MCOperand::CreateImm(0));
513 return MCDisassembler::Success;
516 template <typename InsnType>
517 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
519 const void *Decoder) {
520 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
521 // (otherwise we would have matched the ADDI instruction from the earlier
525 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
527 // BEQZALC if rs == 0 && rt != 0
528 // BEQC if rs < rt && rs != 0
530 InsnType Rs = fieldFromInstruction(insn, 21, 5);
531 InsnType Rt = fieldFromInstruction(insn, 16, 5);
532 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
536 MI.setOpcode(Mips::BOVC);
538 } else if (Rs != 0 && Rs < Rt) {
539 MI.setOpcode(Mips::BEQC);
542 MI.setOpcode(Mips::BEQZALC);
545 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
548 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
550 MI.addOperand(MCOperand::CreateImm(Imm));
552 return MCDisassembler::Success;
555 template <typename InsnType>
556 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
558 const void *Decoder) {
559 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
560 // (otherwise we would have matched the ADDI instruction from the earlier
564 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
566 // BNEZALC if rs == 0 && rt != 0
567 // BNEC if rs < rt && rs != 0
569 InsnType Rs = fieldFromInstruction(insn, 21, 5);
570 InsnType Rt = fieldFromInstruction(insn, 16, 5);
571 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
575 MI.setOpcode(Mips::BNVC);
577 } else if (Rs != 0 && Rs < Rt) {
578 MI.setOpcode(Mips::BNEC);
581 MI.setOpcode(Mips::BNEZALC);
584 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
587 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
589 MI.addOperand(MCOperand::CreateImm(Imm));
591 return MCDisassembler::Success;
594 template <typename InsnType>
595 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
597 const void *Decoder) {
598 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
599 // (otherwise we would have matched the BLEZL instruction from the earlier
603 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
604 // Invalid if rs == 0
605 // BLEZC if rs == 0 && rt != 0
606 // BGEZC if rs == rt && rt != 0
607 // BGEC if rs != rt && rs != 0 && rt != 0
609 InsnType Rs = fieldFromInstruction(insn, 21, 5);
610 InsnType Rt = fieldFromInstruction(insn, 16, 5);
611 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
615 return MCDisassembler::Fail;
617 MI.setOpcode(Mips::BLEZC);
619 MI.setOpcode(Mips::BGEZC);
622 MI.setOpcode(Mips::BGEC);
626 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
629 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
632 MI.addOperand(MCOperand::CreateImm(Imm));
634 return MCDisassembler::Success;
637 template <typename InsnType>
638 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
640 const void *Decoder) {
641 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
642 // (otherwise we would have matched the BGTZL instruction from the earlier
646 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
647 // Invalid if rs == 0
648 // BGTZC if rs == 0 && rt != 0
649 // BLTZC if rs == rt && rt != 0
650 // BLTC if rs != rt && rs != 0 && rt != 0
654 InsnType Rs = fieldFromInstruction(insn, 21, 5);
655 InsnType Rt = fieldFromInstruction(insn, 16, 5);
656 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
659 return MCDisassembler::Fail;
661 MI.setOpcode(Mips::BGTZC);
663 MI.setOpcode(Mips::BLTZC);
665 MI.setOpcode(Mips::BLTC);
670 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
673 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
676 MI.addOperand(MCOperand::CreateImm(Imm));
678 return MCDisassembler::Success;
681 template <typename InsnType>
682 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
684 const void *Decoder) {
685 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
686 // (otherwise we would have matched the BGTZ instruction from the earlier
690 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
692 // BGTZALC if rs == 0 && rt != 0
693 // BLTZALC if rs != 0 && rs == rt
694 // BLTUC if rs != 0 && rs != rt
696 InsnType Rs = fieldFromInstruction(insn, 21, 5);
697 InsnType Rt = fieldFromInstruction(insn, 16, 5);
698 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
703 MI.setOpcode(Mips::BGTZ);
705 } else if (Rs == 0) {
706 MI.setOpcode(Mips::BGTZALC);
708 } else if (Rs == Rt) {
709 MI.setOpcode(Mips::BLTZALC);
712 MI.setOpcode(Mips::BLTUC);
718 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
722 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
725 MI.addOperand(MCOperand::CreateImm(Imm));
727 return MCDisassembler::Success;
730 template <typename InsnType>
731 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
733 const void *Decoder) {
734 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
735 // (otherwise we would have matched the BLEZL instruction from the earlier
739 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
740 // Invalid if rs == 0
741 // BLEZALC if rs == 0 && rt != 0
742 // BGEZALC if rs == rt && rt != 0
743 // BGEUC if rs != rt && rs != 0 && rt != 0
745 InsnType Rs = fieldFromInstruction(insn, 21, 5);
746 InsnType Rt = fieldFromInstruction(insn, 16, 5);
747 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
751 return MCDisassembler::Fail;
753 MI.setOpcode(Mips::BLEZALC);
755 MI.setOpcode(Mips::BGEZALC);
758 MI.setOpcode(Mips::BGEUC);
762 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
764 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
767 MI.addOperand(MCOperand::CreateImm(Imm));
769 return MCDisassembler::Success;
772 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
773 /// according to the given endianess.
774 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
775 uint64_t &Size, uint32_t &Insn,
777 // We want to read exactly 2 Bytes of data.
778 if (Bytes.size() < 2) {
780 return MCDisassembler::Fail;
784 Insn = (Bytes[0] << 8) | Bytes[1];
786 Insn = (Bytes[1] << 8) | Bytes[0];
789 return MCDisassembler::Success;
792 /// Read four bytes from the ArrayRef and return 32 bit word sorted
793 /// according to the given endianess
794 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
795 uint64_t &Size, uint32_t &Insn,
796 bool IsBigEndian, bool IsMicroMips) {
797 // We want to read exactly 4 Bytes of data.
798 if (Bytes.size() < 4) {
800 return MCDisassembler::Fail;
803 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
804 // always precede the low 16 bits in the instruction stream (that is, they
805 // are placed at lower addresses in the instruction stream).
807 // microMIPS byte ordering:
808 // Big-endian: 0 | 1 | 2 | 3
809 // Little-endian: 1 | 0 | 3 | 2
812 // Encoded as a big-endian 32-bit word in the stream.
814 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
817 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
820 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
825 return MCDisassembler::Success;
828 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
829 ArrayRef<uint8_t> Bytes,
831 raw_ostream &VStream,
832 raw_ostream &CStream) const {
837 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
839 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
840 // Calling the auto-generated decoder function.
841 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
843 if (Result != MCDisassembler::Fail) {
848 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
849 if (Result == MCDisassembler::Fail)
850 return MCDisassembler::Fail;
852 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
853 // Calling the auto-generated decoder function.
854 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
856 if (Result != MCDisassembler::Fail) {
860 return MCDisassembler::Fail;
863 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
864 if (Result == MCDisassembler::Fail)
865 return MCDisassembler::Fail;
868 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
870 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
871 if (Result != MCDisassembler::Fail) {
877 if (hasMips32r6() && isGP64()) {
878 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
879 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
881 if (Result != MCDisassembler::Fail) {
888 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
889 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
891 if (Result != MCDisassembler::Fail) {
897 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
898 // Calling the auto-generated decoder function.
900 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
901 if (Result != MCDisassembler::Fail) {
906 return MCDisassembler::Fail;
909 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
910 ArrayRef<uint8_t> Bytes,
912 raw_ostream &VStream,
913 raw_ostream &CStream) const {
916 DecodeStatus Result =
917 readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
918 if (Result == MCDisassembler::Fail)
919 return MCDisassembler::Fail;
921 // Calling the auto-generated decoder function.
923 decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
924 if (Result != MCDisassembler::Fail) {
928 // If we fail to decode in Mips64 decoder space we can try in Mips32
930 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
931 if (Result != MCDisassembler::Fail) {
936 return MCDisassembler::Fail;
939 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
942 const void *Decoder) {
944 return MCDisassembler::Fail;
948 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
951 const void *Decoder) {
954 return MCDisassembler::Fail;
956 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
957 Inst.addOperand(MCOperand::CreateReg(Reg));
958 return MCDisassembler::Success;
961 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
964 const void *Decoder) {
966 return MCDisassembler::Fail;
967 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
968 Inst.addOperand(MCOperand::CreateReg(Reg));
969 return MCDisassembler::Success;
972 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
975 const void *Decoder) {
977 return MCDisassembler::Fail;
978 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
979 Inst.addOperand(MCOperand::CreateReg(Reg));
980 return MCDisassembler::Success;
983 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
986 const void *Decoder) {
988 return MCDisassembler::Fail;
989 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
990 Inst.addOperand(MCOperand::CreateReg(Reg));
991 return MCDisassembler::Success;
994 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
997 const void *Decoder) {
998 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit())
999 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1001 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1004 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1007 const void *Decoder) {
1008 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1011 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1014 const void *Decoder) {
1016 return MCDisassembler::Fail;
1018 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1019 Inst.addOperand(MCOperand::CreateReg(Reg));
1020 return MCDisassembler::Success;
1023 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1026 const void *Decoder) {
1028 return MCDisassembler::Fail;
1030 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1031 Inst.addOperand(MCOperand::CreateReg(Reg));
1032 return MCDisassembler::Success;
1035 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1038 const void *Decoder) {
1040 return MCDisassembler::Fail;
1041 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1042 Inst.addOperand(MCOperand::CreateReg(Reg));
1043 return MCDisassembler::Success;
1046 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1049 const void *Decoder) {
1051 return MCDisassembler::Fail;
1052 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1053 Inst.addOperand(MCOperand::CreateReg(Reg));
1054 return MCDisassembler::Success;
1057 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1059 const void *Decoder) {
1061 return MCDisassembler::Fail;
1063 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1064 Inst.addOperand(MCOperand::CreateReg(Reg));
1065 return MCDisassembler::Success;
1068 static DecodeStatus DecodeMem(MCInst &Inst,
1071 const void *Decoder) {
1072 int Offset = SignExtend32<16>(Insn & 0xffff);
1073 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1074 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1076 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1077 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1079 if(Inst.getOpcode() == Mips::SC ||
1080 Inst.getOpcode() == Mips::SCD){
1081 Inst.addOperand(MCOperand::CreateReg(Reg));
1084 Inst.addOperand(MCOperand::CreateReg(Reg));
1085 Inst.addOperand(MCOperand::CreateReg(Base));
1086 Inst.addOperand(MCOperand::CreateImm(Offset));
1088 return MCDisassembler::Success;
1091 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1094 const void *Decoder) {
1095 int Offset = SignExtend32<16>(Insn & 0xffff);
1096 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1097 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1099 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1101 Inst.addOperand(MCOperand::CreateReg(Base));
1102 Inst.addOperand(MCOperand::CreateImm(Offset));
1103 Inst.addOperand(MCOperand::CreateImm(Hint));
1105 return MCDisassembler::Success;
1108 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1111 const void *Decoder) {
1112 int Offset = SignExtend32<12>(Insn & 0xfff);
1113 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1114 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1116 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1118 Inst.addOperand(MCOperand::CreateReg(Base));
1119 Inst.addOperand(MCOperand::CreateImm(Offset));
1120 Inst.addOperand(MCOperand::CreateImm(Hint));
1122 return MCDisassembler::Success;
1125 static DecodeStatus DecodeSyncI(MCInst &Inst,
1128 const void *Decoder) {
1129 int Offset = SignExtend32<16>(Insn & 0xffff);
1130 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1132 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1134 Inst.addOperand(MCOperand::CreateReg(Base));
1135 Inst.addOperand(MCOperand::CreateImm(Offset));
1137 return MCDisassembler::Success;
1140 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1141 uint64_t Address, const void *Decoder) {
1142 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1143 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1144 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1146 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1147 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1149 Inst.addOperand(MCOperand::CreateReg(Reg));
1150 Inst.addOperand(MCOperand::CreateReg(Base));
1152 // The immediate field of an LD/ST instruction is scaled which means it must
1153 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1159 switch(Inst.getOpcode())
1162 assert (0 && "Unexpected instruction");
1163 return MCDisassembler::Fail;
1167 Inst.addOperand(MCOperand::CreateImm(Offset));
1171 Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1175 Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1179 Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1183 return MCDisassembler::Success;
1186 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1189 const void *Decoder) {
1190 unsigned Offset = Insn & 0xf;
1191 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1192 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1194 switch (Inst.getOpcode()) {
1195 case Mips::LBU16_MM:
1196 case Mips::LHU16_MM:
1198 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1199 == MCDisassembler::Fail)
1200 return MCDisassembler::Fail;
1205 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1206 == MCDisassembler::Fail)
1207 return MCDisassembler::Fail;
1211 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1212 == MCDisassembler::Fail)
1213 return MCDisassembler::Fail;
1215 switch (Inst.getOpcode()) {
1216 case Mips::LBU16_MM:
1218 Inst.addOperand(MCOperand::CreateImm(-1));
1220 Inst.addOperand(MCOperand::CreateImm(Offset));
1223 Inst.addOperand(MCOperand::CreateImm(Offset));
1225 case Mips::LHU16_MM:
1227 Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1231 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1235 return MCDisassembler::Success;
1238 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1241 const void *Decoder) {
1242 unsigned Offset = Insn & 0x1F;
1243 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1245 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1247 Inst.addOperand(MCOperand::CreateReg(Reg));
1248 Inst.addOperand(MCOperand::CreateReg(Mips::SP));
1249 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1251 return MCDisassembler::Success;
1254 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1257 const void *Decoder) {
1258 int Offset = SignExtend32<12>(Insn & 0x0fff);
1259 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1260 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1262 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1263 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1265 switch (Inst.getOpcode()) {
1266 case Mips::SWM32_MM:
1267 case Mips::LWM32_MM:
1268 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1269 == MCDisassembler::Fail)
1270 return MCDisassembler::Fail;
1271 Inst.addOperand(MCOperand::CreateReg(Base));
1272 Inst.addOperand(MCOperand::CreateImm(Offset));
1275 Inst.addOperand(MCOperand::CreateReg(Reg));
1278 Inst.addOperand(MCOperand::CreateReg(Reg));
1279 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1280 Inst.addOperand(MCOperand::CreateReg(Reg+1));
1282 Inst.addOperand(MCOperand::CreateReg(Base));
1283 Inst.addOperand(MCOperand::CreateImm(Offset));
1286 return MCDisassembler::Success;
1289 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1292 const void *Decoder) {
1293 int Offset = SignExtend32<16>(Insn & 0xffff);
1294 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1295 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1297 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1298 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1300 Inst.addOperand(MCOperand::CreateReg(Reg));
1301 Inst.addOperand(MCOperand::CreateReg(Base));
1302 Inst.addOperand(MCOperand::CreateImm(Offset));
1304 return MCDisassembler::Success;
1307 static DecodeStatus DecodeFMem(MCInst &Inst,
1310 const void *Decoder) {
1311 int Offset = SignExtend32<16>(Insn & 0xffff);
1312 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1313 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1315 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1316 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1318 Inst.addOperand(MCOperand::CreateReg(Reg));
1319 Inst.addOperand(MCOperand::CreateReg(Base));
1320 Inst.addOperand(MCOperand::CreateImm(Offset));
1322 return MCDisassembler::Success;
1325 static DecodeStatus DecodeFMem2(MCInst &Inst,
1328 const void *Decoder) {
1329 int Offset = SignExtend32<16>(Insn & 0xffff);
1330 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1331 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1333 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1334 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1336 Inst.addOperand(MCOperand::CreateReg(Reg));
1337 Inst.addOperand(MCOperand::CreateReg(Base));
1338 Inst.addOperand(MCOperand::CreateImm(Offset));
1340 return MCDisassembler::Success;
1343 static DecodeStatus DecodeFMem3(MCInst &Inst,
1346 const void *Decoder) {
1347 int Offset = SignExtend32<16>(Insn & 0xffff);
1348 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1349 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1351 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1352 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1354 Inst.addOperand(MCOperand::CreateReg(Reg));
1355 Inst.addOperand(MCOperand::CreateReg(Base));
1356 Inst.addOperand(MCOperand::CreateImm(Offset));
1358 return MCDisassembler::Success;
1361 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1364 const void *Decoder) {
1365 int Offset = SignExtend32<11>(Insn & 0x07ff);
1366 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1367 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1369 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1370 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1372 Inst.addOperand(MCOperand::CreateReg(Reg));
1373 Inst.addOperand(MCOperand::CreateReg(Base));
1374 Inst.addOperand(MCOperand::CreateImm(Offset));
1376 return MCDisassembler::Success;
1378 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1381 const void *Decoder) {
1382 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1383 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1384 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1386 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1387 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1389 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1390 Inst.addOperand(MCOperand::CreateReg(Rt));
1393 Inst.addOperand(MCOperand::CreateReg(Rt));
1394 Inst.addOperand(MCOperand::CreateReg(Base));
1395 Inst.addOperand(MCOperand::CreateImm(Offset));
1397 return MCDisassembler::Success;
1400 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1403 const void *Decoder) {
1404 // Currently only hardware register 29 is supported.
1406 return MCDisassembler::Fail;
1407 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1408 return MCDisassembler::Success;
1411 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1414 const void *Decoder) {
1415 if (RegNo > 30 || RegNo %2)
1416 return MCDisassembler::Fail;
1419 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1420 Inst.addOperand(MCOperand::CreateReg(Reg));
1421 return MCDisassembler::Success;
1424 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1427 const void *Decoder) {
1429 return MCDisassembler::Fail;
1431 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1432 Inst.addOperand(MCOperand::CreateReg(Reg));
1433 return MCDisassembler::Success;
1436 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1439 const void *Decoder) {
1441 return MCDisassembler::Fail;
1443 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1444 Inst.addOperand(MCOperand::CreateReg(Reg));
1445 return MCDisassembler::Success;
1448 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1451 const void *Decoder) {
1453 return MCDisassembler::Fail;
1455 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1456 Inst.addOperand(MCOperand::CreateReg(Reg));
1457 return MCDisassembler::Success;
1460 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1463 const void *Decoder) {
1465 return MCDisassembler::Fail;
1467 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1468 Inst.addOperand(MCOperand::CreateReg(Reg));
1469 return MCDisassembler::Success;
1472 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1475 const void *Decoder) {
1477 return MCDisassembler::Fail;
1479 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1480 Inst.addOperand(MCOperand::CreateReg(Reg));
1481 return MCDisassembler::Success;
1484 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1487 const void *Decoder) {
1489 return MCDisassembler::Fail;
1491 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1492 Inst.addOperand(MCOperand::CreateReg(Reg));
1493 return MCDisassembler::Success;
1496 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1499 const void *Decoder) {
1501 return MCDisassembler::Fail;
1503 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1504 Inst.addOperand(MCOperand::CreateReg(Reg));
1505 return MCDisassembler::Success;
1508 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1511 const void *Decoder) {
1513 return MCDisassembler::Fail;
1515 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1516 Inst.addOperand(MCOperand::CreateReg(Reg));
1517 return MCDisassembler::Success;
1520 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1523 const void *Decoder) {
1525 return MCDisassembler::Fail;
1527 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1528 Inst.addOperand(MCOperand::CreateReg(Reg));
1529 return MCDisassembler::Success;
1532 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1535 const void *Decoder) {
1536 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1537 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1538 return MCDisassembler::Success;
1541 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1544 const void *Decoder) {
1546 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1547 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1548 return MCDisassembler::Success;
1551 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1554 const void *Decoder) {
1555 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1557 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1558 return MCDisassembler::Success;
1561 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1564 const void *Decoder) {
1565 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1567 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1568 return MCDisassembler::Success;
1571 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1574 const void *Decoder) {
1575 int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1576 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1577 return MCDisassembler::Success;
1580 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1583 const void *Decoder) {
1584 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1585 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1586 return MCDisassembler::Success;
1589 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1592 const void *Decoder) {
1593 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1594 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1595 return MCDisassembler::Success;
1598 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1601 const void *Decoder) {
1603 Inst.addOperand(MCOperand::CreateImm(1));
1604 else if (Value == 0x7)
1605 Inst.addOperand(MCOperand::CreateImm(-1));
1607 Inst.addOperand(MCOperand::CreateImm(Value << 2));
1608 return MCDisassembler::Success;
1611 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1614 const void *Decoder) {
1615 Inst.addOperand(MCOperand::CreateImm(Value << 2));
1616 return MCDisassembler::Success;
1619 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1622 const void *Decoder) {
1624 Inst.addOperand(MCOperand::CreateImm(-1));
1626 Inst.addOperand(MCOperand::CreateImm(Value));
1627 return MCDisassembler::Success;
1630 static DecodeStatus DecodeSimm4(MCInst &Inst,
1633 const void *Decoder) {
1634 Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
1635 return MCDisassembler::Success;
1638 static DecodeStatus DecodeSimm16(MCInst &Inst,
1641 const void *Decoder) {
1642 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1643 return MCDisassembler::Success;
1646 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1649 const void *Decoder) {
1650 // We add one to the immediate field as it was encoded as 'imm - 1'.
1651 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1652 return MCDisassembler::Success;
1655 static DecodeStatus DecodeInsSize(MCInst &Inst,
1658 const void *Decoder) {
1659 // First we need to grab the pos(lsb) from MCInst.
1660 int Pos = Inst.getOperand(2).getImm();
1661 int Size = (int) Insn - Pos + 1;
1662 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1663 return MCDisassembler::Success;
1666 static DecodeStatus DecodeExtSize(MCInst &Inst,
1669 const void *Decoder) {
1670 int Size = (int) Insn + 1;
1671 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1672 return MCDisassembler::Success;
1675 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1676 uint64_t Address, const void *Decoder) {
1677 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1678 return MCDisassembler::Success;
1681 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1682 uint64_t Address, const void *Decoder) {
1683 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1684 return MCDisassembler::Success;
1687 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1688 uint64_t Address, const void *Decoder) {
1689 int32_t DecodedValue;
1691 case 0: DecodedValue = 256; break;
1692 case 1: DecodedValue = 257; break;
1693 case 510: DecodedValue = -258; break;
1694 case 511: DecodedValue = -257; break;
1695 default: DecodedValue = SignExtend32<9>(Insn); break;
1697 Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4));
1698 return MCDisassembler::Success;
1701 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1702 uint64_t Address, const void *Decoder) {
1703 // Insn must be >= 0, since it is unsigned that condition is always true.
1705 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1707 Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
1708 return MCDisassembler::Success;
1711 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1712 uint64_t Address, const void *Decoder) {
1713 Inst.addOperand(MCOperand::CreateImm(Insn << 2));
1714 return MCDisassembler::Success;
1717 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1720 const void *Decoder) {
1721 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1722 Mips::S6, Mips::FP};
1725 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1726 // Empty register lists are not allowed.
1728 return MCDisassembler::Fail;
1730 RegNum = RegLst & 0xf;
1731 for (unsigned i = 0; i < RegNum; i++)
1732 Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1735 Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1737 return MCDisassembler::Success;
1740 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1742 const void *Decoder) {
1743 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1746 unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1747 // Empty register lists are not allowed.
1749 return MCDisassembler::Fail;
1751 RegNum = RegLst & 0x3;
1752 for (unsigned i = 0; i < RegNum - 1; i++)
1753 Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1755 Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1757 return MCDisassembler::Success;