1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
27 #define DEBUG_TYPE "mips-disassembler"
29 typedef MCDisassembler::DecodeStatus DecodeStatus;
33 class MipsDisassembler : public MCDisassembler {
37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
38 : MCDisassembler(STI, Ctx),
39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
40 IsBigEndian(IsBigEndian) {}
42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
44 bool hasMips32r6() const {
45 return STI.getFeatureBits()[Mips::FeatureMips32r6];
48 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
50 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
52 bool hasCOP3() const {
53 // Only present in MIPS-I and MIPS-II
54 return !hasMips32() && !hasMips3();
57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
58 ArrayRef<uint8_t> Bytes, uint64_t Address,
60 raw_ostream &CStream) const override;
63 } // end anonymous namespace
65 // Forward declare these because the autogenerated code will reference them.
66 // Definitions are further down.
67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
100 const void *Decoder);
102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
105 const void *Decoder);
107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
110 const void *Decoder);
112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
115 const void *Decoder);
117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
120 const void *Decoder);
122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
125 const void *Decoder);
127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
129 const void *Decoder);
131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
134 const void *Decoder);
136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
139 const void *Decoder);
141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
144 const void *Decoder);
146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
149 const void *Decoder);
151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
154 const void *Decoder);
156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
159 const void *Decoder);
161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
164 const void *Decoder);
166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
169 const void *Decoder);
171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
174 const void *Decoder);
176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
179 const void *Decoder);
181 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
184 const void *Decoder);
186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
189 const void *Decoder);
191 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
194 const void *Decoder);
196 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
199 const void *Decoder);
201 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
204 const void *Decoder);
206 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
209 const void *Decoder);
211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
212 // shifted left by 1 bit.
213 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
216 const void *Decoder);
218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
219 // shifted left by 1 bit.
220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
223 const void *Decoder);
225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
226 // shifted left by 1 bit.
227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
230 const void *Decoder);
232 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
233 // shifted left by 1 bit.
234 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
237 const void *Decoder);
239 static DecodeStatus DecodeMem(MCInst &Inst,
242 const void *Decoder);
244 static DecodeStatus DecodeCacheOp(MCInst &Inst,
247 const void *Decoder);
249 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
252 const void *Decoder);
254 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
257 const void *Decoder);
259 static DecodeStatus DecodeSyncI(MCInst &Inst,
262 const void *Decoder);
264 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
265 uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
270 const void *Decoder);
272 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
275 const void *Decoder);
277 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
280 const void *Decoder);
282 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
285 const void *Decoder);
287 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
290 const void *Decoder);
292 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
295 const void *Decoder);
297 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
300 const void *Decoder);
302 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
304 const void *Decoder);
306 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
308 const void *Decoder);
310 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
312 const void *Decoder);
314 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
316 const void *Decoder);
318 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
321 const void *Decoder);
323 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
326 const void *Decoder);
328 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
331 const void *Decoder);
333 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
336 const void *Decoder);
338 static DecodeStatus DecodeSimm4(MCInst &Inst,
341 const void *Decoder);
343 static DecodeStatus DecodeSimm16(MCInst &Inst,
346 const void *Decoder);
348 // Decode the immediate field of an LSA instruction which
350 static DecodeStatus DecodeLSAImm(MCInst &Inst,
353 const void *Decoder);
355 static DecodeStatus DecodeInsSize(MCInst &Inst,
358 const void *Decoder);
360 static DecodeStatus DecodeExtSize(MCInst &Inst,
363 const void *Decoder);
365 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
366 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
369 uint64_t Address, const void *Decoder);
371 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
372 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
375 uint64_t Address, const void *Decoder);
377 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
378 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
381 uint64_t Address, const void *Decoder);
383 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
385 template <typename InsnType>
386 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
387 const void *Decoder);
389 template <typename InsnType>
391 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
392 const void *Decoder);
394 template <typename InsnType>
396 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
397 const void *Decoder);
399 template <typename InsnType>
401 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
402 const void *Decoder);
404 template <typename InsnType>
406 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
407 const void *Decoder);
409 template <typename InsnType>
411 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
412 const void *Decoder);
414 template <typename InsnType>
416 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
417 const void *Decoder);
419 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
421 const void *Decoder);
423 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
425 const void *Decoder);
427 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
429 const void *Decoder);
432 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
436 static MCDisassembler *createMipsDisassembler(
438 const MCSubtargetInfo &STI,
440 return new MipsDisassembler(STI, Ctx, true);
443 static MCDisassembler *createMipselDisassembler(
445 const MCSubtargetInfo &STI,
447 return new MipsDisassembler(STI, Ctx, false);
450 extern "C" void LLVMInitializeMipsDisassembler() {
451 // Register the disassembler.
452 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
453 createMipsDisassembler);
454 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
455 createMipselDisassembler);
456 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
457 createMipsDisassembler);
458 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
459 createMipselDisassembler);
462 #include "MipsGenDisassemblerTables.inc"
464 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
465 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
466 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
467 return *(RegInfo->getRegClass(RC).begin() + RegNo);
470 template <typename InsnType>
471 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
472 const void *Decoder) {
473 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
474 // The size of the n field depends on the element size
475 // The register class also depends on this.
476 InsnType tmp = fieldFromInstruction(insn, 17, 5);
478 DecodeFN RegDecoder = nullptr;
479 if ((tmp & 0x18) == 0x00) { // INSVE_B
481 RegDecoder = DecodeMSA128BRegisterClass;
482 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
484 RegDecoder = DecodeMSA128HRegisterClass;
485 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
487 RegDecoder = DecodeMSA128WRegisterClass;
488 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
490 RegDecoder = DecodeMSA128DRegisterClass;
492 llvm_unreachable("Invalid encoding");
494 assert(NSize != 0 && RegDecoder != nullptr);
497 tmp = fieldFromInstruction(insn, 6, 5);
498 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
499 return MCDisassembler::Fail;
501 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
502 return MCDisassembler::Fail;
504 tmp = fieldFromInstruction(insn, 16, NSize);
505 MI.addOperand(MCOperand::createImm(tmp));
507 tmp = fieldFromInstruction(insn, 11, 5);
508 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
509 return MCDisassembler::Fail;
511 MI.addOperand(MCOperand::createImm(0));
513 return MCDisassembler::Success;
516 template <typename InsnType>
517 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
519 const void *Decoder) {
520 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
521 // (otherwise we would have matched the ADDI instruction from the earlier
525 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
527 // BEQZALC if rs == 0 && rt != 0
528 // BEQC if rs < rt && rs != 0
530 InsnType Rs = fieldFromInstruction(insn, 21, 5);
531 InsnType Rt = fieldFromInstruction(insn, 16, 5);
532 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
536 MI.setOpcode(Mips::BOVC);
538 } else if (Rs != 0 && Rs < Rt) {
539 MI.setOpcode(Mips::BEQC);
542 MI.setOpcode(Mips::BEQZALC);
545 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
548 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
550 MI.addOperand(MCOperand::createImm(Imm));
552 return MCDisassembler::Success;
555 template <typename InsnType>
556 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
558 const void *Decoder) {
559 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
560 // (otherwise we would have matched the ADDI instruction from the earlier
564 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
566 // BNEZALC if rs == 0 && rt != 0
567 // BNEC if rs < rt && rs != 0
569 InsnType Rs = fieldFromInstruction(insn, 21, 5);
570 InsnType Rt = fieldFromInstruction(insn, 16, 5);
571 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
575 MI.setOpcode(Mips::BNVC);
577 } else if (Rs != 0 && Rs < Rt) {
578 MI.setOpcode(Mips::BNEC);
581 MI.setOpcode(Mips::BNEZALC);
584 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
587 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
589 MI.addOperand(MCOperand::createImm(Imm));
591 return MCDisassembler::Success;
594 template <typename InsnType>
595 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
597 const void *Decoder) {
598 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
599 // (otherwise we would have matched the BLEZL instruction from the earlier
603 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
604 // Invalid if rs == 0
605 // BLEZC if rs == 0 && rt != 0
606 // BGEZC if rs == rt && rt != 0
607 // BGEC if rs != rt && rs != 0 && rt != 0
609 InsnType Rs = fieldFromInstruction(insn, 21, 5);
610 InsnType Rt = fieldFromInstruction(insn, 16, 5);
611 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
615 return MCDisassembler::Fail;
617 MI.setOpcode(Mips::BLEZC);
619 MI.setOpcode(Mips::BGEZC);
622 MI.setOpcode(Mips::BGEC);
626 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
629 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
632 MI.addOperand(MCOperand::createImm(Imm));
634 return MCDisassembler::Success;
637 template <typename InsnType>
638 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
640 const void *Decoder) {
641 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
642 // (otherwise we would have matched the BGTZL instruction from the earlier
646 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
647 // Invalid if rs == 0
648 // BGTZC if rs == 0 && rt != 0
649 // BLTZC if rs == rt && rt != 0
650 // BLTC if rs != rt && rs != 0 && rt != 0
654 InsnType Rs = fieldFromInstruction(insn, 21, 5);
655 InsnType Rt = fieldFromInstruction(insn, 16, 5);
656 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
659 return MCDisassembler::Fail;
661 MI.setOpcode(Mips::BGTZC);
663 MI.setOpcode(Mips::BLTZC);
665 MI.setOpcode(Mips::BLTC);
670 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
673 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
676 MI.addOperand(MCOperand::createImm(Imm));
678 return MCDisassembler::Success;
681 template <typename InsnType>
682 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
684 const void *Decoder) {
685 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
686 // (otherwise we would have matched the BGTZ instruction from the earlier
690 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
692 // BGTZALC if rs == 0 && rt != 0
693 // BLTZALC if rs != 0 && rs == rt
694 // BLTUC if rs != 0 && rs != rt
696 InsnType Rs = fieldFromInstruction(insn, 21, 5);
697 InsnType Rt = fieldFromInstruction(insn, 16, 5);
698 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
703 MI.setOpcode(Mips::BGTZ);
705 } else if (Rs == 0) {
706 MI.setOpcode(Mips::BGTZALC);
708 } else if (Rs == Rt) {
709 MI.setOpcode(Mips::BLTZALC);
712 MI.setOpcode(Mips::BLTUC);
718 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
722 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
725 MI.addOperand(MCOperand::createImm(Imm));
727 return MCDisassembler::Success;
730 template <typename InsnType>
731 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
733 const void *Decoder) {
734 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
735 // (otherwise we would have matched the BLEZL instruction from the earlier
739 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
740 // Invalid if rs == 0
741 // BLEZALC if rs == 0 && rt != 0
742 // BGEZALC if rs == rt && rt != 0
743 // BGEUC if rs != rt && rs != 0 && rt != 0
745 InsnType Rs = fieldFromInstruction(insn, 21, 5);
746 InsnType Rt = fieldFromInstruction(insn, 16, 5);
747 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
751 return MCDisassembler::Fail;
753 MI.setOpcode(Mips::BLEZALC);
755 MI.setOpcode(Mips::BGEZALC);
758 MI.setOpcode(Mips::BGEUC);
762 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
764 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
767 MI.addOperand(MCOperand::createImm(Imm));
769 return MCDisassembler::Success;
772 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
773 /// according to the given endianess.
774 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
775 uint64_t &Size, uint32_t &Insn,
777 // We want to read exactly 2 Bytes of data.
778 if (Bytes.size() < 2) {
780 return MCDisassembler::Fail;
784 Insn = (Bytes[0] << 8) | Bytes[1];
786 Insn = (Bytes[1] << 8) | Bytes[0];
789 return MCDisassembler::Success;
792 /// Read four bytes from the ArrayRef and return 32 bit word sorted
793 /// according to the given endianess
794 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
795 uint64_t &Size, uint32_t &Insn,
796 bool IsBigEndian, bool IsMicroMips) {
797 // We want to read exactly 4 Bytes of data.
798 if (Bytes.size() < 4) {
800 return MCDisassembler::Fail;
803 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
804 // always precede the low 16 bits in the instruction stream (that is, they
805 // are placed at lower addresses in the instruction stream).
807 // microMIPS byte ordering:
808 // Big-endian: 0 | 1 | 2 | 3
809 // Little-endian: 1 | 0 | 3 | 2
812 // Encoded as a big-endian 32-bit word in the stream.
814 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
817 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
820 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
825 return MCDisassembler::Success;
828 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
829 ArrayRef<uint8_t> Bytes,
831 raw_ostream &VStream,
832 raw_ostream &CStream) const {
837 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
840 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
841 // Calling the auto-generated decoder function for microMIPS32R6
842 // (and microMIPS64R6) 16-bit instructions.
843 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
845 if (Result != MCDisassembler::Fail) {
851 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
852 // Calling the auto-generated decoder function for microMIPS 16-bit
854 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
856 if (Result != MCDisassembler::Fail) {
861 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
862 if (Result == MCDisassembler::Fail)
863 return MCDisassembler::Fail;
866 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
867 // Calling the auto-generated decoder function.
868 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
870 if (Result != MCDisassembler::Fail) {
876 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
877 // Calling the auto-generated decoder function.
878 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
880 if (Result != MCDisassembler::Fail) {
884 return MCDisassembler::Fail;
887 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
888 if (Result == MCDisassembler::Fail)
889 return MCDisassembler::Fail;
892 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
894 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
895 if (Result != MCDisassembler::Fail) {
901 if (hasMips32r6() && isGP64()) {
902 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
903 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
905 if (Result != MCDisassembler::Fail) {
912 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
913 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
915 if (Result != MCDisassembler::Fail) {
922 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
923 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
925 if (Result != MCDisassembler::Fail) {
932 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
933 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
935 if (Result != MCDisassembler::Fail) {
941 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
942 // Calling the auto-generated decoder function.
944 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
945 if (Result != MCDisassembler::Fail) {
950 return MCDisassembler::Fail;
953 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
956 const void *Decoder) {
958 return MCDisassembler::Fail;
962 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
965 const void *Decoder) {
968 return MCDisassembler::Fail;
970 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
971 Inst.addOperand(MCOperand::createReg(Reg));
972 return MCDisassembler::Success;
975 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
978 const void *Decoder) {
980 return MCDisassembler::Fail;
981 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
982 Inst.addOperand(MCOperand::createReg(Reg));
983 return MCDisassembler::Success;
986 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
989 const void *Decoder) {
991 return MCDisassembler::Fail;
992 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
993 Inst.addOperand(MCOperand::createReg(Reg));
994 return MCDisassembler::Success;
997 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
1000 const void *Decoder) {
1002 return MCDisassembler::Fail;
1003 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1004 Inst.addOperand(MCOperand::createReg(Reg));
1005 return MCDisassembler::Success;
1008 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1011 const void *Decoder) {
1013 return MCDisassembler::Fail;
1014 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1015 Inst.addOperand(MCOperand::createReg(Reg));
1016 return MCDisassembler::Success;
1019 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1022 const void *Decoder) {
1023 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1024 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1026 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1029 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1032 const void *Decoder) {
1033 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1036 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1039 const void *Decoder) {
1041 return MCDisassembler::Fail;
1043 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1044 Inst.addOperand(MCOperand::createReg(Reg));
1045 return MCDisassembler::Success;
1048 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1051 const void *Decoder) {
1053 return MCDisassembler::Fail;
1055 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1056 Inst.addOperand(MCOperand::createReg(Reg));
1057 return MCDisassembler::Success;
1060 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1063 const void *Decoder) {
1065 return MCDisassembler::Fail;
1066 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1067 Inst.addOperand(MCOperand::createReg(Reg));
1068 return MCDisassembler::Success;
1071 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1074 const void *Decoder) {
1076 return MCDisassembler::Fail;
1077 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1078 Inst.addOperand(MCOperand::createReg(Reg));
1079 return MCDisassembler::Success;
1082 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1084 const void *Decoder) {
1086 return MCDisassembler::Fail;
1088 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1089 Inst.addOperand(MCOperand::createReg(Reg));
1090 return MCDisassembler::Success;
1093 static DecodeStatus DecodeMem(MCInst &Inst,
1096 const void *Decoder) {
1097 int Offset = SignExtend32<16>(Insn & 0xffff);
1098 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1099 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1101 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1102 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1104 if(Inst.getOpcode() == Mips::SC ||
1105 Inst.getOpcode() == Mips::SCD){
1106 Inst.addOperand(MCOperand::createReg(Reg));
1109 Inst.addOperand(MCOperand::createReg(Reg));
1110 Inst.addOperand(MCOperand::createReg(Base));
1111 Inst.addOperand(MCOperand::createImm(Offset));
1113 return MCDisassembler::Success;
1116 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1119 const void *Decoder) {
1120 int Offset = SignExtend32<16>(Insn & 0xffff);
1121 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1122 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1124 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1126 Inst.addOperand(MCOperand::createReg(Base));
1127 Inst.addOperand(MCOperand::createImm(Offset));
1128 Inst.addOperand(MCOperand::createImm(Hint));
1130 return MCDisassembler::Success;
1133 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1136 const void *Decoder) {
1137 int Offset = SignExtend32<12>(Insn & 0xfff);
1138 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1139 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1141 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1143 Inst.addOperand(MCOperand::createReg(Base));
1144 Inst.addOperand(MCOperand::createImm(Offset));
1145 Inst.addOperand(MCOperand::createImm(Hint));
1147 return MCDisassembler::Success;
1150 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
1153 const void *Decoder) {
1154 int Offset = fieldFromInstruction(Insn, 7, 9);
1155 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1156 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1158 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1160 Inst.addOperand(MCOperand::createReg(Base));
1161 Inst.addOperand(MCOperand::createImm(Offset));
1162 Inst.addOperand(MCOperand::createImm(Hint));
1164 return MCDisassembler::Success;
1167 static DecodeStatus DecodeSyncI(MCInst &Inst,
1170 const void *Decoder) {
1171 int Offset = SignExtend32<16>(Insn & 0xffff);
1172 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1174 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1176 Inst.addOperand(MCOperand::createReg(Base));
1177 Inst.addOperand(MCOperand::createImm(Offset));
1179 return MCDisassembler::Success;
1182 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1183 uint64_t Address, const void *Decoder) {
1184 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1185 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1186 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1188 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1189 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1191 Inst.addOperand(MCOperand::createReg(Reg));
1192 Inst.addOperand(MCOperand::createReg(Base));
1194 // The immediate field of an LD/ST instruction is scaled which means it must
1195 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1201 switch(Inst.getOpcode())
1204 assert (0 && "Unexpected instruction");
1205 return MCDisassembler::Fail;
1209 Inst.addOperand(MCOperand::createImm(Offset));
1213 Inst.addOperand(MCOperand::createImm(Offset * 2));
1217 Inst.addOperand(MCOperand::createImm(Offset * 4));
1221 Inst.addOperand(MCOperand::createImm(Offset * 8));
1225 return MCDisassembler::Success;
1228 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1231 const void *Decoder) {
1232 unsigned Offset = Insn & 0xf;
1233 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1234 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1236 switch (Inst.getOpcode()) {
1237 case Mips::LBU16_MM:
1238 case Mips::LHU16_MM:
1240 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1241 == MCDisassembler::Fail)
1242 return MCDisassembler::Fail;
1247 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1248 == MCDisassembler::Fail)
1249 return MCDisassembler::Fail;
1253 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1254 == MCDisassembler::Fail)
1255 return MCDisassembler::Fail;
1257 switch (Inst.getOpcode()) {
1258 case Mips::LBU16_MM:
1260 Inst.addOperand(MCOperand::createImm(-1));
1262 Inst.addOperand(MCOperand::createImm(Offset));
1265 Inst.addOperand(MCOperand::createImm(Offset));
1267 case Mips::LHU16_MM:
1269 Inst.addOperand(MCOperand::createImm(Offset << 1));
1273 Inst.addOperand(MCOperand::createImm(Offset << 2));
1277 return MCDisassembler::Success;
1280 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1283 const void *Decoder) {
1284 unsigned Offset = Insn & 0x1F;
1285 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1287 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1289 Inst.addOperand(MCOperand::createReg(Reg));
1290 Inst.addOperand(MCOperand::createReg(Mips::SP));
1291 Inst.addOperand(MCOperand::createImm(Offset << 2));
1293 return MCDisassembler::Success;
1296 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1299 const void *Decoder) {
1300 unsigned Offset = Insn & 0x7F;
1301 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1303 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1305 Inst.addOperand(MCOperand::createReg(Reg));
1306 Inst.addOperand(MCOperand::createReg(Mips::GP));
1307 Inst.addOperand(MCOperand::createImm(Offset << 2));
1309 return MCDisassembler::Success;
1312 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1315 const void *Decoder) {
1316 int Offset = SignExtend32<4>(Insn & 0xf);
1318 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1319 == MCDisassembler::Fail)
1320 return MCDisassembler::Fail;
1322 Inst.addOperand(MCOperand::createReg(Mips::SP));
1323 Inst.addOperand(MCOperand::createImm(Offset << 2));
1325 return MCDisassembler::Success;
1328 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
1331 const void *Decoder) {
1332 int Offset = SignExtend32<9>(Insn & 0x1ff);
1333 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1334 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1336 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1337 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1339 Inst.addOperand(MCOperand::createReg(Reg));
1340 Inst.addOperand(MCOperand::createReg(Base));
1341 Inst.addOperand(MCOperand::createImm(Offset));
1343 return MCDisassembler::Success;
1346 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1349 const void *Decoder) {
1350 int Offset = SignExtend32<12>(Insn & 0x0fff);
1351 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1352 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1354 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1355 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1357 switch (Inst.getOpcode()) {
1358 case Mips::SWM32_MM:
1359 case Mips::LWM32_MM:
1360 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1361 == MCDisassembler::Fail)
1362 return MCDisassembler::Fail;
1363 Inst.addOperand(MCOperand::createReg(Base));
1364 Inst.addOperand(MCOperand::createImm(Offset));
1367 Inst.addOperand(MCOperand::createReg(Reg));
1370 Inst.addOperand(MCOperand::createReg(Reg));
1371 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1372 Inst.addOperand(MCOperand::createReg(Reg+1));
1374 Inst.addOperand(MCOperand::createReg(Base));
1375 Inst.addOperand(MCOperand::createImm(Offset));
1378 return MCDisassembler::Success;
1381 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1384 const void *Decoder) {
1385 int Offset = SignExtend32<16>(Insn & 0xffff);
1386 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1387 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1389 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1390 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1392 Inst.addOperand(MCOperand::createReg(Reg));
1393 Inst.addOperand(MCOperand::createReg(Base));
1394 Inst.addOperand(MCOperand::createImm(Offset));
1396 return MCDisassembler::Success;
1399 static DecodeStatus DecodeFMem(MCInst &Inst,
1402 const void *Decoder) {
1403 int Offset = SignExtend32<16>(Insn & 0xffff);
1404 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1405 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1407 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1408 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1410 Inst.addOperand(MCOperand::createReg(Reg));
1411 Inst.addOperand(MCOperand::createReg(Base));
1412 Inst.addOperand(MCOperand::createImm(Offset));
1414 return MCDisassembler::Success;
1417 static DecodeStatus DecodeFMem2(MCInst &Inst,
1420 const void *Decoder) {
1421 int Offset = SignExtend32<16>(Insn & 0xffff);
1422 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1423 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1425 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1426 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1428 Inst.addOperand(MCOperand::createReg(Reg));
1429 Inst.addOperand(MCOperand::createReg(Base));
1430 Inst.addOperand(MCOperand::createImm(Offset));
1432 return MCDisassembler::Success;
1435 static DecodeStatus DecodeFMem3(MCInst &Inst,
1438 const void *Decoder) {
1439 int Offset = SignExtend32<16>(Insn & 0xffff);
1440 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1441 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1443 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1444 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1446 Inst.addOperand(MCOperand::createReg(Reg));
1447 Inst.addOperand(MCOperand::createReg(Base));
1448 Inst.addOperand(MCOperand::createImm(Offset));
1450 return MCDisassembler::Success;
1453 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1456 const void *Decoder) {
1457 int Offset = SignExtend32<11>(Insn & 0x07ff);
1458 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1459 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1461 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1462 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1464 Inst.addOperand(MCOperand::createReg(Reg));
1465 Inst.addOperand(MCOperand::createReg(Base));
1466 Inst.addOperand(MCOperand::createImm(Offset));
1468 return MCDisassembler::Success;
1470 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1473 const void *Decoder) {
1474 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1475 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1476 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1478 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1479 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1481 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1482 Inst.addOperand(MCOperand::createReg(Rt));
1485 Inst.addOperand(MCOperand::createReg(Rt));
1486 Inst.addOperand(MCOperand::createReg(Base));
1487 Inst.addOperand(MCOperand::createImm(Offset));
1489 return MCDisassembler::Success;
1492 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1495 const void *Decoder) {
1496 // Currently only hardware register 29 is supported.
1498 return MCDisassembler::Fail;
1499 Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1500 return MCDisassembler::Success;
1503 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1506 const void *Decoder) {
1507 if (RegNo > 30 || RegNo %2)
1508 return MCDisassembler::Fail;
1511 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1512 Inst.addOperand(MCOperand::createReg(Reg));
1513 return MCDisassembler::Success;
1516 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1519 const void *Decoder) {
1521 return MCDisassembler::Fail;
1523 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1524 Inst.addOperand(MCOperand::createReg(Reg));
1525 return MCDisassembler::Success;
1528 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1531 const void *Decoder) {
1533 return MCDisassembler::Fail;
1535 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1536 Inst.addOperand(MCOperand::createReg(Reg));
1537 return MCDisassembler::Success;
1540 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1543 const void *Decoder) {
1545 return MCDisassembler::Fail;
1547 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1548 Inst.addOperand(MCOperand::createReg(Reg));
1549 return MCDisassembler::Success;
1552 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1555 const void *Decoder) {
1557 return MCDisassembler::Fail;
1559 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1560 Inst.addOperand(MCOperand::createReg(Reg));
1561 return MCDisassembler::Success;
1564 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1567 const void *Decoder) {
1569 return MCDisassembler::Fail;
1571 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1572 Inst.addOperand(MCOperand::createReg(Reg));
1573 return MCDisassembler::Success;
1576 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1579 const void *Decoder) {
1581 return MCDisassembler::Fail;
1583 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1584 Inst.addOperand(MCOperand::createReg(Reg));
1585 return MCDisassembler::Success;
1588 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1591 const void *Decoder) {
1593 return MCDisassembler::Fail;
1595 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1596 Inst.addOperand(MCOperand::createReg(Reg));
1597 return MCDisassembler::Success;
1600 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1603 const void *Decoder) {
1605 return MCDisassembler::Fail;
1607 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1608 Inst.addOperand(MCOperand::createReg(Reg));
1609 return MCDisassembler::Success;
1612 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
1615 const void *Decoder) {
1617 return MCDisassembler::Fail;
1619 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
1620 Inst.addOperand(MCOperand::createReg(Reg));
1621 return MCDisassembler::Success;
1624 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1627 const void *Decoder) {
1629 return MCDisassembler::Fail;
1631 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1632 Inst.addOperand(MCOperand::createReg(Reg));
1633 return MCDisassembler::Success;
1636 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1639 const void *Decoder) {
1640 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1641 Inst.addOperand(MCOperand::createImm(BranchOffset));
1642 return MCDisassembler::Success;
1645 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1648 const void *Decoder) {
1650 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1651 Inst.addOperand(MCOperand::createImm(JumpOffset));
1652 return MCDisassembler::Success;
1655 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1658 const void *Decoder) {
1659 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1661 Inst.addOperand(MCOperand::createImm(BranchOffset));
1662 return MCDisassembler::Success;
1665 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1668 const void *Decoder) {
1669 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1671 Inst.addOperand(MCOperand::createImm(BranchOffset));
1672 return MCDisassembler::Success;
1675 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1678 const void *Decoder) {
1679 int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1680 Inst.addOperand(MCOperand::createImm(BranchOffset));
1681 return MCDisassembler::Success;
1684 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1687 const void *Decoder) {
1688 int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1689 Inst.addOperand(MCOperand::createImm(BranchOffset));
1690 return MCDisassembler::Success;
1693 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1696 const void *Decoder) {
1697 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1698 Inst.addOperand(MCOperand::createImm(BranchOffset));
1699 return MCDisassembler::Success;
1702 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1705 const void *Decoder) {
1706 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1707 Inst.addOperand(MCOperand::createImm(JumpOffset));
1708 return MCDisassembler::Success;
1711 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1714 const void *Decoder) {
1716 Inst.addOperand(MCOperand::createImm(1));
1717 else if (Value == 0x7)
1718 Inst.addOperand(MCOperand::createImm(-1));
1720 Inst.addOperand(MCOperand::createImm(Value << 2));
1721 return MCDisassembler::Success;
1724 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1727 const void *Decoder) {
1728 Inst.addOperand(MCOperand::createImm(Value << 2));
1729 return MCDisassembler::Success;
1732 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1735 const void *Decoder) {
1737 Inst.addOperand(MCOperand::createImm(-1));
1739 Inst.addOperand(MCOperand::createImm(Value));
1740 return MCDisassembler::Success;
1743 static DecodeStatus DecodeSimm4(MCInst &Inst,
1746 const void *Decoder) {
1747 Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
1748 return MCDisassembler::Success;
1751 static DecodeStatus DecodeSimm16(MCInst &Inst,
1754 const void *Decoder) {
1755 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
1756 return MCDisassembler::Success;
1759 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1762 const void *Decoder) {
1763 // We add one to the immediate field as it was encoded as 'imm - 1'.
1764 Inst.addOperand(MCOperand::createImm(Insn + 1));
1765 return MCDisassembler::Success;
1768 static DecodeStatus DecodeInsSize(MCInst &Inst,
1771 const void *Decoder) {
1772 // First we need to grab the pos(lsb) from MCInst.
1773 int Pos = Inst.getOperand(2).getImm();
1774 int Size = (int) Insn - Pos + 1;
1775 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1776 return MCDisassembler::Success;
1779 static DecodeStatus DecodeExtSize(MCInst &Inst,
1782 const void *Decoder) {
1783 int Size = (int) Insn + 1;
1784 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1785 return MCDisassembler::Success;
1788 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1789 uint64_t Address, const void *Decoder) {
1790 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1791 return MCDisassembler::Success;
1794 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1795 uint64_t Address, const void *Decoder) {
1796 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1797 return MCDisassembler::Success;
1800 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1801 uint64_t Address, const void *Decoder) {
1802 int32_t DecodedValue;
1804 case 0: DecodedValue = 256; break;
1805 case 1: DecodedValue = 257; break;
1806 case 510: DecodedValue = -258; break;
1807 case 511: DecodedValue = -257; break;
1808 default: DecodedValue = SignExtend32<9>(Insn); break;
1810 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1811 return MCDisassembler::Success;
1814 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1815 uint64_t Address, const void *Decoder) {
1816 // Insn must be >= 0, since it is unsigned that condition is always true.
1818 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1820 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1821 return MCDisassembler::Success;
1824 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1825 uint64_t Address, const void *Decoder) {
1826 Inst.addOperand(MCOperand::createImm(Insn << 2));
1827 return MCDisassembler::Success;
1830 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1833 const void *Decoder) {
1834 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1835 Mips::S6, Mips::FP};
1838 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1839 // Empty register lists are not allowed.
1841 return MCDisassembler::Fail;
1843 RegNum = RegLst & 0xf;
1844 for (unsigned i = 0; i < RegNum; i++)
1845 Inst.addOperand(MCOperand::createReg(Regs[i]));
1848 Inst.addOperand(MCOperand::createReg(Mips::RA));
1850 return MCDisassembler::Success;
1853 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1855 const void *Decoder) {
1856 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1857 unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1858 unsigned RegNum = RegLst & 0x3;
1860 for (unsigned i = 0; i <= RegNum; i++)
1861 Inst.addOperand(MCOperand::createReg(Regs[i]));
1863 Inst.addOperand(MCOperand::createReg(Mips::RA));
1865 return MCDisassembler::Success;
1868 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
1869 uint64_t Address, const void *Decoder) {
1871 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1875 return MCDisassembler::Fail;
1877 Inst.addOperand(MCOperand::createReg(Mips::A1));
1878 Inst.addOperand(MCOperand::createReg(Mips::A2));
1881 Inst.addOperand(MCOperand::createReg(Mips::A1));
1882 Inst.addOperand(MCOperand::createReg(Mips::A3));
1885 Inst.addOperand(MCOperand::createReg(Mips::A2));
1886 Inst.addOperand(MCOperand::createReg(Mips::A3));
1889 Inst.addOperand(MCOperand::createReg(Mips::A0));
1890 Inst.addOperand(MCOperand::createReg(Mips::S5));
1893 Inst.addOperand(MCOperand::createReg(Mips::A0));
1894 Inst.addOperand(MCOperand::createReg(Mips::S6));
1897 Inst.addOperand(MCOperand::createReg(Mips::A0));
1898 Inst.addOperand(MCOperand::createReg(Mips::A1));
1901 Inst.addOperand(MCOperand::createReg(Mips::A0));
1902 Inst.addOperand(MCOperand::createReg(Mips::A2));
1905 Inst.addOperand(MCOperand::createReg(Mips::A0));
1906 Inst.addOperand(MCOperand::createReg(Mips::A3));
1910 return MCDisassembler::Success;
1913 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1914 uint64_t Address, const void *Decoder) {
1915 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
1916 return MCDisassembler::Success;