lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 class MipsDisassembler : public MCDisassembler {
  34   bool IsMicroMips;
  35   bool IsBigEndian;
  36 public:
  37   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
  43   bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
  44   bool hasMips32r6() const {
  45     return STI.getFeatureBits()[Mips::FeatureMips32r6];
  46   }
  47
  48   bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
  49
  50   bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
  51
  52   bool hasCOP3() const {
  53     // Only present in MIPS-I and MIPS-II
  54     return !hasMips32() && !hasMips3();
  55   }
  56
  57   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  58                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  59                               raw_ostream &VStream,
  60                               raw_ostream &CStream) const override;
  61 };
  62
  63 } // end anonymous namespace
  64
  65 // Forward declare these because the autogenerated code will reference them.
  66 // Definitions are further down.
  67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  68                                              unsigned RegNo,
  69                                              uint64_t Address,
  70                                              const void *Decoder);
  71
  72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
  73                                                  unsigned RegNo,
  74                                                  uint64_t Address,
  75                                                  const void *Decoder);
  76
  77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
  78                                                unsigned RegNo,
  79                                                uint64_t Address,
  80                                                const void *Decoder);
  81
  82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
  83                                                    unsigned RegNo,
  84                                                    uint64_t Address,
  85                                                    const void *Decoder);
  86
  87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
  88                                                     unsigned RegNo,
  89                                                     uint64_t Address,
  90                                                     const void *Decoder);
  91
  92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
  93                                              unsigned RegNo,
  94                                              uint64_t Address,
  95                                              const void *Decoder);
  96
  97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
  98                                            unsigned Insn,
  99                                            uint64_t Address,
 100                                            const void *Decoder);
 101
 102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 103                                             unsigned RegNo,
 104                                             uint64_t Address,
 105                                             const void *Decoder);
 106
 107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 108                                              unsigned RegNo,
 109                                              uint64_t Address,
 110                                              const void *Decoder);
 111
 112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 113                                              unsigned RegNo,
 114                                              uint64_t Address,
 115                                              const void *Decoder);
 116
 117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 118                                            unsigned RegNo,
 119                                            uint64_t Address,
 120                                            const void *Decoder);
 121
 122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 123                                            unsigned RegNo,
 124                                            uint64_t Address,
 125                                            const void *Decoder);
 126
 127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 128                                              uint64_t Address,
 129                                              const void *Decoder);
 130
 131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 132                                               unsigned Insn,
 133                                               uint64_t Address,
 134                                               const void *Decoder);
 135
 136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 137                                               unsigned RegNo,
 138                                               uint64_t Address,
 139                                               const void *Decoder);
 140
 141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 142                                                 unsigned RegNo,
 143                                                 uint64_t Address,
 144                                                 const void *Decoder);
 145
 146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 147                                                unsigned RegNo,
 148                                                uint64_t Address,
 149                                                const void *Decoder);
 150
 151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 152                                                unsigned RegNo,
 153                                                uint64_t Address,
 154                                                const void *Decoder);
 155
 156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 157                                                unsigned RegNo,
 158                                                uint64_t Address,
 159                                                const void *Decoder);
 160
 161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 162                                                unsigned RegNo,
 163                                                uint64_t Address,
 164                                                const void *Decoder);
 165
 166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 167                                                unsigned RegNo,
 168                                                uint64_t Address,
 169                                                const void *Decoder);
 170
 171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
 182                                             unsigned RegNo,
 183                                             uint64_t Address,
 184                                             const void *Decoder);
 185
 186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 187                                             unsigned RegNo,
 188                                             uint64_t Address,
 189                                             const void *Decoder);
 190
 191 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 192                                        unsigned Offset,
 193                                        uint64_t Address,
 194                                        const void *Decoder);
 195
 196 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 197                                      unsigned Insn,
 198                                      uint64_t Address,
 199                                      const void *Decoder);
 200
 201 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 202                                          unsigned Offset,
 203                                          uint64_t Address,
 204                                          const void *Decoder);
 205
 206 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 207                                          unsigned Offset,
 208                                          uint64_t Address,
 209                                          const void *Decoder);
 210
 211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 212 // shifted left by 1 bit.
 213 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
 214                                           unsigned Offset,
 215                                           uint64_t Address,
 216                                           const void *Decoder);
 217
 218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
 219 // shifted left by 1 bit.
 220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
 221                                            unsigned Offset,
 222                                            uint64_t Address,
 223                                            const void *Decoder);
 224
 225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 226 // shifted left by 1 bit.
 227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 228                                          unsigned Offset,
 229                                          uint64_t Address,
 230                                          const void *Decoder);
 231
 232 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 233 // shifted left by 1 bit.
 234 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 235                                        unsigned Insn,
 236                                        uint64_t Address,
 237                                        const void *Decoder);
 238
 239 static DecodeStatus DecodeMem(MCInst &Inst,
 240                               unsigned Insn,
 241                               uint64_t Address,
 242                               const void *Decoder);
 243
 244 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 245                               unsigned Insn,
 246                               uint64_t Address,
 247                               const void *Decoder);
 248
 249 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
 250                                     unsigned Insn,
 251                                     uint64_t Address,
 252                                     const void *Decoder);
 253
 254 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
 255                                     unsigned Insn,
 256                                     uint64_t Address,
 257                                     const void *Decoder);
 258
 259 static DecodeStatus DecodeSyncI(MCInst &Inst,
 260                                 unsigned Insn,
 261                                 uint64_t Address,
 262                                 const void *Decoder);
 263
 264 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 265                                     uint64_t Address, const void *Decoder);
 266
 267 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 268                                     unsigned Insn,
 269                                     uint64_t Address,
 270                                     const void *Decoder);
 271
 272 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
 273                                           unsigned Insn,
 274                                           uint64_t Address,
 275                                           const void *Decoder);
 276
 277 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
 278                                           unsigned Insn,
 279                                           uint64_t Address,
 280                                           const void *Decoder);
 281
 282 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
 283                                                unsigned Insn,
 284                                                uint64_t Address,
 285                                                const void *Decoder);
 286
 287 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
 288                                     unsigned Insn,
 289                                     uint64_t Address,
 290                                     const void *Decoder);
 291
 292 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 293                                      unsigned Insn,
 294                                      uint64_t Address,
 295                                      const void *Decoder);
 296
 297 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 298                                      unsigned Insn,
 299                                      uint64_t Address,
 300                                      const void *Decoder);
 301
 302 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 303                                uint64_t Address,
 304                                const void *Decoder);
 305
 306 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 307                                uint64_t Address,
 308                                const void *Decoder);
 309
 310 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 311                                uint64_t Address,
 312                                const void *Decoder);
 313
 314 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
 315                                uint64_t Address,
 316                                const void *Decoder);
 317
 318 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 319                                        unsigned Insn,
 320                                        uint64_t Address,
 321                                        const void *Decoder);
 322
 323 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 324                                        unsigned Value,
 325                                        uint64_t Address,
 326                                        const void *Decoder);
 327
 328 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
 329                                     unsigned Value,
 330                                     uint64_t Address,
 331                                     const void *Decoder);
 332
 333 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
 334                                   unsigned Value,
 335                                   uint64_t Address,
 336                                   const void *Decoder);
 337
 338 static DecodeStatus DecodeSimm4(MCInst &Inst,
 339                                 unsigned Value,
 340                                 uint64_t Address,
 341                                 const void *Decoder);
 342
 343 static DecodeStatus DecodeSimm16(MCInst &Inst,
 344                                  unsigned Insn,
 345                                  uint64_t Address,
 346                                  const void *Decoder);
 347
 348 // Decode the immediate field of an LSA instruction which
 349 // is off by one.
 350 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 351                                  unsigned Insn,
 352                                  uint64_t Address,
 353                                  const void *Decoder);
 354
 355 static DecodeStatus DecodeInsSize(MCInst &Inst,
 356                                   unsigned Insn,
 357                                   uint64_t Address,
 358                                   const void *Decoder);
 359
 360 static DecodeStatus DecodeExtSize(MCInst &Inst,
 361                                   unsigned Insn,
 362                                   uint64_t Address,
 363                                   const void *Decoder);
 364
 365 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 366                                      uint64_t Address, const void *Decoder);
 367
 368 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 369                                      uint64_t Address, const void *Decoder);
 370
 371 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
 372                                   uint64_t Address, const void *Decoder);
 373
 374 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
 375                                     uint64_t Address, const void *Decoder);
 376
 377 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
 378                                    uint64_t Address, const void *Decoder);
 379
 380 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
 381                                      uint64_t Address, const void *Decoder);
 382
 383 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 384 /// handle.
 385 template <typename InsnType>
 386 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 387                                    const void *Decoder);
 388
 389 template <typename InsnType>
 390 static DecodeStatus
 391 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 392                       const void *Decoder);
 393
 394 template <typename InsnType>
 395 static DecodeStatus
 396 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 397                        const void *Decoder);
 398
 399 template <typename InsnType>
 400 static DecodeStatus
 401 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 402                        const void *Decoder);
 403
 404 template <typename InsnType>
 405 static DecodeStatus
 406 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 407                        const void *Decoder);
 408
 409 template <typename InsnType>
 410 static DecodeStatus
 411 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 412                       const void *Decoder);
 413
 414 template <typename InsnType>
 415 static DecodeStatus
 416 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 417                        const void *Decoder);
 418
 419 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 420                                          uint64_t Address,
 421                                          const void *Decoder);
 422
 423 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 424                                            uint64_t Address,
 425                                            const void *Decoder);
 426
 427 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
 428                                        uint64_t Address,
 429                                        const void *Decoder);
 430
 431 namespace llvm {
 432 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 433               TheMips64elTarget;
 434 }
 435
 436 static MCDisassembler *createMipsDisassembler(
 437                        const Target &T,
 438                        const MCSubtargetInfo &STI,
 439                        MCContext &Ctx) {
 440   return new MipsDisassembler(STI, Ctx, true);
 441 }
 442
 443 static MCDisassembler *createMipselDisassembler(
 444                        const Target &T,
 445                        const MCSubtargetInfo &STI,
 446                        MCContext &Ctx) {
 447   return new MipsDisassembler(STI, Ctx, false);
 448 }
 449
 450 extern "C" void LLVMInitializeMipsDisassembler() {
 451   // Register the disassembler.
 452   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 453                                          createMipsDisassembler);
 454   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 455                                          createMipselDisassembler);
 456   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 457                                          createMipsDisassembler);
 458   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 459                                          createMipselDisassembler);
 460 }
 461
 462 #include "MipsGenDisassemblerTables.inc"
 463
 464 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 465   const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
 466   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 467   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 468 }
 469
 470 template <typename InsnType>
 471 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 472                                    const void *Decoder) {
 473   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 474   // The size of the n field depends on the element size
 475   // The register class also depends on this.
 476   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 477   unsigned NSize = 0;
 478   DecodeFN RegDecoder = nullptr;
 479   if ((tmp & 0x18) == 0x00) { // INSVE_B
 480     NSize = 4;
 481     RegDecoder = DecodeMSA128BRegisterClass;
 482   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 483     NSize = 3;
 484     RegDecoder = DecodeMSA128HRegisterClass;
 485   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 486     NSize = 2;
 487     RegDecoder = DecodeMSA128WRegisterClass;
 488   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 489     NSize = 1;
 490     RegDecoder = DecodeMSA128DRegisterClass;
 491   } else
 492     llvm_unreachable("Invalid encoding");
 493
 494   assert(NSize != 0 && RegDecoder != nullptr);
 495
 496   // $wd
 497   tmp = fieldFromInstruction(insn, 6, 5);
 498   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 499     return MCDisassembler::Fail;
 500   // $wd_in
 501   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 502     return MCDisassembler::Fail;
 503   // $n
 504   tmp = fieldFromInstruction(insn, 16, NSize);
 505   MI.addOperand(MCOperand::createImm(tmp));
 506   // $ws
 507   tmp = fieldFromInstruction(insn, 11, 5);
 508   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 509     return MCDisassembler::Fail;
 510   // $n2
 511   MI.addOperand(MCOperand::createImm(0));
 512
 513   return MCDisassembler::Success;
 514 }
 515
 516 template <typename InsnType>
 517 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 518                                           uint64_t Address,
 519                                           const void *Decoder) {
 520   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 521   // (otherwise we would have matched the ADDI instruction from the earlier
 522   // ISA's instead).
 523   //
 524   // We have:
 525   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 526   //      BOVC if rs >= rt
 527   //      BEQZALC if rs == 0 && rt != 0
 528   //      BEQC if rs < rt && rs != 0
 529
 530   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 531   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 532   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 533   bool HasRs = false;
 534
 535   if (Rs >= Rt) {
 536     MI.setOpcode(Mips::BOVC);
 537     HasRs = true;
 538   } else if (Rs != 0 && Rs < Rt) {
 539     MI.setOpcode(Mips::BEQC);
 540     HasRs = true;
 541   } else
 542     MI.setOpcode(Mips::BEQZALC);
 543
 544   if (HasRs)
 545     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 546                                        Rs)));
 547
 548   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 549                                      Rt)));
 550   MI.addOperand(MCOperand::createImm(Imm));
 551
 552   return MCDisassembler::Success;
 553 }
 554
 555 template <typename InsnType>
 556 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 557                                            uint64_t Address,
 558                                            const void *Decoder) {
 559   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 560   // (otherwise we would have matched the ADDI instruction from the earlier
 561   // ISA's instead).
 562   //
 563   // We have:
 564   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 565   //      BNVC if rs >= rt
 566   //      BNEZALC if rs == 0 && rt != 0
 567   //      BNEC if rs < rt && rs != 0
 568
 569   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 570   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 571   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 572   bool HasRs = false;
 573
 574   if (Rs >= Rt) {
 575     MI.setOpcode(Mips::BNVC);
 576     HasRs = true;
 577   } else if (Rs != 0 && Rs < Rt) {
 578     MI.setOpcode(Mips::BNEC);
 579     HasRs = true;
 580   } else
 581     MI.setOpcode(Mips::BNEZALC);
 582
 583   if (HasRs)
 584     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 585                                        Rs)));
 586
 587   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 588                                      Rt)));
 589   MI.addOperand(MCOperand::createImm(Imm));
 590
 591   return MCDisassembler::Success;
 592 }
 593
 594 template <typename InsnType>
 595 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 596                                            uint64_t Address,
 597                                            const void *Decoder) {
 598   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 599   // (otherwise we would have matched the BLEZL instruction from the earlier
 600   // ISA's instead).
 601   //
 602   // We have:
 603   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 604   //      Invalid if rs == 0
 605   //      BLEZC   if rs == 0  && rt != 0
 606   //      BGEZC   if rs == rt && rt != 0
 607   //      BGEC    if rs != rt && rs != 0  && rt != 0
 608
 609   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 610   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 611   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 612   bool HasRs = false;
 613
 614   if (Rt == 0)
 615     return MCDisassembler::Fail;
 616   else if (Rs == 0)
 617     MI.setOpcode(Mips::BLEZC);
 618   else if (Rs == Rt)
 619     MI.setOpcode(Mips::BGEZC);
 620   else {
 621     HasRs = true;
 622     MI.setOpcode(Mips::BGEC);
 623   }
 624
 625   if (HasRs)
 626     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 627                                        Rs)));
 628
 629   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 630                                      Rt)));
 631
 632   MI.addOperand(MCOperand::createImm(Imm));
 633
 634   return MCDisassembler::Success;
 635 }
 636
 637 template <typename InsnType>
 638 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 639                                            uint64_t Address,
 640                                            const void *Decoder) {
 641   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 642   // (otherwise we would have matched the BGTZL instruction from the earlier
 643   // ISA's instead).
 644   //
 645   // We have:
 646   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 647   //      Invalid if rs == 0
 648   //      BGTZC   if rs == 0  && rt != 0
 649   //      BLTZC   if rs == rt && rt != 0
 650   //      BLTC    if rs != rt && rs != 0  && rt != 0
 651
 652   bool HasRs = false;
 653
 654   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 655   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 656   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 657
 658   if (Rt == 0)
 659     return MCDisassembler::Fail;
 660   else if (Rs == 0)
 661     MI.setOpcode(Mips::BGTZC);
 662   else if (Rs == Rt)
 663     MI.setOpcode(Mips::BLTZC);
 664   else {
 665     MI.setOpcode(Mips::BLTC);
 666     HasRs = true;
 667   }
 668
 669   if (HasRs)
 670     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 671                                               Rs)));
 672
 673   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 674                                      Rt)));
 675
 676   MI.addOperand(MCOperand::createImm(Imm));
 677
 678   return MCDisassembler::Success;
 679 }
 680
 681 template <typename InsnType>
 682 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 683                                           uint64_t Address,
 684                                           const void *Decoder) {
 685   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 686   // (otherwise we would have matched the BGTZ instruction from the earlier
 687   // ISA's instead).
 688   //
 689   // We have:
 690   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 691   //      BGTZ    if rt == 0
 692   //      BGTZALC if rs == 0 && rt != 0
 693   //      BLTZALC if rs != 0 && rs == rt
 694   //      BLTUC   if rs != 0 && rs != rt
 695
 696   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 697   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 698   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 699   bool HasRs = false;
 700   bool HasRt = false;
 701
 702   if (Rt == 0) {
 703     MI.setOpcode(Mips::BGTZ);
 704     HasRs = true;
 705   } else if (Rs == 0) {
 706     MI.setOpcode(Mips::BGTZALC);
 707     HasRt = true;
 708   } else if (Rs == Rt) {
 709     MI.setOpcode(Mips::BLTZALC);
 710     HasRs = true;
 711   } else {
 712     MI.setOpcode(Mips::BLTUC);
 713     HasRs = true;
 714     HasRt = true;
 715   }
 716
 717   if (HasRs)
 718     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 719                                        Rs)));
 720
 721   if (HasRt)
 722     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 723                                        Rt)));
 724
 725   MI.addOperand(MCOperand::createImm(Imm));
 726
 727   return MCDisassembler::Success;
 728 }
 729
 730 template <typename InsnType>
 731 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 732                                            uint64_t Address,
 733                                            const void *Decoder) {
 734   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 735   // (otherwise we would have matched the BLEZL instruction from the earlier
 736   // ISA's instead).
 737   //
 738   // We have:
 739   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 740   //      Invalid   if rs == 0
 741   //      BLEZALC   if rs == 0  && rt != 0
 742   //      BGEZALC   if rs == rt && rt != 0
 743   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 744
 745   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 746   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 747   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 748   bool HasRs = false;
 749
 750   if (Rt == 0)
 751     return MCDisassembler::Fail;
 752   else if (Rs == 0)
 753     MI.setOpcode(Mips::BLEZALC);
 754   else if (Rs == Rt)
 755     MI.setOpcode(Mips::BGEZALC);
 756   else {
 757     HasRs = true;
 758     MI.setOpcode(Mips::BGEUC);
 759   }
 760
 761   if (HasRs)
 762     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 763                                        Rs)));
 764   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 765                                      Rt)));
 766
 767   MI.addOperand(MCOperand::createImm(Imm));
 768
 769   return MCDisassembler::Success;
 770 }
 771
 772 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 773 /// according to the given endianess.
 774 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 775                                       uint64_t &Size, uint32_t &Insn,
 776                                       bool IsBigEndian) {
 777   // We want to read exactly 2 Bytes of data.
 778   if (Bytes.size() < 2) {
 779     Size = 0;
 780     return MCDisassembler::Fail;
 781   }
 782
 783   if (IsBigEndian) {
 784     Insn = (Bytes[0] << 8) | Bytes[1];
 785   } else {
 786     Insn = (Bytes[1] << 8) | Bytes[0];
 787   }
 788
 789   return MCDisassembler::Success;
 790 }
 791
 792 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 793 /// according to the given endianess
 794 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 795                                       uint64_t &Size, uint32_t &Insn,
 796                                       bool IsBigEndian, bool IsMicroMips) {
 797   // We want to read exactly 4 Bytes of data.
 798   if (Bytes.size() < 4) {
 799     Size = 0;
 800     return MCDisassembler::Fail;
 801   }
 802
 803   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 804   // always precede the low 16 bits in the instruction stream (that is, they
 805   // are placed at lower addresses in the instruction stream).
 806   //
 807   // microMIPS byte ordering:
 808   //   Big-endian:    0 | 1 | 2 | 3
 809   //   Little-endian: 1 | 0 | 3 | 2
 810
 811   if (IsBigEndian) {
 812     // Encoded as a big-endian 32-bit word in the stream.
 813     Insn =
 814         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 815   } else {
 816     if (IsMicroMips) {
 817       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 818              (Bytes[1] << 24);
 819     } else {
 820       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 821              (Bytes[3] << 24);
 822     }
 823   }
 824
 825   return MCDisassembler::Success;
 826 }
 827
 828 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 829                                               ArrayRef<uint8_t> Bytes,
 830                                               uint64_t Address,
 831                                               raw_ostream &VStream,
 832                                               raw_ostream &CStream) const {
 833   uint32_t Insn;
 834   DecodeStatus Result;
 835
 836   if (IsMicroMips) {
 837     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 838
 839     if (hasMips32r6()) {
 840       DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
 841       // Calling the auto-generated decoder function for microMIPS32R6
 842       // (and microMIPS64R6) 16-bit instructions.
 843       Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
 844                                  Address, this, STI);
 845       if (Result != MCDisassembler::Fail) {
 846         Size = 2;
 847         return Result;
 848       }
 849     }
 850
 851     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 852     // Calling the auto-generated decoder function for microMIPS 16-bit
 853     // instructions.
 854     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 855                                this, STI);
 856     if (Result != MCDisassembler::Fail) {
 857       Size = 2;
 858       return Result;
 859     }
 860
 861     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 862     if (Result == MCDisassembler::Fail)
 863       return MCDisassembler::Fail;
 864
 865     if (hasMips32r6()) {
 866       DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
 867       // Calling the auto-generated decoder function.
 868       Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
 869                                  this, STI);
 870       if (Result != MCDisassembler::Fail) {
 871         Size = 4;
 872         return Result;
 873       }
 874     }
 875
 876     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 877     // Calling the auto-generated decoder function.
 878     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 879                                this, STI);
 880     if (Result != MCDisassembler::Fail) {
 881       Size = 4;
 882       return Result;
 883     }
 884     return MCDisassembler::Fail;
 885   }
 886
 887   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 888   if (Result == MCDisassembler::Fail)
 889     return MCDisassembler::Fail;
 890
 891   if (hasCOP3()) {
 892     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 893     Result =
 894         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 895     if (Result != MCDisassembler::Fail) {
 896       Size = 4;
 897       return Result;
 898     }
 899   }
 900
 901   if (hasMips32r6() && isGP64()) {
 902     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 903     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 904                                Address, this, STI);
 905     if (Result != MCDisassembler::Fail) {
 906       Size = 4;
 907       return Result;
 908     }
 909   }
 910
 911   if (hasMips32r6()) {
 912     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 913     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 914                                Address, this, STI);
 915     if (Result != MCDisassembler::Fail) {
 916       Size = 4;
 917       return Result;
 918     }
 919   }
 920
 921   if (hasCnMips()) {
 922     DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
 923     Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
 924                                Address, this, STI);
 925     if (Result != MCDisassembler::Fail) {
 926       Size = 4;
 927       return Result;
 928     }
 929   }
 930
 931   if (isGP64()) {
 932     DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
 933     Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
 934                                Address, this, STI);
 935     if (Result != MCDisassembler::Fail) {
 936       Size = 4;
 937       return Result;
 938     }
 939   }
 940
 941   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 942   // Calling the auto-generated decoder function.
 943   Result =
 944       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 945   if (Result != MCDisassembler::Fail) {
 946     Size = 4;
 947     return Result;
 948   }
 949
 950   return MCDisassembler::Fail;
 951 }
 952
 953 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 954                                                  unsigned RegNo,
 955                                                  uint64_t Address,
 956                                                  const void *Decoder) {
 957
 958   return MCDisassembler::Fail;
 959
 960 }
 961
 962 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 963                                              unsigned RegNo,
 964                                              uint64_t Address,
 965                                              const void *Decoder) {
 966
 967   if (RegNo > 31)
 968     return MCDisassembler::Fail;
 969
 970   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 971   Inst.addOperand(MCOperand::createReg(Reg));
 972   return MCDisassembler::Success;
 973 }
 974
 975 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 976                                                unsigned RegNo,
 977                                                uint64_t Address,
 978                                                const void *Decoder) {
 979   if (RegNo > 7)
 980     return MCDisassembler::Fail;
 981   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
 982   Inst.addOperand(MCOperand::createReg(Reg));
 983   return MCDisassembler::Success;
 984 }
 985
 986 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 987                                                    unsigned RegNo,
 988                                                    uint64_t Address,
 989                                                    const void *Decoder) {
 990   if (RegNo > 7)
 991     return MCDisassembler::Fail;
 992   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
 993   Inst.addOperand(MCOperand::createReg(Reg));
 994   return MCDisassembler::Success;
 995 }
 996
 997 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
 998                                                     unsigned RegNo,
 999                                                     uint64_t Address,
1000                                                     const void *Decoder) {
1001   if (RegNo > 7)
1002     return MCDisassembler::Fail;
1003   unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1004   Inst.addOperand(MCOperand::createReg(Reg));
1005   return MCDisassembler::Success;
1006 }
1007
1008 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1009                                              unsigned RegNo,
1010                                              uint64_t Address,
1011                                              const void *Decoder) {
1012   if (RegNo > 31)
1013     return MCDisassembler::Fail;
1014   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1015   Inst.addOperand(MCOperand::createReg(Reg));
1016   return MCDisassembler::Success;
1017 }
1018
1019 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1020                                            unsigned RegNo,
1021                                            uint64_t Address,
1022                                            const void *Decoder) {
1023   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1024     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1025
1026   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1027 }
1028
1029 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1030                                             unsigned RegNo,
1031                                             uint64_t Address,
1032                                             const void *Decoder) {
1033   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1034 }
1035
1036 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1037                                              unsigned RegNo,
1038                                              uint64_t Address,
1039                                              const void *Decoder) {
1040   if (RegNo > 31)
1041     return MCDisassembler::Fail;
1042
1043   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1044   Inst.addOperand(MCOperand::createReg(Reg));
1045   return MCDisassembler::Success;
1046 }
1047
1048 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1049                                              unsigned RegNo,
1050                                              uint64_t Address,
1051                                              const void *Decoder) {
1052   if (RegNo > 31)
1053     return MCDisassembler::Fail;
1054
1055   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1056   Inst.addOperand(MCOperand::createReg(Reg));
1057   return MCDisassembler::Success;
1058 }
1059
1060 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1061                                            unsigned RegNo,
1062                                            uint64_t Address,
1063                                            const void *Decoder) {
1064   if (RegNo > 31)
1065     return MCDisassembler::Fail;
1066   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1067   Inst.addOperand(MCOperand::createReg(Reg));
1068   return MCDisassembler::Success;
1069 }
1070
1071 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1072                                            unsigned RegNo,
1073                                            uint64_t Address,
1074                                            const void *Decoder) {
1075   if (RegNo > 7)
1076     return MCDisassembler::Fail;
1077   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1078   Inst.addOperand(MCOperand::createReg(Reg));
1079   return MCDisassembler::Success;
1080 }
1081
1082 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1083                                              uint64_t Address,
1084                                              const void *Decoder) {
1085   if (RegNo > 31)
1086     return MCDisassembler::Fail;
1087
1088   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1089   Inst.addOperand(MCOperand::createReg(Reg));
1090   return MCDisassembler::Success;
1091 }
1092
1093 static DecodeStatus DecodeMem(MCInst &Inst,
1094                               unsigned Insn,
1095                               uint64_t Address,
1096                               const void *Decoder) {
1097   int Offset = SignExtend32<16>(Insn & 0xffff);
1098   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1099   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1100
1101   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1102   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1103
1104   if(Inst.getOpcode() == Mips::SC ||
1105      Inst.getOpcode() == Mips::SCD){
1106     Inst.addOperand(MCOperand::createReg(Reg));
1107   }
1108
1109   Inst.addOperand(MCOperand::createReg(Reg));
1110   Inst.addOperand(MCOperand::createReg(Base));
1111   Inst.addOperand(MCOperand::createImm(Offset));
1112
1113   return MCDisassembler::Success;
1114 }
1115
1116 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1117                               unsigned Insn,
1118                               uint64_t Address,
1119                               const void *Decoder) {
1120   int Offset = SignExtend32<16>(Insn & 0xffff);
1121   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1122   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1123
1124   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1125
1126   Inst.addOperand(MCOperand::createReg(Base));
1127   Inst.addOperand(MCOperand::createImm(Offset));
1128   Inst.addOperand(MCOperand::createImm(Hint));
1129
1130   return MCDisassembler::Success;
1131 }
1132
1133 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1134                                     unsigned Insn,
1135                                     uint64_t Address,
1136                                     const void *Decoder) {
1137   int Offset = SignExtend32<12>(Insn & 0xfff);
1138   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1139   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1140
1141   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1142
1143   Inst.addOperand(MCOperand::createReg(Base));
1144   Inst.addOperand(MCOperand::createImm(Offset));
1145   Inst.addOperand(MCOperand::createImm(Hint));
1146
1147   return MCDisassembler::Success;
1148 }
1149
1150 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
1151                                     unsigned Insn,
1152                                     uint64_t Address,
1153                                     const void *Decoder) {
1154   int Offset = fieldFromInstruction(Insn, 7, 9);
1155   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1156   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1157
1158   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1159
1160   Inst.addOperand(MCOperand::createReg(Base));
1161   Inst.addOperand(MCOperand::createImm(Offset));
1162   Inst.addOperand(MCOperand::createImm(Hint));
1163
1164   return MCDisassembler::Success;
1165 }
1166
1167 static DecodeStatus DecodeSyncI(MCInst &Inst,
1168                               unsigned Insn,
1169                               uint64_t Address,
1170                               const void *Decoder) {
1171   int Offset = SignExtend32<16>(Insn & 0xffff);
1172   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1173
1174   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1175
1176   Inst.addOperand(MCOperand::createReg(Base));
1177   Inst.addOperand(MCOperand::createImm(Offset));
1178
1179   return MCDisassembler::Success;
1180 }
1181
1182 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1183                                     uint64_t Address, const void *Decoder) {
1184   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1185   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1186   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1187
1188   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1189   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1190
1191   Inst.addOperand(MCOperand::createReg(Reg));
1192   Inst.addOperand(MCOperand::createReg(Base));
1193
1194   // The immediate field of an LD/ST instruction is scaled which means it must
1195   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1196   // data format.
1197   // .b - 1 byte
1198   // .h - 2 bytes
1199   // .w - 4 bytes
1200   // .d - 8 bytes
1201   switch(Inst.getOpcode())
1202   {
1203   default:
1204     assert (0 && "Unexpected instruction");
1205     return MCDisassembler::Fail;
1206     break;
1207   case Mips::LD_B:
1208   case Mips::ST_B:
1209     Inst.addOperand(MCOperand::createImm(Offset));
1210     break;
1211   case Mips::LD_H:
1212   case Mips::ST_H:
1213     Inst.addOperand(MCOperand::createImm(Offset * 2));
1214     break;
1215   case Mips::LD_W:
1216   case Mips::ST_W:
1217     Inst.addOperand(MCOperand::createImm(Offset * 4));
1218     break;
1219   case Mips::LD_D:
1220   case Mips::ST_D:
1221     Inst.addOperand(MCOperand::createImm(Offset * 8));
1222     break;
1223   }
1224
1225   return MCDisassembler::Success;
1226 }
1227
1228 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1229                                     unsigned Insn,
1230                                     uint64_t Address,
1231                                     const void *Decoder) {
1232   unsigned Offset = Insn & 0xf;
1233   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1234   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1235
1236   switch (Inst.getOpcode()) {
1237     case Mips::LBU16_MM:
1238     case Mips::LHU16_MM:
1239     case Mips::LW16_MM:
1240       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1241             == MCDisassembler::Fail)
1242         return MCDisassembler::Fail;
1243       break;
1244     case Mips::SB16_MM:
1245     case Mips::SH16_MM:
1246     case Mips::SW16_MM:
1247       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1248             == MCDisassembler::Fail)
1249         return MCDisassembler::Fail;
1250       break;
1251   }
1252
1253   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1254         == MCDisassembler::Fail)
1255     return MCDisassembler::Fail;
1256
1257   switch (Inst.getOpcode()) {
1258     case Mips::LBU16_MM:
1259       if (Offset == 0xf)
1260         Inst.addOperand(MCOperand::createImm(-1));
1261       else
1262         Inst.addOperand(MCOperand::createImm(Offset));
1263       break;
1264     case Mips::SB16_MM:
1265       Inst.addOperand(MCOperand::createImm(Offset));
1266       break;
1267     case Mips::LHU16_MM:
1268     case Mips::SH16_MM:
1269       Inst.addOperand(MCOperand::createImm(Offset << 1));
1270       break;
1271     case Mips::LW16_MM:
1272     case Mips::SW16_MM:
1273       Inst.addOperand(MCOperand::createImm(Offset << 2));
1274       break;
1275   }
1276
1277   return MCDisassembler::Success;
1278 }
1279
1280 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1281                                           unsigned Insn,
1282                                           uint64_t Address,
1283                                           const void *Decoder) {
1284   unsigned Offset = Insn & 0x1F;
1285   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1286
1287   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1288
1289   Inst.addOperand(MCOperand::createReg(Reg));
1290   Inst.addOperand(MCOperand::createReg(Mips::SP));
1291   Inst.addOperand(MCOperand::createImm(Offset << 2));
1292
1293   return MCDisassembler::Success;
1294 }
1295
1296 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1297                                           unsigned Insn,
1298                                           uint64_t Address,
1299                                           const void *Decoder) {
1300   unsigned Offset = Insn & 0x7F;
1301   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1302
1303   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1304
1305   Inst.addOperand(MCOperand::createReg(Reg));
1306   Inst.addOperand(MCOperand::createReg(Mips::GP));
1307   Inst.addOperand(MCOperand::createImm(Offset << 2));
1308
1309   return MCDisassembler::Success;
1310 }
1311
1312 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1313                                                unsigned Insn,
1314                                                uint64_t Address,
1315                                                const void *Decoder) {
1316   int Offset = SignExtend32<4>(Insn & 0xf);
1317
1318   if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1319       == MCDisassembler::Fail)
1320     return MCDisassembler::Fail;
1321
1322   Inst.addOperand(MCOperand::createReg(Mips::SP));
1323   Inst.addOperand(MCOperand::createImm(Offset << 2));
1324
1325   return MCDisassembler::Success;
1326 }
1327
1328 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
1329                                     unsigned Insn,
1330                                     uint64_t Address,
1331                                     const void *Decoder) {
1332   int Offset = SignExtend32<9>(Insn & 0x1ff);
1333   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1334   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1335
1336   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1337   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1338
1339   Inst.addOperand(MCOperand::createReg(Reg));
1340   Inst.addOperand(MCOperand::createReg(Base));
1341   Inst.addOperand(MCOperand::createImm(Offset));
1342
1343   return MCDisassembler::Success;
1344 }
1345
1346 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1347                                      unsigned Insn,
1348                                      uint64_t Address,
1349                                      const void *Decoder) {
1350   int Offset = SignExtend32<12>(Insn & 0x0fff);
1351   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1352   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1353
1354   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1355   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1356
1357   switch (Inst.getOpcode()) {
1358   case Mips::SWM32_MM:
1359   case Mips::LWM32_MM:
1360     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1361         == MCDisassembler::Fail)
1362       return MCDisassembler::Fail;
1363     Inst.addOperand(MCOperand::createReg(Base));
1364     Inst.addOperand(MCOperand::createImm(Offset));
1365     break;
1366   case Mips::SC_MM:
1367     Inst.addOperand(MCOperand::createReg(Reg));
1368     // fallthrough
1369   default:
1370     Inst.addOperand(MCOperand::createReg(Reg));
1371     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1372       Inst.addOperand(MCOperand::createReg(Reg+1));
1373
1374     Inst.addOperand(MCOperand::createReg(Base));
1375     Inst.addOperand(MCOperand::createImm(Offset));
1376   }
1377
1378   return MCDisassembler::Success;
1379 }
1380
1381 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1382                                      unsigned Insn,
1383                                      uint64_t Address,
1384                                      const void *Decoder) {
1385   int Offset = SignExtend32<16>(Insn & 0xffff);
1386   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1387   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1388
1389   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1390   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1391
1392   Inst.addOperand(MCOperand::createReg(Reg));
1393   Inst.addOperand(MCOperand::createReg(Base));
1394   Inst.addOperand(MCOperand::createImm(Offset));
1395
1396   return MCDisassembler::Success;
1397 }
1398
1399 static DecodeStatus DecodeFMem(MCInst &Inst,
1400                                unsigned Insn,
1401                                uint64_t Address,
1402                                const void *Decoder) {
1403   int Offset = SignExtend32<16>(Insn & 0xffff);
1404   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1405   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1406
1407   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1408   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1409
1410   Inst.addOperand(MCOperand::createReg(Reg));
1411   Inst.addOperand(MCOperand::createReg(Base));
1412   Inst.addOperand(MCOperand::createImm(Offset));
1413
1414   return MCDisassembler::Success;
1415 }
1416
1417 static DecodeStatus DecodeFMem2(MCInst &Inst,
1418                                unsigned Insn,
1419                                uint64_t Address,
1420                                const void *Decoder) {
1421   int Offset = SignExtend32<16>(Insn & 0xffff);
1422   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1423   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1424
1425   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1426   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1427
1428   Inst.addOperand(MCOperand::createReg(Reg));
1429   Inst.addOperand(MCOperand::createReg(Base));
1430   Inst.addOperand(MCOperand::createImm(Offset));
1431
1432   return MCDisassembler::Success;
1433 }
1434
1435 static DecodeStatus DecodeFMem3(MCInst &Inst,
1436                                unsigned Insn,
1437                                uint64_t Address,
1438                                const void *Decoder) {
1439   int Offset = SignExtend32<16>(Insn & 0xffff);
1440   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1441   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1442
1443   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1444   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1445
1446   Inst.addOperand(MCOperand::createReg(Reg));
1447   Inst.addOperand(MCOperand::createReg(Base));
1448   Inst.addOperand(MCOperand::createImm(Offset));
1449
1450   return MCDisassembler::Success;
1451 }
1452
1453 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1454                                     unsigned Insn,
1455                                     uint64_t Address,
1456                                     const void *Decoder) {
1457   int Offset = SignExtend32<11>(Insn & 0x07ff);
1458   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1459   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1460
1461   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1462   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1463
1464   Inst.addOperand(MCOperand::createReg(Reg));
1465   Inst.addOperand(MCOperand::createReg(Base));
1466   Inst.addOperand(MCOperand::createImm(Offset));
1467
1468   return MCDisassembler::Success;
1469 }
1470 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1471                                        unsigned Insn,
1472                                        uint64_t Address,
1473                                        const void *Decoder) {
1474   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1475   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1476   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1477
1478   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1479   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1480
1481   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1482     Inst.addOperand(MCOperand::createReg(Rt));
1483   }
1484
1485   Inst.addOperand(MCOperand::createReg(Rt));
1486   Inst.addOperand(MCOperand::createReg(Base));
1487   Inst.addOperand(MCOperand::createImm(Offset));
1488
1489   return MCDisassembler::Success;
1490 }
1491
1492 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1493                                               unsigned RegNo,
1494                                               uint64_t Address,
1495                                               const void *Decoder) {
1496   // Currently only hardware register 29 is supported.
1497   if (RegNo != 29)
1498     return  MCDisassembler::Fail;
1499   Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1500   return MCDisassembler::Success;
1501 }
1502
1503 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1504                                               unsigned RegNo,
1505                                               uint64_t Address,
1506                                               const void *Decoder) {
1507   if (RegNo > 30 || RegNo %2)
1508     return MCDisassembler::Fail;
1509
1510   ;
1511   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1512   Inst.addOperand(MCOperand::createReg(Reg));
1513   return MCDisassembler::Success;
1514 }
1515
1516 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1517                                                 unsigned RegNo,
1518                                                 uint64_t Address,
1519                                                 const void *Decoder) {
1520   if (RegNo >= 4)
1521     return MCDisassembler::Fail;
1522
1523   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1524   Inst.addOperand(MCOperand::createReg(Reg));
1525   return MCDisassembler::Success;
1526 }
1527
1528 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1529                                                unsigned RegNo,
1530                                                uint64_t Address,
1531                                                const void *Decoder) {
1532   if (RegNo >= 4)
1533     return MCDisassembler::Fail;
1534
1535   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1536   Inst.addOperand(MCOperand::createReg(Reg));
1537   return MCDisassembler::Success;
1538 }
1539
1540 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1541                                                unsigned RegNo,
1542                                                uint64_t Address,
1543                                                const void *Decoder) {
1544   if (RegNo >= 4)
1545     return MCDisassembler::Fail;
1546
1547   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1548   Inst.addOperand(MCOperand::createReg(Reg));
1549   return MCDisassembler::Success;
1550 }
1551
1552 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1553                                                unsigned RegNo,
1554                                                uint64_t Address,
1555                                                const void *Decoder) {
1556   if (RegNo > 31)
1557     return MCDisassembler::Fail;
1558
1559   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1560   Inst.addOperand(MCOperand::createReg(Reg));
1561   return MCDisassembler::Success;
1562 }
1563
1564 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1565                                                unsigned RegNo,
1566                                                uint64_t Address,
1567                                                const void *Decoder) {
1568   if (RegNo > 31)
1569     return MCDisassembler::Fail;
1570
1571   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1572   Inst.addOperand(MCOperand::createReg(Reg));
1573   return MCDisassembler::Success;
1574 }
1575
1576 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1577                                                unsigned RegNo,
1578                                                uint64_t Address,
1579                                                const void *Decoder) {
1580   if (RegNo > 31)
1581     return MCDisassembler::Fail;
1582
1583   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1584   Inst.addOperand(MCOperand::createReg(Reg));
1585   return MCDisassembler::Success;
1586 }
1587
1588 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1589                                                unsigned RegNo,
1590                                                uint64_t Address,
1591                                                const void *Decoder) {
1592   if (RegNo > 31)
1593     return MCDisassembler::Fail;
1594
1595   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1596   Inst.addOperand(MCOperand::createReg(Reg));
1597   return MCDisassembler::Success;
1598 }
1599
1600 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1601                                                unsigned RegNo,
1602                                                uint64_t Address,
1603                                                const void *Decoder) {
1604   if (RegNo > 7)
1605     return MCDisassembler::Fail;
1606
1607   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1608   Inst.addOperand(MCOperand::createReg(Reg));
1609   return MCDisassembler::Success;
1610 }
1611
1612 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
1613                                             unsigned RegNo,
1614                                             uint64_t Address,
1615                                             const void *Decoder) {
1616   if (RegNo > 31)
1617     return MCDisassembler::Fail;
1618
1619   unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
1620   Inst.addOperand(MCOperand::createReg(Reg));
1621   return MCDisassembler::Success;
1622 }
1623
1624 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1625                                             unsigned RegNo,
1626                                             uint64_t Address,
1627                                             const void *Decoder) {
1628   if (RegNo > 31)
1629     return MCDisassembler::Fail;
1630
1631   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1632   Inst.addOperand(MCOperand::createReg(Reg));
1633   return MCDisassembler::Success;
1634 }
1635
1636 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1637                                        unsigned Offset,
1638                                        uint64_t Address,
1639                                        const void *Decoder) {
1640   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1641   Inst.addOperand(MCOperand::createImm(BranchOffset));
1642   return MCDisassembler::Success;
1643 }
1644
1645 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1646                                      unsigned Insn,
1647                                      uint64_t Address,
1648                                      const void *Decoder) {
1649
1650   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1651   Inst.addOperand(MCOperand::createImm(JumpOffset));
1652   return MCDisassembler::Success;
1653 }
1654
1655 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1656                                          unsigned Offset,
1657                                          uint64_t Address,
1658                                          const void *Decoder) {
1659   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1660
1661   Inst.addOperand(MCOperand::createImm(BranchOffset));
1662   return MCDisassembler::Success;
1663 }
1664
1665 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1666                                          unsigned Offset,
1667                                          uint64_t Address,
1668                                          const void *Decoder) {
1669   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1670
1671   Inst.addOperand(MCOperand::createImm(BranchOffset));
1672   return MCDisassembler::Success;
1673 }
1674
1675 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1676                                           unsigned Offset,
1677                                           uint64_t Address,
1678                                           const void *Decoder) {
1679   int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1680   Inst.addOperand(MCOperand::createImm(BranchOffset));
1681   return MCDisassembler::Success;
1682 }
1683
1684 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1685                                            unsigned Offset,
1686                                            uint64_t Address,
1687                                            const void *Decoder) {
1688   int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1689   Inst.addOperand(MCOperand::createImm(BranchOffset));
1690   return MCDisassembler::Success;
1691 }
1692
1693 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1694                                          unsigned Offset,
1695                                          uint64_t Address,
1696                                          const void *Decoder) {
1697   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1698   Inst.addOperand(MCOperand::createImm(BranchOffset));
1699   return MCDisassembler::Success;
1700 }
1701
1702 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1703                                        unsigned Insn,
1704                                        uint64_t Address,
1705                                        const void *Decoder) {
1706   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1707   Inst.addOperand(MCOperand::createImm(JumpOffset));
1708   return MCDisassembler::Success;
1709 }
1710
1711 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1712                                        unsigned Value,
1713                                        uint64_t Address,
1714                                        const void *Decoder) {
1715   if (Value == 0)
1716     Inst.addOperand(MCOperand::createImm(1));
1717   else if (Value == 0x7)
1718     Inst.addOperand(MCOperand::createImm(-1));
1719   else
1720     Inst.addOperand(MCOperand::createImm(Value << 2));
1721   return MCDisassembler::Success;
1722 }
1723
1724 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1725                                     unsigned Value,
1726                                     uint64_t Address,
1727                                     const void *Decoder) {
1728   Inst.addOperand(MCOperand::createImm(Value << 2));
1729   return MCDisassembler::Success;
1730 }
1731
1732 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1733                                   unsigned Value,
1734                                   uint64_t Address,
1735                                   const void *Decoder) {
1736   if (Value == 0x7F)
1737     Inst.addOperand(MCOperand::createImm(-1));
1738   else
1739     Inst.addOperand(MCOperand::createImm(Value));
1740   return MCDisassembler::Success;
1741 }
1742
1743 static DecodeStatus DecodeSimm4(MCInst &Inst,
1744                                 unsigned Value,
1745                                 uint64_t Address,
1746                                 const void *Decoder) {
1747   Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
1748   return MCDisassembler::Success;
1749 }
1750
1751 static DecodeStatus DecodeSimm16(MCInst &Inst,
1752                                  unsigned Insn,
1753                                  uint64_t Address,
1754                                  const void *Decoder) {
1755   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
1756   return MCDisassembler::Success;
1757 }
1758
1759 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1760                                  unsigned Insn,
1761                                  uint64_t Address,
1762                                  const void *Decoder) {
1763   // We add one to the immediate field as it was encoded as 'imm - 1'.
1764   Inst.addOperand(MCOperand::createImm(Insn + 1));
1765   return MCDisassembler::Success;
1766 }
1767
1768 static DecodeStatus DecodeInsSize(MCInst &Inst,
1769                                   unsigned Insn,
1770                                   uint64_t Address,
1771                                   const void *Decoder) {
1772   // First we need to grab the pos(lsb) from MCInst.
1773   int Pos = Inst.getOperand(2).getImm();
1774   int Size = (int) Insn - Pos + 1;
1775   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1776   return MCDisassembler::Success;
1777 }
1778
1779 static DecodeStatus DecodeExtSize(MCInst &Inst,
1780                                   unsigned Insn,
1781                                   uint64_t Address,
1782                                   const void *Decoder) {
1783   int Size = (int) Insn  + 1;
1784   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1785   return MCDisassembler::Success;
1786 }
1787
1788 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1789                                      uint64_t Address, const void *Decoder) {
1790   Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1791   return MCDisassembler::Success;
1792 }
1793
1794 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1795                                      uint64_t Address, const void *Decoder) {
1796   Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1797   return MCDisassembler::Success;
1798 }
1799
1800 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1801                                   uint64_t Address, const void *Decoder) {
1802   int32_t DecodedValue;
1803   switch (Insn) {
1804   case 0: DecodedValue = 256; break;
1805   case 1: DecodedValue = 257; break;
1806   case 510: DecodedValue = -258; break;
1807   case 511: DecodedValue = -257; break;
1808   default: DecodedValue = SignExtend32<9>(Insn); break;
1809   }
1810   Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1811   return MCDisassembler::Success;
1812 }
1813
1814 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1815                                     uint64_t Address, const void *Decoder) {
1816   // Insn must be >= 0, since it is unsigned that condition is always true.
1817   assert(Insn < 16);
1818   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1819                              255, 32768, 65535};
1820   Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1821   return MCDisassembler::Success;
1822 }
1823
1824 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1825                                     uint64_t Address, const void *Decoder) {
1826   Inst.addOperand(MCOperand::createImm(Insn << 2));
1827   return MCDisassembler::Success;
1828 }
1829
1830 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1831                                          unsigned Insn,
1832                                          uint64_t Address,
1833                                          const void *Decoder) {
1834   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1835                      Mips::S6, Mips::FP};
1836   unsigned RegNum;
1837
1838   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1839   // Empty register lists are not allowed.
1840   if (RegLst == 0)
1841     return MCDisassembler::Fail;
1842
1843   RegNum = RegLst & 0xf;
1844   for (unsigned i = 0; i < RegNum; i++)
1845     Inst.addOperand(MCOperand::createReg(Regs[i]));
1846
1847   if (RegLst & 0x10)
1848     Inst.addOperand(MCOperand::createReg(Mips::RA));
1849
1850   return MCDisassembler::Success;
1851 }
1852
1853 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1854                                            uint64_t Address,
1855                                            const void *Decoder) {
1856   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1857   unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1858   unsigned RegNum = RegLst & 0x3;
1859
1860   for (unsigned i = 0; i <= RegNum; i++)
1861     Inst.addOperand(MCOperand::createReg(Regs[i]));
1862
1863   Inst.addOperand(MCOperand::createReg(Mips::RA));
1864
1865   return MCDisassembler::Success;
1866 }
1867
1868 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
1869                                        uint64_t Address, const void *Decoder) {
1870
1871   unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1872
1873   switch (RegPair) {
1874   default:
1875     return MCDisassembler::Fail;
1876   case 0:
1877     Inst.addOperand(MCOperand::createReg(Mips::A1));
1878     Inst.addOperand(MCOperand::createReg(Mips::A2));
1879     break;
1880   case 1:
1881     Inst.addOperand(MCOperand::createReg(Mips::A1));
1882     Inst.addOperand(MCOperand::createReg(Mips::A3));
1883     break;
1884   case 2:
1885     Inst.addOperand(MCOperand::createReg(Mips::A2));
1886     Inst.addOperand(MCOperand::createReg(Mips::A3));
1887     break;
1888   case 3:
1889     Inst.addOperand(MCOperand::createReg(Mips::A0));
1890     Inst.addOperand(MCOperand::createReg(Mips::S5));
1891     break;
1892   case 4:
1893     Inst.addOperand(MCOperand::createReg(Mips::A0));
1894     Inst.addOperand(MCOperand::createReg(Mips::S6));
1895     break;
1896   case 5:
1897     Inst.addOperand(MCOperand::createReg(Mips::A0));
1898     Inst.addOperand(MCOperand::createReg(Mips::A1));
1899     break;
1900   case 6:
1901     Inst.addOperand(MCOperand::createReg(Mips::A0));
1902     Inst.addOperand(MCOperand::createReg(Mips::A2));
1903     break;
1904   case 7:
1905     Inst.addOperand(MCOperand::createReg(Mips::A0));
1906     Inst.addOperand(MCOperand::createReg(Mips::A3));
1907     break;
1908   }
1909
1910   return MCDisassembler::Success;
1911 }
1912
1913 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1914                                      uint64_t Address, const void *Decoder) {
1915   Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
1916   return MCDisassembler::Success;
1917 }