1 //===- MSP430RegisterInfo.cpp - MSP430 Register Information ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MSP430 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "msp430-reg-info"
17 #include "MSP430MachineFunctionInfo.h"
18 #include "MSP430RegisterInfo.h"
19 #include "MSP430TargetMachine.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/Support/ErrorHandling.h"
29 #define GET_REGINFO_MC_DESC
30 #define GET_REGINFO_TARGET_DESC
31 #include "MSP430GenRegisterInfo.inc"
35 // FIXME: Provide proper call frame setup / destroy opcodes.
36 MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
37 const TargetInstrInfo &tii)
38 : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
40 StackAlign = TM.getFrameLowering()->getStackAlignment();
44 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
45 const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering();
46 const Function* F = MF->getFunction();
47 static const unsigned CalleeSavedRegs[] = {
48 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
49 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
52 static const unsigned CalleeSavedRegsFP[] = {
53 MSP430::R5W, MSP430::R6W, MSP430::R7W,
54 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
57 static const unsigned CalleeSavedRegsIntr[] = {
58 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
59 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
60 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
63 static const unsigned CalleeSavedRegsIntrFP[] = {
64 MSP430::R5W, MSP430::R6W, MSP430::R7W,
65 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
66 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
71 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
72 CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
74 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
75 CalleeSavedRegsIntr : CalleeSavedRegs);
79 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
80 BitVector Reserved(getNumRegs());
81 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
83 // Mark 4 special registers with subregisters as reserved.
84 Reserved.set(MSP430::PCB);
85 Reserved.set(MSP430::SPB);
86 Reserved.set(MSP430::SRB);
87 Reserved.set(MSP430::CGB);
88 Reserved.set(MSP430::PCW);
89 Reserved.set(MSP430::SPW);
90 Reserved.set(MSP430::SRW);
91 Reserved.set(MSP430::CGW);
93 // Mark frame pointer as reserved if needed.
95 Reserved.set(MSP430::FPW);
100 const TargetRegisterClass *
101 MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
102 return &MSP430::GR16RegClass;
105 void MSP430RegisterInfo::
106 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
107 MachineBasicBlock::iterator I) const {
108 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
110 if (!TFI->hasReservedCallFrame(MF)) {
111 // If the stack pointer can be changed after prologue, turn the
112 // adjcallstackup instruction into a 'sub SPW, <amt>' and the
113 // adjcallstackdown instruction into 'add SPW, <amt>'
114 // TODO: consider using push / pop instead of sub + store / add
115 MachineInstr *Old = I;
116 uint64_t Amount = Old->getOperand(0).getImm();
118 // We need to keep the stack aligned properly. To do this, we round the
119 // amount of space needed for the outgoing arguments up to the next
120 // alignment boundary.
121 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
123 MachineInstr *New = 0;
124 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
125 New = BuildMI(MF, Old->getDebugLoc(),
126 TII.get(MSP430::SUB16ri), MSP430::SPW)
127 .addReg(MSP430::SPW).addImm(Amount);
129 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
130 // factor out the amount the callee already popped.
131 uint64_t CalleeAmt = Old->getOperand(1).getImm();
134 New = BuildMI(MF, Old->getDebugLoc(),
135 TII.get(MSP430::ADD16ri), MSP430::SPW)
136 .addReg(MSP430::SPW).addImm(Amount);
140 // The SRW implicit def is dead.
141 New->getOperand(3).setIsDead();
143 // Replace the pseudo instruction with a new instruction...
147 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
148 // If we are performing frame pointer elimination and if the callee pops
149 // something off the stack pointer, add it back.
150 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
151 MachineInstr *Old = I;
153 BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
154 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
155 // The SRW implicit def is dead.
156 New->getOperand(3).setIsDead();
166 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
167 int SPAdj, RegScavenger *RS) const {
168 assert(SPAdj == 0 && "Unexpected");
171 MachineInstr &MI = *II;
172 MachineBasicBlock &MBB = *MI.getParent();
173 MachineFunction &MF = *MBB.getParent();
174 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
175 DebugLoc dl = MI.getDebugLoc();
176 while (!MI.getOperand(i).isFI()) {
178 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
181 int FrameIndex = MI.getOperand(i).getIndex();
183 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW);
184 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
190 Offset += MF.getFrameInfo()->getStackSize();
192 Offset += 2; // Skip the saved FPW
194 // Fold imm into offset
195 Offset += MI.getOperand(i+1).getImm();
197 if (MI.getOpcode() == MSP430::ADD16ri) {
198 // This is actually "load effective address" of the stack slot
199 // instruction. We have only two-address instructions, thus we need to
200 // expand it into mov + add
202 MI.setDesc(TII.get(MSP430::MOV16rr));
203 MI.getOperand(i).ChangeToRegister(BasePtr, false);
208 // We need to materialize the offset via add instruction.
209 unsigned DstReg = MI.getOperand(0).getReg();
211 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
212 .addReg(DstReg).addImm(-Offset);
214 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
215 .addReg(DstReg).addImm(Offset);
220 MI.getOperand(i).ChangeToRegister(BasePtr, false);
221 MI.getOperand(i+1).ChangeToImmediate(Offset);
225 MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
227 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
229 // Create a frame entry for the FPW register that must be saved.
230 if (TFI->hasFP(MF)) {
231 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4, true);
233 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
234 "Slot for FPW register must be last in order to be found!");
238 unsigned MSP430RegisterInfo::getRARegister() const {
242 unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
243 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
245 return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW;
248 int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
249 llvm_unreachable("Not implemented yet!");
253 int MSP430RegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
254 llvm_unreachable("Not implemented yet!");