Hide more details in tablegen generated MCRegisterInfo ctor function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134027 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 8f10343a627e11b4ea6b1281f2ac1f4299c49529..fa937f352e50328da3abf6d1d8c50d04e6eae433 100644 (file)
--- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -58,8 +58,7 @@ EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
 
 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
                                          const ARMSubtarget &sti)
-  : ARMGenRegisterInfo(ARMRegDesc, ARMRegInfoDesc,
-                       ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
+  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
     TII(tii), STI(sti),
     FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
     BasePtr(ARM::R6) {

diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 3eef05f751c3bf9390e31c9e8028c6460ac2e3c5..b0bb7c0508a5e384a68e41185a338e848a765eca 100644 (file)
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -41,8 +41,7 @@
 using namespace llvm;
 
 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
-  : AlphaGenRegisterInfo(AlphaRegDesc, AlphaRegInfoDesc,
-                         Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
+  : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
     TII(tii) {
 }
 

diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
index aa4374488dcffdbf4dd85711a3b54522de79f4b2..e0fcce0854fc9013a55b80502f5d777c3718d23a 100644 (file)
--- a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
+++ b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
@@ -38,8 +38,7 @@ using namespace llvm;
 
 BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
                                            const TargetInstrInfo &tii)
-  : BlackfinGenRegisterInfo(BlackfinRegDesc, BlackfinRegInfoDesc,
-                            BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
+  : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
     Subtarget(st),
     TII(tii) {}
 

diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp
index a84dd5ae898029d945bf4aedf06dd8f36a508860..e37bc9bbda69a537610c68bcd44731de3c82c9dc 100644 (file)
--- a/lib/Target/CellSPU/SPURegisterInfo.cpp
+++ b/lib/Target/CellSPU/SPURegisterInfo.cpp
@@ -189,8 +189,7 @@ unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
 
 SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
                                  const TargetInstrInfo &tii) :
-  SPUGenRegisterInfo(SPURegDesc, SPURegInfoDesc,
-                     SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
+  SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
   Subtarget(subtarget),
   TII(tii)
 {

diff --git a/lib/Target/MBlaze/MBlazeRegisterInfo.cpp b/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
index 415c83b31a4d1177eb55c22a5d1dc78104695bbf..c370065c7bd30058e9e9baad9a0f6cbb8cef3322 100644 (file)
--- a/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
+++ b/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
@@ -45,8 +45,7 @@ using namespace llvm;
 
 MBlazeRegisterInfo::
 MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
-  : MBlazeGenRegisterInfo(MBlazeRegDesc, MBlazeRegInfoDesc,
-                          MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
+  : MBlazeGenRegisterInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
     Subtarget(ST), TII(tii) {}
 
 /// getRegisterNumbering - Given the enum value for some register, e.g.

diff --git a/lib/Target/MSP430/MSP430RegisterInfo.cpp b/lib/Target/MSP430/MSP430RegisterInfo.cpp
index 0a2e93ac08bea76f41a3eb367146bd5865ae424a..eaa994777b13bd0814283991626eecfd8dbafd41 100644 (file)
--- a/lib/Target/MSP430/MSP430RegisterInfo.cpp
+++ b/lib/Target/MSP430/MSP430RegisterInfo.cpp
@@ -35,8 +35,7 @@ using namespace llvm;
 // FIXME: Provide proper call frame setup / destroy opcodes.
 MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
                                        const TargetInstrInfo &tii)
-  : MSP430GenRegisterInfo(MSP430RegDesc, MSP430RegInfoDesc,
-                          MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
+  : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
     TM(tm), TII(tii) {
   StackAlign = TM.getFrameLowering()->getStackAlignment();
 }

diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp
index 2b74f73fd52f50b3b9a5327cd0ea47253e532f44..1025583a4cc4dbeb31485d55526627ec2f8a5442 100644 (file)
--- a/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -44,8 +44,7 @@ using namespace llvm;
 
 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
                                    const TargetInstrInfo &tii)
-  : MipsGenRegisterInfo(MipsRegDesc, MipsRegInfoDesc,
-                        Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
+  : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
     Subtarget(ST), TII(tii) {}
 
 /// getRegisterNumbering - Given the enum value for some register, e.g.

diff --git a/lib/Target/PTX/PTXRegisterInfo.cpp b/lib/Target/PTX/PTXRegisterInfo.cpp
index 06c542444f96b7250f249e1f73d96bfffbab843c..f32c2b70a3bc07a49ee4c7d77765249f21cdbad2 100644 (file)
--- a/lib/Target/PTX/PTXRegisterInfo.cpp
+++ b/lib/Target/PTX/PTXRegisterInfo.cpp
@@ -25,7 +25,7 @@ using namespace llvm;
 
 PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM,
                                  const TargetInstrInfo &TII)
-  : PTXGenRegisterInfo(PTXRegDesc, PTXRegInfoDesc) {
+  : PTXGenRegisterInfo() {
 }
 
 void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index bd5c7229472d036901dd669ee5966204a36b0cd3..91408ccb6dca47d83b206a973072ed3872411e00 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -114,8 +114,7 @@ unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
 
 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
                                  const TargetInstrInfo &tii)
-  : PPCGenRegisterInfo(PPCRegDesc, PPCRegInfoDesc,
-                       PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
+  : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
     Subtarget(ST), TII(tii) {
   ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
   ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;

diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index 48ca15b590e15eeb912904fba1d28e398e2149bd..127b9513cece0fadbcc350ac3856a659f2cac665 100644 (file)
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -32,8 +32,7 @@ using namespace llvm;
 
 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
                                      const TargetInstrInfo &tii)
-  : SparcGenRegisterInfo(SparcRegDesc, SparcRegInfoDesc,
-                         SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
+  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
     Subtarget(st), TII(tii) {
 }
 

diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/lib/Target/SystemZ/SystemZRegisterInfo.cpp
index b3c76dd2350efbf9d053ecbaf1cbd8efae2d26d5..319cc46a2dfd11d020a7efcdfc3357ebdf8785ab 100644 (file)
--- a/lib/Target/SystemZ/SystemZRegisterInfo.cpp
+++ b/lib/Target/SystemZ/SystemZRegisterInfo.cpp
@@ -34,8 +34,7 @@ using namespace llvm;
 
 SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
                                          const SystemZInstrInfo &tii)
-  : SystemZGenRegisterInfo(SystemZRegDesc, SystemZRegInfoDesc,
-                           SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
+  : SystemZGenRegisterInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
     TM(tm), TII(tii) {
 }
 

diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 9e4fdad6ceab00b8e4058e772034e909d282ba69..d771d40ce97de1068c525c40ce8ded254e76c793 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -54,8 +54,7 @@ ForceStackAlign("force-align-stack",
 
 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
                                  const TargetInstrInfo &tii)
-  : X86GenRegisterInfo(X86RegDesc, X86RegInfoDesc,
-                       tm.getSubtarget<X86Subtarget>().is64Bit() ?
+  : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
                          X86::ADJCALLSTACKDOWN64 :
                          X86::ADJCALLSTACKDOWN32,
                        tm.getSubtarget<X86Subtarget>().is64Bit() ?

diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp
index 0c9473effffbf62c6906fa92740b08676eb1edd7..ecb9e8047c10d90b213c02d5ca3abe247e758827 100644 (file)
--- a/lib/Target/XCore/XCoreRegisterInfo.cpp
+++ b/lib/Target/XCore/XCoreRegisterInfo.cpp
@@ -40,8 +40,7 @@
 using namespace llvm;
 
 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
-  : XCoreGenRegisterInfo(XCoreRegDesc, XCoreRegInfoDesc,
-                         XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
+  : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
     TII(tii) {
 }
 

diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index 5753c80aeb221a6fc88a058718393c657e2bd21d..bf270533a1a59cda565d00fdd97da0f79e00aef1 100644 (file)
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -215,8 +215,7 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
 
   OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
      << "  explicit " << ClassName
-     << "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
-     << "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
+     << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
      << "  virtual int getDwarfRegNumFull(unsigned RegNum, "
      << "unsigned Flavour) const;\n"
      << "  virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
@@ -549,8 +548,9 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
   OS << "  };\n";
 
   // Emit extra information about registers.
+  const std::string &TargetName = Target.getName();
   OS << "\n  static const TargetRegisterInfoDesc "
-     << Target.getName() << "RegInfoDesc[] = "
+     << TargetName << "RegInfoDesc[] = "
      << "{ // Extra Descriptors\n";
   OS << "    { 0, 0 },\n";
 
@@ -660,13 +660,13 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
 
   // Emit the constructor of the class...
   OS << ClassName << "::" << ClassName
-     << "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
-     << "int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
-     << "  : TargetRegisterInfo(ID"
+     << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
+     << "  : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
      << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
      << "                 SubRegIndexTable,\n"
      << "                 CallFrameSetupOpcode, CallFrameDestroyOpcode) {\n"
-     << "  InitMCRegisterInfo(D, " << Regs.size()+1 << ");\n"
+     << "  InitMCRegisterInfo(" << TargetName << "RegDesc, "
+     << Regs.size()+1 << ");\n"
      << "}\n\n";
 
   // Collect all information about dwarf register numbers