1 //===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
18 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "packets"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/ScheduleDAG.h"
26 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
27 #include "llvm/CodeGen/LatencyPriorityQueue.h"
28 #include "llvm/CodeGen/SchedulerRegistry.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/Statistic.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/MC/MCInstrItineraries.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/Debug.h"
45 #include "HexagonTargetMachine.h"
46 #include "HexagonRegisterInfo.h"
47 #include "HexagonSubtarget.h"
48 #include "HexagonMachineFunctionInfo.h"
55 class HexagonPacketizer : public MachineFunctionPass {
59 HexagonPacketizer() : MachineFunctionPass(ID) {}
61 void getAnalysisUsage(AnalysisUsage &AU) const {
63 AU.addRequired<MachineDominatorTree>();
64 AU.addPreserved<MachineDominatorTree>();
65 AU.addRequired<MachineLoopInfo>();
66 AU.addPreserved<MachineLoopInfo>();
67 MachineFunctionPass::getAnalysisUsage(AU);
70 const char *getPassName() const {
71 return "Hexagon Packetizer";
74 bool runOnMachineFunction(MachineFunction &Fn);
76 char HexagonPacketizer::ID = 0;
78 class HexagonPacketizerList : public VLIWPacketizerList {
82 // Has the instruction been promoted to a dot-new instruction.
83 bool PromotedToDotNew;
85 // Has the instruction been glued to allocframe.
86 bool GlueAllocframeStore;
88 // Has the feeder instruction been glued to new value jump.
89 bool GlueToNewValueJump;
91 // Check if there is a dependence between some instruction already in this
92 // packet and this instruction.
95 // Only check for dependence if there are resources available to
96 // schedule this instruction.
97 bool FoundSequentialDependence;
101 HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
102 MachineDominatorTree &MDT);
104 // initPacketizerState - initialize some internal flags.
105 void initPacketizerState();
107 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
108 bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
110 // isSoloInstruction - return true if instruction MI can not be packetized
111 // with any other instruction, which means that MI itself is a packet.
112 bool isSoloInstruction(MachineInstr *MI);
114 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
116 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ);
118 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
120 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ);
122 MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
124 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
125 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
126 MachineBasicBlock::iterator &MII,
127 const TargetRegisterClass* RC);
128 bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
130 std::map <MachineInstr*, SUnit*> MIToSUnit,
131 MachineBasicBlock::iterator &MII,
132 const TargetRegisterClass* RC);
133 bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
135 std::map <MachineInstr*, SUnit*> MIToSUnit,
136 MachineBasicBlock::iterator &MII);
137 bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
139 std::map <MachineInstr*, SUnit*> MIToSUnit);
140 bool DemoteToDotOld(MachineInstr* MI);
141 bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
142 std::map <MachineInstr*, SUnit*> MIToSUnit);
143 bool RestrictingDepExistInPacket(MachineInstr*,
144 unsigned, std::map <MachineInstr*, SUnit*>);
145 bool isNewifiable(MachineInstr* MI);
146 bool isCondInst(MachineInstr* MI);
147 bool IsNewifyStore (MachineInstr* MI);
148 bool tryAllocateResourcesForConstExt(MachineInstr* MI);
149 bool canReserveResourcesForConstExt(MachineInstr *MI);
150 void reserveResourcesForConstExt(MachineInstr* MI);
151 bool isNewValueInst(MachineInstr* MI);
152 bool isDotNewInst(MachineInstr* MI);
156 // HexagonPacketizerList Ctor.
157 HexagonPacketizerList::HexagonPacketizerList(
158 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT)
159 : VLIWPacketizerList(MF, MLI, MDT, true){
162 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
163 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
164 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
165 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
167 // Instantiate the packetizer.
168 HexagonPacketizerList Packetizer(Fn, MLI, MDT);
170 // DFA state table should not be empty.
171 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
174 // Loop over all basic blocks and remove KILL pseudo-instructions
175 // These instructions confuse the dependence analysis. Consider:
177 // R0 = KILL R0, D0 (Insn 1)
179 // Here, Insn 1 will result in the dependence graph not emitting an output
180 // dependence between Insn 0 and Insn 2. This can lead to incorrect
183 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
184 MBB != MBBe; ++MBB) {
185 MachineBasicBlock::iterator End = MBB->end();
186 MachineBasicBlock::iterator MI = MBB->begin();
189 MachineBasicBlock::iterator DeleteMI = MI;
191 MBB->erase(DeleteMI);
199 // Loop over all of the basic blocks.
200 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
201 MBB != MBBe; ++MBB) {
202 // Find scheduling regions and schedule / packetize each region.
203 unsigned RemainingCount = MBB->size();
204 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
205 RegionEnd != MBB->begin();) {
206 // The next region starts above the previous region. Look backward in the
207 // instruction stream until we find the nearest boundary.
208 MachineBasicBlock::iterator I = RegionEnd;
209 for(;I != MBB->begin(); --I, --RemainingCount) {
210 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
215 // Skip empty scheduling regions.
216 if (I == RegionEnd) {
217 RegionEnd = llvm::prior(RegionEnd);
221 // Skip regions with one instruction.
222 if (I == llvm::prior(RegionEnd)) {
223 RegionEnd = llvm::prior(RegionEnd);
227 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
236 static bool IsIndirectCall(MachineInstr* MI) {
237 return ((MI->getOpcode() == Hexagon::CALLR) ||
238 (MI->getOpcode() == Hexagon::CALLRv3));
241 // Reserve resources for constant extender. Trigure an assertion if
243 void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
244 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
245 MachineInstr *PseudoMI = MI->getParent()->getParent()->CreateMachineInstr(
246 QII->get(Hexagon::IMMEXT), MI->getDebugLoc());
248 if (ResourceTracker->canReserveResources(PseudoMI)) {
249 ResourceTracker->reserveResources(PseudoMI);
250 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
252 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
253 llvm_unreachable("can not reserve resources for constant extender.");
258 bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
259 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
260 assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
261 "Should only be called for constant extended instructions");
262 MachineFunction *MF = MI->getParent()->getParent();
263 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT),
265 bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
266 MF->DeleteMachineInstr(PseudoMI);
270 // Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
271 // true, otherwise, return false.
272 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
273 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
274 MachineInstr *PseudoMI = MI->getParent()->getParent()->CreateMachineInstr(
275 QII->get(Hexagon::IMMEXT), MI->getDebugLoc());
277 if (ResourceTracker->canReserveResources(PseudoMI)) {
278 ResourceTracker->reserveResources(PseudoMI);
279 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
282 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
288 bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
292 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
293 const HexagonRegisterInfo* QRI =
294 (const HexagonRegisterInfo *) TM.getRegisterInfo();
296 // Check for lr dependence
297 if (DepReg == QRI->getRARegister()) {
301 if (QII->isDeallocRet(MI)) {
302 if (DepReg == QRI->getFrameRegister() ||
303 DepReg == QRI->getStackRegister())
307 // Check if this is a predicate dependence
308 const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
309 if (RC == &Hexagon::PredRegsRegClass) {
314 // Lastly check for an operand used in an indirect call
315 // If we had an attribute for checking if an instruction is an indirect call,
316 // then we could have avoided this relatively brittle implementation of
319 // Assumes that the first operand of the CALLr is the function address
321 if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
322 MachineOperand MO = MI->getOperand(0);
323 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
331 static bool IsRegDependence(const SDep::Kind DepType) {
332 return (DepType == SDep::Data || DepType == SDep::Anti ||
333 DepType == SDep::Output);
336 static bool IsDirectJump(MachineInstr* MI) {
337 return (MI->getOpcode() == Hexagon::JMP);
340 static bool IsSchedBarrier(MachineInstr* MI) {
341 switch (MI->getOpcode()) {
342 case Hexagon::BARRIER:
348 static bool IsControlFlow(MachineInstr* MI) {
349 return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
352 bool HexagonPacketizerList::isNewValueInst(MachineInstr* MI) {
353 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
354 if (QII->isNewValueJump(MI))
357 if (QII->isNewValueStore(MI))
363 // Function returns true if an instruction can be promoted to the new-value
364 // store. It will always return false for v2 and v3.
365 // It lists all the conditional and unconditional stores that can be promoted
366 // to the new-value stores.
368 bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
369 const HexagonRegisterInfo* QRI =
370 (const HexagonRegisterInfo *) TM.getRegisterInfo();
371 switch (MI->getOpcode())
375 case Hexagon::STrib_indexed:
376 case Hexagon::STrib_indexed_shl_V4:
377 case Hexagon::STrib_shl_V4:
378 case Hexagon::STrib_GP_V4:
379 case Hexagon::STb_GP_V4:
380 case Hexagon::POST_STbri:
381 case Hexagon::STrib_cPt:
382 case Hexagon::STrib_cdnPt_V4:
383 case Hexagon::STrib_cNotPt:
384 case Hexagon::STrib_cdnNotPt_V4:
385 case Hexagon::STrib_indexed_cPt:
386 case Hexagon::STrib_indexed_cdnPt_V4:
387 case Hexagon::STrib_indexed_cNotPt:
388 case Hexagon::STrib_indexed_cdnNotPt_V4:
389 case Hexagon::STrib_indexed_shl_cPt_V4:
390 case Hexagon::STrib_indexed_shl_cdnPt_V4:
391 case Hexagon::STrib_indexed_shl_cNotPt_V4:
392 case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
393 case Hexagon::POST_STbri_cPt:
394 case Hexagon::POST_STbri_cdnPt_V4:
395 case Hexagon::POST_STbri_cNotPt:
396 case Hexagon::POST_STbri_cdnNotPt_V4:
397 case Hexagon::STrib_abs_V4:
398 case Hexagon::STrib_abs_cPt_V4:
399 case Hexagon::STrib_abs_cdnPt_V4:
400 case Hexagon::STrib_abs_cNotPt_V4:
401 case Hexagon::STrib_abs_cdnNotPt_V4:
402 case Hexagon::STrib_imm_abs_V4:
403 case Hexagon::STrib_imm_abs_cPt_V4:
404 case Hexagon::STrib_imm_abs_cdnPt_V4:
405 case Hexagon::STrib_imm_abs_cNotPt_V4:
406 case Hexagon::STrib_imm_abs_cdnNotPt_V4:
407 case Hexagon::STb_GP_cPt_V4:
408 case Hexagon::STb_GP_cNotPt_V4:
409 case Hexagon::STb_GP_cdnPt_V4:
410 case Hexagon::STb_GP_cdnNotPt_V4:
411 case Hexagon::STrib_GP_cPt_V4:
412 case Hexagon::STrib_GP_cNotPt_V4:
413 case Hexagon::STrib_GP_cdnPt_V4:
414 case Hexagon::STrib_GP_cdnNotPt_V4:
418 case Hexagon::STrih_indexed:
419 case Hexagon::STrih_indexed_shl_V4:
420 case Hexagon::STrih_shl_V4:
421 case Hexagon::STrih_GP_V4:
422 case Hexagon::STh_GP_V4:
423 case Hexagon::POST_SThri:
424 case Hexagon::STrih_cPt:
425 case Hexagon::STrih_cdnPt_V4:
426 case Hexagon::STrih_cNotPt:
427 case Hexagon::STrih_cdnNotPt_V4:
428 case Hexagon::STrih_indexed_cPt:
429 case Hexagon::STrih_indexed_cdnPt_V4:
430 case Hexagon::STrih_indexed_cNotPt:
431 case Hexagon::STrih_indexed_cdnNotPt_V4:
432 case Hexagon::STrih_indexed_shl_cPt_V4:
433 case Hexagon::STrih_indexed_shl_cdnPt_V4:
434 case Hexagon::STrih_indexed_shl_cNotPt_V4:
435 case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
436 case Hexagon::POST_SThri_cPt:
437 case Hexagon::POST_SThri_cdnPt_V4:
438 case Hexagon::POST_SThri_cNotPt:
439 case Hexagon::POST_SThri_cdnNotPt_V4:
440 case Hexagon::STrih_abs_V4:
441 case Hexagon::STrih_abs_cPt_V4:
442 case Hexagon::STrih_abs_cdnPt_V4:
443 case Hexagon::STrih_abs_cNotPt_V4:
444 case Hexagon::STrih_abs_cdnNotPt_V4:
445 case Hexagon::STrih_imm_abs_V4:
446 case Hexagon::STrih_imm_abs_cPt_V4:
447 case Hexagon::STrih_imm_abs_cdnPt_V4:
448 case Hexagon::STrih_imm_abs_cNotPt_V4:
449 case Hexagon::STrih_imm_abs_cdnNotPt_V4:
450 case Hexagon::STh_GP_cPt_V4:
451 case Hexagon::STh_GP_cNotPt_V4:
452 case Hexagon::STh_GP_cdnPt_V4:
453 case Hexagon::STh_GP_cdnNotPt_V4:
454 case Hexagon::STrih_GP_cPt_V4:
455 case Hexagon::STrih_GP_cNotPt_V4:
456 case Hexagon::STrih_GP_cdnPt_V4:
457 case Hexagon::STrih_GP_cdnNotPt_V4:
461 case Hexagon::STriw_indexed:
462 case Hexagon::STriw_indexed_shl_V4:
463 case Hexagon::STriw_shl_V4:
464 case Hexagon::STriw_GP_V4:
465 case Hexagon::STw_GP_V4:
466 case Hexagon::POST_STwri:
467 case Hexagon::STriw_cPt:
468 case Hexagon::STriw_cdnPt_V4:
469 case Hexagon::STriw_cNotPt:
470 case Hexagon::STriw_cdnNotPt_V4:
471 case Hexagon::STriw_indexed_cPt:
472 case Hexagon::STriw_indexed_cdnPt_V4:
473 case Hexagon::STriw_indexed_cNotPt:
474 case Hexagon::STriw_indexed_cdnNotPt_V4:
475 case Hexagon::STriw_indexed_shl_cPt_V4:
476 case Hexagon::STriw_indexed_shl_cdnPt_V4:
477 case Hexagon::STriw_indexed_shl_cNotPt_V4:
478 case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
479 case Hexagon::POST_STwri_cPt:
480 case Hexagon::POST_STwri_cdnPt_V4:
481 case Hexagon::POST_STwri_cNotPt:
482 case Hexagon::POST_STwri_cdnNotPt_V4:
483 case Hexagon::STriw_abs_V4:
484 case Hexagon::STriw_abs_cPt_V4:
485 case Hexagon::STriw_abs_cdnPt_V4:
486 case Hexagon::STriw_abs_cNotPt_V4:
487 case Hexagon::STriw_abs_cdnNotPt_V4:
488 case Hexagon::STriw_imm_abs_V4:
489 case Hexagon::STriw_imm_abs_cPt_V4:
490 case Hexagon::STriw_imm_abs_cdnPt_V4:
491 case Hexagon::STriw_imm_abs_cNotPt_V4:
492 case Hexagon::STriw_imm_abs_cdnNotPt_V4:
493 case Hexagon::STw_GP_cPt_V4:
494 case Hexagon::STw_GP_cNotPt_V4:
495 case Hexagon::STw_GP_cdnPt_V4:
496 case Hexagon::STw_GP_cdnNotPt_V4:
497 case Hexagon::STriw_GP_cPt_V4:
498 case Hexagon::STriw_GP_cNotPt_V4:
499 case Hexagon::STriw_GP_cdnPt_V4:
500 case Hexagon::STriw_GP_cdnNotPt_V4:
501 return QRI->Subtarget.hasV4TOps();
506 static bool IsLoopN(MachineInstr *MI) {
507 return (MI->getOpcode() == Hexagon::LOOP0_i ||
508 MI->getOpcode() == Hexagon::LOOP0_r);
511 /// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
512 /// callee-saved register.
513 static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
514 const TargetRegisterInfo *TRI) {
515 for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
516 unsigned CalleeSavedReg = *CSR;
517 if (MI->modifiesRegister(CalleeSavedReg, TRI))
523 // Return the new value instruction for a given store.
524 static int GetDotNewOp(const int opc) {
526 default: llvm_unreachable("Unknown .new type");
527 // store new value byte
529 return Hexagon::STrib_nv_V4;
531 case Hexagon::STrib_indexed:
532 return Hexagon::STrib_indexed_nv_V4;
534 case Hexagon::STrib_indexed_shl_V4:
535 return Hexagon::STrib_indexed_shl_nv_V4;
537 case Hexagon::STrib_shl_V4:
538 return Hexagon::STrib_shl_nv_V4;
540 case Hexagon::STrib_GP_V4:
541 return Hexagon::STrib_GP_nv_V4;
543 case Hexagon::STb_GP_V4:
544 return Hexagon::STb_GP_nv_V4;
546 case Hexagon::POST_STbri:
547 return Hexagon::POST_STbri_nv_V4;
549 case Hexagon::STrib_cPt:
550 return Hexagon::STrib_cPt_nv_V4;
552 case Hexagon::STrib_cdnPt_V4:
553 return Hexagon::STrib_cdnPt_nv_V4;
555 case Hexagon::STrib_cNotPt:
556 return Hexagon::STrib_cNotPt_nv_V4;
558 case Hexagon::STrib_cdnNotPt_V4:
559 return Hexagon::STrib_cdnNotPt_nv_V4;
561 case Hexagon::STrib_indexed_cPt:
562 return Hexagon::STrib_indexed_cPt_nv_V4;
564 case Hexagon::STrib_indexed_cdnPt_V4:
565 return Hexagon::STrib_indexed_cdnPt_nv_V4;
567 case Hexagon::STrib_indexed_cNotPt:
568 return Hexagon::STrib_indexed_cNotPt_nv_V4;
570 case Hexagon::STrib_indexed_cdnNotPt_V4:
571 return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
573 case Hexagon::STrib_indexed_shl_cPt_V4:
574 return Hexagon::STrib_indexed_shl_cPt_nv_V4;
576 case Hexagon::STrib_indexed_shl_cdnPt_V4:
577 return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
579 case Hexagon::STrib_indexed_shl_cNotPt_V4:
580 return Hexagon::STrib_indexed_shl_cNotPt_nv_V4;
582 case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
583 return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
585 case Hexagon::POST_STbri_cPt:
586 return Hexagon::POST_STbri_cPt_nv_V4;
588 case Hexagon::POST_STbri_cdnPt_V4:
589 return Hexagon::POST_STbri_cdnPt_nv_V4;
591 case Hexagon::POST_STbri_cNotPt:
592 return Hexagon::POST_STbri_cNotPt_nv_V4;
594 case Hexagon::POST_STbri_cdnNotPt_V4:
595 return Hexagon::POST_STbri_cdnNotPt_nv_V4;
597 case Hexagon::STb_GP_cPt_V4:
598 return Hexagon::STb_GP_cPt_nv_V4;
600 case Hexagon::STb_GP_cNotPt_V4:
601 return Hexagon::STb_GP_cNotPt_nv_V4;
603 case Hexagon::STb_GP_cdnPt_V4:
604 return Hexagon::STb_GP_cdnPt_nv_V4;
606 case Hexagon::STb_GP_cdnNotPt_V4:
607 return Hexagon::STb_GP_cdnNotPt_nv_V4;
609 case Hexagon::STrib_GP_cPt_V4:
610 return Hexagon::STrib_GP_cPt_nv_V4;
612 case Hexagon::STrib_GP_cNotPt_V4:
613 return Hexagon::STrib_GP_cNotPt_nv_V4;
615 case Hexagon::STrib_GP_cdnPt_V4:
616 return Hexagon::STrib_GP_cdnPt_nv_V4;
618 case Hexagon::STrib_GP_cdnNotPt_V4:
619 return Hexagon::STrib_GP_cdnNotPt_nv_V4;
621 // store new value halfword
623 return Hexagon::STrih_nv_V4;
625 case Hexagon::STrih_indexed:
626 return Hexagon::STrih_indexed_nv_V4;
628 case Hexagon::STrih_indexed_shl_V4:
629 return Hexagon::STrih_indexed_shl_nv_V4;
631 case Hexagon::STrih_shl_V4:
632 return Hexagon::STrih_shl_nv_V4;
634 case Hexagon::STrih_GP_V4:
635 return Hexagon::STrih_GP_nv_V4;
637 case Hexagon::STh_GP_V4:
638 return Hexagon::STh_GP_nv_V4;
640 case Hexagon::POST_SThri:
641 return Hexagon::POST_SThri_nv_V4;
643 case Hexagon::STrih_cPt:
644 return Hexagon::STrih_cPt_nv_V4;
646 case Hexagon::STrih_cdnPt_V4:
647 return Hexagon::STrih_cdnPt_nv_V4;
649 case Hexagon::STrih_cNotPt:
650 return Hexagon::STrih_cNotPt_nv_V4;
652 case Hexagon::STrih_cdnNotPt_V4:
653 return Hexagon::STrih_cdnNotPt_nv_V4;
655 case Hexagon::STrih_indexed_cPt:
656 return Hexagon::STrih_indexed_cPt_nv_V4;
658 case Hexagon::STrih_indexed_cdnPt_V4:
659 return Hexagon::STrih_indexed_cdnPt_nv_V4;
661 case Hexagon::STrih_indexed_cNotPt:
662 return Hexagon::STrih_indexed_cNotPt_nv_V4;
664 case Hexagon::STrih_indexed_cdnNotPt_V4:
665 return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
667 case Hexagon::STrih_indexed_shl_cPt_V4:
668 return Hexagon::STrih_indexed_shl_cPt_nv_V4;
670 case Hexagon::STrih_indexed_shl_cdnPt_V4:
671 return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
673 case Hexagon::STrih_indexed_shl_cNotPt_V4:
674 return Hexagon::STrih_indexed_shl_cNotPt_nv_V4;
676 case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
677 return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
679 case Hexagon::POST_SThri_cPt:
680 return Hexagon::POST_SThri_cPt_nv_V4;
682 case Hexagon::POST_SThri_cdnPt_V4:
683 return Hexagon::POST_SThri_cdnPt_nv_V4;
685 case Hexagon::POST_SThri_cNotPt:
686 return Hexagon::POST_SThri_cNotPt_nv_V4;
688 case Hexagon::POST_SThri_cdnNotPt_V4:
689 return Hexagon::POST_SThri_cdnNotPt_nv_V4;
691 case Hexagon::STh_GP_cPt_V4:
692 return Hexagon::STh_GP_cPt_nv_V4;
694 case Hexagon::STh_GP_cNotPt_V4:
695 return Hexagon::STh_GP_cNotPt_nv_V4;
697 case Hexagon::STh_GP_cdnPt_V4:
698 return Hexagon::STh_GP_cdnPt_nv_V4;
700 case Hexagon::STh_GP_cdnNotPt_V4:
701 return Hexagon::STh_GP_cdnNotPt_nv_V4;
703 case Hexagon::STrih_GP_cPt_V4:
704 return Hexagon::STrih_GP_cPt_nv_V4;
706 case Hexagon::STrih_GP_cNotPt_V4:
707 return Hexagon::STrih_GP_cNotPt_nv_V4;
709 case Hexagon::STrih_GP_cdnPt_V4:
710 return Hexagon::STrih_GP_cdnPt_nv_V4;
712 case Hexagon::STrih_GP_cdnNotPt_V4:
713 return Hexagon::STrih_GP_cdnNotPt_nv_V4;
715 // store new value word
717 return Hexagon::STriw_nv_V4;
719 case Hexagon::STriw_indexed:
720 return Hexagon::STriw_indexed_nv_V4;
722 case Hexagon::STriw_indexed_shl_V4:
723 return Hexagon::STriw_indexed_shl_nv_V4;
725 case Hexagon::STriw_shl_V4:
726 return Hexagon::STriw_shl_nv_V4;
728 case Hexagon::STriw_GP_V4:
729 return Hexagon::STriw_GP_nv_V4;
731 case Hexagon::STw_GP_V4:
732 return Hexagon::STw_GP_nv_V4;
734 case Hexagon::POST_STwri:
735 return Hexagon::POST_STwri_nv_V4;
737 case Hexagon::STriw_cPt:
738 return Hexagon::STriw_cPt_nv_V4;
740 case Hexagon::STriw_cdnPt_V4:
741 return Hexagon::STriw_cdnPt_nv_V4;
743 case Hexagon::STriw_cNotPt:
744 return Hexagon::STriw_cNotPt_nv_V4;
746 case Hexagon::STriw_cdnNotPt_V4:
747 return Hexagon::STriw_cdnNotPt_nv_V4;
749 case Hexagon::STriw_indexed_cPt:
750 return Hexagon::STriw_indexed_cPt_nv_V4;
752 case Hexagon::STriw_indexed_cdnPt_V4:
753 return Hexagon::STriw_indexed_cdnPt_nv_V4;
755 case Hexagon::STriw_indexed_cNotPt:
756 return Hexagon::STriw_indexed_cNotPt_nv_V4;
758 case Hexagon::STriw_indexed_cdnNotPt_V4:
759 return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
761 case Hexagon::STriw_indexed_shl_cPt_V4:
762 return Hexagon::STriw_indexed_shl_cPt_nv_V4;
764 case Hexagon::STriw_indexed_shl_cdnPt_V4:
765 return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
767 case Hexagon::STriw_indexed_shl_cNotPt_V4:
768 return Hexagon::STriw_indexed_shl_cNotPt_nv_V4;
770 case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
771 return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
773 case Hexagon::POST_STwri_cPt:
774 return Hexagon::POST_STwri_cPt_nv_V4;
776 case Hexagon::POST_STwri_cdnPt_V4:
777 return Hexagon::POST_STwri_cdnPt_nv_V4;
779 case Hexagon::POST_STwri_cNotPt:
780 return Hexagon::POST_STwri_cNotPt_nv_V4;
782 case Hexagon::POST_STwri_cdnNotPt_V4:
783 return Hexagon::POST_STwri_cdnNotPt_nv_V4;
785 // Absolute addressing mode -- global address
786 case Hexagon::STrib_abs_V4:
787 return Hexagon::STrib_abs_nv_V4;
789 case Hexagon::STrib_abs_cPt_V4:
790 return Hexagon::STrib_abs_cPt_nv_V4;
792 case Hexagon::STrib_abs_cdnPt_V4:
793 return Hexagon::STrib_abs_cdnPt_nv_V4;
795 case Hexagon::STrib_abs_cNotPt_V4:
796 return Hexagon::STrib_abs_cNotPt_nv_V4;
798 case Hexagon::STrib_abs_cdnNotPt_V4:
799 return Hexagon::STrib_abs_cdnNotPt_nv_V4;
801 case Hexagon::STrih_abs_V4:
802 return Hexagon::STrih_abs_nv_V4;
804 case Hexagon::STrih_abs_cPt_V4:
805 return Hexagon::STrih_abs_cPt_nv_V4;
807 case Hexagon::STrih_abs_cdnPt_V4:
808 return Hexagon::STrih_abs_cdnPt_nv_V4;
810 case Hexagon::STrih_abs_cNotPt_V4:
811 return Hexagon::STrih_abs_cNotPt_nv_V4;
813 case Hexagon::STrih_abs_cdnNotPt_V4:
814 return Hexagon::STrih_abs_cdnNotPt_nv_V4;
816 case Hexagon::STriw_abs_V4:
817 return Hexagon::STriw_abs_nv_V4;
819 case Hexagon::STriw_abs_cPt_V4:
820 return Hexagon::STriw_abs_cPt_nv_V4;
822 case Hexagon::STriw_abs_cdnPt_V4:
823 return Hexagon::STriw_abs_cdnPt_nv_V4;
825 case Hexagon::STriw_abs_cNotPt_V4:
826 return Hexagon::STriw_abs_cNotPt_nv_V4;
828 case Hexagon::STriw_abs_cdnNotPt_V4:
829 return Hexagon::STriw_abs_cdnNotPt_nv_V4;
831 // Absolute addressing mode -- immediate value
832 case Hexagon::STrib_imm_abs_V4:
833 return Hexagon::STrib_imm_abs_nv_V4;
835 case Hexagon::STrib_imm_abs_cPt_V4:
836 return Hexagon::STrib_imm_abs_cPt_nv_V4;
838 case Hexagon::STrib_imm_abs_cdnPt_V4:
839 return Hexagon::STrib_imm_abs_cdnPt_nv_V4;
841 case Hexagon::STrib_imm_abs_cNotPt_V4:
842 return Hexagon::STrib_imm_abs_cNotPt_nv_V4;
844 case Hexagon::STrib_imm_abs_cdnNotPt_V4:
845 return Hexagon::STrib_imm_abs_cdnNotPt_nv_V4;
847 case Hexagon::STrih_imm_abs_V4:
848 return Hexagon::STrih_imm_abs_nv_V4;
850 case Hexagon::STrih_imm_abs_cPt_V4:
851 return Hexagon::STrih_imm_abs_cPt_nv_V4;
853 case Hexagon::STrih_imm_abs_cdnPt_V4:
854 return Hexagon::STrih_imm_abs_cdnPt_nv_V4;
856 case Hexagon::STrih_imm_abs_cNotPt_V4:
857 return Hexagon::STrih_imm_abs_cNotPt_nv_V4;
859 case Hexagon::STrih_imm_abs_cdnNotPt_V4:
860 return Hexagon::STrih_imm_abs_cdnNotPt_nv_V4;
862 case Hexagon::STriw_imm_abs_V4:
863 return Hexagon::STriw_imm_abs_nv_V4;
865 case Hexagon::STriw_imm_abs_cPt_V4:
866 return Hexagon::STriw_imm_abs_cPt_nv_V4;
868 case Hexagon::STriw_imm_abs_cdnPt_V4:
869 return Hexagon::STriw_imm_abs_cdnPt_nv_V4;
871 case Hexagon::STriw_imm_abs_cNotPt_V4:
872 return Hexagon::STriw_imm_abs_cNotPt_nv_V4;
874 case Hexagon::STriw_imm_abs_cdnNotPt_V4:
875 return Hexagon::STriw_imm_abs_cdnNotPt_nv_V4;
877 case Hexagon::STw_GP_cPt_V4:
878 return Hexagon::STw_GP_cPt_nv_V4;
880 case Hexagon::STw_GP_cNotPt_V4:
881 return Hexagon::STw_GP_cNotPt_nv_V4;
883 case Hexagon::STw_GP_cdnPt_V4:
884 return Hexagon::STw_GP_cdnPt_nv_V4;
886 case Hexagon::STw_GP_cdnNotPt_V4:
887 return Hexagon::STw_GP_cdnNotPt_nv_V4;
889 case Hexagon::STriw_GP_cPt_V4:
890 return Hexagon::STriw_GP_cPt_nv_V4;
892 case Hexagon::STriw_GP_cNotPt_V4:
893 return Hexagon::STriw_GP_cNotPt_nv_V4;
895 case Hexagon::STriw_GP_cdnPt_V4:
896 return Hexagon::STriw_GP_cdnPt_nv_V4;
898 case Hexagon::STriw_GP_cdnNotPt_V4:
899 return Hexagon::STriw_GP_cdnNotPt_nv_V4;
903 // Return .new predicate version for an instruction
904 static int GetDotNewPredOp(const int opc) {
906 default: llvm_unreachable("Unknown .new type");
907 // Conditional stores
908 // Store byte conditionally
909 case Hexagon::STrib_cPt :
910 return Hexagon::STrib_cdnPt_V4;
912 case Hexagon::STrib_cNotPt :
913 return Hexagon::STrib_cdnNotPt_V4;
915 case Hexagon::STrib_indexed_cPt :
916 return Hexagon::STrib_indexed_cdnPt_V4;
918 case Hexagon::STrib_indexed_cNotPt :
919 return Hexagon::STrib_indexed_cdnNotPt_V4;
921 case Hexagon::STrib_imm_cPt_V4 :
922 return Hexagon::STrib_imm_cdnPt_V4;
924 case Hexagon::STrib_imm_cNotPt_V4 :
925 return Hexagon::STrib_imm_cdnNotPt_V4;
927 case Hexagon::POST_STbri_cPt :
928 return Hexagon::POST_STbri_cdnPt_V4;
930 case Hexagon::POST_STbri_cNotPt :
931 return Hexagon::POST_STbri_cdnNotPt_V4;
933 case Hexagon::STrib_indexed_shl_cPt_V4 :
934 return Hexagon::STrib_indexed_shl_cdnPt_V4;
936 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
937 return Hexagon::STrib_indexed_shl_cdnNotPt_V4;
939 case Hexagon::STb_GP_cPt_V4 :
940 return Hexagon::STb_GP_cdnPt_V4;
942 case Hexagon::STb_GP_cNotPt_V4 :
943 return Hexagon::STb_GP_cdnNotPt_V4;
945 case Hexagon::STrib_GP_cPt_V4 :
946 return Hexagon::STrib_GP_cdnPt_V4;
948 case Hexagon::STrib_GP_cNotPt_V4 :
949 return Hexagon::STrib_GP_cdnNotPt_V4;
951 // Store doubleword conditionally
952 case Hexagon::STrid_cPt :
953 return Hexagon::STrid_cdnPt_V4;
955 case Hexagon::STrid_cNotPt :
956 return Hexagon::STrid_cdnNotPt_V4;
958 case Hexagon::STrid_indexed_cPt :
959 return Hexagon::STrid_indexed_cdnPt_V4;
961 case Hexagon::STrid_indexed_cNotPt :
962 return Hexagon::STrid_indexed_cdnNotPt_V4;
964 case Hexagon::STrid_indexed_shl_cPt_V4 :
965 return Hexagon::STrid_indexed_shl_cdnPt_V4;
967 case Hexagon::STrid_indexed_shl_cNotPt_V4 :
968 return Hexagon::STrid_indexed_shl_cdnNotPt_V4;
970 case Hexagon::POST_STdri_cPt :
971 return Hexagon::POST_STdri_cdnPt_V4;
973 case Hexagon::POST_STdri_cNotPt :
974 return Hexagon::POST_STdri_cdnNotPt_V4;
976 case Hexagon::STd_GP_cPt_V4 :
977 return Hexagon::STd_GP_cdnPt_V4;
979 case Hexagon::STd_GP_cNotPt_V4 :
980 return Hexagon::STd_GP_cdnNotPt_V4;
982 case Hexagon::STrid_GP_cPt_V4 :
983 return Hexagon::STrid_GP_cdnPt_V4;
985 case Hexagon::STrid_GP_cNotPt_V4 :
986 return Hexagon::STrid_GP_cdnNotPt_V4;
988 // Store halfword conditionally
989 case Hexagon::STrih_cPt :
990 return Hexagon::STrih_cdnPt_V4;
992 case Hexagon::STrih_cNotPt :
993 return Hexagon::STrih_cdnNotPt_V4;
995 case Hexagon::STrih_indexed_cPt :
996 return Hexagon::STrih_indexed_cdnPt_V4;
998 case Hexagon::STrih_indexed_cNotPt :
999 return Hexagon::STrih_indexed_cdnNotPt_V4;
1001 case Hexagon::STrih_imm_cPt_V4 :
1002 return Hexagon::STrih_imm_cdnPt_V4;
1004 case Hexagon::STrih_imm_cNotPt_V4 :
1005 return Hexagon::STrih_imm_cdnNotPt_V4;
1007 case Hexagon::STrih_indexed_shl_cPt_V4 :
1008 return Hexagon::STrih_indexed_shl_cdnPt_V4;
1010 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
1011 return Hexagon::STrih_indexed_shl_cdnNotPt_V4;
1013 case Hexagon::POST_SThri_cPt :
1014 return Hexagon::POST_SThri_cdnPt_V4;
1016 case Hexagon::POST_SThri_cNotPt :
1017 return Hexagon::POST_SThri_cdnNotPt_V4;
1019 case Hexagon::STh_GP_cPt_V4 :
1020 return Hexagon::STh_GP_cdnPt_V4;
1022 case Hexagon::STh_GP_cNotPt_V4 :
1023 return Hexagon::STh_GP_cdnNotPt_V4;
1025 case Hexagon::STrih_GP_cPt_V4 :
1026 return Hexagon::STrih_GP_cdnPt_V4;
1028 case Hexagon::STrih_GP_cNotPt_V4 :
1029 return Hexagon::STrih_GP_cdnNotPt_V4;
1031 // Store word conditionally
1032 case Hexagon::STriw_cPt :
1033 return Hexagon::STriw_cdnPt_V4;
1035 case Hexagon::STriw_cNotPt :
1036 return Hexagon::STriw_cdnNotPt_V4;
1038 case Hexagon::STriw_indexed_cPt :
1039 return Hexagon::STriw_indexed_cdnPt_V4;
1041 case Hexagon::STriw_indexed_cNotPt :
1042 return Hexagon::STriw_indexed_cdnNotPt_V4;
1044 case Hexagon::STriw_imm_cPt_V4 :
1045 return Hexagon::STriw_imm_cdnPt_V4;
1047 case Hexagon::STriw_imm_cNotPt_V4 :
1048 return Hexagon::STriw_imm_cdnNotPt_V4;
1050 case Hexagon::STriw_indexed_shl_cPt_V4 :
1051 return Hexagon::STriw_indexed_shl_cdnPt_V4;
1053 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
1054 return Hexagon::STriw_indexed_shl_cdnNotPt_V4;
1056 case Hexagon::POST_STwri_cPt :
1057 return Hexagon::POST_STwri_cdnPt_V4;
1059 case Hexagon::POST_STwri_cNotPt :
1060 return Hexagon::POST_STwri_cdnNotPt_V4;
1062 case Hexagon::STw_GP_cPt_V4 :
1063 return Hexagon::STw_GP_cdnPt_V4;
1065 case Hexagon::STw_GP_cNotPt_V4 :
1066 return Hexagon::STw_GP_cdnNotPt_V4;
1068 case Hexagon::STriw_GP_cPt_V4 :
1069 return Hexagon::STriw_GP_cdnPt_V4;
1071 case Hexagon::STriw_GP_cNotPt_V4 :
1072 return Hexagon::STriw_GP_cdnNotPt_V4;
1075 case Hexagon::JMP_c:
1076 return Hexagon::JMP_cdnPt;
1078 case Hexagon::JMP_cNot:
1079 return Hexagon::JMP_cdnNotPt;
1081 case Hexagon::JMPR_cPt:
1082 return Hexagon::JMPR_cdnPt_V3;
1084 case Hexagon::JMPR_cNotPt:
1085 return Hexagon::JMPR_cdnNotPt_V3;
1087 // Conditional Transfers
1088 case Hexagon::TFR_cPt:
1089 return Hexagon::TFR_cdnPt;
1091 case Hexagon::TFR_cNotPt:
1092 return Hexagon::TFR_cdnNotPt;
1094 case Hexagon::TFRI_cPt:
1095 return Hexagon::TFRI_cdnPt;
1097 case Hexagon::TFRI_cNotPt:
1098 return Hexagon::TFRI_cdnNotPt;
1101 case Hexagon::LDrid_cPt :
1102 return Hexagon::LDrid_cdnPt;
1104 case Hexagon::LDrid_cNotPt :
1105 return Hexagon::LDrid_cdnNotPt;
1107 case Hexagon::LDrid_indexed_cPt :
1108 return Hexagon::LDrid_indexed_cdnPt;
1110 case Hexagon::LDrid_indexed_cNotPt :
1111 return Hexagon::LDrid_indexed_cdnNotPt;
1113 case Hexagon::POST_LDrid_cPt :
1114 return Hexagon::POST_LDrid_cdnPt_V4;
1116 case Hexagon::POST_LDrid_cNotPt :
1117 return Hexagon::POST_LDrid_cdnNotPt_V4;
1120 case Hexagon::LDriw_cPt :
1121 return Hexagon::LDriw_cdnPt;
1123 case Hexagon::LDriw_cNotPt :
1124 return Hexagon::LDriw_cdnNotPt;
1126 case Hexagon::LDriw_indexed_cPt :
1127 return Hexagon::LDriw_indexed_cdnPt;
1129 case Hexagon::LDriw_indexed_cNotPt :
1130 return Hexagon::LDriw_indexed_cdnNotPt;
1132 case Hexagon::POST_LDriw_cPt :
1133 return Hexagon::POST_LDriw_cdnPt_V4;
1135 case Hexagon::POST_LDriw_cNotPt :
1136 return Hexagon::POST_LDriw_cdnNotPt_V4;
1139 case Hexagon::LDrih_cPt :
1140 return Hexagon::LDrih_cdnPt;
1142 case Hexagon::LDrih_cNotPt :
1143 return Hexagon::LDrih_cdnNotPt;
1145 case Hexagon::LDrih_indexed_cPt :
1146 return Hexagon::LDrih_indexed_cdnPt;
1148 case Hexagon::LDrih_indexed_cNotPt :
1149 return Hexagon::LDrih_indexed_cdnNotPt;
1151 case Hexagon::POST_LDrih_cPt :
1152 return Hexagon::POST_LDrih_cdnPt_V4;
1154 case Hexagon::POST_LDrih_cNotPt :
1155 return Hexagon::POST_LDrih_cdnNotPt_V4;
1158 case Hexagon::LDrib_cPt :
1159 return Hexagon::LDrib_cdnPt;
1161 case Hexagon::LDrib_cNotPt :
1162 return Hexagon::LDrib_cdnNotPt;
1164 case Hexagon::LDrib_indexed_cPt :
1165 return Hexagon::LDrib_indexed_cdnPt;
1167 case Hexagon::LDrib_indexed_cNotPt :
1168 return Hexagon::LDrib_indexed_cdnNotPt;
1170 case Hexagon::POST_LDrib_cPt :
1171 return Hexagon::POST_LDrib_cdnPt_V4;
1173 case Hexagon::POST_LDrib_cNotPt :
1174 return Hexagon::POST_LDrib_cdnNotPt_V4;
1176 // Load unsigned halfword
1177 case Hexagon::LDriuh_cPt :
1178 return Hexagon::LDriuh_cdnPt;
1180 case Hexagon::LDriuh_cNotPt :
1181 return Hexagon::LDriuh_cdnNotPt;
1183 case Hexagon::LDriuh_indexed_cPt :
1184 return Hexagon::LDriuh_indexed_cdnPt;
1186 case Hexagon::LDriuh_indexed_cNotPt :
1187 return Hexagon::LDriuh_indexed_cdnNotPt;
1189 case Hexagon::POST_LDriuh_cPt :
1190 return Hexagon::POST_LDriuh_cdnPt_V4;
1192 case Hexagon::POST_LDriuh_cNotPt :
1193 return Hexagon::POST_LDriuh_cdnNotPt_V4;
1195 // Load unsigned byte
1196 case Hexagon::LDriub_cPt :
1197 return Hexagon::LDriub_cdnPt;
1199 case Hexagon::LDriub_cNotPt :
1200 return Hexagon::LDriub_cdnNotPt;
1202 case Hexagon::LDriub_indexed_cPt :
1203 return Hexagon::LDriub_indexed_cdnPt;
1205 case Hexagon::LDriub_indexed_cNotPt :
1206 return Hexagon::LDriub_indexed_cdnNotPt;
1208 case Hexagon::POST_LDriub_cPt :
1209 return Hexagon::POST_LDriub_cdnPt_V4;
1211 case Hexagon::POST_LDriub_cNotPt :
1212 return Hexagon::POST_LDriub_cdnNotPt_V4;
1214 // V4 indexed+scaled load
1216 case Hexagon::LDrid_indexed_cPt_V4 :
1217 return Hexagon::LDrid_indexed_cdnPt_V4;
1219 case Hexagon::LDrid_indexed_cNotPt_V4 :
1220 return Hexagon::LDrid_indexed_cdnNotPt_V4;
1222 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1223 return Hexagon::LDrid_indexed_shl_cdnPt_V4;
1225 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1226 return Hexagon::LDrid_indexed_shl_cdnNotPt_V4;
1228 case Hexagon::LDrib_indexed_cPt_V4 :
1229 return Hexagon::LDrib_indexed_cdnPt_V4;
1231 case Hexagon::LDrib_indexed_cNotPt_V4 :
1232 return Hexagon::LDrib_indexed_cdnNotPt_V4;
1234 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1235 return Hexagon::LDrib_indexed_shl_cdnPt_V4;
1237 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1238 return Hexagon::LDrib_indexed_shl_cdnNotPt_V4;
1240 case Hexagon::LDriub_indexed_cPt_V4 :
1241 return Hexagon::LDriub_indexed_cdnPt_V4;
1243 case Hexagon::LDriub_indexed_cNotPt_V4 :
1244 return Hexagon::LDriub_indexed_cdnNotPt_V4;
1246 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1247 return Hexagon::LDriub_indexed_shl_cdnPt_V4;
1249 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1250 return Hexagon::LDriub_indexed_shl_cdnNotPt_V4;
1252 case Hexagon::LDrih_indexed_cPt_V4 :
1253 return Hexagon::LDrih_indexed_cdnPt_V4;
1255 case Hexagon::LDrih_indexed_cNotPt_V4 :
1256 return Hexagon::LDrih_indexed_cdnNotPt_V4;
1258 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1259 return Hexagon::LDrih_indexed_shl_cdnPt_V4;
1261 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1262 return Hexagon::LDrih_indexed_shl_cdnNotPt_V4;
1264 case Hexagon::LDriuh_indexed_cPt_V4 :
1265 return Hexagon::LDriuh_indexed_cdnPt_V4;
1267 case Hexagon::LDriuh_indexed_cNotPt_V4 :
1268 return Hexagon::LDriuh_indexed_cdnNotPt_V4;
1270 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1271 return Hexagon::LDriuh_indexed_shl_cdnPt_V4;
1273 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1274 return Hexagon::LDriuh_indexed_shl_cdnNotPt_V4;
1276 case Hexagon::LDriw_indexed_cPt_V4 :
1277 return Hexagon::LDriw_indexed_cdnPt_V4;
1279 case Hexagon::LDriw_indexed_cNotPt_V4 :
1280 return Hexagon::LDriw_indexed_cdnNotPt_V4;
1282 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1283 return Hexagon::LDriw_indexed_shl_cdnPt_V4;
1285 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1286 return Hexagon::LDriw_indexed_shl_cdnNotPt_V4;
1288 // V4 global address load
1290 case Hexagon::LDd_GP_cPt_V4:
1291 return Hexagon::LDd_GP_cdnPt_V4;
1293 case Hexagon::LDd_GP_cNotPt_V4:
1294 return Hexagon::LDd_GP_cdnNotPt_V4;
1296 case Hexagon::LDb_GP_cPt_V4:
1297 return Hexagon::LDb_GP_cdnPt_V4;
1299 case Hexagon::LDb_GP_cNotPt_V4:
1300 return Hexagon::LDb_GP_cdnNotPt_V4;
1302 case Hexagon::LDub_GP_cPt_V4:
1303 return Hexagon::LDub_GP_cdnPt_V4;
1305 case Hexagon::LDub_GP_cNotPt_V4:
1306 return Hexagon::LDub_GP_cdnNotPt_V4;
1308 case Hexagon::LDh_GP_cPt_V4:
1309 return Hexagon::LDh_GP_cdnPt_V4;
1311 case Hexagon::LDh_GP_cNotPt_V4:
1312 return Hexagon::LDh_GP_cdnNotPt_V4;
1314 case Hexagon::LDuh_GP_cPt_V4:
1315 return Hexagon::LDuh_GP_cdnPt_V4;
1317 case Hexagon::LDuh_GP_cNotPt_V4:
1318 return Hexagon::LDuh_GP_cdnNotPt_V4;
1320 case Hexagon::LDw_GP_cPt_V4:
1321 return Hexagon::LDw_GP_cdnPt_V4;
1323 case Hexagon::LDw_GP_cNotPt_V4:
1324 return Hexagon::LDw_GP_cdnNotPt_V4;
1326 case Hexagon::LDrid_GP_cPt_V4:
1327 return Hexagon::LDrid_GP_cdnPt_V4;
1329 case Hexagon::LDrid_GP_cNotPt_V4:
1330 return Hexagon::LDrid_GP_cdnNotPt_V4;
1332 case Hexagon::LDrib_GP_cPt_V4:
1333 return Hexagon::LDrib_GP_cdnPt_V4;
1335 case Hexagon::LDrib_GP_cNotPt_V4:
1336 return Hexagon::LDrib_GP_cdnNotPt_V4;
1338 case Hexagon::LDriub_GP_cPt_V4:
1339 return Hexagon::LDriub_GP_cdnPt_V4;
1341 case Hexagon::LDriub_GP_cNotPt_V4:
1342 return Hexagon::LDriub_GP_cdnNotPt_V4;
1344 case Hexagon::LDrih_GP_cPt_V4:
1345 return Hexagon::LDrih_GP_cdnPt_V4;
1347 case Hexagon::LDrih_GP_cNotPt_V4:
1348 return Hexagon::LDrih_GP_cdnNotPt_V4;
1350 case Hexagon::LDriuh_GP_cPt_V4:
1351 return Hexagon::LDriuh_GP_cdnPt_V4;
1353 case Hexagon::LDriuh_GP_cNotPt_V4:
1354 return Hexagon::LDriuh_GP_cdnNotPt_V4;
1356 case Hexagon::LDriw_GP_cPt_V4:
1357 return Hexagon::LDriw_GP_cdnPt_V4;
1359 case Hexagon::LDriw_GP_cNotPt_V4:
1360 return Hexagon::LDriw_GP_cdnNotPt_V4;
1362 // Conditional store new-value byte
1363 case Hexagon::STrib_cPt_nv_V4 :
1364 return Hexagon::STrib_cdnPt_nv_V4;
1365 case Hexagon::STrib_cNotPt_nv_V4 :
1366 return Hexagon::STrib_cdnNotPt_nv_V4;
1368 case Hexagon::STrib_indexed_cPt_nv_V4 :
1369 return Hexagon::STrib_indexed_cdnPt_nv_V4;
1370 case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1371 return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
1373 case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1374 return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
1375 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1376 return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
1378 case Hexagon::POST_STbri_cPt_nv_V4 :
1379 return Hexagon::POST_STbri_cdnPt_nv_V4;
1380 case Hexagon::POST_STbri_cNotPt_nv_V4 :
1381 return Hexagon::POST_STbri_cdnNotPt_nv_V4;
1383 case Hexagon::STb_GP_cPt_nv_V4 :
1384 return Hexagon::STb_GP_cdnPt_nv_V4;
1386 case Hexagon::STb_GP_cNotPt_nv_V4 :
1387 return Hexagon::STb_GP_cdnNotPt_nv_V4;
1389 case Hexagon::STrib_GP_cPt_nv_V4 :
1390 return Hexagon::STrib_GP_cdnPt_nv_V4;
1392 case Hexagon::STrib_GP_cNotPt_nv_V4 :
1393 return Hexagon::STrib_GP_cdnNotPt_nv_V4;
1395 // Conditional store new-value halfword
1396 case Hexagon::STrih_cPt_nv_V4 :
1397 return Hexagon::STrih_cdnPt_nv_V4;
1398 case Hexagon::STrih_cNotPt_nv_V4 :
1399 return Hexagon::STrih_cdnNotPt_nv_V4;
1401 case Hexagon::STrih_indexed_cPt_nv_V4 :
1402 return Hexagon::STrih_indexed_cdnPt_nv_V4;
1403 case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1404 return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
1406 case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1407 return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
1408 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1409 return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
1411 case Hexagon::POST_SThri_cPt_nv_V4 :
1412 return Hexagon::POST_SThri_cdnPt_nv_V4;
1413 case Hexagon::POST_SThri_cNotPt_nv_V4 :
1414 return Hexagon::POST_SThri_cdnNotPt_nv_V4;
1416 case Hexagon::STh_GP_cPt_nv_V4 :
1417 return Hexagon::STh_GP_cdnPt_nv_V4;
1419 case Hexagon::STh_GP_cNotPt_nv_V4 :
1420 return Hexagon::STh_GP_cdnNotPt_nv_V4;
1422 case Hexagon::STrih_GP_cPt_nv_V4 :
1423 return Hexagon::STrih_GP_cdnPt_nv_V4;
1425 case Hexagon::STrih_GP_cNotPt_nv_V4 :
1426 return Hexagon::STrih_GP_cdnNotPt_nv_V4;
1428 // Conditional store new-value word
1429 case Hexagon::STriw_cPt_nv_V4 :
1430 return Hexagon::STriw_cdnPt_nv_V4;
1431 case Hexagon::STriw_cNotPt_nv_V4 :
1432 return Hexagon::STriw_cdnNotPt_nv_V4;
1434 case Hexagon::STriw_indexed_cPt_nv_V4 :
1435 return Hexagon::STriw_indexed_cdnPt_nv_V4;
1436 case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1437 return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
1439 case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1440 return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
1441 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1442 return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
1444 case Hexagon::POST_STwri_cPt_nv_V4 :
1445 return Hexagon::POST_STwri_cdnPt_nv_V4;
1446 case Hexagon::POST_STwri_cNotPt_nv_V4:
1447 return Hexagon::POST_STwri_cdnNotPt_nv_V4;
1449 case Hexagon::STw_GP_cPt_nv_V4 :
1450 return Hexagon::STw_GP_cdnPt_nv_V4;
1452 case Hexagon::STw_GP_cNotPt_nv_V4 :
1453 return Hexagon::STw_GP_cdnNotPt_nv_V4;
1455 case Hexagon::STriw_GP_cPt_nv_V4 :
1456 return Hexagon::STriw_GP_cdnPt_nv_V4;
1458 case Hexagon::STriw_GP_cNotPt_nv_V4 :
1459 return Hexagon::STriw_GP_cdnNotPt_nv_V4;
1462 case Hexagon::ADD_ri_cPt :
1463 return Hexagon::ADD_ri_cdnPt;
1464 case Hexagon::ADD_ri_cNotPt :
1465 return Hexagon::ADD_ri_cdnNotPt;
1467 case Hexagon::ADD_rr_cPt :
1468 return Hexagon::ADD_rr_cdnPt;
1469 case Hexagon::ADD_rr_cNotPt :
1470 return Hexagon::ADD_rr_cdnNotPt;
1472 // Conditional logical Operations
1473 case Hexagon::XOR_rr_cPt :
1474 return Hexagon::XOR_rr_cdnPt;
1475 case Hexagon::XOR_rr_cNotPt :
1476 return Hexagon::XOR_rr_cdnNotPt;
1478 case Hexagon::AND_rr_cPt :
1479 return Hexagon::AND_rr_cdnPt;
1480 case Hexagon::AND_rr_cNotPt :
1481 return Hexagon::AND_rr_cdnNotPt;
1483 case Hexagon::OR_rr_cPt :
1484 return Hexagon::OR_rr_cdnPt;
1485 case Hexagon::OR_rr_cNotPt :
1486 return Hexagon::OR_rr_cdnNotPt;
1488 // Conditional Subtract
1489 case Hexagon::SUB_rr_cPt :
1490 return Hexagon::SUB_rr_cdnPt;
1491 case Hexagon::SUB_rr_cNotPt :
1492 return Hexagon::SUB_rr_cdnNotPt;
1494 // Conditional combine
1495 case Hexagon::COMBINE_rr_cPt :
1496 return Hexagon::COMBINE_rr_cdnPt;
1497 case Hexagon::COMBINE_rr_cNotPt :
1498 return Hexagon::COMBINE_rr_cdnNotPt;
1500 case Hexagon::ASLH_cPt_V4 :
1501 return Hexagon::ASLH_cdnPt_V4;
1502 case Hexagon::ASLH_cNotPt_V4 :
1503 return Hexagon::ASLH_cdnNotPt_V4;
1505 case Hexagon::ASRH_cPt_V4 :
1506 return Hexagon::ASRH_cdnPt_V4;
1507 case Hexagon::ASRH_cNotPt_V4 :
1508 return Hexagon::ASRH_cdnNotPt_V4;
1510 case Hexagon::SXTB_cPt_V4 :
1511 return Hexagon::SXTB_cdnPt_V4;
1512 case Hexagon::SXTB_cNotPt_V4 :
1513 return Hexagon::SXTB_cdnNotPt_V4;
1515 case Hexagon::SXTH_cPt_V4 :
1516 return Hexagon::SXTH_cdnPt_V4;
1517 case Hexagon::SXTH_cNotPt_V4 :
1518 return Hexagon::SXTH_cdnNotPt_V4;
1520 case Hexagon::ZXTB_cPt_V4 :
1521 return Hexagon::ZXTB_cdnPt_V4;
1522 case Hexagon::ZXTB_cNotPt_V4 :
1523 return Hexagon::ZXTB_cdnNotPt_V4;
1525 case Hexagon::ZXTH_cPt_V4 :
1526 return Hexagon::ZXTH_cdnPt_V4;
1527 case Hexagon::ZXTH_cNotPt_V4 :
1528 return Hexagon::ZXTH_cdnNotPt_V4;
1530 // Load Absolute Addressing.
1531 case Hexagon::LDrib_abs_cPt_V4 :
1532 return Hexagon::LDrib_abs_cdnPt_V4;
1533 case Hexagon::LDrib_abs_cNotPt_V4 :
1534 return Hexagon::LDrib_abs_cdnNotPt_V4;
1536 case Hexagon::LDriub_abs_cPt_V4 :
1537 return Hexagon::LDriub_abs_cdnPt_V4;
1538 case Hexagon::LDriub_abs_cNotPt_V4 :
1539 return Hexagon::LDriub_abs_cdnNotPt_V4;
1541 case Hexagon::LDrih_abs_cPt_V4 :
1542 return Hexagon::LDrih_abs_cdnPt_V4;
1543 case Hexagon::LDrih_abs_cNotPt_V4 :
1544 return Hexagon::LDrih_abs_cdnNotPt_V4;
1546 case Hexagon::LDriuh_abs_cPt_V4 :
1547 return Hexagon::LDriuh_abs_cdnPt_V4;
1548 case Hexagon::LDriuh_abs_cNotPt_V4 :
1549 return Hexagon::LDriuh_abs_cdnNotPt_V4;
1551 case Hexagon::LDriw_abs_cPt_V4 :
1552 return Hexagon::LDriw_abs_cdnPt_V4;
1553 case Hexagon::LDriw_abs_cNotPt_V4 :
1554 return Hexagon::LDriw_abs_cdnNotPt_V4;
1556 case Hexagon::LDrid_abs_cPt_V4 :
1557 return Hexagon::LDrid_abs_cdnPt_V4;
1558 case Hexagon::LDrid_abs_cNotPt_V4 :
1559 return Hexagon::LDrid_abs_cdnNotPt_V4;
1561 case Hexagon::LDrib_imm_abs_cPt_V4:
1562 return Hexagon::LDrib_imm_abs_cdnPt_V4;
1563 case Hexagon::LDrib_imm_abs_cNotPt_V4:
1564 return Hexagon::LDrib_imm_abs_cdnNotPt_V4;
1566 case Hexagon::LDriub_imm_abs_cPt_V4:
1567 return Hexagon::LDriub_imm_abs_cdnPt_V4;
1568 case Hexagon::LDriub_imm_abs_cNotPt_V4:
1569 return Hexagon::LDriub_imm_abs_cdnNotPt_V4;
1571 case Hexagon::LDrih_imm_abs_cPt_V4:
1572 return Hexagon::LDrih_imm_abs_cdnPt_V4;
1573 case Hexagon::LDrih_imm_abs_cNotPt_V4:
1574 return Hexagon::LDrih_imm_abs_cdnNotPt_V4;
1576 case Hexagon::LDriuh_imm_abs_cPt_V4:
1577 return Hexagon::LDriuh_imm_abs_cdnPt_V4;
1578 case Hexagon::LDriuh_imm_abs_cNotPt_V4:
1579 return Hexagon::LDriuh_imm_abs_cdnNotPt_V4;
1581 case Hexagon::LDriw_imm_abs_cPt_V4:
1582 return Hexagon::LDriw_imm_abs_cdnPt_V4;
1583 case Hexagon::LDriw_imm_abs_cNotPt_V4:
1584 return Hexagon::LDriw_imm_abs_cdnNotPt_V4;
1586 // Store Absolute Addressing.
1587 case Hexagon::STrib_abs_cPt_V4 :
1588 return Hexagon::STrib_abs_cdnPt_V4;
1589 case Hexagon::STrib_abs_cNotPt_V4 :
1590 return Hexagon::STrib_abs_cdnNotPt_V4;
1592 case Hexagon::STrih_abs_cPt_V4 :
1593 return Hexagon::STrih_abs_cdnPt_V4;
1594 case Hexagon::STrih_abs_cNotPt_V4 :
1595 return Hexagon::STrih_abs_cdnNotPt_V4;
1597 case Hexagon::STriw_abs_cPt_V4 :
1598 return Hexagon::STriw_abs_cdnPt_V4;
1599 case Hexagon::STriw_abs_cNotPt_V4 :
1600 return Hexagon::STriw_abs_cdnNotPt_V4;
1602 case Hexagon::STrid_abs_cPt_V4 :
1603 return Hexagon::STrid_abs_cdnPt_V4;
1604 case Hexagon::STrid_abs_cNotPt_V4 :
1605 return Hexagon::STrid_abs_cdnNotPt_V4;
1607 case Hexagon::STrib_imm_abs_cPt_V4:
1608 return Hexagon::STrib_imm_abs_cdnPt_V4;
1609 case Hexagon::STrib_imm_abs_cNotPt_V4:
1610 return Hexagon::STrib_imm_abs_cdnNotPt_V4;
1612 case Hexagon::STrih_imm_abs_cPt_V4:
1613 return Hexagon::STrih_imm_abs_cdnPt_V4;
1614 case Hexagon::STrih_imm_abs_cNotPt_V4:
1615 return Hexagon::STrih_imm_abs_cdnNotPt_V4;
1617 case Hexagon::STriw_imm_abs_cPt_V4:
1618 return Hexagon::STriw_imm_abs_cdnPt_V4;
1619 case Hexagon::STriw_imm_abs_cNotPt_V4:
1620 return Hexagon::STriw_imm_abs_cdnNotPt_V4;
1622 case Hexagon::TFRI_cPt_V4:
1623 return Hexagon::TFRI_cdnPt_V4;
1624 case Hexagon::TFRI_cNotPt_V4:
1625 return Hexagon::TFRI_cdnNotPt_V4;
1629 // Returns true if an instruction can be promoted to .new predicate
1630 // or new-value store.
1631 bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
1632 if ( isCondInst(MI) || IsNewifyStore(MI))
1638 bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
1639 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1640 const MCInstrDesc& TID = MI->getDesc();
1641 // bug 5670: until that is fixed,
1642 // this portion is disabled.
1643 if ( TID.isConditionalBranch() // && !IsRegisterJump(MI)) ||
1644 || QII->isConditionalTransfer(MI)
1645 || QII->isConditionalALU32(MI)
1646 || QII->isConditionalLoad(MI)
1647 || QII->isConditionalStore(MI)) {
1653 // Promote an instructiont to its .new form.
1654 // At this time, we have already made a call to CanPromoteToDotNew
1655 // and made sure that it can *indeed* be promoted.
1656 bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
1657 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
1658 const TargetRegisterClass* RC) {
1660 assert (DepType == SDep::Data);
1661 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1664 if (RC == &Hexagon::PredRegsRegClass)
1665 NewOpcode = GetDotNewPredOp(MI->getOpcode());
1667 NewOpcode = GetDotNewOp(MI->getOpcode());
1668 MI->setDesc(QII->get(NewOpcode));
1673 // Returns the most basic instruction for the .new predicated instructions and
1674 // new-value stores.
1675 // For example, all of the following instructions will be converted back to the
1676 // same instruction:
1677 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1678 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1679 // 3) if (p0.new) memw(R0+#0) = R1 --->
1681 // To understand the translation of instruction 1 to its original form, consider
1682 // a packet with 3 instructions.
1683 // { p0 = cmp.eq(R0,R1)
1684 // if (p0.new) R2 = add(R3, R4)
1685 // R5 = add (R3, R1)
1687 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
1689 // This instruction can be part of the previous packet only if both p0 and R2
1690 // are promoted to .new values. This promotion happens in steps, first
1691 // predicate register is promoted to .new and in the next iteration R2 is
1692 // promoted. Therefore, in case of dependence check failure (due to R5) during
1693 // next iteration, it should be converted back to its most basic form.
1695 static int GetDotOldOp(const int opc) {
1697 default: llvm_unreachable("Unknown .old type");
1698 case Hexagon::TFR_cdnPt:
1699 return Hexagon::TFR_cPt;
1701 case Hexagon::TFR_cdnNotPt:
1702 return Hexagon::TFR_cNotPt;
1704 case Hexagon::TFRI_cdnPt:
1705 return Hexagon::TFRI_cPt;
1707 case Hexagon::TFRI_cdnNotPt:
1708 return Hexagon::TFRI_cNotPt;
1710 case Hexagon::JMP_cdnPt:
1711 return Hexagon::JMP_c;
1713 case Hexagon::JMP_cdnNotPt:
1714 return Hexagon::JMP_cNot;
1716 case Hexagon::JMPR_cdnPt_V3:
1717 return Hexagon::JMPR_cPt;
1719 case Hexagon::JMPR_cdnNotPt_V3:
1720 return Hexagon::JMPR_cNotPt;
1724 case Hexagon::LDrid_cdnPt :
1725 return Hexagon::LDrid_cPt;
1727 case Hexagon::LDrid_cdnNotPt :
1728 return Hexagon::LDrid_cNotPt;
1730 case Hexagon::LDrid_indexed_cdnPt :
1731 return Hexagon::LDrid_indexed_cPt;
1733 case Hexagon::LDrid_indexed_cdnNotPt :
1734 return Hexagon::LDrid_indexed_cNotPt;
1736 case Hexagon::POST_LDrid_cdnPt_V4 :
1737 return Hexagon::POST_LDrid_cPt;
1739 case Hexagon::POST_LDrid_cdnNotPt_V4 :
1740 return Hexagon::POST_LDrid_cNotPt;
1744 case Hexagon::LDriw_cdnPt :
1745 return Hexagon::LDriw_cPt;
1747 case Hexagon::LDriw_cdnNotPt :
1748 return Hexagon::LDriw_cNotPt;
1750 case Hexagon::LDriw_indexed_cdnPt :
1751 return Hexagon::LDriw_indexed_cPt;
1753 case Hexagon::LDriw_indexed_cdnNotPt :
1754 return Hexagon::LDriw_indexed_cNotPt;
1756 case Hexagon::POST_LDriw_cdnPt_V4 :
1757 return Hexagon::POST_LDriw_cPt;
1759 case Hexagon::POST_LDriw_cdnNotPt_V4 :
1760 return Hexagon::POST_LDriw_cNotPt;
1764 case Hexagon::LDrih_cdnPt :
1765 return Hexagon::LDrih_cPt;
1767 case Hexagon::LDrih_cdnNotPt :
1768 return Hexagon::LDrih_cNotPt;
1770 case Hexagon::LDrih_indexed_cdnPt :
1771 return Hexagon::LDrih_indexed_cPt;
1773 case Hexagon::LDrih_indexed_cdnNotPt :
1774 return Hexagon::LDrih_indexed_cNotPt;
1776 case Hexagon::POST_LDrih_cdnPt_V4 :
1777 return Hexagon::POST_LDrih_cPt;
1779 case Hexagon::POST_LDrih_cdnNotPt_V4 :
1780 return Hexagon::POST_LDrih_cNotPt;
1784 case Hexagon::LDrib_cdnPt :
1785 return Hexagon::LDrib_cPt;
1787 case Hexagon::LDrib_cdnNotPt :
1788 return Hexagon::LDrib_cNotPt;
1790 case Hexagon::LDrib_indexed_cdnPt :
1791 return Hexagon::LDrib_indexed_cPt;
1793 case Hexagon::LDrib_indexed_cdnNotPt :
1794 return Hexagon::LDrib_indexed_cNotPt;
1796 case Hexagon::POST_LDrib_cdnPt_V4 :
1797 return Hexagon::POST_LDrib_cPt;
1799 case Hexagon::POST_LDrib_cdnNotPt_V4 :
1800 return Hexagon::POST_LDrib_cNotPt;
1802 // Load unsigned half
1804 case Hexagon::LDriuh_cdnPt :
1805 return Hexagon::LDriuh_cPt;
1807 case Hexagon::LDriuh_cdnNotPt :
1808 return Hexagon::LDriuh_cNotPt;
1810 case Hexagon::LDriuh_indexed_cdnPt :
1811 return Hexagon::LDriuh_indexed_cPt;
1813 case Hexagon::LDriuh_indexed_cdnNotPt :
1814 return Hexagon::LDriuh_indexed_cNotPt;
1816 case Hexagon::POST_LDriuh_cdnPt_V4 :
1817 return Hexagon::POST_LDriuh_cPt;
1819 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
1820 return Hexagon::POST_LDriuh_cNotPt;
1822 // Load unsigned byte
1823 case Hexagon::LDriub_cdnPt :
1824 return Hexagon::LDriub_cPt;
1826 case Hexagon::LDriub_cdnNotPt :
1827 return Hexagon::LDriub_cNotPt;
1829 case Hexagon::LDriub_indexed_cdnPt :
1830 return Hexagon::LDriub_indexed_cPt;
1832 case Hexagon::LDriub_indexed_cdnNotPt :
1833 return Hexagon::LDriub_indexed_cNotPt;
1835 case Hexagon::POST_LDriub_cdnPt_V4 :
1836 return Hexagon::POST_LDriub_cPt;
1838 case Hexagon::POST_LDriub_cdnNotPt_V4 :
1839 return Hexagon::POST_LDriub_cNotPt;
1841 // V4 indexed+scaled Load
1843 case Hexagon::LDrid_indexed_cdnPt_V4 :
1844 return Hexagon::LDrid_indexed_cPt_V4;
1846 case Hexagon::LDrid_indexed_cdnNotPt_V4 :
1847 return Hexagon::LDrid_indexed_cNotPt_V4;
1849 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1850 return Hexagon::LDrid_indexed_shl_cPt_V4;
1852 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
1853 return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1855 case Hexagon::LDrib_indexed_cdnPt_V4 :
1856 return Hexagon::LDrib_indexed_cPt_V4;
1858 case Hexagon::LDrib_indexed_cdnNotPt_V4 :
1859 return Hexagon::LDrib_indexed_cNotPt_V4;
1861 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1862 return Hexagon::LDrib_indexed_shl_cPt_V4;
1864 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
1865 return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1867 case Hexagon::LDriub_indexed_cdnPt_V4 :
1868 return Hexagon::LDriub_indexed_cPt_V4;
1870 case Hexagon::LDriub_indexed_cdnNotPt_V4 :
1871 return Hexagon::LDriub_indexed_cNotPt_V4;
1873 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1874 return Hexagon::LDriub_indexed_shl_cPt_V4;
1876 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
1877 return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1879 case Hexagon::LDrih_indexed_cdnPt_V4 :
1880 return Hexagon::LDrih_indexed_cPt_V4;
1882 case Hexagon::LDrih_indexed_cdnNotPt_V4 :
1883 return Hexagon::LDrih_indexed_cNotPt_V4;
1885 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1886 return Hexagon::LDrih_indexed_shl_cPt_V4;
1888 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
1889 return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1891 case Hexagon::LDriuh_indexed_cdnPt_V4 :
1892 return Hexagon::LDriuh_indexed_cPt_V4;
1894 case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
1895 return Hexagon::LDriuh_indexed_cNotPt_V4;
1897 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1898 return Hexagon::LDriuh_indexed_shl_cPt_V4;
1900 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
1901 return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1903 case Hexagon::LDriw_indexed_cdnPt_V4 :
1904 return Hexagon::LDriw_indexed_cPt_V4;
1906 case Hexagon::LDriw_indexed_cdnNotPt_V4 :
1907 return Hexagon::LDriw_indexed_cNotPt_V4;
1909 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1910 return Hexagon::LDriw_indexed_shl_cPt_V4;
1912 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
1913 return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1915 // V4 global address load
1917 case Hexagon::LDd_GP_cdnPt_V4:
1918 return Hexagon::LDd_GP_cPt_V4;
1920 case Hexagon::LDd_GP_cdnNotPt_V4:
1921 return Hexagon::LDd_GP_cNotPt_V4;
1923 case Hexagon::LDb_GP_cdnPt_V4:
1924 return Hexagon::LDb_GP_cPt_V4;
1926 case Hexagon::LDb_GP_cdnNotPt_V4:
1927 return Hexagon::LDb_GP_cNotPt_V4;
1929 case Hexagon::LDub_GP_cdnPt_V4:
1930 return Hexagon::LDub_GP_cPt_V4;
1932 case Hexagon::LDub_GP_cdnNotPt_V4:
1933 return Hexagon::LDub_GP_cNotPt_V4;
1935 case Hexagon::LDh_GP_cdnPt_V4:
1936 return Hexagon::LDh_GP_cPt_V4;
1938 case Hexagon::LDh_GP_cdnNotPt_V4:
1939 return Hexagon::LDh_GP_cNotPt_V4;
1941 case Hexagon::LDuh_GP_cdnPt_V4:
1942 return Hexagon::LDuh_GP_cPt_V4;
1944 case Hexagon::LDuh_GP_cdnNotPt_V4:
1945 return Hexagon::LDuh_GP_cNotPt_V4;
1947 case Hexagon::LDw_GP_cdnPt_V4:
1948 return Hexagon::LDw_GP_cPt_V4;
1950 case Hexagon::LDw_GP_cdnNotPt_V4:
1951 return Hexagon::LDw_GP_cNotPt_V4;
1953 case Hexagon::LDrid_GP_cdnPt_V4:
1954 return Hexagon::LDrid_GP_cPt_V4;
1956 case Hexagon::LDrid_GP_cdnNotPt_V4:
1957 return Hexagon::LDrid_GP_cNotPt_V4;
1959 case Hexagon::LDrib_GP_cdnPt_V4:
1960 return Hexagon::LDrib_GP_cPt_V4;
1962 case Hexagon::LDrib_GP_cdnNotPt_V4:
1963 return Hexagon::LDrib_GP_cNotPt_V4;
1965 case Hexagon::LDriub_GP_cdnPt_V4:
1966 return Hexagon::LDriub_GP_cPt_V4;
1968 case Hexagon::LDriub_GP_cdnNotPt_V4:
1969 return Hexagon::LDriub_GP_cNotPt_V4;
1971 case Hexagon::LDrih_GP_cdnPt_V4:
1972 return Hexagon::LDrih_GP_cPt_V4;
1974 case Hexagon::LDrih_GP_cdnNotPt_V4:
1975 return Hexagon::LDrih_GP_cNotPt_V4;
1977 case Hexagon::LDriuh_GP_cdnPt_V4:
1978 return Hexagon::LDriuh_GP_cPt_V4;
1980 case Hexagon::LDriuh_GP_cdnNotPt_V4:
1981 return Hexagon::LDriuh_GP_cNotPt_V4;
1983 case Hexagon::LDriw_GP_cdnPt_V4:
1984 return Hexagon::LDriw_GP_cPt_V4;
1986 case Hexagon::LDriw_GP_cdnNotPt_V4:
1987 return Hexagon::LDriw_GP_cNotPt_V4;
1991 case Hexagon::ADD_ri_cdnPt :
1992 return Hexagon::ADD_ri_cPt;
1993 case Hexagon::ADD_ri_cdnNotPt :
1994 return Hexagon::ADD_ri_cNotPt;
1996 case Hexagon::ADD_rr_cdnPt :
1997 return Hexagon::ADD_rr_cPt;
1998 case Hexagon::ADD_rr_cdnNotPt:
1999 return Hexagon::ADD_rr_cNotPt;
2001 // Conditional logical Operations
2003 case Hexagon::XOR_rr_cdnPt :
2004 return Hexagon::XOR_rr_cPt;
2005 case Hexagon::XOR_rr_cdnNotPt :
2006 return Hexagon::XOR_rr_cNotPt;
2008 case Hexagon::AND_rr_cdnPt :
2009 return Hexagon::AND_rr_cPt;
2010 case Hexagon::AND_rr_cdnNotPt :
2011 return Hexagon::AND_rr_cNotPt;
2013 case Hexagon::OR_rr_cdnPt :
2014 return Hexagon::OR_rr_cPt;
2015 case Hexagon::OR_rr_cdnNotPt :
2016 return Hexagon::OR_rr_cNotPt;
2018 // Conditional Subtract
2020 case Hexagon::SUB_rr_cdnPt :
2021 return Hexagon::SUB_rr_cPt;
2022 case Hexagon::SUB_rr_cdnNotPt :
2023 return Hexagon::SUB_rr_cNotPt;
2025 // Conditional combine
2027 case Hexagon::COMBINE_rr_cdnPt :
2028 return Hexagon::COMBINE_rr_cPt;
2029 case Hexagon::COMBINE_rr_cdnNotPt :
2030 return Hexagon::COMBINE_rr_cNotPt;
2032 // Conditional shift operations
2034 case Hexagon::ASLH_cdnPt_V4 :
2035 return Hexagon::ASLH_cPt_V4;
2036 case Hexagon::ASLH_cdnNotPt_V4 :
2037 return Hexagon::ASLH_cNotPt_V4;
2039 case Hexagon::ASRH_cdnPt_V4 :
2040 return Hexagon::ASRH_cPt_V4;
2041 case Hexagon::ASRH_cdnNotPt_V4 :
2042 return Hexagon::ASRH_cNotPt_V4;
2044 case Hexagon::SXTB_cdnPt_V4 :
2045 return Hexagon::SXTB_cPt_V4;
2046 case Hexagon::SXTB_cdnNotPt_V4 :
2047 return Hexagon::SXTB_cNotPt_V4;
2049 case Hexagon::SXTH_cdnPt_V4 :
2050 return Hexagon::SXTH_cPt_V4;
2051 case Hexagon::SXTH_cdnNotPt_V4 :
2052 return Hexagon::SXTH_cNotPt_V4;
2054 case Hexagon::ZXTB_cdnPt_V4 :
2055 return Hexagon::ZXTB_cPt_V4;
2056 case Hexagon::ZXTB_cdnNotPt_V4 :
2057 return Hexagon::ZXTB_cNotPt_V4;
2059 case Hexagon::ZXTH_cdnPt_V4 :
2060 return Hexagon::ZXTH_cPt_V4;
2061 case Hexagon::ZXTH_cdnNotPt_V4 :
2062 return Hexagon::ZXTH_cNotPt_V4;
2066 case Hexagon::STrib_imm_cdnPt_V4 :
2067 return Hexagon::STrib_imm_cPt_V4;
2069 case Hexagon::STrib_imm_cdnNotPt_V4 :
2070 return Hexagon::STrib_imm_cNotPt_V4;
2072 case Hexagon::STrib_cdnPt_nv_V4 :
2073 case Hexagon::STrib_cPt_nv_V4 :
2074 case Hexagon::STrib_cdnPt_V4 :
2075 return Hexagon::STrib_cPt;
2077 case Hexagon::STrib_cdnNotPt_nv_V4 :
2078 case Hexagon::STrib_cNotPt_nv_V4 :
2079 case Hexagon::STrib_cdnNotPt_V4 :
2080 return Hexagon::STrib_cNotPt;
2082 case Hexagon::STrib_indexed_cdnPt_V4 :
2083 case Hexagon::STrib_indexed_cPt_nv_V4 :
2084 case Hexagon::STrib_indexed_cdnPt_nv_V4 :
2085 return Hexagon::STrib_indexed_cPt;
2087 case Hexagon::STrib_indexed_cdnNotPt_V4 :
2088 case Hexagon::STrib_indexed_cNotPt_nv_V4 :
2089 case Hexagon::STrib_indexed_cdnNotPt_nv_V4 :
2090 return Hexagon::STrib_indexed_cNotPt;
2092 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
2093 case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
2094 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
2095 return Hexagon::STrib_indexed_shl_cPt_V4;
2097 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
2098 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
2099 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2100 return Hexagon::STrib_indexed_shl_cNotPt_V4;
2102 case Hexagon::POST_STbri_cdnPt_nv_V4 :
2103 case Hexagon::POST_STbri_cPt_nv_V4 :
2104 case Hexagon::POST_STbri_cdnPt_V4 :
2105 return Hexagon::POST_STbri_cPt;
2107 case Hexagon::POST_STbri_cdnNotPt_nv_V4 :
2108 case Hexagon::POST_STbri_cNotPt_nv_V4:
2109 case Hexagon::POST_STbri_cdnNotPt_V4 :
2110 return Hexagon::POST_STbri_cNotPt;
2112 case Hexagon::STb_GP_cdnPt_nv_V4:
2113 case Hexagon::STb_GP_cdnPt_V4:
2114 case Hexagon::STb_GP_cPt_nv_V4:
2115 return Hexagon::STb_GP_cPt_V4;
2117 case Hexagon::STb_GP_cdnNotPt_nv_V4:
2118 case Hexagon::STb_GP_cdnNotPt_V4:
2119 case Hexagon::STb_GP_cNotPt_nv_V4:
2120 return Hexagon::STb_GP_cNotPt_V4;
2122 case Hexagon::STrib_GP_cdnPt_nv_V4:
2123 case Hexagon::STrib_GP_cdnPt_V4:
2124 case Hexagon::STrib_GP_cPt_nv_V4:
2125 return Hexagon::STrib_GP_cPt_V4;
2127 case Hexagon::STrib_GP_cdnNotPt_nv_V4:
2128 case Hexagon::STrib_GP_cdnNotPt_V4:
2129 case Hexagon::STrib_GP_cNotPt_nv_V4:
2130 return Hexagon::STrib_GP_cNotPt_V4;
2132 // Store new-value byte - unconditional
2133 case Hexagon::STrib_nv_V4:
2134 return Hexagon::STrib;
2136 case Hexagon::STrib_indexed_nv_V4:
2137 return Hexagon::STrib_indexed;
2139 case Hexagon::STrib_indexed_shl_nv_V4:
2140 return Hexagon::STrib_indexed_shl_V4;
2142 case Hexagon::STrib_shl_nv_V4:
2143 return Hexagon::STrib_shl_V4;
2145 case Hexagon::STrib_GP_nv_V4:
2146 return Hexagon::STrib_GP_V4;
2148 case Hexagon::STb_GP_nv_V4:
2149 return Hexagon::STb_GP_V4;
2151 case Hexagon::POST_STbri_nv_V4:
2152 return Hexagon::POST_STbri;
2155 case Hexagon::STrih_imm_cdnPt_V4 :
2156 return Hexagon::STrih_imm_cPt_V4;
2158 case Hexagon::STrih_imm_cdnNotPt_V4 :
2159 return Hexagon::STrih_imm_cNotPt_V4;
2161 case Hexagon::STrih_cdnPt_nv_V4 :
2162 case Hexagon::STrih_cPt_nv_V4 :
2163 case Hexagon::STrih_cdnPt_V4 :
2164 return Hexagon::STrih_cPt;
2166 case Hexagon::STrih_cdnNotPt_nv_V4 :
2167 case Hexagon::STrih_cNotPt_nv_V4 :
2168 case Hexagon::STrih_cdnNotPt_V4 :
2169 return Hexagon::STrih_cNotPt;
2171 case Hexagon::STrih_indexed_cdnPt_nv_V4:
2172 case Hexagon::STrih_indexed_cPt_nv_V4 :
2173 case Hexagon::STrih_indexed_cdnPt_V4 :
2174 return Hexagon::STrih_indexed_cPt;
2176 case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
2177 case Hexagon::STrih_indexed_cNotPt_nv_V4 :
2178 case Hexagon::STrih_indexed_cdnNotPt_V4 :
2179 return Hexagon::STrih_indexed_cNotPt;
2181 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4 :
2182 case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
2183 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
2184 return Hexagon::STrih_indexed_shl_cPt_V4;
2186 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4 :
2187 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
2188 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2189 return Hexagon::STrih_indexed_shl_cNotPt_V4;
2191 case Hexagon::POST_SThri_cdnPt_nv_V4 :
2192 case Hexagon::POST_SThri_cPt_nv_V4 :
2193 case Hexagon::POST_SThri_cdnPt_V4 :
2194 return Hexagon::POST_SThri_cPt;
2196 case Hexagon::POST_SThri_cdnNotPt_nv_V4 :
2197 case Hexagon::POST_SThri_cNotPt_nv_V4 :
2198 case Hexagon::POST_SThri_cdnNotPt_V4 :
2199 return Hexagon::POST_SThri_cNotPt;
2201 case Hexagon::STh_GP_cdnPt_nv_V4:
2202 case Hexagon::STh_GP_cdnPt_V4:
2203 case Hexagon::STh_GP_cPt_nv_V4:
2204 return Hexagon::STh_GP_cPt_V4;
2206 case Hexagon::STh_GP_cdnNotPt_nv_V4:
2207 case Hexagon::STh_GP_cdnNotPt_V4:
2208 case Hexagon::STh_GP_cNotPt_nv_V4:
2209 return Hexagon::STh_GP_cNotPt_V4;
2211 case Hexagon::STrih_GP_cdnPt_nv_V4:
2212 case Hexagon::STrih_GP_cdnPt_V4:
2213 case Hexagon::STrih_GP_cPt_nv_V4:
2214 return Hexagon::STrih_GP_cPt_V4;
2216 case Hexagon::STrih_GP_cdnNotPt_nv_V4:
2217 case Hexagon::STrih_GP_cdnNotPt_V4:
2218 case Hexagon::STrih_GP_cNotPt_nv_V4:
2219 return Hexagon::STrih_GP_cNotPt_V4;
2221 // Store new-value halfword - unconditional
2223 case Hexagon::STrih_nv_V4:
2224 return Hexagon::STrih;
2226 case Hexagon::STrih_indexed_nv_V4:
2227 return Hexagon::STrih_indexed;
2229 case Hexagon::STrih_indexed_shl_nv_V4:
2230 return Hexagon::STrih_indexed_shl_V4;
2232 case Hexagon::STrih_shl_nv_V4:
2233 return Hexagon::STrih_shl_V4;
2235 case Hexagon::STrih_GP_nv_V4:
2236 return Hexagon::STrih_GP_V4;
2238 case Hexagon::STh_GP_nv_V4:
2239 return Hexagon::STh_GP_V4;
2241 case Hexagon::POST_SThri_nv_V4:
2242 return Hexagon::POST_SThri;
2246 case Hexagon::STriw_imm_cdnPt_V4 :
2247 return Hexagon::STriw_imm_cPt_V4;
2249 case Hexagon::STriw_imm_cdnNotPt_V4 :
2250 return Hexagon::STriw_imm_cNotPt_V4;
2252 case Hexagon::STriw_cdnPt_nv_V4 :
2253 case Hexagon::STriw_cPt_nv_V4 :
2254 case Hexagon::STriw_cdnPt_V4 :
2255 return Hexagon::STriw_cPt;
2257 case Hexagon::STriw_cdnNotPt_nv_V4 :
2258 case Hexagon::STriw_cNotPt_nv_V4 :
2259 case Hexagon::STriw_cdnNotPt_V4 :
2260 return Hexagon::STriw_cNotPt;
2262 case Hexagon::STriw_indexed_cdnPt_nv_V4 :
2263 case Hexagon::STriw_indexed_cPt_nv_V4 :
2264 case Hexagon::STriw_indexed_cdnPt_V4 :
2265 return Hexagon::STriw_indexed_cPt;
2267 case Hexagon::STriw_indexed_cdnNotPt_nv_V4 :
2268 case Hexagon::STriw_indexed_cNotPt_nv_V4 :
2269 case Hexagon::STriw_indexed_cdnNotPt_V4 :
2270 return Hexagon::STriw_indexed_cNotPt;
2272 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4 :
2273 case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
2274 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
2275 return Hexagon::STriw_indexed_shl_cPt_V4;
2277 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4 :
2278 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
2279 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2280 return Hexagon::STriw_indexed_shl_cNotPt_V4;
2282 case Hexagon::POST_STwri_cdnPt_nv_V4 :
2283 case Hexagon::POST_STwri_cPt_nv_V4 :
2284 case Hexagon::POST_STwri_cdnPt_V4 :
2285 return Hexagon::POST_STwri_cPt;
2287 case Hexagon::POST_STwri_cdnNotPt_nv_V4 :
2288 case Hexagon::POST_STwri_cNotPt_nv_V4 :
2289 case Hexagon::POST_STwri_cdnNotPt_V4 :
2290 return Hexagon::POST_STwri_cNotPt;
2292 case Hexagon::STw_GP_cdnPt_nv_V4:
2293 case Hexagon::STw_GP_cdnPt_V4:
2294 case Hexagon::STw_GP_cPt_nv_V4:
2295 return Hexagon::STw_GP_cPt_V4;
2297 case Hexagon::STw_GP_cdnNotPt_nv_V4:
2298 case Hexagon::STw_GP_cdnNotPt_V4:
2299 case Hexagon::STw_GP_cNotPt_nv_V4:
2300 return Hexagon::STw_GP_cNotPt_V4;
2302 case Hexagon::STriw_GP_cdnPt_nv_V4:
2303 case Hexagon::STriw_GP_cdnPt_V4:
2304 case Hexagon::STriw_GP_cPt_nv_V4:
2305 return Hexagon::STriw_GP_cPt_V4;
2307 case Hexagon::STriw_GP_cdnNotPt_nv_V4:
2308 case Hexagon::STriw_GP_cdnNotPt_V4:
2309 case Hexagon::STriw_GP_cNotPt_nv_V4:
2310 return Hexagon::STriw_GP_cNotPt_V4;
2312 // Store new-value word - unconditional
2314 case Hexagon::STriw_nv_V4:
2315 return Hexagon::STriw;
2317 case Hexagon::STriw_indexed_nv_V4:
2318 return Hexagon::STriw_indexed;
2320 case Hexagon::STriw_indexed_shl_nv_V4:
2321 return Hexagon::STriw_indexed_shl_V4;
2323 case Hexagon::STriw_shl_nv_V4:
2324 return Hexagon::STriw_shl_V4;
2326 case Hexagon::STriw_GP_nv_V4:
2327 return Hexagon::STriw_GP_V4;
2329 case Hexagon::STw_GP_nv_V4:
2330 return Hexagon::STw_GP_V4;
2332 case Hexagon::POST_STwri_nv_V4:
2333 return Hexagon::POST_STwri;
2337 case Hexagon::STrid_cdnPt_V4 :
2338 return Hexagon::STrid_cPt;
2340 case Hexagon::STrid_cdnNotPt_V4 :
2341 return Hexagon::STrid_cNotPt;
2343 case Hexagon::STrid_indexed_cdnPt_V4 :
2344 return Hexagon::STrid_indexed_cPt;
2346 case Hexagon::STrid_indexed_cdnNotPt_V4 :
2347 return Hexagon::STrid_indexed_cNotPt;
2349 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
2350 return Hexagon::STrid_indexed_shl_cPt_V4;
2352 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2353 return Hexagon::STrid_indexed_shl_cNotPt_V4;
2355 case Hexagon::POST_STdri_cdnPt_V4 :
2356 return Hexagon::POST_STdri_cPt;
2358 case Hexagon::POST_STdri_cdnNotPt_V4 :
2359 return Hexagon::POST_STdri_cNotPt;
2361 // Absolute addressing mode - global address
2362 case Hexagon::STrib_abs_nv_V4:
2363 return Hexagon::STrib_abs_V4;
2365 case Hexagon::STrib_abs_cdnPt_V4:
2366 case Hexagon::STrib_abs_cPt_nv_V4:
2367 case Hexagon::STrib_abs_cdnPt_nv_V4:
2368 return Hexagon::STrib_abs_cPt_V4;
2370 case Hexagon::STrib_abs_cdnNotPt_V4:
2371 case Hexagon::STrib_abs_cNotPt_nv_V4:
2372 case Hexagon::STrib_abs_cdnNotPt_nv_V4:
2373 return Hexagon::STrib_abs_cNotPt_V4;
2375 case Hexagon::STrih_abs_nv_V4:
2376 return Hexagon::STrih_abs_V4;
2378 case Hexagon::STrih_abs_cdnPt_V4:
2379 case Hexagon::STrih_abs_cPt_nv_V4:
2380 case Hexagon::STrih_abs_cdnPt_nv_V4:
2381 return Hexagon::STrih_abs_cPt_V4;
2383 case Hexagon::STrih_abs_cdnNotPt_V4:
2384 case Hexagon::STrih_abs_cNotPt_nv_V4:
2385 case Hexagon::STrih_abs_cdnNotPt_nv_V4:
2386 return Hexagon::STrih_abs_cNotPt_V4;
2388 case Hexagon::STriw_abs_nv_V4:
2389 return Hexagon::STriw_abs_V4;
2391 case Hexagon::STriw_abs_cdnPt_V4:
2392 case Hexagon::STriw_abs_cPt_nv_V4:
2393 case Hexagon::STriw_abs_cdnPt_nv_V4:
2394 return Hexagon::STriw_abs_cPt_V4;
2396 case Hexagon::STriw_abs_cdnNotPt_V4:
2397 case Hexagon::STriw_abs_cNotPt_nv_V4:
2398 case Hexagon::STriw_abs_cdnNotPt_nv_V4:
2399 return Hexagon::STriw_abs_cNotPt_V4;
2401 case Hexagon::STrid_abs_cdnPt_V4:
2402 return Hexagon::STrid_abs_cPt_V4;
2404 case Hexagon::STrid_abs_cdnNotPt_V4:
2405 return Hexagon::STrid_abs_cNotPt_V4;
2407 // Absolute addressing mode - immediate values
2408 case Hexagon::STrib_imm_abs_nv_V4:
2409 return Hexagon::STrib_imm_abs_V4;
2411 case Hexagon::STrib_imm_abs_cdnPt_V4:
2412 case Hexagon::STrib_imm_abs_cPt_nv_V4:
2413 case Hexagon::STrib_imm_abs_cdnPt_nv_V4:
2414 return Hexagon::STrib_imm_abs_cPt_V4;
2416 case Hexagon::STrib_imm_abs_cdnNotPt_V4:
2417 case Hexagon::STrib_imm_abs_cNotPt_nv_V4:
2418 case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4:
2419 return Hexagon::STrib_imm_abs_cNotPt_V4;
2421 case Hexagon::STrih_imm_abs_nv_V4:
2422 return Hexagon::STrih_imm_abs_V4;
2424 case Hexagon::STrih_imm_abs_cdnPt_V4:
2425 case Hexagon::STrih_imm_abs_cPt_nv_V4:
2426 case Hexagon::STrih_imm_abs_cdnPt_nv_V4:
2427 return Hexagon::STrih_imm_abs_cPt_V4;
2429 case Hexagon::STrih_imm_abs_cdnNotPt_V4:
2430 case Hexagon::STrih_imm_abs_cNotPt_nv_V4:
2431 case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4:
2432 return Hexagon::STrih_imm_abs_cNotPt_V4;
2434 case Hexagon::STriw_imm_abs_nv_V4:
2435 return Hexagon::STriw_imm_abs_V4;
2437 case Hexagon::STriw_imm_abs_cdnPt_V4:
2438 case Hexagon::STriw_imm_abs_cPt_nv_V4:
2439 case Hexagon::STriw_imm_abs_cdnPt_nv_V4:
2440 return Hexagon::STriw_imm_abs_cPt_V4;
2442 case Hexagon::STriw_imm_abs_cdnNotPt_V4:
2443 case Hexagon::STriw_imm_abs_cNotPt_nv_V4:
2444 case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4:
2445 return Hexagon::STriw_imm_abs_cNotPt_V4;
2447 // Load - absolute set addressing
2448 case Hexagon::LDrib_abs_cdnPt_V4:
2449 return Hexagon::LDrib_abs_cPt_V4;
2451 case Hexagon::LDrib_abs_cdnNotPt_V4:
2452 return Hexagon::LDrib_abs_cNotPt_V4;
2454 case Hexagon::LDriub_abs_cdnPt_V4:
2455 return Hexagon::LDriub_abs_cPt_V4;
2457 case Hexagon::LDriub_abs_cdnNotPt_V4:
2458 return Hexagon::LDriub_abs_cNotPt_V4;
2460 case Hexagon::LDrih_abs_cdnPt_V4:
2461 return Hexagon::LDrih_abs_cPt_V4;
2463 case Hexagon::LDrih_abs_cdnNotPt_V4:
2464 return Hexagon::LDrih_abs_cNotPt_V4;
2466 case Hexagon::LDriuh_abs_cdnPt_V4:
2467 return Hexagon::LDriuh_abs_cPt_V4;
2469 case Hexagon::LDriuh_abs_cdnNotPt_V4:
2470 return Hexagon::LDriuh_abs_cNotPt_V4;
2472 case Hexagon::LDriw_abs_cdnPt_V4:
2473 return Hexagon::LDriw_abs_cPt_V4;
2475 case Hexagon::LDriw_abs_cdnNotPt_V4:
2476 return Hexagon::LDriw_abs_cNotPt_V4;
2478 case Hexagon::LDrid_abs_cdnPt_V4:
2479 return Hexagon::LDrid_abs_cPt_V4;
2481 case Hexagon::LDrid_abs_cdnNotPt_V4:
2482 return Hexagon::LDrid_abs_cNotPt_V4;
2484 case Hexagon::LDrib_imm_abs_cdnPt_V4:
2485 return Hexagon::LDrib_imm_abs_cPt_V4;
2487 case Hexagon::LDrib_imm_abs_cdnNotPt_V4:
2488 return Hexagon::LDrib_imm_abs_cNotPt_V4;
2490 case Hexagon::LDriub_imm_abs_cdnPt_V4:
2491 return Hexagon::LDriub_imm_abs_cPt_V4;
2493 case Hexagon::LDriub_imm_abs_cdnNotPt_V4:
2494 return Hexagon::LDriub_imm_abs_cNotPt_V4;
2496 case Hexagon::LDrih_imm_abs_cdnPt_V4:
2497 return Hexagon::LDrih_imm_abs_cPt_V4;
2499 case Hexagon::LDrih_imm_abs_cdnNotPt_V4:
2500 return Hexagon::LDrih_imm_abs_cNotPt_V4;
2502 case Hexagon::LDriuh_imm_abs_cdnPt_V4:
2503 return Hexagon::LDriuh_imm_abs_cPt_V4;
2505 case Hexagon::LDriuh_imm_abs_cdnNotPt_V4:
2506 return Hexagon::LDriuh_imm_abs_cNotPt_V4;
2508 case Hexagon::LDriw_imm_abs_cdnPt_V4:
2509 return Hexagon::LDriw_imm_abs_cPt_V4;
2511 case Hexagon::LDriw_imm_abs_cdnNotPt_V4:
2512 return Hexagon::LDriw_imm_abs_cNotPt_V4;
2514 case Hexagon::STd_GP_cdnPt_V4 :
2515 return Hexagon::STd_GP_cPt_V4;
2517 case Hexagon::STd_GP_cdnNotPt_V4 :
2518 return Hexagon::STd_GP_cNotPt_V4;
2520 case Hexagon::STrid_GP_cdnPt_V4 :
2521 return Hexagon::STrid_GP_cPt_V4;
2523 case Hexagon::STrid_GP_cdnNotPt_V4 :
2524 return Hexagon::STrid_GP_cNotPt_V4;
2528 bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
2529 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2530 int NewOpcode = GetDotOldOp(MI->getOpcode());
2531 MI->setDesc(QII->get(NewOpcode));
2535 // Returns true if an instruction is predicated on p0 and false if it's
2536 // predicated on !p0.
2538 static bool GetPredicateSense(MachineInstr* MI,
2539 const HexagonInstrInfo *QII) {
2541 switch (MI->getOpcode()) {
2542 default: llvm_unreachable("Unknown predicate sense of the instruction");
2543 case Hexagon::TFR_cPt:
2544 case Hexagon::TFR_cdnPt:
2545 case Hexagon::TFRI_cPt:
2546 case Hexagon::TFRI_cdnPt:
2547 case Hexagon::STrib_cPt :
2548 case Hexagon::STrib_cdnPt_V4 :
2549 case Hexagon::STrib_indexed_cPt :
2550 case Hexagon::STrib_indexed_cdnPt_V4 :
2551 case Hexagon::STrib_indexed_shl_cPt_V4 :
2552 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
2553 case Hexagon::POST_STbri_cPt :
2554 case Hexagon::POST_STbri_cdnPt_V4 :
2555 case Hexagon::STrih_cPt :
2556 case Hexagon::STrih_cdnPt_V4 :
2557 case Hexagon::STrih_indexed_cPt :
2558 case Hexagon::STrih_indexed_cdnPt_V4 :
2559 case Hexagon::STrih_indexed_shl_cPt_V4 :
2560 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
2561 case Hexagon::POST_SThri_cPt :
2562 case Hexagon::POST_SThri_cdnPt_V4 :
2563 case Hexagon::STriw_cPt :
2564 case Hexagon::STriw_cdnPt_V4 :
2565 case Hexagon::STriw_indexed_cPt :
2566 case Hexagon::STriw_indexed_cdnPt_V4 :
2567 case Hexagon::STriw_indexed_shl_cPt_V4 :
2568 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
2569 case Hexagon::POST_STwri_cPt :
2570 case Hexagon::POST_STwri_cdnPt_V4 :
2571 case Hexagon::STrib_imm_cPt_V4 :
2572 case Hexagon::STrib_imm_cdnPt_V4 :
2573 case Hexagon::STrid_cPt :
2574 case Hexagon::STrid_cdnPt_V4 :
2575 case Hexagon::STrid_indexed_cPt :
2576 case Hexagon::STrid_indexed_cdnPt_V4 :
2577 case Hexagon::STrid_indexed_shl_cPt_V4 :
2578 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
2579 case Hexagon::POST_STdri_cPt :
2580 case Hexagon::POST_STdri_cdnPt_V4 :
2581 case Hexagon::STrih_imm_cPt_V4 :
2582 case Hexagon::STrih_imm_cdnPt_V4 :
2583 case Hexagon::STriw_imm_cPt_V4 :
2584 case Hexagon::STriw_imm_cdnPt_V4 :
2585 case Hexagon::JMP_cdnPt :
2586 case Hexagon::LDrid_cPt :
2587 case Hexagon::LDrid_cdnPt :
2588 case Hexagon::LDrid_indexed_cPt :
2589 case Hexagon::LDrid_indexed_cdnPt :
2590 case Hexagon::POST_LDrid_cPt :
2591 case Hexagon::POST_LDrid_cdnPt_V4 :
2592 case Hexagon::LDriw_cPt :
2593 case Hexagon::LDriw_cdnPt :
2594 case Hexagon::LDriw_indexed_cPt :
2595 case Hexagon::LDriw_indexed_cdnPt :
2596 case Hexagon::POST_LDriw_cPt :
2597 case Hexagon::POST_LDriw_cdnPt_V4 :
2598 case Hexagon::LDrih_cPt :
2599 case Hexagon::LDrih_cdnPt :
2600 case Hexagon::LDrih_indexed_cPt :
2601 case Hexagon::LDrih_indexed_cdnPt :
2602 case Hexagon::POST_LDrih_cPt :
2603 case Hexagon::POST_LDrih_cdnPt_V4 :
2604 case Hexagon::LDrib_cPt :
2605 case Hexagon::LDrib_cdnPt :
2606 case Hexagon::LDrib_indexed_cPt :
2607 case Hexagon::LDrib_indexed_cdnPt :
2608 case Hexagon::POST_LDrib_cPt :
2609 case Hexagon::POST_LDrib_cdnPt_V4 :
2610 case Hexagon::LDriuh_cPt :
2611 case Hexagon::LDriuh_cdnPt :
2612 case Hexagon::LDriuh_indexed_cPt :
2613 case Hexagon::LDriuh_indexed_cdnPt :
2614 case Hexagon::POST_LDriuh_cPt :
2615 case Hexagon::POST_LDriuh_cdnPt_V4 :
2616 case Hexagon::LDriub_cPt :
2617 case Hexagon::LDriub_cdnPt :
2618 case Hexagon::LDriub_indexed_cPt :
2619 case Hexagon::LDriub_indexed_cdnPt :
2620 case Hexagon::POST_LDriub_cPt :
2621 case Hexagon::POST_LDriub_cdnPt_V4 :
2622 case Hexagon::LDrid_indexed_cPt_V4 :
2623 case Hexagon::LDrid_indexed_cdnPt_V4 :
2624 case Hexagon::LDrid_indexed_shl_cPt_V4 :
2625 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
2626 case Hexagon::LDrib_indexed_cPt_V4 :
2627 case Hexagon::LDrib_indexed_cdnPt_V4 :
2628 case Hexagon::LDrib_indexed_shl_cPt_V4 :
2629 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
2630 case Hexagon::LDriub_indexed_cPt_V4 :
2631 case Hexagon::LDriub_indexed_cdnPt_V4 :
2632 case Hexagon::LDriub_indexed_shl_cPt_V4 :
2633 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
2634 case Hexagon::LDrih_indexed_cPt_V4 :
2635 case Hexagon::LDrih_indexed_cdnPt_V4 :
2636 case Hexagon::LDrih_indexed_shl_cPt_V4 :
2637 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
2638 case Hexagon::LDriuh_indexed_cPt_V4 :
2639 case Hexagon::LDriuh_indexed_cdnPt_V4 :
2640 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2641 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
2642 case Hexagon::LDriw_indexed_cPt_V4 :
2643 case Hexagon::LDriw_indexed_cdnPt_V4 :
2644 case Hexagon::LDriw_indexed_shl_cPt_V4 :
2645 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
2646 case Hexagon::ADD_ri_cPt :
2647 case Hexagon::ADD_ri_cdnPt :
2648 case Hexagon::ADD_rr_cPt :
2649 case Hexagon::ADD_rr_cdnPt :
2650 case Hexagon::XOR_rr_cPt :
2651 case Hexagon::XOR_rr_cdnPt :
2652 case Hexagon::AND_rr_cPt :
2653 case Hexagon::AND_rr_cdnPt :
2654 case Hexagon::OR_rr_cPt :
2655 case Hexagon::OR_rr_cdnPt :
2656 case Hexagon::SUB_rr_cPt :
2657 case Hexagon::SUB_rr_cdnPt :
2658 case Hexagon::COMBINE_rr_cPt :
2659 case Hexagon::COMBINE_rr_cdnPt :
2660 case Hexagon::ASLH_cPt_V4 :
2661 case Hexagon::ASLH_cdnPt_V4 :
2662 case Hexagon::ASRH_cPt_V4 :
2663 case Hexagon::ASRH_cdnPt_V4 :
2664 case Hexagon::SXTB_cPt_V4 :
2665 case Hexagon::SXTB_cdnPt_V4 :
2666 case Hexagon::SXTH_cPt_V4 :
2667 case Hexagon::SXTH_cdnPt_V4 :
2668 case Hexagon::ZXTB_cPt_V4 :
2669 case Hexagon::ZXTB_cdnPt_V4 :
2670 case Hexagon::ZXTH_cPt_V4 :
2671 case Hexagon::ZXTH_cdnPt_V4 :
2673 case Hexagon::LDrib_abs_cPt_V4 :
2674 case Hexagon::LDrib_abs_cdnPt_V4:
2675 case Hexagon::LDriub_abs_cPt_V4 :
2676 case Hexagon::LDriub_abs_cdnPt_V4:
2677 case Hexagon::LDrih_abs_cPt_V4 :
2678 case Hexagon::LDrih_abs_cdnPt_V4:
2679 case Hexagon::LDriuh_abs_cPt_V4 :
2680 case Hexagon::LDriuh_abs_cdnPt_V4:
2681 case Hexagon::LDriw_abs_cPt_V4 :
2682 case Hexagon::LDriw_abs_cdnPt_V4:
2683 case Hexagon::LDrid_abs_cPt_V4 :
2684 case Hexagon::LDrid_abs_cdnPt_V4:
2686 case Hexagon::LDrib_imm_abs_cPt_V4 :
2687 case Hexagon::LDrib_imm_abs_cdnPt_V4:
2688 case Hexagon::LDriub_imm_abs_cPt_V4 :
2689 case Hexagon::LDriub_imm_abs_cdnPt_V4:
2690 case Hexagon::LDrih_imm_abs_cPt_V4 :
2691 case Hexagon::LDrih_imm_abs_cdnPt_V4:
2692 case Hexagon::LDriuh_imm_abs_cPt_V4 :
2693 case Hexagon::LDriuh_imm_abs_cdnPt_V4:
2694 case Hexagon::LDriw_imm_abs_cPt_V4 :
2695 case Hexagon::LDriw_imm_abs_cdnPt_V4:
2697 case Hexagon::STrib_abs_cPt_V4:
2698 case Hexagon::STrib_abs_cdnPt_V4:
2699 case Hexagon::STrih_abs_cPt_V4:
2700 case Hexagon::STrih_abs_cdnPt_V4:
2701 case Hexagon::STriw_abs_cPt_V4:
2702 case Hexagon::STriw_abs_cdnPt_V4:
2703 case Hexagon::STrid_abs_cPt_V4:
2704 case Hexagon::STrid_abs_cdnPt_V4:
2705 case Hexagon::STrib_imm_abs_cPt_V4:
2706 case Hexagon::STrib_imm_abs_cdnPt_V4:
2707 case Hexagon::STrih_imm_abs_cPt_V4:
2708 case Hexagon::STrih_imm_abs_cdnPt_V4:
2709 case Hexagon::STriw_imm_abs_cPt_V4:
2710 case Hexagon::STriw_imm_abs_cdnPt_V4:
2712 case Hexagon::LDrid_GP_cPt_V4 :
2713 case Hexagon::LDrib_GP_cPt_V4 :
2714 case Hexagon::LDriub_GP_cPt_V4 :
2715 case Hexagon::LDrih_GP_cPt_V4 :
2716 case Hexagon::LDriuh_GP_cPt_V4 :
2717 case Hexagon::LDriw_GP_cPt_V4 :
2718 case Hexagon::LDd_GP_cPt_V4 :
2719 case Hexagon::LDb_GP_cPt_V4 :
2720 case Hexagon::LDub_GP_cPt_V4 :
2721 case Hexagon::LDh_GP_cPt_V4 :
2722 case Hexagon::LDuh_GP_cPt_V4 :
2723 case Hexagon::LDw_GP_cPt_V4 :
2724 case Hexagon::STrid_GP_cPt_V4 :
2725 case Hexagon::STrib_GP_cPt_V4 :
2726 case Hexagon::STrih_GP_cPt_V4 :
2727 case Hexagon::STriw_GP_cPt_V4 :
2728 case Hexagon::STd_GP_cPt_V4 :
2729 case Hexagon::STb_GP_cPt_V4 :
2730 case Hexagon::STh_GP_cPt_V4 :
2731 case Hexagon::STw_GP_cPt_V4 :
2732 case Hexagon::LDrid_GP_cdnPt_V4 :
2733 case Hexagon::LDrib_GP_cdnPt_V4 :
2734 case Hexagon::LDriub_GP_cdnPt_V4 :
2735 case Hexagon::LDrih_GP_cdnPt_V4 :
2736 case Hexagon::LDriuh_GP_cdnPt_V4 :
2737 case Hexagon::LDriw_GP_cdnPt_V4 :
2738 case Hexagon::LDd_GP_cdnPt_V4 :
2739 case Hexagon::LDb_GP_cdnPt_V4 :
2740 case Hexagon::LDub_GP_cdnPt_V4 :
2741 case Hexagon::LDh_GP_cdnPt_V4 :
2742 case Hexagon::LDuh_GP_cdnPt_V4 :
2743 case Hexagon::LDw_GP_cdnPt_V4 :
2744 case Hexagon::STrid_GP_cdnPt_V4 :
2745 case Hexagon::STrib_GP_cdnPt_V4 :
2746 case Hexagon::STrih_GP_cdnPt_V4 :
2747 case Hexagon::STriw_GP_cdnPt_V4 :
2748 case Hexagon::STd_GP_cdnPt_V4 :
2749 case Hexagon::STb_GP_cdnPt_V4 :
2750 case Hexagon::STh_GP_cdnPt_V4 :
2751 case Hexagon::STw_GP_cdnPt_V4 :
2754 case Hexagon::TFR_cNotPt:
2755 case Hexagon::TFR_cdnNotPt:
2756 case Hexagon::TFRI_cNotPt:
2757 case Hexagon::TFRI_cdnNotPt:
2758 case Hexagon::STrib_cNotPt :
2759 case Hexagon::STrib_cdnNotPt_V4 :
2760 case Hexagon::STrib_indexed_cNotPt :
2761 case Hexagon::STrib_indexed_cdnNotPt_V4 :
2762 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2763 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2764 case Hexagon::POST_STbri_cNotPt :
2765 case Hexagon::POST_STbri_cdnNotPt_V4 :
2766 case Hexagon::STrih_cNotPt :
2767 case Hexagon::STrih_cdnNotPt_V4 :
2768 case Hexagon::STrih_indexed_cNotPt :
2769 case Hexagon::STrih_indexed_cdnNotPt_V4 :
2770 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2771 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2772 case Hexagon::POST_SThri_cNotPt :
2773 case Hexagon::POST_SThri_cdnNotPt_V4 :
2774 case Hexagon::STriw_cNotPt :
2775 case Hexagon::STriw_cdnNotPt_V4 :
2776 case Hexagon::STriw_indexed_cNotPt :
2777 case Hexagon::STriw_indexed_cdnNotPt_V4 :
2778 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2779 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2780 case Hexagon::POST_STwri_cNotPt :
2781 case Hexagon::POST_STwri_cdnNotPt_V4 :
2782 case Hexagon::STrib_imm_cNotPt_V4 :
2783 case Hexagon::STrib_imm_cdnNotPt_V4 :
2784 case Hexagon::STrid_cNotPt :
2785 case Hexagon::STrid_cdnNotPt_V4 :
2786 case Hexagon::STrid_indexed_cdnNotPt_V4 :
2787 case Hexagon::STrid_indexed_cNotPt :
2788 case Hexagon::STrid_indexed_shl_cNotPt_V4 :
2789 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2790 case Hexagon::POST_STdri_cNotPt :
2791 case Hexagon::POST_STdri_cdnNotPt_V4 :
2792 case Hexagon::STrih_imm_cNotPt_V4 :
2793 case Hexagon::STrih_imm_cdnNotPt_V4 :
2794 case Hexagon::STriw_imm_cNotPt_V4 :
2795 case Hexagon::STriw_imm_cdnNotPt_V4 :
2796 case Hexagon::JMP_cdnNotPt :
2797 case Hexagon::LDrid_cNotPt :
2798 case Hexagon::LDrid_cdnNotPt :
2799 case Hexagon::LDrid_indexed_cNotPt :
2800 case Hexagon::LDrid_indexed_cdnNotPt :
2801 case Hexagon::POST_LDrid_cNotPt :
2802 case Hexagon::POST_LDrid_cdnNotPt_V4 :
2803 case Hexagon::LDriw_cNotPt :
2804 case Hexagon::LDriw_cdnNotPt :
2805 case Hexagon::LDriw_indexed_cNotPt :
2806 case Hexagon::LDriw_indexed_cdnNotPt :
2807 case Hexagon::POST_LDriw_cNotPt :
2808 case Hexagon::POST_LDriw_cdnNotPt_V4 :
2809 case Hexagon::LDrih_cNotPt :
2810 case Hexagon::LDrih_cdnNotPt :
2811 case Hexagon::LDrih_indexed_cNotPt :
2812 case Hexagon::LDrih_indexed_cdnNotPt :
2813 case Hexagon::POST_LDrih_cNotPt :
2814 case Hexagon::POST_LDrih_cdnNotPt_V4 :
2815 case Hexagon::LDrib_cNotPt :
2816 case Hexagon::LDrib_cdnNotPt :
2817 case Hexagon::LDrib_indexed_cNotPt :
2818 case Hexagon::LDrib_indexed_cdnNotPt :
2819 case Hexagon::POST_LDrib_cNotPt :
2820 case Hexagon::POST_LDrib_cdnNotPt_V4 :
2821 case Hexagon::LDriuh_cNotPt :
2822 case Hexagon::LDriuh_cdnNotPt :
2823 case Hexagon::LDriuh_indexed_cNotPt :
2824 case Hexagon::LDriuh_indexed_cdnNotPt :
2825 case Hexagon::POST_LDriuh_cNotPt :
2826 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
2827 case Hexagon::LDriub_cNotPt :
2828 case Hexagon::LDriub_cdnNotPt :
2829 case Hexagon::LDriub_indexed_cNotPt :
2830 case Hexagon::LDriub_indexed_cdnNotPt :
2831 case Hexagon::POST_LDriub_cNotPt :
2832 case Hexagon::POST_LDriub_cdnNotPt_V4 :
2833 case Hexagon::LDrid_indexed_cNotPt_V4 :
2834 case Hexagon::LDrid_indexed_cdnNotPt_V4 :
2835 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2836 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
2837 case Hexagon::LDrib_indexed_cNotPt_V4 :
2838 case Hexagon::LDrib_indexed_cdnNotPt_V4 :
2839 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2840 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
2841 case Hexagon::LDriub_indexed_cNotPt_V4 :
2842 case Hexagon::LDriub_indexed_cdnNotPt_V4 :
2843 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2844 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
2845 case Hexagon::LDrih_indexed_cNotPt_V4 :
2846 case Hexagon::LDrih_indexed_cdnNotPt_V4 :
2847 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2848 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
2849 case Hexagon::LDriuh_indexed_cNotPt_V4 :
2850 case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
2851 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2852 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
2853 case Hexagon::LDriw_indexed_cNotPt_V4 :
2854 case Hexagon::LDriw_indexed_cdnNotPt_V4 :
2855 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2856 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
2857 case Hexagon::ADD_ri_cNotPt :
2858 case Hexagon::ADD_ri_cdnNotPt :
2859 case Hexagon::ADD_rr_cNotPt :
2860 case Hexagon::ADD_rr_cdnNotPt :
2861 case Hexagon::XOR_rr_cNotPt :
2862 case Hexagon::XOR_rr_cdnNotPt :
2863 case Hexagon::AND_rr_cNotPt :
2864 case Hexagon::AND_rr_cdnNotPt :
2865 case Hexagon::OR_rr_cNotPt :
2866 case Hexagon::OR_rr_cdnNotPt :
2867 case Hexagon::SUB_rr_cNotPt :
2868 case Hexagon::SUB_rr_cdnNotPt :
2869 case Hexagon::COMBINE_rr_cNotPt :
2870 case Hexagon::COMBINE_rr_cdnNotPt :
2871 case Hexagon::ASLH_cNotPt_V4 :
2872 case Hexagon::ASLH_cdnNotPt_V4 :
2873 case Hexagon::ASRH_cNotPt_V4 :
2874 case Hexagon::ASRH_cdnNotPt_V4 :
2875 case Hexagon::SXTB_cNotPt_V4 :
2876 case Hexagon::SXTB_cdnNotPt_V4 :
2877 case Hexagon::SXTH_cNotPt_V4 :
2878 case Hexagon::SXTH_cdnNotPt_V4 :
2879 case Hexagon::ZXTB_cNotPt_V4 :
2880 case Hexagon::ZXTB_cdnNotPt_V4 :
2881 case Hexagon::ZXTH_cNotPt_V4 :
2882 case Hexagon::ZXTH_cdnNotPt_V4 :
2884 case Hexagon::LDrib_abs_cNotPt_V4:
2885 case Hexagon::LDrib_abs_cdnNotPt_V4:
2886 case Hexagon::LDriub_abs_cNotPt_V4 :
2887 case Hexagon::LDriub_abs_cdnNotPt_V4:
2888 case Hexagon::LDrih_abs_cNotPt_V4 :
2889 case Hexagon::LDrih_abs_cdnNotPt_V4:
2890 case Hexagon::LDriuh_abs_cNotPt_V4 :
2891 case Hexagon::LDriuh_abs_cdnNotPt_V4:
2892 case Hexagon::LDriw_abs_cNotPt_V4 :
2893 case Hexagon::LDriw_abs_cdnNotPt_V4:
2894 case Hexagon::LDrid_abs_cNotPt_V4 :
2895 case Hexagon::LDrid_abs_cdnNotPt_V4:
2897 case Hexagon::LDrib_imm_abs_cNotPt_V4:
2898 case Hexagon::LDrib_imm_abs_cdnNotPt_V4:
2899 case Hexagon::LDriub_imm_abs_cNotPt_V4 :
2900 case Hexagon::LDriub_imm_abs_cdnNotPt_V4:
2901 case Hexagon::LDrih_imm_abs_cNotPt_V4 :
2902 case Hexagon::LDrih_imm_abs_cdnNotPt_V4:
2903 case Hexagon::LDriuh_imm_abs_cNotPt_V4 :
2904 case Hexagon::LDriuh_imm_abs_cdnNotPt_V4:
2905 case Hexagon::LDriw_imm_abs_cNotPt_V4 :
2906 case Hexagon::LDriw_imm_abs_cdnNotPt_V4:
2908 case Hexagon::STrib_abs_cNotPt_V4:
2909 case Hexagon::STrib_abs_cdnNotPt_V4:
2910 case Hexagon::STrih_abs_cNotPt_V4:
2911 case Hexagon::STrih_abs_cdnNotPt_V4:
2912 case Hexagon::STriw_abs_cNotPt_V4:
2913 case Hexagon::STriw_abs_cdnNotPt_V4:
2914 case Hexagon::STrid_abs_cNotPt_V4:
2915 case Hexagon::STrid_abs_cdnNotPt_V4:
2916 case Hexagon::STrib_imm_abs_cNotPt_V4:
2917 case Hexagon::STrib_imm_abs_cdnNotPt_V4:
2918 case Hexagon::STrih_imm_abs_cNotPt_V4:
2919 case Hexagon::STrih_imm_abs_cdnNotPt_V4:
2920 case Hexagon::STriw_imm_abs_cNotPt_V4:
2921 case Hexagon::STriw_imm_abs_cdnNotPt_V4:
2923 case Hexagon::LDrid_GP_cNotPt_V4 :
2924 case Hexagon::LDrib_GP_cNotPt_V4 :
2925 case Hexagon::LDriub_GP_cNotPt_V4 :
2926 case Hexagon::LDrih_GP_cNotPt_V4 :
2927 case Hexagon::LDriuh_GP_cNotPt_V4 :
2928 case Hexagon::LDriw_GP_cNotPt_V4 :
2929 case Hexagon::LDd_GP_cNotPt_V4 :
2930 case Hexagon::LDb_GP_cNotPt_V4 :
2931 case Hexagon::LDub_GP_cNotPt_V4 :
2932 case Hexagon::LDh_GP_cNotPt_V4 :
2933 case Hexagon::LDuh_GP_cNotPt_V4 :
2934 case Hexagon::LDw_GP_cNotPt_V4 :
2935 case Hexagon::STrid_GP_cNotPt_V4 :
2936 case Hexagon::STrib_GP_cNotPt_V4 :
2937 case Hexagon::STrih_GP_cNotPt_V4 :
2938 case Hexagon::STriw_GP_cNotPt_V4 :
2939 case Hexagon::STd_GP_cNotPt_V4 :
2940 case Hexagon::STb_GP_cNotPt_V4 :
2941 case Hexagon::STh_GP_cNotPt_V4 :
2942 case Hexagon::STw_GP_cNotPt_V4 :
2943 case Hexagon::LDrid_GP_cdnNotPt_V4 :
2944 case Hexagon::LDrib_GP_cdnNotPt_V4 :
2945 case Hexagon::LDriub_GP_cdnNotPt_V4 :
2946 case Hexagon::LDrih_GP_cdnNotPt_V4 :
2947 case Hexagon::LDriuh_GP_cdnNotPt_V4 :
2948 case Hexagon::LDriw_GP_cdnNotPt_V4 :
2949 case Hexagon::LDd_GP_cdnNotPt_V4 :
2950 case Hexagon::LDb_GP_cdnNotPt_V4 :
2951 case Hexagon::LDub_GP_cdnNotPt_V4 :
2952 case Hexagon::LDh_GP_cdnNotPt_V4 :
2953 case Hexagon::LDuh_GP_cdnNotPt_V4 :
2954 case Hexagon::LDw_GP_cdnNotPt_V4 :
2955 case Hexagon::STrid_GP_cdnNotPt_V4 :
2956 case Hexagon::STrib_GP_cdnNotPt_V4 :
2957 case Hexagon::STrih_GP_cdnNotPt_V4 :
2958 case Hexagon::STriw_GP_cdnNotPt_V4 :
2959 case Hexagon::STd_GP_cdnNotPt_V4 :
2960 case Hexagon::STb_GP_cdnNotPt_V4 :
2961 case Hexagon::STh_GP_cdnNotPt_V4 :
2962 case Hexagon::STw_GP_cdnNotPt_V4 :
2965 // return *some value* to avoid compiler warning
2969 bool HexagonPacketizerList::isDotNewInst(MachineInstr* MI) {
2970 if (isNewValueInst(MI))
2973 switch (MI->getOpcode()) {
2974 case Hexagon::TFR_cdnNotPt:
2975 case Hexagon::TFR_cdnPt:
2976 case Hexagon::TFRI_cdnNotPt:
2977 case Hexagon::TFRI_cdnPt:
2978 case Hexagon::LDrid_cdnPt :
2979 case Hexagon::LDrid_cdnNotPt :
2980 case Hexagon::LDrid_indexed_cdnPt :
2981 case Hexagon::LDrid_indexed_cdnNotPt :
2982 case Hexagon::POST_LDrid_cdnPt_V4 :
2983 case Hexagon::POST_LDrid_cdnNotPt_V4 :
2984 case Hexagon::LDriw_cdnPt :
2985 case Hexagon::LDriw_cdnNotPt :
2986 case Hexagon::LDriw_indexed_cdnPt :
2987 case Hexagon::LDriw_indexed_cdnNotPt :
2988 case Hexagon::POST_LDriw_cdnPt_V4 :
2989 case Hexagon::POST_LDriw_cdnNotPt_V4 :
2990 case Hexagon::LDrih_cdnPt :
2991 case Hexagon::LDrih_cdnNotPt :
2992 case Hexagon::LDrih_indexed_cdnPt :
2993 case Hexagon::LDrih_indexed_cdnNotPt :
2994 case Hexagon::POST_LDrih_cdnPt_V4 :
2995 case Hexagon::POST_LDrih_cdnNotPt_V4 :
2996 case Hexagon::LDrib_cdnPt :
2997 case Hexagon::LDrib_cdnNotPt :
2998 case Hexagon::LDrib_indexed_cdnPt :
2999 case Hexagon::LDrib_indexed_cdnNotPt :
3000 case Hexagon::POST_LDrib_cdnPt_V4 :
3001 case Hexagon::POST_LDrib_cdnNotPt_V4 :
3002 case Hexagon::LDriuh_cdnPt :
3003 case Hexagon::LDriuh_cdnNotPt :
3004 case Hexagon::LDriuh_indexed_cdnPt :
3005 case Hexagon::LDriuh_indexed_cdnNotPt :
3006 case Hexagon::POST_LDriuh_cdnPt_V4 :
3007 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
3008 case Hexagon::LDriub_cdnPt :
3009 case Hexagon::LDriub_cdnNotPt :
3010 case Hexagon::LDriub_indexed_cdnPt :
3011 case Hexagon::LDriub_indexed_cdnNotPt :
3012 case Hexagon::POST_LDriub_cdnPt_V4 :
3013 case Hexagon::POST_LDriub_cdnNotPt_V4 :
3015 case Hexagon::LDrid_indexed_cdnPt_V4 :
3016 case Hexagon::LDrid_indexed_cdnNotPt_V4 :
3017 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
3018 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
3019 case Hexagon::LDrib_indexed_cdnPt_V4 :
3020 case Hexagon::LDrib_indexed_cdnNotPt_V4 :
3021 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
3022 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
3023 case Hexagon::LDriub_indexed_cdnPt_V4 :
3024 case Hexagon::LDriub_indexed_cdnNotPt_V4 :
3025 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
3026 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
3027 case Hexagon::LDrih_indexed_cdnPt_V4 :
3028 case Hexagon::LDrih_indexed_cdnNotPt_V4 :
3029 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
3030 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
3031 case Hexagon::LDriuh_indexed_cdnPt_V4 :
3032 case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
3033 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
3034 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
3035 case Hexagon::LDriw_indexed_cdnPt_V4 :
3036 case Hexagon::LDriw_indexed_cdnNotPt_V4 :
3037 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
3038 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
3041 case Hexagon::ADD_ri_cdnPt:
3042 case Hexagon::ADD_ri_cdnNotPt:
3043 case Hexagon::ADD_rr_cdnPt:
3044 case Hexagon::ADD_rr_cdnNotPt:
3046 // Conditional logical operations
3047 case Hexagon::XOR_rr_cdnPt :
3048 case Hexagon::XOR_rr_cdnNotPt :
3049 case Hexagon::AND_rr_cdnPt :
3050 case Hexagon::AND_rr_cdnNotPt :
3051 case Hexagon::OR_rr_cdnPt :
3052 case Hexagon::OR_rr_cdnNotPt :
3054 // Conditonal subtract
3055 case Hexagon::SUB_rr_cdnPt :
3056 case Hexagon::SUB_rr_cdnNotPt :
3058 // Conditional combine
3059 case Hexagon::COMBINE_rr_cdnPt :
3060 case Hexagon::COMBINE_rr_cdnNotPt :
3062 // Conditional shift operations
3063 case Hexagon::ASLH_cdnPt_V4:
3064 case Hexagon::ASLH_cdnNotPt_V4:
3065 case Hexagon::ASRH_cdnPt_V4:
3066 case Hexagon::ASRH_cdnNotPt_V4:
3067 case Hexagon::SXTB_cdnPt_V4:
3068 case Hexagon::SXTB_cdnNotPt_V4:
3069 case Hexagon::SXTH_cdnPt_V4:
3070 case Hexagon::SXTH_cdnNotPt_V4:
3071 case Hexagon::ZXTB_cdnPt_V4:
3072 case Hexagon::ZXTB_cdnNotPt_V4:
3073 case Hexagon::ZXTH_cdnPt_V4:
3074 case Hexagon::ZXTH_cdnNotPt_V4:
3076 // Conditional stores
3077 case Hexagon::STrib_imm_cdnPt_V4 :
3078 case Hexagon::STrib_imm_cdnNotPt_V4 :
3079 case Hexagon::STrib_cdnPt_V4 :
3080 case Hexagon::STrib_cdnNotPt_V4 :
3081 case Hexagon::STrib_indexed_cdnPt_V4 :
3082 case Hexagon::STrib_indexed_cdnNotPt_V4 :
3083 case Hexagon::POST_STbri_cdnPt_V4 :
3084 case Hexagon::POST_STbri_cdnNotPt_V4 :
3085 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
3086 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
3088 // Store doubleword conditionally
3089 case Hexagon::STrid_indexed_cdnPt_V4 :
3090 case Hexagon::STrid_indexed_cdnNotPt_V4 :
3091 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
3092 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
3093 case Hexagon::POST_STdri_cdnPt_V4 :
3094 case Hexagon::POST_STdri_cdnNotPt_V4 :
3096 // Store halfword conditionally
3097 case Hexagon::STrih_cdnPt_V4 :
3098 case Hexagon::STrih_cdnNotPt_V4 :
3099 case Hexagon::STrih_indexed_cdnPt_V4 :
3100 case Hexagon::STrih_indexed_cdnNotPt_V4 :
3101 case Hexagon::STrih_imm_cdnPt_V4 :
3102 case Hexagon::STrih_imm_cdnNotPt_V4 :
3103 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
3104 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
3105 case Hexagon::POST_SThri_cdnPt_V4 :
3106 case Hexagon::POST_SThri_cdnNotPt_V4 :
3108 // Store word conditionally
3109 case Hexagon::STriw_cdnPt_V4 :
3110 case Hexagon::STriw_cdnNotPt_V4 :
3111 case Hexagon::STriw_indexed_cdnPt_V4 :
3112 case Hexagon::STriw_indexed_cdnNotPt_V4 :
3113 case Hexagon::STriw_imm_cdnPt_V4 :
3114 case Hexagon::STriw_imm_cdnNotPt_V4 :
3115 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
3116 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
3117 case Hexagon::POST_STwri_cdnPt_V4 :
3118 case Hexagon::POST_STwri_cdnNotPt_V4 :
3120 case Hexagon::LDd_GP_cdnPt_V4:
3121 case Hexagon::LDd_GP_cdnNotPt_V4:
3122 case Hexagon::LDb_GP_cdnPt_V4:
3123 case Hexagon::LDb_GP_cdnNotPt_V4:
3124 case Hexagon::LDub_GP_cdnPt_V4:
3125 case Hexagon::LDub_GP_cdnNotPt_V4:
3126 case Hexagon::LDh_GP_cdnPt_V4:
3127 case Hexagon::LDh_GP_cdnNotPt_V4:
3128 case Hexagon::LDuh_GP_cdnPt_V4:
3129 case Hexagon::LDuh_GP_cdnNotPt_V4:
3130 case Hexagon::LDw_GP_cdnPt_V4:
3131 case Hexagon::LDw_GP_cdnNotPt_V4:
3132 case Hexagon::LDrid_GP_cdnPt_V4:
3133 case Hexagon::LDrid_GP_cdnNotPt_V4:
3134 case Hexagon::LDrib_GP_cdnPt_V4:
3135 case Hexagon::LDrib_GP_cdnNotPt_V4:
3136 case Hexagon::LDriub_GP_cdnPt_V4:
3137 case Hexagon::LDriub_GP_cdnNotPt_V4:
3138 case Hexagon::LDrih_GP_cdnPt_V4:
3139 case Hexagon::LDrih_GP_cdnNotPt_V4:
3140 case Hexagon::LDriuh_GP_cdnPt_V4:
3141 case Hexagon::LDriuh_GP_cdnNotPt_V4:
3142 case Hexagon::LDriw_GP_cdnPt_V4:
3143 case Hexagon::LDriw_GP_cdnNotPt_V4:
3145 case Hexagon::STrid_GP_cdnPt_V4:
3146 case Hexagon::STrid_GP_cdnNotPt_V4:
3147 case Hexagon::STrib_GP_cdnPt_V4:
3148 case Hexagon::STrib_GP_cdnNotPt_V4:
3149 case Hexagon::STrih_GP_cdnPt_V4:
3150 case Hexagon::STrih_GP_cdnNotPt_V4:
3151 case Hexagon::STriw_GP_cdnPt_V4:
3152 case Hexagon::STriw_GP_cdnNotPt_V4:
3153 case Hexagon::STd_GP_cdnPt_V4:
3154 case Hexagon::STd_GP_cdnNotPt_V4:
3155 case Hexagon::STb_GP_cdnPt_V4:
3156 case Hexagon::STb_GP_cdnNotPt_V4:
3157 case Hexagon::STh_GP_cdnPt_V4:
3158 case Hexagon::STh_GP_cdnNotPt_V4:
3159 case Hexagon::STw_GP_cdnPt_V4:
3160 case Hexagon::STw_GP_cdnNotPt_V4:
3166 static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
3167 const HexagonInstrInfo *QII) {
3168 assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
3170 // Post Increment means duplicates. Use dense map to find duplicates in the
3171 // list. Caution: Densemap initializes with the minimum of 64 buckets,
3172 // whereas there are at most 5 operands in the post increment.
3173 DenseMap<unsigned, unsigned> DefRegsSet;
3174 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
3175 if (MI->getOperand(opNum).isReg() &&
3176 MI->getOperand(opNum).isDef()) {
3177 DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
3180 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
3181 if (MI->getOperand(opNum).isReg() &&
3182 MI->getOperand(opNum).isUse()) {
3183 if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
3184 return MI->getOperand(opNum);
3188 if (MI->getDesc().mayLoad()) {
3189 // The 2nd operand is always the post increment operand in load.
3190 assert(MI->getOperand(1).isReg() &&
3191 "Post increment operand has be to a register.");
3192 return (MI->getOperand(1));
3194 if (MI->getDesc().mayStore()) {
3195 // The 1st operand is always the post increment operand in store.
3196 assert(MI->getOperand(0).isReg() &&
3197 "Post increment operand has be to a register.");
3198 return (MI->getOperand(0));
3201 // we should never come here.
3202 llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
3205 // get the value being stored
3206 static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
3207 // value being stored is always the last operand.
3208 return (MI->getOperand(MI->getNumOperands()-1));
3211 // can be new value store?
3212 // Following restrictions are to be respected in convert a store into
3213 // a new value store.
3214 // 1. If an instruction uses auto-increment, its address register cannot
3215 // be a new-value register. Arch Spec 5.4.2.1
3216 // 2. If an instruction uses absolute-set addressing mode,
3217 // its address register cannot be a new-value register.
3218 // Arch Spec 5.4.2.1.TODO: This is not enabled as
3219 // as absolute-set address mode patters are not implemented.
3220 // 3. If an instruction produces a 64-bit result, its registers cannot be used
3221 // as new-value registers. Arch Spec 5.4.2.2.
3222 // 4. If the instruction that sets a new-value register is conditional, then
3223 // the instruction that uses the new-value register must also be conditional,
3224 // and both must always have their predicates evaluate identically.
3225 // Arch Spec 5.4.2.3.
3226 // 5. There is an implied restriction of a packet can not have another store,
3227 // if there is a new value store in the packet. Corollary, if there is
3228 // already a store in a packet, there can not be a new value store.
3229 // Arch Spec: 3.4.4.2
3230 bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
3231 MachineInstr *PacketMI, unsigned DepReg,
3232 std::map <MachineInstr*, SUnit*> MIToSUnit)
3234 // Make sure we are looking at the store
3235 if (!IsNewifyStore(MI))
3238 // Make sure there is dependency and can be new value'ed
3239 if (GetStoreValueOperand(MI).isReg() &&
3240 GetStoreValueOperand(MI).getReg() != DepReg)
3243 const HexagonRegisterInfo* QRI =
3244 (const HexagonRegisterInfo *) TM.getRegisterInfo();
3245 const MCInstrDesc& MCID = PacketMI->getDesc();
3246 // first operand is always the result
3248 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3249 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
3251 // if there is already an store in the packet, no can do new value store
3252 // Arch Spec 3.4.4.2.
3253 for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
3254 VE = CurrentPacketMIs.end();
3256 SUnit* PacketSU = MIToSUnit[*VI];
3257 if (PacketSU->getInstr()->getDesc().mayStore() ||
3258 // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
3259 // then we don't need this
3260 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
3261 PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
3265 if (PacketRC == &Hexagon::DoubleRegsRegClass) {
3266 // new value store constraint: double regs can not feed into new value store
3267 // arch spec section: 5.4.2.2
3271 // Make sure it's NOT the post increment register that we are going to
3273 if (QII->isPostIncrement(MI) &&
3274 MI->getDesc().mayStore() &&
3275 GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
3279 if (QII->isPostIncrement(PacketMI) &&
3280 PacketMI->getDesc().mayLoad() &&
3281 GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
3282 // if source is post_inc, or absolute-set addressing,
3283 // it can not feed into new value store
3284 // r3 = memw(r2++#4)
3285 // memw(r30 + #-1404) = r2.new -> can not be new value store
3286 // arch spec section: 5.4.2.1
3290 // If the source that feeds the store is predicated, new value store must
3291 // also be also predicated.
3292 if (QII->isPredicated(PacketMI)) {
3293 if (!QII->isPredicated(MI))
3296 // Check to make sure that they both will have their predicates
3297 // evaluate identically
3298 unsigned predRegNumSrc;
3299 unsigned predRegNumDst;
3300 const TargetRegisterClass* predRegClass;
3302 // Get predicate register used in the source instruction
3303 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
3304 if ( PacketMI->getOperand(opNum).isReg())
3305 predRegNumSrc = PacketMI->getOperand(opNum).getReg();
3306 predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
3307 if (predRegClass == &Hexagon::PredRegsRegClass) {
3311 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
3312 ("predicate register not found in a predicated PacketMI instruction"));
3314 // Get predicate register used in new-value store instruction
3315 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
3316 if ( MI->getOperand(opNum).isReg())
3317 predRegNumDst = MI->getOperand(opNum).getReg();
3318 predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
3319 if (predRegClass == &Hexagon::PredRegsRegClass) {
3323 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
3324 ("predicate register not found in a predicated MI instruction"));
3326 // New-value register producer and user (store) need to satisfy these
3328 // 1) Both instructions should be predicated on the same register.
3329 // 2) If producer of the new-value register is .new predicated then store
3330 // should also be .new predicated and if producer is not .new predicated
3331 // then store should not be .new predicated.
3332 // 3) Both new-value register producer and user should have same predicate
3333 // sense, i.e, either both should be negated or both should be none negated.
3335 if (( predRegNumDst != predRegNumSrc) ||
3336 isDotNewInst(PacketMI) != isDotNewInst(MI) ||
3337 GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {
3342 // Make sure that other than the new-value register no other store instruction
3343 // register has been modified in the same packet. Predicate registers can be
3344 // modified by they should not be modified between the producer and the store
3345 // instruction as it will make them both conditional on different values.
3346 // We already know this to be true for all the instructions before and
3347 // including PacketMI. Howerver, we need to perform the check for the
3348 // remaining instructions in the packet.
3350 std::vector<MachineInstr*>::iterator VI;
3351 std::vector<MachineInstr*>::iterator VE;
3352 unsigned StartCheck = 0;
3354 for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
3356 SUnit* TempSU = MIToSUnit[*VI];
3357 MachineInstr* TempMI = TempSU->getInstr();
3359 // Following condition is true for all the instructions until PacketMI is
3360 // reached (StartCheck is set to 0 before the for loop).
3361 // StartCheck flag is 1 for all the instructions after PacketMI.
3362 if (TempMI != PacketMI && !StartCheck) // start processing only after
3363 continue; // encountering PacketMI
3366 if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
3369 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
3370 if (MI->getOperand(opNum).isReg() &&
3371 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
3377 // Make sure that for non POST_INC stores:
3378 // 1. The only use of reg is DepReg and no other registers.
3379 // This handles V4 base+index registers.
3380 // The following store can not be dot new.
3381 // Eg. r0 = add(r0, #3)a
3382 // memw(r1+r0<<#2) = r0
3383 if (!QII->isPostIncrement(MI) &&
3384 GetStoreValueOperand(MI).isReg() &&
3385 GetStoreValueOperand(MI).getReg() == DepReg) {
3386 for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
3387 if (MI->getOperand(opNum).isReg() &&
3388 MI->getOperand(opNum).getReg() == DepReg) {
3392 // 2. If data definition is because of implicit definition of the register,
3393 // do not newify the store. Eg.
3394 // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
3395 // STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
3396 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
3397 if (PacketMI->getOperand(opNum).isReg() &&
3398 PacketMI->getOperand(opNum).getReg() == DepReg &&
3399 PacketMI->getOperand(opNum).isDef() &&
3400 PacketMI->getOperand(opNum).isImplicit()) {
3406 // Can be dot new store.
3410 // can this MI to promoted to either
3411 // new value store or new value jump
3412 bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
3413 SUnit *PacketSU, unsigned DepReg,
3414 std::map <MachineInstr*, SUnit*> MIToSUnit,
3415 MachineBasicBlock::iterator &MII)
3418 const HexagonRegisterInfo* QRI =
3419 (const HexagonRegisterInfo *) TM.getRegisterInfo();
3420 if (!QRI->Subtarget.hasV4TOps() ||
3424 MachineInstr *PacketMI = PacketSU->getInstr();
3426 // Check to see the store can be new value'ed.
3427 if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
3430 // Check to see the compare/jump can be new value'ed.
3431 // This is done as a pass on its own. Don't need to check it here.
3435 // Check to see if an instruction can be dot new
3436 // There are three kinds.
3437 // 1. dot new on predicate - V2/V3/V4
3438 // 2. dot new on stores NV/ST - V4
3439 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
3440 bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
3441 SUnit *PacketSU, unsigned DepReg,
3442 std::map <MachineInstr*, SUnit*> MIToSUnit,
3443 MachineBasicBlock::iterator &MII,
3444 const TargetRegisterClass* RC )
3446 // already a dot new instruction
3447 if (isDotNewInst(MI) && !IsNewifyStore(MI))
3450 if (!isNewifiable(MI))
3454 if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
3456 else if (RC != &Hexagon::PredRegsRegClass &&
3457 !IsNewifyStore(MI)) // MI is not a new-value store
3460 // Create a dot new machine instruction to see if resources can be
3461 // allocated. If not, bail out now.
3462 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3463 int NewOpcode = GetDotNewOp(MI->getOpcode());
3464 const MCInstrDesc &desc = QII->get(NewOpcode);
3466 MachineInstr *NewMI =
3467 MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
3468 bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
3469 MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
3471 if (!ResourcesAvailable)
3474 // new value store only
3475 // new new value jump generated as a passes
3476 if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
3483 // Go through the packet instructions and search for anti dependency
3484 // between them and DepReg from MI
3485 // Consider this case:
3487 // a) %R1<def> = TFRI_cdNotPt %P3, 2
3490 // b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
3491 // c) %P3<def> = TFR_PdRs %R23
3492 // d) %R1<def> = TFRI_cdnPt %P3, 4
3494 // The P3 from a) and d) will be complements after
3495 // a)'s P3 is converted to .new form
3496 // Anti Dep between c) and b) is irrelevant for this case
3497 bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
3499 std::map <MachineInstr*, SUnit*> MIToSUnit) {
3501 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3502 SUnit* PacketSUDep = MIToSUnit[MI];
3504 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
3505 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
3507 // We only care for dependencies to predicated instructions
3508 if(!QII->isPredicated(*VIN)) continue;
3510 // Scheduling Unit for current insn in the packet
3511 SUnit* PacketSU = MIToSUnit[*VIN];
3513 // Look at dependencies between current members of the packet
3514 // and predicate defining instruction MI.
3515 // Make sure that dependency is on the exact register
3517 if (PacketSU->isSucc(PacketSUDep)) {
3518 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
3519 if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
3520 (PacketSU->Succs[i].getKind() == SDep::Anti) &&
3521 (PacketSU->Succs[i].getReg() == DepReg)) {
3532 // Given two predicated instructions, this function detects whether
3533 // the predicates are complements
3534 bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
3535 MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
3537 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3538 // Currently can only reason about conditional transfers
3539 if (!QII->isConditionalTransfer(MI1) || !QII->isConditionalTransfer(MI2)) {
3543 // Scheduling unit for candidate
3544 SUnit* SU = MIToSUnit[MI1];
3546 // One corner case deals with the following scenario:
3548 // a) %R24<def> = TFR_cPt %P0, %R25
3552 // b) %R25<def> = TFR_cNotPt %P0, %R24
3553 // c) %P0<def> = CMPEQri %R26, 1
3556 // On general check a) and b) are complements, but
3557 // presence of c) will convert a) to .new form, and
3558 // then it is not a complement
3559 // We attempt to detect it by analyzing existing
3560 // dependencies in the packet
3562 // Analyze relationships between all existing members of the packet.
3563 // Look for Anti dependecy on the same predicate reg
3564 // as used in the candidate
3565 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
3566 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
3568 // Scheduling Unit for current insn in the packet
3569 SUnit* PacketSU = MIToSUnit[*VIN];
3571 // If this instruction in the packet is succeeded by the candidate...
3572 if (PacketSU->isSucc(SU)) {
3573 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
3574 // The corner case exist when there is true data
3575 // dependency between candidate and one of current
3576 // packet members, this dep is on predicate reg, and
3577 // there already exist anti dep on the same pred in
3579 if (PacketSU->Succs[i].getSUnit() == SU &&
3580 Hexagon::PredRegsRegClass.contains(
3581 PacketSU->Succs[i].getReg()) &&
3582 PacketSU->Succs[i].getKind() == SDep::Data &&
3583 // Here I know that *VIN is predicate setting instruction
3584 // with true data dep to candidate on the register
3585 // we care about - c) in the above example.
3586 // Now I need to see if there is an anti dependency
3587 // from c) to any other instruction in the
3588 // same packet on the pred reg of interest
3589 RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
3597 // If the above case does not apply, check regular
3598 // complement condition.
3599 // Check that the predicate register is the same and
3600 // that the predicate sense is different
3601 // We also need to differentiate .old vs. .new:
3602 // !p0 is not complimentary to p0.new
3603 return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
3604 (GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
3605 (isDotNewInst(MI1) == isDotNewInst(MI2)));
3608 // initPacketizerState - Initialize packetizer flags
3609 void HexagonPacketizerList::initPacketizerState() {
3612 PromotedToDotNew = false;
3613 GlueToNewValueJump = false;
3614 GlueAllocframeStore = false;
3615 FoundSequentialDependence = false;
3620 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
3621 bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
3622 MachineBasicBlock *MBB) {
3623 if (MI->isDebugValue())
3626 // We must print out inline assembly
3627 if (MI->isInlineAsm())
3630 // We check if MI has any functional units mapped to it.
3631 // If it doesn't, we ignore the instruction.
3632 const MCInstrDesc& TID = MI->getDesc();
3633 unsigned SchedClass = TID.getSchedClass();
3634 const InstrStage* IS =
3635 ResourceTracker->getInstrItins()->beginStage(SchedClass);
3636 unsigned FuncUnits = IS->getUnits();
3640 // isSoloInstruction: - Returns true for instructions that must be
3641 // scheduled in their own packet.
3642 bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
3644 if (MI->isInlineAsm())
3647 if (MI->isEHLabel())
3650 // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
3651 // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
3652 // They must not be grouped with other instructions in a packet.
3653 if (IsSchedBarrier(MI))
3659 // isLegalToPacketizeTogether:
3660 // SUI is the current instruction that is out side of the current packet.
3661 // SUJ is the current instruction inside the current packet against which that
3662 // SUI will be packetized.
3663 bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
3664 MachineInstr *I = SUI->getInstr();
3665 MachineInstr *J = SUJ->getInstr();
3666 assert(I && J && "Unable to packetize null instruction!");
3668 const MCInstrDesc &MCIDI = I->getDesc();
3669 const MCInstrDesc &MCIDJ = J->getDesc();
3671 MachineBasicBlock::iterator II = I;
3673 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
3674 const HexagonRegisterInfo* QRI =
3675 (const HexagonRegisterInfo *) TM.getRegisterInfo();
3676 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3678 // Inline asm cannot go in the packet.
3679 if (I->getOpcode() == Hexagon::INLINEASM)
3680 llvm_unreachable("Should not meet inline asm here!");
3682 if (isSoloInstruction(I))
3683 llvm_unreachable("Should not meet solo instr here!");
3685 // A save callee-save register function call can only be in a packet
3686 // with instructions that don't write to the callee-save registers.
3687 if ((QII->isSaveCalleeSavedRegsCall(I) &&
3688 DoesModifyCalleeSavedReg(J, QRI)) ||
3689 (QII->isSaveCalleeSavedRegsCall(J) &&
3690 DoesModifyCalleeSavedReg(I, QRI))) {
3695 // Two control flow instructions cannot go in the same packet.
3696 if (IsControlFlow(I) && IsControlFlow(J)) {
3701 // A LoopN instruction cannot appear in the same packet as a jump or call.
3702 if (IsLoopN(I) && ( IsDirectJump(J)
3704 || QII->isDeallocRet(J))) {
3708 if (IsLoopN(J) && ( IsDirectJump(I)
3710 || QII->isDeallocRet(I))) {
3715 // dealloc_return cannot appear in the same packet as a conditional or
3716 // unconditional jump.
3717 if (QII->isDeallocRet(I) && ( MCIDJ.isBranch()
3719 || MCIDJ.isBarrier())) {
3725 // V4 allows dual store. But does not allow second store, if the
3726 // first store is not in SLOT0. New value store, new value jump,
3727 // dealloc_return and memop always take SLOT0.
3728 // Arch spec 3.4.4.2
3729 if (QRI->Subtarget.hasV4TOps()) {
3731 if (MCIDI.mayStore() && MCIDJ.mayStore() && isNewValueInst(J)) {
3736 if ( (QII->isMemOp(J) && MCIDI.mayStore())
3737 || (MCIDJ.mayStore() && QII->isMemOp(I))
3738 || (QII->isMemOp(J) && QII->isMemOp(I))) {
3744 if (MCIDJ.mayStore() && QII->isDeallocRet(I)){
3749 // If an instruction feeds new value jump, glue it.
3750 MachineBasicBlock::iterator NextMII = I;
3752 MachineInstr *NextMI = NextMII;
3754 if (QII->isNewValueJump(NextMI)) {
3756 bool secondRegMatch = false;
3757 bool maintainNewValueJump = false;
3759 if (NextMI->getOperand(1).isReg() &&
3760 I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
3761 secondRegMatch = true;
3762 maintainNewValueJump = true;
3765 if (!secondRegMatch &&
3766 I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
3767 maintainNewValueJump = true;
3770 for (std::vector<MachineInstr*>::iterator
3771 VI = CurrentPacketMIs.begin(),
3772 VE = CurrentPacketMIs.end();
3773 (VI != VE && maintainNewValueJump); ++VI) {
3774 SUnit* PacketSU = MIToSUnit[*VI];
3776 // NVJ can not be part of the dual jump - Arch Spec: section 7.8
3777 if (PacketSU->getInstr()->getDesc().isCall()) {
3782 // 1. Packet does not have a store in it.
3783 // 2. If the first operand of the nvj is newified, and the second
3784 // operand is also a reg, it (second reg) is not defined in
3786 // 3. If the second operand of the nvj is newified, (which means
3787 // first operand is also a reg), first reg is not defined in
3789 if (PacketSU->getInstr()->getDesc().mayStore() ||
3790 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
3792 (!secondRegMatch && NextMI->getOperand(1).isReg() &&
3793 PacketSU->getInstr()->modifiesRegister(
3794 NextMI->getOperand(1).getReg(), QRI)) ||
3797 PacketSU->getInstr()->modifiesRegister(
3798 NextMI->getOperand(0).getReg(), QRI))) {
3804 GlueToNewValueJump = true;
3810 if (SUJ->isSucc(SUI)) {
3811 for (unsigned i = 0;
3812 (i < SUJ->Succs.size()) && !FoundSequentialDependence;
3815 if (SUJ->Succs[i].getSUnit() != SUI) {
3819 SDep::Kind DepType = SUJ->Succs[i].getKind();
3821 // For direct calls:
3822 // Ignore register dependences for call instructions for
3823 // packetization purposes except for those due to r31 and
3824 // predicate registers.
3826 // For indirect calls:
3827 // Same as direct calls + check for true dependences to the register
3828 // used in the indirect call.
3830 // We completely ignore Order dependences for call instructions
3833 // Ignore register dependences for return instructions like jumpr,
3834 // dealloc return unless we have dependencies on the explicit uses
3835 // of the registers used by jumpr (like r31) or dealloc return
3836 // (like r29 or r30).
3838 // TODO: Currently, jumpr is handling only return of r31. So, the
3839 // following logic (specificaly IsCallDependent) is working fine.
3840 // We need to enable jumpr for register other than r31 and then,
3841 // we need to rework the last part, where it handles indirect call
3842 // of that (IsCallDependent) function. Bug 6216 is opened for this.
3844 unsigned DepReg = 0;
3845 const TargetRegisterClass* RC = NULL;
3846 if (DepType == SDep::Data) {
3847 DepReg = SUJ->Succs[i].getReg();
3848 RC = QRI->getMinimalPhysRegClass(DepReg);
3850 if ((MCIDI.isCall() || MCIDI.isReturn()) &&
3851 (!IsRegDependence(DepType) ||
3852 !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
3856 // For instructions that can be promoted to dot-new, try to promote.
3857 else if ((DepType == SDep::Data) &&
3858 CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
3859 PromoteToDotNew(I, DepType, II, RC)) {
3860 PromotedToDotNew = true;
3864 else if ((DepType == SDep::Data) &&
3865 (QII->isNewValueJump(I))) {
3869 // For predicated instructions, if the predicates are complements
3870 // then there can be no dependence.
3871 else if (QII->isPredicated(I) &&
3872 QII->isPredicated(J) &&
3873 ArePredicatesComplements(I, J, MIToSUnit)) {
3877 else if (IsDirectJump(I) &&
3878 !MCIDJ.isBranch() &&
3880 (DepType == SDep::Order)) {
3881 // Ignore Order dependences between unconditional direct branches
3882 // and non-control-flow instructions
3885 else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
3886 (DepType != SDep::Output)) {
3887 // Ignore all dependences for jumps except for true and output
3892 // Ignore output dependences due to superregs. We can
3893 // write to two different subregisters of R1:0 for instance
3894 // in the same cycle
3899 // If neither I nor J defines DepReg, then this is a
3900 // superfluous output dependence. The dependence must be of the
3904 // and there is an output dependence between the two instructions
3907 // We want to ignore these dependences.
3908 // Ideally, the dependence constructor should annotate such
3909 // dependences. We can then avoid this relatively expensive check.
3911 else if (DepType == SDep::Output) {
3912 // DepReg is the register that's responsible for the dependence.
3913 unsigned DepReg = SUJ->Succs[i].getReg();
3915 // Check if I and J really defines DepReg.
3916 if (I->definesRegister(DepReg) ||
3917 J->definesRegister(DepReg)) {
3918 FoundSequentialDependence = true;
3923 // We ignore Order dependences for
3924 // 1. Two loads unless they are volatile.
3925 // 2. Two stores in V4 unless they are volatile.
3926 else if ((DepType == SDep::Order) &&
3927 !I->hasVolatileMemoryRef() &&
3928 !J->hasVolatileMemoryRef()) {
3929 if (QRI->Subtarget.hasV4TOps() &&
3930 // hexagonv4 allows dual store.
3931 MCIDI.mayStore() && MCIDJ.mayStore()) {
3934 // store followed by store-- not OK on V2
3935 // store followed by load -- not OK on all (OK if addresses
3937 // load followed by store -- OK on all
3938 // load followed by load -- OK on all
3939 else if ( !MCIDJ.mayStore()) {
3943 FoundSequentialDependence = true;
3948 // For V4, special case ALLOCFRAME. Even though there is dependency
3949 // between ALLOCAFRAME and subsequent store, allow it to be
3950 // packetized in a same packet. This implies that the store is using
3951 // caller's SP. Hense, offset needs to be updated accordingly.
3952 else if (DepType == SDep::Data
3953 && QRI->Subtarget.hasV4TOps()
3954 && J->getOpcode() == Hexagon::ALLOCFRAME
3955 && (I->getOpcode() == Hexagon::STrid
3956 || I->getOpcode() == Hexagon::STriw_indexed
3957 || I->getOpcode() == Hexagon::STriw
3958 || I->getOpcode() == Hexagon::STrib)
3959 && I->getOperand(0).getReg() == QRI->getStackRegister()
3960 && QII->isValidOffset(I->getOpcode(),
3961 I->getOperand(1).getImm() -
3962 (FrameSize + HEXAGON_LRFP_SIZE)))
3964 GlueAllocframeStore = true;
3965 // Since this store is to be glued with allocframe in the same
3966 // packet, it will use SP of the previous stack frame, i.e
3967 // caller's SP. Therefore, we need to recalculate offset according
3969 I->getOperand(1).setImm(I->getOperand(1).getImm() -
3970 (FrameSize + HEXAGON_LRFP_SIZE));
3974 // Skip over anti-dependences. Two instructions that are
3975 // anti-dependent can share a packet
3977 else if (DepType != SDep::Anti) {
3978 FoundSequentialDependence = true;
3983 if (FoundSequentialDependence) {
3992 // isLegalToPruneDependencies
3993 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
3994 MachineInstr *I = SUI->getInstr();
3995 assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
3997 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
4001 // Check if the instruction was promoted to a dot-new. If so, demote it
4002 // back into a dot-old.
4003 if (PromotedToDotNew) {
4007 // Check if the instruction (must be a store) was glued with an Allocframe
4008 // instruction. If so, restore its offset to its original value, i.e. use
4009 // curent SP instead of caller's SP.
4010 if (GlueAllocframeStore) {
4011 I->getOperand(1).setImm(I->getOperand(1).getImm() +
4012 FrameSize + HEXAGON_LRFP_SIZE);
4020 MachineBasicBlock::iterator
4021 HexagonPacketizerList::addToPacket(MachineInstr *MI) {
4023 MachineBasicBlock::iterator MII = MI;
4024 MachineBasicBlock *MBB = MI->getParent();
4026 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
4028 if (GlueToNewValueJump) {
4031 MachineInstr *nvjMI = MII;
4032 assert(ResourceTracker->canReserveResources(MI));
4033 ResourceTracker->reserveResources(MI);
4034 if ((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
4035 !tryAllocateResourcesForConstExt(MI)) {
4037 ResourceTracker->reserveResources(MI);
4038 assert(canReserveResourcesForConstExt(MI) &&
4039 "Ensure that there is a slot");
4040 reserveResourcesForConstExt(MI);
4041 // Reserve resources for new value jump constant extender.
4042 assert(canReserveResourcesForConstExt(MI) &&
4043 "Ensure that there is a slot");
4044 reserveResourcesForConstExt(nvjMI);
4045 assert(ResourceTracker->canReserveResources(nvjMI) &&
4046 "Ensure that there is a slot");
4048 } else if ( // Extended instruction takes two slots in the packet.
4049 // Try reserve and allocate 4-byte in the current packet first.
4050 (QII->isExtended(nvjMI)
4051 && (!tryAllocateResourcesForConstExt(nvjMI)
4052 || !ResourceTracker->canReserveResources(nvjMI)))
4053 || // For non-extended instruction, no need to allocate extra 4 bytes.
4054 (!QII->isExtended(nvjMI) &&
4055 !ResourceTracker->canReserveResources(nvjMI)))
4058 // A new and empty packet starts.
4059 // We are sure that the resources requirements can be satisfied.
4060 // Therefore, do not need to call "canReserveResources" anymore.
4061 ResourceTracker->reserveResources(MI);
4062 if (QII->isExtended(nvjMI))
4063 reserveResourcesForConstExt(nvjMI);
4065 // Here, we are sure that "reserveResources" would succeed.
4066 ResourceTracker->reserveResources(nvjMI);
4067 CurrentPacketMIs.push_back(MI);
4068 CurrentPacketMIs.push_back(nvjMI);
4070 if ( (QII->isExtended(MI) || QII->isConstExtended(MI))
4071 && ( !tryAllocateResourcesForConstExt(MI)
4072 || !ResourceTracker->canReserveResources(MI)))
4075 // Check if the instruction was promoted to a dot-new. If so, demote it
4076 // back into a dot-old
4077 if (PromotedToDotNew) {
4080 reserveResourcesForConstExt(MI);
4082 // In case that "MI" is not an extended insn,
4083 // the resource availability has already been checked.
4084 ResourceTracker->reserveResources(MI);
4085 CurrentPacketMIs.push_back(MI);
4090 //===----------------------------------------------------------------------===//
4091 // Public Constructor Functions
4092 //===----------------------------------------------------------------------===//
4094 FunctionPass *llvm::createHexagonPacketizer() {
4095 return new HexagonPacketizer();