1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let neverHasSideEffects = 1 in
15 def IMMEXT : Immext<(outs), (ins),
20 // Hexagon V4 Architecture spec defines 8 instruction classes:
21 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
25 // ========================================
26 // Loads (8/16/32/64 bit)
30 // ========================================
31 // Stores (8/16/32/64 bit)
34 // ALU32 Instructions:
35 // ========================================
36 // Arithmetic / Logical (32 bit)
39 // XTYPE Instructions (32/64 bit):
40 // ========================================
41 // Arithmetic, Logical, Bit Manipulation
42 // Multiply (Integer, Fractional, Complex)
43 // Permute / Vector Permute Operations
44 // Predicate Operations
45 // Shift / Shift with Add/Sub/Logical
47 // Vector Halfword (ALU, Shift, Multiply)
48 // Vector Word (ALU, Shift)
51 // ========================================
52 // Jump/Call PC-relative
55 // ========================================
58 // MEMOP Instructions:
59 // ========================================
60 // Operation on memory (8/16/32 bit)
63 // ========================================
68 // ========================================
69 // Control-Register Transfers
70 // Hardware Loop Setup
71 // Predicate Logicals & Reductions
73 // SYSTEM Instructions (not implemented in the compiler):
74 // ========================================
80 //===----------------------------------------------------------------------===//
82 //===----------------------------------------------------------------------===//
86 let isPredicated = 1 in
87 def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
88 (ins PredRegs:$src1, IntRegs:$src2),
89 "if ($src1) $dst = aslh($src2)",
93 let isPredicated = 1 in
94 def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
95 (ins PredRegs:$src1, IntRegs:$src2),
96 "if (!$src1) $dst = aslh($src2)",
100 let isPredicated = 1 in
101 def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
102 (ins PredRegs:$src1, IntRegs:$src2),
103 "if ($src1.new) $dst = aslh($src2)",
107 let isPredicated = 1 in
108 def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
109 (ins PredRegs:$src1, IntRegs:$src2),
110 "if (!$src1.new) $dst = aslh($src2)",
114 let isPredicated = 1 in
115 def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
116 (ins PredRegs:$src1, IntRegs:$src2),
117 "if ($src1) $dst = asrh($src2)",
121 let isPredicated = 1 in
122 def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
123 (ins PredRegs:$src1, IntRegs:$src2),
124 "if (!$src1) $dst = asrh($src2)",
128 let isPredicated = 1 in
129 def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
130 (ins PredRegs:$src1, IntRegs:$src2),
131 "if ($src1.new) $dst = asrh($src2)",
135 let isPredicated = 1 in
136 def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
137 (ins PredRegs:$src1, IntRegs:$src2),
138 "if (!$src1.new) $dst = asrh($src2)",
144 let isPredicated = 1 in
145 def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
146 (ins PredRegs:$src1, IntRegs:$src2),
147 "if ($src1) $dst = sxtb($src2)",
151 let isPredicated = 1 in
152 def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
153 (ins PredRegs:$src1, IntRegs:$src2),
154 "if (!$src1) $dst = sxtb($src2)",
158 let isPredicated = 1 in
159 def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
160 (ins PredRegs:$src1, IntRegs:$src2),
161 "if ($src1.new) $dst = sxtb($src2)",
165 let isPredicated = 1 in
166 def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
167 (ins PredRegs:$src1, IntRegs:$src2),
168 "if (!$src1.new) $dst = sxtb($src2)",
173 let isPredicated = 1 in
174 def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
175 (ins PredRegs:$src1, IntRegs:$src2),
176 "if ($src1) $dst = sxth($src2)",
180 let isPredicated = 1 in
181 def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
182 (ins PredRegs:$src1, IntRegs:$src2),
183 "if (!$src1) $dst = sxth($src2)",
187 let isPredicated = 1 in
188 def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
189 (ins PredRegs:$src1, IntRegs:$src2),
190 "if ($src1.new) $dst = sxth($src2)",
194 let isPredicated = 1 in
195 def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
196 (ins PredRegs:$src1, IntRegs:$src2),
197 "if (!$src1.new) $dst = sxth($src2)",
203 let neverHasSideEffects = 1, isPredicated = 1 in
204 def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
205 (ins PredRegs:$src1, IntRegs:$src2),
206 "if ($src1) $dst = zxtb($src2)",
210 let neverHasSideEffects = 1, isPredicated = 1 in
211 def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
212 (ins PredRegs:$src1, IntRegs:$src2),
213 "if (!$src1) $dst = zxtb($src2)",
217 let neverHasSideEffects = 1, isPredicated = 1 in
218 def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
219 (ins PredRegs:$src1, IntRegs:$src2),
220 "if ($src1.new) $dst = zxtb($src2)",
224 let neverHasSideEffects = 1, isPredicated = 1 in
225 def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
226 (ins PredRegs:$src1, IntRegs:$src2),
227 "if (!$src1.new) $dst = zxtb($src2)",
231 let neverHasSideEffects = 1, isPredicated = 1 in
232 def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
233 (ins PredRegs:$src1, IntRegs:$src2),
234 "if ($src1) $dst = zxth($src2)",
238 let neverHasSideEffects = 1, isPredicated = 1 in
239 def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
240 (ins PredRegs:$src1, IntRegs:$src2),
241 "if (!$src1) $dst = zxth($src2)",
245 let neverHasSideEffects = 1, isPredicated = 1 in
246 def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
247 (ins PredRegs:$src1, IntRegs:$src2),
248 "if ($src1.new) $dst = zxth($src2)",
252 let neverHasSideEffects = 1, isPredicated = 1 in
253 def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
254 (ins PredRegs:$src1, IntRegs:$src2),
255 "if (!$src1.new) $dst = zxth($src2)",
259 // Generate frame index addresses.
260 let neverHasSideEffects = 1, isReMaterializable = 1 in
261 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
262 (ins IntRegs:$src1, s32Imm:$offset),
263 "$dst = add($src1, ##$offset)",
268 //===----------------------------------------------------------------------===//
270 //===----------------------------------------------------------------------===//
273 //===----------------------------------------------------------------------===//
275 //===----------------------------------------------------------------------===//
278 // Rdd=combine(Rs, #s8)
279 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
280 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
281 def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
282 (ins IntRegs:$src1, s8Ext:$src2),
283 "$dst = combine($src1, #$src2)",
287 // Rdd=combine(#s8, Rs)
288 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
289 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
290 def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
291 (ins s8Ext:$src1, IntRegs:$src2),
292 "$dst = combine(#$src1, $src2)",
296 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
297 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
298 def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
299 (ins s8Imm:$src1, u6Ext:$src2),
300 "$dst = combine(#$src1, #$src2)",
304 //===----------------------------------------------------------------------===//
306 //===----------------------------------------------------------------------===//
308 //===----------------------------------------------------------------------===//
310 //===----------------------------------------------------------------------===//
312 // These absolute set addressing mode instructions accept immediate as
313 // an operand. We have duplicated these patterns to take global address.
315 let neverHasSideEffects = 1 in
316 def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
318 "$dst1 = memd($dst2=#$addr)",
323 let neverHasSideEffects = 1 in
324 def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
326 "$dst1 = memb($dst2=#$addr)",
331 let neverHasSideEffects = 1 in
332 def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
334 "$dst1 = memh($dst2=#$addr)",
339 let neverHasSideEffects = 1 in
340 def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
342 "$dst1 = memub($dst2=#$addr)",
347 let neverHasSideEffects = 1 in
348 def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
350 "$dst1 = memuh($dst2=#$addr)",
355 let neverHasSideEffects = 1 in
356 def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
358 "$dst1 = memw($dst2=#$addr)",
362 // Following patterns are defined for absolute set addressing mode
363 // instruction which take global address as operand.
364 let neverHasSideEffects = 1 in
365 def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
366 (ins globaladdress:$addr),
367 "$dst1 = memd($dst2=##$addr)",
372 let neverHasSideEffects = 1 in
373 def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
374 (ins globaladdress:$addr),
375 "$dst1 = memb($dst2=##$addr)",
380 let neverHasSideEffects = 1 in
381 def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
382 (ins globaladdress:$addr),
383 "$dst1 = memh($dst2=##$addr)",
388 let neverHasSideEffects = 1 in
389 def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
390 (ins globaladdress:$addr),
391 "$dst1 = memub($dst2=##$addr)",
396 let neverHasSideEffects = 1 in
397 def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
398 (ins globaladdress:$addr),
399 "$dst1 = memuh($dst2=##$addr)",
404 let neverHasSideEffects = 1 in
405 def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
406 (ins globaladdress:$addr),
407 "$dst1 = memw($dst2=##$addr)",
413 // Make sure that in post increment load, the first operand is always the post
414 // increment operand.
416 // Rdd=memd(Rs+Rt<<#u2)
417 // Special case pattern for indexed load without offset which is easier to
418 // match. AddedComplexity of this pattern should be lower than base+offset load
419 // and lower yet than the more generic version with offset/shift below
420 // Similar approach is taken for all other base+index loads.
421 let AddedComplexity = 10, isPredicable = 1 in
422 def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),
423 (ins IntRegs:$src1, IntRegs:$src2),
424 "$dst=memd($src1+$src2<<#0)",
425 [(set (i64 DoubleRegs:$dst),
426 (i64 (load (add (i32 IntRegs:$src1),
427 (i32 IntRegs:$src2)))))]>,
430 // multiclass for load instructions with base + register offset
432 multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
434 let PNewValue = #!if(isPredNew, "new", "") in
435 def #NAME# : LDInst2<(outs RC:$dst),
436 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
437 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
438 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
439 []>, Requires<[HasV4T]>;
442 multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
443 let PredSense = #!if(PredNot, "false", "true") in {
444 defm _c#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
446 defm _cdn#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
450 let neverHasSideEffects = 1 in
451 multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
452 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
453 let isPredicable = 1 in
454 def #NAME#_V4 : LDInst2<(outs RC:$dst),
455 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
456 "$dst = "#mnemonic#"($src1+$src2<<#$offset)",
457 []>, Requires<[HasV4T]>;
459 let isPredicated = 1 in {
460 defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
461 defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
466 let addrMode = BaseRegOffset in {
467 defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel;
468 defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel;
469 defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
470 defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel;
471 defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
472 defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel;
475 // 'def pats' for load instructions with base + register offset and non-zero
476 // immediate value. Immediate value is used to left-shift the second
478 let AddedComplexity = 40 in {
479 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
480 (shl IntRegs:$src2, u2ImmPred:$offset)))),
481 (LDrib_indexed_shl_V4 IntRegs:$src1,
482 IntRegs:$src2, u2ImmPred:$offset)>,
485 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
486 (shl IntRegs:$src2, u2ImmPred:$offset)))),
487 (LDriub_indexed_shl_V4 IntRegs:$src1,
488 IntRegs:$src2, u2ImmPred:$offset)>,
491 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
492 (shl IntRegs:$src2, u2ImmPred:$offset)))),
493 (LDriub_indexed_shl_V4 IntRegs:$src1,
494 IntRegs:$src2, u2ImmPred:$offset)>,
497 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
498 (shl IntRegs:$src2, u2ImmPred:$offset)))),
499 (LDrih_indexed_shl_V4 IntRegs:$src1,
500 IntRegs:$src2, u2ImmPred:$offset)>,
503 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
504 (shl IntRegs:$src2, u2ImmPred:$offset)))),
505 (LDriuh_indexed_shl_V4 IntRegs:$src1,
506 IntRegs:$src2, u2ImmPred:$offset)>,
509 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
510 (shl IntRegs:$src2, u2ImmPred:$offset)))),
511 (LDriuh_indexed_shl_V4 IntRegs:$src1,
512 IntRegs:$src2, u2ImmPred:$offset)>,
515 def : Pat <(i32 (load (add IntRegs:$src1,
516 (shl IntRegs:$src2, u2ImmPred:$offset)))),
517 (LDriw_indexed_shl_V4 IntRegs:$src1,
518 IntRegs:$src2, u2ImmPred:$offset)>,
521 def : Pat <(i64 (load (add IntRegs:$src1,
522 (shl IntRegs:$src2, u2ImmPred:$offset)))),
523 (LDrid_indexed_shl_V4 IntRegs:$src1,
524 IntRegs:$src2, u2ImmPred:$offset)>,
528 //// Load doubleword conditionally.
529 // if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2)
530 // if (Pv) Rd=memd(Rs+Rt<<#u2)
531 let AddedComplexity = 15, isPredicated = 1 in
532 def LDrid_indexed_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
533 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
534 "if ($src1) $dst=memd($src2+$src3<<#0)",
538 // if (Pv.new) Rd=memd(Rs+Rt<<#u2)
539 let AddedComplexity = 15, isPredicated = 1 in
540 def LDrid_indexed_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
541 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
542 "if ($src1.new) $dst=memd($src2+$src3<<#0)",
546 // if (!Pv) Rd=memd(Rs+Rt<<#u2)
547 let AddedComplexity = 15, isPredicated = 1 in
548 def LDrid_indexed_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
549 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
550 "if (!$src1) $dst=memd($src2+$src3<<#0)",
554 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
555 let AddedComplexity = 15, isPredicated = 1 in
556 def LDrid_indexed_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
557 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
558 "if (!$src1.new) $dst=memd($src2+$src3<<#0)",
562 // Rdd=memd(Rt<<#u2+#U6)
565 // Rd=memb(Rs+Rt<<#u2)
566 let AddedComplexity = 10, isPredicable = 1 in
567 def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),
568 (ins IntRegs:$src1, IntRegs:$src2),
569 "$dst=memb($src1+$src2<<#0)",
570 [(set (i32 IntRegs:$dst),
571 (i32 (sextloadi8 (add (i32 IntRegs:$src1),
572 (i32 IntRegs:$src2)))))]>,
575 let AddedComplexity = 10, isPredicable = 1 in
576 def LDriub_indexed_V4 : LDInst<(outs IntRegs:$dst),
577 (ins IntRegs:$src1, IntRegs:$src2),
578 "$dst=memub($src1+$src2<<#0)",
579 [(set (i32 IntRegs:$dst),
580 (i32 (zextloadi8 (add (i32 IntRegs:$src1),
581 (i32 IntRegs:$src2)))))]>,
584 let AddedComplexity = 10, isPredicable = 1 in
585 def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
586 (ins IntRegs:$src1, IntRegs:$src2),
587 "$dst=memub($src1+$src2<<#0)",
588 [(set (i32 IntRegs:$dst),
589 (i32 (extloadi8 (add (i32 IntRegs:$src1),
590 (i32 IntRegs:$src2)))))]>,
593 let AddedComplexity = 40, isPredicable = 1 in
594 def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
595 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
596 "$dst=memub($src1+$src2<<#$offset)",
597 [(set (i32 IntRegs:$dst),
598 (i32 (extloadi8 (add (i32 IntRegs:$src1),
599 (shl (i32 IntRegs:$src2),
600 u2ImmPred:$offset)))))]>,
603 //// Load byte conditionally.
604 // if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2)
605 // if (Pv) Rd=memb(Rs+Rt<<#u2)
606 let AddedComplexity = 15, isPredicated = 1 in
607 def LDrib_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
608 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
609 "if ($src1) $dst=memb($src2+$src3<<#0)",
613 // if (Pv.new) Rd=memb(Rs+Rt<<#u2)
614 let AddedComplexity = 15, isPredicated = 1 in
615 def LDrib_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
616 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
617 "if ($src1.new) $dst=memb($src2+$src3<<#0)",
621 // if (!Pv) Rd=memb(Rs+Rt<<#u2)
622 let AddedComplexity = 15, isPredicated = 1 in
623 def LDrib_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
624 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
625 "if (!$src1) $dst=memb($src2+$src3<<#0)",
629 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
630 let AddedComplexity = 15, isPredicated = 1 in
631 def LDrib_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
632 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
633 "if (!$src1.new) $dst=memb($src2+$src3<<#0)",
637 //// Load unsigned byte conditionally.
638 // if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2)
639 // if (Pv) Rd=memub(Rs+Rt<<#u2)
640 let AddedComplexity = 15, isPredicated = 1 in
641 def LDriub_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
642 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
643 "if ($src1) $dst=memub($src2+$src3<<#0)",
647 // if (Pv.new) Rd=memub(Rs+Rt<<#u2)
648 let AddedComplexity = 15, isPredicated = 1 in
649 def LDriub_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
650 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
651 "if ($src1.new) $dst=memub($src2+$src3<<#0)",
655 // if (!Pv) Rd=memub(Rs+Rt<<#u2)
656 let AddedComplexity = 15, isPredicated = 1 in
657 def LDriub_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
658 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
659 "if (!$src1) $dst=memub($src2+$src3<<#0)",
663 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
664 let AddedComplexity = 15, isPredicated = 1 in
665 def LDriub_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
666 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
667 "if (!$src1.new) $dst=memub($src2+$src3<<#0)",
671 // Rd=memb(Rt<<#u2+#U6)
674 // Rd=memh(Rs+Rt<<#u2)
675 let AddedComplexity = 10, isPredicable = 1 in
676 def LDrih_indexed_V4 : LDInst<(outs IntRegs:$dst),
677 (ins IntRegs:$src1, IntRegs:$src2),
678 "$dst=memh($src1+$src2<<#0)",
679 [(set (i32 IntRegs:$dst),
680 (i32 (sextloadi16 (add (i32 IntRegs:$src1),
681 (i32 IntRegs:$src2)))))]>,
684 let AddedComplexity = 10, isPredicable = 1 in
685 def LDriuh_indexed_V4 : LDInst<(outs IntRegs:$dst),
686 (ins IntRegs:$src1, IntRegs:$src2),
687 "$dst=memuh($src1+$src2<<#0)",
688 [(set (i32 IntRegs:$dst),
689 (i32 (zextloadi16 (add (i32 IntRegs:$src1),
690 (i32 IntRegs:$src2)))))]>,
693 let AddedComplexity = 10, isPredicable = 1 in
694 def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
695 (ins IntRegs:$src1, IntRegs:$src2),
696 "$dst=memuh($src1+$src2<<#0)",
697 [(set (i32 IntRegs:$dst),
698 (i32 (extloadi16 (add (i32 IntRegs:$src1),
699 (i32 IntRegs:$src2)))))]>,
702 let AddedComplexity = 40, isPredicable = 1 in
703 def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
704 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
705 "$dst=memuh($src1+$src2<<#$offset)",
706 [(set (i32 IntRegs:$dst),
707 (i32 (extloadi16 (add (i32 IntRegs:$src1),
708 (shl (i32 IntRegs:$src2),
709 u2ImmPred:$offset)))))]>,
712 //// Load halfword conditionally.
713 // if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2)
714 // if (Pv) Rd=memh(Rs+Rt<<#u2)
715 let AddedComplexity = 15, isPredicated = 1 in
716 def LDrih_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
717 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
718 "if ($src1) $dst=memh($src2+$src3<<#0)",
722 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
723 let AddedComplexity = 15, isPredicated = 1 in
724 def LDrih_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
725 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
726 "if ($src1.new) $dst=memh($src2+$src3<<#0)",
730 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
731 let AddedComplexity = 15, isPredicated = 1 in
732 def LDrih_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
733 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
734 "if (!$src1) $dst=memh($src2+$src3<<#0)",
738 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
739 let AddedComplexity = 15, isPredicated = 1 in
740 def LDrih_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
741 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
742 "if (!$src1.new) $dst=memh($src2+$src3<<#0)",
746 //// Load unsigned halfword conditionally.
747 // if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2)
748 // if (Pv) Rd=memuh(Rs+Rt<<#u2)
749 let AddedComplexity = 15, isPredicated = 1 in
750 def LDriuh_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
751 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
752 "if ($src1) $dst=memuh($src2+$src3<<#0)",
756 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
757 let AddedComplexity = 15, isPredicated = 1 in
758 def LDriuh_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
759 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
760 "if ($src1.new) $dst=memuh($src2+$src3<<#0)",
764 // if (!Pv) Rd=memuh(Rs+Rt<<#u2)
765 let AddedComplexity = 15, isPredicated = 1 in
766 def LDriuh_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
767 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
768 "if (!$src1) $dst=memuh($src2+$src3<<#0)",
772 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
773 let AddedComplexity = 15, isPredicated = 1 in
774 def LDriuh_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
775 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
776 "if (!$src1.new) $dst=memuh($src2+$src3<<#0)",
780 // Rd=memh(Rt<<#u2+#U6)
783 // Load predicate: Fix for bug 5279.
784 let neverHasSideEffects = 1 in
785 def LDriw_pred_V4 : LDInst2<(outs PredRegs:$dst),
787 "Error; should not emit",
793 // Rd=memw(Rs+Rt<<#u2)
794 let AddedComplexity = 10, isPredicable = 1 in
795 def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst),
796 (ins IntRegs:$src1, IntRegs:$src2),
797 "$dst=memw($src1+$src2<<#0)",
798 [(set (i32 IntRegs:$dst),
799 (i32 (load (add (i32 IntRegs:$src1),
800 (i32 IntRegs:$src2)))))]>,
803 //// Load word conditionally.
804 // if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2)
805 // if (Pv) Rd=memw(Rs+Rt<<#u2)
806 let AddedComplexity = 15, isPredicated = 1 in
807 def LDriw_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
808 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
809 "if ($src1) $dst=memw($src2+$src3<<#0)",
813 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
814 let AddedComplexity = 15, isPredicated = 1 in
815 def LDriw_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
816 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
817 "if ($src1.new) $dst=memw($src2+$src3<<#0)",
821 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
822 let AddedComplexity = 15, isPredicated = 1 in
823 def LDriw_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
824 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
825 "if (!$src1) $dst=memw($src2+$src3<<#0)",
829 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
830 let AddedComplexity = 15, isPredicated = 1 in
831 def LDriw_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
832 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
833 "if (!$src1.new) $dst=memw($src2+$src3<<#0)",
837 /// Load from global offset
839 let isPredicable = 1, neverHasSideEffects = 1 in
840 def LDrid_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
841 (ins globaladdress:$global, u16Imm:$offset),
842 "$dst=memd(#$global+$offset)",
846 let neverHasSideEffects = 1, isPredicated = 1 in
847 def LDrid_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
848 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
849 "if ($src1) $dst=memd(##$global+$offset)",
853 let neverHasSideEffects = 1, isPredicated = 1 in
854 def LDrid_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
855 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
856 "if (!$src1) $dst=memd(##$global+$offset)",
860 let neverHasSideEffects = 1, isPredicated = 1 in
861 def LDrid_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
862 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
863 "if ($src1.new) $dst=memd(##$global+$offset)",
867 let neverHasSideEffects = 1, isPredicated = 1 in
868 def LDrid_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
869 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
870 "if (!$src1.new) $dst=memd(##$global+$offset)",
874 let isPredicable = 1, neverHasSideEffects = 1 in
875 def LDrib_GP_V4 : LDInst2<(outs IntRegs:$dst),
876 (ins globaladdress:$global, u16Imm:$offset),
877 "$dst=memb(#$global+$offset)",
881 let neverHasSideEffects = 1, isPredicated = 1 in
882 def LDrib_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
883 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
884 "if ($src1) $dst=memb(##$global+$offset)",
888 let neverHasSideEffects = 1, isPredicated = 1 in
889 def LDrib_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
890 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
891 "if (!$src1) $dst=memb(##$global+$offset)",
895 let neverHasSideEffects = 1, isPredicated = 1 in
896 def LDrib_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
897 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
898 "if ($src1.new) $dst=memb(##$global+$offset)",
902 let neverHasSideEffects = 1, isPredicated = 1 in
903 def LDrib_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
904 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
905 "if (!$src1.new) $dst=memb(##$global+$offset)",
910 let isPredicable = 1, neverHasSideEffects = 1 in
911 def LDriub_GP_V4 : LDInst2<(outs IntRegs:$dst),
912 (ins globaladdress:$global, u16Imm:$offset),
913 "$dst=memub(#$global+$offset)",
918 let neverHasSideEffects = 1, isPredicated = 1 in
919 def LDriub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
920 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
921 "if ($src1) $dst=memub(##$global+$offset)",
925 let neverHasSideEffects = 1, isPredicated = 1 in
926 def LDriub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
927 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
928 "if (!$src1) $dst=memub(##$global+$offset)",
932 let neverHasSideEffects = 1, isPredicated = 1 in
933 def LDriub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
934 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
935 "if ($src1.new) $dst=memub(##$global+$offset)",
939 let neverHasSideEffects = 1, isPredicated = 1 in
940 def LDriub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
941 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
942 "if (!$src1.new) $dst=memub(##$global+$offset)",
947 let isPredicable = 1, neverHasSideEffects = 1 in
948 def LDrih_GP_V4 : LDInst2<(outs IntRegs:$dst),
949 (ins globaladdress:$global, u16Imm:$offset),
950 "$dst=memh(#$global+$offset)",
955 let neverHasSideEffects = 1, isPredicated = 1 in
956 def LDrih_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
957 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
958 "if ($src1) $dst=memh(##$global+$offset)",
962 let neverHasSideEffects = 1, isPredicated = 1 in
963 def LDrih_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
964 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
965 "if (!$src1) $dst=memh(##$global+$offset)",
969 let neverHasSideEffects = 1, isPredicated = 1 in
970 def LDrih_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
971 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
972 "if ($src1.new) $dst=memh(##$global+$offset)",
976 let neverHasSideEffects = 1, isPredicated = 1 in
977 def LDrih_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
978 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
979 "if (!$src1.new) $dst=memh(##$global+$offset)",
984 let isPredicable = 1, neverHasSideEffects = 1 in
985 def LDriuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
986 (ins globaladdress:$global, u16Imm:$offset),
987 "$dst=memuh(#$global+$offset)",
991 let neverHasSideEffects = 1, isPredicated = 1 in
992 def LDriuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
993 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
994 "if ($src1) $dst=memuh(##$global+$offset)",
998 let neverHasSideEffects = 1, isPredicated = 1 in
999 def LDriuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1000 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1001 "if (!$src1) $dst=memuh(##$global+$offset)",
1005 let neverHasSideEffects = 1, isPredicated = 1 in
1006 def LDriuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1007 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1008 "if ($src1.new) $dst=memuh(##$global+$offset)",
1012 let neverHasSideEffects = 1, isPredicated = 1 in
1013 def LDriuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1014 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1015 "if (!$src1.new) $dst=memuh(##$global+$offset)",
1019 let isPredicable = 1, neverHasSideEffects = 1 in
1020 def LDriw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1021 (ins globaladdress:$global, u16Imm:$offset),
1022 "$dst=memw(#$global+$offset)",
1027 let neverHasSideEffects = 1, isPredicated = 1 in
1028 def LDriw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1029 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1030 "if ($src1) $dst=memw(##$global+$offset)",
1034 let neverHasSideEffects = 1, isPredicated = 1 in
1035 def LDriw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1036 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1037 "if (!$src1) $dst=memw(##$global+$offset)",
1042 let neverHasSideEffects = 1, isPredicated = 1 in
1043 def LDriw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1044 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1045 "if ($src1.new) $dst=memw(##$global+$offset)",
1049 let neverHasSideEffects = 1, isPredicated = 1 in
1050 def LDriw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1051 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1052 "if (!$src1.new) $dst=memw(##$global+$offset)",
1057 let isPredicable = 1, neverHasSideEffects = 1 in
1058 def LDd_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
1059 (ins globaladdress:$global),
1060 "$dst=memd(#$global)",
1064 // if (Pv) Rtt=memd(##global)
1065 let neverHasSideEffects = 1, isPredicated = 1 in
1066 def LDd_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1067 (ins PredRegs:$src1, globaladdress:$global),
1068 "if ($src1) $dst=memd(##$global)",
1073 // if (!Pv) Rtt=memd(##global)
1074 let neverHasSideEffects = 1, isPredicated = 1 in
1075 def LDd_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1076 (ins PredRegs:$src1, globaladdress:$global),
1077 "if (!$src1) $dst=memd(##$global)",
1081 // if (Pv) Rtt=memd(##global)
1082 let neverHasSideEffects = 1, isPredicated = 1 in
1083 def LDd_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1084 (ins PredRegs:$src1, globaladdress:$global),
1085 "if ($src1.new) $dst=memd(##$global)",
1090 // if (!Pv) Rtt=memd(##global)
1091 let neverHasSideEffects = 1, isPredicated = 1 in
1092 def LDd_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1093 (ins PredRegs:$src1, globaladdress:$global),
1094 "if (!$src1.new) $dst=memd(##$global)",
1098 let isPredicable = 1, neverHasSideEffects = 1 in
1099 def LDb_GP_V4 : LDInst2<(outs IntRegs:$dst),
1100 (ins globaladdress:$global),
1101 "$dst=memb(#$global)",
1105 // if (Pv) Rt=memb(##global)
1106 let neverHasSideEffects = 1, isPredicated = 1 in
1107 def LDb_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1108 (ins PredRegs:$src1, globaladdress:$global),
1109 "if ($src1) $dst=memb(##$global)",
1113 // if (!Pv) Rt=memb(##global)
1114 let neverHasSideEffects = 1, isPredicated = 1 in
1115 def LDb_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1116 (ins PredRegs:$src1, globaladdress:$global),
1117 "if (!$src1) $dst=memb(##$global)",
1121 // if (Pv) Rt=memb(##global)
1122 let neverHasSideEffects = 1, isPredicated = 1 in
1123 def LDb_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1124 (ins PredRegs:$src1, globaladdress:$global),
1125 "if ($src1.new) $dst=memb(##$global)",
1129 // if (!Pv) Rt=memb(##global)
1130 let neverHasSideEffects = 1, isPredicated = 1 in
1131 def LDb_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1132 (ins PredRegs:$src1, globaladdress:$global),
1133 "if (!$src1.new) $dst=memb(##$global)",
1137 let isPredicable = 1, neverHasSideEffects = 1 in
1138 def LDub_GP_V4 : LDInst2<(outs IntRegs:$dst),
1139 (ins globaladdress:$global),
1140 "$dst=memub(#$global)",
1144 // if (Pv) Rt=memub(##global)
1145 let neverHasSideEffects = 1, isPredicated = 1 in
1146 def LDub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1147 (ins PredRegs:$src1, globaladdress:$global),
1148 "if ($src1) $dst=memub(##$global)",
1153 // if (!Pv) Rt=memub(##global)
1154 let neverHasSideEffects = 1, isPredicated = 1 in
1155 def LDub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1156 (ins PredRegs:$src1, globaladdress:$global),
1157 "if (!$src1) $dst=memub(##$global)",
1161 // if (Pv) Rt=memub(##global)
1162 let neverHasSideEffects = 1, isPredicated = 1 in
1163 def LDub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1164 (ins PredRegs:$src1, globaladdress:$global),
1165 "if ($src1.new) $dst=memub(##$global)",
1170 // if (!Pv) Rt=memub(##global)
1171 let neverHasSideEffects = 1, isPredicated = 1 in
1172 def LDub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1173 (ins PredRegs:$src1, globaladdress:$global),
1174 "if (!$src1.new) $dst=memub(##$global)",
1178 let isPredicable = 1, neverHasSideEffects = 1 in
1179 def LDh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1180 (ins globaladdress:$global),
1181 "$dst=memh(#$global)",
1185 // if (Pv) Rt=memh(##global)
1186 let neverHasSideEffects = 1, isPredicated = 1 in
1187 def LDh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1188 (ins PredRegs:$src1, globaladdress:$global),
1189 "if ($src1) $dst=memh(##$global)",
1193 // if (!Pv) Rt=memh(##global)
1194 let neverHasSideEffects = 1, isPredicated = 1 in
1195 def LDh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1196 (ins PredRegs:$src1, globaladdress:$global),
1197 "if (!$src1) $dst=memh(##$global)",
1201 // if (Pv) Rt=memh(##global)
1202 let neverHasSideEffects = 1, isPredicated = 1 in
1203 def LDh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1204 (ins PredRegs:$src1, globaladdress:$global),
1205 "if ($src1.new) $dst=memh(##$global)",
1209 // if (!Pv) Rt=memh(##global)
1210 let neverHasSideEffects = 1, isPredicated = 1 in
1211 def LDh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1212 (ins PredRegs:$src1, globaladdress:$global),
1213 "if (!$src1.new) $dst=memh(##$global)",
1217 let isPredicable = 1, neverHasSideEffects = 1 in
1218 def LDuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1219 (ins globaladdress:$global),
1220 "$dst=memuh(#$global)",
1224 // if (Pv) Rt=memuh(##global)
1225 let neverHasSideEffects = 1, isPredicated = 1 in
1226 def LDuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1227 (ins PredRegs:$src1, globaladdress:$global),
1228 "if ($src1) $dst=memuh(##$global)",
1232 // if (!Pv) Rt=memuh(##global)
1233 let neverHasSideEffects = 1, isPredicated = 1 in
1234 def LDuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1235 (ins PredRegs:$src1, globaladdress:$global),
1236 "if (!$src1) $dst=memuh(##$global)",
1240 // if (Pv) Rt=memuh(##global)
1241 let neverHasSideEffects = 1, isPredicated = 1 in
1242 def LDuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1243 (ins PredRegs:$src1, globaladdress:$global),
1244 "if ($src1.new) $dst=memuh(##$global)",
1248 // if (!Pv) Rt=memuh(##global)
1249 let neverHasSideEffects = 1, isPredicated = 1 in
1250 def LDuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1251 (ins PredRegs:$src1, globaladdress:$global),
1252 "if (!$src1.new) $dst=memuh(##$global)",
1256 let isPredicable = 1, neverHasSideEffects = 1 in
1257 def LDw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1258 (ins globaladdress:$global),
1259 "$dst=memw(#$global)",
1263 // if (Pv) Rt=memw(##global)
1264 let neverHasSideEffects = 1, isPredicated = 1 in
1265 def LDw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1266 (ins PredRegs:$src1, globaladdress:$global),
1267 "if ($src1) $dst=memw(##$global)",
1272 // if (!Pv) Rt=memw(##global)
1273 let neverHasSideEffects = 1, isPredicated = 1 in
1274 def LDw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1275 (ins PredRegs:$src1, globaladdress:$global),
1276 "if (!$src1) $dst=memw(##$global)",
1280 // if (Pv) Rt=memw(##global)
1281 let neverHasSideEffects = 1, isPredicated = 1 in
1282 def LDw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1283 (ins PredRegs:$src1, globaladdress:$global),
1284 "if ($src1.new) $dst=memw(##$global)",
1289 // if (!Pv) Rt=memw(##global)
1290 let neverHasSideEffects = 1, isPredicated = 1 in
1291 def LDw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1292 (ins PredRegs:$src1, globaladdress:$global),
1293 "if (!$src1.new) $dst=memw(##$global)",
1299 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
1300 (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1303 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
1304 (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1307 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
1308 (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1311 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
1312 (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1315 // Map from load(globaladdress) -> memw(#foo + 0)
1316 let AddedComplexity = 100 in
1317 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
1318 (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1321 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
1322 let AddedComplexity = 100 in
1323 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
1324 (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>,
1327 // When the Interprocedural Global Variable optimizer realizes that a certain
1328 // global variable takes only two constant values, it shrinks the global to
1329 // a boolean. Catch those loads here in the following 3 patterns.
1330 let AddedComplexity = 100 in
1331 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1332 (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1335 let AddedComplexity = 100 in
1336 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1337 (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1340 // Map from load(globaladdress) -> memb(#foo)
1341 let AddedComplexity = 100 in
1342 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1343 (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1346 // Map from load(globaladdress) -> memb(#foo)
1347 let AddedComplexity = 100 in
1348 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1349 (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1352 let AddedComplexity = 100 in
1353 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1354 (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1357 // Map from load(globaladdress) -> memub(#foo)
1358 let AddedComplexity = 100 in
1359 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1360 (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1363 // Map from load(globaladdress) -> memh(#foo)
1364 let AddedComplexity = 100 in
1365 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1366 (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1369 // Map from load(globaladdress) -> memh(#foo)
1370 let AddedComplexity = 100 in
1371 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1372 (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1375 // Map from load(globaladdress) -> memuh(#foo)
1376 let AddedComplexity = 100 in
1377 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1378 (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1381 // Map from load(globaladdress) -> memw(#foo)
1382 let AddedComplexity = 100 in
1383 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
1384 (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1387 def : Pat <(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
1388 u16ImmPred:$offset)),
1389 (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1392 def : Pat <(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
1393 u16ImmPred:$offset)),
1394 (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1397 def : Pat <(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
1398 u16ImmPred:$offset)),
1399 (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1402 def : Pat <(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
1403 u16ImmPred:$offset)),
1404 (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1407 // Map from load(globaladdress + x) -> memd(#foo + x)
1408 let AddedComplexity = 100 in
1409 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1410 u16ImmPred:$offset))),
1411 (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1414 // Map from load(globaladdress + x) -> memb(#foo + x)
1415 let AddedComplexity = 100 in
1416 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1417 u16ImmPred:$offset))),
1418 (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1421 // Map from load(globaladdress + x) -> memb(#foo + x)
1422 let AddedComplexity = 100 in
1423 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1424 u16ImmPred:$offset))),
1425 (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1428 // Map from load(globaladdress + x) -> memub(#foo + x)
1429 let AddedComplexity = 100 in
1430 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1431 u16ImmPred:$offset))),
1432 (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1435 // Map from load(globaladdress + x) -> memuh(#foo + x)
1436 let AddedComplexity = 100 in
1437 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1438 u16ImmPred:$offset))),
1439 (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1442 // Map from load(globaladdress + x) -> memh(#foo + x)
1443 let AddedComplexity = 100 in
1444 def : Pat <(i32 (sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1445 u16ImmPred:$offset))),
1446 (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1450 // Map from load(globaladdress + x) -> memuh(#foo + x)
1451 let AddedComplexity = 100 in
1452 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1453 u16ImmPred:$offset))),
1454 (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1457 // Map from load(globaladdress + x) -> memw(#foo + x)
1458 let AddedComplexity = 100 in
1459 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1460 u16ImmPred:$offset))),
1461 (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1465 //===----------------------------------------------------------------------===//
1467 //===----------------------------------------------------------------------===//
1469 //===----------------------------------------------------------------------===//
1471 //===----------------------------------------------------------------------===//
1473 /// Assumptions::: ****** DO NOT IGNORE ********
1474 /// 1. Make sure that in post increment store, the zero'th operand is always the
1475 /// post increment operand.
1476 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1481 def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1482 (ins DoubleRegs:$src1, u6Imm:$src2),
1483 "memd($dst1=#$src2) = $src1",
1488 def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1489 (ins IntRegs:$src1, u6Imm:$src2),
1490 "memb($dst1=#$src2) = $src1",
1495 def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1496 (ins IntRegs:$src1, u6Imm:$src2),
1497 "memh($dst1=#$src2) = $src1",
1502 def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1503 (ins IntRegs:$src1, u6Imm:$src2),
1504 "memw($dst1=#$src2) = $src1",
1509 def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1510 (ins DoubleRegs:$src1, globaladdress:$src2),
1511 "memd($dst1=##$src2) = $src1",
1516 def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1517 (ins IntRegs:$src1, globaladdress:$src2),
1518 "memb($dst1=##$src2) = $src1",
1523 def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1524 (ins IntRegs:$src1, globaladdress:$src2),
1525 "memh($dst1=##$src2) = $src1",
1530 def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1531 (ins IntRegs:$src1, globaladdress:$src2),
1532 "memw($dst1=##$src2) = $src1",
1536 // memd(Rs+Ru<<#u2)=Rtt
1537 let AddedComplexity = 10, isPredicable = 1 in
1538 def STrid_indexed_shl_V4 : STInst<(outs),
1539 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, DoubleRegs:$src4),
1540 "memd($src1+$src2<<#$src3) = $src4",
1541 [(store (i64 DoubleRegs:$src4),
1542 (add (i32 IntRegs:$src1),
1543 (shl (i32 IntRegs:$src2), u2ImmPred:$src3)))]>,
1546 // memd(Ru<<#u2+#U6)=Rtt
1547 let AddedComplexity = 10 in
1548 def STrid_shl_V4 : STInst<(outs),
1549 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),
1550 "memd($src1<<#$src2+#$src3) = $src4",
1551 [(store (i64 DoubleRegs:$src4),
1552 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1553 u6ImmPred:$src3))]>,
1556 // memd(Rx++#s4:3)=Rtt
1557 // memd(Rx++#s4:3:circ(Mu))=Rtt
1558 // memd(Rx++I:circ(Mu))=Rtt
1560 // memd(Rx++Mu:brev)=Rtt
1561 // memd(gp+#u16:3)=Rtt
1563 // Store doubleword conditionally.
1564 // if ([!]Pv[.new]) memd(#u6)=Rtt
1565 // TODO: needs to be implemented.
1567 // if ([!]Pv[.new]) memd(Rs+Ru<<#u2)=Rtt
1568 // if (Pv) memd(Rs+Ru<<#u2)=Rtt
1569 let AddedComplexity = 10, neverHasSideEffects = 1,
1571 def STrid_indexed_shl_cPt_V4 : STInst2<(outs),
1572 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1574 "if ($src1) memd($src2+$src3<<#$src4) = $src5",
1578 // if (Pv.new) memd(Rs+Ru<<#u2)=Rtt
1579 let AddedComplexity = 10, neverHasSideEffects = 1,
1581 def STrid_indexed_shl_cdnPt_V4 : STInst2<(outs),
1582 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1584 "if ($src1.new) memd($src2+$src3<<#$src4) = $src5",
1587 // if (!Pv) memd(Rs+Ru<<#u2)=Rtt
1588 let AddedComplexity = 10, neverHasSideEffects = 1,
1590 def STrid_indexed_shl_cNotPt_V4 : STInst2<(outs),
1591 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1593 "if (!$src1) memd($src2+$src3<<#$src4) = $src5",
1596 // if (!Pv.new) memd(Rs+Ru<<#u2)=Rtt
1597 let AddedComplexity = 10, neverHasSideEffects = 1,
1599 def STrid_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
1600 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1602 "if (!$src1.new) memd($src2+$src3<<#$src4) = $src5",
1606 // if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt
1607 // if (Pv) memd(Rx++#s4:3)=Rtt
1608 // if (Pv.new) memd(Rx++#s4:3)=Rtt
1609 let AddedComplexity = 10, neverHasSideEffects = 1,
1611 def POST_STdri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1612 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1614 "if ($src1.new) memd($src3++#$offset) = $src2",
1619 // if (!Pv) memd(Rx++#s4:3)=Rtt
1620 // if (!Pv.new) memd(Rx++#s4:3)=Rtt
1621 let AddedComplexity = 10, neverHasSideEffects = 1,
1623 def POST_STdri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1624 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1626 "if (!$src1.new) memd($src3++#$offset) = $src2",
1633 // memb(Rs+#u6:0)=#S8
1634 let AddedComplexity = 10, isPredicable = 1 in
1635 def STrib_imm_V4 : STInst<(outs),
1636 (ins IntRegs:$src1, u6_0Imm:$src2, s8Imm:$src3),
1637 "memb($src1+#$src2) = #$src3",
1638 [(truncstorei8 s8ImmPred:$src3, (add (i32 IntRegs:$src1),
1639 u6_0ImmPred:$src2))]>,
1642 // memb(Rs+Ru<<#u2)=Rt
1643 let AddedComplexity = 10, isPredicable = 1 in
1644 def STrib_indexed_shl_V4 : STInst<(outs),
1645 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1646 "memb($src1+$src2<<#$src3) = $src4",
1647 [(truncstorei8 (i32 IntRegs:$src4),
1648 (add (i32 IntRegs:$src1),
1649 (shl (i32 IntRegs:$src2),
1650 u2ImmPred:$src3)))]>,
1653 // memb(Ru<<#u2+#U6)=Rt
1654 let AddedComplexity = 10 in
1655 def STrib_shl_V4 : STInst<(outs),
1656 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1657 "memb($src1<<#$src2+#$src3) = $src4",
1658 [(truncstorei8 (i32 IntRegs:$src4),
1659 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1660 u6ImmPred:$src3))]>,
1663 // memb(Rx++#s4:0:circ(Mu))=Rt
1664 // memb(Rx++I:circ(Mu))=Rt
1666 // memb(Rx++Mu:brev)=Rt
1667 // memb(gp+#u16:0)=Rt
1670 // Store byte conditionally.
1671 // if ([!]Pv[.new]) memb(#u6)=Rt
1672 // if ([!]Pv[.new]) memb(Rs+#u6:0)=#S6
1673 // if (Pv) memb(Rs+#u6:0)=#S6
1674 let neverHasSideEffects = 1,
1676 def STrib_imm_cPt_V4 : STInst2<(outs),
1677 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1678 "if ($src1) memb($src2+#$src3) = #$src4",
1682 // if (Pv.new) memb(Rs+#u6:0)=#S6
1683 let neverHasSideEffects = 1,
1685 def STrib_imm_cdnPt_V4 : STInst2<(outs),
1686 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1687 "if ($src1.new) memb($src2+#$src3) = #$src4",
1691 // if (!Pv) memb(Rs+#u6:0)=#S6
1692 let neverHasSideEffects = 1,
1694 def STrib_imm_cNotPt_V4 : STInst2<(outs),
1695 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1696 "if (!$src1) memb($src2+#$src3) = #$src4",
1700 // if (!Pv.new) memb(Rs+#u6:0)=#S6
1701 let neverHasSideEffects = 1,
1703 def STrib_imm_cdnNotPt_V4 : STInst2<(outs),
1704 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1705 "if (!$src1.new) memb($src2+#$src3) = #$src4",
1709 // if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Rt
1710 // if (Pv) memb(Rs+Ru<<#u2)=Rt
1711 let AddedComplexity = 10,
1713 def STrib_indexed_shl_cPt_V4 : STInst2<(outs),
1714 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1716 "if ($src1) memb($src2+$src3<<#$src4) = $src5",
1720 // if (Pv.new) memb(Rs+Ru<<#u2)=Rt
1721 let AddedComplexity = 10,
1723 def STrib_indexed_shl_cdnPt_V4 : STInst2<(outs),
1724 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1726 "if ($src1.new) memb($src2+$src3<<#$src4) = $src5",
1730 // if (!Pv) memb(Rs+Ru<<#u2)=Rt
1731 let AddedComplexity = 10,
1733 def STrib_indexed_shl_cNotPt_V4 : STInst2<(outs),
1734 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1736 "if (!$src1) memb($src2+$src3<<#$src4) = $src5",
1740 // if (!Pv.new) memb(Rs+Ru<<#u2)=Rt
1741 let AddedComplexity = 10,
1743 def STrib_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
1744 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1746 "if (!$src1.new) memb($src2+$src3<<#$src4) = $src5",
1750 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt
1751 // if (Pv) memb(Rx++#s4:0)=Rt
1752 // if (Pv.new) memb(Rx++#s4:0)=Rt
1755 def POST_STbri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1756 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1757 "if ($src1.new) memb($src3++#$offset) = $src2",
1761 // if (!Pv) memb(Rx++#s4:0)=Rt
1762 // if (!Pv.new) memb(Rx++#s4:0)=Rt
1765 def POST_STbri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1766 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1767 "if (!$src1.new) memb($src3++#$offset) = $src2",
1773 // TODO: needs to be implemented
1774 // memh(Re=#U6)=Rt.H
1775 // memh(Rs+#s11:1)=Rt.H
1776 // memh(Rs+#u6:1)=#S8
1777 let AddedComplexity = 10, isPredicable = 1 in
1778 def STrih_imm_V4 : STInst<(outs),
1779 (ins IntRegs:$src1, u6_1Imm:$src2, s8Imm:$src3),
1780 "memh($src1+#$src2) = #$src3",
1781 [(truncstorei16 s8ImmPred:$src3, (add (i32 IntRegs:$src1),
1782 u6_1ImmPred:$src2))]>,
1785 // memh(Rs+Ru<<#u2)=Rt.H
1786 // TODO: needs to be implemented.
1788 // memh(Rs+Ru<<#u2)=Rt
1789 let AddedComplexity = 10, isPredicable = 1 in
1790 def STrih_indexed_shl_V4 : STInst<(outs),
1791 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1792 "memh($src1+$src2<<#$src3) = $src4",
1793 [(truncstorei16 (i32 IntRegs:$src4),
1794 (add (i32 IntRegs:$src1),
1795 (shl (i32 IntRegs:$src2),
1796 u2ImmPred:$src3)))]>,
1799 // memh(Ru<<#u2+#U6)=Rt.H
1800 // memh(Ru<<#u2+#U6)=Rt
1801 let AddedComplexity = 10 in
1802 def STrih_shl_V4 : STInst<(outs),
1803 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1804 "memh($src1<<#$src2+#$src3) = $src4",
1805 [(truncstorei16 (i32 IntRegs:$src4),
1806 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1807 u6ImmPred:$src3))]>,
1810 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1811 // memh(Rx++#s4:1:circ(Mu))=Rt
1812 // memh(Rx++I:circ(Mu))=Rt.H
1813 // memh(Rx++I:circ(Mu))=Rt
1814 // memh(Rx++Mu)=Rt.H
1816 // memh(Rx++Mu:brev)=Rt.H
1817 // memh(Rx++Mu:brev)=Rt
1818 // memh(gp+#u16:1)=Rt
1819 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1820 // if ([!]Pv[.new]) memh(#u6)=Rt
1822 // if ([!]Pv[.new]) memh(Rs+#u6:1)=#S6
1823 // if (Pv) memh(Rs+#u6:1)=#S6
1824 let neverHasSideEffects = 1,
1826 def STrih_imm_cPt_V4 : STInst2<(outs),
1827 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1828 "if ($src1) memh($src2+#$src3) = #$src4",
1832 // if (Pv.new) memh(Rs+#u6:1)=#S6
1833 let neverHasSideEffects = 1,
1835 def STrih_imm_cdnPt_V4 : STInst2<(outs),
1836 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1837 "if ($src1.new) memh($src2+#$src3) = #$src4",
1841 // if (!Pv) memh(Rs+#u6:1)=#S6
1842 let neverHasSideEffects = 1,
1844 def STrih_imm_cNotPt_V4 : STInst2<(outs),
1845 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1846 "if (!$src1) memh($src2+#$src3) = #$src4",
1850 // if (!Pv.new) memh(Rs+#u6:1)=#S6
1851 let neverHasSideEffects = 1,
1853 def STrih_imm_cdnNotPt_V4 : STInst2<(outs),
1854 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1855 "if (!$src1.new) memh($src2+#$src3) = #$src4",
1859 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1860 // TODO: needs to be implemented.
1862 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt.H
1863 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt
1864 // if (Pv) memh(Rs+Ru<<#u2)=Rt
1865 let AddedComplexity = 10,
1867 def STrih_indexed_shl_cPt_V4 : STInst2<(outs),
1868 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1870 "if ($src1) memh($src2+$src3<<#$src4) = $src5",
1874 // if (Pv.new) memh(Rs+Ru<<#u2)=Rt
1875 let AddedComplexity = 10,
1877 def STrih_indexed_shl_cdnPt_V4 : STInst2<(outs),
1878 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1880 "if ($src1.new) memh($src2+$src3<<#$src4) = $src5",
1884 // if (!Pv) memh(Rs+Ru<<#u2)=Rt
1885 let AddedComplexity = 10,
1887 def STrih_indexed_shl_cNotPt_V4 : STInst2<(outs),
1888 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1890 "if (!$src1) memh($src2+$src3<<#$src4) = $src5",
1894 // if (!Pv.new) memh(Rs+Ru<<#u2)=Rt
1895 let AddedComplexity = 10,
1897 def STrih_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
1898 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1900 "if (!$src1.new) memh($src2+$src3<<#$src4) = $src5",
1904 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1905 // TODO: Needs to be implemented.
1907 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt
1908 // if (Pv) memh(Rx++#s4:1)=Rt
1909 // if (Pv.new) memh(Rx++#s4:1)=Rt
1912 def POST_SThri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1913 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1914 "if ($src1.new) memh($src3++#$offset) = $src2",
1918 // if (!Pv) memh(Rx++#s4:1)=Rt
1919 // if (!Pv.new) memh(Rx++#s4:1)=Rt
1922 def POST_SThri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1923 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1924 "if (!$src1.new) memh($src3++#$offset) = $src2",
1931 // TODO: Needs to be implemented.
1934 let neverHasSideEffects = 1 in
1935 def STriw_pred_V4 : STInst2<(outs),
1936 (ins MEMri:$addr, PredRegs:$src1),
1937 "Error; should not emit",
1942 // memw(Rs+#u6:2)=#S8
1943 let AddedComplexity = 10, isPredicable = 1 in
1944 def STriw_imm_V4 : STInst<(outs),
1945 (ins IntRegs:$src1, u6_2Imm:$src2, s8Imm:$src3),
1946 "memw($src1+#$src2) = #$src3",
1947 [(store s8ImmPred:$src3, (add (i32 IntRegs:$src1),
1948 u6_2ImmPred:$src2))]>,
1951 // memw(Rs+Ru<<#u2)=Rt
1952 let AddedComplexity = 10, isPredicable = 1 in
1953 def STriw_indexed_shl_V4 : STInst<(outs),
1954 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1955 "memw($src1+$src2<<#$src3) = $src4",
1956 [(store (i32 IntRegs:$src4), (add (i32 IntRegs:$src1),
1957 (shl (i32 IntRegs:$src2),
1958 u2ImmPred:$src3)))]>,
1961 // memw(Ru<<#u2+#U6)=Rt
1962 let AddedComplexity = 10 in
1963 def STriw_shl_V4 : STInst<(outs),
1964 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1965 "memw($src1<<#$src2+#$src3) = $src4",
1966 [(store (i32 IntRegs:$src4),
1967 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1968 u6ImmPred:$src3))]>,
1971 // memw(Rx++#s4:2)=Rt
1972 // memw(Rx++#s4:2:circ(Mu))=Rt
1973 // memw(Rx++I:circ(Mu))=Rt
1975 // memw(Rx++Mu:brev)=Rt
1976 // memw(gp+#u16:2)=Rt
1979 // Store word conditionally.
1981 // if ([!]Pv[.new]) memw(Rs+#u6:2)=#S6
1982 // if (Pv) memw(Rs+#u6:2)=#S6
1983 let neverHasSideEffects = 1,
1985 def STriw_imm_cPt_V4 : STInst2<(outs),
1986 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
1987 "if ($src1) memw($src2+#$src3) = #$src4",
1991 // if (Pv.new) memw(Rs+#u6:2)=#S6
1992 let neverHasSideEffects = 1,
1994 def STriw_imm_cdnPt_V4 : STInst2<(outs),
1995 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
1996 "if ($src1.new) memw($src2+#$src3) = #$src4",
2000 // if (!Pv) memw(Rs+#u6:2)=#S6
2001 let neverHasSideEffects = 1,
2003 def STriw_imm_cNotPt_V4 : STInst2<(outs),
2004 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
2005 "if (!$src1) memw($src2+#$src3) = #$src4",
2009 // if (!Pv.new) memw(Rs+#u6:2)=#S6
2010 let neverHasSideEffects = 1,
2012 def STriw_imm_cdnNotPt_V4 : STInst2<(outs),
2013 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
2014 "if (!$src1.new) memw($src2+#$src3) = #$src4",
2018 // if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Rt
2019 // if (Pv) memw(Rs+Ru<<#u2)=Rt
2020 let AddedComplexity = 10,
2022 def STriw_indexed_shl_cPt_V4 : STInst2<(outs),
2023 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2025 "if ($src1) memw($src2+$src3<<#$src4) = $src5",
2029 // if (Pv.new) memw(Rs+Ru<<#u2)=Rt
2030 let AddedComplexity = 10,
2032 def STriw_indexed_shl_cdnPt_V4 : STInst2<(outs),
2033 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2035 "if ($src1.new) memw($src2+$src3<<#$src4) = $src5",
2039 // if (!Pv) memw(Rs+Ru<<#u2)=Rt
2040 let AddedComplexity = 10,
2042 def STriw_indexed_shl_cNotPt_V4 : STInst2<(outs),
2043 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2045 "if (!$src1) memw($src2+$src3<<#$src4) = $src5",
2049 // if (!Pv.new) memw(Rs+Ru<<#u2)=Rt
2050 let AddedComplexity = 10,
2052 def STriw_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
2053 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2055 "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5",
2059 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt
2060 // if (Pv) memw(Rx++#s4:2)=Rt
2061 // if (Pv.new) memw(Rx++#s4:2)=Rt
2064 def POST_STwri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
2065 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2066 "if ($src1.new) memw($src3++#$offset) = $src2",
2070 // if (!Pv) memw(Rx++#s4:2)=Rt
2071 // if (!Pv.new) memw(Rx++#s4:2)=Rt
2074 def POST_STwri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
2075 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2076 "if (!$src1.new) memw($src3++#$offset) = $src2",
2081 /// store to global address
2083 let isPredicable = 1, neverHasSideEffects = 1 in
2084 def STrid_GP_V4 : STInst2<(outs),
2085 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
2086 "memd(#$global+$offset) = $src",
2090 let neverHasSideEffects = 1, isPredicated = 1 in
2091 def STrid_GP_cPt_V4 : STInst2<(outs),
2092 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2094 "if ($src1) memd(##$global+$offset) = $src2",
2098 let neverHasSideEffects = 1, isPredicated = 1 in
2099 def STrid_GP_cNotPt_V4 : STInst2<(outs),
2100 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2102 "if (!$src1) memd(##$global+$offset) = $src2",
2106 let neverHasSideEffects = 1, isPredicated = 1 in
2107 def STrid_GP_cdnPt_V4 : STInst2<(outs),
2108 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2110 "if ($src1.new) memd(##$global+$offset) = $src2",
2114 let neverHasSideEffects = 1, isPredicated = 1 in
2115 def STrid_GP_cdnNotPt_V4 : STInst2<(outs),
2116 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2118 "if (!$src1.new) memd(##$global+$offset) = $src2",
2122 let isPredicable = 1, neverHasSideEffects = 1 in
2123 def STrib_GP_V4 : STInst2<(outs),
2124 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2125 "memb(#$global+$offset) = $src",
2129 let neverHasSideEffects = 1, isPredicated = 1 in
2130 def STrib_GP_cPt_V4 : STInst2<(outs),
2131 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2133 "if ($src1) memb(##$global+$offset) = $src2",
2137 let neverHasSideEffects = 1, isPredicated = 1 in
2138 def STrib_GP_cNotPt_V4 : STInst2<(outs),
2139 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2141 "if (!$src1) memb(##$global+$offset) = $src2",
2145 let neverHasSideEffects = 1, isPredicated = 1 in
2146 def STrib_GP_cdnPt_V4 : STInst2<(outs),
2147 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2149 "if ($src1.new) memb(##$global+$offset) = $src2",
2153 let neverHasSideEffects = 1, isPredicated = 1 in
2154 def STrib_GP_cdnNotPt_V4 : STInst2<(outs),
2155 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2157 "if (!$src1.new) memb(##$global+$offset) = $src2",
2161 let isPredicable = 1, neverHasSideEffects = 1 in
2162 def STrih_GP_V4 : STInst2<(outs),
2163 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2164 "memh(#$global+$offset) = $src",
2168 let neverHasSideEffects = 1, isPredicated = 1 in
2169 def STrih_GP_cPt_V4 : STInst2<(outs),
2170 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2172 "if ($src1) memh(##$global+$offset) = $src2",
2176 let neverHasSideEffects = 1, isPredicated = 1 in
2177 def STrih_GP_cNotPt_V4 : STInst2<(outs),
2178 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2180 "if (!$src1) memh(##$global+$offset) = $src2",
2184 let neverHasSideEffects = 1, isPredicated = 1 in
2185 def STrih_GP_cdnPt_V4 : STInst2<(outs),
2186 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2188 "if ($src1.new) memh(##$global+$offset) = $src2",
2192 let neverHasSideEffects = 1, isPredicated = 1 in
2193 def STrih_GP_cdnNotPt_V4 : STInst2<(outs),
2194 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2196 "if (!$src1.new) memh(##$global+$offset) = $src2",
2200 let isPredicable = 1, neverHasSideEffects = 1 in
2201 def STriw_GP_V4 : STInst2<(outs),
2202 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2203 "memw(#$global+$offset) = $src",
2207 let neverHasSideEffects = 1, isPredicated = 1 in
2208 def STriw_GP_cPt_V4 : STInst2<(outs),
2209 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2211 "if ($src1) memw(##$global+$offset) = $src2",
2215 let neverHasSideEffects = 1, isPredicated = 1 in
2216 def STriw_GP_cNotPt_V4 : STInst2<(outs),
2217 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2219 "if (!$src1) memw(##$global+$offset) = $src2",
2223 let neverHasSideEffects = 1, isPredicated = 1 in
2224 def STriw_GP_cdnPt_V4 : STInst2<(outs),
2225 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2227 "if ($src1.new) memw(##$global+$offset) = $src2",
2231 let neverHasSideEffects = 1, isPredicated = 1 in
2232 def STriw_GP_cdnNotPt_V4 : STInst2<(outs),
2233 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2235 "if (!$src1.new) memw(##$global+$offset) = $src2",
2239 // memd(#global)=Rtt
2240 let isPredicable = 1, neverHasSideEffects = 1 in
2241 def STd_GP_V4 : STInst2<(outs),
2242 (ins globaladdress:$global, DoubleRegs:$src),
2243 "memd(#$global) = $src",
2247 // if (Pv) memd(##global) = Rtt
2248 let neverHasSideEffects = 1, isPredicated = 1 in
2249 def STd_GP_cPt_V4 : STInst2<(outs),
2250 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2251 "if ($src1) memd(##$global) = $src2",
2255 // if (!Pv) memd(##global) = Rtt
2256 let neverHasSideEffects = 1, isPredicated = 1 in
2257 def STd_GP_cNotPt_V4 : STInst2<(outs),
2258 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2259 "if (!$src1) memd(##$global) = $src2",
2263 // if (Pv) memd(##global) = Rtt
2264 let neverHasSideEffects = 1, isPredicated = 1 in
2265 def STd_GP_cdnPt_V4 : STInst2<(outs),
2266 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2267 "if ($src1.new) memd(##$global) = $src2",
2271 // if (!Pv) memd(##global) = Rtt
2272 let neverHasSideEffects = 1, isPredicated = 1 in
2273 def STd_GP_cdnNotPt_V4 : STInst2<(outs),
2274 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2275 "if (!$src1.new) memd(##$global) = $src2",
2280 let isPredicable = 1, neverHasSideEffects = 1 in
2281 def STb_GP_V4 : STInst2<(outs),
2282 (ins globaladdress:$global, IntRegs:$src),
2283 "memb(#$global) = $src",
2287 // if (Pv) memb(##global) = Rt
2288 let neverHasSideEffects = 1, isPredicated = 1 in
2289 def STb_GP_cPt_V4 : STInst2<(outs),
2290 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2291 "if ($src1) memb(##$global) = $src2",
2295 // if (!Pv) memb(##global) = Rt
2296 let neverHasSideEffects = 1, isPredicated = 1 in
2297 def STb_GP_cNotPt_V4 : STInst2<(outs),
2298 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2299 "if (!$src1) memb(##$global) = $src2",
2303 // if (Pv) memb(##global) = Rt
2304 let neverHasSideEffects = 1, isPredicated = 1 in
2305 def STb_GP_cdnPt_V4 : STInst2<(outs),
2306 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2307 "if ($src1.new) memb(##$global) = $src2",
2311 // if (!Pv) memb(##global) = Rt
2312 let neverHasSideEffects = 1, isPredicated = 1 in
2313 def STb_GP_cdnNotPt_V4 : STInst2<(outs),
2314 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2315 "if (!$src1.new) memb(##$global) = $src2",
2320 let isPredicable = 1, neverHasSideEffects = 1 in
2321 def STh_GP_V4 : STInst2<(outs),
2322 (ins globaladdress:$global, IntRegs:$src),
2323 "memh(#$global) = $src",
2327 // if (Pv) memh(##global) = Rt
2328 let neverHasSideEffects = 1, isPredicated = 1 in
2329 def STh_GP_cPt_V4 : STInst2<(outs),
2330 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2331 "if ($src1) memh(##$global) = $src2",
2335 // if (!Pv) memh(##global) = Rt
2336 let neverHasSideEffects = 1, isPredicated = 1 in
2337 def STh_GP_cNotPt_V4 : STInst2<(outs),
2338 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2339 "if (!$src1) memh(##$global) = $src2",
2343 // if (Pv) memh(##global) = Rt
2344 let neverHasSideEffects = 1, isPredicated = 1 in
2345 def STh_GP_cdnPt_V4 : STInst2<(outs),
2346 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2347 "if ($src1.new) memh(##$global) = $src2",
2351 // if (!Pv) memh(##global) = Rt
2352 let neverHasSideEffects = 1, isPredicated = 1 in
2353 def STh_GP_cdnNotPt_V4 : STInst2<(outs),
2354 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2355 "if (!$src1.new) memh(##$global) = $src2",
2360 let isPredicable = 1, neverHasSideEffects = 1 in
2361 def STw_GP_V4 : STInst2<(outs),
2362 (ins globaladdress:$global, IntRegs:$src),
2363 "memw(#$global) = $src",
2367 // if (Pv) memw(##global) = Rt
2368 let neverHasSideEffects = 1, isPredicated = 1 in
2369 def STw_GP_cPt_V4 : STInst2<(outs),
2370 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2371 "if ($src1) memw(##$global) = $src2",
2375 // if (!Pv) memw(##global) = Rt
2376 let neverHasSideEffects = 1, isPredicated = 1 in
2377 def STw_GP_cNotPt_V4 : STInst2<(outs),
2378 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2379 "if (!$src1) memw(##$global) = $src2",
2383 // if (Pv) memw(##global) = Rt
2384 let neverHasSideEffects = 1, isPredicated = 1 in
2385 def STw_GP_cdnPt_V4 : STInst2<(outs),
2386 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2387 "if ($src1.new) memw(##$global) = $src2",
2391 // if (!Pv) memw(##global) = Rt
2392 let neverHasSideEffects = 1, isPredicated = 1 in
2393 def STw_GP_cdnNotPt_V4 : STInst2<(outs),
2394 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2395 "if (!$src1.new) memw(##$global) = $src2",
2399 // 64 bit atomic store
2400 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2401 (i64 DoubleRegs:$src1)),
2402 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2405 // Map from store(globaladdress) -> memd(#foo)
2406 let AddedComplexity = 100 in
2407 def : Pat <(store (i64 DoubleRegs:$src1),
2408 (HexagonCONST32_GP tglobaladdr:$global)),
2409 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2412 // 8 bit atomic store
2413 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2414 (i32 IntRegs:$src1)),
2415 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2418 // Map from store(globaladdress) -> memb(#foo)
2419 let AddedComplexity = 100 in
2420 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2421 (HexagonCONST32_GP tglobaladdr:$global)),
2422 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2425 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
2426 // to "r0 = 1; memw(#foo) = r0"
2427 let AddedComplexity = 100 in
2428 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2429 (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>,
2432 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2433 (i32 IntRegs:$src1)),
2434 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2437 // Map from store(globaladdress) -> memh(#foo)
2438 let AddedComplexity = 100 in
2439 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2440 (HexagonCONST32_GP tglobaladdr:$global)),
2441 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2444 // 32 bit atomic store
2445 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2446 (i32 IntRegs:$src1)),
2447 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2450 // Map from store(globaladdress) -> memw(#foo)
2451 let AddedComplexity = 100 in
2452 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2453 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2456 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2457 u16ImmPred:$offset),
2458 (i64 DoubleRegs:$src1)),
2459 (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2460 (i64 DoubleRegs:$src1))>,
2463 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2464 u16ImmPred:$offset),
2465 (i32 IntRegs:$src1)),
2466 (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2467 (i32 IntRegs:$src1))>,
2470 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2471 u16ImmPred:$offset),
2472 (i32 IntRegs:$src1)),
2473 (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2474 (i32 IntRegs:$src1))>,
2477 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2478 u16ImmPred:$offset),
2479 (i32 IntRegs:$src1)),
2480 (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2481 (i32 IntRegs:$src1))>,
2484 // Map from store(globaladdress + x) -> memd(#foo + x)
2485 let AddedComplexity = 100 in
2486 def : Pat<(store (i64 DoubleRegs:$src1),
2487 (add (HexagonCONST32_GP tglobaladdr:$global),
2488 u16ImmPred:$offset)),
2489 (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2490 (i64 DoubleRegs:$src1))>,
2493 // Map from store(globaladdress + x) -> memb(#foo + x)
2494 let AddedComplexity = 100 in
2495 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2496 (add (HexagonCONST32_GP tglobaladdr:$global),
2497 u16ImmPred:$offset)),
2498 (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2499 (i32 IntRegs:$src1))>,
2502 // Map from store(globaladdress + x) -> memh(#foo + x)
2503 let AddedComplexity = 100 in
2504 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2505 (add (HexagonCONST32_GP tglobaladdr:$global),
2506 u16ImmPred:$offset)),
2507 (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2508 (i32 IntRegs:$src1))>,
2511 // Map from store(globaladdress + x) -> memw(#foo + x)
2512 let AddedComplexity = 100 in
2513 def : Pat<(store (i32 IntRegs:$src1),
2514 (add (HexagonCONST32_GP tglobaladdr:$global),
2515 u16ImmPred:$offset)),
2516 (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2517 (i32 IntRegs:$src1))>,
2522 //===----------------------------------------------------------------------===
2524 //===----------------------------------------------------------------------===
2527 //===----------------------------------------------------------------------===//
2529 //===----------------------------------------------------------------------===//
2531 // Store new-value byte.
2533 // memb(Re=#U6)=Nt.new
2534 // memb(Rs+#s11:0)=Nt.new
2535 let mayStore = 1, isPredicable = 1 in
2536 def STrib_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
2537 "memb($addr) = $src1.new",
2541 let mayStore = 1, isPredicable = 1 in
2542 def STrib_indexed_nv_V4 : NVInst_V4<(outs),
2543 (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
2544 "memb($src1+#$src2) = $src3.new",
2548 // memb(Rs+Ru<<#u2)=Nt.new
2549 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
2550 def STrib_indexed_shl_nv_V4 : NVInst_V4<(outs),
2551 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
2552 "memb($src1+$src2<<#$src3) = $src4.new",
2556 // memb(Ru<<#u2+#U6)=Nt.new
2557 let mayStore = 1, AddedComplexity = 10 in
2558 def STrib_shl_nv_V4 : NVInst_V4<(outs),
2559 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2560 "memb($src1<<#$src2+#$src3) = $src4.new",
2564 // memb(Rx++#s4:0)=Nt.new
2565 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
2566 def POST_STbri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2567 (ins IntRegs:$src1, IntRegs:$src2, s4_0Imm:$offset),
2568 "memb($src2++#$offset) = $src1.new",
2573 // memb(Rx++#s4:0:circ(Mu))=Nt.new
2574 // memb(Rx++I:circ(Mu))=Nt.new
2575 // memb(Rx++Mu)=Nt.new
2576 // memb(Rx++Mu:brev)=Nt.new
2578 // memb(gp+#u16:0)=Nt.new
2579 let mayStore = 1, neverHasSideEffects = 1 in
2580 def STrib_GP_nv_V4 : NVInst_V4<(outs),
2581 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2582 "memb(#$global+$offset) = $src.new",
2586 // memb(#global)=Nt.new
2587 let mayStore = 1, neverHasSideEffects = 1 in
2588 def STb_GP_nv_V4 : NVInst_V4<(outs),
2589 (ins globaladdress:$global, IntRegs:$src),
2590 "memb(#$global) = $src.new",
2594 // Store new-value byte conditionally.
2595 // if ([!]Pv[.new]) memb(#u6)=Nt.new
2596 // if (Pv) memb(Rs+#u6:0)=Nt.new
2597 let mayStore = 1, neverHasSideEffects = 1,
2599 def STrib_cPt_nv_V4 : NVInst_V4<(outs),
2600 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2601 "if ($src1) memb($addr) = $src2.new",
2605 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
2606 let mayStore = 1, neverHasSideEffects = 1,
2608 def STrib_cdnPt_nv_V4 : NVInst_V4<(outs),
2609 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2610 "if ($src1.new) memb($addr) = $src2.new",
2614 // if (!Pv) memb(Rs+#u6:0)=Nt.new
2615 let mayStore = 1, neverHasSideEffects = 1,
2617 def STrib_cNotPt_nv_V4 : NVInst_V4<(outs),
2618 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2619 "if (!$src1) memb($addr) = $src2.new",
2623 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
2624 let mayStore = 1, neverHasSideEffects = 1,
2626 def STrib_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2627 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2628 "if (!$src1.new) memb($addr) = $src2.new",
2632 // if (Pv) memb(Rs+#u6:0)=Nt.new
2633 let mayStore = 1, neverHasSideEffects = 1,
2635 def STrib_indexed_cPt_nv_V4 : NVInst_V4<(outs),
2636 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2637 "if ($src1) memb($src2+#$src3) = $src4.new",
2641 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
2642 let mayStore = 1, neverHasSideEffects = 1,
2644 def STrib_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
2645 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2646 "if ($src1.new) memb($src2+#$src3) = $src4.new",
2650 // if (!Pv) memb(Rs+#u6:0)=Nt.new
2651 let mayStore = 1, neverHasSideEffects = 1,
2653 def STrib_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
2654 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2655 "if (!$src1) memb($src2+#$src3) = $src4.new",
2659 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
2660 let mayStore = 1, neverHasSideEffects = 1,
2662 def STrib_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2663 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2664 "if (!$src1.new) memb($src2+#$src3) = $src4.new",
2669 // if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Nt.new
2670 // if (Pv) memb(Rs+Ru<<#u2)=Nt.new
2671 let mayStore = 1, AddedComplexity = 10,
2673 def STrib_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
2674 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2676 "if ($src1) memb($src2+$src3<<#$src4) = $src5.new",
2680 // if (Pv.new) memb(Rs+Ru<<#u2)=Nt.new
2681 let mayStore = 1, AddedComplexity = 10,
2683 def STrib_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
2684 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2686 "if ($src1.new) memb($src2+$src3<<#$src4) = $src5.new",
2690 // if (!Pv) memb(Rs+Ru<<#u2)=Nt.new
2691 let mayStore = 1, AddedComplexity = 10,
2693 def STrib_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
2694 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2696 "if (!$src1) memb($src2+$src3<<#$src4) = $src5.new",
2700 // if (!Pv.new) memb(Rs+Ru<<#u2)=Nt.new
2701 let mayStore = 1, AddedComplexity = 10,
2703 def STrib_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2704 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2706 "if (!$src1.new) memb($src2+$src3<<#$src4) = $src5.new",
2710 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new
2711 // if (Pv) memb(Rx++#s4:0)=Nt.new
2712 let mayStore = 1, hasCtrlDep = 1,
2714 def POST_STbri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2715 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2716 "if ($src1) memb($src3++#$offset) = $src2.new",
2720 // if (Pv.new) memb(Rx++#s4:0)=Nt.new
2721 let mayStore = 1, hasCtrlDep = 1,
2723 def POST_STbri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2724 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2725 "if ($src1.new) memb($src3++#$offset) = $src2.new",
2729 // if (!Pv) memb(Rx++#s4:0)=Nt.new
2730 let mayStore = 1, hasCtrlDep = 1,
2732 def POST_STbri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2733 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2734 "if (!$src1) memb($src3++#$offset) = $src2.new",
2738 // if (!Pv.new) memb(Rx++#s4:0)=Nt.new
2739 let mayStore = 1, hasCtrlDep = 1,
2741 def POST_STbri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2742 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2743 "if (!$src1.new) memb($src3++#$offset) = $src2.new",
2748 // Store new-value halfword.
2749 // memh(Re=#U6)=Nt.new
2750 // memh(Rs+#s11:1)=Nt.new
2751 let mayStore = 1, isPredicable = 1 in
2752 def STrih_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
2753 "memh($addr) = $src1.new",
2757 let mayStore = 1, isPredicable = 1 in
2758 def STrih_indexed_nv_V4 : NVInst_V4<(outs),
2759 (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
2760 "memh($src1+#$src2) = $src3.new",
2764 // memh(Rs+Ru<<#u2)=Nt.new
2765 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
2766 def STrih_indexed_shl_nv_V4 : NVInst_V4<(outs),
2767 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
2768 "memh($src1+$src2<<#$src3) = $src4.new",
2772 // memh(Ru<<#u2+#U6)=Nt.new
2773 let mayStore = 1, AddedComplexity = 10 in
2774 def STrih_shl_nv_V4 : NVInst_V4<(outs),
2775 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2776 "memh($src1<<#$src2+#$src3) = $src4.new",
2780 // memh(Rx++#s4:1)=Nt.new
2781 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
2782 def POST_SThri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2783 (ins IntRegs:$src1, IntRegs:$src2, s4_1Imm:$offset),
2784 "memh($src2++#$offset) = $src1.new",
2789 // memh(Rx++#s4:1:circ(Mu))=Nt.new
2790 // memh(Rx++I:circ(Mu))=Nt.new
2791 // memh(Rx++Mu)=Nt.new
2792 // memh(Rx++Mu:brev)=Nt.new
2794 // memh(gp+#u16:1)=Nt.new
2795 let mayStore = 1, neverHasSideEffects = 1 in
2796 def STrih_GP_nv_V4 : NVInst_V4<(outs),
2797 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2798 "memh(#$global+$offset) = $src.new",
2802 // memh(#global)=Nt.new
2803 let mayStore = 1, neverHasSideEffects = 1 in
2804 def STh_GP_nv_V4 : NVInst_V4<(outs),
2805 (ins globaladdress:$global, IntRegs:$src),
2806 "memh(#$global) = $src.new",
2811 // Store new-value halfword conditionally.
2813 // if ([!]Pv[.new]) memh(#u6)=Nt.new
2815 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Nt.new
2816 // if (Pv) memh(Rs+#u6:1)=Nt.new
2817 let mayStore = 1, neverHasSideEffects = 1,
2819 def STrih_cPt_nv_V4 : NVInst_V4<(outs),
2820 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2821 "if ($src1) memh($addr) = $src2.new",
2825 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
2826 let mayStore = 1, neverHasSideEffects = 1,
2828 def STrih_cdnPt_nv_V4 : NVInst_V4<(outs),
2829 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2830 "if ($src1.new) memh($addr) = $src2.new",
2834 // if (!Pv) memh(Rs+#u6:1)=Nt.new
2835 let mayStore = 1, neverHasSideEffects = 1,
2837 def STrih_cNotPt_nv_V4 : NVInst_V4<(outs),
2838 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2839 "if (!$src1) memh($addr) = $src2.new",
2843 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
2844 let mayStore = 1, neverHasSideEffects = 1,
2846 def STrih_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2847 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2848 "if (!$src1.new) memh($addr) = $src2.new",
2852 // if (Pv) memh(Rs+#u6:1)=Nt.new
2853 let mayStore = 1, neverHasSideEffects = 1,
2855 def STrih_indexed_cPt_nv_V4 : NVInst_V4<(outs),
2856 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2857 "if ($src1) memh($src2+#$src3) = $src4.new",
2861 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
2862 let mayStore = 1, neverHasSideEffects = 1,
2864 def STrih_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
2865 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2866 "if ($src1.new) memh($src2+#$src3) = $src4.new",
2870 // if (!Pv) memh(Rs+#u6:1)=Nt.new
2871 let mayStore = 1, neverHasSideEffects = 1,
2873 def STrih_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
2874 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2875 "if (!$src1) memh($src2+#$src3) = $src4.new",
2879 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
2880 let mayStore = 1, neverHasSideEffects = 1,
2882 def STrih_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2883 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2884 "if (!$src1.new) memh($src2+#$src3) = $src4.new",
2888 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Nt.new
2889 // if (Pv) memh(Rs+Ru<<#u2)=Nt.new
2890 let mayStore = 1, AddedComplexity = 10,
2892 def STrih_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
2893 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2895 "if ($src1) memh($src2+$src3<<#$src4) = $src5.new",
2899 // if (Pv.new) memh(Rs+Ru<<#u2)=Nt.new
2900 let mayStore = 1, AddedComplexity = 10,
2902 def STrih_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
2903 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2905 "if ($src1.new) memh($src2+$src3<<#$src4) = $src5.new",
2909 // if (!Pv) memh(Rs+Ru<<#u2)=Nt.new
2910 let mayStore = 1, AddedComplexity = 10,
2912 def STrih_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
2913 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2915 "if (!$src1) memh($src2+$src3<<#$src4) = $src5.new",
2919 // if (!Pv.new) memh(Rs+Ru<<#u2)=Nt.new
2920 let mayStore = 1, AddedComplexity = 10,
2922 def STrih_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2923 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2925 "if (!$src1.new) memh($src2+$src3<<#$src4) = $src5.new",
2929 // if ([!]Pv[]) memh(Rx++#s4:1)=Nt.new
2930 // if (Pv) memh(Rx++#s4:1)=Nt.new
2931 let mayStore = 1, hasCtrlDep = 1,
2933 def POST_SThri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2934 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2935 "if ($src1) memh($src3++#$offset) = $src2.new",
2939 // if (Pv.new) memh(Rx++#s4:1)=Nt.new
2940 let mayStore = 1, hasCtrlDep = 1,
2942 def POST_SThri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2943 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2944 "if ($src1.new) memh($src3++#$offset) = $src2.new",
2948 // if (!Pv) memh(Rx++#s4:1)=Nt.new
2949 let mayStore = 1, hasCtrlDep = 1,
2951 def POST_SThri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2952 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2953 "if (!$src1) memh($src3++#$offset) = $src2.new",
2957 // if (!Pv.new) memh(Rx++#s4:1)=Nt.new
2958 let mayStore = 1, hasCtrlDep = 1,
2960 def POST_SThri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2961 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2962 "if (!$src1.new) memh($src3++#$offset) = $src2.new",
2967 // Store new-value word.
2969 // memw(Re=#U6)=Nt.new
2970 // memw(Rs+#s11:2)=Nt.new
2971 let mayStore = 1, isPredicable = 1 in
2972 def STriw_nv_V4 : NVInst_V4<(outs),
2973 (ins MEMri:$addr, IntRegs:$src1),
2974 "memw($addr) = $src1.new",
2978 let mayStore = 1, isPredicable = 1 in
2979 def STriw_indexed_nv_V4 : NVInst_V4<(outs),
2980 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
2981 "memw($src1+#$src2) = $src3.new",
2985 // memw(Rs+Ru<<#u2)=Nt.new
2986 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
2987 def STriw_indexed_shl_nv_V4 : NVInst_V4<(outs),
2988 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
2989 "memw($src1+$src2<<#$src3) = $src4.new",
2993 // memw(Ru<<#u2+#U6)=Nt.new
2994 let mayStore = 1, AddedComplexity = 10 in
2995 def STriw_shl_nv_V4 : NVInst_V4<(outs),
2996 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2997 "memw($src1<<#$src2+#$src3) = $src4.new",
3001 // memw(Rx++#s4:2)=Nt.new
3002 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
3003 def POST_STwri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3004 (ins IntRegs:$src1, IntRegs:$src2, s4_2Imm:$offset),
3005 "memw($src2++#$offset) = $src1.new",
3010 // memw(Rx++#s4:2:circ(Mu))=Nt.new
3011 // memw(Rx++I:circ(Mu))=Nt.new
3012 // memw(Rx++Mu)=Nt.new
3013 // memw(Rx++Mu:brev)=Nt.new
3014 // memw(gp+#u16:2)=Nt.new
3015 let mayStore = 1, neverHasSideEffects = 1 in
3016 def STriw_GP_nv_V4 : NVInst_V4<(outs),
3017 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
3018 "memw(#$global+$offset) = $src.new",
3022 let mayStore = 1, neverHasSideEffects = 1 in
3023 def STw_GP_nv_V4 : NVInst_V4<(outs),
3024 (ins globaladdress:$global, IntRegs:$src),
3025 "memw(#$global) = $src.new",
3029 // Store new-value word conditionally.
3031 // if ([!]Pv[.new]) memw(#u6)=Nt.new
3033 // if ([!]Pv[.new]) memw(Rs+#u6:2)=Nt.new
3034 // if (Pv) memw(Rs+#u6:2)=Nt.new
3035 let mayStore = 1, neverHasSideEffects = 1,
3037 def STriw_cPt_nv_V4 : NVInst_V4<(outs),
3038 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3039 "if ($src1) memw($addr) = $src2.new",
3043 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
3044 let mayStore = 1, neverHasSideEffects = 1,
3046 def STriw_cdnPt_nv_V4 : NVInst_V4<(outs),
3047 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3048 "if ($src1.new) memw($addr) = $src2.new",
3052 // if (!Pv) memw(Rs+#u6:2)=Nt.new
3053 let mayStore = 1, neverHasSideEffects = 1,
3055 def STriw_cNotPt_nv_V4 : NVInst_V4<(outs),
3056 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3057 "if (!$src1) memw($addr) = $src2.new",
3061 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
3062 let mayStore = 1, neverHasSideEffects = 1,
3064 def STriw_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3065 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3066 "if (!$src1.new) memw($addr) = $src2.new",
3070 // if (Pv) memw(Rs+#u6:2)=Nt.new
3071 let mayStore = 1, neverHasSideEffects = 1,
3073 def STriw_indexed_cPt_nv_V4 : NVInst_V4<(outs),
3074 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3075 "if ($src1) memw($src2+#$src3) = $src4.new",
3079 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
3080 let mayStore = 1, neverHasSideEffects = 1,
3082 def STriw_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
3083 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3084 "if ($src1.new) memw($src2+#$src3) = $src4.new",
3088 // if (!Pv) memw(Rs+#u6:2)=Nt.new
3089 let mayStore = 1, neverHasSideEffects = 1,
3091 def STriw_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
3092 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3093 "if (!$src1) memw($src2+#$src3) = $src4.new",
3097 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
3098 let mayStore = 1, neverHasSideEffects = 1,
3100 def STriw_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3101 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3102 "if (!$src1.new) memw($src2+#$src3) = $src4.new",
3107 // if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Nt.new
3108 // if (Pv) memw(Rs+Ru<<#u2)=Nt.new
3109 let mayStore = 1, AddedComplexity = 10,
3111 def STriw_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
3112 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3114 "if ($src1) memw($src2+$src3<<#$src4) = $src5.new",
3118 // if (Pv.new) memw(Rs+Ru<<#u2)=Nt.new
3119 let mayStore = 1, AddedComplexity = 10,
3121 def STriw_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
3122 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3124 "if ($src1.new) memw($src2+$src3<<#$src4) = $src5.new",
3128 // if (!Pv) memw(Rs+Ru<<#u2)=Nt.new
3129 let mayStore = 1, AddedComplexity = 10,
3131 def STriw_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
3132 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3134 "if (!$src1) memw($src2+$src3<<#$src4) = $src5.new",
3138 // if (!Pv.new) memw(Rs+Ru<<#u2)=Nt.new
3139 let mayStore = 1, AddedComplexity = 10,
3141 def STriw_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3142 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3144 "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5.new",
3148 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new
3149 // if (Pv) memw(Rx++#s4:2)=Nt.new
3150 let mayStore = 1, hasCtrlDep = 1,
3152 def POST_STwri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3153 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3154 "if ($src1) memw($src3++#$offset) = $src2.new",
3158 // if (Pv.new) memw(Rx++#s4:2)=Nt.new
3159 let mayStore = 1, hasCtrlDep = 1,
3161 def POST_STwri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3162 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3163 "if ($src1.new) memw($src3++#$offset) = $src2.new",
3167 // if (!Pv) memw(Rx++#s4:2)=Nt.new
3168 let mayStore = 1, hasCtrlDep = 1,
3170 def POST_STwri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3171 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3172 "if (!$src1) memw($src3++#$offset) = $src2.new",
3176 // if (!Pv.new) memw(Rx++#s4:2)=Nt.new
3177 let mayStore = 1, hasCtrlDep = 1,
3179 def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3180 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3181 "if (!$src1.new) memw($src3++#$offset) = $src2.new",
3187 // if (Pv) memb(##global) = Rt
3188 let mayStore = 1, neverHasSideEffects = 1 in
3189 def STb_GP_cPt_nv_V4 : NVInst_V4<(outs),
3190 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3191 "if ($src1) memb(##$global) = $src2.new",
3195 // if (!Pv) memb(##global) = Rt
3196 let mayStore = 1, neverHasSideEffects = 1 in
3197 def STb_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3198 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3199 "if (!$src1) memb(##$global) = $src2.new",
3203 // if (Pv) memb(##global) = Rt
3204 let mayStore = 1, neverHasSideEffects = 1 in
3205 def STb_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3206 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3207 "if ($src1.new) memb(##$global) = $src2.new",
3211 // if (!Pv) memb(##global) = Rt
3212 let mayStore = 1, neverHasSideEffects = 1 in
3213 def STb_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3214 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3215 "if (!$src1.new) memb(##$global) = $src2.new",
3219 // if (Pv) memh(##global) = Rt
3220 let mayStore = 1, neverHasSideEffects = 1 in
3221 def STh_GP_cPt_nv_V4 : NVInst_V4<(outs),
3222 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3223 "if ($src1) memh(##$global) = $src2.new",
3227 // if (!Pv) memh(##global) = Rt
3228 let mayStore = 1, neverHasSideEffects = 1 in
3229 def STh_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3230 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3231 "if (!$src1) memh(##$global) = $src2.new",
3235 // if (Pv) memh(##global) = Rt
3236 let mayStore = 1, neverHasSideEffects = 1 in
3237 def STh_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3238 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3239 "if ($src1.new) memh(##$global) = $src2.new",
3243 // if (!Pv) memh(##global) = Rt
3244 let mayStore = 1, neverHasSideEffects = 1 in
3245 def STh_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3246 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3247 "if (!$src1.new) memh(##$global) = $src2.new",
3251 // if (Pv) memw(##global) = Rt
3252 let mayStore = 1, neverHasSideEffects = 1 in
3253 def STw_GP_cPt_nv_V4 : NVInst_V4<(outs),
3254 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3255 "if ($src1) memw(##$global) = $src2.new",
3259 // if (!Pv) memw(##global) = Rt
3260 let mayStore = 1, neverHasSideEffects = 1 in
3261 def STw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3262 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3263 "if (!$src1) memw(##$global) = $src2.new",
3267 // if (Pv) memw(##global) = Rt
3268 let mayStore = 1, neverHasSideEffects = 1 in
3269 def STw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3270 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3271 "if ($src1.new) memw(##$global) = $src2.new",
3275 // if (!Pv) memw(##global) = Rt
3276 let mayStore = 1, neverHasSideEffects = 1 in
3277 def STw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3278 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3279 "if (!$src1.new) memw(##$global) = $src2.new",
3283 let mayStore = 1, neverHasSideEffects = 1 in
3284 def STrib_GP_cPt_nv_V4 : NVInst_V4<(outs),
3285 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3287 "if ($src1) memb(##$global+$offset) = $src2.new",
3291 let mayStore = 1, neverHasSideEffects = 1 in
3292 def STrib_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3293 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3295 "if (!$src1) memb(##$global+$offset) = $src2.new",
3299 let mayStore = 1, neverHasSideEffects = 1 in
3300 def STrib_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3301 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3303 "if ($src1.new) memb(##$global+$offset) = $src2.new",
3307 let mayStore = 1, neverHasSideEffects = 1 in
3308 def STrib_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3309 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3311 "if (!$src1.new) memb(##$global+$offset) = $src2.new",
3315 let mayStore = 1, neverHasSideEffects = 1 in
3316 def STrih_GP_cPt_nv_V4 : NVInst_V4<(outs),
3317 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3319 "if ($src1) memh(##$global+$offset) = $src2.new",
3323 let mayStore = 1, neverHasSideEffects = 1 in
3324 def STrih_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3325 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3327 "if (!$src1) memh(##$global+$offset) = $src2.new",
3331 let mayStore = 1, neverHasSideEffects = 1 in
3332 def STrih_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3333 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3335 "if ($src1.new) memh(##$global+$offset) = $src2.new",
3339 let mayStore = 1, neverHasSideEffects = 1 in
3340 def STrih_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3341 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3343 "if (!$src1.new) memh(##$global+$offset) = $src2.new",
3347 let mayStore = 1, neverHasSideEffects = 1 in
3348 def STriw_GP_cPt_nv_V4 : NVInst_V4<(outs),
3349 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3351 "if ($src1) memw(##$global+$offset) = $src2.new",
3355 let mayStore = 1, neverHasSideEffects = 1 in
3356 def STriw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3357 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3359 "if (!$src1) memw(##$global+$offset) = $src2.new",
3363 let mayStore = 1, neverHasSideEffects = 1 in
3364 def STriw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3365 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3367 "if ($src1.new) memw(##$global+$offset) = $src2.new",
3371 let mayStore = 1, neverHasSideEffects = 1 in
3372 def STriw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3373 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3375 "if (!$src1.new) memw(##$global+$offset) = $src2.new",
3379 //===----------------------------------------------------------------------===//
3381 //===----------------------------------------------------------------------===//
3383 //===----------------------------------------------------------------------===//
3385 //===----------------------------------------------------------------------===//
3387 multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
3388 def _ie_nv_V4 : NVInst_V4<(outs),
3389 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3390 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3391 !strconcat("($src1.new, $src2)) jump:",
3392 !strconcat(TakenStr, " $offset"))))),
3396 def _nv_V4 : NVInst_V4<(outs),
3397 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3398 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3399 !strconcat("($src1.new, $src2)) jump:",
3400 !strconcat(TakenStr, " $offset"))))),
3405 multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr,
3407 def _ie_nv_V4 : NVInst_V4<(outs),
3408 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3409 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3410 !strconcat("($src1, $src2.new)) jump:",
3411 !strconcat(TakenStr, " $offset"))))),
3415 def _nv_V4 : NVInst_V4<(outs),
3416 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3417 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3418 !strconcat("($src1, $src2.new)) jump:",
3419 !strconcat(TakenStr, " $offset"))))),
3424 multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
3425 def _ie_nv_V4 : NVInst_V4<(outs),
3426 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
3427 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3428 !strconcat("($src1.new, #$src2)) jump:",
3429 !strconcat(TakenStr, " $offset"))))),
3433 def _nv_V4 : NVInst_V4<(outs),
3434 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
3435 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3436 !strconcat("($src1.new, #$src2)) jump:",
3437 !strconcat(TakenStr, " $offset"))))),
3442 multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
3443 def _ie_nv_V4 : NVInst_V4<(outs),
3444 (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
3445 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3446 !strconcat("($src1.new, #$src2)) jump:",
3447 !strconcat(TakenStr, " $offset"))))),
3451 def _nv_V4 : NVInst_V4<(outs),
3452 (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
3453 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3454 !strconcat("($src1.new, #$src2)) jump:",
3455 !strconcat(TakenStr, " $offset"))))),
3460 multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr,
3462 def _ie_nv_V4 : NVInst_V4<(outs),
3463 (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
3464 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3465 !strconcat("($src1.new, #$src2)) jump:",
3466 !strconcat(TakenStr, " $offset"))))),
3470 def _nv_V4 : NVInst_V4<(outs),
3471 (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
3472 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3473 !strconcat("($src1.new, #$src2)) jump:",
3474 !strconcat(TakenStr, " $offset"))))),
3479 // Multiclass for regular dot new of Ist operand register.
3480 multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
3481 defm Pt : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
3482 defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
3485 // Multiclass for dot new of 2nd operand register.
3486 multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
3487 defm Pt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
3488 defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
3491 // Multiclass for 2nd operand immediate, including -1.
3492 multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
3493 defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
3494 defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3495 defm Ptneg : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
3496 defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
3499 // Multiclass for 2nd operand immediate, excluding -1.
3500 multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
3501 defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
3502 defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3505 // Multiclass for tstbit, where 2nd operand is always #0.
3506 multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
3507 defm Pt : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
3508 defm Pnt : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
3511 // Multiclass for GT.
3512 multiclass NVJ_type_rr_ri<string OpcStr> {
3513 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
3514 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
3515 defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3516 defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
3517 defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
3518 defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
3521 // Multiclass for EQ.
3522 multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
3523 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
3524 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
3525 defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
3526 defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
3529 // Multiclass for GTU.
3530 multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
3531 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
3532 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
3533 defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3534 defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
3535 defm riNot : NVJ_type_br_pred_imm_only<"!", OpcStr>;
3536 defm ri : NVJ_type_br_pred_imm_only<"", OpcStr>;
3539 // Multiclass for tstbit.
3540 multiclass NVJ_type_r0<string OpcStr> {
3541 defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
3542 defm r0 : NVJ_type_br_pred_tstbit<"", OpcStr>;
3545 // Base Multiclass for New Value Jump.
3546 multiclass NVJ_type {
3547 defm GT : NVJ_type_rr_ri<"cmp.gt">;
3548 defm EQ : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
3549 defm GTU : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
3550 defm TSTBIT : NVJ_type_r0<"tstbit">;
3553 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
3554 defm JMP_ : NVJ_type;
3557 //===----------------------------------------------------------------------===//
3559 //===----------------------------------------------------------------------===//
3561 //===----------------------------------------------------------------------===//
3563 //===----------------------------------------------------------------------===//
3565 // Add and accumulate.
3566 // Rd=add(Rs,add(Ru,#s6))
3567 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
3568 (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
3569 "$dst = add($src1, add($src2, #$src3))",
3570 [(set (i32 IntRegs:$dst),
3571 (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
3572 s6ImmPred:$src3)))]>,
3575 // Rd=add(Rs,sub(#s6,Ru))
3576 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
3577 (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3578 "$dst = add($src1, sub(#$src2, $src3))",
3579 [(set (i32 IntRegs:$dst),
3580 (add (i32 IntRegs:$src1), (sub s6ImmPred:$src2,
3581 (i32 IntRegs:$src3))))]>,
3584 // Generates the same instruction as ADDr_SUBri_V4 but matches different
3586 // Rd=add(Rs,sub(#s6,Ru))
3587 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
3588 (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3589 "$dst = add($src1, sub(#$src2, $src3))",
3590 [(set (i32 IntRegs:$dst),
3591 (sub (add (i32 IntRegs:$src1), s6ImmPred:$src2),
3592 (i32 IntRegs:$src3)))]>,
3596 // Add or subtract doublewords with carry.
3598 // Rdd=add(Rss,Rtt,Px):carry
3600 // Rdd=sub(Rss,Rtt,Px):carry
3603 // Logical doublewords.
3604 // Rdd=and(Rtt,~Rss)
3605 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3606 (ins DoubleRegs:$src1, DoubleRegs:$src2),
3607 "$dst = and($src1, ~$src2)",
3608 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
3609 (not (i64 DoubleRegs:$src2))))]>,
3613 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3614 (ins DoubleRegs:$src1, DoubleRegs:$src2),
3615 "$dst = or($src1, ~$src2)",
3616 [(set (i64 DoubleRegs:$dst),
3617 (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
3621 // Logical-logical doublewords.
3622 // Rxx^=xor(Rss,Rtt)
3623 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
3624 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
3625 "$dst ^= xor($src2, $src3)",
3626 [(set (i64 DoubleRegs:$dst),
3627 (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
3628 (i64 DoubleRegs:$src3))))],
3633 // Logical-logical words.
3634 // Rx=or(Ru,and(Rx,#s10))
3635 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
3636 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3637 "$dst = or($src1, and($src2, #$src3))",
3638 [(set (i32 IntRegs:$dst),
3639 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3640 s10ImmPred:$src3)))],
3644 // Rx[&|^]=and(Rs,Rt)
3646 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3647 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3648 "$dst &= and($src2, $src3)",
3649 [(set (i32 IntRegs:$dst),
3650 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3651 (i32 IntRegs:$src3))))],
3656 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3657 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3658 "$dst |= and($src2, $src3)",
3659 [(set (i32 IntRegs:$dst),
3660 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3661 (i32 IntRegs:$src3))))],
3666 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3667 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3668 "$dst ^= and($src2, $src3)",
3669 [(set (i32 IntRegs:$dst),
3670 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3671 (i32 IntRegs:$src3))))],
3675 // Rx[&|^]=and(Rs,~Rt)
3677 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3678 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3679 "$dst &= and($src2, ~$src3)",
3680 [(set (i32 IntRegs:$dst),
3681 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3682 (not (i32 IntRegs:$src3)))))],
3687 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3688 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3689 "$dst |= and($src2, ~$src3)",
3690 [(set (i32 IntRegs:$dst),
3691 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3692 (not (i32 IntRegs:$src3)))))],
3697 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3698 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3699 "$dst ^= and($src2, ~$src3)",
3700 [(set (i32 IntRegs:$dst),
3701 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3702 (not (i32 IntRegs:$src3)))))],
3706 // Rx[&|^]=or(Rs,Rt)
3708 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3709 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3710 "$dst &= or($src2, $src3)",
3711 [(set (i32 IntRegs:$dst),
3712 (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3713 (i32 IntRegs:$src3))))],
3718 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3719 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3720 "$dst |= or($src2, $src3)",
3721 [(set (i32 IntRegs:$dst),
3722 (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3723 (i32 IntRegs:$src3))))],
3728 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3729 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3730 "$dst ^= or($src2, $src3)",
3731 [(set (i32 IntRegs:$dst),
3732 (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3733 (i32 IntRegs:$src3))))],
3737 // Rx[&|^]=xor(Rs,Rt)
3739 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3740 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3741 "$dst &= xor($src2, $src3)",
3742 [(set (i32 IntRegs:$dst),
3743 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3744 (i32 IntRegs:$src3))))],
3749 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3750 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3751 "$dst |= xor($src2, $src3)",
3752 [(set (i32 IntRegs:$dst),
3753 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3754 (i32 IntRegs:$src3))))],
3759 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3760 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3761 "$dst ^= xor($src2, $src3)",
3762 [(set (i32 IntRegs:$dst),
3763 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3764 (i32 IntRegs:$src3))))],
3769 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
3770 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3771 "$dst |= and($src2, #$src3)",
3772 [(set (i32 IntRegs:$dst),
3773 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3774 s10ImmPred:$src3)))],
3779 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
3780 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3781 "$dst |= or($src2, #$src3)",
3782 [(set (i32 IntRegs:$dst),
3783 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3784 s10ImmPred:$src3)))],
3790 // Rd=modwrap(Rs,Rt)
3792 // Rd=cround(Rs,#u5)
3794 // Rd=round(Rs,#u5)[:sat]
3795 // Rd=round(Rs,Rt)[:sat]
3796 // Vector reduce add unsigned halfwords
3797 // Rd=vraddh(Rss,Rtt)
3799 // Rdd=vaddb(Rss,Rtt)
3800 // Vector conditional negate
3801 // Rdd=vcnegh(Rss,Rt)
3802 // Rxx+=vrcnegh(Rss,Rt)
3803 // Vector maximum bytes
3804 // Rdd=vmaxb(Rtt,Rss)
3805 // Vector reduce maximum halfwords
3806 // Rxx=vrmaxh(Rss,Ru)
3807 // Rxx=vrmaxuh(Rss,Ru)
3808 // Vector reduce maximum words
3809 // Rxx=vrmaxuw(Rss,Ru)
3810 // Rxx=vrmaxw(Rss,Ru)
3811 // Vector minimum bytes
3812 // Rdd=vminb(Rtt,Rss)
3813 // Vector reduce minimum halfwords
3814 // Rxx=vrminh(Rss,Ru)
3815 // Rxx=vrminuh(Rss,Ru)
3816 // Vector reduce minimum words
3817 // Rxx=vrminuw(Rss,Ru)
3818 // Rxx=vrminw(Rss,Ru)
3819 // Vector subtract bytes
3820 // Rdd=vsubb(Rss,Rtt)
3822 //===----------------------------------------------------------------------===//
3824 //===----------------------------------------------------------------------===//
3827 //===----------------------------------------------------------------------===//
3829 //===----------------------------------------------------------------------===//
3831 // Multiply and user lower result.
3832 // Rd=add(#u6,mpyi(Rs,#U6))
3833 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
3834 (ins u6Imm:$src1, IntRegs:$src2, u6Imm:$src3),
3835 "$dst = add(#$src1, mpyi($src2, #$src3))",
3836 [(set (i32 IntRegs:$dst),
3837 (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
3838 u6ImmPred:$src1))]>,
3841 // Rd=add(#u6,mpyi(Rs,Rt))
3843 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
3844 (ins u6Imm:$src1, IntRegs:$src2, IntRegs:$src3),
3845 "$dst = add(#$src1, mpyi($src2, $src3))",
3846 [(set (i32 IntRegs:$dst),
3847 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
3848 u6ImmPred:$src1))]>,
3851 // Rd=add(Ru,mpyi(#u6:2,Rs))
3852 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
3853 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
3854 "$dst = add($src1, mpyi(#$src2, $src3))",
3855 [(set (i32 IntRegs:$dst),
3856 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
3857 u6_2ImmPred:$src2)))]>,
3860 // Rd=add(Ru,mpyi(Rs,#u6))
3861 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
3862 (ins IntRegs:$src1, IntRegs:$src2, u6Imm:$src3),
3863 "$dst = add($src1, mpyi($src2, #$src3))",
3864 [(set (i32 IntRegs:$dst),
3865 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
3866 u6ImmPred:$src3)))]>,
3869 // Rx=add(Ru,mpyi(Rx,Rs))
3870 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
3871 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3872 "$dst = add($src1, mpyi($src2, $src3))",
3873 [(set (i32 IntRegs:$dst),
3874 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
3875 (i32 IntRegs:$src3))))],
3880 // Polynomial multiply words
3882 // Rxx^=pmpyw(Rs,Rt)
3884 // Vector reduce multiply word by signed half (32x16)
3885 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
3886 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
3887 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
3888 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
3890 // Multiply and use upper result
3891 // Rd=mpy(Rs,Rt.H):<<1:sat
3892 // Rd=mpy(Rs,Rt.L):<<1:sat
3893 // Rd=mpy(Rs,Rt):<<1
3894 // Rd=mpy(Rs,Rt):<<1:sat
3896 // Rx+=mpy(Rs,Rt):<<1:sat
3897 // Rx-=mpy(Rs,Rt):<<1:sat
3899 // Vector multiply bytes
3900 // Rdd=vmpybsu(Rs,Rt)
3901 // Rdd=vmpybu(Rs,Rt)
3902 // Rxx+=vmpybsu(Rs,Rt)
3903 // Rxx+=vmpybu(Rs,Rt)
3905 // Vector polynomial multiply halfwords
3906 // Rdd=vpmpyh(Rs,Rt)
3907 // Rxx^=vpmpyh(Rs,Rt)
3909 //===----------------------------------------------------------------------===//
3911 //===----------------------------------------------------------------------===//
3914 //===----------------------------------------------------------------------===//
3916 //===----------------------------------------------------------------------===//
3918 // Shift by immediate and accumulate.
3919 // Rx=add(#u8,asl(Rx,#U5))
3920 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3921 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3922 "$dst = add(#$src1, asl($src2, #$src3))",
3923 [(set (i32 IntRegs:$dst),
3924 (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3929 // Rx=add(#u8,lsr(Rx,#U5))
3930 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3931 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3932 "$dst = add(#$src1, lsr($src2, #$src3))",
3933 [(set (i32 IntRegs:$dst),
3934 (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3939 // Rx=sub(#u8,asl(Rx,#U5))
3940 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3941 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3942 "$dst = sub(#$src1, asl($src2, #$src3))",
3943 [(set (i32 IntRegs:$dst),
3944 (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3949 // Rx=sub(#u8,lsr(Rx,#U5))
3950 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3951 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3952 "$dst = sub(#$src1, lsr($src2, #$src3))",
3953 [(set (i32 IntRegs:$dst),
3954 (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3960 //Shift by immediate and logical.
3961 //Rx=and(#u8,asl(Rx,#U5))
3962 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3963 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3964 "$dst = and(#$src1, asl($src2, #$src3))",
3965 [(set (i32 IntRegs:$dst),
3966 (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3971 //Rx=and(#u8,lsr(Rx,#U5))
3972 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3973 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3974 "$dst = and(#$src1, lsr($src2, #$src3))",
3975 [(set (i32 IntRegs:$dst),
3976 (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3981 //Rx=or(#u8,asl(Rx,#U5))
3982 let AddedComplexity = 30 in
3983 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3984 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3985 "$dst = or(#$src1, asl($src2, #$src3))",
3986 [(set (i32 IntRegs:$dst),
3987 (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3992 //Rx=or(#u8,lsr(Rx,#U5))
3993 let AddedComplexity = 30 in
3994 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3995 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3996 "$dst = or(#$src1, lsr($src2, #$src3))",
3997 [(set (i32 IntRegs:$dst),
3998 (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
4004 //Shift by register.
4006 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
4007 "$dst = lsl(#$src1, $src2)",
4008 [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
4009 (i32 IntRegs:$src2)))]>,
4013 //Shift by register and logical.
4015 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4016 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4017 "$dst ^= asl($src2, $src3)",
4018 [(set (i64 DoubleRegs:$dst),
4019 (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
4020 (i32 IntRegs:$src3))))],
4025 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4026 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4027 "$dst ^= asr($src2, $src3)",
4028 [(set (i64 DoubleRegs:$dst),
4029 (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
4030 (i32 IntRegs:$src3))))],
4035 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4036 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4037 "$dst ^= lsl($src2, $src3)",
4038 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
4039 (shl (i64 DoubleRegs:$src2),
4040 (i32 IntRegs:$src3))))],
4045 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4046 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4047 "$dst ^= lsr($src2, $src3)",
4048 [(set (i64 DoubleRegs:$dst),
4049 (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
4050 (i32 IntRegs:$src3))))],
4055 //===----------------------------------------------------------------------===//
4057 //===----------------------------------------------------------------------===//
4059 //===----------------------------------------------------------------------===//
4060 // MEMOP: Word, Half, Byte
4061 //===----------------------------------------------------------------------===//
4063 //===----------------------------------------------------------------------===//
4067 // MEMw_ADDi_indexed_V4 : memw(Rs+#u6:2)+=#U5
4068 // MEMw_SUBi_indexed_V4 : memw(Rs+#u6:2)-=#U5
4069 // MEMw_ADDr_indexed_V4 : memw(Rs+#u6:2)+=Rt
4070 // MEMw_SUBr_indexed_V4 : memw(Rs+#u6:2)-=Rt
4071 // MEMw_CLRr_indexed_V4 : memw(Rs+#u6:2)&=Rt
4072 // MEMw_SETr_indexed_V4 : memw(Rs+#u6:2)|=Rt
4073 // MEMw_ADDi_V4 : memw(Rs+#u6:2)+=#U5
4074 // MEMw_SUBi_V4 : memw(Rs+#u6:2)-=#U5
4075 // MEMw_ADDr_V4 : memw(Rs+#u6:2)+=Rt
4076 // MEMw_SUBr_V4 : memw(Rs+#u6:2)-=Rt
4077 // MEMw_CLRr_V4 : memw(Rs+#u6:2)&=Rt
4078 // MEMw_SETr_V4 : memw(Rs+#u6:2)|=Rt
4081 // MEMw_CLRi_indexed_V4 : memw(Rs+#u6:2)=clrbit(#U5)
4082 // MEMw_SETi_indexed_V4 : memw(Rs+#u6:2)=setbit(#U5)
4083 // MEMw_CLRi_V4 : memw(Rs+#u6:2)=clrbit(#U5)
4084 // MEMw_SETi_V4 : memw(Rs+#u6:2)=setbit(#U5)
4085 //===----------------------------------------------------------------------===//
4089 // memw(Rs+#u6:2) += #U5
4090 let AddedComplexity = 30 in
4091 def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
4092 (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),
4093 "memw($base+#$offset) += #$addend",
4095 Requires<[HasV4T, UseMEMOP]>;
4097 // memw(Rs+#u6:2) -= #U5
4098 let AddedComplexity = 30 in
4099 def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
4100 (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),
4101 "memw($base+#$offset) -= #$subend",
4103 Requires<[HasV4T, UseMEMOP]>;
4105 // memw(Rs+#u6:2) += Rt
4106 let AddedComplexity = 30 in
4107 def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4108 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),
4109 "memw($base+#$offset) += $addend",
4110 [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4111 (i32 IntRegs:$addend)),
4112 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4113 Requires<[HasV4T, UseMEMOP]>;
4115 // memw(Rs+#u6:2) -= Rt
4116 let AddedComplexity = 30 in
4117 def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
4118 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),
4119 "memw($base+#$offset) -= $subend",
4120 [(store (sub (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4121 (i32 IntRegs:$subend)),
4122 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4123 Requires<[HasV4T, UseMEMOP]>;
4125 // memw(Rs+#u6:2) &= Rt
4126 let AddedComplexity = 30 in
4127 def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4128 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),
4129 "memw($base+#$offset) &= $andend",
4130 [(store (and (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4131 (i32 IntRegs:$andend)),
4132 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4133 Requires<[HasV4T, UseMEMOP]>;
4135 // memw(Rs+#u6:2) |= Rt
4136 let AddedComplexity = 30 in
4137 def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
4138 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),
4139 "memw($base+#$offset) |= $orend",
4140 [(store (or (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4141 (i32 IntRegs:$orend)),
4142 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4143 Requires<[HasV4T, UseMEMOP]>;
4145 // memw(Rs+#u6:2) += #U5
4146 let AddedComplexity = 30 in
4147 def MEMw_ADDi_MEM_V4 : MEMInst_V4<(outs),
4148 (ins MEMri:$addr, u5Imm:$addend),
4149 "memw($addr) += $addend",
4151 Requires<[HasV4T, UseMEMOP]>;
4153 // memw(Rs+#u6:2) -= #U5
4154 let AddedComplexity = 30 in
4155 def MEMw_SUBi_MEM_V4 : MEMInst_V4<(outs),
4156 (ins MEMri:$addr, u5Imm:$subend),
4157 "memw($addr) -= $subend",
4159 Requires<[HasV4T, UseMEMOP]>;
4161 // memw(Rs+#u6:2) += Rt
4162 let AddedComplexity = 30 in
4163 def MEMw_ADDr_MEM_V4 : MEMInst_V4<(outs),
4164 (ins MEMri:$addr, IntRegs:$addend),
4165 "memw($addr) += $addend",
4166 [(store (add (load ADDRriU6_2:$addr), (i32 IntRegs:$addend)),
4167 ADDRriU6_2:$addr)]>,
4168 Requires<[HasV4T, UseMEMOP]>;
4170 // memw(Rs+#u6:2) -= Rt
4171 let AddedComplexity = 30 in
4172 def MEMw_SUBr_MEM_V4 : MEMInst_V4<(outs),
4173 (ins MEMri:$addr, IntRegs:$subend),
4174 "memw($addr) -= $subend",
4175 [(store (sub (load ADDRriU6_2:$addr), (i32 IntRegs:$subend)),
4176 ADDRriU6_2:$addr)]>,
4177 Requires<[HasV4T, UseMEMOP]>;
4179 // memw(Rs+#u6:2) &= Rt
4180 let AddedComplexity = 30 in
4181 def MEMw_ANDr_MEM_V4 : MEMInst_V4<(outs),
4182 (ins MEMri:$addr, IntRegs:$andend),
4183 "memw($addr) &= $andend",
4184 [(store (and (load ADDRriU6_2:$addr), (i32 IntRegs:$andend)),
4185 ADDRriU6_2:$addr)]>,
4186 Requires<[HasV4T, UseMEMOP]>;
4188 // memw(Rs+#u6:2) |= Rt
4189 let AddedComplexity = 30 in
4190 def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs),
4191 (ins MEMri:$addr, IntRegs:$orend),
4192 "memw($addr) |= $orend",
4193 [(store (or (load ADDRriU6_2:$addr), (i32 IntRegs:$orend)),
4194 ADDRriU6_2:$addr)]>,
4195 Requires<[HasV4T, UseMEMOP]>;
4197 //===----------------------------------------------------------------------===//
4201 // MEMh_ADDi_indexed_V4 : memw(Rs+#u6:2)+=#U5
4202 // MEMh_SUBi_indexed_V4 : memw(Rs+#u6:2)-=#U5
4203 // MEMh_ADDr_indexed_V4 : memw(Rs+#u6:2)+=Rt
4204 // MEMh_SUBr_indexed_V4 : memw(Rs+#u6:2)-=Rt
4205 // MEMh_CLRr_indexed_V4 : memw(Rs+#u6:2)&=Rt
4206 // MEMh_SETr_indexed_V4 : memw(Rs+#u6:2)|=Rt
4207 // MEMh_ADDi_V4 : memw(Rs+#u6:2)+=#U5
4208 // MEMh_SUBi_V4 : memw(Rs+#u6:2)-=#U5
4209 // MEMh_ADDr_V4 : memw(Rs+#u6:2)+=Rt
4210 // MEMh_SUBr_V4 : memw(Rs+#u6:2)-=Rt
4211 // MEMh_CLRr_V4 : memw(Rs+#u6:2)&=Rt
4212 // MEMh_SETr_V4 : memw(Rs+#u6:2)|=Rt
4215 // MEMh_CLRi_indexed_V4 : memw(Rs+#u6:2)=clrbit(#U5)
4216 // MEMh_SETi_indexed_V4 : memw(Rs+#u6:2)=setbit(#U5)
4217 // MEMh_CLRi_V4 : memw(Rs+#u6:2)=clrbit(#U5)
4218 // MEMh_SETi_V4 : memw(Rs+#u6:2)=setbit(#U5)
4219 //===----------------------------------------------------------------------===//
4222 // memh(Rs+#u6:1) += #U5
4223 let AddedComplexity = 30 in
4224 def MEMh_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
4225 (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$addend),
4226 "memh($base+#$offset) += $addend",
4228 Requires<[HasV4T, UseMEMOP]>;
4230 // memh(Rs+#u6:1) -= #U5
4231 let AddedComplexity = 30 in
4232 def MEMh_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
4233 (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$subend),
4234 "memh($base+#$offset) -= $subend",
4236 Requires<[HasV4T, UseMEMOP]>;
4238 // memh(Rs+#u6:1) += Rt
4239 let AddedComplexity = 30 in
4240 def MEMh_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4241 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$addend),
4242 "memh($base+#$offset) += $addend",
4243 [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base),
4244 u6_1ImmPred:$offset)),
4245 (i32 IntRegs:$addend)),
4246 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4247 Requires<[HasV4T, UseMEMOP]>;
4249 // memh(Rs+#u6:1) -= Rt
4250 let AddedComplexity = 30 in
4251 def MEMh_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
4252 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$subend),
4253 "memh($base+#$offset) -= $subend",
4254 [(truncstorei16 (sub (sextloadi16 (add (i32 IntRegs:$base),
4255 u6_1ImmPred:$offset)),
4256 (i32 IntRegs:$subend)),
4257 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4258 Requires<[HasV4T, UseMEMOP]>;
4260 // memh(Rs+#u6:1) &= Rt
4261 let AddedComplexity = 30 in
4262 def MEMh_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4263 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$andend),
4264 "memh($base+#$offset) += $andend",
4265 [(truncstorei16 (and (sextloadi16 (add (i32 IntRegs:$base),
4266 u6_1ImmPred:$offset)),
4267 (i32 IntRegs:$andend)),
4268 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4269 Requires<[HasV4T, UseMEMOP]>;
4271 // memh(Rs+#u6:1) |= Rt
4272 let AddedComplexity = 30 in
4273 def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
4274 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$orend),
4275 "memh($base+#$offset) |= $orend",
4276 [(truncstorei16 (or (sextloadi16 (add (i32 IntRegs:$base),
4277 u6_1ImmPred:$offset)),
4278 (i32 IntRegs:$orend)),
4279 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4280 Requires<[HasV4T, UseMEMOP]>;
4282 // memh(Rs+#u6:1) += #U5
4283 let AddedComplexity = 30 in
4284 def MEMh_ADDi_MEM_V4 : MEMInst_V4<(outs),
4285 (ins MEMri:$addr, u5Imm:$addend),
4286 "memh($addr) += $addend",
4288 Requires<[HasV4T, UseMEMOP]>;
4290 // memh(Rs+#u6:1) -= #U5
4291 let AddedComplexity = 30 in
4292 def MEMh_SUBi_MEM_V4 : MEMInst_V4<(outs),
4293 (ins MEMri:$addr, u5Imm:$subend),
4294 "memh($addr) -= $subend",
4296 Requires<[HasV4T, UseMEMOP]>;
4298 // memh(Rs+#u6:1) += Rt
4299 let AddedComplexity = 30 in
4300 def MEMh_ADDr_MEM_V4 : MEMInst_V4<(outs),
4301 (ins MEMri:$addr, IntRegs:$addend),
4302 "memh($addr) += $addend",
4303 [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
4304 (i32 IntRegs:$addend)), ADDRriU6_1:$addr)]>,
4305 Requires<[HasV4T, UseMEMOP]>;
4307 // memh(Rs+#u6:1) -= Rt
4308 let AddedComplexity = 30 in
4309 def MEMh_SUBr_MEM_V4 : MEMInst_V4<(outs),
4310 (ins MEMri:$addr, IntRegs:$subend),
4311 "memh($addr) -= $subend",
4312 [(truncstorei16 (sub (sextloadi16 ADDRriU6_1:$addr),
4313 (i32 IntRegs:$subend)), ADDRriU6_1:$addr)]>,
4314 Requires<[HasV4T, UseMEMOP]>;
4316 // memh(Rs+#u6:1) &= Rt
4317 let AddedComplexity = 30 in
4318 def MEMh_ANDr_MEM_V4 : MEMInst_V4<(outs),
4319 (ins MEMri:$addr, IntRegs:$andend),
4320 "memh($addr) &= $andend",
4321 [(truncstorei16 (and (sextloadi16 ADDRriU6_1:$addr),
4322 (i32 IntRegs:$andend)), ADDRriU6_1:$addr)]>,
4323 Requires<[HasV4T, UseMEMOP]>;
4325 // memh(Rs+#u6:1) |= Rt
4326 let AddedComplexity = 30 in
4327 def MEMh_ORr_MEM_V4 : MEMInst_V4<(outs),
4328 (ins MEMri:$addr, IntRegs:$orend),
4329 "memh($addr) |= $orend",
4330 [(truncstorei16 (or (sextloadi16 ADDRriU6_1:$addr),
4331 (i32 IntRegs:$orend)), ADDRriU6_1:$addr)]>,
4332 Requires<[HasV4T, UseMEMOP]>;
4335 //===----------------------------------------------------------------------===//
4339 // MEMb_ADDi_indexed_V4 : memb(Rs+#u6:0)+=#U5
4340 // MEMb_SUBi_indexed_V4 : memb(Rs+#u6:0)-=#U5
4341 // MEMb_ADDr_indexed_V4 : memb(Rs+#u6:0)+=Rt
4342 // MEMb_SUBr_indexed_V4 : memb(Rs+#u6:0)-=Rt
4343 // MEMb_CLRr_indexed_V4 : memb(Rs+#u6:0)&=Rt
4344 // MEMb_SETr_indexed_V4 : memb(Rs+#u6:0)|=Rt
4345 // MEMb_ADDi_V4 : memb(Rs+#u6:0)+=#U5
4346 // MEMb_SUBi_V4 : memb(Rs+#u6:0)-=#U5
4347 // MEMb_ADDr_V4 : memb(Rs+#u6:0)+=Rt
4348 // MEMb_SUBr_V4 : memb(Rs+#u6:0)-=Rt
4349 // MEMb_CLRr_V4 : memb(Rs+#u6:0)&=Rt
4350 // MEMb_SETr_V4 : memb(Rs+#u6:0)|=Rt
4353 // MEMb_CLRi_indexed_V4 : memb(Rs+#u6:0)=clrbit(#U5)
4354 // MEMb_SETi_indexed_V4 : memb(Rs+#u6:0)=setbit(#U5)
4355 // MEMb_CLRi_V4 : memb(Rs+#u6:0)=clrbit(#U5)
4356 // MEMb_SETi_V4 : memb(Rs+#u6:0)=setbit(#U5)
4357 //===----------------------------------------------------------------------===//
4359 // memb(Rs+#u6:0) += #U5
4360 let AddedComplexity = 30 in
4361 def MEMb_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
4362 (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$addend),
4363 "memb($base+#$offset) += $addend",
4365 Requires<[HasV4T, UseMEMOP]>;
4367 // memb(Rs+#u6:0) -= #U5
4368 let AddedComplexity = 30 in
4369 def MEMb_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
4370 (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$subend),
4371 "memb($base+#$offset) -= $subend",
4373 Requires<[HasV4T, UseMEMOP]>;
4375 // memb(Rs+#u6:0) += Rt
4376 let AddedComplexity = 30 in
4377 def MEMb_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4378 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$addend),
4379 "memb($base+#$offset) += $addend",
4380 [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base),
4381 u6_0ImmPred:$offset)),
4382 (i32 IntRegs:$addend)),
4383 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4384 Requires<[HasV4T, UseMEMOP]>;
4386 // memb(Rs+#u6:0) -= Rt
4387 let AddedComplexity = 30 in
4388 def MEMb_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
4389 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$subend),
4390 "memb($base+#$offset) -= $subend",
4391 [(truncstorei8 (sub (sextloadi8 (add (i32 IntRegs:$base),
4392 u6_0ImmPred:$offset)),
4393 (i32 IntRegs:$subend)),
4394 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4395 Requires<[HasV4T, UseMEMOP]>;
4397 // memb(Rs+#u6:0) &= Rt
4398 let AddedComplexity = 30 in
4399 def MEMb_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4400 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$andend),
4401 "memb($base+#$offset) += $andend",
4402 [(truncstorei8 (and (sextloadi8 (add (i32 IntRegs:$base),
4403 u6_0ImmPred:$offset)),
4404 (i32 IntRegs:$andend)),
4405 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4406 Requires<[HasV4T, UseMEMOP]>;
4408 // memb(Rs+#u6:0) |= Rt
4409 let AddedComplexity = 30 in
4410 def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
4411 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$orend),
4412 "memb($base+#$offset) |= $orend",
4413 [(truncstorei8 (or (sextloadi8 (add (i32 IntRegs:$base),
4414 u6_0ImmPred:$offset)),
4415 (i32 IntRegs:$orend)),
4416 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4417 Requires<[HasV4T, UseMEMOP]>;
4419 // memb(Rs+#u6:0) += #U5
4420 let AddedComplexity = 30 in
4421 def MEMb_ADDi_MEM_V4 : MEMInst_V4<(outs),
4422 (ins MEMri:$addr, u5Imm:$addend),
4423 "memb($addr) += $addend",
4425 Requires<[HasV4T, UseMEMOP]>;
4427 // memb(Rs+#u6:0) -= #U5
4428 let AddedComplexity = 30 in
4429 def MEMb_SUBi_MEM_V4 : MEMInst_V4<(outs),
4430 (ins MEMri:$addr, u5Imm:$subend),
4431 "memb($addr) -= $subend",
4433 Requires<[HasV4T, UseMEMOP]>;
4435 // memb(Rs+#u6:0) += Rt
4436 let AddedComplexity = 30 in
4437 def MEMb_ADDr_MEM_V4 : MEMInst_V4<(outs),
4438 (ins MEMri:$addr, IntRegs:$addend),
4439 "memb($addr) += $addend",
4440 [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
4441 (i32 IntRegs:$addend)), ADDRriU6_0:$addr)]>,
4442 Requires<[HasV4T, UseMEMOP]>;
4444 // memb(Rs+#u6:0) -= Rt
4445 let AddedComplexity = 30 in
4446 def MEMb_SUBr_MEM_V4 : MEMInst_V4<(outs),
4447 (ins MEMri:$addr, IntRegs:$subend),
4448 "memb($addr) -= $subend",
4449 [(truncstorei8 (sub (sextloadi8 ADDRriU6_0:$addr),
4450 (i32 IntRegs:$subend)), ADDRriU6_0:$addr)]>,
4451 Requires<[HasV4T, UseMEMOP]>;
4453 // memb(Rs+#u6:0) &= Rt
4454 let AddedComplexity = 30 in
4455 def MEMb_ANDr_MEM_V4 : MEMInst_V4<(outs),
4456 (ins MEMri:$addr, IntRegs:$andend),
4457 "memb($addr) &= $andend",
4458 [(truncstorei8 (and (sextloadi8 ADDRriU6_0:$addr),
4459 (i32 IntRegs:$andend)), ADDRriU6_0:$addr)]>,
4460 Requires<[HasV4T, UseMEMOP]>;
4462 // memb(Rs+#u6:0) |= Rt
4463 let AddedComplexity = 30 in
4464 def MEMb_ORr_MEM_V4 : MEMInst_V4<(outs),
4465 (ins MEMri:$addr, IntRegs:$orend),
4466 "memb($addr) |= $orend",
4467 [(truncstorei8 (or (sextloadi8 ADDRriU6_0:$addr),
4468 (i32 IntRegs:$orend)), ADDRriU6_0:$addr)]>,
4469 Requires<[HasV4T, UseMEMOP]>;
4472 //===----------------------------------------------------------------------===//
4474 //===----------------------------------------------------------------------===//
4476 // Hexagon V4 only supports these flavors of byte/half compare instructions:
4477 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
4478 // hardware. However, compiler can still implement these patterns through
4479 // appropriate patterns combinations based on current implemented patterns.
4480 // The implemented patterns are: EQ/GT/GTU.
4481 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
4483 // Following instruction is not being extended as it results into the
4484 // incorrect code for negative numbers.
4485 // Pd=cmpb.eq(Rs,#u8)
4487 let isCompare = 1 in
4488 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
4489 (ins IntRegs:$src1, u8Imm:$src2),
4490 "$dst = cmpb.eq($src1, #$src2)",
4491 [(set (i1 PredRegs:$dst),
4492 (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
4495 // Pd=cmpb.eq(Rs,Rt)
4496 let isCompare = 1 in
4497 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
4498 (ins IntRegs:$src1, IntRegs:$src2),
4499 "$dst = cmpb.eq($src1, $src2)",
4500 [(set (i1 PredRegs:$dst),
4501 (seteq (and (xor (i32 IntRegs:$src1),
4502 (i32 IntRegs:$src2)), 255), 0))]>,
4505 // Pd=cmpb.eq(Rs,Rt)
4506 let isCompare = 1 in
4507 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
4508 (ins IntRegs:$src1, IntRegs:$src2),
4509 "$dst = cmpb.eq($src1, $src2)",
4510 [(set (i1 PredRegs:$dst),
4511 (seteq (shl (i32 IntRegs:$src1), (i32 24)),
4512 (shl (i32 IntRegs:$src2), (i32 24))))]>,
4515 // Pd=cmpb.gt(Rs,Rt)
4516 let isCompare = 1 in
4517 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
4518 (ins IntRegs:$src1, IntRegs:$src2),
4519 "$dst = cmpb.gt($src1, $src2)",
4520 [(set (i1 PredRegs:$dst),
4521 (setgt (shl (i32 IntRegs:$src1), (i32 24)),
4522 (shl (i32 IntRegs:$src2), (i32 24))))]>,
4525 // Pd=cmpb.gtu(Rs,#u7)
4526 let isCompare = 1 in
4527 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
4528 (ins IntRegs:$src1, u7Imm:$src2),
4529 "$dst = cmpb.gtu($src1, #$src2)",
4530 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4531 u7ImmPred:$src2))]>,
4534 // Pd=cmpb.gtu(Rs,Rt)
4535 let isCompare = 1 in
4536 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
4537 (ins IntRegs:$src1, IntRegs:$src2),
4538 "$dst = cmpb.gtu($src1, $src2)",
4539 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4540 (and (i32 IntRegs:$src2), 255)))]>,
4543 // Following instruction is not being extended as it results into the incorrect
4544 // code for negative numbers.
4546 // Signed half compare(.eq) ri.
4547 // Pd=cmph.eq(Rs,#s8)
4548 let isCompare = 1 in
4549 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
4550 (ins IntRegs:$src1, s8Imm:$src2),
4551 "$dst = cmph.eq($src1, #$src2)",
4552 [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
4553 s8ImmPred:$src2))]>,
4556 // Signed half compare(.eq) rr.
4557 // Case 1: xor + and, then compare:
4559 // r0=and(r0,#0xffff)
4561 // Pd=cmph.eq(Rs,Rt)
4562 let isCompare = 1 in
4563 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
4564 (ins IntRegs:$src1, IntRegs:$src2),
4565 "$dst = cmph.eq($src1, $src2)",
4566 [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
4567 (i32 IntRegs:$src2)),
4571 // Signed half compare(.eq) rr.
4572 // Case 2: shift left 16 bits then compare:
4576 // Pd=cmph.eq(Rs,Rt)
4577 let isCompare = 1 in
4578 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
4579 (ins IntRegs:$src1, IntRegs:$src2),
4580 "$dst = cmph.eq($src1, $src2)",
4581 [(set (i1 PredRegs:$dst),
4582 (seteq (shl (i32 IntRegs:$src1), (i32 16)),
4583 (shl (i32 IntRegs:$src2), (i32 16))))]>,
4586 /* Incorrect Pattern -- immediate should be right shifted before being
4587 used in the cmph.gt instruction.
4588 // Signed half compare(.gt) ri.
4589 // Pd=cmph.gt(Rs,#s8)
4591 let isCompare = 1 in
4592 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
4593 (ins IntRegs:$src1, s8Imm:$src2),
4594 "$dst = cmph.gt($src1, #$src2)",
4595 [(set (i1 PredRegs:$dst),
4596 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4597 s8ImmPred:$src2))]>,
4601 // Signed half compare(.gt) rr.
4602 // Pd=cmph.gt(Rs,Rt)
4603 let isCompare = 1 in
4604 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
4605 (ins IntRegs:$src1, IntRegs:$src2),
4606 "$dst = cmph.gt($src1, $src2)",
4607 [(set (i1 PredRegs:$dst),
4608 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4609 (shl (i32 IntRegs:$src2), (i32 16))))]>,
4612 // Unsigned half compare rr (.gtu).
4613 // Pd=cmph.gtu(Rs,Rt)
4614 let isCompare = 1 in
4615 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
4616 (ins IntRegs:$src1, IntRegs:$src2),
4617 "$dst = cmph.gtu($src1, $src2)",
4618 [(set (i1 PredRegs:$dst),
4619 (setugt (and (i32 IntRegs:$src1), 65535),
4620 (and (i32 IntRegs:$src2), 65535)))]>,
4623 // Unsigned half compare ri (.gtu).
4624 // Pd=cmph.gtu(Rs,#u7)
4625 let isCompare = 1 in
4626 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
4627 (ins IntRegs:$src1, u7Imm:$src2),
4628 "$dst = cmph.gtu($src1, #$src2)",
4629 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
4630 u7ImmPred:$src2))]>,
4633 //===----------------------------------------------------------------------===//
4635 //===----------------------------------------------------------------------===//
4637 //Deallocate frame and return.
4639 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
4640 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
4641 def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
4647 // Restore registers and dealloc return function call.
4648 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
4649 Defs = [R29, R30, R31, PC] in {
4650 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
4651 (ins calltarget:$dst),
4652 "jump $dst // Restore_and_dealloc_return",
4657 // Restore registers and dealloc frame before a tail call.
4658 let isCall = 1, isBarrier = 1,
4659 Defs = [R29, R30, R31, PC] in {
4660 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
4661 (ins calltarget:$dst),
4662 "call $dst // Restore_and_dealloc_before_tailcall",
4667 // Save registers function call.
4668 let isCall = 1, isBarrier = 1,
4669 Uses = [R29, R31] in {
4670 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
4671 (ins calltarget:$dst),
4672 "call $dst // Save_calle_saved_registers",
4677 // if (Ps) dealloc_return
4678 let isReturn = 1, isTerminator = 1,
4679 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4680 isPredicated = 1 in {
4681 def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs),
4682 (ins PredRegs:$src1, i32imm:$amt1),
4683 "if ($src1) dealloc_return",
4688 // if (!Ps) dealloc_return
4689 let isReturn = 1, isTerminator = 1,
4690 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4691 isPredicated = 1 in {
4692 def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4694 "if (!$src1) dealloc_return",
4699 // if (Ps.new) dealloc_return:nt
4700 let isReturn = 1, isTerminator = 1,
4701 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4702 isPredicated = 1 in {
4703 def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4705 "if ($src1.new) dealloc_return:nt",
4710 // if (!Ps.new) dealloc_return:nt
4711 let isReturn = 1, isTerminator = 1,
4712 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4713 isPredicated = 1 in {
4714 def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4716 "if (!$src1.new) dealloc_return:nt",
4721 // if (Ps.new) dealloc_return:t
4722 let isReturn = 1, isTerminator = 1,
4723 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4724 isPredicated = 1 in {
4725 def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4727 "if ($src1.new) dealloc_return:t",
4732 // if (!Ps.new) dealloc_return:nt
4733 let isReturn = 1, isTerminator = 1,
4734 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4735 isPredicated = 1 in {
4736 def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4738 "if (!$src1.new) dealloc_return:t",
4744 // Load/Store with absolute addressing mode
4747 multiclass ST_abs<string OpcStr> {
4748 let isPredicable = 1 in
4749 def _abs_V4 : STInst2<(outs),
4750 (ins globaladdress:$absaddr, IntRegs:$src),
4751 !strconcat(OpcStr, "(##$absaddr) = $src"),
4755 let isPredicated = 1 in
4756 def _abs_cPt_V4 : STInst2<(outs),
4757 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4758 !strconcat("if ($src1)",
4759 !strconcat(OpcStr, "(##$absaddr) = $src2")),
4763 let isPredicated = 1 in
4764 def _abs_cNotPt_V4 : STInst2<(outs),
4765 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4766 !strconcat("if (!$src1)",
4767 !strconcat(OpcStr, "(##$absaddr) = $src2")),
4771 let isPredicated = 1 in
4772 def _abs_cdnPt_V4 : STInst2<(outs),
4773 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4774 !strconcat("if ($src1.new)",
4775 !strconcat(OpcStr, "(##$absaddr) = $src2")),
4779 let isPredicated = 1 in
4780 def _abs_cdnNotPt_V4 : STInst2<(outs),
4781 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4782 !strconcat("if (!$src1.new)",
4783 !strconcat(OpcStr, "(##$absaddr) = $src2")),
4787 def _abs_nv_V4 : STInst2<(outs),
4788 (ins globaladdress:$absaddr, IntRegs:$src),
4789 !strconcat(OpcStr, "(##$absaddr) = $src.new"),
4793 let isPredicated = 1 in
4794 def _abs_cPt_nv_V4 : STInst2<(outs),
4795 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4796 !strconcat("if ($src1)",
4797 !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4801 let isPredicated = 1 in
4802 def _abs_cNotPt_nv_V4 : STInst2<(outs),
4803 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4804 !strconcat("if (!$src1)",
4805 !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4809 let isPredicated = 1 in
4810 def _abs_cdnPt_nv_V4 : STInst2<(outs),
4811 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4812 !strconcat("if ($src1.new)",
4813 !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4817 let isPredicated = 1 in
4818 def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
4819 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4820 !strconcat("if (!$src1.new)",
4821 !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4826 let AddedComplexity = 30, isPredicable = 1 in
4827 def STrid_abs_V4 : STInst<(outs),
4828 (ins globaladdress:$absaddr, DoubleRegs:$src),
4829 "memd(##$absaddr) = $src",
4830 [(store (i64 DoubleRegs:$src),
4831 (HexagonCONST32 tglobaladdr:$absaddr))]>,
4834 let AddedComplexity = 30, isPredicated = 1 in
4835 def STrid_abs_cPt_V4 : STInst2<(outs),
4836 (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4837 "if ($src1) memd(##$absaddr) = $src2",
4841 let AddedComplexity = 30, isPredicated = 1 in
4842 def STrid_abs_cNotPt_V4 : STInst2<(outs),
4843 (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4844 "if (!$src1) memd(##$absaddr) = $src2",
4848 let AddedComplexity = 30, isPredicated = 1 in
4849 def STrid_abs_cdnPt_V4 : STInst2<(outs),
4850 (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4851 "if ($src1.new) memd(##$absaddr) = $src2",
4855 let AddedComplexity = 30, isPredicated = 1 in
4856 def STrid_abs_cdnNotPt_V4 : STInst2<(outs),
4857 (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4858 "if (!$src1.new) memd(##$absaddr) = $src2",
4862 defm STrib : ST_abs<"memb">;
4863 defm STrih : ST_abs<"memh">;
4864 defm STriw : ST_abs<"memw">;
4866 let Predicates = [HasV4T], AddedComplexity = 30 in
4867 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
4868 (HexagonCONST32 tglobaladdr:$absaddr)),
4869 (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4871 let Predicates = [HasV4T], AddedComplexity = 30 in
4872 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
4873 (HexagonCONST32 tglobaladdr:$absaddr)),
4874 (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4876 let Predicates = [HasV4T], AddedComplexity = 30 in
4877 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
4878 (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4881 multiclass LD_abs<string OpcStr> {
4882 let isPredicable = 1 in
4883 def _abs_V4 : LDInst2<(outs IntRegs:$dst),
4884 (ins globaladdress:$absaddr),
4885 !strconcat("$dst = ", !strconcat(OpcStr, "(##$absaddr)")),
4889 let isPredicated = 1 in
4890 def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
4891 (ins PredRegs:$src1, globaladdress:$absaddr),
4892 !strconcat("if ($src1) $dst = ",
4893 !strconcat(OpcStr, "(##$absaddr)")),
4897 let isPredicated = 1 in
4898 def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4899 (ins PredRegs:$src1, globaladdress:$absaddr),
4900 !strconcat("if (!$src1) $dst = ",
4901 !strconcat(OpcStr, "(##$absaddr)")),
4905 let isPredicated = 1 in
4906 def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
4907 (ins PredRegs:$src1, globaladdress:$absaddr),
4908 !strconcat("if ($src1.new) $dst = ",
4909 !strconcat(OpcStr, "(##$absaddr)")),
4913 let isPredicated = 1 in
4914 def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4915 (ins PredRegs:$src1, globaladdress:$absaddr),
4916 !strconcat("if (!$src1.new) $dst = ",
4917 !strconcat(OpcStr, "(##$absaddr)")),
4922 let AddedComplexity = 30 in
4923 def LDrid_abs_V4 : LDInst<(outs DoubleRegs:$dst),
4924 (ins globaladdress:$absaddr),
4925 "$dst = memd(##$absaddr)",
4926 [(set (i64 DoubleRegs:$dst),
4927 (load (HexagonCONST32 tglobaladdr:$absaddr)))]>,
4930 let AddedComplexity = 30, isPredicated = 1 in
4931 def LDrid_abs_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4932 (ins PredRegs:$src1, globaladdress:$absaddr),
4933 "if ($src1) $dst = memd(##$absaddr)",
4937 let AddedComplexity = 30, isPredicated = 1 in
4938 def LDrid_abs_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4939 (ins PredRegs:$src1, globaladdress:$absaddr),
4940 "if (!$src1) $dst = memd(##$absaddr)",
4944 let AddedComplexity = 30, isPredicated = 1 in
4945 def LDrid_abs_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4946 (ins PredRegs:$src1, globaladdress:$absaddr),
4947 "if ($src1.new) $dst = memd(##$absaddr)",
4951 let AddedComplexity = 30, isPredicated = 1 in
4952 def LDrid_abs_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4953 (ins PredRegs:$src1, globaladdress:$absaddr),
4954 "if (!$src1.new) $dst = memd(##$absaddr)",
4958 defm LDrib : LD_abs<"memb">;
4959 defm LDriub : LD_abs<"memub">;
4960 defm LDrih : LD_abs<"memh">;
4961 defm LDriuh : LD_abs<"memuh">;
4962 defm LDriw : LD_abs<"memw">;
4965 let Predicates = [HasV4T], AddedComplexity = 30 in
4966 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
4967 (LDriw_abs_V4 tglobaladdr: $absaddr)>;
4969 let Predicates = [HasV4T], AddedComplexity=30 in
4970 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
4971 (LDrib_abs_V4 tglobaladdr:$absaddr)>;
4973 let Predicates = [HasV4T], AddedComplexity=30 in
4974 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
4975 (LDriub_abs_V4 tglobaladdr:$absaddr)>;
4977 let Predicates = [HasV4T], AddedComplexity=30 in
4978 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
4979 (LDrih_abs_V4 tglobaladdr:$absaddr)>;
4981 let Predicates = [HasV4T], AddedComplexity=30 in
4982 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
4983 (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
4985 // Transfer global address into a register
4986 let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
4987 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
4989 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
4992 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4993 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4994 (ins PredRegs:$src1, globaladdress:$src2),
4995 "if($src1) $dst = ##$src2",
4999 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
5000 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
5001 (ins PredRegs:$src1, globaladdress:$src2),
5002 "if(!$src1) $dst = ##$src2",
5006 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
5007 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
5008 (ins PredRegs:$src1, globaladdress:$src2),
5009 "if($src1.new) $dst = ##$src2",
5013 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
5014 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
5015 (ins PredRegs:$src1, globaladdress:$src2),
5016 "if(!$src1.new) $dst = ##$src2",
5020 let AddedComplexity = 50, Predicates = [HasV4T] in
5021 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
5022 (TFRI_V4 tglobaladdr:$src1)>;
5025 // Load - Indirect with long offset: These instructions take global address
5027 let AddedComplexity = 10 in
5028 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
5029 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
5030 "$dst=memd($src1<<#$src2+##$offset)",
5031 [(set (i64 DoubleRegs:$dst),
5032 (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
5033 (HexagonCONST32 tglobaladdr:$offset))))]>,
5036 let AddedComplexity = 10 in
5037 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
5038 def _lo_V4 : LDInst<(outs IntRegs:$dst),
5039 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
5040 !strconcat("$dst = ",
5041 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
5043 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
5044 (HexagonCONST32 tglobaladdr:$offset)))))]>,
5048 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
5049 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
5050 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
5051 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
5052 defm LDriw_ind : LD_indirect_lo<"memw", load>;
5054 // Store - Indirect with long offset: These instructions take global address
5056 let AddedComplexity = 10 in
5057 def STrid_ind_lo_V4 : STInst<(outs),
5058 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
5060 "memd($src1<<#$src2+#$src3) = $src4",
5061 [(store (i64 DoubleRegs:$src4),
5062 (add (shl IntRegs:$src1, u2ImmPred:$src2),
5063 (HexagonCONST32 tglobaladdr:$src3)))]>,
5066 let AddedComplexity = 10 in
5067 multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> {
5068 def _lo_V4 : STInst<(outs),
5069 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
5071 !strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"),
5072 [(OpNode (i32 IntRegs:$src4),
5073 (add (shl IntRegs:$src1, u2ImmPred:$src2),
5074 (HexagonCONST32 tglobaladdr:$src3)))]>,
5078 defm STrib_ind : ST_indirect_lo<"memb", truncstorei8>;
5079 defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>;
5080 defm STriw_ind : ST_indirect_lo<"memw", store>;
5082 // Store - absolute addressing mode: These instruction take constant
5083 // value as the extended operand
5084 multiclass ST_absimm<string OpcStr> {
5085 let isPredicable = 1 in
5086 def _abs_V4 : STInst2<(outs),
5087 (ins u6Imm:$src1, IntRegs:$src2),
5088 !strconcat(OpcStr, "(#$src1) = $src2"),
5092 let isPredicated = 1 in
5093 def _abs_cPt_V4 : STInst2<(outs),
5094 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5095 !strconcat("if ($src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
5099 let isPredicated = 1 in
5100 def _abs_cNotPt_V4 : STInst2<(outs),
5101 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5102 !strconcat("if (!$src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
5106 let isPredicated = 1 in
5107 def _abs_cdnPt_V4 : STInst2<(outs),
5108 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5109 !strconcat("if ($src1.new)",
5110 !strconcat(OpcStr, "(#$src2) = $src3")),
5114 let isPredicated = 1 in
5115 def _abs_cdnNotPt_V4 : STInst2<(outs),
5116 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5117 !strconcat("if (!$src1.new)",
5118 !strconcat(OpcStr, "(#$src2) = $src3")),
5122 def _abs_nv_V4 : STInst2<(outs),
5123 (ins u6Imm:$src1, IntRegs:$src2),
5124 !strconcat(OpcStr, "(#$src1) = $src2.new"),
5128 let isPredicated = 1 in
5129 def _abs_cPt_nv_V4 : STInst2<(outs),
5130 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5131 !strconcat("if ($src1)",
5132 !strconcat(OpcStr, "(#$src2) = $src3.new")),
5136 let isPredicated = 1 in
5137 def _abs_cNotPt_nv_V4 : STInst2<(outs),
5138 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5139 !strconcat("if (!$src1)",
5140 !strconcat(OpcStr, "(#$src2) = $src3.new")),
5144 let isPredicated = 1 in
5145 def _abs_cdnPt_nv_V4 : STInst2<(outs),
5146 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5147 !strconcat("if ($src1.new)",
5148 !strconcat(OpcStr, "(#$src2) = $src3.new")),
5152 let isPredicated = 1 in
5153 def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
5154 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5155 !strconcat("if (!$src1.new)",
5156 !strconcat(OpcStr, "(#$src2) = $src3.new")),
5161 defm STrib_imm : ST_absimm<"memb">;
5162 defm STrih_imm : ST_absimm<"memh">;
5163 defm STriw_imm : ST_absimm<"memw">;
5165 let Predicates = [HasV4T], AddedComplexity = 30 in
5166 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ImmPred:$src2),
5167 (STrib_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
5169 let Predicates = [HasV4T], AddedComplexity = 30 in
5170 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ImmPred:$src2),
5171 (STrih_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
5173 let Predicates = [HasV4T], AddedComplexity = 30 in
5174 def : Pat<(store (i32 IntRegs:$src1), u6ImmPred:$src2),
5175 (STriw_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
5178 // Load - absolute addressing mode: These instruction take constant
5179 // value as the extended operand
5181 multiclass LD_absimm<string OpcStr> {
5182 let isPredicable = 1 in
5183 def _abs_V4 : LDInst2<(outs IntRegs:$dst),
5185 !strconcat("$dst = ",
5186 !strconcat(OpcStr, "(#$src)")),
5190 let isPredicated = 1 in
5191 def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
5192 (ins PredRegs:$src1, u6Imm:$src2),
5193 !strconcat("if ($src1) $dst = ",
5194 !strconcat(OpcStr, "(#$src2)")),
5198 let isPredicated = 1 in
5199 def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
5200 (ins PredRegs:$src1, u6Imm:$src2),
5201 !strconcat("if (!$src1) $dst = ",
5202 !strconcat(OpcStr, "(#$src2)")),
5206 let isPredicated = 1 in
5207 def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
5208 (ins PredRegs:$src1, u6Imm:$src2),
5209 !strconcat("if ($src1.new) $dst = ",
5210 !strconcat(OpcStr, "(#$src2)")),
5214 let isPredicated = 1 in
5215 def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
5216 (ins PredRegs:$src1, u6Imm:$src2),
5217 !strconcat("if (!$src1.new) $dst = ",
5218 !strconcat(OpcStr, "(#$src2)")),
5223 defm LDrib_imm : LD_absimm<"memb">;
5224 defm LDriub_imm : LD_absimm<"memub">;
5225 defm LDrih_imm : LD_absimm<"memh">;
5226 defm LDriuh_imm : LD_absimm<"memuh">;
5227 defm LDriw_imm : LD_absimm<"memw">;
5229 let Predicates = [HasV4T], AddedComplexity = 30 in
5230 def : Pat<(i32 (load u6ImmPred:$src)),
5231 (LDriw_imm_abs_V4 u6ImmPred:$src)>;
5233 let Predicates = [HasV4T], AddedComplexity=30 in
5234 def : Pat<(i32 (sextloadi8 u6ImmPred:$src)),
5235 (LDrib_imm_abs_V4 u6ImmPred:$src)>;
5237 let Predicates = [HasV4T], AddedComplexity=30 in
5238 def : Pat<(i32 (zextloadi8 u6ImmPred:$src)),
5239 (LDriub_imm_abs_V4 u6ImmPred:$src)>;
5241 let Predicates = [HasV4T], AddedComplexity=30 in
5242 def : Pat<(i32 (sextloadi16 u6ImmPred:$src)),
5243 (LDrih_imm_abs_V4 u6ImmPred:$src)>;
5245 let Predicates = [HasV4T], AddedComplexity=30 in
5246 def : Pat<(i32 (zextloadi16 u6ImmPred:$src)),
5247 (LDriuh_imm_abs_V4 u6ImmPred:$src)>;
5250 // Indexed store double word - global address.
5251 // memw(Rs+#u6:2)=#S8
5252 let AddedComplexity = 10 in
5253 def STriw_offset_ext_V4 : STInst<(outs),
5254 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
5255 "memw($src1+#$src2) = ##$src3",
5256 [(store (HexagonCONST32 tglobaladdr:$src3),
5257 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
5261 // Indexed store double word - global address.
5262 // memw(Rs+#u6:2)=#S8
5263 let AddedComplexity = 10 in
5264 def STrih_offset_ext_V4 : STInst<(outs),
5265 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
5266 "memh($src1+#$src2) = ##$src3",
5267 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
5268 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,