1 //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "AlphaRegisterInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/STLExtras.h"
36 static const int IMM_LOW = -32768;
37 static const int IMM_HIGH = 32767;
38 static const int IMM_MULT = 65536;
40 static long getUpper16(long l)
42 long y = l / IMM_MULT;
43 if (l % IMM_MULT > IMM_HIGH)
48 static long getLower16(long l)
50 long h = getUpper16(l);
51 return l - h * IMM_MULT;
54 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
55 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
61 AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MI,
63 unsigned SrcReg, int FrameIdx,
64 const TargetRegisterClass *RC) const {
65 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
66 // << FrameIdx << "\n";
67 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
68 if (RC == Alpha::F4RCRegisterClass)
69 BuildMI(MBB, MI, TII.get(Alpha::STS))
70 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
71 else if (RC == Alpha::F8RCRegisterClass)
72 BuildMI(MBB, MI, TII.get(Alpha::STT))
73 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
74 else if (RC == Alpha::GPRCRegisterClass)
75 BuildMI(MBB, MI, TII.get(Alpha::STQ))
76 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
82 AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator MI,
84 unsigned DestReg, int FrameIdx,
85 const TargetRegisterClass *RC) const {
86 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
87 // << FrameIdx << "\n";
88 if (RC == Alpha::F4RCRegisterClass)
89 BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
90 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
91 else if (RC == Alpha::F8RCRegisterClass)
92 BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
93 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
94 else if (RC == Alpha::GPRCRegisterClass)
95 BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
96 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
101 MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
103 int FrameIndex) const {
104 // Make sure this is a reg-reg copy.
105 unsigned Opc = MI->getOpcode();
107 MachineInstr *NewMI = NULL;
114 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
115 if (OpNum == 0) { // move -> store
116 unsigned InReg = MI->getOperand(1).getReg();
117 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
118 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
119 NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
121 } else { // load -> move
122 unsigned OutReg = MI->getOperand(0).getReg();
123 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
124 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
125 NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
132 NewMI->copyKillDeadInfo(MI);
137 void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
138 MachineBasicBlock::iterator MI,
139 unsigned DestReg, unsigned SrcReg,
140 const TargetRegisterClass *RC) const {
141 //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
142 if (RC == Alpha::GPRCRegisterClass) {
143 BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
144 } else if (RC == Alpha::F4RCRegisterClass) {
145 BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
146 } else if (RC == Alpha::F8RCRegisterClass) {
147 BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
149 cerr << "Attempt to copy register that is not GPR or FPR";
154 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs() const {
155 static const unsigned CalleeSavedRegs[] = {
156 Alpha::R9, Alpha::R10,
157 Alpha::R11, Alpha::R12,
158 Alpha::R13, Alpha::R14,
159 Alpha::F2, Alpha::F3,
160 Alpha::F4, Alpha::F5,
161 Alpha::F6, Alpha::F7,
162 Alpha::F8, Alpha::F9, 0
164 return CalleeSavedRegs;
167 const TargetRegisterClass* const*
168 AlphaRegisterInfo::getCalleeSavedRegClasses() const {
169 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
170 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
171 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
172 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
173 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
174 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
175 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
176 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
178 return CalleeSavedRegClasses;
181 //===----------------------------------------------------------------------===//
182 // Stack Frame Processing methods
183 //===----------------------------------------------------------------------===//
185 // hasFP - Return true if the specified function should have a dedicated frame
186 // pointer register. This is true if the function has variable sized allocas or
187 // if frame pointer elimination is disabled.
189 static bool hasFP(const MachineFunction &MF) {
190 MachineFrameInfo *MFI = MF.getFrameInfo();
191 return MFI->hasVarSizedObjects();
194 void AlphaRegisterInfo::
195 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
196 MachineBasicBlock::iterator I) const {
198 // If we have a frame pointer, turn the adjcallstackup instruction into a
199 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
201 MachineInstr *Old = I;
202 uint64_t Amount = Old->getOperand(0).getImmedValue();
204 // We need to keep the stack aligned properly. To do this, we round the
205 // amount of space needed for the outgoing arguments up to the next
206 // alignment boundary.
207 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
208 Amount = (Amount+Align-1)/Align*Align;
211 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
212 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
213 .addImm(-Amount).addReg(Alpha::R30);
215 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
216 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
217 .addImm(Amount).addReg(Alpha::R30);
220 // Replace the pseudo instruction with a new instruction...
228 //Alpha has a slightly funny stack:
231 //fixed locals (and spills, callee saved, etc)
237 AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
239 MachineInstr &MI = *II;
240 MachineBasicBlock &MBB = *MI.getParent();
241 MachineFunction &MF = *MBB.getParent();
244 while (!MI.getOperand(i).isFrameIndex()) {
246 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
249 int FrameIndex = MI.getOperand(i).getFrameIndex();
251 // Add the base register of R30 (SP) or R15 (FP).
252 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
254 // Now add the frame object offset to the offset from the virtual frame index.
255 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
257 DOUT << "FI: " << FrameIndex << " Offset: " << Offset << "\n";
259 Offset += MF.getFrameInfo()->getStackSize();
261 DOUT << "Corrected Offset " << Offset
262 << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n";
264 if (Offset > IMM_HIGH || Offset < IMM_LOW) {
265 DOUT << "Unconditionally using R28 for evil purposes Offset: "
267 //so in this case, we need to use a temporary register, and move the
268 //original inst off the SP/FP
270 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
271 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
273 MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28)
274 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
277 MI.getOperand(i).ChangeToImmediate(Offset);
282 void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
283 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
284 MachineBasicBlock::iterator MBBI = MBB.begin();
285 MachineFrameInfo *MFI = MF.getFrameInfo();
288 static int curgpdist = 0;
291 BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29)
292 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
293 .addReg(Alpha::R27).addImm(++curgpdist);
294 BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29)
295 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
296 .addReg(Alpha::R29).addImm(curgpdist);
298 //evil const_cast until MO stuff setup to handle const
299 BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT))
300 .addGlobalAddress(const_cast<Function*>(MF.getFunction()));
302 // Get the number of bytes to allocate from the FrameInfo
303 long NumBytes = MFI->getStackSize();
305 if (MFI->hasCalls() && !FP) {
306 // We reserve argument space for call sites in the function immediately on
307 // entry to the current function. This eliminates the need for add/sub
308 // brackets around call sites.
309 //If there is a frame pointer, then we don't do this
310 NumBytes += MFI->getMaxCallFrameSize();
311 DOUT << "Added " << MFI->getMaxCallFrameSize()
312 << " to the stack due to calls\n";
316 NumBytes += 8; //reserve space for the old FP
318 // Do we need to allocate space on the stack?
319 if (NumBytes == 0) return;
321 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
322 NumBytes = (NumBytes+Align-1)/Align*Align;
324 // Update frame info to pretend that this is part of the stack...
325 MFI->setStackSize(NumBytes);
327 // adjust stack pointer: r30 -= numbytes
328 NumBytes = -NumBytes;
329 if (NumBytes >= IMM_LOW) {
330 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
332 } else if (getUpper16(NumBytes) >= IMM_LOW) {
333 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes))
335 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes))
338 cerr << "Too big a stack frame at " << NumBytes << "\n";
342 //now if we need to, save the old FP and set the new
345 BuildMI(MBB, MBBI, TII.get(Alpha::STQ))
346 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
347 //this must be the last instr in the prolog
348 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15)
349 .addReg(Alpha::R30).addReg(Alpha::R30);
354 void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
355 MachineBasicBlock &MBB) const {
356 const MachineFrameInfo *MFI = MF.getFrameInfo();
357 MachineBasicBlock::iterator MBBI = prior(MBB.end());
358 assert(MBBI->getOpcode() == Alpha::RETDAG ||
359 MBBI->getOpcode() == Alpha::RETDAGp
360 && "Can only insert epilog into returning blocks");
364 // Get the number of bytes allocated from the FrameInfo...
365 long NumBytes = MFI->getStackSize();
367 //now if we need to, restore the old FP
370 //copy the FP into the SP (discards allocas)
371 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
374 BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15);
379 if (NumBytes <= IMM_HIGH) {
380 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
382 } else if (getUpper16(NumBytes) <= IMM_HIGH) {
383 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30)
384 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
385 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30)
386 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
388 cerr << "Too big a stack frame at " << NumBytes << "\n";
394 unsigned AlphaRegisterInfo::getRARegister() const {
395 assert(0 && "What is the return address register");
399 unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const {
400 return hasFP(MF) ? Alpha::R15 : Alpha::R30;
403 #include "AlphaGenRegisterInfo.inc"
405 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
407 std::string s(RegisterDescriptors[reg].Name);