Fix naming inconsistency.
authorEvan Cheng <evan.cheng@apple.com>
Tue, 2 Jan 2007 21:33:40 +0000 (21:33 +0000)
committerEvan Cheng <evan.cheng@apple.com>
Tue, 2 Jan 2007 21:33:40 +0000 (21:33 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32823 91177308-0d34-0410-b5e6-96231b3b80d8

12 files changed:
lib/Target/ARM/ARMRegisterInfo.cpp
lib/Target/ARM/ARMRegisterInfo.h
lib/Target/Alpha/AlphaRegisterInfo.cpp
lib/Target/Alpha/AlphaRegisterInfo.h
lib/Target/IA64/IA64RegisterInfo.cpp
lib/Target/IA64/IA64RegisterInfo.h
lib/Target/PowerPC/PPCRegisterInfo.cpp
lib/Target/PowerPC/PPCRegisterInfo.h
lib/Target/Sparc/SparcRegisterInfo.cpp
lib/Target/Sparc/SparcRegisterInfo.h
lib/Target/X86/X86RegisterInfo.cpp
lib/Target/X86/X86RegisterInfo.h

index 73fd7a4899de8fdce0a7f1a4e9e561d691daa91d..404ebee0f48722079159894614f4b7807e034ec2 100644 (file)
@@ -157,23 +157,23 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
   return NULL;
 }
 
-const unsigned* ARMRegisterInfo::getCalleeSaveRegs() const {
-  static const unsigned CalleeSaveRegs[] = {
+const unsigned* ARMRegisterInfo::getCalleeSavedRegs() const {
+  static const unsigned CalleeSavedRegs[] = {
     ARM::R4,  ARM::R5, ARM::R6,  ARM::R7,
     ARM::R8,  ARM::R9, ARM::R10, ARM::R11,
     ARM::R14, 0
   };
-  return CalleeSaveRegs;
+  return CalleeSavedRegs;
 }
 
 const TargetRegisterClass* const *
-ARMRegisterInfo::getCalleeSaveRegClasses() const {
-  static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
+ARMRegisterInfo::getCalleeSavedRegClasses() const {
+  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
     &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass,
     &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass,
     &ARM::IntRegsRegClass, 0
   };
-  return CalleeSaveRegClasses;
+  return CalleeSavedRegClasses;
 }
 
 void ARMRegisterInfo::
index 9ef761832c6290c0d5c5897d6f4fef996f65e6de..16c277ed928705db492d290649f9717843a5e438 100644 (file)
@@ -47,9 +47,9 @@ struct ARMRegisterInfo : public ARMGenRegisterInfo {
                                           unsigned OpNum,
                                           int FrameIndex) const;
 
-  const unsigned *getCalleeSaveRegs() const;
+  const unsigned *getCalleeSavedRegs() const;
 
-  const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+  const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
                                      MachineBasicBlock &MBB,
index bafd3b3229e0701ec3fcff099af7bd352bebc438..5ad7b1962175f6545e8493c9b4a022ef4807275a 100644 (file)
@@ -151,8 +151,8 @@ void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
   }
 }
 
-const unsigned* AlphaRegisterInfo::getCalleeSaveRegs() const {
-  static const unsigned CalleeSaveRegs[] = {
+const unsigned* AlphaRegisterInfo::getCalleeSavedRegs() const {
+  static const unsigned CalleeSavedRegs[] = {
     Alpha::R9, Alpha::R10,
     Alpha::R11, Alpha::R12,
     Alpha::R13, Alpha::R14,
@@ -161,12 +161,12 @@ const unsigned* AlphaRegisterInfo::getCalleeSaveRegs() const {
     Alpha::F6, Alpha::F7,
     Alpha::F8, Alpha::F9,  0
   };
-  return CalleeSaveRegs;
+  return CalleeSavedRegs;
 }
 
 const TargetRegisterClass* const*
-AlphaRegisterInfo::getCalleeSaveRegClasses() const {
-  static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
+AlphaRegisterInfo::getCalleeSavedRegClasses() const {
+  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
     &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
     &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
     &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
@@ -175,7 +175,7 @@ AlphaRegisterInfo::getCalleeSaveRegClasses() const {
     &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
     &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,  0
   };
-  return CalleeSaveRegClasses;
+  return CalleeSavedRegClasses;
 }
 
 //===----------------------------------------------------------------------===//
index 2cd9e8dc5da9d65a0277513a8f615d6eb131ec02..6e76e4c50821c306410444225b65896215e40230 100644 (file)
@@ -45,9 +45,9 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
                     unsigned DestReg, unsigned SrcReg,
                     const TargetRegisterClass *RC) const;
 
-  const unsigned *getCalleeSaveRegs() const;
+  const unsigned *getCalleeSavedRegs() const;
 
-  const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+  const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
                                      MachineBasicBlock &MBB,
index 3c66c448536d7ad1d572a63314fd3ceed8a4f62d..4e6ebd64ab7bb2e5d7d28ee5854bd96741130543 100644 (file)
@@ -91,19 +91,19 @@ void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
     BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg);
 }
 
-const unsigned* IA64RegisterInfo::getCalleeSaveRegs() const {
-  static const unsigned CalleeSaveRegs[] = {
+const unsigned* IA64RegisterInfo::getCalleeSavedRegs() const {
+  static const unsigned CalleeSavedRegs[] = {
     IA64::r5,  0
   };
-  return CalleeSaveRegs;
+  return CalleeSavedRegs;
 }
 
 const TargetRegisterClass* const*
-IA64RegisterInfo::getCalleeSaveRegClasses() const {
-  static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
+IA64RegisterInfo::getCalleeSavedRegClasses() const {
+  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
     &IA64::GRRegClass,  0
   };
-  return CalleeSaveRegClasses;
+  return CalleeSavedRegClasses;
 }
 
 //===----------------------------------------------------------------------===//
index feb6d3e697441cb2bff9caa3bf99f4f5d3ed775d..e107e7d1c95ca5ed83d7772328eac44729009d8b 100644 (file)
@@ -44,9 +44,9 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
                     unsigned DestReg, unsigned SrcReg,
                     const TargetRegisterClass *RC) const;
 
-  const unsigned *getCalleeSaveRegs() const;
+  const unsigned *getCalleeSavedRegs() const;
 
-  const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+  const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
                                      MachineBasicBlock &MBB,
index 61639c0d3f2b7c2367125a7fca3853628aae4660..371ab7fa478968ac07a92695d505129c5923b371 100644 (file)
@@ -238,9 +238,9 @@ void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
   }
 }
 
-const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
+const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
   // 32-bit Darwin calling convention. 
-  static const unsigned Darwin32_CalleeSaveRegs[] = {
+  static const unsigned Darwin32_CalleeSavedRegs[] = {
               PPC::R13, PPC::R14, PPC::R15,
     PPC::R16, PPC::R17, PPC::R18, PPC::R19,
     PPC::R20, PPC::R21, PPC::R22, PPC::R23,
@@ -261,7 +261,7 @@ const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
     PPC::LR,  0
   };
   // 64-bit Darwin calling convention. 
-  static const unsigned Darwin64_CalleeSaveRegs[] = {
+  static const unsigned Darwin64_CalleeSavedRegs[] = {
     PPC::X14, PPC::X15,
     PPC::X16, PPC::X17, PPC::X18, PPC::X19,
     PPC::X20, PPC::X21, PPC::X22, PPC::X23,
@@ -282,14 +282,14 @@ const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
     PPC::LR8,  0
   };
   
-  return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs :
-                               Darwin32_CalleeSaveRegs;
+  return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
+                               Darwin32_CalleeSavedRegs;
 }
 
 const TargetRegisterClass* const*
-PPCRegisterInfo::getCalleeSaveRegClasses() const {
+PPCRegisterInfo::getCalleeSavedRegClasses() const {
   // 32-bit Darwin calling convention. 
-  static const TargetRegisterClass * const Darwin32_CalleeSaveRegClasses[] = {
+  static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
                        &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
     &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
     &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
@@ -312,7 +312,7 @@ PPCRegisterInfo::getCalleeSaveRegClasses() const {
   };
   
   // 64-bit Darwin calling convention. 
-  static const TargetRegisterClass * const Darwin64_CalleeSaveRegClasses[] = {
+  static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
     &PPC::G8RCRegClass,&PPC::G8RCRegClass,
     &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
     &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
@@ -334,8 +334,8 @@ PPCRegisterInfo::getCalleeSaveRegClasses() const {
     &PPC::G8RCRegClass, 0
   };
  
-  return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegClasses :
-                               Darwin32_CalleeSaveRegClasses;
+  return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
+                               Darwin32_CalleeSavedRegClasses;
 }
 
 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
index 4f916a66582a1c88b2059bbb3bb16602d55dc31c..5af613896e3fccf5d70cdf3e9955b2f3a12e3989 100644 (file)
@@ -54,9 +54,9 @@ public:
   virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
                                           int FrameIndex) const;
   
-  const unsigned *getCalleeSaveRegs() const;
+  const unsigned *getCalleeSavedRegs() const;
 
-  const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+  const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
                                      MachineBasicBlock &MBB,
index eee4f6c87395ad808e105a79428f104ca5602782..0c884369fb8339c93d1f108675a8d496be86abfd 100644 (file)
@@ -111,15 +111,15 @@ MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
   return NewMI;
 }
 
-const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {
-  static const unsigned CalleeSaveRegs[] = { 0 };
-  return CalleeSaveRegs;
+const unsigned* SparcRegisterInfo::getCalleeSavedRegs() const {
+  static const unsigned CalleeSavedRegs[] = { 0 };
+  return CalleeSavedRegs;
 }
 
 const TargetRegisterClass* const*
-SparcRegisterInfo::getCalleeSaveRegClasses() const {
-  static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
-  return CalleeSaveRegClasses;
+SparcRegisterInfo::getCalleeSavedRegClasses() const {
+  static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
+  return CalleeSavedRegClasses;
 }
 
 
index 37d687ed4d7b4d355e612fe1c3074ecd165ccf8f..263a95fe80db4e3b667638a528521e62b2e6c222 100644 (file)
@@ -48,9 +48,9 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
                                           unsigned OpNum,
                                           int FrameIndex) const;
 
-  const unsigned *getCalleeSaveRegs() const;
+  const unsigned *getCalleeSavedRegs() const;
 
-  const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+  const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
                                      MachineBasicBlock &MBB,
index 2eeb04f7c50e739d0c43e389cabbe97c6d13bccd..2e899a5fae72472e6bb63b1e06eed1ca050d24d4 100644 (file)
@@ -853,30 +853,30 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
 }
 
 
-const unsigned *X86RegisterInfo::getCalleeSaveRegs() const {
-  static const unsigned CalleeSaveRegs32Bit[] = {
+const unsigned *X86RegisterInfo::getCalleeSavedRegs() const {
+  static const unsigned CalleeSavedRegs32Bit[] = {
     X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
   };
-  static const unsigned CalleeSaveRegs64Bit[] = {
+  static const unsigned CalleeSavedRegs64Bit[] = {
     X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
   };
 
-  return Is64Bit ? CalleeSaveRegs64Bit : CalleeSaveRegs32Bit;
+  return Is64Bit ? CalleeSavedRegs64Bit : CalleeSavedRegs32Bit;
 }
 
 const TargetRegisterClass* const*
-X86RegisterInfo::getCalleeSaveRegClasses() const {
-  static const TargetRegisterClass * const CalleeSaveRegClasses32Bit[] = {
+X86RegisterInfo::getCalleeSavedRegClasses() const {
+  static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
     &X86::GR32RegClass, &X86::GR32RegClass,
     &X86::GR32RegClass, &X86::GR32RegClass,  0
   };
-  static const TargetRegisterClass * const CalleeSaveRegClasses64Bit[] = {
+  static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
     &X86::GR64RegClass, &X86::GR64RegClass,
     &X86::GR64RegClass, &X86::GR64RegClass,
     &X86::GR64RegClass, &X86::GR64RegClass, 0
   };
 
-  return Is64Bit ? CalleeSaveRegClasses64Bit : CalleeSaveRegClasses32Bit;
+  return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
 }
 
 //===----------------------------------------------------------------------===//
index df43b86d2aec5bb101c0c9a4ee8ebbec57dfb8b7..d8bf486cae41d8800fd5965cfa7b442fa0b590ef 100644 (file)
@@ -69,14 +69,14 @@ public:
                                   unsigned OpNum,
                                   int FrameIndex) const;
 
-  /// getCalleeSaveRegs - Return a null-terminated list of all of the
+  /// getCalleeSavedRegs - Return a null-terminated list of all of the
   /// callee-save registers on this target.
-  const unsigned *getCalleeSaveRegs() const;
+  const unsigned *getCalleeSavedRegs() const;
 
-  /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
+  /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
   /// register classes to spill each callee-saved register with.  The order and
-  /// length of this list match the getCalleeSaveRegs() list.
-  const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+  /// length of this list match the getCalleeSavedRegs() list.
+  const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
                                      MachineBasicBlock &MBB,