1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "llvm/MC/EDInstInfo.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCDisassembler.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Support/raw_ostream.h"
30 typedef MCDisassembler::DecodeStatus DecodeStatus;
33 /// ARMDisassembler - ARM disassembler for all ARM platforms.
34 class ARMDisassembler : public MCDisassembler {
36 /// Constructor - Initializes the disassembler.
38 ARMDisassembler(const MCSubtargetInfo &STI) :
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
48 const MemoryObject ®ion,
51 raw_ostream &cStream) const;
53 /// getEDInfo - See MCDisassembler.
54 const EDInstInfo *getEDInfo() const;
58 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
59 class ThumbDisassembler : public MCDisassembler {
61 /// Constructor - Initializes the disassembler.
63 ThumbDisassembler(const MCSubtargetInfo &STI) :
67 ~ThumbDisassembler() {
70 /// getInstruction - See MCDisassembler.
71 DecodeStatus getInstruction(MCInst &instr,
73 const MemoryObject ®ion,
76 raw_ostream &cStream) const;
78 /// getEDInfo - See MCDisassembler.
79 const EDInstInfo *getEDInfo() const;
81 mutable std::vector<unsigned> ITBlock;
82 DecodeStatus AddThumbPredicate(MCInst&) const;
83 void UpdateThumbVFPPredicate(MCInst&) const;
87 static bool Check(DecodeStatus &Out, DecodeStatus In) {
89 case MCDisassembler::Success:
90 // Out stays the same.
92 case MCDisassembler::SoftFail:
95 case MCDisassembler::Fail:
99 llvm_unreachable("Invalid DecodeStatus!");
103 // Forward declare these because the autogenerated code will reference them.
104 // Definitions are further down.
105 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
106 uint64_t Address, const void *Decoder);
107 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
108 unsigned RegNo, uint64_t Address,
109 const void *Decoder);
110 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
111 uint64_t Address, const void *Decoder);
112 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
113 uint64_t Address, const void *Decoder);
114 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
115 uint64_t Address, const void *Decoder);
116 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
117 uint64_t Address, const void *Decoder);
118 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
119 uint64_t Address, const void *Decoder);
120 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
121 uint64_t Address, const void *Decoder);
122 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
125 const void *Decoder);
126 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
127 uint64_t Address, const void *Decoder);
128 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
129 uint64_t Address, const void *Decoder);
130 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
131 unsigned RegNo, uint64_t Address,
132 const void *Decoder);
134 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
135 uint64_t Address, const void *Decoder);
136 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
137 uint64_t Address, const void *Decoder);
138 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
139 uint64_t Address, const void *Decoder);
140 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
141 uint64_t Address, const void *Decoder);
142 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
143 uint64_t Address, const void *Decoder);
144 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
145 uint64_t Address, const void *Decoder);
147 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
148 uint64_t Address, const void *Decoder);
149 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
150 uint64_t Address, const void *Decoder);
151 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
154 const void *Decoder);
155 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
156 uint64_t Address, const void *Decoder);
157 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
158 uint64_t Address, const void *Decoder);
159 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
160 uint64_t Address, const void *Decoder);
161 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
162 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
167 const void *Decoder);
168 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
185 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
201 uint64_t Address, const void *Decoder);
202 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
203 uint64_t Address, const void *Decoder);
204 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
205 uint64_t Address, const void *Decoder);
206 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
207 uint64_t Address, const void *Decoder);
208 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
209 uint64_t Address, const void *Decoder);
210 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
211 uint64_t Address, const void *Decoder);
212 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
213 uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
215 uint64_t Address, const void *Decoder);
216 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
217 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
219 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
261 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
317 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
323 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
325 uint64_t Address, const void *Decoder);
327 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
328 uint64_t Address, const void *Decoder);
329 #include "ARMGenDisassemblerTables.inc"
330 #include "ARMGenInstrInfo.inc"
331 #include "ARMGenEDInfo.inc"
333 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
334 return new ARMDisassembler(STI);
337 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
338 return new ThumbDisassembler(STI);
341 const EDInstInfo *ARMDisassembler::getEDInfo() const {
345 const EDInstInfo *ThumbDisassembler::getEDInfo() const {
349 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
350 const MemoryObject &Region,
353 raw_ostream &cs) const {
358 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
359 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
361 // We want to read exactly 4 bytes of data.
362 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
364 return MCDisassembler::Fail;
367 // Encoded as a small-endian 32-bit word in the stream.
368 uint32_t insn = (bytes[3] << 24) |
373 // Calling the auto-generated decoder function.
374 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
375 if (result != MCDisassembler::Fail) {
380 // VFP and NEON instructions, similarly, are shared between ARM
383 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
384 if (result != MCDisassembler::Fail) {
390 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
391 if (result != MCDisassembler::Fail) {
393 // Add a fake predicate operand, because we share these instruction
394 // definitions with Thumb2 where these instructions are predicable.
395 if (!DecodePredicateOperand(MI, 0xE, Address, this))
396 return MCDisassembler::Fail;
401 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
402 if (result != MCDisassembler::Fail) {
404 // Add a fake predicate operand, because we share these instruction
405 // definitions with Thumb2 where these instructions are predicable.
406 if (!DecodePredicateOperand(MI, 0xE, Address, this))
407 return MCDisassembler::Fail;
412 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
413 if (result != MCDisassembler::Fail) {
415 // Add a fake predicate operand, because we share these instruction
416 // definitions with Thumb2 where these instructions are predicable.
417 if (!DecodePredicateOperand(MI, 0xE, Address, this))
418 return MCDisassembler::Fail;
425 return MCDisassembler::Fail;
429 extern const MCInstrDesc ARMInsts[];
432 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
433 /// immediate Value in the MCInst. The immediate Value has had any PC
434 /// adjustment made by the caller. If the instruction is a branch instruction
435 /// then isBranch is true, else false. If the getOpInfo() function was set as
436 /// part of the setupForSymbolicDisassembly() call then that function is called
437 /// to get any symbolic information at the Address for this instruction. If
438 /// that returns non-zero then the symbolic information it returns is used to
439 /// create an MCExpr and that is added as an operand to the MCInst. If
440 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
441 /// Value is done and if a symbol is found an MCExpr is created with that, else
442 /// an MCExpr with Value is created. This function returns true if it adds an
443 /// operand to the MCInst and false otherwise.
444 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
445 bool isBranch, uint64_t InstSize,
446 MCInst &MI, const void *Decoder) {
447 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
448 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
449 struct LLVMOpInfo1 SymbolicOp;
450 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
451 SymbolicOp.Value = Value;
452 void *DisInfo = Dis->getDisInfoBlock();
455 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
456 // Clear SymbolicOp.Value from above and also all other fields.
457 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
458 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
461 uint64_t ReferenceType;
463 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
465 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
466 const char *ReferenceName;
467 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
470 SymbolicOp.AddSymbol.Name = Name;
471 SymbolicOp.AddSymbol.Present = true;
473 // For branches always create an MCExpr so it gets printed as hex address.
475 SymbolicOp.Value = Value;
477 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
478 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
479 if (!Name && !isBranch)
483 MCContext *Ctx = Dis->getMCContext();
484 const MCExpr *Add = NULL;
485 if (SymbolicOp.AddSymbol.Present) {
486 if (SymbolicOp.AddSymbol.Name) {
487 StringRef Name(SymbolicOp.AddSymbol.Name);
488 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
489 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
491 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
495 const MCExpr *Sub = NULL;
496 if (SymbolicOp.SubtractSymbol.Present) {
497 if (SymbolicOp.SubtractSymbol.Name) {
498 StringRef Name(SymbolicOp.SubtractSymbol.Name);
499 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
500 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
502 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
506 const MCExpr *Off = NULL;
507 if (SymbolicOp.Value != 0)
508 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
514 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
516 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
518 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
523 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
530 Expr = MCConstantExpr::Create(0, *Ctx);
533 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
534 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
535 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
536 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
537 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
538 MI.addOperand(MCOperand::CreateExpr(Expr));
540 llvm_unreachable("bad SymbolicOp.VariantKind");
545 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
546 /// referenced by a load instruction with the base register that is the Pc.
547 /// These can often be values in a literal pool near the Address of the
548 /// instruction. The Address of the instruction and its immediate Value are
549 /// used as a possible literal pool entry. The SymbolLookUp call back will
550 /// return the name of a symbol referenced by the the literal pool's entry if
551 /// the referenced address is that of a symbol. Or it will return a pointer to
552 /// a literal 'C' string if the referenced address of the literal pool's entry
553 /// is an address into a section with 'C' string literals.
554 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
555 const void *Decoder) {
556 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
557 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
559 void *DisInfo = Dis->getDisInfoBlock();
560 uint64_t ReferenceType;
561 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
562 const char *ReferenceName;
563 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
564 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
565 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
566 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
570 // Thumb1 instructions don't have explicit S bits. Rather, they
571 // implicitly set CPSR. Since it's not represented in the encoding, the
572 // auto-generated decoder won't inject the CPSR operand. We need to fix
573 // that as a post-pass.
574 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
575 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
576 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
577 MCInst::iterator I = MI.begin();
578 for (unsigned i = 0; i < NumOps; ++i, ++I) {
579 if (I == MI.end()) break;
580 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
581 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
582 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
587 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
590 // Most Thumb instructions don't have explicit predicates in the
591 // encoding, but rather get their predicates from IT context. We need
592 // to fix up the predicate operands using this context information as a
594 MCDisassembler::DecodeStatus
595 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
596 MCDisassembler::DecodeStatus S = Success;
598 // A few instructions actually have predicates encoded in them. Don't
599 // try to overwrite it if we're seeing one of those.
600 switch (MI.getOpcode()) {
611 // Some instructions (mostly conditional branches) are not
612 // allowed in IT blocks.
613 if (!ITBlock.empty())
622 // Some instructions (mostly unconditional branches) can
623 // only appears at the end of, or outside of, an IT.
624 if (ITBlock.size() > 1)
631 // If we're in an IT block, base the predicate on that. Otherwise,
632 // assume a predicate of AL.
634 if (!ITBlock.empty()) {
642 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
643 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
644 MCInst::iterator I = MI.begin();
645 for (unsigned i = 0; i < NumOps; ++i, ++I) {
646 if (I == MI.end()) break;
647 if (OpInfo[i].isPredicate()) {
648 I = MI.insert(I, MCOperand::CreateImm(CC));
651 MI.insert(I, MCOperand::CreateReg(0));
653 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
658 I = MI.insert(I, MCOperand::CreateImm(CC));
661 MI.insert(I, MCOperand::CreateReg(0));
663 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
668 // Thumb VFP instructions are a special case. Because we share their
669 // encodings between ARM and Thumb modes, and they are predicable in ARM
670 // mode, the auto-generated decoder will give them an (incorrect)
671 // predicate operand. We need to rewrite these operands based on the IT
672 // context as a post-pass.
673 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
675 if (!ITBlock.empty()) {
681 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
682 MCInst::iterator I = MI.begin();
683 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
684 for (unsigned i = 0; i < NumOps; ++i, ++I) {
685 if (OpInfo[i].isPredicate() ) {
691 I->setReg(ARM::CPSR);
697 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
698 const MemoryObject &Region,
701 raw_ostream &cs) const {
706 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
707 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
709 // We want to read exactly 2 bytes of data.
710 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
712 return MCDisassembler::Fail;
715 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
716 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
717 if (result != MCDisassembler::Fail) {
719 Check(result, AddThumbPredicate(MI));
724 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
727 bool InITBlock = !ITBlock.empty();
728 Check(result, AddThumbPredicate(MI));
729 AddThumb1SBit(MI, InITBlock);
734 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
735 if (result != MCDisassembler::Fail) {
738 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
739 // the Thumb predicate.
740 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
741 result = MCDisassembler::SoftFail;
743 Check(result, AddThumbPredicate(MI));
745 // If we find an IT instruction, we need to parse its condition
746 // code and mask operands so that we can apply them correctly
747 // to the subsequent instructions.
748 if (MI.getOpcode() == ARM::t2IT) {
750 // (3 - the number of trailing zeros) is the number of then / else.
751 unsigned firstcond = MI.getOperand(0).getImm();
752 unsigned Mask = MI.getOperand(1).getImm();
753 unsigned CondBit0 = Mask >> 4 & 1;
754 unsigned NumTZ = CountTrailingZeros_32(Mask);
755 assert(NumTZ <= 3 && "Invalid IT mask!");
756 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
757 bool T = ((Mask >> Pos) & 1) == CondBit0;
759 ITBlock.insert(ITBlock.begin(), firstcond);
761 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
764 ITBlock.push_back(firstcond);
770 // We want to read exactly 4 bytes of data.
771 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
773 return MCDisassembler::Fail;
776 uint32_t insn32 = (bytes[3] << 8) |
781 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
782 if (result != MCDisassembler::Fail) {
784 bool InITBlock = ITBlock.size();
785 Check(result, AddThumbPredicate(MI));
786 AddThumb1SBit(MI, InITBlock);
791 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
792 if (result != MCDisassembler::Fail) {
794 Check(result, AddThumbPredicate(MI));
799 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
800 if (result != MCDisassembler::Fail) {
802 UpdateThumbVFPPredicate(MI);
807 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
808 if (result != MCDisassembler::Fail) {
810 Check(result, AddThumbPredicate(MI));
814 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
816 uint32_t NEONLdStInsn = insn32;
817 NEONLdStInsn &= 0xF0FFFFFF;
818 NEONLdStInsn |= 0x04000000;
819 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
820 if (result != MCDisassembler::Fail) {
822 Check(result, AddThumbPredicate(MI));
827 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
829 uint32_t NEONDataInsn = insn32;
830 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
831 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
832 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
833 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
834 if (result != MCDisassembler::Fail) {
836 Check(result, AddThumbPredicate(MI));
842 return MCDisassembler::Fail;
846 extern "C" void LLVMInitializeARMDisassembler() {
847 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
848 createARMDisassembler);
849 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
850 createThumbDisassembler);
853 static const uint16_t GPRDecoderTable[] = {
854 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
855 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
856 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
857 ARM::R12, ARM::SP, ARM::LR, ARM::PC
860 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
861 uint64_t Address, const void *Decoder) {
863 return MCDisassembler::Fail;
865 unsigned Register = GPRDecoderTable[RegNo];
866 Inst.addOperand(MCOperand::CreateReg(Register));
867 return MCDisassembler::Success;
871 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
872 uint64_t Address, const void *Decoder) {
873 DecodeStatus S = MCDisassembler::Success;
876 S = MCDisassembler::SoftFail;
878 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
883 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
884 uint64_t Address, const void *Decoder) {
886 return MCDisassembler::Fail;
887 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
890 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
891 uint64_t Address, const void *Decoder) {
892 unsigned Register = 0;
913 return MCDisassembler::Fail;
916 Inst.addOperand(MCOperand::CreateReg(Register));
917 return MCDisassembler::Success;
920 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
921 uint64_t Address, const void *Decoder) {
922 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
923 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
926 static const uint16_t SPRDecoderTable[] = {
927 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
928 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
929 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
930 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
931 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
932 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
933 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
934 ARM::S28, ARM::S29, ARM::S30, ARM::S31
937 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
938 uint64_t Address, const void *Decoder) {
940 return MCDisassembler::Fail;
942 unsigned Register = SPRDecoderTable[RegNo];
943 Inst.addOperand(MCOperand::CreateReg(Register));
944 return MCDisassembler::Success;
947 static const uint16_t DPRDecoderTable[] = {
948 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
949 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
950 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
951 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
952 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
953 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
954 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
955 ARM::D28, ARM::D29, ARM::D30, ARM::D31
958 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
959 uint64_t Address, const void *Decoder) {
961 return MCDisassembler::Fail;
963 unsigned Register = DPRDecoderTable[RegNo];
964 Inst.addOperand(MCOperand::CreateReg(Register));
965 return MCDisassembler::Success;
968 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
969 uint64_t Address, const void *Decoder) {
971 return MCDisassembler::Fail;
972 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
976 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
977 uint64_t Address, const void *Decoder) {
979 return MCDisassembler::Fail;
980 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
983 static const uint16_t QPRDecoderTable[] = {
984 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
985 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
986 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
987 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
991 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
992 uint64_t Address, const void *Decoder) {
994 return MCDisassembler::Fail;
997 unsigned Register = QPRDecoderTable[RegNo];
998 Inst.addOperand(MCOperand::CreateReg(Register));
999 return MCDisassembler::Success;
1002 static const uint16_t DPairDecoderTable[] = {
1003 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1004 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1005 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1006 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1007 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1011 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1012 uint64_t Address, const void *Decoder) {
1014 return MCDisassembler::Fail;
1016 unsigned Register = DPairDecoderTable[RegNo];
1017 Inst.addOperand(MCOperand::CreateReg(Register));
1018 return MCDisassembler::Success;
1021 static const uint16_t DPairSpacedDecoderTable[] = {
1022 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1023 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1024 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1025 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1026 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1027 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1028 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1029 ARM::D28_D30, ARM::D29_D31
1032 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1035 const void *Decoder) {
1037 return MCDisassembler::Fail;
1039 unsigned Register = DPairSpacedDecoderTable[RegNo];
1040 Inst.addOperand(MCOperand::CreateReg(Register));
1041 return MCDisassembler::Success;
1044 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1045 uint64_t Address, const void *Decoder) {
1046 if (Val == 0xF) return MCDisassembler::Fail;
1047 // AL predicate is not allowed on Thumb1 branches.
1048 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1049 return MCDisassembler::Fail;
1050 Inst.addOperand(MCOperand::CreateImm(Val));
1051 if (Val == ARMCC::AL) {
1052 Inst.addOperand(MCOperand::CreateReg(0));
1054 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1055 return MCDisassembler::Success;
1058 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1059 uint64_t Address, const void *Decoder) {
1061 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1063 Inst.addOperand(MCOperand::CreateReg(0));
1064 return MCDisassembler::Success;
1067 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1068 uint64_t Address, const void *Decoder) {
1069 uint32_t imm = Val & 0xFF;
1070 uint32_t rot = (Val & 0xF00) >> 7;
1071 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1072 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1073 return MCDisassembler::Success;
1076 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1077 uint64_t Address, const void *Decoder) {
1078 DecodeStatus S = MCDisassembler::Success;
1080 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1081 unsigned type = fieldFromInstruction32(Val, 5, 2);
1082 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1084 // Register-immediate
1085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1086 return MCDisassembler::Fail;
1088 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1091 Shift = ARM_AM::lsl;
1094 Shift = ARM_AM::lsr;
1097 Shift = ARM_AM::asr;
1100 Shift = ARM_AM::ror;
1104 if (Shift == ARM_AM::ror && imm == 0)
1105 Shift = ARM_AM::rrx;
1107 unsigned Op = Shift | (imm << 3);
1108 Inst.addOperand(MCOperand::CreateImm(Op));
1113 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1114 uint64_t Address, const void *Decoder) {
1115 DecodeStatus S = MCDisassembler::Success;
1117 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1118 unsigned type = fieldFromInstruction32(Val, 5, 2);
1119 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1121 // Register-register
1122 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1123 return MCDisassembler::Fail;
1124 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1125 return MCDisassembler::Fail;
1127 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1130 Shift = ARM_AM::lsl;
1133 Shift = ARM_AM::lsr;
1136 Shift = ARM_AM::asr;
1139 Shift = ARM_AM::ror;
1143 Inst.addOperand(MCOperand::CreateImm(Shift));
1148 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1149 uint64_t Address, const void *Decoder) {
1150 DecodeStatus S = MCDisassembler::Success;
1152 bool writebackLoad = false;
1153 unsigned writebackReg = 0;
1154 switch (Inst.getOpcode()) {
1157 case ARM::LDMIA_UPD:
1158 case ARM::LDMDB_UPD:
1159 case ARM::LDMIB_UPD:
1160 case ARM::LDMDA_UPD:
1161 case ARM::t2LDMIA_UPD:
1162 case ARM::t2LDMDB_UPD:
1163 writebackLoad = true;
1164 writebackReg = Inst.getOperand(0).getReg();
1168 // Empty register lists are not allowed.
1169 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
1170 for (unsigned i = 0; i < 16; ++i) {
1171 if (Val & (1 << i)) {
1172 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1173 return MCDisassembler::Fail;
1174 // Writeback not allowed if Rn is in the target list.
1175 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1176 Check(S, MCDisassembler::SoftFail);
1183 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1184 uint64_t Address, const void *Decoder) {
1185 DecodeStatus S = MCDisassembler::Success;
1187 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1188 unsigned regs = Val & 0xFF;
1190 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1191 return MCDisassembler::Fail;
1192 for (unsigned i = 0; i < (regs - 1); ++i) {
1193 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1194 return MCDisassembler::Fail;
1200 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1201 uint64_t Address, const void *Decoder) {
1202 DecodeStatus S = MCDisassembler::Success;
1204 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1205 unsigned regs = (Val & 0xFF) / 2;
1207 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1208 return MCDisassembler::Fail;
1209 for (unsigned i = 0; i < (regs - 1); ++i) {
1210 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1211 return MCDisassembler::Fail;
1217 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1218 uint64_t Address, const void *Decoder) {
1219 // This operand encodes a mask of contiguous zeros between a specified MSB
1220 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1221 // the mask of all bits LSB-and-lower, and then xor them to create
1222 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1223 // create the final mask.
1224 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1225 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
1227 DecodeStatus S = MCDisassembler::Success;
1228 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1230 uint32_t msb_mask = 0xFFFFFFFF;
1231 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1232 uint32_t lsb_mask = (1U << lsb) - 1;
1234 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1238 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1239 uint64_t Address, const void *Decoder) {
1240 DecodeStatus S = MCDisassembler::Success;
1242 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1243 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1244 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1245 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1246 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1247 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1249 switch (Inst.getOpcode()) {
1250 case ARM::LDC_OFFSET:
1253 case ARM::LDC_OPTION:
1254 case ARM::LDCL_OFFSET:
1256 case ARM::LDCL_POST:
1257 case ARM::LDCL_OPTION:
1258 case ARM::STC_OFFSET:
1261 case ARM::STC_OPTION:
1262 case ARM::STCL_OFFSET:
1264 case ARM::STCL_POST:
1265 case ARM::STCL_OPTION:
1266 case ARM::t2LDC_OFFSET:
1267 case ARM::t2LDC_PRE:
1268 case ARM::t2LDC_POST:
1269 case ARM::t2LDC_OPTION:
1270 case ARM::t2LDCL_OFFSET:
1271 case ARM::t2LDCL_PRE:
1272 case ARM::t2LDCL_POST:
1273 case ARM::t2LDCL_OPTION:
1274 case ARM::t2STC_OFFSET:
1275 case ARM::t2STC_PRE:
1276 case ARM::t2STC_POST:
1277 case ARM::t2STC_OPTION:
1278 case ARM::t2STCL_OFFSET:
1279 case ARM::t2STCL_PRE:
1280 case ARM::t2STCL_POST:
1281 case ARM::t2STCL_OPTION:
1282 if (coproc == 0xA || coproc == 0xB)
1283 return MCDisassembler::Fail;
1289 Inst.addOperand(MCOperand::CreateImm(coproc));
1290 Inst.addOperand(MCOperand::CreateImm(CRd));
1291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1292 return MCDisassembler::Fail;
1294 switch (Inst.getOpcode()) {
1295 case ARM::t2LDC2_OFFSET:
1296 case ARM::t2LDC2L_OFFSET:
1297 case ARM::t2LDC2_PRE:
1298 case ARM::t2LDC2L_PRE:
1299 case ARM::t2STC2_OFFSET:
1300 case ARM::t2STC2L_OFFSET:
1301 case ARM::t2STC2_PRE:
1302 case ARM::t2STC2L_PRE:
1303 case ARM::LDC2_OFFSET:
1304 case ARM::LDC2L_OFFSET:
1306 case ARM::LDC2L_PRE:
1307 case ARM::STC2_OFFSET:
1308 case ARM::STC2L_OFFSET:
1310 case ARM::STC2L_PRE:
1311 case ARM::t2LDC_OFFSET:
1312 case ARM::t2LDCL_OFFSET:
1313 case ARM::t2LDC_PRE:
1314 case ARM::t2LDCL_PRE:
1315 case ARM::t2STC_OFFSET:
1316 case ARM::t2STCL_OFFSET:
1317 case ARM::t2STC_PRE:
1318 case ARM::t2STCL_PRE:
1319 case ARM::LDC_OFFSET:
1320 case ARM::LDCL_OFFSET:
1323 case ARM::STC_OFFSET:
1324 case ARM::STCL_OFFSET:
1327 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1328 Inst.addOperand(MCOperand::CreateImm(imm));
1330 case ARM::t2LDC2_POST:
1331 case ARM::t2LDC2L_POST:
1332 case ARM::t2STC2_POST:
1333 case ARM::t2STC2L_POST:
1334 case ARM::LDC2_POST:
1335 case ARM::LDC2L_POST:
1336 case ARM::STC2_POST:
1337 case ARM::STC2L_POST:
1338 case ARM::t2LDC_POST:
1339 case ARM::t2LDCL_POST:
1340 case ARM::t2STC_POST:
1341 case ARM::t2STCL_POST:
1343 case ARM::LDCL_POST:
1345 case ARM::STCL_POST:
1349 // The 'option' variant doesn't encode 'U' in the immediate since
1350 // the immediate is unsigned [0,255].
1351 Inst.addOperand(MCOperand::CreateImm(imm));
1355 switch (Inst.getOpcode()) {
1356 case ARM::LDC_OFFSET:
1359 case ARM::LDC_OPTION:
1360 case ARM::LDCL_OFFSET:
1362 case ARM::LDCL_POST:
1363 case ARM::LDCL_OPTION:
1364 case ARM::STC_OFFSET:
1367 case ARM::STC_OPTION:
1368 case ARM::STCL_OFFSET:
1370 case ARM::STCL_POST:
1371 case ARM::STCL_OPTION:
1372 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1373 return MCDisassembler::Fail;
1383 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1384 uint64_t Address, const void *Decoder) {
1385 DecodeStatus S = MCDisassembler::Success;
1387 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1388 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1389 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1390 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1391 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1392 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1393 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1394 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1396 // On stores, the writeback operand precedes Rt.
1397 switch (Inst.getOpcode()) {
1398 case ARM::STR_POST_IMM:
1399 case ARM::STR_POST_REG:
1400 case ARM::STRB_POST_IMM:
1401 case ARM::STRB_POST_REG:
1402 case ARM::STRT_POST_REG:
1403 case ARM::STRT_POST_IMM:
1404 case ARM::STRBT_POST_REG:
1405 case ARM::STRBT_POST_IMM:
1406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1407 return MCDisassembler::Fail;
1413 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1414 return MCDisassembler::Fail;
1416 // On loads, the writeback operand comes after Rt.
1417 switch (Inst.getOpcode()) {
1418 case ARM::LDR_POST_IMM:
1419 case ARM::LDR_POST_REG:
1420 case ARM::LDRB_POST_IMM:
1421 case ARM::LDRB_POST_REG:
1422 case ARM::LDRBT_POST_REG:
1423 case ARM::LDRBT_POST_IMM:
1424 case ARM::LDRT_POST_REG:
1425 case ARM::LDRT_POST_IMM:
1426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1427 return MCDisassembler::Fail;
1433 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1434 return MCDisassembler::Fail;
1436 ARM_AM::AddrOpc Op = ARM_AM::add;
1437 if (!fieldFromInstruction32(Insn, 23, 1))
1440 bool writeback = (P == 0) || (W == 1);
1441 unsigned idx_mode = 0;
1443 idx_mode = ARMII::IndexModePre;
1444 else if (!P && writeback)
1445 idx_mode = ARMII::IndexModePost;
1447 if (writeback && (Rn == 15 || Rn == Rt))
1448 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1451 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1452 return MCDisassembler::Fail;
1453 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1454 switch( fieldFromInstruction32(Insn, 5, 2)) {
1468 return MCDisassembler::Fail;
1470 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1471 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1473 Inst.addOperand(MCOperand::CreateImm(imm));
1475 Inst.addOperand(MCOperand::CreateReg(0));
1476 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1477 Inst.addOperand(MCOperand::CreateImm(tmp));
1480 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1481 return MCDisassembler::Fail;
1486 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1487 uint64_t Address, const void *Decoder) {
1488 DecodeStatus S = MCDisassembler::Success;
1490 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1491 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1492 unsigned type = fieldFromInstruction32(Val, 5, 2);
1493 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1494 unsigned U = fieldFromInstruction32(Val, 12, 1);
1496 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1513 return MCDisassembler::Fail;
1514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1515 return MCDisassembler::Fail;
1518 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1520 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1521 Inst.addOperand(MCOperand::CreateImm(shift));
1527 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1528 uint64_t Address, const void *Decoder) {
1529 DecodeStatus S = MCDisassembler::Success;
1531 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1532 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1533 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1534 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1535 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1536 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1537 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1538 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1539 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1540 unsigned Rt2 = Rt + 1;
1542 bool writeback = (W == 1) | (P == 0);
1544 // For {LD,ST}RD, Rt must be even, else undefined.
1545 switch (Inst.getOpcode()) {
1548 case ARM::STRD_POST:
1551 case ARM::LDRD_POST:
1552 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1557 switch (Inst.getOpcode()) {
1560 case ARM::STRD_POST:
1561 if (P == 0 && W == 1)
1562 S = MCDisassembler::SoftFail;
1564 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1565 S = MCDisassembler::SoftFail;
1566 if (type && Rm == 15)
1567 S = MCDisassembler::SoftFail;
1569 S = MCDisassembler::SoftFail;
1570 if (!type && fieldFromInstruction32(Insn, 8, 4))
1571 S = MCDisassembler::SoftFail;
1575 case ARM::STRH_POST:
1577 S = MCDisassembler::SoftFail;
1578 if (writeback && (Rn == 15 || Rn == Rt))
1579 S = MCDisassembler::SoftFail;
1580 if (!type && Rm == 15)
1581 S = MCDisassembler::SoftFail;
1585 case ARM::LDRD_POST:
1586 if (type && Rn == 15){
1588 S = MCDisassembler::SoftFail;
1591 if (P == 0 && W == 1)
1592 S = MCDisassembler::SoftFail;
1593 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1594 S = MCDisassembler::SoftFail;
1595 if (!type && writeback && Rn == 15)
1596 S = MCDisassembler::SoftFail;
1597 if (writeback && (Rn == Rt || Rn == Rt2))
1598 S = MCDisassembler::SoftFail;
1602 case ARM::LDRH_POST:
1603 if (type && Rn == 15){
1605 S = MCDisassembler::SoftFail;
1609 S = MCDisassembler::SoftFail;
1610 if (!type && Rm == 15)
1611 S = MCDisassembler::SoftFail;
1612 if (!type && writeback && (Rn == 15 || Rn == Rt))
1613 S = MCDisassembler::SoftFail;
1616 case ARM::LDRSH_PRE:
1617 case ARM::LDRSH_POST:
1619 case ARM::LDRSB_PRE:
1620 case ARM::LDRSB_POST:
1621 if (type && Rn == 15){
1623 S = MCDisassembler::SoftFail;
1626 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1627 S = MCDisassembler::SoftFail;
1628 if (!type && (Rt == 15 || Rm == 15))
1629 S = MCDisassembler::SoftFail;
1630 if (!type && writeback && (Rn == 15 || Rn == Rt))
1631 S = MCDisassembler::SoftFail;
1637 if (writeback) { // Writeback
1639 U |= ARMII::IndexModePre << 9;
1641 U |= ARMII::IndexModePost << 9;
1643 // On stores, the writeback operand precedes Rt.
1644 switch (Inst.getOpcode()) {
1647 case ARM::STRD_POST:
1650 case ARM::STRH_POST:
1651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1652 return MCDisassembler::Fail;
1659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1660 return MCDisassembler::Fail;
1661 switch (Inst.getOpcode()) {
1664 case ARM::STRD_POST:
1667 case ARM::LDRD_POST:
1668 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1669 return MCDisassembler::Fail;
1676 // On loads, the writeback operand comes after Rt.
1677 switch (Inst.getOpcode()) {
1680 case ARM::LDRD_POST:
1683 case ARM::LDRH_POST:
1685 case ARM::LDRSH_PRE:
1686 case ARM::LDRSH_POST:
1688 case ARM::LDRSB_PRE:
1689 case ARM::LDRSB_POST:
1692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1693 return MCDisassembler::Fail;
1700 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1701 return MCDisassembler::Fail;
1704 Inst.addOperand(MCOperand::CreateReg(0));
1705 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1708 return MCDisassembler::Fail;
1709 Inst.addOperand(MCOperand::CreateImm(U));
1712 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1713 return MCDisassembler::Fail;
1718 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1719 uint64_t Address, const void *Decoder) {
1720 DecodeStatus S = MCDisassembler::Success;
1722 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1723 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1740 Inst.addOperand(MCOperand::CreateImm(mode));
1741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1742 return MCDisassembler::Fail;
1747 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1749 uint64_t Address, const void *Decoder) {
1750 DecodeStatus S = MCDisassembler::Success;
1752 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1753 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1754 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1757 switch (Inst.getOpcode()) {
1759 Inst.setOpcode(ARM::RFEDA);
1761 case ARM::LDMDA_UPD:
1762 Inst.setOpcode(ARM::RFEDA_UPD);
1765 Inst.setOpcode(ARM::RFEDB);
1767 case ARM::LDMDB_UPD:
1768 Inst.setOpcode(ARM::RFEDB_UPD);
1771 Inst.setOpcode(ARM::RFEIA);
1773 case ARM::LDMIA_UPD:
1774 Inst.setOpcode(ARM::RFEIA_UPD);
1777 Inst.setOpcode(ARM::RFEIB);
1779 case ARM::LDMIB_UPD:
1780 Inst.setOpcode(ARM::RFEIB_UPD);
1783 Inst.setOpcode(ARM::SRSDA);
1785 case ARM::STMDA_UPD:
1786 Inst.setOpcode(ARM::SRSDA_UPD);
1789 Inst.setOpcode(ARM::SRSDB);
1791 case ARM::STMDB_UPD:
1792 Inst.setOpcode(ARM::SRSDB_UPD);
1795 Inst.setOpcode(ARM::SRSIA);
1797 case ARM::STMIA_UPD:
1798 Inst.setOpcode(ARM::SRSIA_UPD);
1801 Inst.setOpcode(ARM::SRSIB);
1803 case ARM::STMIB_UPD:
1804 Inst.setOpcode(ARM::SRSIB_UPD);
1807 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
1810 // For stores (which become SRS's, the only operand is the mode.
1811 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1813 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1817 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1821 return MCDisassembler::Fail;
1822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1823 return MCDisassembler::Fail; // Tied
1824 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1825 return MCDisassembler::Fail;
1826 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1827 return MCDisassembler::Fail;
1832 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1833 uint64_t Address, const void *Decoder) {
1834 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1835 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1836 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1837 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1839 DecodeStatus S = MCDisassembler::Success;
1841 // imod == '01' --> UNPREDICTABLE
1842 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1843 // return failure here. The '01' imod value is unprintable, so there's
1844 // nothing useful we could do even if we returned UNPREDICTABLE.
1846 if (imod == 1) return MCDisassembler::Fail;
1849 Inst.setOpcode(ARM::CPS3p);
1850 Inst.addOperand(MCOperand::CreateImm(imod));
1851 Inst.addOperand(MCOperand::CreateImm(iflags));
1852 Inst.addOperand(MCOperand::CreateImm(mode));
1853 } else if (imod && !M) {
1854 Inst.setOpcode(ARM::CPS2p);
1855 Inst.addOperand(MCOperand::CreateImm(imod));
1856 Inst.addOperand(MCOperand::CreateImm(iflags));
1857 if (mode) S = MCDisassembler::SoftFail;
1858 } else if (!imod && M) {
1859 Inst.setOpcode(ARM::CPS1p);
1860 Inst.addOperand(MCOperand::CreateImm(mode));
1861 if (iflags) S = MCDisassembler::SoftFail;
1863 // imod == '00' && M == '0' --> UNPREDICTABLE
1864 Inst.setOpcode(ARM::CPS1p);
1865 Inst.addOperand(MCOperand::CreateImm(mode));
1866 S = MCDisassembler::SoftFail;
1872 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1873 uint64_t Address, const void *Decoder) {
1874 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1875 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1876 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1877 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1879 DecodeStatus S = MCDisassembler::Success;
1881 // imod == '01' --> UNPREDICTABLE
1882 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1883 // return failure here. The '01' imod value is unprintable, so there's
1884 // nothing useful we could do even if we returned UNPREDICTABLE.
1886 if (imod == 1) return MCDisassembler::Fail;
1889 Inst.setOpcode(ARM::t2CPS3p);
1890 Inst.addOperand(MCOperand::CreateImm(imod));
1891 Inst.addOperand(MCOperand::CreateImm(iflags));
1892 Inst.addOperand(MCOperand::CreateImm(mode));
1893 } else if (imod && !M) {
1894 Inst.setOpcode(ARM::t2CPS2p);
1895 Inst.addOperand(MCOperand::CreateImm(imod));
1896 Inst.addOperand(MCOperand::CreateImm(iflags));
1897 if (mode) S = MCDisassembler::SoftFail;
1898 } else if (!imod && M) {
1899 Inst.setOpcode(ARM::t2CPS1p);
1900 Inst.addOperand(MCOperand::CreateImm(mode));
1901 if (iflags) S = MCDisassembler::SoftFail;
1903 // imod == '00' && M == '0' --> UNPREDICTABLE
1904 Inst.setOpcode(ARM::t2CPS1p);
1905 Inst.addOperand(MCOperand::CreateImm(mode));
1906 S = MCDisassembler::SoftFail;
1912 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
1913 uint64_t Address, const void *Decoder) {
1914 DecodeStatus S = MCDisassembler::Success;
1916 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1919 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1920 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1921 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1922 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1924 if (Inst.getOpcode() == ARM::t2MOVTi16)
1925 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1926 return MCDisassembler::Fail;
1927 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1928 return MCDisassembler::Fail;
1930 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1931 Inst.addOperand(MCOperand::CreateImm(imm));
1936 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
1937 uint64_t Address, const void *Decoder) {
1938 DecodeStatus S = MCDisassembler::Success;
1940 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1941 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1944 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1945 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1947 if (Inst.getOpcode() == ARM::MOVTi16)
1948 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1949 return MCDisassembler::Fail;
1950 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1951 return MCDisassembler::Fail;
1953 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1954 Inst.addOperand(MCOperand::CreateImm(imm));
1956 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1957 return MCDisassembler::Fail;
1962 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
1963 uint64_t Address, const void *Decoder) {
1964 DecodeStatus S = MCDisassembler::Success;
1966 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1967 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1968 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1969 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1970 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1973 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1975 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1976 return MCDisassembler::Fail;
1977 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1978 return MCDisassembler::Fail;
1979 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1980 return MCDisassembler::Fail;
1981 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1982 return MCDisassembler::Fail;
1984 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1985 return MCDisassembler::Fail;
1990 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
1991 uint64_t Address, const void *Decoder) {
1992 DecodeStatus S = MCDisassembler::Success;
1994 unsigned add = fieldFromInstruction32(Val, 12, 1);
1995 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1996 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1998 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1999 return MCDisassembler::Fail;
2001 if (!add) imm *= -1;
2002 if (imm == 0 && !add) imm = INT32_MIN;
2003 Inst.addOperand(MCOperand::CreateImm(imm));
2005 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2010 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2011 uint64_t Address, const void *Decoder) {
2012 DecodeStatus S = MCDisassembler::Success;
2014 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2015 unsigned U = fieldFromInstruction32(Val, 8, 1);
2016 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2018 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2019 return MCDisassembler::Fail;
2022 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2024 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2029 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2030 uint64_t Address, const void *Decoder) {
2031 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2035 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2036 uint64_t Address, const void *Decoder) {
2037 DecodeStatus S = MCDisassembler::Success;
2038 unsigned imm = (fieldFromInstruction32(Insn, 0, 11) << 0) |
2039 (fieldFromInstruction32(Insn, 11, 1) << 18) |
2040 (fieldFromInstruction32(Insn, 13, 1) << 17) |
2041 (fieldFromInstruction32(Insn, 16, 6) << 11) |
2042 (fieldFromInstruction32(Insn, 26, 1) << 19);
2043 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
2044 true, 4, Inst, Decoder))
2045 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
2050 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2051 uint64_t Address, const void *Decoder) {
2052 DecodeStatus S = MCDisassembler::Success;
2054 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2055 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
2058 Inst.setOpcode(ARM::BLXi);
2059 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
2060 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2061 true, 4, Inst, Decoder))
2062 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2066 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2067 true, 4, Inst, Decoder))
2068 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2069 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2070 return MCDisassembler::Fail;
2076 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2077 uint64_t Address, const void *Decoder) {
2078 DecodeStatus S = MCDisassembler::Success;
2080 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
2081 unsigned align = fieldFromInstruction32(Val, 4, 2);
2083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2084 return MCDisassembler::Fail;
2086 Inst.addOperand(MCOperand::CreateImm(0));
2088 Inst.addOperand(MCOperand::CreateImm(4 << align));
2093 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2094 uint64_t Address, const void *Decoder) {
2095 DecodeStatus S = MCDisassembler::Success;
2097 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2098 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2099 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2100 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2101 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2102 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2104 // First output register
2105 switch (Inst.getOpcode()) {
2106 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2107 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2108 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2109 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2110 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2111 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2112 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2113 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2114 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2115 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2116 return MCDisassembler::Fail;
2121 case ARM::VLD2b16wb_fixed:
2122 case ARM::VLD2b16wb_register:
2123 case ARM::VLD2b32wb_fixed:
2124 case ARM::VLD2b32wb_register:
2125 case ARM::VLD2b8wb_fixed:
2126 case ARM::VLD2b8wb_register:
2127 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2128 return MCDisassembler::Fail;
2131 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2132 return MCDisassembler::Fail;
2135 // Second output register
2136 switch (Inst.getOpcode()) {
2140 case ARM::VLD3d8_UPD:
2141 case ARM::VLD3d16_UPD:
2142 case ARM::VLD3d32_UPD:
2146 case ARM::VLD4d8_UPD:
2147 case ARM::VLD4d16_UPD:
2148 case ARM::VLD4d32_UPD:
2149 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2150 return MCDisassembler::Fail;
2155 case ARM::VLD3q8_UPD:
2156 case ARM::VLD3q16_UPD:
2157 case ARM::VLD3q32_UPD:
2161 case ARM::VLD4q8_UPD:
2162 case ARM::VLD4q16_UPD:
2163 case ARM::VLD4q32_UPD:
2164 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2165 return MCDisassembler::Fail;
2170 // Third output register
2171 switch(Inst.getOpcode()) {
2175 case ARM::VLD3d8_UPD:
2176 case ARM::VLD3d16_UPD:
2177 case ARM::VLD3d32_UPD:
2181 case ARM::VLD4d8_UPD:
2182 case ARM::VLD4d16_UPD:
2183 case ARM::VLD4d32_UPD:
2184 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2185 return MCDisassembler::Fail;
2190 case ARM::VLD3q8_UPD:
2191 case ARM::VLD3q16_UPD:
2192 case ARM::VLD3q32_UPD:
2196 case ARM::VLD4q8_UPD:
2197 case ARM::VLD4q16_UPD:
2198 case ARM::VLD4q32_UPD:
2199 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2200 return MCDisassembler::Fail;
2206 // Fourth output register
2207 switch (Inst.getOpcode()) {
2211 case ARM::VLD4d8_UPD:
2212 case ARM::VLD4d16_UPD:
2213 case ARM::VLD4d32_UPD:
2214 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2215 return MCDisassembler::Fail;
2220 case ARM::VLD4q8_UPD:
2221 case ARM::VLD4q16_UPD:
2222 case ARM::VLD4q32_UPD:
2223 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2224 return MCDisassembler::Fail;
2230 // Writeback operand
2231 switch (Inst.getOpcode()) {
2232 case ARM::VLD1d8wb_fixed:
2233 case ARM::VLD1d16wb_fixed:
2234 case ARM::VLD1d32wb_fixed:
2235 case ARM::VLD1d64wb_fixed:
2236 case ARM::VLD1d8wb_register:
2237 case ARM::VLD1d16wb_register:
2238 case ARM::VLD1d32wb_register:
2239 case ARM::VLD1d64wb_register:
2240 case ARM::VLD1q8wb_fixed:
2241 case ARM::VLD1q16wb_fixed:
2242 case ARM::VLD1q32wb_fixed:
2243 case ARM::VLD1q64wb_fixed:
2244 case ARM::VLD1q8wb_register:
2245 case ARM::VLD1q16wb_register:
2246 case ARM::VLD1q32wb_register:
2247 case ARM::VLD1q64wb_register:
2248 case ARM::VLD1d8Twb_fixed:
2249 case ARM::VLD1d8Twb_register:
2250 case ARM::VLD1d16Twb_fixed:
2251 case ARM::VLD1d16Twb_register:
2252 case ARM::VLD1d32Twb_fixed:
2253 case ARM::VLD1d32Twb_register:
2254 case ARM::VLD1d64Twb_fixed:
2255 case ARM::VLD1d64Twb_register:
2256 case ARM::VLD1d8Qwb_fixed:
2257 case ARM::VLD1d8Qwb_register:
2258 case ARM::VLD1d16Qwb_fixed:
2259 case ARM::VLD1d16Qwb_register:
2260 case ARM::VLD1d32Qwb_fixed:
2261 case ARM::VLD1d32Qwb_register:
2262 case ARM::VLD1d64Qwb_fixed:
2263 case ARM::VLD1d64Qwb_register:
2264 case ARM::VLD2d8wb_fixed:
2265 case ARM::VLD2d16wb_fixed:
2266 case ARM::VLD2d32wb_fixed:
2267 case ARM::VLD2q8wb_fixed:
2268 case ARM::VLD2q16wb_fixed:
2269 case ARM::VLD2q32wb_fixed:
2270 case ARM::VLD2d8wb_register:
2271 case ARM::VLD2d16wb_register:
2272 case ARM::VLD2d32wb_register:
2273 case ARM::VLD2q8wb_register:
2274 case ARM::VLD2q16wb_register:
2275 case ARM::VLD2q32wb_register:
2276 case ARM::VLD2b8wb_fixed:
2277 case ARM::VLD2b16wb_fixed:
2278 case ARM::VLD2b32wb_fixed:
2279 case ARM::VLD2b8wb_register:
2280 case ARM::VLD2b16wb_register:
2281 case ARM::VLD2b32wb_register:
2282 Inst.addOperand(MCOperand::CreateImm(0));
2284 case ARM::VLD3d8_UPD:
2285 case ARM::VLD3d16_UPD:
2286 case ARM::VLD3d32_UPD:
2287 case ARM::VLD3q8_UPD:
2288 case ARM::VLD3q16_UPD:
2289 case ARM::VLD3q32_UPD:
2290 case ARM::VLD4d8_UPD:
2291 case ARM::VLD4d16_UPD:
2292 case ARM::VLD4d32_UPD:
2293 case ARM::VLD4q8_UPD:
2294 case ARM::VLD4q16_UPD:
2295 case ARM::VLD4q32_UPD:
2296 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2297 return MCDisassembler::Fail;
2303 // AddrMode6 Base (register+alignment)
2304 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2305 return MCDisassembler::Fail;
2307 // AddrMode6 Offset (register)
2308 switch (Inst.getOpcode()) {
2310 // The below have been updated to have explicit am6offset split
2311 // between fixed and register offset. For those instructions not
2312 // yet updated, we need to add an additional reg0 operand for the
2315 // The fixed offset encodes as Rm == 0xd, so we check for that.
2317 Inst.addOperand(MCOperand::CreateReg(0));
2320 // Fall through to handle the register offset variant.
2321 case ARM::VLD1d8wb_fixed:
2322 case ARM::VLD1d16wb_fixed:
2323 case ARM::VLD1d32wb_fixed:
2324 case ARM::VLD1d64wb_fixed:
2325 case ARM::VLD1d8Twb_fixed:
2326 case ARM::VLD1d16Twb_fixed:
2327 case ARM::VLD1d32Twb_fixed:
2328 case ARM::VLD1d64Twb_fixed:
2329 case ARM::VLD1d8Qwb_fixed:
2330 case ARM::VLD1d16Qwb_fixed:
2331 case ARM::VLD1d32Qwb_fixed:
2332 case ARM::VLD1d64Qwb_fixed:
2333 case ARM::VLD1d8wb_register:
2334 case ARM::VLD1d16wb_register:
2335 case ARM::VLD1d32wb_register:
2336 case ARM::VLD1d64wb_register:
2337 case ARM::VLD1q8wb_fixed:
2338 case ARM::VLD1q16wb_fixed:
2339 case ARM::VLD1q32wb_fixed:
2340 case ARM::VLD1q64wb_fixed:
2341 case ARM::VLD1q8wb_register:
2342 case ARM::VLD1q16wb_register:
2343 case ARM::VLD1q32wb_register:
2344 case ARM::VLD1q64wb_register:
2345 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2346 // variant encodes Rm == 0xf. Anything else is a register offset post-
2347 // increment and we need to add the register operand to the instruction.
2348 if (Rm != 0xD && Rm != 0xF &&
2349 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2350 return MCDisassembler::Fail;
2352 case ARM::VLD2d8wb_fixed:
2353 case ARM::VLD2d16wb_fixed:
2354 case ARM::VLD2d32wb_fixed:
2355 case ARM::VLD2b8wb_fixed:
2356 case ARM::VLD2b16wb_fixed:
2357 case ARM::VLD2b32wb_fixed:
2358 case ARM::VLD2q8wb_fixed:
2359 case ARM::VLD2q16wb_fixed:
2360 case ARM::VLD2q32wb_fixed:
2367 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2368 uint64_t Address, const void *Decoder) {
2369 DecodeStatus S = MCDisassembler::Success;
2371 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2372 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2373 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2374 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2375 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2376 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2378 // Writeback Operand
2379 switch (Inst.getOpcode()) {
2380 case ARM::VST1d8wb_fixed:
2381 case ARM::VST1d16wb_fixed:
2382 case ARM::VST1d32wb_fixed:
2383 case ARM::VST1d64wb_fixed:
2384 case ARM::VST1d8wb_register:
2385 case ARM::VST1d16wb_register:
2386 case ARM::VST1d32wb_register:
2387 case ARM::VST1d64wb_register:
2388 case ARM::VST1q8wb_fixed:
2389 case ARM::VST1q16wb_fixed:
2390 case ARM::VST1q32wb_fixed:
2391 case ARM::VST1q64wb_fixed:
2392 case ARM::VST1q8wb_register:
2393 case ARM::VST1q16wb_register:
2394 case ARM::VST1q32wb_register:
2395 case ARM::VST1q64wb_register:
2396 case ARM::VST1d8Twb_fixed:
2397 case ARM::VST1d16Twb_fixed:
2398 case ARM::VST1d32Twb_fixed:
2399 case ARM::VST1d64Twb_fixed:
2400 case ARM::VST1d8Twb_register:
2401 case ARM::VST1d16Twb_register:
2402 case ARM::VST1d32Twb_register:
2403 case ARM::VST1d64Twb_register:
2404 case ARM::VST1d8Qwb_fixed:
2405 case ARM::VST1d16Qwb_fixed:
2406 case ARM::VST1d32Qwb_fixed:
2407 case ARM::VST1d64Qwb_fixed:
2408 case ARM::VST1d8Qwb_register:
2409 case ARM::VST1d16Qwb_register:
2410 case ARM::VST1d32Qwb_register:
2411 case ARM::VST1d64Qwb_register:
2412 case ARM::VST2d8wb_fixed:
2413 case ARM::VST2d16wb_fixed:
2414 case ARM::VST2d32wb_fixed:
2415 case ARM::VST2d8wb_register:
2416 case ARM::VST2d16wb_register:
2417 case ARM::VST2d32wb_register:
2418 case ARM::VST2q8wb_fixed:
2419 case ARM::VST2q16wb_fixed:
2420 case ARM::VST2q32wb_fixed:
2421 case ARM::VST2q8wb_register:
2422 case ARM::VST2q16wb_register:
2423 case ARM::VST2q32wb_register:
2424 case ARM::VST2b8wb_fixed:
2425 case ARM::VST2b16wb_fixed:
2426 case ARM::VST2b32wb_fixed:
2427 case ARM::VST2b8wb_register:
2428 case ARM::VST2b16wb_register:
2429 case ARM::VST2b32wb_register:
2431 return MCDisassembler::Fail;
2432 Inst.addOperand(MCOperand::CreateImm(0));
2434 case ARM::VST3d8_UPD:
2435 case ARM::VST3d16_UPD:
2436 case ARM::VST3d32_UPD:
2437 case ARM::VST3q8_UPD:
2438 case ARM::VST3q16_UPD:
2439 case ARM::VST3q32_UPD:
2440 case ARM::VST4d8_UPD:
2441 case ARM::VST4d16_UPD:
2442 case ARM::VST4d32_UPD:
2443 case ARM::VST4q8_UPD:
2444 case ARM::VST4q16_UPD:
2445 case ARM::VST4q32_UPD:
2446 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2447 return MCDisassembler::Fail;
2453 // AddrMode6 Base (register+alignment)
2454 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2455 return MCDisassembler::Fail;
2457 // AddrMode6 Offset (register)
2458 switch (Inst.getOpcode()) {
2461 Inst.addOperand(MCOperand::CreateReg(0));
2462 else if (Rm != 0xF) {
2463 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2464 return MCDisassembler::Fail;
2467 case ARM::VST1d8wb_fixed:
2468 case ARM::VST1d16wb_fixed:
2469 case ARM::VST1d32wb_fixed:
2470 case ARM::VST1d64wb_fixed:
2471 case ARM::VST1q8wb_fixed:
2472 case ARM::VST1q16wb_fixed:
2473 case ARM::VST1q32wb_fixed:
2474 case ARM::VST1q64wb_fixed:
2475 case ARM::VST1d8Twb_fixed:
2476 case ARM::VST1d16Twb_fixed:
2477 case ARM::VST1d32Twb_fixed:
2478 case ARM::VST1d64Twb_fixed:
2479 case ARM::VST1d8Qwb_fixed:
2480 case ARM::VST1d16Qwb_fixed:
2481 case ARM::VST1d32Qwb_fixed:
2482 case ARM::VST1d64Qwb_fixed:
2483 case ARM::VST2d8wb_fixed:
2484 case ARM::VST2d16wb_fixed:
2485 case ARM::VST2d32wb_fixed:
2486 case ARM::VST2q8wb_fixed:
2487 case ARM::VST2q16wb_fixed:
2488 case ARM::VST2q32wb_fixed:
2489 case ARM::VST2b8wb_fixed:
2490 case ARM::VST2b16wb_fixed:
2491 case ARM::VST2b32wb_fixed:
2496 // First input register
2497 switch (Inst.getOpcode()) {
2502 case ARM::VST1q16wb_fixed:
2503 case ARM::VST1q16wb_register:
2504 case ARM::VST1q32wb_fixed:
2505 case ARM::VST1q32wb_register:
2506 case ARM::VST1q64wb_fixed:
2507 case ARM::VST1q64wb_register:
2508 case ARM::VST1q8wb_fixed:
2509 case ARM::VST1q8wb_register:
2513 case ARM::VST2d16wb_fixed:
2514 case ARM::VST2d16wb_register:
2515 case ARM::VST2d32wb_fixed:
2516 case ARM::VST2d32wb_register:
2517 case ARM::VST2d8wb_fixed:
2518 case ARM::VST2d8wb_register:
2519 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2520 return MCDisassembler::Fail;
2525 case ARM::VST2b16wb_fixed:
2526 case ARM::VST2b16wb_register:
2527 case ARM::VST2b32wb_fixed:
2528 case ARM::VST2b32wb_register:
2529 case ARM::VST2b8wb_fixed:
2530 case ARM::VST2b8wb_register:
2531 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2532 return MCDisassembler::Fail;
2535 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2536 return MCDisassembler::Fail;
2539 // Second input register
2540 switch (Inst.getOpcode()) {
2544 case ARM::VST3d8_UPD:
2545 case ARM::VST3d16_UPD:
2546 case ARM::VST3d32_UPD:
2550 case ARM::VST4d8_UPD:
2551 case ARM::VST4d16_UPD:
2552 case ARM::VST4d32_UPD:
2553 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2554 return MCDisassembler::Fail;
2559 case ARM::VST3q8_UPD:
2560 case ARM::VST3q16_UPD:
2561 case ARM::VST3q32_UPD:
2565 case ARM::VST4q8_UPD:
2566 case ARM::VST4q16_UPD:
2567 case ARM::VST4q32_UPD:
2568 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2569 return MCDisassembler::Fail;
2575 // Third input register
2576 switch (Inst.getOpcode()) {
2580 case ARM::VST3d8_UPD:
2581 case ARM::VST3d16_UPD:
2582 case ARM::VST3d32_UPD:
2586 case ARM::VST4d8_UPD:
2587 case ARM::VST4d16_UPD:
2588 case ARM::VST4d32_UPD:
2589 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2590 return MCDisassembler::Fail;
2595 case ARM::VST3q8_UPD:
2596 case ARM::VST3q16_UPD:
2597 case ARM::VST3q32_UPD:
2601 case ARM::VST4q8_UPD:
2602 case ARM::VST4q16_UPD:
2603 case ARM::VST4q32_UPD:
2604 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2605 return MCDisassembler::Fail;
2611 // Fourth input register
2612 switch (Inst.getOpcode()) {
2616 case ARM::VST4d8_UPD:
2617 case ARM::VST4d16_UPD:
2618 case ARM::VST4d32_UPD:
2619 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2620 return MCDisassembler::Fail;
2625 case ARM::VST4q8_UPD:
2626 case ARM::VST4q16_UPD:
2627 case ARM::VST4q32_UPD:
2628 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2629 return MCDisassembler::Fail;
2638 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2639 uint64_t Address, const void *Decoder) {
2640 DecodeStatus S = MCDisassembler::Success;
2642 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2643 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2644 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2645 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2646 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2647 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2649 align *= (1 << size);
2651 switch (Inst.getOpcode()) {
2652 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2653 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2654 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2655 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2656 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2657 return MCDisassembler::Fail;
2660 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2661 return MCDisassembler::Fail;
2665 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2666 return MCDisassembler::Fail;
2669 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2670 return MCDisassembler::Fail;
2671 Inst.addOperand(MCOperand::CreateImm(align));
2673 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2674 // variant encodes Rm == 0xf. Anything else is a register offset post-
2675 // increment and we need to add the register operand to the instruction.
2676 if (Rm != 0xD && Rm != 0xF &&
2677 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2678 return MCDisassembler::Fail;
2683 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2684 uint64_t Address, const void *Decoder) {
2685 DecodeStatus S = MCDisassembler::Success;
2687 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2688 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2689 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2690 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2691 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2692 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2695 switch (Inst.getOpcode()) {
2696 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2697 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2698 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2699 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2700 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2701 return MCDisassembler::Fail;
2703 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2704 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2705 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2706 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2707 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2708 return MCDisassembler::Fail;
2711 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2712 return MCDisassembler::Fail;
2717 Inst.addOperand(MCOperand::CreateImm(0));
2719 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2720 return MCDisassembler::Fail;
2721 Inst.addOperand(MCOperand::CreateImm(align));
2723 if (Rm != 0xD && Rm != 0xF) {
2724 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2725 return MCDisassembler::Fail;
2731 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2732 uint64_t Address, const void *Decoder) {
2733 DecodeStatus S = MCDisassembler::Success;
2735 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2736 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2737 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2738 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2739 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2741 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2742 return MCDisassembler::Fail;
2743 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2744 return MCDisassembler::Fail;
2745 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2746 return MCDisassembler::Fail;
2748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2749 return MCDisassembler::Fail;
2752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2753 return MCDisassembler::Fail;
2754 Inst.addOperand(MCOperand::CreateImm(0));
2757 Inst.addOperand(MCOperand::CreateReg(0));
2758 else if (Rm != 0xF) {
2759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2760 return MCDisassembler::Fail;
2766 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2767 uint64_t Address, const void *Decoder) {
2768 DecodeStatus S = MCDisassembler::Success;
2770 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2771 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2772 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2773 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2774 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2775 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2776 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2791 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2792 return MCDisassembler::Fail;
2793 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2794 return MCDisassembler::Fail;
2795 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2796 return MCDisassembler::Fail;
2797 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2798 return MCDisassembler::Fail;
2800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2801 return MCDisassembler::Fail;
2804 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2805 return MCDisassembler::Fail;
2806 Inst.addOperand(MCOperand::CreateImm(align));
2809 Inst.addOperand(MCOperand::CreateReg(0));
2810 else if (Rm != 0xF) {
2811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2812 return MCDisassembler::Fail;
2819 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
2820 uint64_t Address, const void *Decoder) {
2821 DecodeStatus S = MCDisassembler::Success;
2823 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2824 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2825 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2826 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2827 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2828 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2829 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2830 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2833 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2834 return MCDisassembler::Fail;
2836 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2837 return MCDisassembler::Fail;
2840 Inst.addOperand(MCOperand::CreateImm(imm));
2842 switch (Inst.getOpcode()) {
2843 case ARM::VORRiv4i16:
2844 case ARM::VORRiv2i32:
2845 case ARM::VBICiv4i16:
2846 case ARM::VBICiv2i32:
2847 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2848 return MCDisassembler::Fail;
2850 case ARM::VORRiv8i16:
2851 case ARM::VORRiv4i32:
2852 case ARM::VBICiv8i16:
2853 case ARM::VBICiv4i32:
2854 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2855 return MCDisassembler::Fail;
2864 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
2865 uint64_t Address, const void *Decoder) {
2866 DecodeStatus S = MCDisassembler::Success;
2868 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2869 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2870 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2871 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2872 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2874 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2875 return MCDisassembler::Fail;
2876 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2877 return MCDisassembler::Fail;
2878 Inst.addOperand(MCOperand::CreateImm(8 << size));
2883 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
2884 uint64_t Address, const void *Decoder) {
2885 Inst.addOperand(MCOperand::CreateImm(8 - Val));
2886 return MCDisassembler::Success;
2889 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
2890 uint64_t Address, const void *Decoder) {
2891 Inst.addOperand(MCOperand::CreateImm(16 - Val));
2892 return MCDisassembler::Success;
2895 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
2896 uint64_t Address, const void *Decoder) {
2897 Inst.addOperand(MCOperand::CreateImm(32 - Val));
2898 return MCDisassembler::Success;
2901 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
2902 uint64_t Address, const void *Decoder) {
2903 Inst.addOperand(MCOperand::CreateImm(64 - Val));
2904 return MCDisassembler::Success;
2907 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
2908 uint64_t Address, const void *Decoder) {
2909 DecodeStatus S = MCDisassembler::Success;
2911 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2912 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2913 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2914 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2915 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2916 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2917 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2920 return MCDisassembler::Fail;
2922 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2923 return MCDisassembler::Fail; // Writeback
2926 switch (Inst.getOpcode()) {
2929 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2930 return MCDisassembler::Fail;
2933 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2934 return MCDisassembler::Fail;
2937 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2938 return MCDisassembler::Fail;
2943 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
2944 uint64_t Address, const void *Decoder) {
2945 DecodeStatus S = MCDisassembler::Success;
2947 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2948 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2950 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2951 return MCDisassembler::Fail;
2953 switch(Inst.getOpcode()) {
2955 return MCDisassembler::Fail;
2957 break; // tADR does not explicitly represent the PC as an operand.
2959 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2963 Inst.addOperand(MCOperand::CreateImm(imm));
2967 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
2968 uint64_t Address, const void *Decoder) {
2969 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
2970 true, 2, Inst, Decoder))
2971 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
2972 return MCDisassembler::Success;
2975 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
2976 uint64_t Address, const void *Decoder) {
2977 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
2978 true, 4, Inst, Decoder))
2979 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
2980 return MCDisassembler::Success;
2983 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
2984 uint64_t Address, const void *Decoder) {
2985 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4,
2986 true, 2, Inst, Decoder))
2987 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
2988 return MCDisassembler::Success;
2991 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
2992 uint64_t Address, const void *Decoder) {
2993 DecodeStatus S = MCDisassembler::Success;
2995 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2996 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2998 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2999 return MCDisassembler::Fail;
3000 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3001 return MCDisassembler::Fail;
3006 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3007 uint64_t Address, const void *Decoder) {
3008 DecodeStatus S = MCDisassembler::Success;
3010 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
3011 unsigned imm = fieldFromInstruction32(Val, 3, 5);
3013 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3014 return MCDisassembler::Fail;
3015 Inst.addOperand(MCOperand::CreateImm(imm));
3020 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3021 uint64_t Address, const void *Decoder) {
3022 unsigned imm = Val << 2;
3024 Inst.addOperand(MCOperand::CreateImm(imm));
3025 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3027 return MCDisassembler::Success;
3030 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3031 uint64_t Address, const void *Decoder) {
3032 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3033 Inst.addOperand(MCOperand::CreateImm(Val));
3035 return MCDisassembler::Success;
3038 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3039 uint64_t Address, const void *Decoder) {
3040 DecodeStatus S = MCDisassembler::Success;
3042 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
3043 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
3044 unsigned imm = fieldFromInstruction32(Val, 0, 2);
3046 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3047 return MCDisassembler::Fail;
3048 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3049 return MCDisassembler::Fail;
3050 Inst.addOperand(MCOperand::CreateImm(imm));
3055 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3056 uint64_t Address, const void *Decoder) {
3057 DecodeStatus S = MCDisassembler::Success;
3059 switch (Inst.getOpcode()) {
3065 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3066 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3067 return MCDisassembler::Fail;
3071 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3073 switch (Inst.getOpcode()) {
3075 Inst.setOpcode(ARM::t2LDRBpci);
3078 Inst.setOpcode(ARM::t2LDRHpci);
3081 Inst.setOpcode(ARM::t2LDRSHpci);
3084 Inst.setOpcode(ARM::t2LDRSBpci);
3087 Inst.setOpcode(ARM::t2PLDi12);
3088 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3091 return MCDisassembler::Fail;
3094 int imm = fieldFromInstruction32(Insn, 0, 12);
3095 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
3096 Inst.addOperand(MCOperand::CreateImm(imm));
3101 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
3102 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
3103 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
3104 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3105 return MCDisassembler::Fail;
3110 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3111 uint64_t Address, const void *Decoder) {
3112 int imm = Val & 0xFF;
3113 if (!(Val & 0x100)) imm *= -1;
3114 Inst.addOperand(MCOperand::CreateImm(imm << 2));
3116 return MCDisassembler::Success;
3119 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3120 uint64_t Address, const void *Decoder) {
3121 DecodeStatus S = MCDisassembler::Success;
3123 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3124 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3126 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3127 return MCDisassembler::Fail;
3128 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3129 return MCDisassembler::Fail;
3134 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3135 uint64_t Address, const void *Decoder) {
3136 DecodeStatus S = MCDisassembler::Success;
3138 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
3139 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3141 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3142 return MCDisassembler::Fail;
3144 Inst.addOperand(MCOperand::CreateImm(imm));
3149 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3150 uint64_t Address, const void *Decoder) {
3151 int imm = Val & 0xFF;
3154 else if (!(Val & 0x100))
3156 Inst.addOperand(MCOperand::CreateImm(imm));
3158 return MCDisassembler::Success;
3162 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3163 uint64_t Address, const void *Decoder) {
3164 DecodeStatus S = MCDisassembler::Success;
3166 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3167 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3169 // Some instructions always use an additive offset.
3170 switch (Inst.getOpcode()) {
3185 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3186 return MCDisassembler::Fail;
3187 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3188 return MCDisassembler::Fail;
3193 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3194 uint64_t Address, const void *Decoder) {
3195 DecodeStatus S = MCDisassembler::Success;
3197 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3198 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3199 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3200 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
3202 unsigned load = fieldFromInstruction32(Insn, 20, 1);
3205 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3206 return MCDisassembler::Fail;
3209 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3210 return MCDisassembler::Fail;
3213 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3214 return MCDisassembler::Fail;
3217 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3218 return MCDisassembler::Fail;
3223 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3224 uint64_t Address, const void *Decoder) {
3225 DecodeStatus S = MCDisassembler::Success;
3227 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3228 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3231 return MCDisassembler::Fail;
3232 Inst.addOperand(MCOperand::CreateImm(imm));
3238 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3239 uint64_t Address, const void *Decoder) {
3240 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3242 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3243 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3244 Inst.addOperand(MCOperand::CreateImm(imm));
3246 return MCDisassembler::Success;
3249 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3250 uint64_t Address, const void *Decoder) {
3251 DecodeStatus S = MCDisassembler::Success;
3253 if (Inst.getOpcode() == ARM::tADDrSP) {
3254 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3255 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3257 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3258 return MCDisassembler::Fail;
3259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3260 return MCDisassembler::Fail;
3261 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3262 } else if (Inst.getOpcode() == ARM::tADDspr) {
3263 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3265 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3266 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3268 return MCDisassembler::Fail;
3274 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3275 uint64_t Address, const void *Decoder) {
3276 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3277 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3279 Inst.addOperand(MCOperand::CreateImm(imod));
3280 Inst.addOperand(MCOperand::CreateImm(flags));
3282 return MCDisassembler::Success;
3285 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3286 uint64_t Address, const void *Decoder) {
3287 DecodeStatus S = MCDisassembler::Success;
3288 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3289 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3291 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3292 return MCDisassembler::Fail;
3293 Inst.addOperand(MCOperand::CreateImm(add));
3298 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3299 uint64_t Address, const void *Decoder) {
3300 if (!tryAddingSymbolicOperand(Address,
3301 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3302 true, 4, Inst, Decoder))
3303 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3304 return MCDisassembler::Success;
3307 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3308 uint64_t Address, const void *Decoder) {
3309 if (Val == 0xA || Val == 0xB)
3310 return MCDisassembler::Fail;
3312 Inst.addOperand(MCOperand::CreateImm(Val));
3313 return MCDisassembler::Success;
3317 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3318 uint64_t Address, const void *Decoder) {
3319 DecodeStatus S = MCDisassembler::Success;
3321 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3322 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3324 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3326 return MCDisassembler::Fail;
3327 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3328 return MCDisassembler::Fail;
3333 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3334 uint64_t Address, const void *Decoder) {
3335 DecodeStatus S = MCDisassembler::Success;
3337 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3338 if (pred == 0xE || pred == 0xF) {
3339 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
3342 return MCDisassembler::Fail;
3344 Inst.setOpcode(ARM::t2DSB);
3347 Inst.setOpcode(ARM::t2DMB);
3350 Inst.setOpcode(ARM::t2ISB);
3354 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
3355 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3358 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3359 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3360 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3361 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3362 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3364 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3365 return MCDisassembler::Fail;
3366 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3367 return MCDisassembler::Fail;
3372 // Decode a shifted immediate operand. These basically consist
3373 // of an 8-bit value, and a 4-bit directive that specifies either
3374 // a splat operation or a rotation.
3375 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3376 uint64_t Address, const void *Decoder) {
3377 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3379 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3380 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3383 Inst.addOperand(MCOperand::CreateImm(imm));
3386 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3389 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3392 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3397 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3398 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3399 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3400 Inst.addOperand(MCOperand::CreateImm(imm));
3403 return MCDisassembler::Success;
3407 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3408 uint64_t Address, const void *Decoder){
3409 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<8>(Val<<1) + 4,
3410 true, 2, Inst, Decoder))
3411 Inst.addOperand(MCOperand::CreateImm(SignExtend32<8>(Val << 1)));
3412 return MCDisassembler::Success;
3415 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3416 uint64_t Address, const void *Decoder){
3417 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
3418 true, 4, Inst, Decoder))
3419 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3420 return MCDisassembler::Success;
3423 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3424 uint64_t Address, const void *Decoder) {
3427 return MCDisassembler::Fail;
3439 Inst.addOperand(MCOperand::CreateImm(Val));
3440 return MCDisassembler::Success;
3443 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
3444 uint64_t Address, const void *Decoder) {
3445 if (!Val) return MCDisassembler::Fail;
3446 Inst.addOperand(MCOperand::CreateImm(Val));
3447 return MCDisassembler::Success;
3450 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
3451 uint64_t Address, const void *Decoder) {
3452 DecodeStatus S = MCDisassembler::Success;
3454 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3455 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3456 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3458 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3460 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3461 return MCDisassembler::Fail;
3462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3463 return MCDisassembler::Fail;
3464 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3465 return MCDisassembler::Fail;
3466 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3467 return MCDisassembler::Fail;
3473 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
3474 uint64_t Address, const void *Decoder){
3475 DecodeStatus S = MCDisassembler::Success;
3477 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3478 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3479 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3480 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3482 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3483 return MCDisassembler::Fail;
3485 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3486 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
3488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3489 return MCDisassembler::Fail;
3490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3491 return MCDisassembler::Fail;
3492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3493 return MCDisassembler::Fail;
3494 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3495 return MCDisassembler::Fail;
3500 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
3501 uint64_t Address, const void *Decoder) {
3502 DecodeStatus S = MCDisassembler::Success;
3504 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3505 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3506 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3507 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3508 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3509 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3511 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3514 return MCDisassembler::Fail;
3515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3516 return MCDisassembler::Fail;
3517 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3518 return MCDisassembler::Fail;
3519 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3520 return MCDisassembler::Fail;
3525 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
3526 uint64_t Address, const void *Decoder) {
3527 DecodeStatus S = MCDisassembler::Success;
3529 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3530 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3531 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3532 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3533 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3534 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3535 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3537 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3538 if (Rm == 0xF) S = MCDisassembler::SoftFail;
3540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3541 return MCDisassembler::Fail;
3542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3543 return MCDisassembler::Fail;
3544 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3545 return MCDisassembler::Fail;
3546 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3547 return MCDisassembler::Fail;
3553 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
3554 uint64_t Address, const void *Decoder) {
3555 DecodeStatus S = MCDisassembler::Success;
3557 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3558 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3559 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3560 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3561 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3562 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3564 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3566 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3567 return MCDisassembler::Fail;
3568 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3569 return MCDisassembler::Fail;
3570 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3571 return MCDisassembler::Fail;
3572 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3573 return MCDisassembler::Fail;
3578 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
3579 uint64_t Address, const void *Decoder) {
3580 DecodeStatus S = MCDisassembler::Success;
3582 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3583 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3584 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3585 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3586 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3587 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3589 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3592 return MCDisassembler::Fail;
3593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3594 return MCDisassembler::Fail;
3595 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3596 return MCDisassembler::Fail;
3597 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3598 return MCDisassembler::Fail;
3603 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
3604 uint64_t Address, const void *Decoder) {
3605 DecodeStatus S = MCDisassembler::Success;
3607 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3608 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3609 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3610 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3611 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3617 return MCDisassembler::Fail;
3619 if (fieldFromInstruction32(Insn, 4, 1))
3620 return MCDisassembler::Fail; // UNDEFINED
3621 index = fieldFromInstruction32(Insn, 5, 3);
3624 if (fieldFromInstruction32(Insn, 5, 1))
3625 return MCDisassembler::Fail; // UNDEFINED
3626 index = fieldFromInstruction32(Insn, 6, 2);
3627 if (fieldFromInstruction32(Insn, 4, 1))
3631 if (fieldFromInstruction32(Insn, 6, 1))
3632 return MCDisassembler::Fail; // UNDEFINED
3633 index = fieldFromInstruction32(Insn, 7, 1);
3634 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3638 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3639 return MCDisassembler::Fail;
3640 if (Rm != 0xF) { // Writeback
3641 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3642 return MCDisassembler::Fail;
3644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3645 return MCDisassembler::Fail;
3646 Inst.addOperand(MCOperand::CreateImm(align));
3649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3650 return MCDisassembler::Fail;
3652 Inst.addOperand(MCOperand::CreateReg(0));
3655 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3656 return MCDisassembler::Fail;
3657 Inst.addOperand(MCOperand::CreateImm(index));
3662 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
3663 uint64_t Address, const void *Decoder) {
3664 DecodeStatus S = MCDisassembler::Success;
3666 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3667 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3668 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3669 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3670 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3676 return MCDisassembler::Fail;
3678 if (fieldFromInstruction32(Insn, 4, 1))
3679 return MCDisassembler::Fail; // UNDEFINED
3680 index = fieldFromInstruction32(Insn, 5, 3);
3683 if (fieldFromInstruction32(Insn, 5, 1))
3684 return MCDisassembler::Fail; // UNDEFINED
3685 index = fieldFromInstruction32(Insn, 6, 2);
3686 if (fieldFromInstruction32(Insn, 4, 1))
3690 if (fieldFromInstruction32(Insn, 6, 1))
3691 return MCDisassembler::Fail; // UNDEFINED
3692 index = fieldFromInstruction32(Insn, 7, 1);
3693 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3697 if (Rm != 0xF) { // Writeback
3698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3699 return MCDisassembler::Fail;
3701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3702 return MCDisassembler::Fail;
3703 Inst.addOperand(MCOperand::CreateImm(align));
3706 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3707 return MCDisassembler::Fail;
3709 Inst.addOperand(MCOperand::CreateReg(0));
3712 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3713 return MCDisassembler::Fail;
3714 Inst.addOperand(MCOperand::CreateImm(index));
3720 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
3721 uint64_t Address, const void *Decoder) {
3722 DecodeStatus S = MCDisassembler::Success;
3724 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3725 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3726 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3727 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3728 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3735 return MCDisassembler::Fail;
3737 index = fieldFromInstruction32(Insn, 5, 3);
3738 if (fieldFromInstruction32(Insn, 4, 1))
3742 index = fieldFromInstruction32(Insn, 6, 2);
3743 if (fieldFromInstruction32(Insn, 4, 1))
3745 if (fieldFromInstruction32(Insn, 5, 1))
3749 if (fieldFromInstruction32(Insn, 5, 1))
3750 return MCDisassembler::Fail; // UNDEFINED
3751 index = fieldFromInstruction32(Insn, 7, 1);
3752 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3754 if (fieldFromInstruction32(Insn, 6, 1))
3759 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3760 return MCDisassembler::Fail;
3761 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3762 return MCDisassembler::Fail;
3763 if (Rm != 0xF) { // Writeback
3764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3765 return MCDisassembler::Fail;
3767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3768 return MCDisassembler::Fail;
3769 Inst.addOperand(MCOperand::CreateImm(align));
3772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3773 return MCDisassembler::Fail;
3775 Inst.addOperand(MCOperand::CreateReg(0));
3778 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3779 return MCDisassembler::Fail;
3780 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3781 return MCDisassembler::Fail;
3782 Inst.addOperand(MCOperand::CreateImm(index));
3787 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
3788 uint64_t Address, const void *Decoder) {
3789 DecodeStatus S = MCDisassembler::Success;
3791 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3792 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3793 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3794 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3795 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3802 return MCDisassembler::Fail;
3804 index = fieldFromInstruction32(Insn, 5, 3);
3805 if (fieldFromInstruction32(Insn, 4, 1))
3809 index = fieldFromInstruction32(Insn, 6, 2);
3810 if (fieldFromInstruction32(Insn, 4, 1))
3812 if (fieldFromInstruction32(Insn, 5, 1))
3816 if (fieldFromInstruction32(Insn, 5, 1))
3817 return MCDisassembler::Fail; // UNDEFINED
3818 index = fieldFromInstruction32(Insn, 7, 1);
3819 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3821 if (fieldFromInstruction32(Insn, 6, 1))
3826 if (Rm != 0xF) { // Writeback
3827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3828 return MCDisassembler::Fail;
3830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3831 return MCDisassembler::Fail;
3832 Inst.addOperand(MCOperand::CreateImm(align));
3835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3836 return MCDisassembler::Fail;
3838 Inst.addOperand(MCOperand::CreateReg(0));
3841 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3842 return MCDisassembler::Fail;
3843 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3844 return MCDisassembler::Fail;
3845 Inst.addOperand(MCOperand::CreateImm(index));
3851 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
3852 uint64_t Address, const void *Decoder) {
3853 DecodeStatus S = MCDisassembler::Success;
3855 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3856 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3857 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3858 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3859 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3866 return MCDisassembler::Fail;
3868 if (fieldFromInstruction32(Insn, 4, 1))
3869 return MCDisassembler::Fail; // UNDEFINED
3870 index = fieldFromInstruction32(Insn, 5, 3);
3873 if (fieldFromInstruction32(Insn, 4, 1))
3874 return MCDisassembler::Fail; // UNDEFINED
3875 index = fieldFromInstruction32(Insn, 6, 2);
3876 if (fieldFromInstruction32(Insn, 5, 1))
3880 if (fieldFromInstruction32(Insn, 4, 2))
3881 return MCDisassembler::Fail; // UNDEFINED
3882 index = fieldFromInstruction32(Insn, 7, 1);
3883 if (fieldFromInstruction32(Insn, 6, 1))
3888 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3889 return MCDisassembler::Fail;
3890 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3891 return MCDisassembler::Fail;
3892 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3893 return MCDisassembler::Fail;
3895 if (Rm != 0xF) { // Writeback
3896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3897 return MCDisassembler::Fail;
3899 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3900 return MCDisassembler::Fail;
3901 Inst.addOperand(MCOperand::CreateImm(align));
3904 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3905 return MCDisassembler::Fail;
3907 Inst.addOperand(MCOperand::CreateReg(0));
3910 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3911 return MCDisassembler::Fail;
3912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3913 return MCDisassembler::Fail;
3914 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3915 return MCDisassembler::Fail;
3916 Inst.addOperand(MCOperand::CreateImm(index));
3921 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
3922 uint64_t Address, const void *Decoder) {
3923 DecodeStatus S = MCDisassembler::Success;
3925 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3926 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3927 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3928 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3929 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3936 return MCDisassembler::Fail;
3938 if (fieldFromInstruction32(Insn, 4, 1))
3939 return MCDisassembler::Fail; // UNDEFINED
3940 index = fieldFromInstruction32(Insn, 5, 3);
3943 if (fieldFromInstruction32(Insn, 4, 1))
3944 return MCDisassembler::Fail; // UNDEFINED
3945 index = fieldFromInstruction32(Insn, 6, 2);
3946 if (fieldFromInstruction32(Insn, 5, 1))
3950 if (fieldFromInstruction32(Insn, 4, 2))
3951 return MCDisassembler::Fail; // UNDEFINED
3952 index = fieldFromInstruction32(Insn, 7, 1);
3953 if (fieldFromInstruction32(Insn, 6, 1))
3958 if (Rm != 0xF) { // Writeback
3959 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3960 return MCDisassembler::Fail;
3962 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3963 return MCDisassembler::Fail;
3964 Inst.addOperand(MCOperand::CreateImm(align));
3967 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3968 return MCDisassembler::Fail;
3970 Inst.addOperand(MCOperand::CreateReg(0));
3973 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3974 return MCDisassembler::Fail;
3975 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3976 return MCDisassembler::Fail;
3977 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3978 return MCDisassembler::Fail;
3979 Inst.addOperand(MCOperand::CreateImm(index));
3985 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
3986 uint64_t Address, const void *Decoder) {
3987 DecodeStatus S = MCDisassembler::Success;
3989 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3990 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3991 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3992 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3993 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4000 return MCDisassembler::Fail;
4002 if (fieldFromInstruction32(Insn, 4, 1))
4004 index = fieldFromInstruction32(Insn, 5, 3);
4007 if (fieldFromInstruction32(Insn, 4, 1))
4009 index = fieldFromInstruction32(Insn, 6, 2);
4010 if (fieldFromInstruction32(Insn, 5, 1))
4014 if (fieldFromInstruction32(Insn, 4, 2))
4015 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4016 index = fieldFromInstruction32(Insn, 7, 1);
4017 if (fieldFromInstruction32(Insn, 6, 1))
4022 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4023 return MCDisassembler::Fail;
4024 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4025 return MCDisassembler::Fail;
4026 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4027 return MCDisassembler::Fail;
4028 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4029 return MCDisassembler::Fail;
4031 if (Rm != 0xF) { // Writeback
4032 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4033 return MCDisassembler::Fail;
4035 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4036 return MCDisassembler::Fail;
4037 Inst.addOperand(MCOperand::CreateImm(align));
4040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4041 return MCDisassembler::Fail;
4043 Inst.addOperand(MCOperand::CreateReg(0));
4046 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4047 return MCDisassembler::Fail;
4048 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4049 return MCDisassembler::Fail;
4050 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4051 return MCDisassembler::Fail;
4052 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4053 return MCDisassembler::Fail;
4054 Inst.addOperand(MCOperand::CreateImm(index));
4059 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4060 uint64_t Address, const void *Decoder) {
4061 DecodeStatus S = MCDisassembler::Success;
4063 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4064 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4065 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4066 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4067 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4074 return MCDisassembler::Fail;
4076 if (fieldFromInstruction32(Insn, 4, 1))
4078 index = fieldFromInstruction32(Insn, 5, 3);
4081 if (fieldFromInstruction32(Insn, 4, 1))
4083 index = fieldFromInstruction32(Insn, 6, 2);
4084 if (fieldFromInstruction32(Insn, 5, 1))
4088 if (fieldFromInstruction32(Insn, 4, 2))
4089 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4090 index = fieldFromInstruction32(Insn, 7, 1);
4091 if (fieldFromInstruction32(Insn, 6, 1))
4096 if (Rm != 0xF) { // Writeback
4097 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4098 return MCDisassembler::Fail;
4100 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4101 return MCDisassembler::Fail;
4102 Inst.addOperand(MCOperand::CreateImm(align));
4105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4106 return MCDisassembler::Fail;
4108 Inst.addOperand(MCOperand::CreateReg(0));
4111 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4112 return MCDisassembler::Fail;
4113 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4114 return MCDisassembler::Fail;
4115 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4116 return MCDisassembler::Fail;
4117 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4118 return MCDisassembler::Fail;
4119 Inst.addOperand(MCOperand::CreateImm(index));
4124 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4125 uint64_t Address, const void *Decoder) {
4126 DecodeStatus S = MCDisassembler::Success;
4127 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4128 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4129 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4130 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4131 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4133 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4134 S = MCDisassembler::SoftFail;
4136 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4137 return MCDisassembler::Fail;
4138 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4139 return MCDisassembler::Fail;
4140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4141 return MCDisassembler::Fail;
4142 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4143 return MCDisassembler::Fail;
4144 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4145 return MCDisassembler::Fail;
4150 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4151 uint64_t Address, const void *Decoder) {
4152 DecodeStatus S = MCDisassembler::Success;
4153 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4154 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4155 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4156 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4157 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4159 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4160 S = MCDisassembler::SoftFail;
4162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4163 return MCDisassembler::Fail;
4164 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4165 return MCDisassembler::Fail;
4166 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4167 return MCDisassembler::Fail;
4168 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4169 return MCDisassembler::Fail;
4170 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4171 return MCDisassembler::Fail;
4176 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4177 uint64_t Address, const void *Decoder) {
4178 DecodeStatus S = MCDisassembler::Success;
4179 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
4180 // The InstPrinter needs to have the low bit of the predicate in
4181 // the mask operand to be able to print it properly.
4182 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
4186 S = MCDisassembler::SoftFail;
4189 if ((mask & 0xF) == 0) {
4190 // Preserve the high bit of the mask, which is the low bit of
4194 S = MCDisassembler::SoftFail;
4197 Inst.addOperand(MCOperand::CreateImm(pred));
4198 Inst.addOperand(MCOperand::CreateImm(mask));
4203 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4204 uint64_t Address, const void *Decoder) {
4205 DecodeStatus S = MCDisassembler::Success;
4207 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4208 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4209 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4210 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4211 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4212 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4213 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4214 bool writeback = (W == 1) | (P == 0);
4216 addr |= (U << 8) | (Rn << 9);
4218 if (writeback && (Rn == Rt || Rn == Rt2))
4219 Check(S, MCDisassembler::SoftFail);
4221 Check(S, MCDisassembler::SoftFail);
4224 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4225 return MCDisassembler::Fail;
4227 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4228 return MCDisassembler::Fail;
4229 // Writeback operand
4230 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4231 return MCDisassembler::Fail;
4233 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4234 return MCDisassembler::Fail;
4240 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4241 uint64_t Address, const void *Decoder) {
4242 DecodeStatus S = MCDisassembler::Success;
4244 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4245 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4246 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4247 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4248 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4249 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4250 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4251 bool writeback = (W == 1) | (P == 0);
4253 addr |= (U << 8) | (Rn << 9);
4255 if (writeback && (Rn == Rt || Rn == Rt2))
4256 Check(S, MCDisassembler::SoftFail);
4258 // Writeback operand
4259 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4260 return MCDisassembler::Fail;
4262 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4263 return MCDisassembler::Fail;
4265 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4266 return MCDisassembler::Fail;
4268 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4269 return MCDisassembler::Fail;
4274 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4275 uint64_t Address, const void *Decoder) {
4276 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4277 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4278 if (sign1 != sign2) return MCDisassembler::Fail;
4280 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4281 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4282 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4284 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4286 return MCDisassembler::Success;
4289 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4291 const void *Decoder) {
4292 DecodeStatus S = MCDisassembler::Success;
4294 // Shift of "asr #32" is not allowed in Thumb2 mode.
4295 if (Val == 0x20) S = MCDisassembler::SoftFail;
4296 Inst.addOperand(MCOperand::CreateImm(Val));
4300 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4301 uint64_t Address, const void *Decoder) {
4302 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4303 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4304 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4305 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4308 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4310 DecodeStatus S = MCDisassembler::Success;
4311 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4312 return MCDisassembler::Fail;
4313 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4314 return MCDisassembler::Fail;
4315 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4316 return MCDisassembler::Fail;
4317 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4318 return MCDisassembler::Fail;
4323 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
4324 uint64_t Address, const void *Decoder) {
4325 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4326 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4327 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4328 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4329 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4330 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4332 DecodeStatus S = MCDisassembler::Success;
4334 // VMOVv2f32 is ambiguous with these decodings.
4335 if (!(imm & 0x38) && cmode == 0xF) {
4336 Inst.setOpcode(ARM::VMOVv2f32);
4337 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4340 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4342 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4343 return MCDisassembler::Fail;
4344 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4345 return MCDisassembler::Fail;
4346 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4351 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
4352 uint64_t Address, const void *Decoder) {
4353 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4354 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4355 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4356 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4357 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4358 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4360 DecodeStatus S = MCDisassembler::Success;
4362 // VMOVv4f32 is ambiguous with these decodings.
4363 if (!(imm & 0x38) && cmode == 0xF) {
4364 Inst.setOpcode(ARM::VMOVv4f32);
4365 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4368 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4370 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4371 return MCDisassembler::Fail;
4372 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4373 return MCDisassembler::Fail;
4374 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4379 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
4380 uint64_t Address, const void *Decoder) {
4381 DecodeStatus S = MCDisassembler::Success;
4383 unsigned Rn = fieldFromInstruction32(Val, 16, 4);
4384 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4385 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
4386 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4);
4387 unsigned Cond = fieldFromInstruction32(Val, 28, 4);
4389 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt)
4390 S = MCDisassembler::SoftFail;
4392 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4393 return MCDisassembler::Fail;
4394 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4395 return MCDisassembler::Fail;
4396 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4397 return MCDisassembler::Fail;
4398 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4399 return MCDisassembler::Fail;
4400 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4401 return MCDisassembler::Fail;