1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "llvm/MC/MCDisassembler.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/LEB128.h"
25 #include "llvm/Support/MemoryObject.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
32 typedef MCDisassembler::DecodeStatus DecodeStatus;
35 // Handles the condition code status of instructions in IT blocks
39 // Returns the condition code for instruction in IT block
41 unsigned CC = ARMCC::AL;
47 // Advances the IT block state to the next T or E
48 void advanceITState() {
52 // Returns true if the current instruction is in an IT block
53 bool instrInITBlock() {
54 return !ITStates.empty();
57 // Returns true if current instruction is the last instruction in an IT block
58 bool instrLastInITBlock() {
59 return ITStates.size() == 1;
62 // Called when decoding an IT instruction. Sets the IT state for the following
63 // instructions that for the IT block. Firstcond and Mask correspond to the
64 // fields in the IT instruction encoding.
65 void setITState(char Firstcond, char Mask) {
66 // (3 - the number of trailing zeros) is the number of then / else.
67 unsigned CondBit0 = Firstcond & 1;
68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
70 assert(NumTZ <= 3 && "Invalid IT mask!");
71 // push condition codes onto the stack the correct order for the pops
72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
75 ITStates.push_back(CCBits);
77 ITStates.push_back(CCBits ^ 1);
79 ITStates.push_back(CCBits);
83 std::vector<unsigned char> ITStates;
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
89 class ARMDisassembler : public MCDisassembler {
91 /// Constructor - Initializes the disassembler.
93 ARMDisassembler(const MCSubtargetInfo &STI) :
100 /// getInstruction - See MCDisassembler.
101 DecodeStatus getInstruction(MCInst &instr,
103 const MemoryObject ®ion,
105 raw_ostream &vStream,
106 raw_ostream &cStream) const;
109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
110 class ThumbDisassembler : public MCDisassembler {
112 /// Constructor - Initializes the disassembler.
114 ThumbDisassembler(const MCSubtargetInfo &STI) :
115 MCDisassembler(STI) {
118 ~ThumbDisassembler() {
121 /// getInstruction - See MCDisassembler.
122 DecodeStatus getInstruction(MCInst &instr,
124 const MemoryObject ®ion,
126 raw_ostream &vStream,
127 raw_ostream &cStream) const;
130 mutable ITStatus ITBlock;
131 DecodeStatus AddThumbPredicate(MCInst&) const;
132 void UpdateThumbVFPPredicate(MCInst&) const;
136 static bool Check(DecodeStatus &Out, DecodeStatus In) {
138 case MCDisassembler::Success:
139 // Out stays the same.
141 case MCDisassembler::SoftFail:
144 case MCDisassembler::Fail:
148 llvm_unreachable("Invalid DecodeStatus!");
152 // Forward declare these because the autogenerated code will reference them.
153 // Definitions are further down.
154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
155 uint64_t Address, const void *Decoder);
156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
157 unsigned RegNo, uint64_t Address,
158 const void *Decoder);
159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
160 unsigned RegNo, uint64_t Address,
161 const void *Decoder);
162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
179 const void *Decoder);
180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
185 unsigned RegNo, uint64_t Address,
186 const void *Decoder);
188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
199 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
208 const void *Decoder);
209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
221 const void *Decoder);
222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
317 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
323 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
327 const void *Decoder);
330 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
347 uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
349 uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
351 uint64_t Address, const void *Decoder);
352 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
353 uint64_t Address, const void *Decoder);
354 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
381 uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
383 uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
385 uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
387 uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
389 uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
391 uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
393 uint64_t Address, const void *Decoder);
395 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
396 uint64_t Address, const void *Decoder);
397 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
398 uint64_t Address, const void *Decoder);
399 #include "ARMGenDisassemblerTables.inc"
401 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
402 return new ARMDisassembler(STI);
405 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
406 return new ThumbDisassembler(STI);
409 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
410 const MemoryObject &Region,
413 raw_ostream &cs) const {
418 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
419 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
421 // We want to read exactly 4 bytes of data.
422 if (Region.readBytes(Address, 4, bytes) == -1) {
424 return MCDisassembler::Fail;
427 // Encoded as a small-endian 32-bit word in the stream.
428 uint32_t insn = (bytes[3] << 24) |
433 // Calling the auto-generated decoder function.
434 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
436 if (result != MCDisassembler::Fail) {
441 // VFP and NEON instructions, similarly, are shared between ARM
444 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
445 if (result != MCDisassembler::Fail) {
451 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
453 if (result != MCDisassembler::Fail) {
455 // Add a fake predicate operand, because we share these instruction
456 // definitions with Thumb2 where these instructions are predicable.
457 if (!DecodePredicateOperand(MI, 0xE, Address, this))
458 return MCDisassembler::Fail;
463 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
465 if (result != MCDisassembler::Fail) {
467 // Add a fake predicate operand, because we share these instruction
468 // definitions with Thumb2 where these instructions are predicable.
469 if (!DecodePredicateOperand(MI, 0xE, Address, this))
470 return MCDisassembler::Fail;
475 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
477 if (result != MCDisassembler::Fail) {
479 // Add a fake predicate operand, because we share these instruction
480 // definitions with Thumb2 where these instructions are predicable.
481 if (!DecodePredicateOperand(MI, 0xE, Address, this))
482 return MCDisassembler::Fail;
489 return MCDisassembler::Fail;
493 extern const MCInstrDesc ARMInsts[];
496 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
497 /// immediate Value in the MCInst. The immediate Value has had any PC
498 /// adjustment made by the caller. If the instruction is a branch instruction
499 /// then isBranch is true, else false. If the getOpInfo() function was set as
500 /// part of the setupForSymbolicDisassembly() call then that function is called
501 /// to get any symbolic information at the Address for this instruction. If
502 /// that returns non-zero then the symbolic information it returns is used to
503 /// create an MCExpr and that is added as an operand to the MCInst. If
504 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
505 /// Value is done and if a symbol is found an MCExpr is created with that, else
506 /// an MCExpr with Value is created. This function returns true if it adds an
507 /// operand to the MCInst and false otherwise.
508 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
509 bool isBranch, uint64_t InstSize,
510 MCInst &MI, const void *Decoder) {
511 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
512 // FIXME: Does it make sense for value to be negative?
513 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
514 /* Offset */ 0, InstSize);
517 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
518 /// referenced by a load instruction with the base register that is the Pc.
519 /// These can often be values in a literal pool near the Address of the
520 /// instruction. The Address of the instruction and its immediate Value are
521 /// used as a possible literal pool entry. The SymbolLookUp call back will
522 /// return the name of a symbol referenced by the literal pool's entry if
523 /// the referenced address is that of a symbol. Or it will return a pointer to
524 /// a literal 'C' string if the referenced address of the literal pool's entry
525 /// is an address into a section with 'C' string literals.
526 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
527 const void *Decoder) {
528 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
529 Dis->tryAddingPcLoadReferenceComment(Value, Address);
532 // Thumb1 instructions don't have explicit S bits. Rather, they
533 // implicitly set CPSR. Since it's not represented in the encoding, the
534 // auto-generated decoder won't inject the CPSR operand. We need to fix
535 // that as a post-pass.
536 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
537 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
538 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
539 MCInst::iterator I = MI.begin();
540 for (unsigned i = 0; i < NumOps; ++i, ++I) {
541 if (I == MI.end()) break;
542 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
543 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
544 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
549 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
552 // Most Thumb instructions don't have explicit predicates in the
553 // encoding, but rather get their predicates from IT context. We need
554 // to fix up the predicate operands using this context information as a
556 MCDisassembler::DecodeStatus
557 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
558 MCDisassembler::DecodeStatus S = Success;
560 // A few instructions actually have predicates encoded in them. Don't
561 // try to overwrite it if we're seeing one of those.
562 switch (MI.getOpcode()) {
573 // Some instructions (mostly conditional branches) are not
574 // allowed in IT blocks.
575 if (ITBlock.instrInITBlock())
584 // Some instructions (mostly unconditional branches) can
585 // only appears at the end of, or outside of, an IT.
586 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
593 // If we're in an IT block, base the predicate on that. Otherwise,
594 // assume a predicate of AL.
596 CC = ITBlock.getITCC();
599 if (ITBlock.instrInITBlock())
600 ITBlock.advanceITState();
602 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
603 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
604 MCInst::iterator I = MI.begin();
605 for (unsigned i = 0; i < NumOps; ++i, ++I) {
606 if (I == MI.end()) break;
607 if (OpInfo[i].isPredicate()) {
608 I = MI.insert(I, MCOperand::CreateImm(CC));
611 MI.insert(I, MCOperand::CreateReg(0));
613 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
618 I = MI.insert(I, MCOperand::CreateImm(CC));
621 MI.insert(I, MCOperand::CreateReg(0));
623 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
628 // Thumb VFP instructions are a special case. Because we share their
629 // encodings between ARM and Thumb modes, and they are predicable in ARM
630 // mode, the auto-generated decoder will give them an (incorrect)
631 // predicate operand. We need to rewrite these operands based on the IT
632 // context as a post-pass.
633 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
635 CC = ITBlock.getITCC();
636 if (ITBlock.instrInITBlock())
637 ITBlock.advanceITState();
639 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
640 MCInst::iterator I = MI.begin();
641 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
642 for (unsigned i = 0; i < NumOps; ++i, ++I) {
643 if (OpInfo[i].isPredicate() ) {
649 I->setReg(ARM::CPSR);
655 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
656 const MemoryObject &Region,
659 raw_ostream &cs) const {
664 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
665 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
667 // We want to read exactly 2 bytes of data.
668 if (Region.readBytes(Address, 2, bytes) == -1) {
670 return MCDisassembler::Fail;
673 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
674 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
676 if (result != MCDisassembler::Fail) {
678 Check(result, AddThumbPredicate(MI));
683 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
687 bool InITBlock = ITBlock.instrInITBlock();
688 Check(result, AddThumbPredicate(MI));
689 AddThumb1SBit(MI, InITBlock);
694 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
696 if (result != MCDisassembler::Fail) {
699 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
700 // the Thumb predicate.
701 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
702 result = MCDisassembler::SoftFail;
704 Check(result, AddThumbPredicate(MI));
706 // If we find an IT instruction, we need to parse its condition
707 // code and mask operands so that we can apply them correctly
708 // to the subsequent instructions.
709 if (MI.getOpcode() == ARM::t2IT) {
711 unsigned Firstcond = MI.getOperand(0).getImm();
712 unsigned Mask = MI.getOperand(1).getImm();
713 ITBlock.setITState(Firstcond, Mask);
719 // We want to read exactly 4 bytes of data.
720 if (Region.readBytes(Address, 4, bytes) == -1) {
722 return MCDisassembler::Fail;
725 uint32_t insn32 = (bytes[3] << 8) |
730 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
732 if (result != MCDisassembler::Fail) {
734 bool InITBlock = ITBlock.instrInITBlock();
735 Check(result, AddThumbPredicate(MI));
736 AddThumb1SBit(MI, InITBlock);
741 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
743 if (result != MCDisassembler::Fail) {
745 Check(result, AddThumbPredicate(MI));
750 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
751 if (result != MCDisassembler::Fail) {
753 UpdateThumbVFPPredicate(MI);
758 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
760 if (result != MCDisassembler::Fail) {
762 Check(result, AddThumbPredicate(MI));
766 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
768 uint32_t NEONLdStInsn = insn32;
769 NEONLdStInsn &= 0xF0FFFFFF;
770 NEONLdStInsn |= 0x04000000;
771 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
773 if (result != MCDisassembler::Fail) {
775 Check(result, AddThumbPredicate(MI));
780 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
782 uint32_t NEONDataInsn = insn32;
783 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
784 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
785 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
786 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
788 if (result != MCDisassembler::Fail) {
790 Check(result, AddThumbPredicate(MI));
796 return MCDisassembler::Fail;
800 extern "C" void LLVMInitializeARMDisassembler() {
801 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
802 createARMDisassembler);
803 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
804 createThumbDisassembler);
807 static const uint16_t GPRDecoderTable[] = {
808 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
809 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
810 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
811 ARM::R12, ARM::SP, ARM::LR, ARM::PC
814 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
815 uint64_t Address, const void *Decoder) {
817 return MCDisassembler::Fail;
819 unsigned Register = GPRDecoderTable[RegNo];
820 Inst.addOperand(MCOperand::CreateReg(Register));
821 return MCDisassembler::Success;
825 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
826 uint64_t Address, const void *Decoder) {
827 DecodeStatus S = MCDisassembler::Success;
830 S = MCDisassembler::SoftFail;
832 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
838 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
839 uint64_t Address, const void *Decoder) {
840 DecodeStatus S = MCDisassembler::Success;
844 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
845 return MCDisassembler::Success;
848 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
852 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
853 uint64_t Address, const void *Decoder) {
855 return MCDisassembler::Fail;
856 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
859 static const uint16_t GPRPairDecoderTable[] = {
860 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
861 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
864 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
865 uint64_t Address, const void *Decoder) {
866 DecodeStatus S = MCDisassembler::Success;
869 return MCDisassembler::Fail;
871 if ((RegNo & 1) || RegNo == 0xe)
872 S = MCDisassembler::SoftFail;
874 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
875 Inst.addOperand(MCOperand::CreateReg(RegisterPair));
879 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
880 uint64_t Address, const void *Decoder) {
881 unsigned Register = 0;
902 return MCDisassembler::Fail;
905 Inst.addOperand(MCOperand::CreateReg(Register));
906 return MCDisassembler::Success;
909 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
910 uint64_t Address, const void *Decoder) {
911 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
912 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
915 static const uint16_t SPRDecoderTable[] = {
916 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
917 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
918 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
919 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
920 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
921 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
922 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
923 ARM::S28, ARM::S29, ARM::S30, ARM::S31
926 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
927 uint64_t Address, const void *Decoder) {
929 return MCDisassembler::Fail;
931 unsigned Register = SPRDecoderTable[RegNo];
932 Inst.addOperand(MCOperand::CreateReg(Register));
933 return MCDisassembler::Success;
936 static const uint16_t DPRDecoderTable[] = {
937 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
938 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
939 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
940 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
941 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
942 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
943 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
944 ARM::D28, ARM::D29, ARM::D30, ARM::D31
947 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
948 uint64_t Address, const void *Decoder) {
950 return MCDisassembler::Fail;
952 unsigned Register = DPRDecoderTable[RegNo];
953 Inst.addOperand(MCOperand::CreateReg(Register));
954 return MCDisassembler::Success;
957 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
958 uint64_t Address, const void *Decoder) {
960 return MCDisassembler::Fail;
961 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
965 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
966 uint64_t Address, const void *Decoder) {
968 return MCDisassembler::Fail;
969 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
972 static const uint16_t QPRDecoderTable[] = {
973 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
974 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
975 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
976 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
980 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
981 uint64_t Address, const void *Decoder) {
982 if (RegNo > 31 || (RegNo & 1) != 0)
983 return MCDisassembler::Fail;
986 unsigned Register = QPRDecoderTable[RegNo];
987 Inst.addOperand(MCOperand::CreateReg(Register));
988 return MCDisassembler::Success;
991 static const uint16_t DPairDecoderTable[] = {
992 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
993 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
994 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
995 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
996 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1000 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1001 uint64_t Address, const void *Decoder) {
1003 return MCDisassembler::Fail;
1005 unsigned Register = DPairDecoderTable[RegNo];
1006 Inst.addOperand(MCOperand::CreateReg(Register));
1007 return MCDisassembler::Success;
1010 static const uint16_t DPairSpacedDecoderTable[] = {
1011 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1012 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1013 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1014 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1015 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1016 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1017 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1018 ARM::D28_D30, ARM::D29_D31
1021 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1024 const void *Decoder) {
1026 return MCDisassembler::Fail;
1028 unsigned Register = DPairSpacedDecoderTable[RegNo];
1029 Inst.addOperand(MCOperand::CreateReg(Register));
1030 return MCDisassembler::Success;
1033 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1034 uint64_t Address, const void *Decoder) {
1035 if (Val == 0xF) return MCDisassembler::Fail;
1036 // AL predicate is not allowed on Thumb1 branches.
1037 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1038 return MCDisassembler::Fail;
1039 Inst.addOperand(MCOperand::CreateImm(Val));
1040 if (Val == ARMCC::AL) {
1041 Inst.addOperand(MCOperand::CreateReg(0));
1043 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1044 return MCDisassembler::Success;
1047 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1048 uint64_t Address, const void *Decoder) {
1050 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1052 Inst.addOperand(MCOperand::CreateReg(0));
1053 return MCDisassembler::Success;
1056 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1057 uint64_t Address, const void *Decoder) {
1058 uint32_t imm = Val & 0xFF;
1059 uint32_t rot = (Val & 0xF00) >> 7;
1060 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1061 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1062 return MCDisassembler::Success;
1065 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1066 uint64_t Address, const void *Decoder) {
1067 DecodeStatus S = MCDisassembler::Success;
1069 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1070 unsigned type = fieldFromInstruction(Val, 5, 2);
1071 unsigned imm = fieldFromInstruction(Val, 7, 5);
1073 // Register-immediate
1074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1075 return MCDisassembler::Fail;
1077 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1080 Shift = ARM_AM::lsl;
1083 Shift = ARM_AM::lsr;
1086 Shift = ARM_AM::asr;
1089 Shift = ARM_AM::ror;
1093 if (Shift == ARM_AM::ror && imm == 0)
1094 Shift = ARM_AM::rrx;
1096 unsigned Op = Shift | (imm << 3);
1097 Inst.addOperand(MCOperand::CreateImm(Op));
1102 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1103 uint64_t Address, const void *Decoder) {
1104 DecodeStatus S = MCDisassembler::Success;
1106 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1107 unsigned type = fieldFromInstruction(Val, 5, 2);
1108 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1110 // Register-register
1111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1112 return MCDisassembler::Fail;
1113 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1114 return MCDisassembler::Fail;
1116 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1119 Shift = ARM_AM::lsl;
1122 Shift = ARM_AM::lsr;
1125 Shift = ARM_AM::asr;
1128 Shift = ARM_AM::ror;
1132 Inst.addOperand(MCOperand::CreateImm(Shift));
1137 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1138 uint64_t Address, const void *Decoder) {
1139 DecodeStatus S = MCDisassembler::Success;
1141 bool writebackLoad = false;
1142 unsigned writebackReg = 0;
1143 switch (Inst.getOpcode()) {
1146 case ARM::LDMIA_UPD:
1147 case ARM::LDMDB_UPD:
1148 case ARM::LDMIB_UPD:
1149 case ARM::LDMDA_UPD:
1150 case ARM::t2LDMIA_UPD:
1151 case ARM::t2LDMDB_UPD:
1152 writebackLoad = true;
1153 writebackReg = Inst.getOperand(0).getReg();
1157 // Empty register lists are not allowed.
1158 if (Val == 0) return MCDisassembler::Fail;
1159 for (unsigned i = 0; i < 16; ++i) {
1160 if (Val & (1 << i)) {
1161 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1162 return MCDisassembler::Fail;
1163 // Writeback not allowed if Rn is in the target list.
1164 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1165 Check(S, MCDisassembler::SoftFail);
1172 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1173 uint64_t Address, const void *Decoder) {
1174 DecodeStatus S = MCDisassembler::Success;
1176 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1177 unsigned regs = fieldFromInstruction(Val, 0, 8);
1179 // In case of unpredictable encoding, tweak the operands.
1180 if (regs == 0 || (Vd + regs) > 32) {
1181 regs = Vd + regs > 32 ? 32 - Vd : regs;
1182 regs = std::max( 1u, regs);
1183 S = MCDisassembler::SoftFail;
1186 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1187 return MCDisassembler::Fail;
1188 for (unsigned i = 0; i < (regs - 1); ++i) {
1189 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1190 return MCDisassembler::Fail;
1196 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1197 uint64_t Address, const void *Decoder) {
1198 DecodeStatus S = MCDisassembler::Success;
1200 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1201 unsigned regs = fieldFromInstruction(Val, 1, 7);
1203 // In case of unpredictable encoding, tweak the operands.
1204 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1205 regs = Vd + regs > 32 ? 32 - Vd : regs;
1206 regs = std::max( 1u, regs);
1207 regs = std::min(16u, regs);
1208 S = MCDisassembler::SoftFail;
1211 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1212 return MCDisassembler::Fail;
1213 for (unsigned i = 0; i < (regs - 1); ++i) {
1214 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1215 return MCDisassembler::Fail;
1221 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1222 uint64_t Address, const void *Decoder) {
1223 // This operand encodes a mask of contiguous zeros between a specified MSB
1224 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1225 // the mask of all bits LSB-and-lower, and then xor them to create
1226 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1227 // create the final mask.
1228 unsigned msb = fieldFromInstruction(Val, 5, 5);
1229 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1231 DecodeStatus S = MCDisassembler::Success;
1233 Check(S, MCDisassembler::SoftFail);
1234 // The check above will cause the warning for the "potentially undefined
1235 // instruction encoding" but we can't build a bad MCOperand value here
1236 // with a lsb > msb or else printing the MCInst will cause a crash.
1240 uint32_t msb_mask = 0xFFFFFFFF;
1241 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1242 uint32_t lsb_mask = (1U << lsb) - 1;
1244 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1248 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1249 uint64_t Address, const void *Decoder) {
1250 DecodeStatus S = MCDisassembler::Success;
1252 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1253 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1254 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1255 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1256 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1257 unsigned U = fieldFromInstruction(Insn, 23, 1);
1259 switch (Inst.getOpcode()) {
1260 case ARM::LDC_OFFSET:
1263 case ARM::LDC_OPTION:
1264 case ARM::LDCL_OFFSET:
1266 case ARM::LDCL_POST:
1267 case ARM::LDCL_OPTION:
1268 case ARM::STC_OFFSET:
1271 case ARM::STC_OPTION:
1272 case ARM::STCL_OFFSET:
1274 case ARM::STCL_POST:
1275 case ARM::STCL_OPTION:
1276 case ARM::t2LDC_OFFSET:
1277 case ARM::t2LDC_PRE:
1278 case ARM::t2LDC_POST:
1279 case ARM::t2LDC_OPTION:
1280 case ARM::t2LDCL_OFFSET:
1281 case ARM::t2LDCL_PRE:
1282 case ARM::t2LDCL_POST:
1283 case ARM::t2LDCL_OPTION:
1284 case ARM::t2STC_OFFSET:
1285 case ARM::t2STC_PRE:
1286 case ARM::t2STC_POST:
1287 case ARM::t2STC_OPTION:
1288 case ARM::t2STCL_OFFSET:
1289 case ARM::t2STCL_PRE:
1290 case ARM::t2STCL_POST:
1291 case ARM::t2STCL_OPTION:
1292 if (coproc == 0xA || coproc == 0xB)
1293 return MCDisassembler::Fail;
1299 Inst.addOperand(MCOperand::CreateImm(coproc));
1300 Inst.addOperand(MCOperand::CreateImm(CRd));
1301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1302 return MCDisassembler::Fail;
1304 switch (Inst.getOpcode()) {
1305 case ARM::t2LDC2_OFFSET:
1306 case ARM::t2LDC2L_OFFSET:
1307 case ARM::t2LDC2_PRE:
1308 case ARM::t2LDC2L_PRE:
1309 case ARM::t2STC2_OFFSET:
1310 case ARM::t2STC2L_OFFSET:
1311 case ARM::t2STC2_PRE:
1312 case ARM::t2STC2L_PRE:
1313 case ARM::LDC2_OFFSET:
1314 case ARM::LDC2L_OFFSET:
1316 case ARM::LDC2L_PRE:
1317 case ARM::STC2_OFFSET:
1318 case ARM::STC2L_OFFSET:
1320 case ARM::STC2L_PRE:
1321 case ARM::t2LDC_OFFSET:
1322 case ARM::t2LDCL_OFFSET:
1323 case ARM::t2LDC_PRE:
1324 case ARM::t2LDCL_PRE:
1325 case ARM::t2STC_OFFSET:
1326 case ARM::t2STCL_OFFSET:
1327 case ARM::t2STC_PRE:
1328 case ARM::t2STCL_PRE:
1329 case ARM::LDC_OFFSET:
1330 case ARM::LDCL_OFFSET:
1333 case ARM::STC_OFFSET:
1334 case ARM::STCL_OFFSET:
1337 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1338 Inst.addOperand(MCOperand::CreateImm(imm));
1340 case ARM::t2LDC2_POST:
1341 case ARM::t2LDC2L_POST:
1342 case ARM::t2STC2_POST:
1343 case ARM::t2STC2L_POST:
1344 case ARM::LDC2_POST:
1345 case ARM::LDC2L_POST:
1346 case ARM::STC2_POST:
1347 case ARM::STC2L_POST:
1348 case ARM::t2LDC_POST:
1349 case ARM::t2LDCL_POST:
1350 case ARM::t2STC_POST:
1351 case ARM::t2STCL_POST:
1353 case ARM::LDCL_POST:
1355 case ARM::STCL_POST:
1359 // The 'option' variant doesn't encode 'U' in the immediate since
1360 // the immediate is unsigned [0,255].
1361 Inst.addOperand(MCOperand::CreateImm(imm));
1365 switch (Inst.getOpcode()) {
1366 case ARM::LDC_OFFSET:
1369 case ARM::LDC_OPTION:
1370 case ARM::LDCL_OFFSET:
1372 case ARM::LDCL_POST:
1373 case ARM::LDCL_OPTION:
1374 case ARM::STC_OFFSET:
1377 case ARM::STC_OPTION:
1378 case ARM::STCL_OFFSET:
1380 case ARM::STCL_POST:
1381 case ARM::STCL_OPTION:
1382 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1383 return MCDisassembler::Fail;
1393 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1394 uint64_t Address, const void *Decoder) {
1395 DecodeStatus S = MCDisassembler::Success;
1397 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1398 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1399 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1400 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1401 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1402 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1403 unsigned P = fieldFromInstruction(Insn, 24, 1);
1404 unsigned W = fieldFromInstruction(Insn, 21, 1);
1406 // On stores, the writeback operand precedes Rt.
1407 switch (Inst.getOpcode()) {
1408 case ARM::STR_POST_IMM:
1409 case ARM::STR_POST_REG:
1410 case ARM::STRB_POST_IMM:
1411 case ARM::STRB_POST_REG:
1412 case ARM::STRT_POST_REG:
1413 case ARM::STRT_POST_IMM:
1414 case ARM::STRBT_POST_REG:
1415 case ARM::STRBT_POST_IMM:
1416 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1417 return MCDisassembler::Fail;
1423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1424 return MCDisassembler::Fail;
1426 // On loads, the writeback operand comes after Rt.
1427 switch (Inst.getOpcode()) {
1428 case ARM::LDR_POST_IMM:
1429 case ARM::LDR_POST_REG:
1430 case ARM::LDRB_POST_IMM:
1431 case ARM::LDRB_POST_REG:
1432 case ARM::LDRBT_POST_REG:
1433 case ARM::LDRBT_POST_IMM:
1434 case ARM::LDRT_POST_REG:
1435 case ARM::LDRT_POST_IMM:
1436 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1437 return MCDisassembler::Fail;
1443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1444 return MCDisassembler::Fail;
1446 ARM_AM::AddrOpc Op = ARM_AM::add;
1447 if (!fieldFromInstruction(Insn, 23, 1))
1450 bool writeback = (P == 0) || (W == 1);
1451 unsigned idx_mode = 0;
1453 idx_mode = ARMII::IndexModePre;
1454 else if (!P && writeback)
1455 idx_mode = ARMII::IndexModePost;
1457 if (writeback && (Rn == 15 || Rn == Rt))
1458 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1461 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1462 return MCDisassembler::Fail;
1463 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1464 switch( fieldFromInstruction(Insn, 5, 2)) {
1478 return MCDisassembler::Fail;
1480 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1481 if (Opc == ARM_AM::ror && amt == 0)
1483 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1485 Inst.addOperand(MCOperand::CreateImm(imm));
1487 Inst.addOperand(MCOperand::CreateReg(0));
1488 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1489 Inst.addOperand(MCOperand::CreateImm(tmp));
1492 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1493 return MCDisassembler::Fail;
1498 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1499 uint64_t Address, const void *Decoder) {
1500 DecodeStatus S = MCDisassembler::Success;
1502 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1503 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1504 unsigned type = fieldFromInstruction(Val, 5, 2);
1505 unsigned imm = fieldFromInstruction(Val, 7, 5);
1506 unsigned U = fieldFromInstruction(Val, 12, 1);
1508 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1524 if (ShOp == ARM_AM::ror && imm == 0)
1527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1528 return MCDisassembler::Fail;
1529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1530 return MCDisassembler::Fail;
1533 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1535 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1536 Inst.addOperand(MCOperand::CreateImm(shift));
1542 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1543 uint64_t Address, const void *Decoder) {
1544 DecodeStatus S = MCDisassembler::Success;
1546 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1547 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1548 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1549 unsigned type = fieldFromInstruction(Insn, 22, 1);
1550 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1551 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1552 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1553 unsigned W = fieldFromInstruction(Insn, 21, 1);
1554 unsigned P = fieldFromInstruction(Insn, 24, 1);
1555 unsigned Rt2 = Rt + 1;
1557 bool writeback = (W == 1) | (P == 0);
1559 // For {LD,ST}RD, Rt must be even, else undefined.
1560 switch (Inst.getOpcode()) {
1563 case ARM::STRD_POST:
1566 case ARM::LDRD_POST:
1567 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1572 switch (Inst.getOpcode()) {
1575 case ARM::STRD_POST:
1576 if (P == 0 && W == 1)
1577 S = MCDisassembler::SoftFail;
1579 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1580 S = MCDisassembler::SoftFail;
1581 if (type && Rm == 15)
1582 S = MCDisassembler::SoftFail;
1584 S = MCDisassembler::SoftFail;
1585 if (!type && fieldFromInstruction(Insn, 8, 4))
1586 S = MCDisassembler::SoftFail;
1590 case ARM::STRH_POST:
1592 S = MCDisassembler::SoftFail;
1593 if (writeback && (Rn == 15 || Rn == Rt))
1594 S = MCDisassembler::SoftFail;
1595 if (!type && Rm == 15)
1596 S = MCDisassembler::SoftFail;
1600 case ARM::LDRD_POST:
1601 if (type && Rn == 15){
1603 S = MCDisassembler::SoftFail;
1606 if (P == 0 && W == 1)
1607 S = MCDisassembler::SoftFail;
1608 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1609 S = MCDisassembler::SoftFail;
1610 if (!type && writeback && Rn == 15)
1611 S = MCDisassembler::SoftFail;
1612 if (writeback && (Rn == Rt || Rn == Rt2))
1613 S = MCDisassembler::SoftFail;
1617 case ARM::LDRH_POST:
1618 if (type && Rn == 15){
1620 S = MCDisassembler::SoftFail;
1624 S = MCDisassembler::SoftFail;
1625 if (!type && Rm == 15)
1626 S = MCDisassembler::SoftFail;
1627 if (!type && writeback && (Rn == 15 || Rn == Rt))
1628 S = MCDisassembler::SoftFail;
1631 case ARM::LDRSH_PRE:
1632 case ARM::LDRSH_POST:
1634 case ARM::LDRSB_PRE:
1635 case ARM::LDRSB_POST:
1636 if (type && Rn == 15){
1638 S = MCDisassembler::SoftFail;
1641 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1642 S = MCDisassembler::SoftFail;
1643 if (!type && (Rt == 15 || Rm == 15))
1644 S = MCDisassembler::SoftFail;
1645 if (!type && writeback && (Rn == 15 || Rn == Rt))
1646 S = MCDisassembler::SoftFail;
1652 if (writeback) { // Writeback
1654 U |= ARMII::IndexModePre << 9;
1656 U |= ARMII::IndexModePost << 9;
1658 // On stores, the writeback operand precedes Rt.
1659 switch (Inst.getOpcode()) {
1662 case ARM::STRD_POST:
1665 case ARM::STRH_POST:
1666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1667 return MCDisassembler::Fail;
1674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1675 return MCDisassembler::Fail;
1676 switch (Inst.getOpcode()) {
1679 case ARM::STRD_POST:
1682 case ARM::LDRD_POST:
1683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1684 return MCDisassembler::Fail;
1691 // On loads, the writeback operand comes after Rt.
1692 switch (Inst.getOpcode()) {
1695 case ARM::LDRD_POST:
1698 case ARM::LDRH_POST:
1700 case ARM::LDRSH_PRE:
1701 case ARM::LDRSH_POST:
1703 case ARM::LDRSB_PRE:
1704 case ARM::LDRSB_POST:
1707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1708 return MCDisassembler::Fail;
1715 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1716 return MCDisassembler::Fail;
1719 Inst.addOperand(MCOperand::CreateReg(0));
1720 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1722 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1723 return MCDisassembler::Fail;
1724 Inst.addOperand(MCOperand::CreateImm(U));
1727 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1728 return MCDisassembler::Fail;
1733 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1734 uint64_t Address, const void *Decoder) {
1735 DecodeStatus S = MCDisassembler::Success;
1737 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1738 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1755 Inst.addOperand(MCOperand::CreateImm(mode));
1756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1757 return MCDisassembler::Fail;
1762 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1763 uint64_t Address, const void *Decoder) {
1764 DecodeStatus S = MCDisassembler::Success;
1766 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1767 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1768 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1769 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1772 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1774 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1775 return MCDisassembler::Fail;
1776 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1777 return MCDisassembler::Fail;
1778 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1779 return MCDisassembler::Fail;
1780 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1781 return MCDisassembler::Fail;
1785 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1787 uint64_t Address, const void *Decoder) {
1788 DecodeStatus S = MCDisassembler::Success;
1790 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1791 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1792 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1795 // Ambiguous with RFE and SRS
1796 switch (Inst.getOpcode()) {
1798 Inst.setOpcode(ARM::RFEDA);
1800 case ARM::LDMDA_UPD:
1801 Inst.setOpcode(ARM::RFEDA_UPD);
1804 Inst.setOpcode(ARM::RFEDB);
1806 case ARM::LDMDB_UPD:
1807 Inst.setOpcode(ARM::RFEDB_UPD);
1810 Inst.setOpcode(ARM::RFEIA);
1812 case ARM::LDMIA_UPD:
1813 Inst.setOpcode(ARM::RFEIA_UPD);
1816 Inst.setOpcode(ARM::RFEIB);
1818 case ARM::LDMIB_UPD:
1819 Inst.setOpcode(ARM::RFEIB_UPD);
1822 Inst.setOpcode(ARM::SRSDA);
1824 case ARM::STMDA_UPD:
1825 Inst.setOpcode(ARM::SRSDA_UPD);
1828 Inst.setOpcode(ARM::SRSDB);
1830 case ARM::STMDB_UPD:
1831 Inst.setOpcode(ARM::SRSDB_UPD);
1834 Inst.setOpcode(ARM::SRSIA);
1836 case ARM::STMIA_UPD:
1837 Inst.setOpcode(ARM::SRSIA_UPD);
1840 Inst.setOpcode(ARM::SRSIB);
1842 case ARM::STMIB_UPD:
1843 Inst.setOpcode(ARM::SRSIB_UPD);
1846 return MCDisassembler::Fail;
1849 // For stores (which become SRS's, the only operand is the mode.
1850 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1851 // Check SRS encoding constraints
1852 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1853 fieldFromInstruction(Insn, 20, 1) == 0))
1854 return MCDisassembler::Fail;
1857 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1861 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1865 return MCDisassembler::Fail;
1866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1867 return MCDisassembler::Fail; // Tied
1868 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1869 return MCDisassembler::Fail;
1870 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1871 return MCDisassembler::Fail;
1876 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1877 uint64_t Address, const void *Decoder) {
1878 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1879 unsigned M = fieldFromInstruction(Insn, 17, 1);
1880 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1881 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1883 DecodeStatus S = MCDisassembler::Success;
1885 // This decoder is called from multiple location that do not check
1886 // the full encoding is valid before they do.
1887 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1888 fieldFromInstruction(Insn, 16, 1) != 0 ||
1889 fieldFromInstruction(Insn, 20, 8) != 0x10)
1890 return MCDisassembler::Fail;
1892 // imod == '01' --> UNPREDICTABLE
1893 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1894 // return failure here. The '01' imod value is unprintable, so there's
1895 // nothing useful we could do even if we returned UNPREDICTABLE.
1897 if (imod == 1) return MCDisassembler::Fail;
1900 Inst.setOpcode(ARM::CPS3p);
1901 Inst.addOperand(MCOperand::CreateImm(imod));
1902 Inst.addOperand(MCOperand::CreateImm(iflags));
1903 Inst.addOperand(MCOperand::CreateImm(mode));
1904 } else if (imod && !M) {
1905 Inst.setOpcode(ARM::CPS2p);
1906 Inst.addOperand(MCOperand::CreateImm(imod));
1907 Inst.addOperand(MCOperand::CreateImm(iflags));
1908 if (mode) S = MCDisassembler::SoftFail;
1909 } else if (!imod && M) {
1910 Inst.setOpcode(ARM::CPS1p);
1911 Inst.addOperand(MCOperand::CreateImm(mode));
1912 if (iflags) S = MCDisassembler::SoftFail;
1914 // imod == '00' && M == '0' --> UNPREDICTABLE
1915 Inst.setOpcode(ARM::CPS1p);
1916 Inst.addOperand(MCOperand::CreateImm(mode));
1917 S = MCDisassembler::SoftFail;
1923 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1924 uint64_t Address, const void *Decoder) {
1925 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1926 unsigned M = fieldFromInstruction(Insn, 8, 1);
1927 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1928 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1930 DecodeStatus S = MCDisassembler::Success;
1932 // imod == '01' --> UNPREDICTABLE
1933 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1934 // return failure here. The '01' imod value is unprintable, so there's
1935 // nothing useful we could do even if we returned UNPREDICTABLE.
1937 if (imod == 1) return MCDisassembler::Fail;
1940 Inst.setOpcode(ARM::t2CPS3p);
1941 Inst.addOperand(MCOperand::CreateImm(imod));
1942 Inst.addOperand(MCOperand::CreateImm(iflags));
1943 Inst.addOperand(MCOperand::CreateImm(mode));
1944 } else if (imod && !M) {
1945 Inst.setOpcode(ARM::t2CPS2p);
1946 Inst.addOperand(MCOperand::CreateImm(imod));
1947 Inst.addOperand(MCOperand::CreateImm(iflags));
1948 if (mode) S = MCDisassembler::SoftFail;
1949 } else if (!imod && M) {
1950 Inst.setOpcode(ARM::t2CPS1p);
1951 Inst.addOperand(MCOperand::CreateImm(mode));
1952 if (iflags) S = MCDisassembler::SoftFail;
1954 // imod == '00' && M == '0' --> this is a HINT instruction
1955 int imm = fieldFromInstruction(Insn, 0, 8);
1956 // HINT are defined only for immediate in [0..4]
1957 if(imm > 4) return MCDisassembler::Fail;
1958 Inst.setOpcode(ARM::t2HINT);
1959 Inst.addOperand(MCOperand::CreateImm(imm));
1965 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
1966 uint64_t Address, const void *Decoder) {
1967 DecodeStatus S = MCDisassembler::Success;
1969 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
1972 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
1973 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
1974 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
1975 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
1977 if (Inst.getOpcode() == ARM::t2MOVTi16)
1978 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1979 return MCDisassembler::Fail;
1980 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1981 return MCDisassembler::Fail;
1983 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1984 Inst.addOperand(MCOperand::CreateImm(imm));
1989 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
1990 uint64_t Address, const void *Decoder) {
1991 DecodeStatus S = MCDisassembler::Success;
1993 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1994 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1997 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
1998 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2000 if (Inst.getOpcode() == ARM::MOVTi16)
2001 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2002 return MCDisassembler::Fail;
2004 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2005 return MCDisassembler::Fail;
2007 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2008 Inst.addOperand(MCOperand::CreateImm(imm));
2010 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2011 return MCDisassembler::Fail;
2016 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2017 uint64_t Address, const void *Decoder) {
2018 DecodeStatus S = MCDisassembler::Success;
2020 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2021 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2022 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2023 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2024 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2027 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2029 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2030 return MCDisassembler::Fail;
2031 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2032 return MCDisassembler::Fail;
2033 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2034 return MCDisassembler::Fail;
2035 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2036 return MCDisassembler::Fail;
2038 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2039 return MCDisassembler::Fail;
2044 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2045 uint64_t Address, const void *Decoder) {
2046 DecodeStatus S = MCDisassembler::Success;
2048 unsigned add = fieldFromInstruction(Val, 12, 1);
2049 unsigned imm = fieldFromInstruction(Val, 0, 12);
2050 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2052 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2053 return MCDisassembler::Fail;
2055 if (!add) imm *= -1;
2056 if (imm == 0 && !add) imm = INT32_MIN;
2057 Inst.addOperand(MCOperand::CreateImm(imm));
2059 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2064 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2065 uint64_t Address, const void *Decoder) {
2066 DecodeStatus S = MCDisassembler::Success;
2068 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2069 unsigned U = fieldFromInstruction(Val, 8, 1);
2070 unsigned imm = fieldFromInstruction(Val, 0, 8);
2072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2073 return MCDisassembler::Fail;
2076 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2078 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2083 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2084 uint64_t Address, const void *Decoder) {
2085 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2089 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2090 uint64_t Address, const void *Decoder) {
2091 DecodeStatus Status = MCDisassembler::Success;
2093 // Note the J1 and J2 values are from the encoded instruction. So here
2094 // change them to I1 and I2 values via as documented:
2095 // I1 = NOT(J1 EOR S);
2096 // I2 = NOT(J2 EOR S);
2097 // and build the imm32 with one trailing zero as documented:
2098 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2099 unsigned S = fieldFromInstruction(Insn, 26, 1);
2100 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2101 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2102 unsigned I1 = !(J1 ^ S);
2103 unsigned I2 = !(J2 ^ S);
2104 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2105 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2106 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2107 int imm32 = SignExtend32<25>(tmp << 1);
2108 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2109 true, 4, Inst, Decoder))
2110 Inst.addOperand(MCOperand::CreateImm(imm32));
2116 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2117 uint64_t Address, const void *Decoder) {
2118 DecodeStatus S = MCDisassembler::Success;
2120 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2121 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2124 Inst.setOpcode(ARM::BLXi);
2125 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2126 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2127 true, 4, Inst, Decoder))
2128 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2132 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2133 true, 4, Inst, Decoder))
2134 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2135 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2136 return MCDisassembler::Fail;
2142 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2143 uint64_t Address, const void *Decoder) {
2144 DecodeStatus S = MCDisassembler::Success;
2146 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2147 unsigned align = fieldFromInstruction(Val, 4, 2);
2149 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2150 return MCDisassembler::Fail;
2152 Inst.addOperand(MCOperand::CreateImm(0));
2154 Inst.addOperand(MCOperand::CreateImm(4 << align));
2159 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2160 uint64_t Address, const void *Decoder) {
2161 DecodeStatus S = MCDisassembler::Success;
2163 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2164 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2165 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2166 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2167 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2168 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2170 // First output register
2171 switch (Inst.getOpcode()) {
2172 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2173 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2174 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2175 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2176 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2177 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2178 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2179 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2180 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2181 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2182 return MCDisassembler::Fail;
2187 case ARM::VLD2b16wb_fixed:
2188 case ARM::VLD2b16wb_register:
2189 case ARM::VLD2b32wb_fixed:
2190 case ARM::VLD2b32wb_register:
2191 case ARM::VLD2b8wb_fixed:
2192 case ARM::VLD2b8wb_register:
2193 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2194 return MCDisassembler::Fail;
2197 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2198 return MCDisassembler::Fail;
2201 // Second output register
2202 switch (Inst.getOpcode()) {
2206 case ARM::VLD3d8_UPD:
2207 case ARM::VLD3d16_UPD:
2208 case ARM::VLD3d32_UPD:
2212 case ARM::VLD4d8_UPD:
2213 case ARM::VLD4d16_UPD:
2214 case ARM::VLD4d32_UPD:
2215 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2216 return MCDisassembler::Fail;
2221 case ARM::VLD3q8_UPD:
2222 case ARM::VLD3q16_UPD:
2223 case ARM::VLD3q32_UPD:
2227 case ARM::VLD4q8_UPD:
2228 case ARM::VLD4q16_UPD:
2229 case ARM::VLD4q32_UPD:
2230 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2231 return MCDisassembler::Fail;
2236 // Third output register
2237 switch(Inst.getOpcode()) {
2241 case ARM::VLD3d8_UPD:
2242 case ARM::VLD3d16_UPD:
2243 case ARM::VLD3d32_UPD:
2247 case ARM::VLD4d8_UPD:
2248 case ARM::VLD4d16_UPD:
2249 case ARM::VLD4d32_UPD:
2250 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2251 return MCDisassembler::Fail;
2256 case ARM::VLD3q8_UPD:
2257 case ARM::VLD3q16_UPD:
2258 case ARM::VLD3q32_UPD:
2262 case ARM::VLD4q8_UPD:
2263 case ARM::VLD4q16_UPD:
2264 case ARM::VLD4q32_UPD:
2265 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2266 return MCDisassembler::Fail;
2272 // Fourth output register
2273 switch (Inst.getOpcode()) {
2277 case ARM::VLD4d8_UPD:
2278 case ARM::VLD4d16_UPD:
2279 case ARM::VLD4d32_UPD:
2280 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2281 return MCDisassembler::Fail;
2286 case ARM::VLD4q8_UPD:
2287 case ARM::VLD4q16_UPD:
2288 case ARM::VLD4q32_UPD:
2289 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2290 return MCDisassembler::Fail;
2296 // Writeback operand
2297 switch (Inst.getOpcode()) {
2298 case ARM::VLD1d8wb_fixed:
2299 case ARM::VLD1d16wb_fixed:
2300 case ARM::VLD1d32wb_fixed:
2301 case ARM::VLD1d64wb_fixed:
2302 case ARM::VLD1d8wb_register:
2303 case ARM::VLD1d16wb_register:
2304 case ARM::VLD1d32wb_register:
2305 case ARM::VLD1d64wb_register:
2306 case ARM::VLD1q8wb_fixed:
2307 case ARM::VLD1q16wb_fixed:
2308 case ARM::VLD1q32wb_fixed:
2309 case ARM::VLD1q64wb_fixed:
2310 case ARM::VLD1q8wb_register:
2311 case ARM::VLD1q16wb_register:
2312 case ARM::VLD1q32wb_register:
2313 case ARM::VLD1q64wb_register:
2314 case ARM::VLD1d8Twb_fixed:
2315 case ARM::VLD1d8Twb_register:
2316 case ARM::VLD1d16Twb_fixed:
2317 case ARM::VLD1d16Twb_register:
2318 case ARM::VLD1d32Twb_fixed:
2319 case ARM::VLD1d32Twb_register:
2320 case ARM::VLD1d64Twb_fixed:
2321 case ARM::VLD1d64Twb_register:
2322 case ARM::VLD1d8Qwb_fixed:
2323 case ARM::VLD1d8Qwb_register:
2324 case ARM::VLD1d16Qwb_fixed:
2325 case ARM::VLD1d16Qwb_register:
2326 case ARM::VLD1d32Qwb_fixed:
2327 case ARM::VLD1d32Qwb_register:
2328 case ARM::VLD1d64Qwb_fixed:
2329 case ARM::VLD1d64Qwb_register:
2330 case ARM::VLD2d8wb_fixed:
2331 case ARM::VLD2d16wb_fixed:
2332 case ARM::VLD2d32wb_fixed:
2333 case ARM::VLD2q8wb_fixed:
2334 case ARM::VLD2q16wb_fixed:
2335 case ARM::VLD2q32wb_fixed:
2336 case ARM::VLD2d8wb_register:
2337 case ARM::VLD2d16wb_register:
2338 case ARM::VLD2d32wb_register:
2339 case ARM::VLD2q8wb_register:
2340 case ARM::VLD2q16wb_register:
2341 case ARM::VLD2q32wb_register:
2342 case ARM::VLD2b8wb_fixed:
2343 case ARM::VLD2b16wb_fixed:
2344 case ARM::VLD2b32wb_fixed:
2345 case ARM::VLD2b8wb_register:
2346 case ARM::VLD2b16wb_register:
2347 case ARM::VLD2b32wb_register:
2348 Inst.addOperand(MCOperand::CreateImm(0));
2350 case ARM::VLD3d8_UPD:
2351 case ARM::VLD3d16_UPD:
2352 case ARM::VLD3d32_UPD:
2353 case ARM::VLD3q8_UPD:
2354 case ARM::VLD3q16_UPD:
2355 case ARM::VLD3q32_UPD:
2356 case ARM::VLD4d8_UPD:
2357 case ARM::VLD4d16_UPD:
2358 case ARM::VLD4d32_UPD:
2359 case ARM::VLD4q8_UPD:
2360 case ARM::VLD4q16_UPD:
2361 case ARM::VLD4q32_UPD:
2362 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2363 return MCDisassembler::Fail;
2369 // AddrMode6 Base (register+alignment)
2370 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2371 return MCDisassembler::Fail;
2373 // AddrMode6 Offset (register)
2374 switch (Inst.getOpcode()) {
2376 // The below have been updated to have explicit am6offset split
2377 // between fixed and register offset. For those instructions not
2378 // yet updated, we need to add an additional reg0 operand for the
2381 // The fixed offset encodes as Rm == 0xd, so we check for that.
2383 Inst.addOperand(MCOperand::CreateReg(0));
2386 // Fall through to handle the register offset variant.
2387 case ARM::VLD1d8wb_fixed:
2388 case ARM::VLD1d16wb_fixed:
2389 case ARM::VLD1d32wb_fixed:
2390 case ARM::VLD1d64wb_fixed:
2391 case ARM::VLD1d8Twb_fixed:
2392 case ARM::VLD1d16Twb_fixed:
2393 case ARM::VLD1d32Twb_fixed:
2394 case ARM::VLD1d64Twb_fixed:
2395 case ARM::VLD1d8Qwb_fixed:
2396 case ARM::VLD1d16Qwb_fixed:
2397 case ARM::VLD1d32Qwb_fixed:
2398 case ARM::VLD1d64Qwb_fixed:
2399 case ARM::VLD1d8wb_register:
2400 case ARM::VLD1d16wb_register:
2401 case ARM::VLD1d32wb_register:
2402 case ARM::VLD1d64wb_register:
2403 case ARM::VLD1q8wb_fixed:
2404 case ARM::VLD1q16wb_fixed:
2405 case ARM::VLD1q32wb_fixed:
2406 case ARM::VLD1q64wb_fixed:
2407 case ARM::VLD1q8wb_register:
2408 case ARM::VLD1q16wb_register:
2409 case ARM::VLD1q32wb_register:
2410 case ARM::VLD1q64wb_register:
2411 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2412 // variant encodes Rm == 0xf. Anything else is a register offset post-
2413 // increment and we need to add the register operand to the instruction.
2414 if (Rm != 0xD && Rm != 0xF &&
2415 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2416 return MCDisassembler::Fail;
2418 case ARM::VLD2d8wb_fixed:
2419 case ARM::VLD2d16wb_fixed:
2420 case ARM::VLD2d32wb_fixed:
2421 case ARM::VLD2b8wb_fixed:
2422 case ARM::VLD2b16wb_fixed:
2423 case ARM::VLD2b32wb_fixed:
2424 case ARM::VLD2q8wb_fixed:
2425 case ARM::VLD2q16wb_fixed:
2426 case ARM::VLD2q32wb_fixed:
2433 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2434 uint64_t Address, const void *Decoder) {
2435 unsigned type = fieldFromInstruction(Insn, 8, 4);
2436 unsigned align = fieldFromInstruction(Insn, 4, 2);
2437 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2438 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2439 if (type == 10 && align == 3) return MCDisassembler::Fail;
2441 unsigned load = fieldFromInstruction(Insn, 21, 1);
2442 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2443 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2446 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2447 uint64_t Address, const void *Decoder) {
2448 unsigned size = fieldFromInstruction(Insn, 6, 2);
2449 if (size == 3) return MCDisassembler::Fail;
2451 unsigned type = fieldFromInstruction(Insn, 8, 4);
2452 unsigned align = fieldFromInstruction(Insn, 4, 2);
2453 if (type == 8 && align == 3) return MCDisassembler::Fail;
2454 if (type == 9 && align == 3) return MCDisassembler::Fail;
2456 unsigned load = fieldFromInstruction(Insn, 21, 1);
2457 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2458 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2461 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2462 uint64_t Address, const void *Decoder) {
2463 unsigned size = fieldFromInstruction(Insn, 6, 2);
2464 if (size == 3) return MCDisassembler::Fail;
2466 unsigned align = fieldFromInstruction(Insn, 4, 2);
2467 if (align & 2) return MCDisassembler::Fail;
2469 unsigned load = fieldFromInstruction(Insn, 21, 1);
2470 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2471 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2474 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2475 uint64_t Address, const void *Decoder) {
2476 unsigned size = fieldFromInstruction(Insn, 6, 2);
2477 if (size == 3) return MCDisassembler::Fail;
2479 unsigned load = fieldFromInstruction(Insn, 21, 1);
2480 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2481 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2484 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2485 uint64_t Address, const void *Decoder) {
2486 DecodeStatus S = MCDisassembler::Success;
2488 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2489 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2490 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2491 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2492 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2493 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2495 // Writeback Operand
2496 switch (Inst.getOpcode()) {
2497 case ARM::VST1d8wb_fixed:
2498 case ARM::VST1d16wb_fixed:
2499 case ARM::VST1d32wb_fixed:
2500 case ARM::VST1d64wb_fixed:
2501 case ARM::VST1d8wb_register:
2502 case ARM::VST1d16wb_register:
2503 case ARM::VST1d32wb_register:
2504 case ARM::VST1d64wb_register:
2505 case ARM::VST1q8wb_fixed:
2506 case ARM::VST1q16wb_fixed:
2507 case ARM::VST1q32wb_fixed:
2508 case ARM::VST1q64wb_fixed:
2509 case ARM::VST1q8wb_register:
2510 case ARM::VST1q16wb_register:
2511 case ARM::VST1q32wb_register:
2512 case ARM::VST1q64wb_register:
2513 case ARM::VST1d8Twb_fixed:
2514 case ARM::VST1d16Twb_fixed:
2515 case ARM::VST1d32Twb_fixed:
2516 case ARM::VST1d64Twb_fixed:
2517 case ARM::VST1d8Twb_register:
2518 case ARM::VST1d16Twb_register:
2519 case ARM::VST1d32Twb_register:
2520 case ARM::VST1d64Twb_register:
2521 case ARM::VST1d8Qwb_fixed:
2522 case ARM::VST1d16Qwb_fixed:
2523 case ARM::VST1d32Qwb_fixed:
2524 case ARM::VST1d64Qwb_fixed:
2525 case ARM::VST1d8Qwb_register:
2526 case ARM::VST1d16Qwb_register:
2527 case ARM::VST1d32Qwb_register:
2528 case ARM::VST1d64Qwb_register:
2529 case ARM::VST2d8wb_fixed:
2530 case ARM::VST2d16wb_fixed:
2531 case ARM::VST2d32wb_fixed:
2532 case ARM::VST2d8wb_register:
2533 case ARM::VST2d16wb_register:
2534 case ARM::VST2d32wb_register:
2535 case ARM::VST2q8wb_fixed:
2536 case ARM::VST2q16wb_fixed:
2537 case ARM::VST2q32wb_fixed:
2538 case ARM::VST2q8wb_register:
2539 case ARM::VST2q16wb_register:
2540 case ARM::VST2q32wb_register:
2541 case ARM::VST2b8wb_fixed:
2542 case ARM::VST2b16wb_fixed:
2543 case ARM::VST2b32wb_fixed:
2544 case ARM::VST2b8wb_register:
2545 case ARM::VST2b16wb_register:
2546 case ARM::VST2b32wb_register:
2548 return MCDisassembler::Fail;
2549 Inst.addOperand(MCOperand::CreateImm(0));
2551 case ARM::VST3d8_UPD:
2552 case ARM::VST3d16_UPD:
2553 case ARM::VST3d32_UPD:
2554 case ARM::VST3q8_UPD:
2555 case ARM::VST3q16_UPD:
2556 case ARM::VST3q32_UPD:
2557 case ARM::VST4d8_UPD:
2558 case ARM::VST4d16_UPD:
2559 case ARM::VST4d32_UPD:
2560 case ARM::VST4q8_UPD:
2561 case ARM::VST4q16_UPD:
2562 case ARM::VST4q32_UPD:
2563 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2564 return MCDisassembler::Fail;
2570 // AddrMode6 Base (register+alignment)
2571 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2572 return MCDisassembler::Fail;
2574 // AddrMode6 Offset (register)
2575 switch (Inst.getOpcode()) {
2578 Inst.addOperand(MCOperand::CreateReg(0));
2579 else if (Rm != 0xF) {
2580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2581 return MCDisassembler::Fail;
2584 case ARM::VST1d8wb_fixed:
2585 case ARM::VST1d16wb_fixed:
2586 case ARM::VST1d32wb_fixed:
2587 case ARM::VST1d64wb_fixed:
2588 case ARM::VST1q8wb_fixed:
2589 case ARM::VST1q16wb_fixed:
2590 case ARM::VST1q32wb_fixed:
2591 case ARM::VST1q64wb_fixed:
2592 case ARM::VST1d8Twb_fixed:
2593 case ARM::VST1d16Twb_fixed:
2594 case ARM::VST1d32Twb_fixed:
2595 case ARM::VST1d64Twb_fixed:
2596 case ARM::VST1d8Qwb_fixed:
2597 case ARM::VST1d16Qwb_fixed:
2598 case ARM::VST1d32Qwb_fixed:
2599 case ARM::VST1d64Qwb_fixed:
2600 case ARM::VST2d8wb_fixed:
2601 case ARM::VST2d16wb_fixed:
2602 case ARM::VST2d32wb_fixed:
2603 case ARM::VST2q8wb_fixed:
2604 case ARM::VST2q16wb_fixed:
2605 case ARM::VST2q32wb_fixed:
2606 case ARM::VST2b8wb_fixed:
2607 case ARM::VST2b16wb_fixed:
2608 case ARM::VST2b32wb_fixed:
2613 // First input register
2614 switch (Inst.getOpcode()) {
2619 case ARM::VST1q16wb_fixed:
2620 case ARM::VST1q16wb_register:
2621 case ARM::VST1q32wb_fixed:
2622 case ARM::VST1q32wb_register:
2623 case ARM::VST1q64wb_fixed:
2624 case ARM::VST1q64wb_register:
2625 case ARM::VST1q8wb_fixed:
2626 case ARM::VST1q8wb_register:
2630 case ARM::VST2d16wb_fixed:
2631 case ARM::VST2d16wb_register:
2632 case ARM::VST2d32wb_fixed:
2633 case ARM::VST2d32wb_register:
2634 case ARM::VST2d8wb_fixed:
2635 case ARM::VST2d8wb_register:
2636 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2637 return MCDisassembler::Fail;
2642 case ARM::VST2b16wb_fixed:
2643 case ARM::VST2b16wb_register:
2644 case ARM::VST2b32wb_fixed:
2645 case ARM::VST2b32wb_register:
2646 case ARM::VST2b8wb_fixed:
2647 case ARM::VST2b8wb_register:
2648 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2649 return MCDisassembler::Fail;
2652 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2653 return MCDisassembler::Fail;
2656 // Second input register
2657 switch (Inst.getOpcode()) {
2661 case ARM::VST3d8_UPD:
2662 case ARM::VST3d16_UPD:
2663 case ARM::VST3d32_UPD:
2667 case ARM::VST4d8_UPD:
2668 case ARM::VST4d16_UPD:
2669 case ARM::VST4d32_UPD:
2670 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2671 return MCDisassembler::Fail;
2676 case ARM::VST3q8_UPD:
2677 case ARM::VST3q16_UPD:
2678 case ARM::VST3q32_UPD:
2682 case ARM::VST4q8_UPD:
2683 case ARM::VST4q16_UPD:
2684 case ARM::VST4q32_UPD:
2685 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2686 return MCDisassembler::Fail;
2692 // Third input register
2693 switch (Inst.getOpcode()) {
2697 case ARM::VST3d8_UPD:
2698 case ARM::VST3d16_UPD:
2699 case ARM::VST3d32_UPD:
2703 case ARM::VST4d8_UPD:
2704 case ARM::VST4d16_UPD:
2705 case ARM::VST4d32_UPD:
2706 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2707 return MCDisassembler::Fail;
2712 case ARM::VST3q8_UPD:
2713 case ARM::VST3q16_UPD:
2714 case ARM::VST3q32_UPD:
2718 case ARM::VST4q8_UPD:
2719 case ARM::VST4q16_UPD:
2720 case ARM::VST4q32_UPD:
2721 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2722 return MCDisassembler::Fail;
2728 // Fourth input register
2729 switch (Inst.getOpcode()) {
2733 case ARM::VST4d8_UPD:
2734 case ARM::VST4d16_UPD:
2735 case ARM::VST4d32_UPD:
2736 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2737 return MCDisassembler::Fail;
2742 case ARM::VST4q8_UPD:
2743 case ARM::VST4q16_UPD:
2744 case ARM::VST4q32_UPD:
2745 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2746 return MCDisassembler::Fail;
2755 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2756 uint64_t Address, const void *Decoder) {
2757 DecodeStatus S = MCDisassembler::Success;
2759 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2760 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2761 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2762 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2763 unsigned align = fieldFromInstruction(Insn, 4, 1);
2764 unsigned size = fieldFromInstruction(Insn, 6, 2);
2766 if (size == 0 && align == 1)
2767 return MCDisassembler::Fail;
2768 align *= (1 << size);
2770 switch (Inst.getOpcode()) {
2771 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2772 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2773 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2774 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2775 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2776 return MCDisassembler::Fail;
2779 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2780 return MCDisassembler::Fail;
2784 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2785 return MCDisassembler::Fail;
2788 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2789 return MCDisassembler::Fail;
2790 Inst.addOperand(MCOperand::CreateImm(align));
2792 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2793 // variant encodes Rm == 0xf. Anything else is a register offset post-
2794 // increment and we need to add the register operand to the instruction.
2795 if (Rm != 0xD && Rm != 0xF &&
2796 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2797 return MCDisassembler::Fail;
2802 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2803 uint64_t Address, const void *Decoder) {
2804 DecodeStatus S = MCDisassembler::Success;
2806 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2807 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2808 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2809 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2810 unsigned align = fieldFromInstruction(Insn, 4, 1);
2811 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2814 switch (Inst.getOpcode()) {
2815 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2816 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2817 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2818 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2819 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2820 return MCDisassembler::Fail;
2822 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2823 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2824 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2825 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2826 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2827 return MCDisassembler::Fail;
2830 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2831 return MCDisassembler::Fail;
2836 Inst.addOperand(MCOperand::CreateImm(0));
2838 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2839 return MCDisassembler::Fail;
2840 Inst.addOperand(MCOperand::CreateImm(align));
2842 if (Rm != 0xD && Rm != 0xF) {
2843 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2844 return MCDisassembler::Fail;
2850 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2851 uint64_t Address, const void *Decoder) {
2852 DecodeStatus S = MCDisassembler::Success;
2854 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2855 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2856 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2857 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2858 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2860 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2861 return MCDisassembler::Fail;
2862 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2863 return MCDisassembler::Fail;
2864 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2865 return MCDisassembler::Fail;
2867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2868 return MCDisassembler::Fail;
2871 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2872 return MCDisassembler::Fail;
2873 Inst.addOperand(MCOperand::CreateImm(0));
2876 Inst.addOperand(MCOperand::CreateReg(0));
2877 else if (Rm != 0xF) {
2878 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2879 return MCDisassembler::Fail;
2885 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2886 uint64_t Address, const void *Decoder) {
2887 DecodeStatus S = MCDisassembler::Success;
2889 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2890 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2891 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2892 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2893 unsigned size = fieldFromInstruction(Insn, 6, 2);
2894 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2895 unsigned align = fieldFromInstruction(Insn, 4, 1);
2899 return MCDisassembler::Fail;
2912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2913 return MCDisassembler::Fail;
2914 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2915 return MCDisassembler::Fail;
2916 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2917 return MCDisassembler::Fail;
2918 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2919 return MCDisassembler::Fail;
2921 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2922 return MCDisassembler::Fail;
2925 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2926 return MCDisassembler::Fail;
2927 Inst.addOperand(MCOperand::CreateImm(align));
2930 Inst.addOperand(MCOperand::CreateReg(0));
2931 else if (Rm != 0xF) {
2932 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2933 return MCDisassembler::Fail;
2940 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
2941 uint64_t Address, const void *Decoder) {
2942 DecodeStatus S = MCDisassembler::Success;
2944 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2945 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2946 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2947 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2948 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
2949 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
2950 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2951 unsigned Q = fieldFromInstruction(Insn, 6, 1);
2954 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2955 return MCDisassembler::Fail;
2957 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2958 return MCDisassembler::Fail;
2961 Inst.addOperand(MCOperand::CreateImm(imm));
2963 switch (Inst.getOpcode()) {
2964 case ARM::VORRiv4i16:
2965 case ARM::VORRiv2i32:
2966 case ARM::VBICiv4i16:
2967 case ARM::VBICiv2i32:
2968 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2969 return MCDisassembler::Fail;
2971 case ARM::VORRiv8i16:
2972 case ARM::VORRiv4i32:
2973 case ARM::VBICiv8i16:
2974 case ARM::VBICiv4i32:
2975 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2976 return MCDisassembler::Fail;
2985 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
2986 uint64_t Address, const void *Decoder) {
2987 DecodeStatus S = MCDisassembler::Success;
2989 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2990 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2991 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2992 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2993 unsigned size = fieldFromInstruction(Insn, 18, 2);
2995 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2996 return MCDisassembler::Fail;
2997 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2998 return MCDisassembler::Fail;
2999 Inst.addOperand(MCOperand::CreateImm(8 << size));
3004 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3005 uint64_t Address, const void *Decoder) {
3006 Inst.addOperand(MCOperand::CreateImm(8 - Val));
3007 return MCDisassembler::Success;
3010 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3011 uint64_t Address, const void *Decoder) {
3012 Inst.addOperand(MCOperand::CreateImm(16 - Val));
3013 return MCDisassembler::Success;
3016 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3017 uint64_t Address, const void *Decoder) {
3018 Inst.addOperand(MCOperand::CreateImm(32 - Val));
3019 return MCDisassembler::Success;
3022 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3023 uint64_t Address, const void *Decoder) {
3024 Inst.addOperand(MCOperand::CreateImm(64 - Val));
3025 return MCDisassembler::Success;
3028 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3029 uint64_t Address, const void *Decoder) {
3030 DecodeStatus S = MCDisassembler::Success;
3032 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3033 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3034 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3035 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3036 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3037 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3038 unsigned op = fieldFromInstruction(Insn, 6, 1);
3040 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3041 return MCDisassembler::Fail;
3043 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3044 return MCDisassembler::Fail; // Writeback
3047 switch (Inst.getOpcode()) {
3050 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3051 return MCDisassembler::Fail;
3054 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3055 return MCDisassembler::Fail;
3058 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3059 return MCDisassembler::Fail;
3064 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3065 uint64_t Address, const void *Decoder) {
3066 DecodeStatus S = MCDisassembler::Success;
3068 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3069 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3071 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3072 return MCDisassembler::Fail;
3074 switch(Inst.getOpcode()) {
3076 return MCDisassembler::Fail;
3078 break; // tADR does not explicitly represent the PC as an operand.
3080 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3084 Inst.addOperand(MCOperand::CreateImm(imm));
3088 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3089 uint64_t Address, const void *Decoder) {
3090 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3091 true, 2, Inst, Decoder))
3092 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3093 return MCDisassembler::Success;
3096 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3097 uint64_t Address, const void *Decoder) {
3098 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3099 true, 4, Inst, Decoder))
3100 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3101 return MCDisassembler::Success;
3104 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3105 uint64_t Address, const void *Decoder) {
3106 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3107 true, 2, Inst, Decoder))
3108 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3109 return MCDisassembler::Success;
3112 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3113 uint64_t Address, const void *Decoder) {
3114 DecodeStatus S = MCDisassembler::Success;
3116 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3117 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3119 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3120 return MCDisassembler::Fail;
3121 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3122 return MCDisassembler::Fail;
3127 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3128 uint64_t Address, const void *Decoder) {
3129 DecodeStatus S = MCDisassembler::Success;
3131 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3132 unsigned imm = fieldFromInstruction(Val, 3, 5);
3134 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3135 return MCDisassembler::Fail;
3136 Inst.addOperand(MCOperand::CreateImm(imm));
3141 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3142 uint64_t Address, const void *Decoder) {
3143 unsigned imm = Val << 2;
3145 Inst.addOperand(MCOperand::CreateImm(imm));
3146 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3148 return MCDisassembler::Success;
3151 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3152 uint64_t Address, const void *Decoder) {
3153 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3154 Inst.addOperand(MCOperand::CreateImm(Val));
3156 return MCDisassembler::Success;
3159 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3160 uint64_t Address, const void *Decoder) {
3161 DecodeStatus S = MCDisassembler::Success;
3163 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3164 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3165 unsigned imm = fieldFromInstruction(Val, 0, 2);
3167 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3168 return MCDisassembler::Fail;
3169 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3170 return MCDisassembler::Fail;
3171 Inst.addOperand(MCOperand::CreateImm(imm));
3176 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3177 uint64_t Address, const void *Decoder) {
3178 DecodeStatus S = MCDisassembler::Success;
3180 switch (Inst.getOpcode()) {
3186 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3187 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3188 return MCDisassembler::Fail;
3192 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3194 switch (Inst.getOpcode()) {
3196 Inst.setOpcode(ARM::t2LDRBpci);
3199 Inst.setOpcode(ARM::t2LDRHpci);
3202 Inst.setOpcode(ARM::t2LDRSHpci);
3205 Inst.setOpcode(ARM::t2LDRSBpci);
3208 Inst.setOpcode(ARM::t2PLDi12);
3209 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3212 return MCDisassembler::Fail;
3215 int imm = fieldFromInstruction(Insn, 0, 12);
3216 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
3217 Inst.addOperand(MCOperand::CreateImm(imm));
3222 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3223 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3224 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3225 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3226 return MCDisassembler::Fail;
3231 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3232 uint64_t Address, const void *Decoder) {
3234 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3236 int imm = Val & 0xFF;
3238 if (!(Val & 0x100)) imm *= -1;
3239 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3242 return MCDisassembler::Success;
3245 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3246 uint64_t Address, const void *Decoder) {
3247 DecodeStatus S = MCDisassembler::Success;
3249 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3250 unsigned imm = fieldFromInstruction(Val, 0, 9);
3252 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3253 return MCDisassembler::Fail;
3254 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3255 return MCDisassembler::Fail;
3260 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3261 uint64_t Address, const void *Decoder) {
3262 DecodeStatus S = MCDisassembler::Success;
3264 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3265 unsigned imm = fieldFromInstruction(Val, 0, 8);
3267 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3268 return MCDisassembler::Fail;
3270 Inst.addOperand(MCOperand::CreateImm(imm));
3275 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3276 uint64_t Address, const void *Decoder) {
3277 int imm = Val & 0xFF;
3280 else if (!(Val & 0x100))
3282 Inst.addOperand(MCOperand::CreateImm(imm));
3284 return MCDisassembler::Success;
3288 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3289 uint64_t Address, const void *Decoder) {
3290 DecodeStatus S = MCDisassembler::Success;
3292 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3293 unsigned imm = fieldFromInstruction(Val, 0, 9);
3295 // Some instructions always use an additive offset.
3296 switch (Inst.getOpcode()) {
3311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3312 return MCDisassembler::Fail;
3313 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3314 return MCDisassembler::Fail;
3319 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3320 uint64_t Address, const void *Decoder) {
3321 DecodeStatus S = MCDisassembler::Success;
3323 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3324 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3325 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3326 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3328 unsigned load = fieldFromInstruction(Insn, 20, 1);
3331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3332 return MCDisassembler::Fail;
3335 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3336 return MCDisassembler::Fail;
3339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3340 return MCDisassembler::Fail;
3343 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3344 return MCDisassembler::Fail;
3349 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3350 uint64_t Address, const void *Decoder) {
3351 DecodeStatus S = MCDisassembler::Success;
3353 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3354 unsigned imm = fieldFromInstruction(Val, 0, 12);
3356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3357 return MCDisassembler::Fail;
3358 Inst.addOperand(MCOperand::CreateImm(imm));
3364 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3365 uint64_t Address, const void *Decoder) {
3366 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3368 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3369 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3370 Inst.addOperand(MCOperand::CreateImm(imm));
3372 return MCDisassembler::Success;
3375 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3376 uint64_t Address, const void *Decoder) {
3377 DecodeStatus S = MCDisassembler::Success;
3379 if (Inst.getOpcode() == ARM::tADDrSP) {
3380 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3381 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3384 return MCDisassembler::Fail;
3385 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3387 return MCDisassembler::Fail;
3388 } else if (Inst.getOpcode() == ARM::tADDspr) {
3389 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3391 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3392 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3393 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3394 return MCDisassembler::Fail;
3400 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3401 uint64_t Address, const void *Decoder) {
3402 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3403 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3405 Inst.addOperand(MCOperand::CreateImm(imod));
3406 Inst.addOperand(MCOperand::CreateImm(flags));
3408 return MCDisassembler::Success;
3411 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3412 uint64_t Address, const void *Decoder) {
3413 DecodeStatus S = MCDisassembler::Success;
3414 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3415 unsigned add = fieldFromInstruction(Insn, 4, 1);
3417 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3418 return MCDisassembler::Fail;
3419 Inst.addOperand(MCOperand::CreateImm(add));
3424 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3425 uint64_t Address, const void *Decoder) {
3426 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3427 // Note only one trailing zero not two. Also the J1 and J2 values are from
3428 // the encoded instruction. So here change to I1 and I2 values via:
3429 // I1 = NOT(J1 EOR S);
3430 // I2 = NOT(J2 EOR S);
3431 // and build the imm32 with two trailing zeros as documented:
3432 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3433 unsigned S = (Val >> 23) & 1;
3434 unsigned J1 = (Val >> 22) & 1;
3435 unsigned J2 = (Val >> 21) & 1;
3436 unsigned I1 = !(J1 ^ S);
3437 unsigned I2 = !(J2 ^ S);
3438 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3439 int imm32 = SignExtend32<25>(tmp << 1);
3441 if (!tryAddingSymbolicOperand(Address,
3442 (Address & ~2u) + imm32 + 4,
3443 true, 4, Inst, Decoder))
3444 Inst.addOperand(MCOperand::CreateImm(imm32));
3445 return MCDisassembler::Success;
3448 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3449 uint64_t Address, const void *Decoder) {
3450 if (Val == 0xA || Val == 0xB)
3451 return MCDisassembler::Fail;
3453 Inst.addOperand(MCOperand::CreateImm(Val));
3454 return MCDisassembler::Success;
3458 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3459 uint64_t Address, const void *Decoder) {
3460 DecodeStatus S = MCDisassembler::Success;
3462 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3463 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3465 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3467 return MCDisassembler::Fail;
3468 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3469 return MCDisassembler::Fail;
3474 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3475 uint64_t Address, const void *Decoder) {
3476 DecodeStatus S = MCDisassembler::Success;
3478 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3479 if (pred == 0xE || pred == 0xF) {
3480 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3483 return MCDisassembler::Fail;
3485 Inst.setOpcode(ARM::t2DSB);
3488 Inst.setOpcode(ARM::t2DMB);
3491 Inst.setOpcode(ARM::t2ISB);
3495 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3496 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3499 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3500 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3501 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3502 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3503 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3505 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3506 return MCDisassembler::Fail;
3507 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3508 return MCDisassembler::Fail;
3513 // Decode a shifted immediate operand. These basically consist
3514 // of an 8-bit value, and a 4-bit directive that specifies either
3515 // a splat operation or a rotation.
3516 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3517 uint64_t Address, const void *Decoder) {
3518 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3520 unsigned byte = fieldFromInstruction(Val, 8, 2);
3521 unsigned imm = fieldFromInstruction(Val, 0, 8);
3524 Inst.addOperand(MCOperand::CreateImm(imm));
3527 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3530 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3533 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3538 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3539 unsigned rot = fieldFromInstruction(Val, 7, 5);
3540 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3541 Inst.addOperand(MCOperand::CreateImm(imm));
3544 return MCDisassembler::Success;
3548 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3549 uint64_t Address, const void *Decoder){
3550 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3551 true, 2, Inst, Decoder))
3552 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
3553 return MCDisassembler::Success;
3556 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3557 uint64_t Address, const void *Decoder){
3558 // Val is passed in as S:J1:J2:imm10:imm11
3559 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3560 // the encoded instruction. So here change to I1 and I2 values via:
3561 // I1 = NOT(J1 EOR S);
3562 // I2 = NOT(J2 EOR S);
3563 // and build the imm32 with one trailing zero as documented:
3564 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3565 unsigned S = (Val >> 23) & 1;
3566 unsigned J1 = (Val >> 22) & 1;
3567 unsigned J2 = (Val >> 21) & 1;
3568 unsigned I1 = !(J1 ^ S);
3569 unsigned I2 = !(J2 ^ S);
3570 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3571 int imm32 = SignExtend32<25>(tmp << 1);
3573 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
3574 true, 4, Inst, Decoder))
3575 Inst.addOperand(MCOperand::CreateImm(imm32));
3576 return MCDisassembler::Success;
3579 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3580 uint64_t Address, const void *Decoder) {
3582 return MCDisassembler::Fail;
3584 Inst.addOperand(MCOperand::CreateImm(Val));
3585 return MCDisassembler::Success;
3588 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
3589 uint64_t Address, const void *Decoder) {
3591 return MCDisassembler::Fail;
3593 Inst.addOperand(MCOperand::CreateImm(Val));
3594 return MCDisassembler::Success;
3597 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
3598 uint64_t Address, const void *Decoder) {
3599 if (!Val) return MCDisassembler::Fail;
3600 Inst.addOperand(MCOperand::CreateImm(Val));
3601 return MCDisassembler::Success;
3604 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
3605 uint64_t Address, const void *Decoder) {
3606 DecodeStatus S = MCDisassembler::Success;
3608 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3609 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3610 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3613 S = MCDisassembler::SoftFail;
3615 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
3616 return MCDisassembler::Fail;
3617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3618 return MCDisassembler::Fail;
3619 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3620 return MCDisassembler::Fail;
3625 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
3626 uint64_t Address, const void *Decoder){
3627 DecodeStatus S = MCDisassembler::Success;
3629 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3630 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
3631 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3632 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3634 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
3635 return MCDisassembler::Fail;
3637 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
3638 S = MCDisassembler::SoftFail;
3640 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
3641 return MCDisassembler::Fail;
3642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3643 return MCDisassembler::Fail;
3644 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3645 return MCDisassembler::Fail;
3650 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
3651 uint64_t Address, const void *Decoder) {
3652 DecodeStatus S = MCDisassembler::Success;
3654 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3655 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3656 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3657 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3658 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3659 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3661 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3663 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3664 return MCDisassembler::Fail;
3665 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3666 return MCDisassembler::Fail;
3667 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3668 return MCDisassembler::Fail;
3669 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3670 return MCDisassembler::Fail;
3675 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
3676 uint64_t Address, const void *Decoder) {
3677 DecodeStatus S = MCDisassembler::Success;
3679 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3680 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3681 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3682 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3683 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3684 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3685 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3687 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3688 if (Rm == 0xF) S = MCDisassembler::SoftFail;
3690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3691 return MCDisassembler::Fail;
3692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3693 return MCDisassembler::Fail;
3694 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3695 return MCDisassembler::Fail;
3696 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3697 return MCDisassembler::Fail;
3703 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
3704 uint64_t Address, const void *Decoder) {
3705 DecodeStatus S = MCDisassembler::Success;
3707 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3708 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3709 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3710 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3711 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3712 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3714 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3716 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3717 return MCDisassembler::Fail;
3718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3719 return MCDisassembler::Fail;
3720 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3721 return MCDisassembler::Fail;
3722 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3723 return MCDisassembler::Fail;
3728 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
3729 uint64_t Address, const void *Decoder) {
3730 DecodeStatus S = MCDisassembler::Success;
3732 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3733 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3734 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3735 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3736 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3737 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3739 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3742 return MCDisassembler::Fail;
3743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3744 return MCDisassembler::Fail;
3745 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3746 return MCDisassembler::Fail;
3747 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3748 return MCDisassembler::Fail;
3753 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
3754 uint64_t Address, const void *Decoder) {
3755 DecodeStatus S = MCDisassembler::Success;
3757 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3758 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3759 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3760 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3761 unsigned size = fieldFromInstruction(Insn, 10, 2);
3767 return MCDisassembler::Fail;
3769 if (fieldFromInstruction(Insn, 4, 1))
3770 return MCDisassembler::Fail; // UNDEFINED
3771 index = fieldFromInstruction(Insn, 5, 3);
3774 if (fieldFromInstruction(Insn, 5, 1))
3775 return MCDisassembler::Fail; // UNDEFINED
3776 index = fieldFromInstruction(Insn, 6, 2);
3777 if (fieldFromInstruction(Insn, 4, 1))
3781 if (fieldFromInstruction(Insn, 6, 1))
3782 return MCDisassembler::Fail; // UNDEFINED
3783 index = fieldFromInstruction(Insn, 7, 1);
3785 switch (fieldFromInstruction(Insn, 4, 2)) {
3791 return MCDisassembler::Fail;
3796 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3797 return MCDisassembler::Fail;
3798 if (Rm != 0xF) { // Writeback
3799 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3800 return MCDisassembler::Fail;
3802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3803 return MCDisassembler::Fail;
3804 Inst.addOperand(MCOperand::CreateImm(align));
3807 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3808 return MCDisassembler::Fail;
3810 Inst.addOperand(MCOperand::CreateReg(0));
3813 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3814 return MCDisassembler::Fail;
3815 Inst.addOperand(MCOperand::CreateImm(index));
3820 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
3821 uint64_t Address, const void *Decoder) {
3822 DecodeStatus S = MCDisassembler::Success;
3824 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3825 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3826 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3827 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3828 unsigned size = fieldFromInstruction(Insn, 10, 2);
3834 return MCDisassembler::Fail;
3836 if (fieldFromInstruction(Insn, 4, 1))
3837 return MCDisassembler::Fail; // UNDEFINED
3838 index = fieldFromInstruction(Insn, 5, 3);
3841 if (fieldFromInstruction(Insn, 5, 1))
3842 return MCDisassembler::Fail; // UNDEFINED
3843 index = fieldFromInstruction(Insn, 6, 2);
3844 if (fieldFromInstruction(Insn, 4, 1))
3848 if (fieldFromInstruction(Insn, 6, 1))
3849 return MCDisassembler::Fail; // UNDEFINED
3850 index = fieldFromInstruction(Insn, 7, 1);
3852 switch (fieldFromInstruction(Insn, 4, 2)) {
3858 return MCDisassembler::Fail;
3863 if (Rm != 0xF) { // Writeback
3864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3865 return MCDisassembler::Fail;
3867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3868 return MCDisassembler::Fail;
3869 Inst.addOperand(MCOperand::CreateImm(align));
3872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3873 return MCDisassembler::Fail;
3875 Inst.addOperand(MCOperand::CreateReg(0));
3878 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3879 return MCDisassembler::Fail;
3880 Inst.addOperand(MCOperand::CreateImm(index));
3886 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
3887 uint64_t Address, const void *Decoder) {
3888 DecodeStatus S = MCDisassembler::Success;
3890 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3891 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3892 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3893 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3894 unsigned size = fieldFromInstruction(Insn, 10, 2);
3901 return MCDisassembler::Fail;
3903 index = fieldFromInstruction(Insn, 5, 3);
3904 if (fieldFromInstruction(Insn, 4, 1))
3908 index = fieldFromInstruction(Insn, 6, 2);
3909 if (fieldFromInstruction(Insn, 4, 1))
3911 if (fieldFromInstruction(Insn, 5, 1))
3915 if (fieldFromInstruction(Insn, 5, 1))
3916 return MCDisassembler::Fail; // UNDEFINED
3917 index = fieldFromInstruction(Insn, 7, 1);
3918 if (fieldFromInstruction(Insn, 4, 1) != 0)
3920 if (fieldFromInstruction(Insn, 6, 1))
3925 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3926 return MCDisassembler::Fail;
3927 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3928 return MCDisassembler::Fail;
3929 if (Rm != 0xF) { // Writeback
3930 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3931 return MCDisassembler::Fail;
3933 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3934 return MCDisassembler::Fail;
3935 Inst.addOperand(MCOperand::CreateImm(align));
3938 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3939 return MCDisassembler::Fail;
3941 Inst.addOperand(MCOperand::CreateReg(0));
3944 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3945 return MCDisassembler::Fail;
3946 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3947 return MCDisassembler::Fail;
3948 Inst.addOperand(MCOperand::CreateImm(index));
3953 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
3954 uint64_t Address, const void *Decoder) {
3955 DecodeStatus S = MCDisassembler::Success;
3957 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3958 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3959 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3960 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3961 unsigned size = fieldFromInstruction(Insn, 10, 2);
3968 return MCDisassembler::Fail;
3970 index = fieldFromInstruction(Insn, 5, 3);
3971 if (fieldFromInstruction(Insn, 4, 1))
3975 index = fieldFromInstruction(Insn, 6, 2);
3976 if (fieldFromInstruction(Insn, 4, 1))
3978 if (fieldFromInstruction(Insn, 5, 1))
3982 if (fieldFromInstruction(Insn, 5, 1))
3983 return MCDisassembler::Fail; // UNDEFINED
3984 index = fieldFromInstruction(Insn, 7, 1);
3985 if (fieldFromInstruction(Insn, 4, 1) != 0)
3987 if (fieldFromInstruction(Insn, 6, 1))
3992 if (Rm != 0xF) { // Writeback
3993 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3994 return MCDisassembler::Fail;
3996 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3997 return MCDisassembler::Fail;
3998 Inst.addOperand(MCOperand::CreateImm(align));
4001 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4002 return MCDisassembler::Fail;
4004 Inst.addOperand(MCOperand::CreateReg(0));
4007 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4008 return MCDisassembler::Fail;
4009 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4010 return MCDisassembler::Fail;
4011 Inst.addOperand(MCOperand::CreateImm(index));
4017 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4018 uint64_t Address, const void *Decoder) {
4019 DecodeStatus S = MCDisassembler::Success;
4021 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4022 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4023 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4024 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4025 unsigned size = fieldFromInstruction(Insn, 10, 2);
4032 return MCDisassembler::Fail;
4034 if (fieldFromInstruction(Insn, 4, 1))
4035 return MCDisassembler::Fail; // UNDEFINED
4036 index = fieldFromInstruction(Insn, 5, 3);
4039 if (fieldFromInstruction(Insn, 4, 1))
4040 return MCDisassembler::Fail; // UNDEFINED
4041 index = fieldFromInstruction(Insn, 6, 2);
4042 if (fieldFromInstruction(Insn, 5, 1))
4046 if (fieldFromInstruction(Insn, 4, 2))
4047 return MCDisassembler::Fail; // UNDEFINED
4048 index = fieldFromInstruction(Insn, 7, 1);
4049 if (fieldFromInstruction(Insn, 6, 1))
4054 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4055 return MCDisassembler::Fail;
4056 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4057 return MCDisassembler::Fail;
4058 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4059 return MCDisassembler::Fail;
4061 if (Rm != 0xF) { // Writeback
4062 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4063 return MCDisassembler::Fail;
4065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4066 return MCDisassembler::Fail;
4067 Inst.addOperand(MCOperand::CreateImm(align));
4070 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4071 return MCDisassembler::Fail;
4073 Inst.addOperand(MCOperand::CreateReg(0));
4076 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4077 return MCDisassembler::Fail;
4078 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4079 return MCDisassembler::Fail;
4080 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4081 return MCDisassembler::Fail;
4082 Inst.addOperand(MCOperand::CreateImm(index));
4087 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4088 uint64_t Address, const void *Decoder) {
4089 DecodeStatus S = MCDisassembler::Success;
4091 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4092 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4093 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4094 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4095 unsigned size = fieldFromInstruction(Insn, 10, 2);
4102 return MCDisassembler::Fail;
4104 if (fieldFromInstruction(Insn, 4, 1))
4105 return MCDisassembler::Fail; // UNDEFINED
4106 index = fieldFromInstruction(Insn, 5, 3);
4109 if (fieldFromInstruction(Insn, 4, 1))
4110 return MCDisassembler::Fail; // UNDEFINED
4111 index = fieldFromInstruction(Insn, 6, 2);
4112 if (fieldFromInstruction(Insn, 5, 1))
4116 if (fieldFromInstruction(Insn, 4, 2))
4117 return MCDisassembler::Fail; // UNDEFINED
4118 index = fieldFromInstruction(Insn, 7, 1);
4119 if (fieldFromInstruction(Insn, 6, 1))
4124 if (Rm != 0xF) { // Writeback
4125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4126 return MCDisassembler::Fail;
4128 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4129 return MCDisassembler::Fail;
4130 Inst.addOperand(MCOperand::CreateImm(align));
4133 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4134 return MCDisassembler::Fail;
4136 Inst.addOperand(MCOperand::CreateReg(0));
4139 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4140 return MCDisassembler::Fail;
4141 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4142 return MCDisassembler::Fail;
4143 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4144 return MCDisassembler::Fail;
4145 Inst.addOperand(MCOperand::CreateImm(index));
4151 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4152 uint64_t Address, const void *Decoder) {
4153 DecodeStatus S = MCDisassembler::Success;
4155 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4156 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4157 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4158 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4159 unsigned size = fieldFromInstruction(Insn, 10, 2);
4166 return MCDisassembler::Fail;
4168 if (fieldFromInstruction(Insn, 4, 1))
4170 index = fieldFromInstruction(Insn, 5, 3);
4173 if (fieldFromInstruction(Insn, 4, 1))
4175 index = fieldFromInstruction(Insn, 6, 2);
4176 if (fieldFromInstruction(Insn, 5, 1))
4180 switch (fieldFromInstruction(Insn, 4, 2)) {
4184 return MCDisassembler::Fail;
4186 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4189 index = fieldFromInstruction(Insn, 7, 1);
4190 if (fieldFromInstruction(Insn, 6, 1))
4195 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4196 return MCDisassembler::Fail;
4197 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4198 return MCDisassembler::Fail;
4199 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4200 return MCDisassembler::Fail;
4201 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4202 return MCDisassembler::Fail;
4204 if (Rm != 0xF) { // Writeback
4205 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4206 return MCDisassembler::Fail;
4208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4209 return MCDisassembler::Fail;
4210 Inst.addOperand(MCOperand::CreateImm(align));
4213 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4214 return MCDisassembler::Fail;
4216 Inst.addOperand(MCOperand::CreateReg(0));
4219 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4220 return MCDisassembler::Fail;
4221 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4222 return MCDisassembler::Fail;
4223 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4224 return MCDisassembler::Fail;
4225 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4226 return MCDisassembler::Fail;
4227 Inst.addOperand(MCOperand::CreateImm(index));
4232 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4233 uint64_t Address, const void *Decoder) {
4234 DecodeStatus S = MCDisassembler::Success;
4236 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4237 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4238 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4239 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4240 unsigned size = fieldFromInstruction(Insn, 10, 2);
4247 return MCDisassembler::Fail;
4249 if (fieldFromInstruction(Insn, 4, 1))
4251 index = fieldFromInstruction(Insn, 5, 3);
4254 if (fieldFromInstruction(Insn, 4, 1))
4256 index = fieldFromInstruction(Insn, 6, 2);
4257 if (fieldFromInstruction(Insn, 5, 1))
4261 switch (fieldFromInstruction(Insn, 4, 2)) {
4265 return MCDisassembler::Fail;
4267 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4270 index = fieldFromInstruction(Insn, 7, 1);
4271 if (fieldFromInstruction(Insn, 6, 1))
4276 if (Rm != 0xF) { // Writeback
4277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4278 return MCDisassembler::Fail;
4280 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4281 return MCDisassembler::Fail;
4282 Inst.addOperand(MCOperand::CreateImm(align));
4285 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4286 return MCDisassembler::Fail;
4288 Inst.addOperand(MCOperand::CreateReg(0));
4291 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4292 return MCDisassembler::Fail;
4293 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4294 return MCDisassembler::Fail;
4295 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4296 return MCDisassembler::Fail;
4297 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4298 return MCDisassembler::Fail;
4299 Inst.addOperand(MCOperand::CreateImm(index));
4304 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4305 uint64_t Address, const void *Decoder) {
4306 DecodeStatus S = MCDisassembler::Success;
4307 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4308 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4309 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4310 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4311 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4313 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4314 S = MCDisassembler::SoftFail;
4316 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4317 return MCDisassembler::Fail;
4318 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4319 return MCDisassembler::Fail;
4320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4321 return MCDisassembler::Fail;
4322 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4323 return MCDisassembler::Fail;
4324 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4325 return MCDisassembler::Fail;
4330 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4331 uint64_t Address, const void *Decoder) {
4332 DecodeStatus S = MCDisassembler::Success;
4333 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4334 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4335 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4336 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4337 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4339 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4340 S = MCDisassembler::SoftFail;
4342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4343 return MCDisassembler::Fail;
4344 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4345 return MCDisassembler::Fail;
4346 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4347 return MCDisassembler::Fail;
4348 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4349 return MCDisassembler::Fail;
4350 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4351 return MCDisassembler::Fail;
4356 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4357 uint64_t Address, const void *Decoder) {
4358 DecodeStatus S = MCDisassembler::Success;
4359 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4360 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4364 S = MCDisassembler::SoftFail;
4369 S = MCDisassembler::SoftFail;
4372 Inst.addOperand(MCOperand::CreateImm(pred));
4373 Inst.addOperand(MCOperand::CreateImm(mask));
4378 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4379 uint64_t Address, const void *Decoder) {
4380 DecodeStatus S = MCDisassembler::Success;
4382 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4383 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4384 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4385 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4386 unsigned W = fieldFromInstruction(Insn, 21, 1);
4387 unsigned U = fieldFromInstruction(Insn, 23, 1);
4388 unsigned P = fieldFromInstruction(Insn, 24, 1);
4389 bool writeback = (W == 1) | (P == 0);
4391 addr |= (U << 8) | (Rn << 9);
4393 if (writeback && (Rn == Rt || Rn == Rt2))
4394 Check(S, MCDisassembler::SoftFail);
4396 Check(S, MCDisassembler::SoftFail);
4399 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4400 return MCDisassembler::Fail;
4402 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4403 return MCDisassembler::Fail;
4404 // Writeback operand
4405 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4406 return MCDisassembler::Fail;
4408 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4409 return MCDisassembler::Fail;
4415 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4416 uint64_t Address, const void *Decoder) {
4417 DecodeStatus S = MCDisassembler::Success;
4419 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4420 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4421 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4422 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4423 unsigned W = fieldFromInstruction(Insn, 21, 1);
4424 unsigned U = fieldFromInstruction(Insn, 23, 1);
4425 unsigned P = fieldFromInstruction(Insn, 24, 1);
4426 bool writeback = (W == 1) | (P == 0);
4428 addr |= (U << 8) | (Rn << 9);
4430 if (writeback && (Rn == Rt || Rn == Rt2))
4431 Check(S, MCDisassembler::SoftFail);
4433 // Writeback operand
4434 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4435 return MCDisassembler::Fail;
4437 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4438 return MCDisassembler::Fail;
4440 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4441 return MCDisassembler::Fail;
4443 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4444 return MCDisassembler::Fail;
4449 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4450 uint64_t Address, const void *Decoder) {
4451 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4452 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4453 if (sign1 != sign2) return MCDisassembler::Fail;
4455 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4456 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4457 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4459 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4461 return MCDisassembler::Success;
4464 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4466 const void *Decoder) {
4467 DecodeStatus S = MCDisassembler::Success;
4469 // Shift of "asr #32" is not allowed in Thumb2 mode.
4470 if (Val == 0x20) S = MCDisassembler::SoftFail;
4471 Inst.addOperand(MCOperand::CreateImm(Val));
4475 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4476 uint64_t Address, const void *Decoder) {
4477 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4478 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4479 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4480 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4483 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4485 DecodeStatus S = MCDisassembler::Success;
4487 if (Rt == Rn || Rn == Rt2)
4488 S = MCDisassembler::SoftFail;
4490 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4491 return MCDisassembler::Fail;
4492 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4493 return MCDisassembler::Fail;
4494 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4495 return MCDisassembler::Fail;
4496 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4497 return MCDisassembler::Fail;
4502 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
4503 uint64_t Address, const void *Decoder) {
4504 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4505 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4506 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4507 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4508 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4509 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4510 unsigned op = fieldFromInstruction(Insn, 5, 1);
4512 DecodeStatus S = MCDisassembler::Success;
4514 // VMOVv2f32 is ambiguous with these decodings.
4515 if (!(imm & 0x38) && cmode == 0xF) {
4516 if (op == 1) return MCDisassembler::Fail;
4517 Inst.setOpcode(ARM::VMOVv2f32);
4518 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4521 if (!(imm & 0x20)) return MCDisassembler::Fail;
4523 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4524 return MCDisassembler::Fail;
4525 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4526 return MCDisassembler::Fail;
4527 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4532 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
4533 uint64_t Address, const void *Decoder) {
4534 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4535 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4536 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4537 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4538 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4539 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4540 unsigned op = fieldFromInstruction(Insn, 5, 1);
4542 DecodeStatus S = MCDisassembler::Success;
4544 // VMOVv4f32 is ambiguous with these decodings.
4545 if (!(imm & 0x38) && cmode == 0xF) {
4546 if (op == 1) return MCDisassembler::Fail;
4547 Inst.setOpcode(ARM::VMOVv4f32);
4548 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4551 if (!(imm & 0x20)) return MCDisassembler::Fail;
4553 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4554 return MCDisassembler::Fail;
4555 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4556 return MCDisassembler::Fail;
4557 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4562 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
4563 const void *Decoder)
4565 unsigned Imm = fieldFromInstruction(Insn, 0, 3);
4566 if (Imm > 4) return MCDisassembler::Fail;
4567 Inst.addOperand(MCOperand::CreateImm(Imm));
4568 return MCDisassembler::Success;
4571 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
4572 uint64_t Address, const void *Decoder) {
4573 DecodeStatus S = MCDisassembler::Success;
4575 unsigned Rn = fieldFromInstruction(Val, 16, 4);
4576 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4577 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4578 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4579 unsigned Cond = fieldFromInstruction(Val, 28, 4);
4581 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
4582 S = MCDisassembler::SoftFail;
4584 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4585 return MCDisassembler::Fail;
4586 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4587 return MCDisassembler::Fail;
4588 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4589 return MCDisassembler::Fail;
4590 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4591 return MCDisassembler::Fail;
4592 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4593 return MCDisassembler::Fail;
4598 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4599 uint64_t Address, const void *Decoder) {
4601 DecodeStatus S = MCDisassembler::Success;
4603 unsigned CRm = fieldFromInstruction(Val, 0, 4);
4604 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
4605 unsigned cop = fieldFromInstruction(Val, 8, 4);
4606 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4607 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
4609 if ((cop & ~0x1) == 0xa)
4610 return MCDisassembler::Fail;
4613 S = MCDisassembler::SoftFail;
4615 Inst.addOperand(MCOperand::CreateImm(cop));
4616 Inst.addOperand(MCOperand::CreateImm(opc1));
4617 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4618 return MCDisassembler::Fail;
4619 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4620 return MCDisassembler::Fail;
4621 Inst.addOperand(MCOperand::CreateImm(CRm));