1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFeatures.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCAssembler.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCDisassembler.h"
24 #include "llvm/MC/MCELFStreamer.h"
25 #include "llvm/MC/MCExpr.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCObjectFileInfo.h"
30 #include "llvm/MC/MCParser/MCAsmLexer.h"
31 #include "llvm/MC/MCParser/MCAsmParser.h"
32 #include "llvm/MC/MCParser/MCAsmParserUtils.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCRegisterInfo.h"
35 #include "llvm/MC/MCSection.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCTargetAsmParser.h"
40 #include "llvm/Support/ARMBuildAttributes.h"
41 #include "llvm/Support/ARMEHABI.h"
42 #include "llvm/Support/TargetParser.h"
43 #include "llvm/Support/COFF.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/MathExtras.h"
47 #include "llvm/Support/SourceMgr.h"
48 #include "llvm/Support/TargetRegistry.h"
49 #include "llvm/Support/raw_ostream.h"
57 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
62 typedef SmallVector<SMLoc, 4> Locs;
67 Locs PersonalityIndexLocs;
72 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
74 bool hasFnStart() const { return !FnStartLocs.empty(); }
75 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
76 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
77 bool hasPersonality() const {
78 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
81 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
82 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
83 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
84 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
85 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
87 void saveFPReg(int Reg) { FPReg = Reg; }
88 int getFPReg() const { return FPReg; }
90 void emitFnStartLocNotes() const {
91 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
93 Parser.Note(*FI, ".fnstart was specified here");
95 void emitCantUnwindLocNotes() const {
96 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
97 UE = CantUnwindLocs.end(); UI != UE; ++UI)
98 Parser.Note(*UI, ".cantunwind was specified here");
100 void emitHandlerDataLocNotes() const {
101 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
102 HE = HandlerDataLocs.end(); HI != HE; ++HI)
103 Parser.Note(*HI, ".handlerdata was specified here");
105 void emitPersonalityLocNotes() const {
106 for (Locs::const_iterator PI = PersonalityLocs.begin(),
107 PE = PersonalityLocs.end(),
108 PII = PersonalityIndexLocs.begin(),
109 PIE = PersonalityIndexLocs.end();
110 PI != PE || PII != PIE;) {
111 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
112 Parser.Note(*PI++, ".personality was specified here");
113 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
114 Parser.Note(*PII++, ".personalityindex was specified here");
116 llvm_unreachable(".personality and .personalityindex cannot be "
117 "at the same location");
122 FnStartLocs = Locs();
123 CantUnwindLocs = Locs();
124 PersonalityLocs = Locs();
125 HandlerDataLocs = Locs();
126 PersonalityIndexLocs = Locs();
131 class ARMAsmParser : public MCTargetAsmParser {
132 MCSubtargetInfo &STI;
133 const MCInstrInfo &MII;
134 const MCRegisterInfo *MRI;
137 ARMTargetStreamer &getTargetStreamer() {
138 assert(getParser().getStreamer().getTargetStreamer() &&
139 "do not have a target streamer");
140 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
141 return static_cast<ARMTargetStreamer &>(TS);
144 // Map of register aliases registers via the .req directive.
145 StringMap<unsigned> RegisterReqs;
147 bool NextSymbolIsThumb;
150 ARMCC::CondCodes Cond; // Condition for IT block.
151 unsigned Mask:4; // Condition mask for instructions.
152 // Starting at first 1 (from lsb).
153 // '1' condition as indicated in IT.
154 // '0' inverse of condition (else).
155 // Count of instructions in IT block is
156 // 4 - trailingzeroes(mask)
158 bool FirstCond; // Explicit flag for when we're parsing the
159 // First instruction in the IT block. It's
160 // implied in the mask, so needs special
163 unsigned CurPosition; // Current position in parsing of IT
164 // block. In range [0,3]. Initialized
165 // according to count of instructions in block.
166 // ~0U if no active IT block.
168 bool inITBlock() { return ITState.CurPosition != ~0U; }
169 bool lastInITBlock() {
170 return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
172 void forwardITPosition() {
173 if (!inITBlock()) return;
174 // Move to the next instruction in the IT block, if there is one. If not,
175 // mark the block as done.
176 unsigned TZ = countTrailingZeros(ITState.Mask);
177 if (++ITState.CurPosition == 5 - TZ)
178 ITState.CurPosition = ~0U; // Done with the IT block after this.
181 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
182 return getParser().Note(L, Msg, Ranges);
184 bool Warning(SMLoc L, const Twine &Msg,
185 ArrayRef<SMRange> Ranges = None) {
186 return getParser().Warning(L, Msg, Ranges);
188 bool Error(SMLoc L, const Twine &Msg,
189 ArrayRef<SMRange> Ranges = None) {
190 return getParser().Error(L, Msg, Ranges);
193 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
194 unsigned ListNo, bool IsARPop = false);
195 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
198 int tryParseRegister();
199 bool tryParseRegisterWithWriteBack(OperandVector &);
200 int tryParseShiftRegister(OperandVector &);
201 bool parseRegisterList(OperandVector &);
202 bool parseMemory(OperandVector &);
203 bool parseOperand(OperandVector &, StringRef Mnemonic);
204 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
205 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
206 unsigned &ShiftAmount);
207 bool parseLiteralValues(unsigned Size, SMLoc L);
208 bool parseDirectiveThumb(SMLoc L);
209 bool parseDirectiveARM(SMLoc L);
210 bool parseDirectiveThumbFunc(SMLoc L);
211 bool parseDirectiveCode(SMLoc L);
212 bool parseDirectiveSyntax(SMLoc L);
213 bool parseDirectiveReq(StringRef Name, SMLoc L);
214 bool parseDirectiveUnreq(SMLoc L);
215 bool parseDirectiveArch(SMLoc L);
216 bool parseDirectiveEabiAttr(SMLoc L);
217 bool parseDirectiveCPU(SMLoc L);
218 bool parseDirectiveFPU(SMLoc L);
219 bool parseDirectiveFnStart(SMLoc L);
220 bool parseDirectiveFnEnd(SMLoc L);
221 bool parseDirectiveCantUnwind(SMLoc L);
222 bool parseDirectivePersonality(SMLoc L);
223 bool parseDirectiveHandlerData(SMLoc L);
224 bool parseDirectiveSetFP(SMLoc L);
225 bool parseDirectivePad(SMLoc L);
226 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
227 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
228 bool parseDirectiveLtorg(SMLoc L);
229 bool parseDirectiveEven(SMLoc L);
230 bool parseDirectivePersonalityIndex(SMLoc L);
231 bool parseDirectiveUnwindRaw(SMLoc L);
232 bool parseDirectiveTLSDescSeq(SMLoc L);
233 bool parseDirectiveMovSP(SMLoc L);
234 bool parseDirectiveObjectArch(SMLoc L);
235 bool parseDirectiveArchExtension(SMLoc L);
236 bool parseDirectiveAlign(SMLoc L);
237 bool parseDirectiveThumbSet(SMLoc L);
239 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
240 bool &CarrySetting, unsigned &ProcessorIMod,
242 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
243 bool &CanAcceptCarrySet,
244 bool &CanAcceptPredicationCode);
246 void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
247 OperandVector &Operands);
248 bool isThumb() const {
249 // FIXME: Can tablegen auto-generate this?
250 return STI.getFeatureBits()[ARM::ModeThumb];
252 bool isThumbOne() const {
253 return isThumb() && !STI.getFeatureBits()[ARM::FeatureThumb2];
255 bool isThumbTwo() const {
256 return isThumb() && STI.getFeatureBits()[ARM::FeatureThumb2];
258 bool hasThumb() const {
259 return STI.getFeatureBits()[ARM::HasV4TOps];
261 bool hasV6Ops() const {
262 return STI.getFeatureBits()[ARM::HasV6Ops];
264 bool hasV6MOps() const {
265 return STI.getFeatureBits()[ARM::HasV6MOps];
267 bool hasV7Ops() const {
268 return STI.getFeatureBits()[ARM::HasV7Ops];
270 bool hasV8Ops() const {
271 return STI.getFeatureBits()[ARM::HasV8Ops];
273 bool hasARM() const {
274 return !STI.getFeatureBits()[ARM::FeatureNoARM];
276 bool hasDSP() const {
277 return STI.getFeatureBits()[ARM::FeatureDSP];
279 bool hasD16() const {
280 return STI.getFeatureBits()[ARM::FeatureD16];
282 bool hasV8_1aOps() const {
283 return STI.getFeatureBits()[ARM::HasV8_1aOps];
287 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
288 setAvailableFeatures(FB);
290 bool isMClass() const {
291 return STI.getFeatureBits()[ARM::FeatureMClass];
294 /// @name Auto-generated Match Functions
297 #define GET_ASSEMBLER_HEADER
298 #include "ARMGenAsmMatcher.inc"
302 OperandMatchResultTy parseITCondCode(OperandVector &);
303 OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
304 OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
305 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
306 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
307 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
308 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
309 OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
310 OperandMatchResultTy parseBankedRegOperand(OperandVector &);
311 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
313 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
314 return parsePKHImm(O, "lsl", 0, 31);
316 OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
317 return parsePKHImm(O, "asr", 1, 32);
319 OperandMatchResultTy parseSetEndImm(OperandVector &);
320 OperandMatchResultTy parseShifterImm(OperandVector &);
321 OperandMatchResultTy parseRotImm(OperandVector &);
322 OperandMatchResultTy parseModImm(OperandVector &);
323 OperandMatchResultTy parseBitfield(OperandVector &);
324 OperandMatchResultTy parsePostIdxReg(OperandVector &);
325 OperandMatchResultTy parseAM3Offset(OperandVector &);
326 OperandMatchResultTy parseFPImm(OperandVector &);
327 OperandMatchResultTy parseVectorList(OperandVector &);
328 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
331 // Asm Match Converter Methods
332 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
333 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
335 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
336 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
337 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
338 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
341 enum ARMMatchResultTy {
342 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
343 Match_RequiresNotITBlock,
345 Match_RequiresThumb2,
347 #define GET_OPERAND_DIAGNOSTIC_TYPES
348 #include "ARMGenAsmMatcher.inc"
352 ARMAsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser,
353 const MCInstrInfo &MII, const MCTargetOptions &Options)
354 : MCTargetAsmParser(Options), STI(STI), MII(MII), UC(Parser) {
355 MCAsmParserExtension::Initialize(Parser);
357 // Cache the MCRegisterInfo.
358 MRI = getContext().getRegisterInfo();
360 // Initialize the set of available features.
361 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
363 // Not in an ITBlock to start with.
364 ITState.CurPosition = ~0U;
366 NextSymbolIsThumb = false;
369 // Implementation of the MCTargetAsmParser interface:
370 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
371 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
372 SMLoc NameLoc, OperandVector &Operands) override;
373 bool ParseDirective(AsmToken DirectiveID) override;
375 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
376 unsigned Kind) override;
377 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
379 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
380 OperandVector &Operands, MCStreamer &Out,
382 bool MatchingInlineAsm) override;
383 void onLabelParsed(MCSymbol *Symbol) override;
385 } // end anonymous namespace
389 /// ARMOperand - Instances of this class represent a parsed ARM machine
391 class ARMOperand : public MCParsedAsmOperand {
401 k_InstSyncBarrierOpt,
413 k_VectorListAllLanes,
420 k_BitfieldDescriptor,
424 SMLoc StartLoc, EndLoc, AlignmentLoc;
425 SmallVector<unsigned, 8> Registers;
428 ARMCC::CondCodes Val;
435 struct CoprocOptionOp {
448 ARM_ISB::InstSyncBOpt Val;
452 ARM_PROC::IFlags Val;
472 // A vector register list is a sequential list of 1 to 4 registers.
473 struct VectorListOp {
480 struct VectorIndexOp {
488 /// Combined record for all forms of ARM address expressions.
491 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
493 const MCConstantExpr *OffsetImm; // Offset immediate value
494 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
495 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
496 unsigned ShiftImm; // shift for OffsetReg.
497 unsigned Alignment; // 0 = no alignment specified
498 // n = alignment in bytes (2, 4, 8, 16, or 32)
499 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
502 struct PostIdxRegOp {
505 ARM_AM::ShiftOpc ShiftTy;
509 struct ShifterImmOp {
514 struct RegShiftedRegOp {
515 ARM_AM::ShiftOpc ShiftTy;
521 struct RegShiftedImmOp {
522 ARM_AM::ShiftOpc ShiftTy;
544 struct CoprocOptionOp CoprocOption;
545 struct MBOptOp MBOpt;
546 struct ISBOptOp ISBOpt;
547 struct ITMaskOp ITMask;
548 struct IFlagsOp IFlags;
549 struct MMaskOp MMask;
550 struct BankedRegOp BankedReg;
553 struct VectorListOp VectorList;
554 struct VectorIndexOp VectorIndex;
556 struct MemoryOp Memory;
557 struct PostIdxRegOp PostIdxReg;
558 struct ShifterImmOp ShifterImm;
559 struct RegShiftedRegOp RegShiftedReg;
560 struct RegShiftedImmOp RegShiftedImm;
561 struct RotImmOp RotImm;
562 struct ModImmOp ModImm;
563 struct BitfieldOp Bitfield;
567 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
569 /// getStartLoc - Get the location of the first token of this operand.
570 SMLoc getStartLoc() const override { return StartLoc; }
571 /// getEndLoc - Get the location of the last token of this operand.
572 SMLoc getEndLoc() const override { return EndLoc; }
573 /// getLocRange - Get the range between the first and last token of this
575 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
577 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
578 SMLoc getAlignmentLoc() const {
579 assert(Kind == k_Memory && "Invalid access!");
583 ARMCC::CondCodes getCondCode() const {
584 assert(Kind == k_CondCode && "Invalid access!");
588 unsigned getCoproc() const {
589 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
593 StringRef getToken() const {
594 assert(Kind == k_Token && "Invalid access!");
595 return StringRef(Tok.Data, Tok.Length);
598 unsigned getReg() const override {
599 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
603 const SmallVectorImpl<unsigned> &getRegList() const {
604 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
605 Kind == k_SPRRegisterList) && "Invalid access!");
609 const MCExpr *getImm() const {
610 assert(isImm() && "Invalid access!");
614 unsigned getVectorIndex() const {
615 assert(Kind == k_VectorIndex && "Invalid access!");
616 return VectorIndex.Val;
619 ARM_MB::MemBOpt getMemBarrierOpt() const {
620 assert(Kind == k_MemBarrierOpt && "Invalid access!");
624 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
625 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
629 ARM_PROC::IFlags getProcIFlags() const {
630 assert(Kind == k_ProcIFlags && "Invalid access!");
634 unsigned getMSRMask() const {
635 assert(Kind == k_MSRMask && "Invalid access!");
639 unsigned getBankedReg() const {
640 assert(Kind == k_BankedReg && "Invalid access!");
641 return BankedReg.Val;
644 bool isCoprocNum() const { return Kind == k_CoprocNum; }
645 bool isCoprocReg() const { return Kind == k_CoprocReg; }
646 bool isCoprocOption() const { return Kind == k_CoprocOption; }
647 bool isCondCode() const { return Kind == k_CondCode; }
648 bool isCCOut() const { return Kind == k_CCOut; }
649 bool isITMask() const { return Kind == k_ITCondMask; }
650 bool isITCondCode() const { return Kind == k_CondCode; }
651 bool isImm() const override { return Kind == k_Immediate; }
652 // checks whether this operand is an unsigned offset which fits is a field
653 // of specified width and scaled by a specific number of bits
654 template<unsigned width, unsigned scale>
655 bool isUnsignedOffset() const {
656 if (!isImm()) return false;
657 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
658 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
659 int64_t Val = CE->getValue();
660 int64_t Align = 1LL << scale;
661 int64_t Max = Align * ((1LL << width) - 1);
662 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
666 // checks whether this operand is an signed offset which fits is a field
667 // of specified width and scaled by a specific number of bits
668 template<unsigned width, unsigned scale>
669 bool isSignedOffset() const {
670 if (!isImm()) return false;
671 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
672 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
673 int64_t Val = CE->getValue();
674 int64_t Align = 1LL << scale;
675 int64_t Max = Align * ((1LL << (width-1)) - 1);
676 int64_t Min = -Align * (1LL << (width-1));
677 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
682 // checks whether this operand is a memory operand computed as an offset
683 // applied to PC. the offset may have 8 bits of magnitude and is represented
684 // with two bits of shift. textually it may be either [pc, #imm], #imm or
685 // relocable expression...
686 bool isThumbMemPC() const {
689 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
690 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
691 if (!CE) return false;
692 Val = CE->getValue();
695 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
696 if(Memory.BaseRegNum != ARM::PC) return false;
697 Val = Memory.OffsetImm->getValue();
700 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
702 bool isFPImm() const {
703 if (!isImm()) return false;
704 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
705 if (!CE) return false;
706 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
709 bool isFBits16() const {
710 if (!isImm()) return false;
711 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
712 if (!CE) return false;
713 int64_t Value = CE->getValue();
714 return Value >= 0 && Value <= 16;
716 bool isFBits32() const {
717 if (!isImm()) return false;
718 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
719 if (!CE) return false;
720 int64_t Value = CE->getValue();
721 return Value >= 1 && Value <= 32;
723 bool isImm8s4() const {
724 if (!isImm()) return false;
725 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
726 if (!CE) return false;
727 int64_t Value = CE->getValue();
728 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
730 bool isImm0_1020s4() const {
731 if (!isImm()) return false;
732 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
733 if (!CE) return false;
734 int64_t Value = CE->getValue();
735 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
737 bool isImm0_508s4() const {
738 if (!isImm()) return false;
739 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
740 if (!CE) return false;
741 int64_t Value = CE->getValue();
742 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
744 bool isImm0_508s4Neg() const {
745 if (!isImm()) return false;
746 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
747 if (!CE) return false;
748 int64_t Value = -CE->getValue();
749 // explicitly exclude zero. we want that to use the normal 0_508 version.
750 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
752 bool isImm0_239() const {
753 if (!isImm()) return false;
754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
755 if (!CE) return false;
756 int64_t Value = CE->getValue();
757 return Value >= 0 && Value < 240;
759 bool isImm0_255() const {
760 if (!isImm()) return false;
761 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
762 if (!CE) return false;
763 int64_t Value = CE->getValue();
764 return Value >= 0 && Value < 256;
766 bool isImm0_4095() const {
767 if (!isImm()) return false;
768 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
769 if (!CE) return false;
770 int64_t Value = CE->getValue();
771 return Value >= 0 && Value < 4096;
773 bool isImm0_4095Neg() const {
774 if (!isImm()) return false;
775 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
776 if (!CE) return false;
777 int64_t Value = -CE->getValue();
778 return Value > 0 && Value < 4096;
780 bool isImm0_1() const {
781 if (!isImm()) return false;
782 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
783 if (!CE) return false;
784 int64_t Value = CE->getValue();
785 return Value >= 0 && Value < 2;
787 bool isImm0_3() const {
788 if (!isImm()) return false;
789 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
790 if (!CE) return false;
791 int64_t Value = CE->getValue();
792 return Value >= 0 && Value < 4;
794 bool isImm0_7() const {
795 if (!isImm()) return false;
796 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
797 if (!CE) return false;
798 int64_t Value = CE->getValue();
799 return Value >= 0 && Value < 8;
801 bool isImm0_15() const {
802 if (!isImm()) return false;
803 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
804 if (!CE) return false;
805 int64_t Value = CE->getValue();
806 return Value >= 0 && Value < 16;
808 bool isImm0_31() const {
809 if (!isImm()) return false;
810 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
811 if (!CE) return false;
812 int64_t Value = CE->getValue();
813 return Value >= 0 && Value < 32;
815 bool isImm0_63() const {
816 if (!isImm()) return false;
817 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
818 if (!CE) return false;
819 int64_t Value = CE->getValue();
820 return Value >= 0 && Value < 64;
822 bool isImm8() const {
823 if (!isImm()) return false;
824 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
825 if (!CE) return false;
826 int64_t Value = CE->getValue();
829 bool isImm16() const {
830 if (!isImm()) return false;
831 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
832 if (!CE) return false;
833 int64_t Value = CE->getValue();
836 bool isImm32() const {
837 if (!isImm()) return false;
838 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
839 if (!CE) return false;
840 int64_t Value = CE->getValue();
843 bool isShrImm8() const {
844 if (!isImm()) return false;
845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
846 if (!CE) return false;
847 int64_t Value = CE->getValue();
848 return Value > 0 && Value <= 8;
850 bool isShrImm16() const {
851 if (!isImm()) return false;
852 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
853 if (!CE) return false;
854 int64_t Value = CE->getValue();
855 return Value > 0 && Value <= 16;
857 bool isShrImm32() const {
858 if (!isImm()) return false;
859 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
860 if (!CE) return false;
861 int64_t Value = CE->getValue();
862 return Value > 0 && Value <= 32;
864 bool isShrImm64() const {
865 if (!isImm()) return false;
866 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
867 if (!CE) return false;
868 int64_t Value = CE->getValue();
869 return Value > 0 && Value <= 64;
871 bool isImm1_7() const {
872 if (!isImm()) return false;
873 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
874 if (!CE) return false;
875 int64_t Value = CE->getValue();
876 return Value > 0 && Value < 8;
878 bool isImm1_15() const {
879 if (!isImm()) return false;
880 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
881 if (!CE) return false;
882 int64_t Value = CE->getValue();
883 return Value > 0 && Value < 16;
885 bool isImm1_31() const {
886 if (!isImm()) return false;
887 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
888 if (!CE) return false;
889 int64_t Value = CE->getValue();
890 return Value > 0 && Value < 32;
892 bool isImm1_16() const {
893 if (!isImm()) return false;
894 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
895 if (!CE) return false;
896 int64_t Value = CE->getValue();
897 return Value > 0 && Value < 17;
899 bool isImm1_32() const {
900 if (!isImm()) return false;
901 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
902 if (!CE) return false;
903 int64_t Value = CE->getValue();
904 return Value > 0 && Value < 33;
906 bool isImm0_32() const {
907 if (!isImm()) return false;
908 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
909 if (!CE) return false;
910 int64_t Value = CE->getValue();
911 return Value >= 0 && Value < 33;
913 bool isImm0_65535() const {
914 if (!isImm()) return false;
915 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
916 if (!CE) return false;
917 int64_t Value = CE->getValue();
918 return Value >= 0 && Value < 65536;
920 bool isImm256_65535Expr() const {
921 if (!isImm()) return false;
922 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
923 // If it's not a constant expression, it'll generate a fixup and be
925 if (!CE) return true;
926 int64_t Value = CE->getValue();
927 return Value >= 256 && Value < 65536;
929 bool isImm0_65535Expr() const {
930 if (!isImm()) return false;
931 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
932 // If it's not a constant expression, it'll generate a fixup and be
934 if (!CE) return true;
935 int64_t Value = CE->getValue();
936 return Value >= 0 && Value < 65536;
938 bool isImm24bit() const {
939 if (!isImm()) return false;
940 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
941 if (!CE) return false;
942 int64_t Value = CE->getValue();
943 return Value >= 0 && Value <= 0xffffff;
945 bool isImmThumbSR() const {
946 if (!isImm()) return false;
947 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
948 if (!CE) return false;
949 int64_t Value = CE->getValue();
950 return Value > 0 && Value < 33;
952 bool isPKHLSLImm() const {
953 if (!isImm()) return false;
954 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
955 if (!CE) return false;
956 int64_t Value = CE->getValue();
957 return Value >= 0 && Value < 32;
959 bool isPKHASRImm() const {
960 if (!isImm()) return false;
961 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
962 if (!CE) return false;
963 int64_t Value = CE->getValue();
964 return Value > 0 && Value <= 32;
966 bool isAdrLabel() const {
967 // If we have an immediate that's not a constant, treat it as a label
968 // reference needing a fixup.
969 if (isImm() && !isa<MCConstantExpr>(getImm()))
972 // If it is a constant, it must fit into a modified immediate encoding.
973 if (!isImm()) return false;
974 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
975 if (!CE) return false;
976 int64_t Value = CE->getValue();
977 return (ARM_AM::getSOImmVal(Value) != -1 ||
978 ARM_AM::getSOImmVal(-Value) != -1);
980 bool isT2SOImm() const {
981 if (!isImm()) return false;
982 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
983 if (!CE) return false;
984 int64_t Value = CE->getValue();
985 return ARM_AM::getT2SOImmVal(Value) != -1;
987 bool isT2SOImmNot() const {
988 if (!isImm()) return false;
989 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
990 if (!CE) return false;
991 int64_t Value = CE->getValue();
992 return ARM_AM::getT2SOImmVal(Value) == -1 &&
993 ARM_AM::getT2SOImmVal(~Value) != -1;
995 bool isT2SOImmNeg() const {
996 if (!isImm()) return false;
997 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
998 if (!CE) return false;
999 int64_t Value = CE->getValue();
1000 // Only use this when not representable as a plain so_imm.
1001 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1002 ARM_AM::getT2SOImmVal(-Value) != -1;
1004 bool isSetEndImm() const {
1005 if (!isImm()) return false;
1006 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1007 if (!CE) return false;
1008 int64_t Value = CE->getValue();
1009 return Value == 1 || Value == 0;
1011 bool isReg() const override { return Kind == k_Register; }
1012 bool isRegList() const { return Kind == k_RegisterList; }
1013 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1014 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1015 bool isToken() const override { return Kind == k_Token; }
1016 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1017 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1018 bool isMem() const override { return Kind == k_Memory; }
1019 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1020 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1021 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1022 bool isRotImm() const { return Kind == k_RotateImmediate; }
1023 bool isModImm() const { return Kind == k_ModifiedImmediate; }
1024 bool isModImmNot() const {
1025 if (!isImm()) return false;
1026 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1027 if (!CE) return false;
1028 int64_t Value = CE->getValue();
1029 return ARM_AM::getSOImmVal(~Value) != -1;
1031 bool isModImmNeg() const {
1032 if (!isImm()) return false;
1033 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1034 if (!CE) return false;
1035 int64_t Value = CE->getValue();
1036 return ARM_AM::getSOImmVal(Value) == -1 &&
1037 ARM_AM::getSOImmVal(-Value) != -1;
1039 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1040 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1041 bool isPostIdxReg() const {
1042 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1044 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1047 // No offset of any kind.
1048 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1049 (alignOK || Memory.Alignment == Alignment);
1051 bool isMemPCRelImm12() const {
1052 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1054 // Base register must be PC.
1055 if (Memory.BaseRegNum != ARM::PC)
1057 // Immediate offset in range [-4095, 4095].
1058 if (!Memory.OffsetImm) return true;
1059 int64_t Val = Memory.OffsetImm->getValue();
1060 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1062 bool isAlignedMemory() const {
1063 return isMemNoOffset(true);
1065 bool isAlignedMemoryNone() const {
1066 return isMemNoOffset(false, 0);
1068 bool isDupAlignedMemoryNone() const {
1069 return isMemNoOffset(false, 0);
1071 bool isAlignedMemory16() const {
1072 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1074 return isMemNoOffset(false, 0);
1076 bool isDupAlignedMemory16() const {
1077 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1079 return isMemNoOffset(false, 0);
1081 bool isAlignedMemory32() const {
1082 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1084 return isMemNoOffset(false, 0);
1086 bool isDupAlignedMemory32() const {
1087 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1089 return isMemNoOffset(false, 0);
1091 bool isAlignedMemory64() const {
1092 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1094 return isMemNoOffset(false, 0);
1096 bool isDupAlignedMemory64() const {
1097 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1099 return isMemNoOffset(false, 0);
1101 bool isAlignedMemory64or128() const {
1102 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1104 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1106 return isMemNoOffset(false, 0);
1108 bool isDupAlignedMemory64or128() const {
1109 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1111 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1113 return isMemNoOffset(false, 0);
1115 bool isAlignedMemory64or128or256() const {
1116 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1118 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1120 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1122 return isMemNoOffset(false, 0);
1124 bool isAddrMode2() const {
1125 if (!isMem() || Memory.Alignment != 0) return false;
1126 // Check for register offset.
1127 if (Memory.OffsetRegNum) return true;
1128 // Immediate offset in range [-4095, 4095].
1129 if (!Memory.OffsetImm) return true;
1130 int64_t Val = Memory.OffsetImm->getValue();
1131 return Val > -4096 && Val < 4096;
1133 bool isAM2OffsetImm() const {
1134 if (!isImm()) return false;
1135 // Immediate offset in range [-4095, 4095].
1136 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1137 if (!CE) return false;
1138 int64_t Val = CE->getValue();
1139 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1141 bool isAddrMode3() const {
1142 // If we have an immediate that's not a constant, treat it as a label
1143 // reference needing a fixup. If it is a constant, it's something else
1144 // and we reject it.
1145 if (isImm() && !isa<MCConstantExpr>(getImm()))
1147 if (!isMem() || Memory.Alignment != 0) return false;
1148 // No shifts are legal for AM3.
1149 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1150 // Check for register offset.
1151 if (Memory.OffsetRegNum) return true;
1152 // Immediate offset in range [-255, 255].
1153 if (!Memory.OffsetImm) return true;
1154 int64_t Val = Memory.OffsetImm->getValue();
1155 // The #-0 offset is encoded as INT32_MIN, and we have to check
1157 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1159 bool isAM3Offset() const {
1160 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1162 if (Kind == k_PostIndexRegister)
1163 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1164 // Immediate offset in range [-255, 255].
1165 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1166 if (!CE) return false;
1167 int64_t Val = CE->getValue();
1168 // Special case, #-0 is INT32_MIN.
1169 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1171 bool isAddrMode5() const {
1172 // If we have an immediate that's not a constant, treat it as a label
1173 // reference needing a fixup. If it is a constant, it's something else
1174 // and we reject it.
1175 if (isImm() && !isa<MCConstantExpr>(getImm()))
1177 if (!isMem() || Memory.Alignment != 0) return false;
1178 // Check for register offset.
1179 if (Memory.OffsetRegNum) return false;
1180 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1181 if (!Memory.OffsetImm) return true;
1182 int64_t Val = Memory.OffsetImm->getValue();
1183 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1186 bool isMemTBB() const {
1187 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1188 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1192 bool isMemTBH() const {
1193 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1194 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1195 Memory.Alignment != 0 )
1199 bool isMemRegOffset() const {
1200 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1204 bool isT2MemRegOffset() const {
1205 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1206 Memory.Alignment != 0)
1208 // Only lsl #{0, 1, 2, 3} allowed.
1209 if (Memory.ShiftType == ARM_AM::no_shift)
1211 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1215 bool isMemThumbRR() const {
1216 // Thumb reg+reg addressing is simple. Just two registers, a base and
1217 // an offset. No shifts, negations or any other complicating factors.
1218 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1219 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1221 return isARMLowRegister(Memory.BaseRegNum) &&
1222 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1224 bool isMemThumbRIs4() const {
1225 if (!isMem() || Memory.OffsetRegNum != 0 ||
1226 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1228 // Immediate offset, multiple of 4 in range [0, 124].
1229 if (!Memory.OffsetImm) return true;
1230 int64_t Val = Memory.OffsetImm->getValue();
1231 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1233 bool isMemThumbRIs2() const {
1234 if (!isMem() || Memory.OffsetRegNum != 0 ||
1235 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1237 // Immediate offset, multiple of 4 in range [0, 62].
1238 if (!Memory.OffsetImm) return true;
1239 int64_t Val = Memory.OffsetImm->getValue();
1240 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1242 bool isMemThumbRIs1() const {
1243 if (!isMem() || Memory.OffsetRegNum != 0 ||
1244 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1246 // Immediate offset in range [0, 31].
1247 if (!Memory.OffsetImm) return true;
1248 int64_t Val = Memory.OffsetImm->getValue();
1249 return Val >= 0 && Val <= 31;
1251 bool isMemThumbSPI() const {
1252 if (!isMem() || Memory.OffsetRegNum != 0 ||
1253 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1255 // Immediate offset, multiple of 4 in range [0, 1020].
1256 if (!Memory.OffsetImm) return true;
1257 int64_t Val = Memory.OffsetImm->getValue();
1258 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1260 bool isMemImm8s4Offset() const {
1261 // If we have an immediate that's not a constant, treat it as a label
1262 // reference needing a fixup. If it is a constant, it's something else
1263 // and we reject it.
1264 if (isImm() && !isa<MCConstantExpr>(getImm()))
1266 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1268 // Immediate offset a multiple of 4 in range [-1020, 1020].
1269 if (!Memory.OffsetImm) return true;
1270 int64_t Val = Memory.OffsetImm->getValue();
1271 // Special case, #-0 is INT32_MIN.
1272 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1274 bool isMemImm0_1020s4Offset() const {
1275 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1277 // Immediate offset a multiple of 4 in range [0, 1020].
1278 if (!Memory.OffsetImm) return true;
1279 int64_t Val = Memory.OffsetImm->getValue();
1280 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1282 bool isMemImm8Offset() const {
1283 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1285 // Base reg of PC isn't allowed for these encodings.
1286 if (Memory.BaseRegNum == ARM::PC) return false;
1287 // Immediate offset in range [-255, 255].
1288 if (!Memory.OffsetImm) return true;
1289 int64_t Val = Memory.OffsetImm->getValue();
1290 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1292 bool isMemPosImm8Offset() const {
1293 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1295 // Immediate offset in range [0, 255].
1296 if (!Memory.OffsetImm) return true;
1297 int64_t Val = Memory.OffsetImm->getValue();
1298 return Val >= 0 && Val < 256;
1300 bool isMemNegImm8Offset() const {
1301 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1303 // Base reg of PC isn't allowed for these encodings.
1304 if (Memory.BaseRegNum == ARM::PC) return false;
1305 // Immediate offset in range [-255, -1].
1306 if (!Memory.OffsetImm) return false;
1307 int64_t Val = Memory.OffsetImm->getValue();
1308 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1310 bool isMemUImm12Offset() const {
1311 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1313 // Immediate offset in range [0, 4095].
1314 if (!Memory.OffsetImm) return true;
1315 int64_t Val = Memory.OffsetImm->getValue();
1316 return (Val >= 0 && Val < 4096);
1318 bool isMemImm12Offset() const {
1319 // If we have an immediate that's not a constant, treat it as a label
1320 // reference needing a fixup. If it is a constant, it's something else
1321 // and we reject it.
1322 if (isImm() && !isa<MCConstantExpr>(getImm()))
1325 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1327 // Immediate offset in range [-4095, 4095].
1328 if (!Memory.OffsetImm) return true;
1329 int64_t Val = Memory.OffsetImm->getValue();
1330 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1332 bool isPostIdxImm8() const {
1333 if (!isImm()) return false;
1334 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1335 if (!CE) return false;
1336 int64_t Val = CE->getValue();
1337 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1339 bool isPostIdxImm8s4() const {
1340 if (!isImm()) return false;
1341 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1342 if (!CE) return false;
1343 int64_t Val = CE->getValue();
1344 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1348 bool isMSRMask() const { return Kind == k_MSRMask; }
1349 bool isBankedReg() const { return Kind == k_BankedReg; }
1350 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1353 bool isSingleSpacedVectorList() const {
1354 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1356 bool isDoubleSpacedVectorList() const {
1357 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1359 bool isVecListOneD() const {
1360 if (!isSingleSpacedVectorList()) return false;
1361 return VectorList.Count == 1;
1364 bool isVecListDPair() const {
1365 if (!isSingleSpacedVectorList()) return false;
1366 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1367 .contains(VectorList.RegNum));
1370 bool isVecListThreeD() const {
1371 if (!isSingleSpacedVectorList()) return false;
1372 return VectorList.Count == 3;
1375 bool isVecListFourD() const {
1376 if (!isSingleSpacedVectorList()) return false;
1377 return VectorList.Count == 4;
1380 bool isVecListDPairSpaced() const {
1381 if (Kind != k_VectorList) return false;
1382 if (isSingleSpacedVectorList()) return false;
1383 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1384 .contains(VectorList.RegNum));
1387 bool isVecListThreeQ() const {
1388 if (!isDoubleSpacedVectorList()) return false;
1389 return VectorList.Count == 3;
1392 bool isVecListFourQ() const {
1393 if (!isDoubleSpacedVectorList()) return false;
1394 return VectorList.Count == 4;
1397 bool isSingleSpacedVectorAllLanes() const {
1398 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1400 bool isDoubleSpacedVectorAllLanes() const {
1401 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1403 bool isVecListOneDAllLanes() const {
1404 if (!isSingleSpacedVectorAllLanes()) return false;
1405 return VectorList.Count == 1;
1408 bool isVecListDPairAllLanes() const {
1409 if (!isSingleSpacedVectorAllLanes()) return false;
1410 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1411 .contains(VectorList.RegNum));
1414 bool isVecListDPairSpacedAllLanes() const {
1415 if (!isDoubleSpacedVectorAllLanes()) return false;
1416 return VectorList.Count == 2;
1419 bool isVecListThreeDAllLanes() const {
1420 if (!isSingleSpacedVectorAllLanes()) return false;
1421 return VectorList.Count == 3;
1424 bool isVecListThreeQAllLanes() const {
1425 if (!isDoubleSpacedVectorAllLanes()) return false;
1426 return VectorList.Count == 3;
1429 bool isVecListFourDAllLanes() const {
1430 if (!isSingleSpacedVectorAllLanes()) return false;
1431 return VectorList.Count == 4;
1434 bool isVecListFourQAllLanes() const {
1435 if (!isDoubleSpacedVectorAllLanes()) return false;
1436 return VectorList.Count == 4;
1439 bool isSingleSpacedVectorIndexed() const {
1440 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1442 bool isDoubleSpacedVectorIndexed() const {
1443 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1445 bool isVecListOneDByteIndexed() const {
1446 if (!isSingleSpacedVectorIndexed()) return false;
1447 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1450 bool isVecListOneDHWordIndexed() const {
1451 if (!isSingleSpacedVectorIndexed()) return false;
1452 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1455 bool isVecListOneDWordIndexed() const {
1456 if (!isSingleSpacedVectorIndexed()) return false;
1457 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1460 bool isVecListTwoDByteIndexed() const {
1461 if (!isSingleSpacedVectorIndexed()) return false;
1462 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1465 bool isVecListTwoDHWordIndexed() const {
1466 if (!isSingleSpacedVectorIndexed()) return false;
1467 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1470 bool isVecListTwoQWordIndexed() const {
1471 if (!isDoubleSpacedVectorIndexed()) return false;
1472 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1475 bool isVecListTwoQHWordIndexed() const {
1476 if (!isDoubleSpacedVectorIndexed()) return false;
1477 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1480 bool isVecListTwoDWordIndexed() const {
1481 if (!isSingleSpacedVectorIndexed()) return false;
1482 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1485 bool isVecListThreeDByteIndexed() const {
1486 if (!isSingleSpacedVectorIndexed()) return false;
1487 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1490 bool isVecListThreeDHWordIndexed() const {
1491 if (!isSingleSpacedVectorIndexed()) return false;
1492 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1495 bool isVecListThreeQWordIndexed() const {
1496 if (!isDoubleSpacedVectorIndexed()) return false;
1497 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1500 bool isVecListThreeQHWordIndexed() const {
1501 if (!isDoubleSpacedVectorIndexed()) return false;
1502 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1505 bool isVecListThreeDWordIndexed() const {
1506 if (!isSingleSpacedVectorIndexed()) return false;
1507 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1510 bool isVecListFourDByteIndexed() const {
1511 if (!isSingleSpacedVectorIndexed()) return false;
1512 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1515 bool isVecListFourDHWordIndexed() const {
1516 if (!isSingleSpacedVectorIndexed()) return false;
1517 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1520 bool isVecListFourQWordIndexed() const {
1521 if (!isDoubleSpacedVectorIndexed()) return false;
1522 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1525 bool isVecListFourQHWordIndexed() const {
1526 if (!isDoubleSpacedVectorIndexed()) return false;
1527 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1530 bool isVecListFourDWordIndexed() const {
1531 if (!isSingleSpacedVectorIndexed()) return false;
1532 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1535 bool isVectorIndex8() const {
1536 if (Kind != k_VectorIndex) return false;
1537 return VectorIndex.Val < 8;
1539 bool isVectorIndex16() const {
1540 if (Kind != k_VectorIndex) return false;
1541 return VectorIndex.Val < 4;
1543 bool isVectorIndex32() const {
1544 if (Kind != k_VectorIndex) return false;
1545 return VectorIndex.Val < 2;
1548 bool isNEONi8splat() const {
1549 if (!isImm()) return false;
1550 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1551 // Must be a constant.
1552 if (!CE) return false;
1553 int64_t Value = CE->getValue();
1554 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1556 return Value >= 0 && Value < 256;
1559 bool isNEONi16splat() const {
1560 if (isNEONByteReplicate(2))
1561 return false; // Leave that for bytes replication and forbid by default.
1564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1565 // Must be a constant.
1566 if (!CE) return false;
1567 unsigned Value = CE->getValue();
1568 return ARM_AM::isNEONi16splat(Value);
1571 bool isNEONi16splatNot() const {
1574 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1575 // Must be a constant.
1576 if (!CE) return false;
1577 unsigned Value = CE->getValue();
1578 return ARM_AM::isNEONi16splat(~Value & 0xffff);
1581 bool isNEONi32splat() const {
1582 if (isNEONByteReplicate(4))
1583 return false; // Leave that for bytes replication and forbid by default.
1586 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1587 // Must be a constant.
1588 if (!CE) return false;
1589 unsigned Value = CE->getValue();
1590 return ARM_AM::isNEONi32splat(Value);
1593 bool isNEONi32splatNot() const {
1596 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1597 // Must be a constant.
1598 if (!CE) return false;
1599 unsigned Value = CE->getValue();
1600 return ARM_AM::isNEONi32splat(~Value);
1603 bool isNEONByteReplicate(unsigned NumBytes) const {
1606 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1607 // Must be a constant.
1610 int64_t Value = CE->getValue();
1612 return false; // Don't bother with zero.
1614 unsigned char B = Value & 0xff;
1615 for (unsigned i = 1; i < NumBytes; ++i) {
1617 if ((Value & 0xff) != B)
1622 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1623 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1624 bool isNEONi32vmov() const {
1625 if (isNEONByteReplicate(4))
1626 return false; // Let it to be classified as byte-replicate case.
1629 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1630 // Must be a constant.
1633 int64_t Value = CE->getValue();
1634 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1635 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1636 // FIXME: This is probably wrong and a copy and paste from previous example
1637 return (Value >= 0 && Value < 256) ||
1638 (Value >= 0x0100 && Value <= 0xff00) ||
1639 (Value >= 0x010000 && Value <= 0xff0000) ||
1640 (Value >= 0x01000000 && Value <= 0xff000000) ||
1641 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1642 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1644 bool isNEONi32vmovNeg() const {
1645 if (!isImm()) return false;
1646 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1647 // Must be a constant.
1648 if (!CE) return false;
1649 int64_t Value = ~CE->getValue();
1650 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1651 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1652 // FIXME: This is probably wrong and a copy and paste from previous example
1653 return (Value >= 0 && Value < 256) ||
1654 (Value >= 0x0100 && Value <= 0xff00) ||
1655 (Value >= 0x010000 && Value <= 0xff0000) ||
1656 (Value >= 0x01000000 && Value <= 0xff000000) ||
1657 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1658 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1661 bool isNEONi64splat() const {
1662 if (!isImm()) return false;
1663 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1664 // Must be a constant.
1665 if (!CE) return false;
1666 uint64_t Value = CE->getValue();
1667 // i64 value with each byte being either 0 or 0xff.
1668 for (unsigned i = 0; i < 8; ++i)
1669 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1673 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1674 // Add as immediates when possible. Null MCExpr = 0.
1676 Inst.addOperand(MCOperand::createImm(0));
1677 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1678 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1680 Inst.addOperand(MCOperand::createExpr(Expr));
1683 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1684 assert(N == 2 && "Invalid number of operands!");
1685 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1686 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1687 Inst.addOperand(MCOperand::createReg(RegNum));
1690 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1691 assert(N == 1 && "Invalid number of operands!");
1692 Inst.addOperand(MCOperand::createImm(getCoproc()));
1695 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1696 assert(N == 1 && "Invalid number of operands!");
1697 Inst.addOperand(MCOperand::createImm(getCoproc()));
1700 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1701 assert(N == 1 && "Invalid number of operands!");
1702 Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
1705 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1706 assert(N == 1 && "Invalid number of operands!");
1707 Inst.addOperand(MCOperand::createImm(ITMask.Mask));
1710 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1711 assert(N == 1 && "Invalid number of operands!");
1712 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1715 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1716 assert(N == 1 && "Invalid number of operands!");
1717 Inst.addOperand(MCOperand::createReg(getReg()));
1720 void addRegOperands(MCInst &Inst, unsigned N) const {
1721 assert(N == 1 && "Invalid number of operands!");
1722 Inst.addOperand(MCOperand::createReg(getReg()));
1725 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1726 assert(N == 3 && "Invalid number of operands!");
1727 assert(isRegShiftedReg() &&
1728 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1729 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
1730 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
1731 Inst.addOperand(MCOperand::createImm(
1732 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1735 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1736 assert(N == 2 && "Invalid number of operands!");
1737 assert(isRegShiftedImm() &&
1738 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1739 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
1740 // Shift of #32 is encoded as 0 where permitted
1741 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1742 Inst.addOperand(MCOperand::createImm(
1743 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1746 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1747 assert(N == 1 && "Invalid number of operands!");
1748 Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
1752 void addRegListOperands(MCInst &Inst, unsigned N) const {
1753 assert(N == 1 && "Invalid number of operands!");
1754 const SmallVectorImpl<unsigned> &RegList = getRegList();
1755 for (SmallVectorImpl<unsigned>::const_iterator
1756 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1757 Inst.addOperand(MCOperand::createReg(*I));
1760 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1761 addRegListOperands(Inst, N);
1764 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1765 addRegListOperands(Inst, N);
1768 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1769 assert(N == 1 && "Invalid number of operands!");
1770 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1771 Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
1774 void addModImmOperands(MCInst &Inst, unsigned N) const {
1775 assert(N == 1 && "Invalid number of operands!");
1777 // Support for fixups (MCFixup)
1779 return addImmOperands(Inst, N);
1781 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
1784 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
1785 assert(N == 1 && "Invalid number of operands!");
1786 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1787 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
1788 Inst.addOperand(MCOperand::createImm(Enc));
1791 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
1792 assert(N == 1 && "Invalid number of operands!");
1793 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1794 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
1795 Inst.addOperand(MCOperand::createImm(Enc));
1798 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1799 assert(N == 1 && "Invalid number of operands!");
1800 // Munge the lsb/width into a bitfield mask.
1801 unsigned lsb = Bitfield.LSB;
1802 unsigned width = Bitfield.Width;
1803 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1804 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1805 (32 - (lsb + width)));
1806 Inst.addOperand(MCOperand::createImm(Mask));
1809 void addImmOperands(MCInst &Inst, unsigned N) const {
1810 assert(N == 1 && "Invalid number of operands!");
1811 addExpr(Inst, getImm());
1814 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1815 assert(N == 1 && "Invalid number of operands!");
1816 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1817 Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
1820 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1821 assert(N == 1 && "Invalid number of operands!");
1822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1823 Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
1826 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1827 assert(N == 1 && "Invalid number of operands!");
1828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1829 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1830 Inst.addOperand(MCOperand::createImm(Val));
1833 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1834 assert(N == 1 && "Invalid number of operands!");
1835 // FIXME: We really want to scale the value here, but the LDRD/STRD
1836 // instruction don't encode operands that way yet.
1837 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1838 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1841 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1842 assert(N == 1 && "Invalid number of operands!");
1843 // The immediate is scaled by four in the encoding and is stored
1844 // in the MCInst as such. Lop off the low two bits here.
1845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1846 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
1849 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1850 assert(N == 1 && "Invalid number of operands!");
1851 // The immediate is scaled by four in the encoding and is stored
1852 // in the MCInst as such. Lop off the low two bits here.
1853 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1854 Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
1857 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1858 assert(N == 1 && "Invalid number of operands!");
1859 // The immediate is scaled by four in the encoding and is stored
1860 // in the MCInst as such. Lop off the low two bits here.
1861 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1862 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
1865 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1866 assert(N == 1 && "Invalid number of operands!");
1867 // The constant encodes as the immediate-1, and we store in the instruction
1868 // the bits as encoded, so subtract off one here.
1869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1870 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
1873 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1874 assert(N == 1 && "Invalid number of operands!");
1875 // The constant encodes as the immediate-1, and we store in the instruction
1876 // the bits as encoded, so subtract off one here.
1877 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1878 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
1881 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1882 assert(N == 1 && "Invalid number of operands!");
1883 // The constant encodes as the immediate, except for 32, which encodes as
1885 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1886 unsigned Imm = CE->getValue();
1887 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
1890 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1891 assert(N == 1 && "Invalid number of operands!");
1892 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1893 // the instruction as well.
1894 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1895 int Val = CE->getValue();
1896 Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
1899 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1900 assert(N == 1 && "Invalid number of operands!");
1901 // The operand is actually a t2_so_imm, but we have its bitwise
1902 // negation in the assembly source, so twiddle it here.
1903 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1904 Inst.addOperand(MCOperand::createImm(~CE->getValue()));
1907 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1908 assert(N == 1 && "Invalid number of operands!");
1909 // The operand is actually a t2_so_imm, but we have its
1910 // negation in the assembly source, so twiddle it here.
1911 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1912 Inst.addOperand(MCOperand::createImm(-CE->getValue()));
1915 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1916 assert(N == 1 && "Invalid number of operands!");
1917 // The operand is actually an imm0_4095, but we have its
1918 // negation in the assembly source, so twiddle it here.
1919 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1920 Inst.addOperand(MCOperand::createImm(-CE->getValue()));
1923 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1924 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1925 Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
1929 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1930 assert(SR && "Unknown value type!");
1931 Inst.addOperand(MCOperand::createExpr(SR));
1934 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1935 assert(N == 1 && "Invalid number of operands!");
1937 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1939 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1943 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1944 assert(SR && "Unknown value type!");
1945 Inst.addOperand(MCOperand::createExpr(SR));
1949 assert(isMem() && "Unknown value type!");
1950 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1951 Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
1954 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1955 assert(N == 1 && "Invalid number of operands!");
1956 Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
1959 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1960 assert(N == 1 && "Invalid number of operands!");
1961 Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
1964 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1965 assert(N == 1 && "Invalid number of operands!");
1966 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
1969 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1970 assert(N == 1 && "Invalid number of operands!");
1971 int32_t Imm = Memory.OffsetImm->getValue();
1972 Inst.addOperand(MCOperand::createImm(Imm));
1975 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1976 assert(N == 1 && "Invalid number of operands!");
1977 assert(isImm() && "Not an immediate!");
1979 // If we have an immediate that's not a constant, treat it as a label
1980 // reference needing a fixup.
1981 if (!isa<MCConstantExpr>(getImm())) {
1982 Inst.addOperand(MCOperand::createExpr(getImm()));
1986 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1987 int Val = CE->getValue();
1988 Inst.addOperand(MCOperand::createImm(Val));
1991 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1992 assert(N == 2 && "Invalid number of operands!");
1993 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
1994 Inst.addOperand(MCOperand::createImm(Memory.Alignment));
1997 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
1998 addAlignedMemoryOperands(Inst, N);
2001 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2002 addAlignedMemoryOperands(Inst, N);
2005 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2006 addAlignedMemoryOperands(Inst, N);
2009 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2010 addAlignedMemoryOperands(Inst, N);
2013 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2014 addAlignedMemoryOperands(Inst, N);
2017 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2018 addAlignedMemoryOperands(Inst, N);
2021 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2022 addAlignedMemoryOperands(Inst, N);
2025 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2026 addAlignedMemoryOperands(Inst, N);
2029 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2030 addAlignedMemoryOperands(Inst, N);
2033 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2034 addAlignedMemoryOperands(Inst, N);
2037 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2038 addAlignedMemoryOperands(Inst, N);
2041 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2042 assert(N == 3 && "Invalid number of operands!");
2043 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2044 if (!Memory.OffsetRegNum) {
2045 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2046 // Special case for #-0
2047 if (Val == INT32_MIN) Val = 0;
2048 if (Val < 0) Val = -Val;
2049 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2051 // For register offset, we encode the shift type and negation flag
2053 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2054 Memory.ShiftImm, Memory.ShiftType);
2056 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2057 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2058 Inst.addOperand(MCOperand::createImm(Val));
2061 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2062 assert(N == 2 && "Invalid number of operands!");
2063 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2064 assert(CE && "non-constant AM2OffsetImm operand!");
2065 int32_t Val = CE->getValue();
2066 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2067 // Special case for #-0
2068 if (Val == INT32_MIN) Val = 0;
2069 if (Val < 0) Val = -Val;
2070 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2071 Inst.addOperand(MCOperand::createReg(0));
2072 Inst.addOperand(MCOperand::createImm(Val));
2075 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2076 assert(N == 3 && "Invalid number of operands!");
2077 // If we have an immediate that's not a constant, treat it as a label
2078 // reference needing a fixup. If it is a constant, it's something else
2079 // and we reject it.
2081 Inst.addOperand(MCOperand::createExpr(getImm()));
2082 Inst.addOperand(MCOperand::createReg(0));
2083 Inst.addOperand(MCOperand::createImm(0));
2087 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2088 if (!Memory.OffsetRegNum) {
2089 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2090 // Special case for #-0
2091 if (Val == INT32_MIN) Val = 0;
2092 if (Val < 0) Val = -Val;
2093 Val = ARM_AM::getAM3Opc(AddSub, Val);
2095 // For register offset, we encode the shift type and negation flag
2097 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2099 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2100 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2101 Inst.addOperand(MCOperand::createImm(Val));
2104 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2105 assert(N == 2 && "Invalid number of operands!");
2106 if (Kind == k_PostIndexRegister) {
2108 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2109 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2110 Inst.addOperand(MCOperand::createImm(Val));
2115 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2116 int32_t Val = CE->getValue();
2117 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2118 // Special case for #-0
2119 if (Val == INT32_MIN) Val = 0;
2120 if (Val < 0) Val = -Val;
2121 Val = ARM_AM::getAM3Opc(AddSub, Val);
2122 Inst.addOperand(MCOperand::createReg(0));
2123 Inst.addOperand(MCOperand::createImm(Val));
2126 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2127 assert(N == 2 && "Invalid number of operands!");
2128 // If we have an immediate that's not a constant, treat it as a label
2129 // reference needing a fixup. If it is a constant, it's something else
2130 // and we reject it.
2132 Inst.addOperand(MCOperand::createExpr(getImm()));
2133 Inst.addOperand(MCOperand::createImm(0));
2137 // The lower two bits are always zero and as such are not encoded.
2138 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2139 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2140 // Special case for #-0
2141 if (Val == INT32_MIN) Val = 0;
2142 if (Val < 0) Val = -Val;
2143 Val = ARM_AM::getAM5Opc(AddSub, Val);
2144 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2145 Inst.addOperand(MCOperand::createImm(Val));
2148 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2149 assert(N == 2 && "Invalid number of operands!");
2150 // If we have an immediate that's not a constant, treat it as a label
2151 // reference needing a fixup. If it is a constant, it's something else
2152 // and we reject it.
2154 Inst.addOperand(MCOperand::createExpr(getImm()));
2155 Inst.addOperand(MCOperand::createImm(0));
2159 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2160 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2161 Inst.addOperand(MCOperand::createImm(Val));
2164 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2165 assert(N == 2 && "Invalid number of operands!");
2166 // The lower two bits are always zero and as such are not encoded.
2167 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2168 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2169 Inst.addOperand(MCOperand::createImm(Val));
2172 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2173 assert(N == 2 && "Invalid number of operands!");
2174 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2175 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2176 Inst.addOperand(MCOperand::createImm(Val));
2179 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2180 addMemImm8OffsetOperands(Inst, N);
2183 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2184 addMemImm8OffsetOperands(Inst, N);
2187 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2188 assert(N == 2 && "Invalid number of operands!");
2189 // If this is an immediate, it's a label reference.
2191 addExpr(Inst, getImm());
2192 Inst.addOperand(MCOperand::createImm(0));
2196 // Otherwise, it's a normal memory reg+offset.
2197 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2198 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2199 Inst.addOperand(MCOperand::createImm(Val));
2202 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2203 assert(N == 2 && "Invalid number of operands!");
2204 // If this is an immediate, it's a label reference.
2206 addExpr(Inst, getImm());
2207 Inst.addOperand(MCOperand::createImm(0));
2211 // Otherwise, it's a normal memory reg+offset.
2212 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2213 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2214 Inst.addOperand(MCOperand::createImm(Val));
2217 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2218 assert(N == 2 && "Invalid number of operands!");
2219 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2220 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2223 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2224 assert(N == 2 && "Invalid number of operands!");
2225 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2226 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2229 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2230 assert(N == 3 && "Invalid number of operands!");
2232 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2233 Memory.ShiftImm, Memory.ShiftType);
2234 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2235 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2236 Inst.addOperand(MCOperand::createImm(Val));
2239 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2240 assert(N == 3 && "Invalid number of operands!");
2241 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2242 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2243 Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
2246 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2247 assert(N == 2 && "Invalid number of operands!");
2248 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2249 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2252 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2253 assert(N == 2 && "Invalid number of operands!");
2254 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2255 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2256 Inst.addOperand(MCOperand::createImm(Val));
2259 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2260 assert(N == 2 && "Invalid number of operands!");
2261 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2262 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2263 Inst.addOperand(MCOperand::createImm(Val));
2266 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2267 assert(N == 2 && "Invalid number of operands!");
2268 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2269 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2270 Inst.addOperand(MCOperand::createImm(Val));
2273 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2274 assert(N == 2 && "Invalid number of operands!");
2275 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2276 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2277 Inst.addOperand(MCOperand::createImm(Val));
2280 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2281 assert(N == 1 && "Invalid number of operands!");
2282 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2283 assert(CE && "non-constant post-idx-imm8 operand!");
2284 int Imm = CE->getValue();
2285 bool isAdd = Imm >= 0;
2286 if (Imm == INT32_MIN) Imm = 0;
2287 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2288 Inst.addOperand(MCOperand::createImm(Imm));
2291 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2292 assert(N == 1 && "Invalid number of operands!");
2293 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2294 assert(CE && "non-constant post-idx-imm8s4 operand!");
2295 int Imm = CE->getValue();
2296 bool isAdd = Imm >= 0;
2297 if (Imm == INT32_MIN) Imm = 0;
2298 // Immediate is scaled by 4.
2299 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2300 Inst.addOperand(MCOperand::createImm(Imm));
2303 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2304 assert(N == 2 && "Invalid number of operands!");
2305 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2306 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
2309 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2310 assert(N == 2 && "Invalid number of operands!");
2311 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2312 // The sign, shift type, and shift amount are encoded in a single operand
2313 // using the AM2 encoding helpers.
2314 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2315 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2316 PostIdxReg.ShiftTy);
2317 Inst.addOperand(MCOperand::createImm(Imm));
2320 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2321 assert(N == 1 && "Invalid number of operands!");
2322 Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
2325 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2326 assert(N == 1 && "Invalid number of operands!");
2327 Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
2330 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2331 assert(N == 1 && "Invalid number of operands!");
2332 Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
2335 void addVecListOperands(MCInst &Inst, unsigned N) const {
2336 assert(N == 1 && "Invalid number of operands!");
2337 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2340 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2341 assert(N == 2 && "Invalid number of operands!");
2342 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2343 Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
2346 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2347 assert(N == 1 && "Invalid number of operands!");
2348 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2351 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2352 assert(N == 1 && "Invalid number of operands!");
2353 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2356 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2357 assert(N == 1 && "Invalid number of operands!");
2358 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2361 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2362 assert(N == 1 && "Invalid number of operands!");
2363 // The immediate encodes the type of constant as well as the value.
2364 // Mask in that this is an i8 splat.
2365 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2366 Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
2369 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2370 assert(N == 1 && "Invalid number of operands!");
2371 // The immediate encodes the type of constant as well as the value.
2372 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2373 unsigned Value = CE->getValue();
2374 Value = ARM_AM::encodeNEONi16splat(Value);
2375 Inst.addOperand(MCOperand::createImm(Value));
2378 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2379 assert(N == 1 && "Invalid number of operands!");
2380 // The immediate encodes the type of constant as well as the value.
2381 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2382 unsigned Value = CE->getValue();
2383 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2384 Inst.addOperand(MCOperand::createImm(Value));
2387 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2388 assert(N == 1 && "Invalid number of operands!");
2389 // The immediate encodes the type of constant as well as the value.
2390 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2391 unsigned Value = CE->getValue();
2392 Value = ARM_AM::encodeNEONi32splat(Value);
2393 Inst.addOperand(MCOperand::createImm(Value));
2396 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2397 assert(N == 1 && "Invalid number of operands!");
2398 // The immediate encodes the type of constant as well as the value.
2399 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2400 unsigned Value = CE->getValue();
2401 Value = ARM_AM::encodeNEONi32splat(~Value);
2402 Inst.addOperand(MCOperand::createImm(Value));
2405 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2406 assert(N == 1 && "Invalid number of operands!");
2407 // The immediate encodes the type of constant as well as the value.
2408 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2409 unsigned Value = CE->getValue();
2410 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2411 Inst.getOpcode() == ARM::VMOVv16i8) &&
2412 "All vmvn instructions that wants to replicate non-zero byte "
2413 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2414 unsigned B = ((~Value) & 0xff);
2415 B |= 0xe00; // cmode = 0b1110
2416 Inst.addOperand(MCOperand::createImm(B));
2418 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2419 assert(N == 1 && "Invalid number of operands!");
2420 // The immediate encodes the type of constant as well as the value.
2421 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2422 unsigned Value = CE->getValue();
2423 if (Value >= 256 && Value <= 0xffff)
2424 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2425 else if (Value > 0xffff && Value <= 0xffffff)
2426 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2427 else if (Value > 0xffffff)
2428 Value = (Value >> 24) | 0x600;
2429 Inst.addOperand(MCOperand::createImm(Value));
2432 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2433 assert(N == 1 && "Invalid number of operands!");
2434 // The immediate encodes the type of constant as well as the value.
2435 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2436 unsigned Value = CE->getValue();
2437 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2438 Inst.getOpcode() == ARM::VMOVv16i8) &&
2439 "All instructions that wants to replicate non-zero byte "
2440 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2441 unsigned B = Value & 0xff;
2442 B |= 0xe00; // cmode = 0b1110
2443 Inst.addOperand(MCOperand::createImm(B));
2445 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2446 assert(N == 1 && "Invalid number of operands!");
2447 // The immediate encodes the type of constant as well as the value.
2448 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2449 unsigned Value = ~CE->getValue();
2450 if (Value >= 256 && Value <= 0xffff)
2451 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2452 else if (Value > 0xffff && Value <= 0xffffff)
2453 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2454 else if (Value > 0xffffff)
2455 Value = (Value >> 24) | 0x600;
2456 Inst.addOperand(MCOperand::createImm(Value));
2459 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2460 assert(N == 1 && "Invalid number of operands!");
2461 // The immediate encodes the type of constant as well as the value.
2462 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2463 uint64_t Value = CE->getValue();
2465 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2466 Imm |= (Value & 1) << i;
2468 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
2471 void print(raw_ostream &OS) const override;
2473 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2474 auto Op = make_unique<ARMOperand>(k_ITCondMask);
2475 Op->ITMask.Mask = Mask;
2481 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2483 auto Op = make_unique<ARMOperand>(k_CondCode);
2490 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2491 auto Op = make_unique<ARMOperand>(k_CoprocNum);
2492 Op->Cop.Val = CopVal;
2498 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2499 auto Op = make_unique<ARMOperand>(k_CoprocReg);
2500 Op->Cop.Val = CopVal;
2506 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2508 auto Op = make_unique<ARMOperand>(k_CoprocOption);
2515 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2516 auto Op = make_unique<ARMOperand>(k_CCOut);
2517 Op->Reg.RegNum = RegNum;
2523 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2524 auto Op = make_unique<ARMOperand>(k_Token);
2525 Op->Tok.Data = Str.data();
2526 Op->Tok.Length = Str.size();
2532 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2534 auto Op = make_unique<ARMOperand>(k_Register);
2535 Op->Reg.RegNum = RegNum;
2541 static std::unique_ptr<ARMOperand>
2542 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2543 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2545 auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2546 Op->RegShiftedReg.ShiftTy = ShTy;
2547 Op->RegShiftedReg.SrcReg = SrcReg;
2548 Op->RegShiftedReg.ShiftReg = ShiftReg;
2549 Op->RegShiftedReg.ShiftImm = ShiftImm;
2555 static std::unique_ptr<ARMOperand>
2556 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2557 unsigned ShiftImm, SMLoc S, SMLoc E) {
2558 auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2559 Op->RegShiftedImm.ShiftTy = ShTy;
2560 Op->RegShiftedImm.SrcReg = SrcReg;
2561 Op->RegShiftedImm.ShiftImm = ShiftImm;
2567 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2569 auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2570 Op->ShifterImm.isASR = isASR;
2571 Op->ShifterImm.Imm = Imm;
2577 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2579 auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2580 Op->RotImm.Imm = Imm;
2586 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
2588 auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
2589 Op->ModImm.Bits = Bits;
2590 Op->ModImm.Rot = Rot;
2596 static std::unique_ptr<ARMOperand>
2597 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2598 auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2599 Op->Bitfield.LSB = LSB;
2600 Op->Bitfield.Width = Width;
2606 static std::unique_ptr<ARMOperand>
2607 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2608 SMLoc StartLoc, SMLoc EndLoc) {
2609 assert (Regs.size() > 0 && "RegList contains no registers?");
2610 KindTy Kind = k_RegisterList;
2612 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2613 Kind = k_DPRRegisterList;
2614 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2615 contains(Regs.front().second))
2616 Kind = k_SPRRegisterList;
2618 // Sort based on the register encoding values.
2619 array_pod_sort(Regs.begin(), Regs.end());
2621 auto Op = make_unique<ARMOperand>(Kind);
2622 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2623 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2624 Op->Registers.push_back(I->second);
2625 Op->StartLoc = StartLoc;
2626 Op->EndLoc = EndLoc;
2630 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2632 bool isDoubleSpaced,
2634 auto Op = make_unique<ARMOperand>(k_VectorList);
2635 Op->VectorList.RegNum = RegNum;
2636 Op->VectorList.Count = Count;
2637 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2643 static std::unique_ptr<ARMOperand>
2644 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2646 auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2647 Op->VectorList.RegNum = RegNum;
2648 Op->VectorList.Count = Count;
2649 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2655 static std::unique_ptr<ARMOperand>
2656 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2657 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2658 auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2659 Op->VectorList.RegNum = RegNum;
2660 Op->VectorList.Count = Count;
2661 Op->VectorList.LaneIndex = Index;
2662 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2668 static std::unique_ptr<ARMOperand>
2669 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2670 auto Op = make_unique<ARMOperand>(k_VectorIndex);
2671 Op->VectorIndex.Val = Idx;
2677 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2679 auto Op = make_unique<ARMOperand>(k_Immediate);
2686 static std::unique_ptr<ARMOperand>
2687 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2688 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2689 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2690 SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2691 auto Op = make_unique<ARMOperand>(k_Memory);
2692 Op->Memory.BaseRegNum = BaseRegNum;
2693 Op->Memory.OffsetImm = OffsetImm;
2694 Op->Memory.OffsetRegNum = OffsetRegNum;
2695 Op->Memory.ShiftType = ShiftType;
2696 Op->Memory.ShiftImm = ShiftImm;
2697 Op->Memory.Alignment = Alignment;
2698 Op->Memory.isNegative = isNegative;
2701 Op->AlignmentLoc = AlignmentLoc;
2705 static std::unique_ptr<ARMOperand>
2706 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2707 unsigned ShiftImm, SMLoc S, SMLoc E) {
2708 auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2709 Op->PostIdxReg.RegNum = RegNum;
2710 Op->PostIdxReg.isAdd = isAdd;
2711 Op->PostIdxReg.ShiftTy = ShiftTy;
2712 Op->PostIdxReg.ShiftImm = ShiftImm;
2718 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2720 auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2721 Op->MBOpt.Val = Opt;
2727 static std::unique_ptr<ARMOperand>
2728 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2729 auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2730 Op->ISBOpt.Val = Opt;
2736 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2738 auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2739 Op->IFlags.Val = IFlags;
2745 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2746 auto Op = make_unique<ARMOperand>(k_MSRMask);
2747 Op->MMask.Val = MMask;
2753 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
2754 auto Op = make_unique<ARMOperand>(k_BankedReg);
2755 Op->BankedReg.Val = Reg;
2762 } // end anonymous namespace.
2764 void ARMOperand::print(raw_ostream &OS) const {
2767 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2770 OS << "<ccout " << getReg() << ">";
2772 case k_ITCondMask: {
2773 static const char *const MaskStr[] = {
2774 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2775 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2777 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2778 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2782 OS << "<coprocessor number: " << getCoproc() << ">";
2785 OS << "<coprocessor register: " << getCoproc() << ">";
2787 case k_CoprocOption:
2788 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2791 OS << "<mask: " << getMSRMask() << ">";
2794 OS << "<banked reg: " << getBankedReg() << ">";
2799 case k_MemBarrierOpt:
2800 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2802 case k_InstSyncBarrierOpt:
2803 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2807 << " base:" << Memory.BaseRegNum;
2810 case k_PostIndexRegister:
2811 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2812 << PostIdxReg.RegNum;
2813 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2814 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2815 << PostIdxReg.ShiftImm;
2818 case k_ProcIFlags: {
2819 OS << "<ARM_PROC::";
2820 unsigned IFlags = getProcIFlags();
2821 for (int i=2; i >= 0; --i)
2822 if (IFlags & (1 << i))
2823 OS << ARM_PROC::IFlagsToString(1 << i);
2828 OS << "<register " << getReg() << ">";
2830 case k_ShifterImmediate:
2831 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2832 << " #" << ShifterImm.Imm << ">";
2834 case k_ShiftedRegister:
2835 OS << "<so_reg_reg "
2836 << RegShiftedReg.SrcReg << " "
2837 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2838 << " " << RegShiftedReg.ShiftReg << ">";
2840 case k_ShiftedImmediate:
2841 OS << "<so_reg_imm "
2842 << RegShiftedImm.SrcReg << " "
2843 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2844 << " #" << RegShiftedImm.ShiftImm << ">";
2846 case k_RotateImmediate:
2847 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2849 case k_ModifiedImmediate:
2850 OS << "<mod_imm #" << ModImm.Bits << ", #"
2851 << ModImm.Rot << ")>";
2853 case k_BitfieldDescriptor:
2854 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2855 << ", width: " << Bitfield.Width << ">";
2857 case k_RegisterList:
2858 case k_DPRRegisterList:
2859 case k_SPRRegisterList: {
2860 OS << "<register_list ";
2862 const SmallVectorImpl<unsigned> &RegList = getRegList();
2863 for (SmallVectorImpl<unsigned>::const_iterator
2864 I = RegList.begin(), E = RegList.end(); I != E; ) {
2866 if (++I < E) OS << ", ";
2873 OS << "<vector_list " << VectorList.Count << " * "
2874 << VectorList.RegNum << ">";
2876 case k_VectorListAllLanes:
2877 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2878 << VectorList.RegNum << ">";
2880 case k_VectorListIndexed:
2881 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2882 << VectorList.Count << " * " << VectorList.RegNum << ">";
2885 OS << "'" << getToken() << "'";
2888 OS << "<vectorindex " << getVectorIndex() << ">";
2893 /// @name Auto-generated Match Functions
2896 static unsigned MatchRegisterName(StringRef Name);
2900 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2901 SMLoc &StartLoc, SMLoc &EndLoc) {
2902 const AsmToken &Tok = getParser().getTok();
2903 StartLoc = Tok.getLoc();
2904 EndLoc = Tok.getEndLoc();
2905 RegNo = tryParseRegister();
2907 return (RegNo == (unsigned)-1);
2910 /// Try to parse a register name. The token must be an Identifier when called,
2911 /// and if it is a register name the token is eaten and the register number is
2912 /// returned. Otherwise return -1.
2914 int ARMAsmParser::tryParseRegister() {
2915 MCAsmParser &Parser = getParser();
2916 const AsmToken &Tok = Parser.getTok();
2917 if (Tok.isNot(AsmToken::Identifier)) return -1;
2919 std::string lowerCase = Tok.getString().lower();
2920 unsigned RegNum = MatchRegisterName(lowerCase);
2922 RegNum = StringSwitch<unsigned>(lowerCase)
2923 .Case("r13", ARM::SP)
2924 .Case("r14", ARM::LR)
2925 .Case("r15", ARM::PC)
2926 .Case("ip", ARM::R12)
2927 // Additional register name aliases for 'gas' compatibility.
2928 .Case("a1", ARM::R0)
2929 .Case("a2", ARM::R1)
2930 .Case("a3", ARM::R2)
2931 .Case("a4", ARM::R3)
2932 .Case("v1", ARM::R4)
2933 .Case("v2", ARM::R5)
2934 .Case("v3", ARM::R6)
2935 .Case("v4", ARM::R7)
2936 .Case("v5", ARM::R8)
2937 .Case("v6", ARM::R9)
2938 .Case("v7", ARM::R10)
2939 .Case("v8", ARM::R11)
2940 .Case("sb", ARM::R9)
2941 .Case("sl", ARM::R10)
2942 .Case("fp", ARM::R11)
2946 // Check for aliases registered via .req. Canonicalize to lower case.
2947 // That's more consistent since register names are case insensitive, and
2948 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2949 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2950 // If no match, return failure.
2951 if (Entry == RegisterReqs.end())
2953 Parser.Lex(); // Eat identifier token.
2954 return Entry->getValue();
2957 // Some FPUs only have 16 D registers, so D16-D31 are invalid
2958 if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
2961 Parser.Lex(); // Eat identifier token.
2966 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2967 // If a recoverable error occurs, return 1. If an irrecoverable error
2968 // occurs, return -1. An irrecoverable error is one where tokens have been
2969 // consumed in the process of trying to parse the shifter (i.e., when it is
2970 // indeed a shifter operand, but malformed).
2971 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
2972 MCAsmParser &Parser = getParser();
2973 SMLoc S = Parser.getTok().getLoc();
2974 const AsmToken &Tok = Parser.getTok();
2975 if (Tok.isNot(AsmToken::Identifier))
2978 std::string lowerCase = Tok.getString().lower();
2979 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2980 .Case("asl", ARM_AM::lsl)
2981 .Case("lsl", ARM_AM::lsl)
2982 .Case("lsr", ARM_AM::lsr)
2983 .Case("asr", ARM_AM::asr)
2984 .Case("ror", ARM_AM::ror)
2985 .Case("rrx", ARM_AM::rrx)
2986 .Default(ARM_AM::no_shift);
2988 if (ShiftTy == ARM_AM::no_shift)
2991 Parser.Lex(); // Eat the operator.
2993 // The source register for the shift has already been added to the
2994 // operand list, so we need to pop it off and combine it into the shifted
2995 // register operand instead.
2996 std::unique_ptr<ARMOperand> PrevOp(
2997 (ARMOperand *)Operands.pop_back_val().release());
2998 if (!PrevOp->isReg())
2999 return Error(PrevOp->getStartLoc(), "shift must be of a register");
3000 int SrcReg = PrevOp->getReg();
3005 if (ShiftTy == ARM_AM::rrx) {
3006 // RRX Doesn't have an explicit shift amount. The encoder expects
3007 // the shift register to be the same as the source register. Seems odd,
3011 // Figure out if this is shifted by a constant or a register (for non-RRX).
3012 if (Parser.getTok().is(AsmToken::Hash) ||
3013 Parser.getTok().is(AsmToken::Dollar)) {
3014 Parser.Lex(); // Eat hash.
3015 SMLoc ImmLoc = Parser.getTok().getLoc();
3016 const MCExpr *ShiftExpr = nullptr;
3017 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3018 Error(ImmLoc, "invalid immediate shift value");
3021 // The expression must be evaluatable as an immediate.
3022 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3024 Error(ImmLoc, "invalid immediate shift value");
3027 // Range check the immediate.
3028 // lsl, ror: 0 <= imm <= 31
3029 // lsr, asr: 0 <= imm <= 32
3030 Imm = CE->getValue();
3032 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3033 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3034 Error(ImmLoc, "immediate shift value out of range");
3037 // shift by zero is a nop. Always send it through as lsl.
3038 // ('as' compatibility)
3040 ShiftTy = ARM_AM::lsl;
3041 } else if (Parser.getTok().is(AsmToken::Identifier)) {
3042 SMLoc L = Parser.getTok().getLoc();
3043 EndLoc = Parser.getTok().getEndLoc();
3044 ShiftReg = tryParseRegister();
3045 if (ShiftReg == -1) {
3046 Error(L, "expected immediate or register in shift operand");
3050 Error(Parser.getTok().getLoc(),
3051 "expected immediate or register in shift operand");
3056 if (ShiftReg && ShiftTy != ARM_AM::rrx)
3057 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3061 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3068 /// Try to parse a register name. The token must be an Identifier when called.
3069 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3070 /// if there is a "writeback". 'true' if it's not a register.
3072 /// TODO this is likely to change to allow different register types and or to
3073 /// parse for a specific register type.
3074 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3075 MCAsmParser &Parser = getParser();
3076 const AsmToken &RegTok = Parser.getTok();
3077 int RegNo = tryParseRegister();
3081 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3082 RegTok.getEndLoc()));
3084 const AsmToken &ExclaimTok = Parser.getTok();
3085 if (ExclaimTok.is(AsmToken::Exclaim)) {
3086 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3087 ExclaimTok.getLoc()));
3088 Parser.Lex(); // Eat exclaim token
3092 // Also check for an index operand. This is only legal for vector registers,
3093 // but that'll get caught OK in operand matching, so we don't need to
3094 // explicitly filter everything else out here.
3095 if (Parser.getTok().is(AsmToken::LBrac)) {
3096 SMLoc SIdx = Parser.getTok().getLoc();
3097 Parser.Lex(); // Eat left bracket token.
3099 const MCExpr *ImmVal;
3100 if (getParser().parseExpression(ImmVal))
3102 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3104 return TokError("immediate value expected for vector index");
3106 if (Parser.getTok().isNot(AsmToken::RBrac))
3107 return Error(Parser.getTok().getLoc(), "']' expected");
3109 SMLoc E = Parser.getTok().getEndLoc();
3110 Parser.Lex(); // Eat right bracket token.
3112 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3120 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3121 /// instruction with a symbolic operand name.
3122 /// We accept "crN" syntax for GAS compatibility.
3123 /// <operand-name> ::= <prefix><number>
3124 /// If CoprocOp is 'c', then:
3125 /// <prefix> ::= c | cr
3126 /// If CoprocOp is 'p', then :
3128 /// <number> ::= integer in range [0, 15]
3129 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3130 // Use the same layout as the tablegen'erated register name matcher. Ugly,
3132 if (Name.size() < 2 || Name[0] != CoprocOp)
3134 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3136 switch (Name.size()) {
3157 // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3158 // However, old cores (v5/v6) did use them in that way.
3159 case '0': return 10;
3160 case '1': return 11;
3161 case '2': return 12;
3162 case '3': return 13;
3163 case '4': return 14;
3164 case '5': return 15;
3169 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3170 ARMAsmParser::OperandMatchResultTy
3171 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3172 MCAsmParser &Parser = getParser();
3173 SMLoc S = Parser.getTok().getLoc();
3174 const AsmToken &Tok = Parser.getTok();
3175 if (!Tok.is(AsmToken::Identifier))
3176 return MatchOperand_NoMatch;
3177 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3178 .Case("eq", ARMCC::EQ)
3179 .Case("ne", ARMCC::NE)
3180 .Case("hs", ARMCC::HS)
3181 .Case("cs", ARMCC::HS)
3182 .Case("lo", ARMCC::LO)
3183 .Case("cc", ARMCC::LO)
3184 .Case("mi", ARMCC::MI)
3185 .Case("pl", ARMCC::PL)
3186 .Case("vs", ARMCC::VS)
3187 .Case("vc", ARMCC::VC)
3188 .Case("hi", ARMCC::HI)
3189 .Case("ls", ARMCC::LS)
3190 .Case("ge", ARMCC::GE)
3191 .Case("lt", ARMCC::LT)
3192 .Case("gt", ARMCC::GT)
3193 .Case("le", ARMCC::LE)
3194 .Case("al", ARMCC::AL)
3197 return MatchOperand_NoMatch;
3198 Parser.Lex(); // Eat the token.
3200 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3202 return MatchOperand_Success;
3205 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3206 /// token must be an Identifier when called, and if it is a coprocessor
3207 /// number, the token is eaten and the operand is added to the operand list.
3208 ARMAsmParser::OperandMatchResultTy
3209 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3210 MCAsmParser &Parser = getParser();
3211 SMLoc S = Parser.getTok().getLoc();
3212 const AsmToken &Tok = Parser.getTok();
3213 if (Tok.isNot(AsmToken::Identifier))
3214 return MatchOperand_NoMatch;
3216 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3218 return MatchOperand_NoMatch;
3219 // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3220 if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3221 return MatchOperand_NoMatch;
3223 Parser.Lex(); // Eat identifier token.
3224 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3225 return MatchOperand_Success;
3228 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3229 /// token must be an Identifier when called, and if it is a coprocessor
3230 /// number, the token is eaten and the operand is added to the operand list.
3231 ARMAsmParser::OperandMatchResultTy
3232 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3233 MCAsmParser &Parser = getParser();
3234 SMLoc S = Parser.getTok().getLoc();
3235 const AsmToken &Tok = Parser.getTok();
3236 if (Tok.isNot(AsmToken::Identifier))
3237 return MatchOperand_NoMatch;
3239 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3241 return MatchOperand_NoMatch;
3243 Parser.Lex(); // Eat identifier token.
3244 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3245 return MatchOperand_Success;
3248 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3249 /// coproc_option : '{' imm0_255 '}'
3250 ARMAsmParser::OperandMatchResultTy
3251 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3252 MCAsmParser &Parser = getParser();
3253 SMLoc S = Parser.getTok().getLoc();
3255 // If this isn't a '{', this isn't a coprocessor immediate operand.
3256 if (Parser.getTok().isNot(AsmToken::LCurly))
3257 return MatchOperand_NoMatch;
3258 Parser.Lex(); // Eat the '{'
3261 SMLoc Loc = Parser.getTok().getLoc();
3262 if (getParser().parseExpression(Expr)) {
3263 Error(Loc, "illegal expression");
3264 return MatchOperand_ParseFail;
3266 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3267 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3268 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3269 return MatchOperand_ParseFail;
3271 int Val = CE->getValue();
3273 // Check for and consume the closing '}'
3274 if (Parser.getTok().isNot(AsmToken::RCurly))
3275 return MatchOperand_ParseFail;
3276 SMLoc E = Parser.getTok().getEndLoc();
3277 Parser.Lex(); // Eat the '}'
3279 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3280 return MatchOperand_Success;
3283 // For register list parsing, we need to map from raw GPR register numbering
3284 // to the enumeration values. The enumeration values aren't sorted by
3285 // register number due to our using "sp", "lr" and "pc" as canonical names.
3286 static unsigned getNextRegister(unsigned Reg) {
3287 // If this is a GPR, we need to do it manually, otherwise we can rely
3288 // on the sort ordering of the enumeration since the other reg-classes
3290 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3293 default: llvm_unreachable("Invalid GPR number!");
3294 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3295 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3296 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3297 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3298 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3299 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3300 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3301 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3305 // Return the low-subreg of a given Q register.
3306 static unsigned getDRegFromQReg(unsigned QReg) {
3308 default: llvm_unreachable("expected a Q register!");
3309 case ARM::Q0: return ARM::D0;
3310 case ARM::Q1: return ARM::D2;
3311 case ARM::Q2: return ARM::D4;
3312 case ARM::Q3: return ARM::D6;
3313 case ARM::Q4: return ARM::D8;
3314 case ARM::Q5: return ARM::D10;
3315 case ARM::Q6: return ARM::D12;
3316 case ARM::Q7: return ARM::D14;
3317 case ARM::Q8: return ARM::D16;
3318 case ARM::Q9: return ARM::D18;
3319 case ARM::Q10: return ARM::D20;
3320 case ARM::Q11: return ARM::D22;
3321 case ARM::Q12: return ARM::D24;
3322 case ARM::Q13: return ARM::D26;
3323 case ARM::Q14: return ARM::D28;
3324 case ARM::Q15: return ARM::D30;
3328 /// Parse a register list.
3329 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3330 MCAsmParser &Parser = getParser();
3331 assert(Parser.getTok().is(AsmToken::LCurly) &&
3332 "Token is not a Left Curly Brace");
3333 SMLoc S = Parser.getTok().getLoc();
3334 Parser.Lex(); // Eat '{' token.
3335 SMLoc RegLoc = Parser.getTok().getLoc();
3337 // Check the first register in the list to see what register class
3338 // this is a list of.
3339 int Reg = tryParseRegister();
3341 return Error(RegLoc, "register expected");
3343 // The reglist instructions have at most 16 registers, so reserve
3344 // space for that many.
3346 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3348 // Allow Q regs and just interpret them as the two D sub-registers.
3349 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3350 Reg = getDRegFromQReg(Reg);
3351 EReg = MRI->getEncodingValue(Reg);
3352 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3355 const MCRegisterClass *RC;
3356 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3357 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3358 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3359 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3360 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3361 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3363 return Error(RegLoc, "invalid register in register list");
3365 // Store the register.
3366 EReg = MRI->getEncodingValue(Reg);
3367 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3369 // This starts immediately after the first register token in the list,
3370 // so we can see either a comma or a minus (range separator) as a legal
3372 while (Parser.getTok().is(AsmToken::Comma) ||
3373 Parser.getTok().is(AsmToken::Minus)) {
3374 if (Parser.getTok().is(AsmToken::Minus)) {
3375 Parser.Lex(); // Eat the minus.
3376 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3377 int EndReg = tryParseRegister();
3379 return Error(AfterMinusLoc, "register expected");
3380 // Allow Q regs and just interpret them as the two D sub-registers.
3381 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3382 EndReg = getDRegFromQReg(EndReg) + 1;
3383 // If the register is the same as the start reg, there's nothing
3387 // The register must be in the same register class as the first.
3388 if (!RC->contains(EndReg))
3389 return Error(AfterMinusLoc, "invalid register in register list");
3390 // Ranges must go from low to high.
3391 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3392 return Error(AfterMinusLoc, "bad range in register list");
3394 // Add all the registers in the range to the register list.
3395 while (Reg != EndReg) {
3396 Reg = getNextRegister(Reg);
3397 EReg = MRI->getEncodingValue(Reg);
3398 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3402 Parser.Lex(); // Eat the comma.
3403 RegLoc = Parser.getTok().getLoc();
3405 const AsmToken RegTok = Parser.getTok();
3406 Reg = tryParseRegister();
3408 return Error(RegLoc, "register expected");
3409 // Allow Q regs and just interpret them as the two D sub-registers.
3410 bool isQReg = false;
3411 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3412 Reg = getDRegFromQReg(Reg);
3415 // The register must be in the same register class as the first.
3416 if (!RC->contains(Reg))
3417 return Error(RegLoc, "invalid register in register list");
3418 // List must be monotonically increasing.
3419 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3420 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3421 Warning(RegLoc, "register list not in ascending order");
3423 return Error(RegLoc, "register list not in ascending order");
3425 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3426 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3427 ") in register list");
3430 // VFP register lists must also be contiguous.
3431 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3433 return Error(RegLoc, "non-contiguous register range");
3434 EReg = MRI->getEncodingValue(Reg);
3435 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3437 EReg = MRI->getEncodingValue(++Reg);
3438 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3442 if (Parser.getTok().isNot(AsmToken::RCurly))
3443 return Error(Parser.getTok().getLoc(), "'}' expected");
3444 SMLoc E = Parser.getTok().getEndLoc();
3445 Parser.Lex(); // Eat '}' token.
3447 // Push the register list operand.
3448 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3450 // The ARM system instruction variants for LDM/STM have a '^' token here.
3451 if (Parser.getTok().is(AsmToken::Caret)) {
3452 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3453 Parser.Lex(); // Eat '^' token.
3459 // Helper function to parse the lane index for vector lists.
3460 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3461 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3462 MCAsmParser &Parser = getParser();
3463 Index = 0; // Always return a defined index value.
3464 if (Parser.getTok().is(AsmToken::LBrac)) {
3465 Parser.Lex(); // Eat the '['.
3466 if (Parser.getTok().is(AsmToken::RBrac)) {
3467 // "Dn[]" is the 'all lanes' syntax.
3468 LaneKind = AllLanes;
3469 EndLoc = Parser.getTok().getEndLoc();
3470 Parser.Lex(); // Eat the ']'.
3471 return MatchOperand_Success;
3474 // There's an optional '#' token here. Normally there wouldn't be, but
3475 // inline assemble puts one in, and it's friendly to accept that.
3476 if (Parser.getTok().is(AsmToken::Hash))
3477 Parser.Lex(); // Eat '#' or '$'.
3479 const MCExpr *LaneIndex;
3480 SMLoc Loc = Parser.getTok().getLoc();
3481 if (getParser().parseExpression(LaneIndex)) {
3482 Error(Loc, "illegal expression");
3483 return MatchOperand_ParseFail;
3485 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3487 Error(Loc, "lane index must be empty or an integer");
3488 return MatchOperand_ParseFail;
3490 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3491 Error(Parser.getTok().getLoc(), "']' expected");
3492 return MatchOperand_ParseFail;
3494 EndLoc = Parser.getTok().getEndLoc();
3495 Parser.Lex(); // Eat the ']'.
3496 int64_t Val = CE->getValue();
3498 // FIXME: Make this range check context sensitive for .8, .16, .32.
3499 if (Val < 0 || Val > 7) {
3500 Error(Parser.getTok().getLoc(), "lane index out of range");
3501 return MatchOperand_ParseFail;
3504 LaneKind = IndexedLane;
3505 return MatchOperand_Success;
3508 return MatchOperand_Success;
3511 // parse a vector register list
3512 ARMAsmParser::OperandMatchResultTy
3513 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3514 MCAsmParser &Parser = getParser();
3515 VectorLaneTy LaneKind;
3517 SMLoc S = Parser.getTok().getLoc();
3518 // As an extension (to match gas), support a plain D register or Q register
3519 // (without encosing curly braces) as a single or double entry list,
3521 if (Parser.getTok().is(AsmToken::Identifier)) {
3522 SMLoc E = Parser.getTok().getEndLoc();
3523 int Reg = tryParseRegister();
3525 return MatchOperand_NoMatch;
3526 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3527 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3528 if (Res != MatchOperand_Success)
3532 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3535 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3539 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3544 return MatchOperand_Success;
3546 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3547 Reg = getDRegFromQReg(Reg);
3548 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3549 if (Res != MatchOperand_Success)
3553 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3554 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3555 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3558 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3559 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3560 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3564 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3569 return MatchOperand_Success;
3571 Error(S, "vector register expected");
3572 return MatchOperand_ParseFail;
3575 if (Parser.getTok().isNot(AsmToken::LCurly))
3576 return MatchOperand_NoMatch;
3578 Parser.Lex(); // Eat '{' token.
3579 SMLoc RegLoc = Parser.getTok().getLoc();
3581 int Reg = tryParseRegister();
3583 Error(RegLoc, "register expected");
3584 return MatchOperand_ParseFail;
3588 unsigned FirstReg = Reg;
3589 // The list is of D registers, but we also allow Q regs and just interpret
3590 // them as the two D sub-registers.
3591 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3592 FirstReg = Reg = getDRegFromQReg(Reg);
3593 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3594 // it's ambiguous with four-register single spaced.
3600 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3601 return MatchOperand_ParseFail;
3603 while (Parser.getTok().is(AsmToken::Comma) ||
3604 Parser.getTok().is(AsmToken::Minus)) {
3605 if (Parser.getTok().is(AsmToken::Minus)) {
3607 Spacing = 1; // Register range implies a single spaced list.
3608 else if (Spacing == 2) {
3609 Error(Parser.getTok().getLoc(),
3610 "sequential registers in double spaced list");
3611 return MatchOperand_ParseFail;
3613 Parser.Lex(); // Eat the minus.
3614 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3615 int EndReg = tryParseRegister();
3617 Error(AfterMinusLoc, "register expected");
3618 return MatchOperand_ParseFail;
3620 // Allow Q regs and just interpret them as the two D sub-registers.
3621 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3622 EndReg = getDRegFromQReg(EndReg) + 1;
3623 // If the register is the same as the start reg, there's nothing
3627 // The register must be in the same register class as the first.
3628 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3629 Error(AfterMinusLoc, "invalid register in register list");
3630 return MatchOperand_ParseFail;
3632 // Ranges must go from low to high.
3634 Error(AfterMinusLoc, "bad range in register list");
3635 return MatchOperand_ParseFail;
3637 // Parse the lane specifier if present.
3638 VectorLaneTy NextLaneKind;
3639 unsigned NextLaneIndex;
3640 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3641 MatchOperand_Success)
3642 return MatchOperand_ParseFail;
3643 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3644 Error(AfterMinusLoc, "mismatched lane index in register list");
3645 return MatchOperand_ParseFail;
3648 // Add all the registers in the range to the register list.
3649 Count += EndReg - Reg;
3653 Parser.Lex(); // Eat the comma.
3654 RegLoc = Parser.getTok().getLoc();
3656 Reg = tryParseRegister();
3658 Error(RegLoc, "register expected");
3659 return MatchOperand_ParseFail;
3661 // vector register lists must be contiguous.
3662 // It's OK to use the enumeration values directly here rather, as the
3663 // VFP register classes have the enum sorted properly.
3665 // The list is of D registers, but we also allow Q regs and just interpret
3666 // them as the two D sub-registers.
3667 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3669 Spacing = 1; // Register range implies a single spaced list.
3670 else if (Spacing == 2) {
3672 "invalid register in double-spaced list (must be 'D' register')");
3673 return MatchOperand_ParseFail;
3675 Reg = getDRegFromQReg(Reg);
3676 if (Reg != OldReg + 1) {
3677 Error(RegLoc, "non-contiguous register range");
3678 return MatchOperand_ParseFail;
3682 // Parse the lane specifier if present.
3683 VectorLaneTy NextLaneKind;
3684 unsigned NextLaneIndex;
3685 SMLoc LaneLoc = Parser.getTok().getLoc();
3686 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3687 MatchOperand_Success)
3688 return MatchOperand_ParseFail;
3689 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3690 Error(LaneLoc, "mismatched lane index in register list");
3691 return MatchOperand_ParseFail;
3695 // Normal D register.
3696 // Figure out the register spacing (single or double) of the list if
3697 // we don't know it already.
3699 Spacing = 1 + (Reg == OldReg + 2);
3701 // Just check that it's contiguous and keep going.
3702 if (Reg != OldReg + Spacing) {
3703 Error(RegLoc, "non-contiguous register range");
3704 return MatchOperand_ParseFail;
3707 // Parse the lane specifier if present.
3708 VectorLaneTy NextLaneKind;
3709 unsigned NextLaneIndex;
3710 SMLoc EndLoc = Parser.getTok().getLoc();
3711 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3712 return MatchOperand_ParseFail;
3713 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3714 Error(EndLoc, "mismatched lane index in register list");
3715 return MatchOperand_ParseFail;
3719 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3720 Error(Parser.getTok().getLoc(), "'}' expected");
3721 return MatchOperand_ParseFail;
3723 E = Parser.getTok().getEndLoc();
3724 Parser.Lex(); // Eat '}' token.
3728 // Two-register operands have been converted to the
3729 // composite register classes.
3731 const MCRegisterClass *RC = (Spacing == 1) ?
3732 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3733 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3734 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3737 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3738 (Spacing == 2), S, E));
3741 // Two-register operands have been converted to the
3742 // composite register classes.
3744 const MCRegisterClass *RC = (Spacing == 1) ?
3745 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3746 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3747 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3749 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3754 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3760 return MatchOperand_Success;
3763 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3764 ARMAsmParser::OperandMatchResultTy
3765 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3766 MCAsmParser &Parser = getParser();
3767 SMLoc S = Parser.getTok().getLoc();
3768 const AsmToken &Tok = Parser.getTok();
3771 if (Tok.is(AsmToken::Identifier)) {
3772 StringRef OptStr = Tok.getString();
3774 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3775 .Case("sy", ARM_MB::SY)
3776 .Case("st", ARM_MB::ST)
3777 .Case("ld", ARM_MB::LD)
3778 .Case("sh", ARM_MB::ISH)
3779 .Case("ish", ARM_MB::ISH)
3780 .Case("shst", ARM_MB::ISHST)
3781 .Case("ishst", ARM_MB::ISHST)
3782 .Case("ishld", ARM_MB::ISHLD)
3783 .Case("nsh", ARM_MB::NSH)
3784 .Case("un", ARM_MB::NSH)
3785 .Case("nshst", ARM_MB::NSHST)
3786 .Case("nshld", ARM_MB::NSHLD)
3787 .Case("unst", ARM_MB::NSHST)
3788 .Case("osh", ARM_MB::OSH)
3789 .Case("oshst", ARM_MB::OSHST)
3790 .Case("oshld", ARM_MB::OSHLD)
3793 // ishld, oshld, nshld and ld are only available from ARMv8.
3794 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3795 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3799 return MatchOperand_NoMatch;
3801 Parser.Lex(); // Eat identifier token.
3802 } else if (Tok.is(AsmToken::Hash) ||
3803 Tok.is(AsmToken::Dollar) ||
3804 Tok.is(AsmToken::Integer)) {
3805 if (Parser.getTok().isNot(AsmToken::Integer))
3806 Parser.Lex(); // Eat '#' or '$'.
3807 SMLoc Loc = Parser.getTok().getLoc();
3809 const MCExpr *MemBarrierID;
3810 if (getParser().parseExpression(MemBarrierID)) {
3811 Error(Loc, "illegal expression");
3812 return MatchOperand_ParseFail;
3815 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3817 Error(Loc, "constant expression expected");
3818 return MatchOperand_ParseFail;
3821 int Val = CE->getValue();
3823 Error(Loc, "immediate value out of range");
3824 return MatchOperand_ParseFail;
3827 Opt = ARM_MB::RESERVED_0 + Val;
3829 return MatchOperand_ParseFail;
3831 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3832 return MatchOperand_Success;
3835 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3836 ARMAsmParser::OperandMatchResultTy
3837 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3838 MCAsmParser &Parser = getParser();
3839 SMLoc S = Parser.getTok().getLoc();
3840 const AsmToken &Tok = Parser.getTok();
3843 if (Tok.is(AsmToken::Identifier)) {
3844 StringRef OptStr = Tok.getString();
3846 if (OptStr.equals_lower("sy"))
3849 return MatchOperand_NoMatch;
3851 Parser.Lex(); // Eat identifier token.
3852 } else if (Tok.is(AsmToken::Hash) ||
3853 Tok.is(AsmToken::Dollar) ||
3854 Tok.is(AsmToken::Integer)) {
3855 if (Parser.getTok().isNot(AsmToken::Integer))
3856 Parser.Lex(); // Eat '#' or '$'.
3857 SMLoc Loc = Parser.getTok().getLoc();
3859 const MCExpr *ISBarrierID;
3860 if (getParser().parseExpression(ISBarrierID)) {
3861 Error(Loc, "illegal expression");
3862 return MatchOperand_ParseFail;
3865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3867 Error(Loc, "constant expression expected");
3868 return MatchOperand_ParseFail;
3871 int Val = CE->getValue();
3873 Error(Loc, "immediate value out of range");
3874 return MatchOperand_ParseFail;
3877 Opt = ARM_ISB::RESERVED_0 + Val;
3879 return MatchOperand_ParseFail;
3881 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3882 (ARM_ISB::InstSyncBOpt)Opt, S));
3883 return MatchOperand_Success;
3887 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3888 ARMAsmParser::OperandMatchResultTy
3889 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
3890 MCAsmParser &Parser = getParser();
3891 SMLoc S = Parser.getTok().getLoc();
3892 const AsmToken &Tok = Parser.getTok();
3893 if (!Tok.is(AsmToken::Identifier))
3894 return MatchOperand_NoMatch;
3895 StringRef IFlagsStr = Tok.getString();
3897 // An iflags string of "none" is interpreted to mean that none of the AIF
3898 // bits are set. Not a terribly useful instruction, but a valid encoding.
3899 unsigned IFlags = 0;
3900 if (IFlagsStr != "none") {
3901 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3902 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3903 .Case("a", ARM_PROC::A)
3904 .Case("i", ARM_PROC::I)
3905 .Case("f", ARM_PROC::F)
3908 // If some specific iflag is already set, it means that some letter is
3909 // present more than once, this is not acceptable.
3910 if (Flag == ~0U || (IFlags & Flag))
3911 return MatchOperand_NoMatch;
3917 Parser.Lex(); // Eat identifier token.
3918 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3919 return MatchOperand_Success;
3922 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3923 ARMAsmParser::OperandMatchResultTy
3924 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
3925 MCAsmParser &Parser = getParser();
3926 SMLoc S = Parser.getTok().getLoc();
3927 const AsmToken &Tok = Parser.getTok();
3928 if (!Tok.is(AsmToken::Identifier))
3929 return MatchOperand_NoMatch;
3930 StringRef Mask = Tok.getString();
3933 // See ARMv6-M 10.1.1
3934 std::string Name = Mask.lower();
3935 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3936 // Note: in the documentation:
3937 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3938 // for MSR APSR_nzcvq.
3939 // but we do make it an alias here. This is so to get the "mask encoding"
3940 // bits correct on MSR APSR writes.
3942 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3943 // should really only be allowed when writing a special register. Note
3944 // they get dropped in the MRS instruction reading a special register as
3945 // the SYSm field is only 8 bits.
3946 .Case("apsr", 0x800)
3947 .Case("apsr_nzcvq", 0x800)
3948 .Case("apsr_g", 0x400)
3949 .Case("apsr_nzcvqg", 0xc00)
3950 .Case("iapsr", 0x801)
3951 .Case("iapsr_nzcvq", 0x801)
3952 .Case("iapsr_g", 0x401)
3953 .Case("iapsr_nzcvqg", 0xc01)
3954 .Case("eapsr", 0x802)
3955 .Case("eapsr_nzcvq", 0x802)
3956 .Case("eapsr_g", 0x402)
3957 .Case("eapsr_nzcvqg", 0xc02)
3958 .Case("xpsr", 0x803)
3959 .Case("xpsr_nzcvq", 0x803)
3960 .Case("xpsr_g", 0x403)
3961 .Case("xpsr_nzcvqg", 0xc03)
3962 .Case("ipsr", 0x805)
3963 .Case("epsr", 0x806)
3964 .Case("iepsr", 0x807)
3967 .Case("primask", 0x810)
3968 .Case("basepri", 0x811)
3969 .Case("basepri_max", 0x812)
3970 .Case("faultmask", 0x813)
3971 .Case("control", 0x814)
3974 if (FlagsVal == ~0U)
3975 return MatchOperand_NoMatch;
3977 if (!hasDSP() && (FlagsVal & 0x400))
3978 // The _g and _nzcvqg versions are only valid if the DSP extension is
3980 return MatchOperand_NoMatch;
3982 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3983 // basepri, basepri_max and faultmask only valid for V7m.
3984 return MatchOperand_NoMatch;
3986 Parser.Lex(); // Eat identifier token.
3987 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3988 return MatchOperand_Success;
3991 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3992 size_t Start = 0, Next = Mask.find('_');
3993 StringRef Flags = "";
3994 std::string SpecReg = Mask.slice(Start, Next).lower();
3995 if (Next != StringRef::npos)
3996 Flags = Mask.slice(Next+1, Mask.size());
3998 // FlagsVal contains the complete mask:
4000 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4001 unsigned FlagsVal = 0;
4003 if (SpecReg == "apsr") {
4004 FlagsVal = StringSwitch<unsigned>(Flags)
4005 .Case("nzcvq", 0x8) // same as CPSR_f
4006 .Case("g", 0x4) // same as CPSR_s
4007 .Case("nzcvqg", 0xc) // same as CPSR_fs
4010 if (FlagsVal == ~0U) {
4012 return MatchOperand_NoMatch;
4014 FlagsVal = 8; // No flag
4016 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4017 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4018 if (Flags == "all" || Flags == "")
4020 for (int i = 0, e = Flags.size(); i != e; ++i) {
4021 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4028 // If some specific flag is already set, it means that some letter is
4029 // present more than once, this is not acceptable.
4030 if (FlagsVal == ~0U || (FlagsVal & Flag))
4031 return MatchOperand_NoMatch;
4034 } else // No match for special register.
4035 return MatchOperand_NoMatch;
4037 // Special register without flags is NOT equivalent to "fc" flags.
4038 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
4039 // two lines would enable gas compatibility at the expense of breaking
4045 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4046 if (SpecReg == "spsr")
4049 Parser.Lex(); // Eat identifier token.
4050 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4051 return MatchOperand_Success;
4054 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4055 /// use in the MRS/MSR instructions added to support virtualization.
4056 ARMAsmParser::OperandMatchResultTy
4057 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4058 MCAsmParser &Parser = getParser();
4059 SMLoc S = Parser.getTok().getLoc();
4060 const AsmToken &Tok = Parser.getTok();
4061 if (!Tok.is(AsmToken::Identifier))
4062 return MatchOperand_NoMatch;
4063 StringRef RegName = Tok.getString();
4065 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4067 unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4068 .Case("r8_usr", 0x00)
4069 .Case("r9_usr", 0x01)
4070 .Case("r10_usr", 0x02)
4071 .Case("r11_usr", 0x03)
4072 .Case("r12_usr", 0x04)
4073 .Case("sp_usr", 0x05)
4074 .Case("lr_usr", 0x06)
4075 .Case("r8_fiq", 0x08)
4076 .Case("r9_fiq", 0x09)
4077 .Case("r10_fiq", 0x0a)
4078 .Case("r11_fiq", 0x0b)
4079 .Case("r12_fiq", 0x0c)
4080 .Case("sp_fiq", 0x0d)
4081 .Case("lr_fiq", 0x0e)
4082 .Case("lr_irq", 0x10)
4083 .Case("sp_irq", 0x11)
4084 .Case("lr_svc", 0x12)
4085 .Case("sp_svc", 0x13)
4086 .Case("lr_abt", 0x14)
4087 .Case("sp_abt", 0x15)
4088 .Case("lr_und", 0x16)
4089 .Case("sp_und", 0x17)
4090 .Case("lr_mon", 0x1c)
4091 .Case("sp_mon", 0x1d)
4092 .Case("elr_hyp", 0x1e)
4093 .Case("sp_hyp", 0x1f)
4094 .Case("spsr_fiq", 0x2e)
4095 .Case("spsr_irq", 0x30)
4096 .Case("spsr_svc", 0x32)
4097 .Case("spsr_abt", 0x34)
4098 .Case("spsr_und", 0x36)
4099 .Case("spsr_mon", 0x3c)
4100 .Case("spsr_hyp", 0x3e)
4103 if (Encoding == ~0U)
4104 return MatchOperand_NoMatch;
4106 Parser.Lex(); // Eat identifier token.
4107 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4108 return MatchOperand_Success;
4111 ARMAsmParser::OperandMatchResultTy
4112 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4114 MCAsmParser &Parser = getParser();
4115 const AsmToken &Tok = Parser.getTok();
4116 if (Tok.isNot(AsmToken::Identifier)) {
4117 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4118 return MatchOperand_ParseFail;
4120 StringRef ShiftName = Tok.getString();
4121 std::string LowerOp = Op.lower();
4122 std::string UpperOp = Op.upper();
4123 if (ShiftName != LowerOp && ShiftName != UpperOp) {
4124 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4125 return MatchOperand_ParseFail;
4127 Parser.Lex(); // Eat shift type token.
4129 // There must be a '#' and a shift amount.
4130 if (Parser.getTok().isNot(AsmToken::Hash) &&
4131 Parser.getTok().isNot(AsmToken::Dollar)) {
4132 Error(Parser.getTok().getLoc(), "'#' expected");
4133 return MatchOperand_ParseFail;
4135 Parser.Lex(); // Eat hash token.
4137 const MCExpr *ShiftAmount;
4138 SMLoc Loc = Parser.getTok().getLoc();
4140 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4141 Error(Loc, "illegal expression");
4142 return MatchOperand_ParseFail;
4144 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4146 Error(Loc, "constant expression expected");
4147 return MatchOperand_ParseFail;
4149 int Val = CE->getValue();
4150 if (Val < Low || Val > High) {
4151 Error(Loc, "immediate value out of range");
4152 return MatchOperand_ParseFail;
4155 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4157 return MatchOperand_Success;
4160 ARMAsmParser::OperandMatchResultTy
4161 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4162 MCAsmParser &Parser = getParser();
4163 const AsmToken &Tok = Parser.getTok();
4164 SMLoc S = Tok.getLoc();
4165 if (Tok.isNot(AsmToken::Identifier)) {
4166 Error(S, "'be' or 'le' operand expected");
4167 return MatchOperand_ParseFail;
4169 int Val = StringSwitch<int>(Tok.getString().lower())
4173 Parser.Lex(); // Eat the token.
4176 Error(S, "'be' or 'le' operand expected");
4177 return MatchOperand_ParseFail;
4179 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
4181 S, Tok.getEndLoc()));
4182 return MatchOperand_Success;
4185 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4186 /// instructions. Legal values are:
4187 /// lsl #n 'n' in [0,31]
4188 /// asr #n 'n' in [1,32]
4189 /// n == 32 encoded as n == 0.
4190 ARMAsmParser::OperandMatchResultTy
4191 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4192 MCAsmParser &Parser = getParser();
4193 const AsmToken &Tok = Parser.getTok();
4194 SMLoc S = Tok.getLoc();
4195 if (Tok.isNot(AsmToken::Identifier)) {
4196 Error(S, "shift operator 'asr' or 'lsl' expected");
4197 return MatchOperand_ParseFail;
4199 StringRef ShiftName = Tok.getString();
4201 if (ShiftName == "lsl" || ShiftName == "LSL")
4203 else if (ShiftName == "asr" || ShiftName == "ASR")
4206 Error(S, "shift operator 'asr' or 'lsl' expected");
4207 return MatchOperand_ParseFail;
4209 Parser.Lex(); // Eat the operator.
4211 // A '#' and a shift amount.
4212 if (Parser.getTok().isNot(AsmToken::Hash) &&
4213 Parser.getTok().isNot(AsmToken::Dollar)) {
4214 Error(Parser.getTok().getLoc(), "'#' expected");
4215 return MatchOperand_ParseFail;
4217 Parser.Lex(); // Eat hash token.
4218 SMLoc ExLoc = Parser.getTok().getLoc();
4220 const MCExpr *ShiftAmount;
4222 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4223 Error(ExLoc, "malformed shift expression");
4224 return MatchOperand_ParseFail;
4226 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4228 Error(ExLoc, "shift amount must be an immediate");
4229 return MatchOperand_ParseFail;
4232 int64_t Val = CE->getValue();
4234 // Shift amount must be in [1,32]
4235 if (Val < 1 || Val > 32) {
4236 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4237 return MatchOperand_ParseFail;
4239 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4240 if (isThumb() && Val == 32) {
4241 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4242 return MatchOperand_ParseFail;
4244 if (Val == 32) Val = 0;
4246 // Shift amount must be in [1,32]
4247 if (Val < 0 || Val > 31) {
4248 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4249 return MatchOperand_ParseFail;
4253 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4255 return MatchOperand_Success;
4258 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4259 /// of instructions. Legal values are:
4260 /// ror #n 'n' in {0, 8, 16, 24}
4261 ARMAsmParser::OperandMatchResultTy
4262 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4263 MCAsmParser &Parser = getParser();
4264 const AsmToken &Tok = Parser.getTok();
4265 SMLoc S = Tok.getLoc();
4266 if (Tok.isNot(AsmToken::Identifier))
4267 return MatchOperand_NoMatch;
4268 StringRef ShiftName = Tok.getString();
4269 if (ShiftName != "ror" && ShiftName != "ROR")
4270 return MatchOperand_NoMatch;
4271 Parser.Lex(); // Eat the operator.
4273 // A '#' and a rotate amount.
4274 if (Parser.getTok().isNot(AsmToken::Hash) &&
4275 Parser.getTok().isNot(AsmToken::Dollar)) {
4276 Error(Parser.getTok().getLoc(), "'#' expected");
4277 return MatchOperand_ParseFail;
4279 Parser.Lex(); // Eat hash token.
4280 SMLoc ExLoc = Parser.getTok().getLoc();
4282 const MCExpr *ShiftAmount;
4284 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4285 Error(ExLoc, "malformed rotate expression");
4286 return MatchOperand_ParseFail;
4288 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4290 Error(ExLoc, "rotate amount must be an immediate");
4291 return MatchOperand_ParseFail;
4294 int64_t Val = CE->getValue();
4295 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4296 // normally, zero is represented in asm by omitting the rotate operand
4298 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4299 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4300 return MatchOperand_ParseFail;
4303 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4305 return MatchOperand_Success;
4308 ARMAsmParser::OperandMatchResultTy
4309 ARMAsmParser::parseModImm(OperandVector &Operands) {
4310 MCAsmParser &Parser = getParser();
4311 MCAsmLexer &Lexer = getLexer();
4314 SMLoc S = Parser.getTok().getLoc();
4316 // 1) A mod_imm operand can appear in the place of a register name:
4318 // add r0, r0, #mod_imm
4319 // to correctly handle the latter, we bail out as soon as we see an
4322 // 2) Similarly, we do not want to parse into complex operands:
4324 // mov r0, :lower16:(_foo)
4325 if (Parser.getTok().is(AsmToken::Identifier) ||
4326 Parser.getTok().is(AsmToken::Colon))
4327 return MatchOperand_NoMatch;
4329 // Hash (dollar) is optional as per the ARMARM
4330 if (Parser.getTok().is(AsmToken::Hash) ||
4331 Parser.getTok().is(AsmToken::Dollar)) {
4332 // Avoid parsing into complex operands (#:)
4333 if (Lexer.peekTok().is(AsmToken::Colon))
4334 return MatchOperand_NoMatch;
4336 // Eat the hash (dollar)
4341 Sx1 = Parser.getTok().getLoc();
4342 const MCExpr *Imm1Exp;
4343 if (getParser().parseExpression(Imm1Exp, Ex1)) {
4344 Error(Sx1, "malformed expression");
4345 return MatchOperand_ParseFail;
4348 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
4351 // Immediate must fit within 32-bits
4352 Imm1 = CE->getValue();
4353 int Enc = ARM_AM::getSOImmVal(Imm1);
4354 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4356 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4359 return MatchOperand_Success;
4362 // We have parsed an immediate which is not for us, fallback to a plain
4363 // immediate. This can happen for instruction aliases. For an example,
4364 // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
4365 // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
4366 // instruction with a mod_imm operand. The alias is defined such that the
4367 // parser method is shared, that's why we have to do this here.
4368 if (Parser.getTok().is(AsmToken::EndOfStatement)) {
4369 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4370 return MatchOperand_Success;
4373 // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
4374 // MCFixup). Fallback to a plain immediate.
4375 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4376 return MatchOperand_Success;
4379 // From this point onward, we expect the input to be a (#bits, #rot) pair
4380 if (Parser.getTok().isNot(AsmToken::Comma)) {
4381 Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
4382 return MatchOperand_ParseFail;
4386 Error(Sx1, "immediate operand must a number in the range [0, 255]");
4387 return MatchOperand_ParseFail;
4395 Sx2 = Parser.getTok().getLoc();
4397 // Eat the optional hash (dollar)
4398 if (Parser.getTok().is(AsmToken::Hash) ||
4399 Parser.getTok().is(AsmToken::Dollar))
4402 const MCExpr *Imm2Exp;
4403 if (getParser().parseExpression(Imm2Exp, Ex2)) {
4404 Error(Sx2, "malformed expression");
4405 return MatchOperand_ParseFail;
4408 CE = dyn_cast<MCConstantExpr>(Imm2Exp);
4411 Imm2 = CE->getValue();
4412 if (!(Imm2 & ~0x1E)) {
4414 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4415 return MatchOperand_Success;
4417 Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4418 return MatchOperand_ParseFail;
4420 Error(Sx2, "constant expression expected");
4421 return MatchOperand_ParseFail;
4425 ARMAsmParser::OperandMatchResultTy
4426 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4427 MCAsmParser &Parser = getParser();
4428 SMLoc S = Parser.getTok().getLoc();
4429 // The bitfield descriptor is really two operands, the LSB and the width.
4430 if (Parser.getTok().isNot(AsmToken::Hash) &&
4431 Parser.getTok().isNot(AsmToken::Dollar)) {
4432 Error(Parser.getTok().getLoc(), "'#' expected");
4433 return MatchOperand_ParseFail;
4435 Parser.Lex(); // Eat hash token.
4437 const MCExpr *LSBExpr;
4438 SMLoc E = Parser.getTok().getLoc();
4439 if (getParser().parseExpression(LSBExpr)) {
4440 Error(E, "malformed immediate expression");
4441 return MatchOperand_ParseFail;
4443 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4445 Error(E, "'lsb' operand must be an immediate");
4446 return MatchOperand_ParseFail;
4449 int64_t LSB = CE->getValue();
4450 // The LSB must be in the range [0,31]
4451 if (LSB < 0 || LSB > 31) {
4452 Error(E, "'lsb' operand must be in the range [0,31]");
4453 return MatchOperand_ParseFail;
4455 E = Parser.getTok().getLoc();
4457 // Expect another immediate operand.
4458 if (Parser.getTok().isNot(AsmToken::Comma)) {
4459 Error(Parser.getTok().getLoc(), "too few operands");
4460 return MatchOperand_ParseFail;
4462 Parser.Lex(); // Eat hash token.
4463 if (Parser.getTok().isNot(AsmToken::Hash) &&
4464 Parser.getTok().isNot(AsmToken::Dollar)) {
4465 Error(Parser.getTok().getLoc(), "'#' expected");
4466 return MatchOperand_ParseFail;
4468 Parser.Lex(); // Eat hash token.
4470 const MCExpr *WidthExpr;
4472 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4473 Error(E, "malformed immediate expression");
4474 return MatchOperand_ParseFail;
4476 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4478 Error(E, "'width' operand must be an immediate");
4479 return MatchOperand_ParseFail;
4482 int64_t Width = CE->getValue();
4483 // The LSB must be in the range [1,32-lsb]
4484 if (Width < 1 || Width > 32 - LSB) {
4485 Error(E, "'width' operand must be in the range [1,32-lsb]");
4486 return MatchOperand_ParseFail;
4489 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4491 return MatchOperand_Success;
4494 ARMAsmParser::OperandMatchResultTy
4495 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4496 // Check for a post-index addressing register operand. Specifically:
4497 // postidx_reg := '+' register {, shift}
4498 // | '-' register {, shift}
4499 // | register {, shift}
4501 // This method must return MatchOperand_NoMatch without consuming any tokens
4502 // in the case where there is no match, as other alternatives take other
4504 MCAsmParser &Parser = getParser();
4505 AsmToken Tok = Parser.getTok();
4506 SMLoc S = Tok.getLoc();
4507 bool haveEaten = false;
4509 if (Tok.is(AsmToken::Plus)) {
4510 Parser.Lex(); // Eat the '+' token.
4512 } else if (Tok.is(AsmToken::Minus)) {
4513 Parser.Lex(); // Eat the '-' token.
4518 SMLoc E = Parser.getTok().getEndLoc();
4519 int Reg = tryParseRegister();
4522 return MatchOperand_NoMatch;
4523 Error(Parser.getTok().getLoc(), "register expected");
4524 return MatchOperand_ParseFail;
4527 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4528 unsigned ShiftImm = 0;
4529 if (Parser.getTok().is(AsmToken::Comma)) {
4530 Parser.Lex(); // Eat the ','.
4531 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4532 return MatchOperand_ParseFail;
4534 // FIXME: Only approximates end...may include intervening whitespace.
4535 E = Parser.getTok().getLoc();
4538 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4541 return MatchOperand_Success;
4544 ARMAsmParser::OperandMatchResultTy
4545 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4546 // Check for a post-index addressing register operand. Specifically:
4547 // am3offset := '+' register
4554 // This method must return MatchOperand_NoMatch without consuming any tokens
4555 // in the case where there is no match, as other alternatives take other
4557 MCAsmParser &Parser = getParser();
4558 AsmToken Tok = Parser.getTok();
4559 SMLoc S = Tok.getLoc();
4561 // Do immediates first, as we always parse those if we have a '#'.
4562 if (Parser.getTok().is(AsmToken::Hash) ||
4563 Parser.getTok().is(AsmToken::Dollar)) {
4564 Parser.Lex(); // Eat '#' or '$'.
4565 // Explicitly look for a '-', as we need to encode negative zero
4567 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4568 const MCExpr *Offset;
4570 if (getParser().parseExpression(Offset, E))
4571 return MatchOperand_ParseFail;
4572 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4574 Error(S, "constant expression expected");
4575 return MatchOperand_ParseFail;
4577 // Negative zero is encoded as the flag value INT32_MIN.
4578 int32_t Val = CE->getValue();
4579 if (isNegative && Val == 0)
4583 ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
4585 return MatchOperand_Success;
4589 bool haveEaten = false;
4591 if (Tok.is(AsmToken::Plus)) {
4592 Parser.Lex(); // Eat the '+' token.
4594 } else if (Tok.is(AsmToken::Minus)) {
4595 Parser.Lex(); // Eat the '-' token.
4600 Tok = Parser.getTok();
4601 int Reg = tryParseRegister();
4604 return MatchOperand_NoMatch;
4605 Error(Tok.getLoc(), "register expected");
4606 return MatchOperand_ParseFail;
4609 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4610 0, S, Tok.getEndLoc()));
4612 return MatchOperand_Success;
4615 /// Convert parsed operands to MCInst. Needed here because this instruction
4616 /// only has two register operands, but multiplication is commutative so
4617 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4618 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4619 const OperandVector &Operands) {
4620 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4621 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4622 // If we have a three-operand form, make sure to set Rn to be the operand
4623 // that isn't the same as Rd.
4625 if (Operands.size() == 6 &&
4626 ((ARMOperand &)*Operands[4]).getReg() ==
4627 ((ARMOperand &)*Operands[3]).getReg())
4629 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4630 Inst.addOperand(Inst.getOperand(0));
4631 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4634 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4635 const OperandVector &Operands) {
4636 int CondOp = -1, ImmOp = -1;
4637 switch(Inst.getOpcode()) {
4639 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4642 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4644 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4646 // first decide whether or not the branch should be conditional
4647 // by looking at it's location relative to an IT block
4649 // inside an IT block we cannot have any conditional branches. any
4650 // such instructions needs to be converted to unconditional form
4651 switch(Inst.getOpcode()) {
4652 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4653 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4656 // outside IT blocks we can only have unconditional branches with AL
4657 // condition code or conditional branches with non-AL condition code
4658 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4659 switch(Inst.getOpcode()) {
4662 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4666 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4671 // now decide on encoding size based on branch target range
4672 switch(Inst.getOpcode()) {
4673 // classify tB as either t2B or t1B based on range of immediate operand
4675 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4676 if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4677 Inst.setOpcode(ARM::t2B);
4680 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4682 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4683 if (!op.isSignedOffset<8, 1>() && isThumbTwo())
4684 Inst.setOpcode(ARM::t2Bcc);
4688 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4689 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4692 /// Parse an ARM memory expression, return false if successful else return true
4693 /// or an error. The first token must be a '[' when called.
4694 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4695 MCAsmParser &Parser = getParser();
4697 assert(Parser.getTok().is(AsmToken::LBrac) &&
4698 "Token is not a Left Bracket");
4699 S = Parser.getTok().getLoc();
4700 Parser.Lex(); // Eat left bracket token.
4702 const AsmToken &BaseRegTok = Parser.getTok();
4703 int BaseRegNum = tryParseRegister();
4704 if (BaseRegNum == -1)
4705 return Error(BaseRegTok.getLoc(), "register expected");
4707 // The next token must either be a comma, a colon or a closing bracket.
4708 const AsmToken &Tok = Parser.getTok();
4709 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4710 !Tok.is(AsmToken::RBrac))
4711 return Error(Tok.getLoc(), "malformed memory operand");
4713 if (Tok.is(AsmToken::RBrac)) {
4714 E = Tok.getEndLoc();
4715 Parser.Lex(); // Eat right bracket token.
4717 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4718 ARM_AM::no_shift, 0, 0, false,
4721 // If there's a pre-indexing writeback marker, '!', just add it as a token
4722 // operand. It's rather odd, but syntactically valid.
4723 if (Parser.getTok().is(AsmToken::Exclaim)) {
4724 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4725 Parser.Lex(); // Eat the '!'.
4731 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4732 "Lost colon or comma in memory operand?!");
4733 if (Tok.is(AsmToken::Comma)) {
4734 Parser.Lex(); // Eat the comma.
4737 // If we have a ':', it's an alignment specifier.
4738 if (Parser.getTok().is(AsmToken::Colon)) {
4739 Parser.Lex(); // Eat the ':'.
4740 E = Parser.getTok().getLoc();
4741 SMLoc AlignmentLoc = Tok.getLoc();
4744 if (getParser().parseExpression(Expr))
4747 // The expression has to be a constant. Memory references with relocations
4748 // don't come through here, as they use the <label> forms of the relevant
4750 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4752 return Error (E, "constant expression expected");
4755 switch (CE->getValue()) {
4758 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4759 case 16: Align = 2; break;
4760 case 32: Align = 4; break;
4761 case 64: Align = 8; break;
4762 case 128: Align = 16; break;
4763 case 256: Align = 32; break;
4766 // Now we should have the closing ']'
4767 if (Parser.getTok().isNot(AsmToken::RBrac))
4768 return Error(Parser.getTok().getLoc(), "']' expected");
4769 E = Parser.getTok().getEndLoc();
4770 Parser.Lex(); // Eat right bracket token.
4772 // Don't worry about range checking the value here. That's handled by
4773 // the is*() predicates.
4774 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4775 ARM_AM::no_shift, 0, Align,
4776 false, S, E, AlignmentLoc));
4778 // If there's a pre-indexing writeback marker, '!', just add it as a token
4780 if (Parser.getTok().is(AsmToken::Exclaim)) {
4781 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4782 Parser.Lex(); // Eat the '!'.
4788 // If we have a '#', it's an immediate offset, else assume it's a register
4789 // offset. Be friendly and also accept a plain integer (without a leading
4790 // hash) for gas compatibility.
4791 if (Parser.getTok().is(AsmToken::Hash) ||
4792 Parser.getTok().is(AsmToken::Dollar) ||
4793 Parser.getTok().is(AsmToken::Integer)) {
4794 if (Parser.getTok().isNot(AsmToken::Integer))
4795 Parser.Lex(); // Eat '#' or '$'.
4796 E = Parser.getTok().getLoc();
4798 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4799 const MCExpr *Offset;
4800 if (getParser().parseExpression(Offset))
4803 // The expression has to be a constant. Memory references with relocations
4804 // don't come through here, as they use the <label> forms of the relevant
4806 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4808 return Error (E, "constant expression expected");
4810 // If the constant was #-0, represent it as INT32_MIN.
4811 int32_t Val = CE->getValue();
4812 if (isNegative && Val == 0)
4813 CE = MCConstantExpr::create(INT32_MIN, getContext());
4815 // Now we should have the closing ']'
4816 if (Parser.getTok().isNot(AsmToken::RBrac))
4817 return Error(Parser.getTok().getLoc(), "']' expected");
4818 E = Parser.getTok().getEndLoc();
4819 Parser.Lex(); // Eat right bracket token.
4821 // Don't worry about range checking the value here. That's handled by
4822 // the is*() predicates.
4823 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4824 ARM_AM::no_shift, 0, 0,
4827 // If there's a pre-indexing writeback marker, '!', just add it as a token
4829 if (Parser.getTok().is(AsmToken::Exclaim)) {
4830 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4831 Parser.Lex(); // Eat the '!'.
4837 // The register offset is optionally preceded by a '+' or '-'
4838 bool isNegative = false;
4839 if (Parser.getTok().is(AsmToken::Minus)) {
4841 Parser.Lex(); // Eat the '-'.
4842 } else if (Parser.getTok().is(AsmToken::Plus)) {
4844 Parser.Lex(); // Eat the '+'.
4847 E = Parser.getTok().getLoc();
4848 int OffsetRegNum = tryParseRegister();
4849 if (OffsetRegNum == -1)
4850 return Error(E, "register expected");
4852 // If there's a shift operator, handle it.
4853 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4854 unsigned ShiftImm = 0;
4855 if (Parser.getTok().is(AsmToken::Comma)) {
4856 Parser.Lex(); // Eat the ','.
4857 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4861 // Now we should have the closing ']'
4862 if (Parser.getTok().isNot(AsmToken::RBrac))
4863 return Error(Parser.getTok().getLoc(), "']' expected");
4864 E = Parser.getTok().getEndLoc();
4865 Parser.Lex(); // Eat right bracket token.
4867 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4868 ShiftType, ShiftImm, 0, isNegative,
4871 // If there's a pre-indexing writeback marker, '!', just add it as a token
4873 if (Parser.getTok().is(AsmToken::Exclaim)) {
4874 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4875 Parser.Lex(); // Eat the '!'.
4881 /// parseMemRegOffsetShift - one of these two:
4882 /// ( lsl | lsr | asr | ror ) , # shift_amount
4884 /// return true if it parses a shift otherwise it returns false.
4885 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4887 MCAsmParser &Parser = getParser();
4888 SMLoc Loc = Parser.getTok().getLoc();
4889 const AsmToken &Tok = Parser.getTok();
4890 if (Tok.isNot(AsmToken::Identifier))
4892 StringRef ShiftName = Tok.getString();
4893 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4894 ShiftName == "asl" || ShiftName == "ASL")
4896 else if (ShiftName == "lsr" || ShiftName == "LSR")
4898 else if (ShiftName == "asr" || ShiftName == "ASR")
4900 else if (ShiftName == "ror" || ShiftName == "ROR")
4902 else if (ShiftName == "rrx" || ShiftName == "RRX")
4905 return Error(Loc, "illegal shift operator");
4906 Parser.Lex(); // Eat shift type token.
4908 // rrx stands alone.
4910 if (St != ARM_AM::rrx) {
4911 Loc = Parser.getTok().getLoc();
4912 // A '#' and a shift amount.
4913 const AsmToken &HashTok = Parser.getTok();
4914 if (HashTok.isNot(AsmToken::Hash) &&
4915 HashTok.isNot(AsmToken::Dollar))
4916 return Error(HashTok.getLoc(), "'#' expected");
4917 Parser.Lex(); // Eat hash token.
4920 if (getParser().parseExpression(Expr))
4922 // Range check the immediate.
4923 // lsl, ror: 0 <= imm <= 31
4924 // lsr, asr: 0 <= imm <= 32
4925 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4927 return Error(Loc, "shift amount must be an immediate");
4928 int64_t Imm = CE->getValue();
4930 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4931 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4932 return Error(Loc, "immediate shift value out of range");
4933 // If <ShiftTy> #0, turn it into a no_shift.
4936 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4945 /// parseFPImm - A floating point immediate expression operand.
4946 ARMAsmParser::OperandMatchResultTy
4947 ARMAsmParser::parseFPImm(OperandVector &Operands) {
4948 MCAsmParser &Parser = getParser();
4949 // Anything that can accept a floating point constant as an operand
4950 // needs to go through here, as the regular parseExpression is
4953 // This routine still creates a generic Immediate operand, containing
4954 // a bitcast of the 64-bit floating point value. The various operands
4955 // that accept floats can check whether the value is valid for them
4956 // via the standard is*() predicates.
4958 SMLoc S = Parser.getTok().getLoc();
4960 if (Parser.getTok().isNot(AsmToken::Hash) &&
4961 Parser.getTok().isNot(AsmToken::Dollar))
4962 return MatchOperand_NoMatch;
4964 // Disambiguate the VMOV forms that can accept an FP immediate.
4965 // vmov.f32 <sreg>, #imm
4966 // vmov.f64 <dreg>, #imm
4967 // vmov.f32 <dreg>, #imm @ vector f32x2
4968 // vmov.f32 <qreg>, #imm @ vector f32x4
4970 // There are also the NEON VMOV instructions which expect an
4971 // integer constant. Make sure we don't try to parse an FPImm
4973 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4974 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
4975 bool isVmovf = TyOp.isToken() &&
4976 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
4977 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
4978 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
4979 Mnemonic.getToken() == "fconsts");
4980 if (!(isVmovf || isFconst))
4981 return MatchOperand_NoMatch;
4983 Parser.Lex(); // Eat '#' or '$'.
4985 // Handle negation, as that still comes through as a separate token.
4986 bool isNegative = false;
4987 if (Parser.getTok().is(AsmToken::Minus)) {
4991 const AsmToken &Tok = Parser.getTok();
4992 SMLoc Loc = Tok.getLoc();
4993 if (Tok.is(AsmToken::Real) && isVmovf) {
4994 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4995 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4996 // If we had a '-' in front, toggle the sign bit.
4997 IntVal ^= (uint64_t)isNegative << 31;
4998 Parser.Lex(); // Eat the token.
4999 Operands.push_back(ARMOperand::CreateImm(
5000 MCConstantExpr::create(IntVal, getContext()),
5001 S, Parser.getTok().getLoc()));
5002 return MatchOperand_Success;
5004 // Also handle plain integers. Instructions which allow floating point
5005 // immediates also allow a raw encoded 8-bit value.
5006 if (Tok.is(AsmToken::Integer) && isFconst) {
5007 int64_t Val = Tok.getIntVal();
5008 Parser.Lex(); // Eat the token.
5009 if (Val > 255 || Val < 0) {
5010 Error(Loc, "encoded floating point value out of range");
5011 return MatchOperand_ParseFail;
5013 float RealVal = ARM_AM::getFPImmFloat(Val);
5014 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5016 Operands.push_back(ARMOperand::CreateImm(
5017 MCConstantExpr::create(Val, getContext()), S,
5018 Parser.getTok().getLoc()));
5019 return MatchOperand_Success;
5022 Error(Loc, "invalid floating point immediate");
5023 return MatchOperand_ParseFail;
5026 /// Parse a arm instruction operand. For now this parses the operand regardless
5027 /// of the mnemonic.
5028 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5029 MCAsmParser &Parser = getParser();
5032 // Check if the current operand has a custom associated parser, if so, try to
5033 // custom parse the operand, or fallback to the general approach.
5034 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5035 if (ResTy == MatchOperand_Success)
5037 // If there wasn't a custom match, try the generic matcher below. Otherwise,
5038 // there was a match, but an error occurred, in which case, just return that
5039 // the operand parsing failed.
5040 if (ResTy == MatchOperand_ParseFail)
5043 switch (getLexer().getKind()) {
5045 Error(Parser.getTok().getLoc(), "unexpected token in operand");
5047 case AsmToken::Identifier: {
5048 // If we've seen a branch mnemonic, the next operand must be a label. This
5049 // is true even if the label is a register name. So "br r1" means branch to
5051 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
5053 if (!tryParseRegisterWithWriteBack(Operands))
5055 int Res = tryParseShiftRegister(Operands);
5056 if (Res == 0) // success
5058 else if (Res == -1) // irrecoverable error
5060 // If this is VMRS, check for the apsr_nzcv operand.
5061 if (Mnemonic == "vmrs" &&
5062 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
5063 S = Parser.getTok().getLoc();
5065 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
5070 // Fall though for the Identifier case that is not a register or a
5073 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
5074 case AsmToken::Integer: // things like 1f and 2b as a branch targets
5075 case AsmToken::String: // quoted label names.
5076 case AsmToken::Dot: { // . as a branch target
5077 // This was not a register so parse other operands that start with an
5078 // identifier (like labels) as expressions and create them as immediates.
5079 const MCExpr *IdVal;
5080 S = Parser.getTok().getLoc();
5081 if (getParser().parseExpression(IdVal))
5083 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5084 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
5087 case AsmToken::LBrac:
5088 return parseMemory(Operands);
5089 case AsmToken::LCurly:
5090 return parseRegisterList(Operands);
5091 case AsmToken::Dollar:
5092 case AsmToken::Hash: {
5093 // #42 -> immediate.
5094 S = Parser.getTok().getLoc();
5097 if (Parser.getTok().isNot(AsmToken::Colon)) {
5098 bool isNegative = Parser.getTok().is(AsmToken::Minus);
5099 const MCExpr *ImmVal;
5100 if (getParser().parseExpression(ImmVal))
5102 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
5104 int32_t Val = CE->getValue();
5105 if (isNegative && Val == 0)
5106 ImmVal = MCConstantExpr::create(INT32_MIN, getContext());
5108 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5109 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
5111 // There can be a trailing '!' on operands that we want as a separate
5112 // '!' Token operand. Handle that here. For example, the compatibility
5113 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
5114 if (Parser.getTok().is(AsmToken::Exclaim)) {
5115 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
5116 Parser.getTok().getLoc()));
5117 Parser.Lex(); // Eat exclaim token
5121 // w/ a ':' after the '#', it's just like a plain ':'.
5124 case AsmToken::Colon: {
5125 // ":lower16:" and ":upper16:" expression prefixes
5126 // FIXME: Check it's an expression prefix,
5127 // e.g. (FOO - :lower16:BAR) isn't legal.
5128 ARMMCExpr::VariantKind RefKind;
5129 if (parsePrefix(RefKind))
5132 const MCExpr *SubExprVal;
5133 if (getParser().parseExpression(SubExprVal))
5136 const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal,
5138 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5139 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
5142 case AsmToken::Equal: {
5143 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
5144 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
5146 Parser.Lex(); // Eat '='
5147 const MCExpr *SubExprVal;
5148 if (getParser().parseExpression(SubExprVal))
5150 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5152 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
5153 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
5159 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5160 // :lower16: and :upper16:.
5161 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5162 MCAsmParser &Parser = getParser();
5163 RefKind = ARMMCExpr::VK_ARM_None;
5165 // consume an optional '#' (GNU compatibility)
5166 if (getLexer().is(AsmToken::Hash))
5169 // :lower16: and :upper16: modifiers
5170 assert(getLexer().is(AsmToken::Colon) && "expected a :");
5171 Parser.Lex(); // Eat ':'
5173 if (getLexer().isNot(AsmToken::Identifier)) {
5174 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5179 COFF = (1 << MCObjectFileInfo::IsCOFF),
5180 ELF = (1 << MCObjectFileInfo::IsELF),
5181 MACHO = (1 << MCObjectFileInfo::IsMachO)
5183 static const struct PrefixEntry {
5184 const char *Spelling;
5185 ARMMCExpr::VariantKind VariantKind;
5186 uint8_t SupportedFormats;
5187 } PrefixEntries[] = {
5188 { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
5189 { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
5192 StringRef IDVal = Parser.getTok().getIdentifier();
5194 const auto &Prefix =
5195 std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries),
5196 [&IDVal](const PrefixEntry &PE) {
5197 return PE.Spelling == IDVal;
5199 if (Prefix == std::end(PrefixEntries)) {
5200 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5204 uint8_t CurrentFormat;
5205 switch (getContext().getObjectFileInfo()->getObjectFileType()) {
5206 case MCObjectFileInfo::IsMachO:
5207 CurrentFormat = MACHO;
5209 case MCObjectFileInfo::IsELF:
5210 CurrentFormat = ELF;
5212 case MCObjectFileInfo::IsCOFF:
5213 CurrentFormat = COFF;
5217 if (~Prefix->SupportedFormats & CurrentFormat) {
5218 Error(Parser.getTok().getLoc(),
5219 "cannot represent relocation in the current file format");
5223 RefKind = Prefix->VariantKind;
5226 if (getLexer().isNot(AsmToken::Colon)) {
5227 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5230 Parser.Lex(); // Eat the last ':'
5235 /// \brief Given a mnemonic, split out possible predication code and carry
5236 /// setting letters to form a canonical mnemonic and flags.
5238 // FIXME: Would be nice to autogen this.
5239 // FIXME: This is a bit of a maze of special cases.
5240 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5241 unsigned &PredicationCode,
5243 unsigned &ProcessorIMod,
5244 StringRef &ITMask) {
5245 PredicationCode = ARMCC::AL;
5246 CarrySetting = false;
5249 // Ignore some mnemonics we know aren't predicated forms.
5251 // FIXME: Would be nice to autogen this.
5252 if ((Mnemonic == "movs" && isThumb()) ||
5253 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
5254 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
5255 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
5256 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
5257 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
5258 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
5259 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
5260 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5261 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5262 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
5263 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5264 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
5265 Mnemonic.startswith("vsel"))
5268 // First, split out any predication code. Ignore mnemonics we know aren't
5269 // predicated but do have a carry-set and so weren't caught above.
5270 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5271 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5272 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5273 Mnemonic != "sbcs" && Mnemonic != "rscs") {
5274 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5275 .Case("eq", ARMCC::EQ)
5276 .Case("ne", ARMCC::NE)
5277 .Case("hs", ARMCC::HS)
5278 .Case("cs", ARMCC::HS)
5279 .Case("lo", ARMCC::LO)
5280 .Case("cc", ARMCC::LO)
5281 .Case("mi", ARMCC::MI)
5282 .Case("pl", ARMCC::PL)
5283 .Case("vs", ARMCC::VS)
5284 .Case("vc", ARMCC::VC)
5285 .Case("hi", ARMCC::HI)
5286 .Case("ls", ARMCC::LS)
5287 .Case("ge", ARMCC::GE)
5288 .Case("lt", ARMCC::LT)
5289 .Case("gt", ARMCC::GT)
5290 .Case("le", ARMCC::LE)
5291 .Case("al", ARMCC::AL)
5294 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5295 PredicationCode = CC;
5299 // Next, determine if we have a carry setting bit. We explicitly ignore all
5300 // the instructions we know end in 's'.
5301 if (Mnemonic.endswith("s") &&
5302 !(Mnemonic == "cps" || Mnemonic == "mls" ||
5303 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5304 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5305 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5306 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5307 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5308 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5309 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5310 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5311 (Mnemonic == "movs" && isThumb()))) {
5312 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5313 CarrySetting = true;
5316 // The "cps" instruction can have a interrupt mode operand which is glued into
5317 // the mnemonic. Check if this is the case, split it and parse the imod op
5318 if (Mnemonic.startswith("cps")) {
5319 // Split out any imod code.
5321 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5322 .Case("ie", ARM_PROC::IE)
5323 .Case("id", ARM_PROC::ID)
5326 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5327 ProcessorIMod = IMod;
5331 // The "it" instruction has the condition mask on the end of the mnemonic.
5332 if (Mnemonic.startswith("it")) {
5333 ITMask = Mnemonic.slice(2, Mnemonic.size());
5334 Mnemonic = Mnemonic.slice(0, 2);
5340 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5341 /// inclusion of carry set or predication code operands.
5343 // FIXME: It would be nice to autogen this.
5344 void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5345 bool &CanAcceptCarrySet,
5346 bool &CanAcceptPredicationCode) {
5348 Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5349 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5350 Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" ||
5351 Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" ||
5352 Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" ||
5353 Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" ||
5354 Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5356 (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" ||
5357 Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull"));
5359 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5360 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5361 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5362 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5363 Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
5364 Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
5365 Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
5366 Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
5367 Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
5368 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5369 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5370 // These mnemonics are never predicable
5371 CanAcceptPredicationCode = false;
5372 } else if (!isThumb()) {
5373 // Some instructions are only predicable in Thumb mode
5374 CanAcceptPredicationCode =
5375 Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5376 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5377 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5378 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5379 Mnemonic != "ldc2" && Mnemonic != "ldc2l" && Mnemonic != "stc2" &&
5380 Mnemonic != "stc2l" && !Mnemonic.startswith("rfe") &&
5381 !Mnemonic.startswith("srs");
5382 } else if (isThumbOne()) {
5384 CanAcceptPredicationCode = Mnemonic != "movs";
5386 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5388 CanAcceptPredicationCode = true;
5391 // \brief Some Thumb instructions have two operand forms that are not
5392 // available as three operand, convert to two operand form if possible.
5394 // FIXME: We would really like to be able to tablegen'erate this.
5395 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
5397 OperandVector &Operands) {
5398 if (Operands.size() != 6)
5401 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5402 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
5403 if (!Op3.isReg() || !Op4.isReg())
5406 auto Op3Reg = Op3.getReg();
5407 auto Op4Reg = Op4.getReg();
5409 // For most Thumb2 cases we just generate the 3 operand form and reduce
5410 // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr)
5411 // won't accept SP or PC so we do the transformation here taking care
5412 // with immediate range in the 'add sp, sp #imm' case.
5413 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
5415 if (Mnemonic != "add")
5417 bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
5418 (Op5.isReg() && Op5.getReg() == ARM::PC);
5419 if (!TryTransform) {
5420 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
5421 (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
5422 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
5423 Op5.isImm() && !Op5.isImm0_508s4());
5427 } else if (!isThumbOne())
5430 if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
5431 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5432 Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
5433 Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))
5436 // If first 2 operands of a 3 operand instruction are the same
5437 // then transform to 2 operand version of the same instruction
5438 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
5439 bool Transform = Op3Reg == Op4Reg;
5441 // For communtative operations, we might be able to transform if we swap
5442 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially
5444 const ARMOperand *LastOp = &Op5;
5446 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
5447 ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
5448 Mnemonic == "and" || Mnemonic == "eor" ||
5449 Mnemonic == "adc" || Mnemonic == "orr")) {
5455 // If both registers are the same then remove one of them from
5456 // the operand list, with certain exceptions.
5458 // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
5459 // 2 operand forms don't exist.
5460 if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
5464 // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
5465 // 3-bits because the ARMARM says not to.
5466 if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
5472 std::swap(Op4, Op5);
5473 Operands.erase(Operands.begin() + 3);
5477 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5478 OperandVector &Operands) {
5479 // FIXME: This is all horribly hacky. We really need a better way to deal
5480 // with optional operands like this in the matcher table.
5482 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5483 // another does not. Specifically, the MOVW instruction does not. So we
5484 // special case it here and remove the defaulted (non-setting) cc_out
5485 // operand if that's the instruction we're trying to match.
5487 // We do this as post-processing of the explicit operands rather than just
5488 // conditionally adding the cc_out in the first place because we need
5489 // to check the type of the parsed immediate operand.
5490 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5491 !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
5492 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5493 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5496 // Register-register 'add' for thumb does not have a cc_out operand
5497 // when there are only two register operands.
5498 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5499 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5500 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5501 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5503 // Register-register 'add' for thumb does not have a cc_out operand
5504 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5505 // have to check the immediate range here since Thumb2 has a variant
5506 // that can handle a different range and has a cc_out operand.
5507 if (((isThumb() && Mnemonic == "add") ||
5508 (isThumbTwo() && Mnemonic == "sub")) &&
5509 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5510 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5511 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5512 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5513 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5514 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5516 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5517 // imm0_4095 variant. That's the least-preferred variant when
5518 // selecting via the generic "add" mnemonic, so to know that we
5519 // should remove the cc_out operand, we have to explicitly check that
5520 // it's not one of the other variants. Ugh.
5521 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5522 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5523 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5524 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5525 // Nest conditions rather than one big 'if' statement for readability.
5527 // If both registers are low, we're in an IT block, and the immediate is
5528 // in range, we should use encoding T1 instead, which has a cc_out.
5530 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5531 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5532 static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5534 // Check against T3. If the second register is the PC, this is an
5535 // alternate form of ADR, which uses encoding T4, so check for that too.
5536 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5537 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5540 // Otherwise, we use encoding T4, which does not have a cc_out
5545 // The thumb2 multiply instruction doesn't have a CCOut register, so
5546 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5547 // use the 16-bit encoding or not.
5548 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5549 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5550 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5551 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5552 static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5553 // If the registers aren't low regs, the destination reg isn't the
5554 // same as one of the source regs, or the cc_out operand is zero
5555 // outside of an IT block, we have to use the 32-bit encoding, so
5556 // remove the cc_out operand.
5557 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5558 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5559 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5560 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5561 static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5562 static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5563 static_cast<ARMOperand &>(*Operands[4]).getReg())))
5566 // Also check the 'mul' syntax variant that doesn't specify an explicit
5567 // destination register.
5568 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5569 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5570 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5571 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5572 // If the registers aren't low regs or the cc_out operand is zero
5573 // outside of an IT block, we have to use the 32-bit encoding, so
5574 // remove the cc_out operand.
5575 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5576 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5582 // Register-register 'add/sub' for thumb does not have a cc_out operand
5583 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5584 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5585 // right, this will result in better diagnostics (which operand is off)
5587 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5588 (Operands.size() == 5 || Operands.size() == 6) &&
5589 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5590 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5591 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5592 (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5593 (Operands.size() == 6 &&
5594 static_cast<ARMOperand &>(*Operands[5]).isImm())))
5600 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5601 OperandVector &Operands) {
5602 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5603 unsigned RegIdx = 3;
5604 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5605 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
5606 if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5607 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
5610 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5611 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5612 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5613 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5614 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5620 static bool isDataTypeToken(StringRef Tok) {
5621 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5622 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5623 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5624 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5625 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5626 Tok == ".f" || Tok == ".d";
5629 // FIXME: This bit should probably be handled via an explicit match class
5630 // in the .td files that matches the suffix instead of having it be
5631 // a literal string token the way it is now.
5632 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5633 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5635 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5636 unsigned VariantID);
5638 static bool RequiresVFPRegListValidation(StringRef Inst,
5639 bool &AcceptSinglePrecisionOnly,
5640 bool &AcceptDoublePrecisionOnly) {
5641 if (Inst.size() < 7)
5644 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5645 StringRef AddressingMode = Inst.substr(4, 2);
5646 if (AddressingMode == "ia" || AddressingMode == "db" ||
5647 AddressingMode == "ea" || AddressingMode == "fd") {
5648 AcceptSinglePrecisionOnly = Inst[6] == 's';
5649 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5657 /// Parse an arm instruction mnemonic followed by its operands.
5658 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5659 SMLoc NameLoc, OperandVector &Operands) {
5660 MCAsmParser &Parser = getParser();
5661 // FIXME: Can this be done via tablegen in some fashion?
5662 bool RequireVFPRegisterListCheck;
5663 bool AcceptSinglePrecisionOnly;
5664 bool AcceptDoublePrecisionOnly;
5665 RequireVFPRegisterListCheck =
5666 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5667 AcceptDoublePrecisionOnly);
5669 // Apply mnemonic aliases before doing anything else, as the destination
5670 // mnemonic may include suffices and we want to handle them normally.
5671 // The generic tblgen'erated code does this later, at the start of
5672 // MatchInstructionImpl(), but that's too late for aliases that include
5673 // any sort of suffix.
5674 uint64_t AvailableFeatures = getAvailableFeatures();
5675 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5676 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5678 // First check for the ARM-specific .req directive.
5679 if (Parser.getTok().is(AsmToken::Identifier) &&
5680 Parser.getTok().getIdentifier() == ".req") {
5681 parseDirectiveReq(Name, NameLoc);
5682 // We always return 'error' for this, as we're done with this
5683 // statement and don't need to match the 'instruction."
5687 // Create the leading tokens for the mnemonic, split by '.' characters.
5688 size_t Start = 0, Next = Name.find('.');
5689 StringRef Mnemonic = Name.slice(Start, Next);
5691 // Split out the predication code and carry setting flag from the mnemonic.
5692 unsigned PredicationCode;
5693 unsigned ProcessorIMod;
5696 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5697 ProcessorIMod, ITMask);
5699 // In Thumb1, only the branch (B) instruction can be predicated.
5700 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5701 Parser.eatToEndOfStatement();
5702 return Error(NameLoc, "conditional execution not supported in Thumb1");
5705 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5707 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5708 // is the mask as it will be for the IT encoding if the conditional
5709 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5710 // where the conditional bit0 is zero, the instruction post-processing
5711 // will adjust the mask accordingly.
5712 if (Mnemonic == "it") {
5713 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5714 if (ITMask.size() > 3) {
5715 Parser.eatToEndOfStatement();
5716 return Error(Loc, "too many conditions on IT instruction");
5719 for (unsigned i = ITMask.size(); i != 0; --i) {
5720 char pos = ITMask[i - 1];
5721 if (pos != 't' && pos != 'e') {
5722 Parser.eatToEndOfStatement();
5723 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5726 if (ITMask[i - 1] == 't')
5729 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5732 // FIXME: This is all a pretty gross hack. We should automatically handle
5733 // optional operands like this via tblgen.
5735 // Next, add the CCOut and ConditionCode operands, if needed.
5737 // For mnemonics which can ever incorporate a carry setting bit or predication
5738 // code, our matching model involves us always generating CCOut and
5739 // ConditionCode operands to match the mnemonic "as written" and then we let
5740 // the matcher deal with finding the right instruction or generating an
5741 // appropriate error.
5742 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5743 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5745 // If we had a carry-set on an instruction that can't do that, issue an
5747 if (!CanAcceptCarrySet && CarrySetting) {
5748 Parser.eatToEndOfStatement();
5749 return Error(NameLoc, "instruction '" + Mnemonic +
5750 "' can not set flags, but 's' suffix specified");
5752 // If we had a predication code on an instruction that can't do that, issue an
5754 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5755 Parser.eatToEndOfStatement();
5756 return Error(NameLoc, "instruction '" + Mnemonic +
5757 "' is not predicable, but condition code specified");
5760 // Add the carry setting operand, if necessary.
5761 if (CanAcceptCarrySet) {
5762 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5763 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5767 // Add the predication code operand, if necessary.
5768 if (CanAcceptPredicationCode) {
5769 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5771 Operands.push_back(ARMOperand::CreateCondCode(
5772 ARMCC::CondCodes(PredicationCode), Loc));
5775 // Add the processor imod operand, if necessary.
5776 if (ProcessorIMod) {
5777 Operands.push_back(ARMOperand::CreateImm(
5778 MCConstantExpr::create(ProcessorIMod, getContext()),
5780 } else if (Mnemonic == "cps" && isMClass()) {
5781 return Error(NameLoc, "instruction 'cps' requires effect for M-class");
5784 // Add the remaining tokens in the mnemonic.
5785 while (Next != StringRef::npos) {
5787 Next = Name.find('.', Start + 1);
5788 StringRef ExtraToken = Name.slice(Start, Next);
5790 // Some NEON instructions have an optional datatype suffix that is
5791 // completely ignored. Check for that.
5792 if (isDataTypeToken(ExtraToken) &&
5793 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5796 // For for ARM mode generate an error if the .n qualifier is used.
5797 if (ExtraToken == ".n" && !isThumb()) {
5798 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5799 Parser.eatToEndOfStatement();
5800 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5804 // The .n qualifier is always discarded as that is what the tables
5805 // and matcher expect. In ARM mode the .w qualifier has no effect,
5806 // so discard it to avoid errors that can be caused by the matcher.
5807 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5808 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5809 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5813 // Read the remaining operands.
5814 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5815 // Read the first operand.
5816 if (parseOperand(Operands, Mnemonic)) {
5817 Parser.eatToEndOfStatement();
5821 while (getLexer().is(AsmToken::Comma)) {
5822 Parser.Lex(); // Eat the comma.
5824 // Parse and remember the operand.
5825 if (parseOperand(Operands, Mnemonic)) {
5826 Parser.eatToEndOfStatement();
5832 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5833 SMLoc Loc = getLexer().getLoc();
5834 Parser.eatToEndOfStatement();
5835 return Error(Loc, "unexpected token in argument list");
5838 Parser.Lex(); // Consume the EndOfStatement
5840 if (RequireVFPRegisterListCheck) {
5841 ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
5842 if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5843 return Error(Op.getStartLoc(),
5844 "VFP/Neon single precision register expected");
5845 if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5846 return Error(Op.getStartLoc(),
5847 "VFP/Neon double precision register expected");
5850 tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands);
5852 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5853 // do and don't have a cc_out optional-def operand. With some spot-checks
5854 // of the operand list, we can figure out which variant we're trying to
5855 // parse and adjust accordingly before actually matching. We shouldn't ever
5856 // try to remove a cc_out operand that was explicitly set on the
5857 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5858 // table driven matcher doesn't fit well with the ARM instruction set.
5859 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
5860 Operands.erase(Operands.begin() + 1);
5862 // Some instructions have the same mnemonic, but don't always
5863 // have a predicate. Distinguish them here and delete the
5864 // predicate if needed.
5865 if (shouldOmitPredicateOperand(Mnemonic, Operands))
5866 Operands.erase(Operands.begin() + 1);
5868 // ARM mode 'blx' need special handling, as the register operand version
5869 // is predicable, but the label operand version is not. So, we can't rely
5870 // on the Mnemonic based checking to correctly figure out when to put
5871 // a k_CondCode operand in the list. If we're trying to match the label
5872 // version, remove the k_CondCode operand here.
5873 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5874 static_cast<ARMOperand &>(*Operands[2]).isImm())
5875 Operands.erase(Operands.begin() + 1);
5877 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5878 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5879 // a single GPRPair reg operand is used in the .td file to replace the two
5880 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5881 // expressed as a GPRPair, so we have to manually merge them.
5882 // FIXME: We would really like to be able to tablegen'erate this.
5883 if (!isThumb() && Operands.size() > 4 &&
5884 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5885 Mnemonic == "stlexd")) {
5886 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5887 unsigned Idx = isLoad ? 2 : 3;
5888 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
5889 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
5891 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5892 // Adjust only if Op1 and Op2 are GPRs.
5893 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5894 MRC.contains(Op2.getReg())) {
5895 unsigned Reg1 = Op1.getReg();
5896 unsigned Reg2 = Op2.getReg();
5897 unsigned Rt = MRI->getEncodingValue(Reg1);
5898 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5900 // Rt2 must be Rt + 1 and Rt must be even.
5901 if (Rt + 1 != Rt2 || (Rt & 1)) {
5902 Error(Op2.getStartLoc(), isLoad
5903 ? "destination operands must be sequential"
5904 : "source operands must be sequential");
5907 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5908 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5910 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5911 Operands.erase(Operands.begin() + Idx + 1);
5915 // GNU Assembler extension (compatibility)
5916 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5917 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5918 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5920 assert(Op2.isReg() && "expected register argument");
5922 unsigned SuperReg = MRI->getMatchingSuperReg(
5923 Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5925 assert(SuperReg && "expected register pair");
5927 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5930 Operands.begin() + 3,
5931 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
5935 // FIXME: As said above, this is all a pretty gross hack. This instruction
5936 // does not fit with other "subs" and tblgen.
5937 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5938 // so the Mnemonic is the original name "subs" and delete the predicate
5939 // operand so it will match the table entry.
5940 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5941 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5942 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
5943 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5944 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
5945 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5946 Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
5947 Operands.erase(Operands.begin() + 1);
5952 // Validate context-sensitive operand constraints.
5954 // return 'true' if register list contains non-low GPR registers,
5955 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5956 // 'containsReg' to true.
5957 static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
5958 unsigned Reg, unsigned HiReg,
5959 bool &containsReg) {
5960 containsReg = false;
5961 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5962 unsigned OpReg = Inst.getOperand(i).getReg();
5965 // Anything other than a low register isn't legal here.
5966 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5972 // Check if the specified regisgter is in the register list of the inst,
5973 // starting at the indicated operand number.
5974 static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
5975 for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
5976 unsigned OpReg = Inst.getOperand(i).getReg();
5983 // Return true if instruction has the interesting property of being
5984 // allowed in IT blocks, but not being predicable.
5985 static bool instIsBreakpoint(const MCInst &Inst) {
5986 return Inst.getOpcode() == ARM::tBKPT ||
5987 Inst.getOpcode() == ARM::BKPT ||
5988 Inst.getOpcode() == ARM::tHLT ||
5989 Inst.getOpcode() == ARM::HLT;
5993 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
5994 const OperandVector &Operands,
5995 unsigned ListNo, bool IsARPop) {
5996 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
5997 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
5999 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6000 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
6001 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6003 if (!IsARPop && ListContainsSP)
6004 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6005 "SP may not be in the register list");
6006 else if (ListContainsPC && ListContainsLR)
6007 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6008 "PC and LR may not be in the register list simultaneously");
6009 else if (inITBlock() && !lastInITBlock() && ListContainsPC)
6010 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6011 "instruction must be outside of IT block or the last "
6012 "instruction in an IT block");
6016 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
6017 const OperandVector &Operands,
6019 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6020 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6022 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6023 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6025 if (ListContainsSP && ListContainsPC)
6026 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6027 "SP and PC may not be in the register list");
6028 else if (ListContainsSP)
6029 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6030 "SP may not be in the register list");
6031 else if (ListContainsPC)
6032 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6033 "PC may not be in the register list");
6037 // FIXME: We would really like to be able to tablegen'erate this.
6038 bool ARMAsmParser::validateInstruction(MCInst &Inst,
6039 const OperandVector &Operands) {
6040 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
6041 SMLoc Loc = Operands[0]->getStartLoc();
6043 // Check the IT block state first.
6044 // NOTE: BKPT and HLT instructions have the interesting property of being
6045 // allowed in IT blocks, but not being predicable. They just always execute.
6046 if (inITBlock() && !instIsBreakpoint(Inst)) {
6048 if (ITState.FirstCond)
6049 ITState.FirstCond = false;
6051 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
6052 // The instruction must be predicable.
6053 if (!MCID.isPredicable())
6054 return Error(Loc, "instructions in IT block must be predicable");
6055 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
6056 unsigned ITCond = Bit ? ITState.Cond :
6057 ARMCC::getOppositeCondition(ITState.Cond);
6058 if (Cond != ITCond) {
6059 // Find the condition code Operand to get its SMLoc information.
6061 for (unsigned I = 1; I < Operands.size(); ++I)
6062 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
6063 CondLoc = Operands[I]->getStartLoc();
6064 return Error(CondLoc, "incorrect condition in IT block; got '" +
6065 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
6066 "', but expected '" +
6067 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
6069 // Check for non-'al' condition codes outside of the IT block.
6070 } else if (isThumbTwo() && MCID.isPredicable() &&
6071 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6072 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
6073 Inst.getOpcode() != ARM::t2Bcc)
6074 return Error(Loc, "predicated instructions must be in IT block");
6076 const unsigned Opcode = Inst.getOpcode();
6080 case ARM::LDRD_POST: {
6081 const unsigned RtReg = Inst.getOperand(0).getReg();
6084 if (RtReg == ARM::LR)
6085 return Error(Operands[3]->getStartLoc(),
6088 const unsigned Rt = MRI->getEncodingValue(RtReg);
6089 // Rt must be even-numbered.
6091 return Error(Operands[3]->getStartLoc(),
6092 "Rt must be even-numbered");
6094 // Rt2 must be Rt + 1.
6095 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6097 return Error(Operands[3]->getStartLoc(),
6098 "destination operands must be sequential");
6100 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
6101 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6102 // For addressing modes with writeback, the base register needs to be
6103 // different from the destination registers.
6104 if (Rn == Rt || Rn == Rt2)
6105 return Error(Operands[3]->getStartLoc(),
6106 "base register needs to be different from destination "
6113 case ARM::t2LDRD_PRE:
6114 case ARM::t2LDRD_POST: {
6115 // Rt2 must be different from Rt.
6116 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6117 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6119 return Error(Operands[3]->getStartLoc(),
6120 "destination operands can't be identical");
6124 const unsigned RmReg = Inst.getOperand(0).getReg();
6125 // Rm = SP is no longer unpredictable in v8-A
6126 if (RmReg == ARM::SP && !hasV8Ops())
6127 return Error(Operands[2]->getStartLoc(),
6128 "r13 (SP) is an unpredictable operand to BXJ");
6132 // Rt2 must be Rt + 1.
6133 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6134 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6136 return Error(Operands[3]->getStartLoc(),
6137 "source operands must be sequential");
6141 case ARM::STRD_POST: {
6142 // Rt2 must be Rt + 1.
6143 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6144 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6146 return Error(Operands[3]->getStartLoc(),
6147 "source operands must be sequential");
6150 case ARM::STR_PRE_IMM:
6151 case ARM::STR_PRE_REG:
6152 case ARM::STR_POST_IMM:
6153 case ARM::STR_POST_REG:
6155 case ARM::STRH_POST:
6156 case ARM::STRB_PRE_IMM:
6157 case ARM::STRB_PRE_REG:
6158 case ARM::STRB_POST_IMM:
6159 case ARM::STRB_POST_REG: {
6160 // Rt must be different from Rn.
6161 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6162 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6165 return Error(Operands[3]->getStartLoc(),
6166 "source register and base register can't be identical");
6169 case ARM::LDR_PRE_IMM:
6170 case ARM::LDR_PRE_REG:
6171 case ARM::LDR_POST_IMM:
6172 case ARM::LDR_POST_REG:
6174 case ARM::LDRH_POST:
6175 case ARM::LDRSH_PRE:
6176 case ARM::LDRSH_POST:
6177 case ARM::LDRB_PRE_IMM:
6178 case ARM::LDRB_PRE_REG:
6179 case ARM::LDRB_POST_IMM:
6180 case ARM::LDRB_POST_REG:
6181 case ARM::LDRSB_PRE:
6182 case ARM::LDRSB_POST: {
6183 // Rt must be different from Rn.
6184 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6185 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6188 return Error(Operands[3]->getStartLoc(),
6189 "destination register and base register can't be identical");
6194 // Width must be in range [1, 32-lsb].
6195 unsigned LSB = Inst.getOperand(2).getImm();
6196 unsigned Widthm1 = Inst.getOperand(3).getImm();
6197 if (Widthm1 >= 32 - LSB)
6198 return Error(Operands[5]->getStartLoc(),
6199 "bitfield width must be in range [1,32-lsb]");
6202 // Notionally handles ARM::tLDMIA_UPD too.
6204 // If we're parsing Thumb2, the .w variant is available and handles
6205 // most cases that are normally illegal for a Thumb1 LDM instruction.
6206 // We'll make the transformation in processInstruction() if necessary.
6208 // Thumb LDM instructions are writeback iff the base register is not
6209 // in the register list.
6210 unsigned Rn = Inst.getOperand(0).getReg();
6211 bool HasWritebackToken =
6212 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6213 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
6214 bool ListContainsBase;
6215 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6216 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
6217 "registers must be in range r0-r7");
6218 // If we should have writeback, then there should be a '!' token.
6219 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
6220 return Error(Operands[2]->getStartLoc(),
6221 "writeback operator '!' expected");
6222 // If we should not have writeback, there must not be a '!'. This is
6223 // true even for the 32-bit wide encodings.
6224 if (ListContainsBase && HasWritebackToken)
6225 return Error(Operands[3]->getStartLoc(),
6226 "writeback operator '!' not allowed when base register "
6227 "in register list");
6229 if (validatetLDMRegList(Inst, Operands, 3))
6233 case ARM::LDMIA_UPD:
6234 case ARM::LDMDB_UPD:
6235 case ARM::LDMIB_UPD:
6236 case ARM::LDMDA_UPD:
6237 // ARM variants loading and updating the same register are only officially
6238 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
6241 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6242 return Error(Operands.back()->getStartLoc(),
6243 "writeback register not allowed in register list");
6247 if (validatetLDMRegList(Inst, Operands, 3))
6252 if (validatetSTMRegList(Inst, Operands, 3))
6255 case ARM::t2LDMIA_UPD:
6256 case ARM::t2LDMDB_UPD:
6257 case ARM::t2STMIA_UPD:
6258 case ARM::t2STMDB_UPD: {
6259 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6260 return Error(Operands.back()->getStartLoc(),
6261 "writeback register not allowed in register list");
6263 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
6264 if (validatetLDMRegList(Inst, Operands, 3))
6267 if (validatetSTMRegList(Inst, Operands, 3))
6272 case ARM::sysLDMIA_UPD:
6273 case ARM::sysLDMDA_UPD:
6274 case ARM::sysLDMDB_UPD:
6275 case ARM::sysLDMIB_UPD:
6276 if (!listContainsReg(Inst, 3, ARM::PC))
6277 return Error(Operands[4]->getStartLoc(),
6278 "writeback register only allowed on system LDM "
6279 "if PC in register-list");
6281 case ARM::sysSTMIA_UPD:
6282 case ARM::sysSTMDA_UPD:
6283 case ARM::sysSTMDB_UPD:
6284 case ARM::sysSTMIB_UPD:
6285 return Error(Operands[2]->getStartLoc(),
6286 "system STM cannot have writeback register");
6288 // The second source operand must be the same register as the destination
6291 // In this case, we must directly check the parsed operands because the
6292 // cvtThumbMultiply() function is written in such a way that it guarantees
6293 // this first statement is always true for the new Inst. Essentially, the
6294 // destination is unconditionally copied into the second source operand
6295 // without checking to see if it matches what we actually parsed.
6296 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
6297 ((ARMOperand &)*Operands[5]).getReg()) &&
6298 (((ARMOperand &)*Operands[3]).getReg() !=
6299 ((ARMOperand &)*Operands[4]).getReg())) {
6300 return Error(Operands[3]->getStartLoc(),
6301 "destination register must match source register");
6305 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
6306 // so only issue a diagnostic for thumb1. The instructions will be
6307 // switched to the t2 encodings in processInstruction() if necessary.
6309 bool ListContainsBase;
6310 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6312 return Error(Operands[2]->getStartLoc(),
6313 "registers must be in range r0-r7 or pc");
6314 if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
6319 bool ListContainsBase;
6320 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6322 return Error(Operands[2]->getStartLoc(),
6323 "registers must be in range r0-r7 or lr");
6324 if (validatetSTMRegList(Inst, Operands, 2))
6328 case ARM::tSTMIA_UPD: {
6329 bool ListContainsBase, InvalidLowList;
6330 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6331 0, ListContainsBase);
6332 if (InvalidLowList && !isThumbTwo())
6333 return Error(Operands[4]->getStartLoc(),
6334 "registers must be in range r0-r7");
6336 // This would be converted to a 32-bit stm, but that's not valid if the
6337 // writeback register is in the list.
6338 if (InvalidLowList && ListContainsBase)
6339 return Error(Operands[4]->getStartLoc(),
6340 "writeback operator '!' not allowed when base register "
6341 "in register list");
6343 if (validatetSTMRegList(Inst, Operands, 4))
6347 case ARM::tADDrSP: {
6348 // If the non-SP source operand and the destination operand are not the
6349 // same, we need thumb2 (for the wide encoding), or we have an error.
6350 if (!isThumbTwo() &&
6351 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6352 return Error(Operands[4]->getStartLoc(),
6353 "source register must be the same as destination");
6357 // Final range checking for Thumb unconditional branch instructions.
6359 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6360 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6363 int op = (Operands[2]->isImm()) ? 2 : 3;
6364 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6365 return Error(Operands[op]->getStartLoc(), "branch target out of range");
6368 // Final range checking for Thumb conditional branch instructions.
6370 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6371 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6374 int Op = (Operands[2]->isImm()) ? 2 : 3;
6375 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6376 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6381 case ARM::t2MOVTi16:
6383 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6384 // especially when we turn it into a movw and the expression <symbol> does
6385 // not have a :lower16: or :upper16 as part of the expression. We don't
6386 // want the behavior of silently truncating, which can be unexpected and
6387 // lead to bugs that are difficult to find since this is an easy mistake
6389 int i = (Operands[3]->isImm()) ? 3 : 4;
6390 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6391 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6393 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6395 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6396 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6397 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6400 "immediate expression for mov requires :lower16: or :upper16");
6408 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6410 default: llvm_unreachable("unexpected opcode!");
6412 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6413 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6414 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6415 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6416 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6417 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6418 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
6419 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6420 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6423 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6424 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6425 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6426 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6427 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6429 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6430 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6431 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6432 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6433 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6435 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
6436 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6437 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6438 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6439 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6442 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6443 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6444 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6445 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6446 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6447 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6448 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6449 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6450 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6451 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6452 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
6453 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6454 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6455 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6456 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6459 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6460 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6461 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6462 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6463 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6464 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6465 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6466 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6467 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6468 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6469 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6470 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6471 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
6472 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6473 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6474 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
6475 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6476 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6479 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6480 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6481 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6482 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6483 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6484 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6485 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6486 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6487 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6488 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6489 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
6490 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6491 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6492 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6493 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6496 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6497 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6498 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6499 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6500 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6501 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6502 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6503 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6504 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6505 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6506 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6507 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6508 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
6509 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6510 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6511 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
6512 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6513 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6517 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6519 default: llvm_unreachable("unexpected opcode!");
6521 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6522 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6523 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6524 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6525 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6526 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6527 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
6528 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6529 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6532 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6533 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6534 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6535 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6536 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6537 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6538 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6539 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6540 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6541 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6542 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
6543 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6544 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6545 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6546 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6549 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6550 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6551 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6552 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6553 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6554 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6555 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6556 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6557 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6558 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6559 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6560 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6561 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
6562 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6563 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6564 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6565 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6566 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6569 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6570 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6571 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6572 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6573 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6574 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6575 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6576 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6577 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6578 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6579 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
6580 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6581 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6582 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6583 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6586 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6587 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6588 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6589 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6590 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6591 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6592 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6593 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6594 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6595 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6596 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6597 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6598 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
6599 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6600 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6601 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
6602 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6603 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6606 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6607 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6608 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6609 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6610 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6611 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6612 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6613 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6614 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6615 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6616 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
6617 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6618 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6619 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6620 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6623 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6624 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6625 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6626 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6627 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6628 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6629 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6630 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6631 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6632 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6633 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6634 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6635 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
6636 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6637 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6638 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6639 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6640 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6643 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6644 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6645 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6646 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6647 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6648 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6649 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6650 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6651 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6652 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6653 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6654 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6655 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6656 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6657 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6658 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6659 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6660 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6664 bool ARMAsmParser::processInstruction(MCInst &Inst,
6665 const OperandVector &Operands,
6667 switch (Inst.getOpcode()) {
6668 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6669 case ARM::LDRT_POST:
6670 case ARM::LDRBT_POST: {
6671 const unsigned Opcode =
6672 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6673 : ARM::LDRBT_POST_IMM;
6675 TmpInst.setOpcode(Opcode);
6676 TmpInst.addOperand(Inst.getOperand(0));
6677 TmpInst.addOperand(Inst.getOperand(1));
6678 TmpInst.addOperand(Inst.getOperand(1));
6679 TmpInst.addOperand(MCOperand::createReg(0));
6680 TmpInst.addOperand(MCOperand::createImm(0));
6681 TmpInst.addOperand(Inst.getOperand(2));
6682 TmpInst.addOperand(Inst.getOperand(3));
6686 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6687 case ARM::STRT_POST:
6688 case ARM::STRBT_POST: {
6689 const unsigned Opcode =
6690 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6691 : ARM::STRBT_POST_IMM;
6693 TmpInst.setOpcode(Opcode);
6694 TmpInst.addOperand(Inst.getOperand(1));
6695 TmpInst.addOperand(Inst.getOperand(0));
6696 TmpInst.addOperand(Inst.getOperand(1));
6697 TmpInst.addOperand(MCOperand::createReg(0));
6698 TmpInst.addOperand(MCOperand::createImm(0));
6699 TmpInst.addOperand(Inst.getOperand(2));
6700 TmpInst.addOperand(Inst.getOperand(3));
6704 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6706 if (Inst.getOperand(1).getReg() != ARM::PC ||
6707 Inst.getOperand(5).getReg() != 0 ||
6708 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
6711 TmpInst.setOpcode(ARM::ADR);
6712 TmpInst.addOperand(Inst.getOperand(0));
6713 if (Inst.getOperand(2).isImm()) {
6714 // Immediate (mod_imm) will be in its encoded form, we must unencode it
6715 // before passing it to the ADR instruction.
6716 unsigned Enc = Inst.getOperand(2).getImm();
6717 TmpInst.addOperand(MCOperand::createImm(
6718 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
6720 // Turn PC-relative expression into absolute expression.
6721 // Reading PC provides the start of the current instruction + 8 and
6722 // the transform to adr is biased by that.
6723 MCSymbol *Dot = getContext().createTempSymbol();
6725 const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
6726 const MCExpr *InstPC = MCSymbolRefExpr::create(Dot,
6727 MCSymbolRefExpr::VK_None,
6729 const MCExpr *Const8 = MCConstantExpr::create(8, getContext());
6730 const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8,
6732 const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr,
6734 TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
6736 TmpInst.addOperand(Inst.getOperand(3));
6737 TmpInst.addOperand(Inst.getOperand(4));
6741 // Aliases for alternate PC+imm syntax of LDR instructions.
6742 case ARM::t2LDRpcrel:
6743 // Select the narrow version if the immediate will fit.
6744 if (Inst.getOperand(1).getImm() > 0 &&
6745 Inst.getOperand(1).getImm() <= 0xff &&
6746 !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
6747 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
6748 Inst.setOpcode(ARM::tLDRpci);
6750 Inst.setOpcode(ARM::t2LDRpci);
6752 case ARM::t2LDRBpcrel:
6753 Inst.setOpcode(ARM::t2LDRBpci);
6755 case ARM::t2LDRHpcrel:
6756 Inst.setOpcode(ARM::t2LDRHpci);
6758 case ARM::t2LDRSBpcrel:
6759 Inst.setOpcode(ARM::t2LDRSBpci);
6761 case ARM::t2LDRSHpcrel:
6762 Inst.setOpcode(ARM::t2LDRSHpci);
6764 // Handle NEON VST complex aliases.
6765 case ARM::VST1LNdWB_register_Asm_8:
6766 case ARM::VST1LNdWB_register_Asm_16:
6767 case ARM::VST1LNdWB_register_Asm_32: {
6769 // Shuffle the operands around so the lane index operand is in the
6772 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6773 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6774 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6775 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6776 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6777 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6778 TmpInst.addOperand(Inst.getOperand(1)); // lane
6779 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6780 TmpInst.addOperand(Inst.getOperand(6));
6785 case ARM::VST2LNdWB_register_Asm_8:
6786 case ARM::VST2LNdWB_register_Asm_16:
6787 case ARM::VST2LNdWB_register_Asm_32:
6788 case ARM::VST2LNqWB_register_Asm_16:
6789 case ARM::VST2LNqWB_register_Asm_32: {
6791 // Shuffle the operands around so the lane index operand is in the
6794 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6795 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6796 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6797 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6798 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6799 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6800 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6802 TmpInst.addOperand(Inst.getOperand(1)); // lane
6803 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6804 TmpInst.addOperand(Inst.getOperand(6));
6809 case ARM::VST3LNdWB_register_Asm_8:
6810 case ARM::VST3LNdWB_register_Asm_16:
6811 case ARM::VST3LNdWB_register_Asm_32:
6812 case ARM::VST3LNqWB_register_Asm_16:
6813 case ARM::VST3LNqWB_register_Asm_32: {
6815 // Shuffle the operands around so the lane index operand is in the
6818 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6819 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6820 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6821 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6822 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6823 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6824 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6826 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6828 TmpInst.addOperand(Inst.getOperand(1)); // lane
6829 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6830 TmpInst.addOperand(Inst.getOperand(6));
6835 case ARM::VST4LNdWB_register_Asm_8:
6836 case ARM::VST4LNdWB_register_Asm_16:
6837 case ARM::VST4LNdWB_register_Asm_32:
6838 case ARM::VST4LNqWB_register_Asm_16:
6839 case ARM::VST4LNqWB_register_Asm_32: {
6841 // Shuffle the operands around so the lane index operand is in the
6844 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6845 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6846 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6847 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6848 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6849 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6850 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6852 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6854 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6856 TmpInst.addOperand(Inst.getOperand(1)); // lane
6857 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6858 TmpInst.addOperand(Inst.getOperand(6));
6863 case ARM::VST1LNdWB_fixed_Asm_8:
6864 case ARM::VST1LNdWB_fixed_Asm_16:
6865 case ARM::VST1LNdWB_fixed_Asm_32: {
6867 // Shuffle the operands around so the lane index operand is in the
6870 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6871 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6872 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6873 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6874 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
6875 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6876 TmpInst.addOperand(Inst.getOperand(1)); // lane
6877 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6878 TmpInst.addOperand(Inst.getOperand(5));
6883 case ARM::VST2LNdWB_fixed_Asm_8:
6884 case ARM::VST2LNdWB_fixed_Asm_16:
6885 case ARM::VST2LNdWB_fixed_Asm_32:
6886 case ARM::VST2LNqWB_fixed_Asm_16:
6887 case ARM::VST2LNqWB_fixed_Asm_32: {
6889 // Shuffle the operands around so the lane index operand is in the
6892 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6893 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6894 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6895 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6896 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
6897 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6898 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6900 TmpInst.addOperand(Inst.getOperand(1)); // lane
6901 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6902 TmpInst.addOperand(Inst.getOperand(5));
6907 case ARM::VST3LNdWB_fixed_Asm_8:
6908 case ARM::VST3LNdWB_fixed_Asm_16:
6909 case ARM::VST3LNdWB_fixed_Asm_32:
6910 case ARM::VST3LNqWB_fixed_Asm_16:
6911 case ARM::VST3LNqWB_fixed_Asm_32: {
6913 // Shuffle the operands around so the lane index operand is in the
6916 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6917 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6918 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6919 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6920 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
6921 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6922 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6924 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6926 TmpInst.addOperand(Inst.getOperand(1)); // lane
6927 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6928 TmpInst.addOperand(Inst.getOperand(5));
6933 case ARM::VST4LNdWB_fixed_Asm_8:
6934 case ARM::VST4LNdWB_fixed_Asm_16:
6935 case ARM::VST4LNdWB_fixed_Asm_32:
6936 case ARM::VST4LNqWB_fixed_Asm_16:
6937 case ARM::VST4LNqWB_fixed_Asm_32: {
6939 // Shuffle the operands around so the lane index operand is in the
6942 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6943 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6944 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6945 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6946 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
6947 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6948 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6950 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6952 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6954 TmpInst.addOperand(Inst.getOperand(1)); // lane
6955 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6956 TmpInst.addOperand(Inst.getOperand(5));
6961 case ARM::VST1LNdAsm_8:
6962 case ARM::VST1LNdAsm_16:
6963 case ARM::VST1LNdAsm_32: {
6965 // Shuffle the operands around so the lane index operand is in the
6968 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6969 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6970 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6971 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6972 TmpInst.addOperand(Inst.getOperand(1)); // lane
6973 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6974 TmpInst.addOperand(Inst.getOperand(5));
6979 case ARM::VST2LNdAsm_8:
6980 case ARM::VST2LNdAsm_16:
6981 case ARM::VST2LNdAsm_32:
6982 case ARM::VST2LNqAsm_16:
6983 case ARM::VST2LNqAsm_32: {
6985 // Shuffle the operands around so the lane index operand is in the
6988 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6989 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6990 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6991 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6992 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6994 TmpInst.addOperand(Inst.getOperand(1)); // lane
6995 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6996 TmpInst.addOperand(Inst.getOperand(5));
7001 case ARM::VST3LNdAsm_8:
7002 case ARM::VST3LNdAsm_16:
7003 case ARM::VST3LNdAsm_32:
7004 case ARM::VST3LNqAsm_16:
7005 case ARM::VST3LNqAsm_32: {
7007 // Shuffle the operands around so the lane index operand is in the
7010 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7011 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7012 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7013 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7014 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7016 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7018 TmpInst.addOperand(Inst.getOperand(1)); // lane
7019 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7020 TmpInst.addOperand(Inst.getOperand(5));
7025 case ARM::VST4LNdAsm_8:
7026 case ARM::VST4LNdAsm_16:
7027 case ARM::VST4LNdAsm_32:
7028 case ARM::VST4LNqAsm_16:
7029 case ARM::VST4LNqAsm_32: {
7031 // Shuffle the operands around so the lane index operand is in the
7034 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7035 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7036 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7037 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7038 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7040 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7042 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7044 TmpInst.addOperand(Inst.getOperand(1)); // lane
7045 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7046 TmpInst.addOperand(Inst.getOperand(5));
7051 // Handle NEON VLD complex aliases.
7052 case ARM::VLD1LNdWB_register_Asm_8:
7053 case ARM::VLD1LNdWB_register_Asm_16:
7054 case ARM::VLD1LNdWB_register_Asm_32: {
7056 // Shuffle the operands around so the lane index operand is in the
7059 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7060 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7061 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7062 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7063 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7064 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7065 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7066 TmpInst.addOperand(Inst.getOperand(1)); // lane
7067 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7068 TmpInst.addOperand(Inst.getOperand(6));
7073 case ARM::VLD2LNdWB_register_Asm_8:
7074 case ARM::VLD2LNdWB_register_Asm_16:
7075 case ARM::VLD2LNdWB_register_Asm_32:
7076 case ARM::VLD2LNqWB_register_Asm_16:
7077 case ARM::VLD2LNqWB_register_Asm_32: {
7079 // Shuffle the operands around so the lane index operand is in the
7082 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7083 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7084 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7086 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7087 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7088 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7089 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7090 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7091 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7093 TmpInst.addOperand(Inst.getOperand(1)); // lane
7094 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7095 TmpInst.addOperand(Inst.getOperand(6));
7100 case ARM::VLD3LNdWB_register_Asm_8:
7101 case ARM::VLD3LNdWB_register_Asm_16:
7102 case ARM::VLD3LNdWB_register_Asm_32:
7103 case ARM::VLD3LNqWB_register_Asm_16:
7104 case ARM::VLD3LNqWB_register_Asm_32: {
7106 // Shuffle the operands around so the lane index operand is in the
7109 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7110 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7111 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7113 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7115 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7116 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7117 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7118 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7119 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7120 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7122 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7124 TmpInst.addOperand(Inst.getOperand(1)); // lane
7125 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7126 TmpInst.addOperand(Inst.getOperand(6));
7131 case ARM::VLD4LNdWB_register_Asm_8:
7132 case ARM::VLD4LNdWB_register_Asm_16:
7133 case ARM::VLD4LNdWB_register_Asm_32:
7134 case ARM::VLD4LNqWB_register_Asm_16:
7135 case ARM::VLD4LNqWB_register_Asm_32: {
7137 // Shuffle the operands around so the lane index operand is in the
7140 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7141 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7142 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7144 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7146 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7148 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7149 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7150 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7151 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7152 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7153 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7155 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7157 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7159 TmpInst.addOperand(Inst.getOperand(1)); // lane
7160 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7161 TmpInst.addOperand(Inst.getOperand(6));
7166 case ARM::VLD1LNdWB_fixed_Asm_8:
7167 case ARM::VLD1LNdWB_fixed_Asm_16:
7168 case ARM::VLD1LNdWB_fixed_Asm_32: {
7170 // Shuffle the operands around so the lane index operand is in the
7173 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7174 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7175 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7176 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7177 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7178 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7179 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7180 TmpInst.addOperand(Inst.getOperand(1)); // lane
7181 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7182 TmpInst.addOperand(Inst.getOperand(5));
7187 case ARM::VLD2LNdWB_fixed_Asm_8:
7188 case ARM::VLD2LNdWB_fixed_Asm_16:
7189 case ARM::VLD2LNdWB_fixed_Asm_32:
7190 case ARM::VLD2LNqWB_fixed_Asm_16:
7191 case ARM::VLD2LNqWB_fixed_Asm_32: {
7193 // Shuffle the operands around so the lane index operand is in the
7196 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7197 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7198 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7200 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7201 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7202 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7203 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7204 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7205 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7207 TmpInst.addOperand(Inst.getOperand(1)); // lane
7208 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7209 TmpInst.addOperand(Inst.getOperand(5));
7214 case ARM::VLD3LNdWB_fixed_Asm_8:
7215 case ARM::VLD3LNdWB_fixed_Asm_16:
7216 case ARM::VLD3LNdWB_fixed_Asm_32:
7217 case ARM::VLD3LNqWB_fixed_Asm_16:
7218 case ARM::VLD3LNqWB_fixed_Asm_32: {
7220 // Shuffle the operands around so the lane index operand is in the
7223 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7224 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7225 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7227 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7229 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7230 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7231 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7232 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7233 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7234 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7236 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7238 TmpInst.addOperand(Inst.getOperand(1)); // lane
7239 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7240 TmpInst.addOperand(Inst.getOperand(5));
7245 case ARM::VLD4LNdWB_fixed_Asm_8:
7246 case ARM::VLD4LNdWB_fixed_Asm_16:
7247 case ARM::VLD4LNdWB_fixed_Asm_32:
7248 case ARM::VLD4LNqWB_fixed_Asm_16:
7249 case ARM::VLD4LNqWB_fixed_Asm_32: {
7251 // Shuffle the operands around so the lane index operand is in the
7254 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7255 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7256 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7258 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7260 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7262 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7263 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7264 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7265 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7266 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7267 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7269 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7271 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7273 TmpInst.addOperand(Inst.getOperand(1)); // lane
7274 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7275 TmpInst.addOperand(Inst.getOperand(5));
7280 case ARM::VLD1LNdAsm_8:
7281 case ARM::VLD1LNdAsm_16:
7282 case ARM::VLD1LNdAsm_32: {
7284 // Shuffle the operands around so the lane index operand is in the
7287 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7288 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7289 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7290 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7291 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7292 TmpInst.addOperand(Inst.getOperand(1)); // lane
7293 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7294 TmpInst.addOperand(Inst.getOperand(5));
7299 case ARM::VLD2LNdAsm_8:
7300 case ARM::VLD2LNdAsm_16:
7301 case ARM::VLD2LNdAsm_32:
7302 case ARM::VLD2LNqAsm_16:
7303 case ARM::VLD2LNqAsm_32: {
7305 // Shuffle the operands around so the lane index operand is in the
7308 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7309 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7310 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7312 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7313 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7314 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7315 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7317 TmpInst.addOperand(Inst.getOperand(1)); // lane
7318 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7319 TmpInst.addOperand(Inst.getOperand(5));
7324 case ARM::VLD3LNdAsm_8:
7325 case ARM::VLD3LNdAsm_16:
7326 case ARM::VLD3LNdAsm_32:
7327 case ARM::VLD3LNqAsm_16:
7328 case ARM::VLD3LNqAsm_32: {
7330 // Shuffle the operands around so the lane index operand is in the
7333 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7334 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7335 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7337 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7339 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7340 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7341 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7342 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7344 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7346 TmpInst.addOperand(Inst.getOperand(1)); // lane
7347 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7348 TmpInst.addOperand(Inst.getOperand(5));
7353 case ARM::VLD4LNdAsm_8:
7354 case ARM::VLD4LNdAsm_16:
7355 case ARM::VLD4LNdAsm_32:
7356 case ARM::VLD4LNqAsm_16:
7357 case ARM::VLD4LNqAsm_32: {
7359 // Shuffle the operands around so the lane index operand is in the
7362 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7363 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7364 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7366 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7368 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7370 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7371 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7372 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7373 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7375 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7377 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7379 TmpInst.addOperand(Inst.getOperand(1)); // lane
7380 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7381 TmpInst.addOperand(Inst.getOperand(5));
7386 // VLD3DUP single 3-element structure to all lanes instructions.
7387 case ARM::VLD3DUPdAsm_8:
7388 case ARM::VLD3DUPdAsm_16:
7389 case ARM::VLD3DUPdAsm_32:
7390 case ARM::VLD3DUPqAsm_8:
7391 case ARM::VLD3DUPqAsm_16:
7392 case ARM::VLD3DUPqAsm_32: {
7395 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7396 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7397 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7399 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7401 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7402 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7403 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7404 TmpInst.addOperand(Inst.getOperand(4));
7409 case ARM::VLD3DUPdWB_fixed_Asm_8:
7410 case ARM::VLD3DUPdWB_fixed_Asm_16:
7411 case ARM::VLD3DUPdWB_fixed_Asm_32:
7412 case ARM::VLD3DUPqWB_fixed_Asm_8:
7413 case ARM::VLD3DUPqWB_fixed_Asm_16:
7414 case ARM::VLD3DUPqWB_fixed_Asm_32: {
7417 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7418 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7419 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7421 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7423 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7424 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7425 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7426 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7427 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7428 TmpInst.addOperand(Inst.getOperand(4));
7433 case ARM::VLD3DUPdWB_register_Asm_8:
7434 case ARM::VLD3DUPdWB_register_Asm_16:
7435 case ARM::VLD3DUPdWB_register_Asm_32:
7436 case ARM::VLD3DUPqWB_register_Asm_8:
7437 case ARM::VLD3DUPqWB_register_Asm_16:
7438 case ARM::VLD3DUPqWB_register_Asm_32: {
7441 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7442 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7443 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7445 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7447 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7448 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7449 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7450 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7451 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7452 TmpInst.addOperand(Inst.getOperand(5));
7457 // VLD3 multiple 3-element structure instructions.
7458 case ARM::VLD3dAsm_8:
7459 case ARM::VLD3dAsm_16:
7460 case ARM::VLD3dAsm_32:
7461 case ARM::VLD3qAsm_8:
7462 case ARM::VLD3qAsm_16:
7463 case ARM::VLD3qAsm_32: {
7466 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7467 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7468 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7470 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7472 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7473 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7474 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7475 TmpInst.addOperand(Inst.getOperand(4));
7480 case ARM::VLD3dWB_fixed_Asm_8:
7481 case ARM::VLD3dWB_fixed_Asm_16:
7482 case ARM::VLD3dWB_fixed_Asm_32:
7483 case ARM::VLD3qWB_fixed_Asm_8:
7484 case ARM::VLD3qWB_fixed_Asm_16:
7485 case ARM::VLD3qWB_fixed_Asm_32: {
7488 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7489 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7490 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7492 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7494 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7495 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7496 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7497 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7498 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7499 TmpInst.addOperand(Inst.getOperand(4));
7504 case ARM::VLD3dWB_register_Asm_8:
7505 case ARM::VLD3dWB_register_Asm_16:
7506 case ARM::VLD3dWB_register_Asm_32:
7507 case ARM::VLD3qWB_register_Asm_8:
7508 case ARM::VLD3qWB_register_Asm_16:
7509 case ARM::VLD3qWB_register_Asm_32: {
7512 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7513 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7514 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7516 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7518 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7519 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7520 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7521 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7522 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7523 TmpInst.addOperand(Inst.getOperand(5));
7528 // VLD4DUP single 3-element structure to all lanes instructions.
7529 case ARM::VLD4DUPdAsm_8:
7530 case ARM::VLD4DUPdAsm_16:
7531 case ARM::VLD4DUPdAsm_32:
7532 case ARM::VLD4DUPqAsm_8:
7533 case ARM::VLD4DUPqAsm_16:
7534 case ARM::VLD4DUPqAsm_32: {
7537 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7538 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7539 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7541 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7543 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7545 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7546 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7547 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7548 TmpInst.addOperand(Inst.getOperand(4));
7553 case ARM::VLD4DUPdWB_fixed_Asm_8:
7554 case ARM::VLD4DUPdWB_fixed_Asm_16:
7555 case ARM::VLD4DUPdWB_fixed_Asm_32:
7556 case ARM::VLD4DUPqWB_fixed_Asm_8:
7557 case ARM::VLD4DUPqWB_fixed_Asm_16:
7558 case ARM::VLD4DUPqWB_fixed_Asm_32: {
7561 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7562 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7563 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7565 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7567 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7569 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7570 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7571 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7572 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7573 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7574 TmpInst.addOperand(Inst.getOperand(4));
7579 case ARM::VLD4DUPdWB_register_Asm_8:
7580 case ARM::VLD4DUPdWB_register_Asm_16:
7581 case ARM::VLD4DUPdWB_register_Asm_32:
7582 case ARM::VLD4DUPqWB_register_Asm_8:
7583 case ARM::VLD4DUPqWB_register_Asm_16:
7584 case ARM::VLD4DUPqWB_register_Asm_32: {
7587 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7588 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7589 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7591 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7593 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7595 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7596 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7597 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7598 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7599 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7600 TmpInst.addOperand(Inst.getOperand(5));
7605 // VLD4 multiple 4-element structure instructions.
7606 case ARM::VLD4dAsm_8:
7607 case ARM::VLD4dAsm_16:
7608 case ARM::VLD4dAsm_32:
7609 case ARM::VLD4qAsm_8:
7610 case ARM::VLD4qAsm_16:
7611 case ARM::VLD4qAsm_32: {
7614 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7615 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7616 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7618 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7620 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7622 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7623 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7624 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7625 TmpInst.addOperand(Inst.getOperand(4));
7630 case ARM::VLD4dWB_fixed_Asm_8:
7631 case ARM::VLD4dWB_fixed_Asm_16:
7632 case ARM::VLD4dWB_fixed_Asm_32:
7633 case ARM::VLD4qWB_fixed_Asm_8:
7634 case ARM::VLD4qWB_fixed_Asm_16:
7635 case ARM::VLD4qWB_fixed_Asm_32: {
7638 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7639 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7640 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7642 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7644 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7646 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7647 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7648 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7649 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7650 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7651 TmpInst.addOperand(Inst.getOperand(4));
7656 case ARM::VLD4dWB_register_Asm_8:
7657 case ARM::VLD4dWB_register_Asm_16:
7658 case ARM::VLD4dWB_register_Asm_32:
7659 case ARM::VLD4qWB_register_Asm_8:
7660 case ARM::VLD4qWB_register_Asm_16:
7661 case ARM::VLD4qWB_register_Asm_32: {
7664 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7665 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7666 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7668 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7670 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7672 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7673 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7674 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7675 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7676 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7677 TmpInst.addOperand(Inst.getOperand(5));
7682 // VST3 multiple 3-element structure instructions.
7683 case ARM::VST3dAsm_8:
7684 case ARM::VST3dAsm_16:
7685 case ARM::VST3dAsm_32:
7686 case ARM::VST3qAsm_8:
7687 case ARM::VST3qAsm_16:
7688 case ARM::VST3qAsm_32: {
7691 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7692 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7693 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7694 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7695 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7697 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7699 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7700 TmpInst.addOperand(Inst.getOperand(4));
7705 case ARM::VST3dWB_fixed_Asm_8:
7706 case ARM::VST3dWB_fixed_Asm_16:
7707 case ARM::VST3dWB_fixed_Asm_32:
7708 case ARM::VST3qWB_fixed_Asm_8:
7709 case ARM::VST3qWB_fixed_Asm_16:
7710 case ARM::VST3qWB_fixed_Asm_32: {
7713 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7714 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7715 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7716 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7717 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7718 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7719 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7721 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7723 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7724 TmpInst.addOperand(Inst.getOperand(4));
7729 case ARM::VST3dWB_register_Asm_8:
7730 case ARM::VST3dWB_register_Asm_16:
7731 case ARM::VST3dWB_register_Asm_32:
7732 case ARM::VST3qWB_register_Asm_8:
7733 case ARM::VST3qWB_register_Asm_16:
7734 case ARM::VST3qWB_register_Asm_32: {
7737 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7738 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7739 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7740 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7741 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7742 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7743 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7745 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7747 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7748 TmpInst.addOperand(Inst.getOperand(5));
7753 // VST4 multiple 3-element structure instructions.
7754 case ARM::VST4dAsm_8:
7755 case ARM::VST4dAsm_16:
7756 case ARM::VST4dAsm_32:
7757 case ARM::VST4qAsm_8:
7758 case ARM::VST4qAsm_16:
7759 case ARM::VST4qAsm_32: {
7762 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7763 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7764 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7765 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7766 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7768 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7770 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7772 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7773 TmpInst.addOperand(Inst.getOperand(4));
7778 case ARM::VST4dWB_fixed_Asm_8:
7779 case ARM::VST4dWB_fixed_Asm_16:
7780 case ARM::VST4dWB_fixed_Asm_32:
7781 case ARM::VST4qWB_fixed_Asm_8:
7782 case ARM::VST4qWB_fixed_Asm_16:
7783 case ARM::VST4qWB_fixed_Asm_32: {
7786 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7787 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7788 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7789 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7790 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7791 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7792 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7794 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7796 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7798 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7799 TmpInst.addOperand(Inst.getOperand(4));
7804 case ARM::VST4dWB_register_Asm_8:
7805 case ARM::VST4dWB_register_Asm_16:
7806 case ARM::VST4dWB_register_Asm_32:
7807 case ARM::VST4qWB_register_Asm_8:
7808 case ARM::VST4qWB_register_Asm_16:
7809 case ARM::VST4qWB_register_Asm_32: {
7812 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7813 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7814 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7815 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7816 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7817 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7818 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7820 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7822 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7824 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7825 TmpInst.addOperand(Inst.getOperand(5));
7830 // Handle encoding choice for the shift-immediate instructions.
7833 case ARM::t2ASRri: {
7834 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7835 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7836 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7837 !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7838 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
7840 switch (Inst.getOpcode()) {
7841 default: llvm_unreachable("unexpected opcode");
7842 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7843 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7844 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7846 // The Thumb1 operands aren't in the same order. Awesome, eh?
7848 TmpInst.setOpcode(NewOpc);
7849 TmpInst.addOperand(Inst.getOperand(0));
7850 TmpInst.addOperand(Inst.getOperand(5));
7851 TmpInst.addOperand(Inst.getOperand(1));
7852 TmpInst.addOperand(Inst.getOperand(2));
7853 TmpInst.addOperand(Inst.getOperand(3));
7854 TmpInst.addOperand(Inst.getOperand(4));
7861 // Handle the Thumb2 mode MOV complex aliases.
7863 case ARM::t2MOVSsr: {
7864 // Which instruction to expand to depends on the CCOut operand and
7865 // whether we're in an IT block if the register operands are low
7867 bool isNarrow = false;
7868 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7869 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7870 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7871 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7872 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7876 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7877 default: llvm_unreachable("unexpected opcode!");
7878 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7879 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7880 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7881 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7883 TmpInst.setOpcode(newOpc);
7884 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7886 TmpInst.addOperand(MCOperand::createReg(
7887 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7888 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7889 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7890 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7891 TmpInst.addOperand(Inst.getOperand(5));
7893 TmpInst.addOperand(MCOperand::createReg(
7894 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7899 case ARM::t2MOVSsi: {
7900 // Which instruction to expand to depends on the CCOut operand and
7901 // whether we're in an IT block if the register operands are low
7903 bool isNarrow = false;
7904 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7905 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7906 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7910 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7911 default: llvm_unreachable("unexpected opcode!");
7912 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7913 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7914 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7915 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7916 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7918 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7919 if (Amount == 32) Amount = 0;
7920 TmpInst.setOpcode(newOpc);
7921 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7923 TmpInst.addOperand(MCOperand::createReg(
7924 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7925 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7926 if (newOpc != ARM::t2RRX)
7927 TmpInst.addOperand(MCOperand::createImm(Amount));
7928 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7929 TmpInst.addOperand(Inst.getOperand(4));
7931 TmpInst.addOperand(MCOperand::createReg(
7932 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7936 // Handle the ARM mode MOV complex aliases.
7941 ARM_AM::ShiftOpc ShiftTy;
7942 switch(Inst.getOpcode()) {
7943 default: llvm_unreachable("unexpected opcode!");
7944 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7945 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7946 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7947 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7949 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7951 TmpInst.setOpcode(ARM::MOVsr);
7952 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7953 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7954 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7955 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
7956 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7957 TmpInst.addOperand(Inst.getOperand(4));
7958 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7966 ARM_AM::ShiftOpc ShiftTy;
7967 switch(Inst.getOpcode()) {
7968 default: llvm_unreachable("unexpected opcode!");
7969 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7970 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7971 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7972 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7974 // A shift by zero is a plain MOVr, not a MOVsi.
7975 unsigned Amt = Inst.getOperand(2).getImm();
7976 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7977 // A shift by 32 should be encoded as 0 when permitted
7978 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7980 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7982 TmpInst.setOpcode(Opc);
7983 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7984 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7985 if (Opc == ARM::MOVsi)
7986 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
7987 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7988 TmpInst.addOperand(Inst.getOperand(4));
7989 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7994 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7996 TmpInst.setOpcode(ARM::MOVsi);
7997 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7998 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7999 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8000 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8001 TmpInst.addOperand(Inst.getOperand(3));
8002 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
8006 case ARM::t2LDMIA_UPD: {
8007 // If this is a load of a single register, then we should use
8008 // a post-indexed LDR instruction instead, per the ARM ARM.
8009 if (Inst.getNumOperands() != 5)
8012 TmpInst.setOpcode(ARM::t2LDR_POST);
8013 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8014 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8015 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8016 TmpInst.addOperand(MCOperand::createImm(4));
8017 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8018 TmpInst.addOperand(Inst.getOperand(3));
8022 case ARM::t2STMDB_UPD: {
8023 // If this is a store of a single register, then we should use
8024 // a pre-indexed STR instruction instead, per the ARM ARM.
8025 if (Inst.getNumOperands() != 5)
8028 TmpInst.setOpcode(ARM::t2STR_PRE);
8029 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8030 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8031 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8032 TmpInst.addOperand(MCOperand::createImm(-4));
8033 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8034 TmpInst.addOperand(Inst.getOperand(3));
8038 case ARM::LDMIA_UPD:
8039 // If this is a load of a single register via a 'pop', then we should use
8040 // a post-indexed LDR instruction instead, per the ARM ARM.
8041 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
8042 Inst.getNumOperands() == 5) {
8044 TmpInst.setOpcode(ARM::LDR_POST_IMM);
8045 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8046 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8047 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8048 TmpInst.addOperand(MCOperand::createReg(0)); // am2offset
8049 TmpInst.addOperand(MCOperand::createImm(4));
8050 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8051 TmpInst.addOperand(Inst.getOperand(3));
8056 case ARM::STMDB_UPD:
8057 // If this is a store of a single register via a 'push', then we should use
8058 // a pre-indexed STR instruction instead, per the ARM ARM.
8059 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
8060 Inst.getNumOperands() == 5) {
8062 TmpInst.setOpcode(ARM::STR_PRE_IMM);
8063 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8064 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8065 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
8066 TmpInst.addOperand(MCOperand::createImm(-4));
8067 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8068 TmpInst.addOperand(Inst.getOperand(3));
8072 case ARM::t2ADDri12:
8073 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
8074 // mnemonic was used (not "addw"), encoding T3 is preferred.
8075 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
8076 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8078 Inst.setOpcode(ARM::t2ADDri);
8079 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8081 case ARM::t2SUBri12:
8082 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
8083 // mnemonic was used (not "subw"), encoding T3 is preferred.
8084 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
8085 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8087 Inst.setOpcode(ARM::t2SUBri);
8088 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8091 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8092 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8093 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8094 // to encoding T1 if <Rd> is omitted."
8095 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8096 Inst.setOpcode(ARM::tADDi3);
8101 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8102 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8103 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8104 // to encoding T1 if <Rd> is omitted."
8105 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8106 Inst.setOpcode(ARM::tSUBi3);
8111 case ARM::t2SUBri: {
8112 // If the destination and first source operand are the same, and
8113 // the flags are compatible with the current IT status, use encoding T2
8114 // instead of T3. For compatibility with the system 'as'. Make sure the
8115 // wide encoding wasn't explicit.
8116 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8117 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
8118 (unsigned)Inst.getOperand(2).getImm() > 255 ||
8119 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
8120 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
8121 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8122 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8125 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
8126 ARM::tADDi8 : ARM::tSUBi8);
8127 TmpInst.addOperand(Inst.getOperand(0));
8128 TmpInst.addOperand(Inst.getOperand(5));
8129 TmpInst.addOperand(Inst.getOperand(0));
8130 TmpInst.addOperand(Inst.getOperand(2));
8131 TmpInst.addOperand(Inst.getOperand(3));
8132 TmpInst.addOperand(Inst.getOperand(4));
8136 case ARM::t2ADDrr: {
8137 // If the destination and first source operand are the same, and
8138 // there's no setting of the flags, use encoding T2 instead of T3.
8139 // Note that this is only for ADD, not SUB. This mirrors the system
8140 // 'as' behaviour. Also take advantage of ADD being commutative.
8141 // Make sure the wide encoding wasn't explicit.
8143 auto DestReg = Inst.getOperand(0).getReg();
8144 bool Transform = DestReg == Inst.getOperand(1).getReg();
8145 if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
8150 Inst.getOperand(5).getReg() != 0 ||
8151 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8152 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8155 TmpInst.setOpcode(ARM::tADDhirr);
8156 TmpInst.addOperand(Inst.getOperand(0));
8157 TmpInst.addOperand(Inst.getOperand(0));
8158 TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
8159 TmpInst.addOperand(Inst.getOperand(3));
8160 TmpInst.addOperand(Inst.getOperand(4));
8164 case ARM::tADDrSP: {
8165 // If the non-SP source operand and the destination operand are not the
8166 // same, we need to use the 32-bit encoding if it's available.
8167 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8168 Inst.setOpcode(ARM::t2ADDrr);
8169 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8175 // A Thumb conditional branch outside of an IT block is a tBcc.
8176 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
8177 Inst.setOpcode(ARM::tBcc);
8182 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
8183 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
8184 Inst.setOpcode(ARM::t2Bcc);
8189 // If the conditional is AL or we're in an IT block, we really want t2B.
8190 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
8191 Inst.setOpcode(ARM::t2B);
8196 // If the conditional is AL, we really want tB.
8197 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
8198 Inst.setOpcode(ARM::tB);
8203 // If the register list contains any high registers, or if the writeback
8204 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
8205 // instead if we're in Thumb2. Otherwise, this should have generated
8206 // an error in validateInstruction().
8207 unsigned Rn = Inst.getOperand(0).getReg();
8208 bool hasWritebackToken =
8209 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8210 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
8211 bool listContainsBase;
8212 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
8213 (!listContainsBase && !hasWritebackToken) ||
8214 (listContainsBase && hasWritebackToken)) {
8215 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8216 assert (isThumbTwo());
8217 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
8218 // If we're switching to the updating version, we need to insert
8219 // the writeback tied operand.
8220 if (hasWritebackToken)
8221 Inst.insert(Inst.begin(),
8222 MCOperand::createReg(Inst.getOperand(0).getReg()));
8227 case ARM::tSTMIA_UPD: {
8228 // If the register list contains any high registers, we need to use
8229 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8230 // should have generated an error in validateInstruction().
8231 unsigned Rn = Inst.getOperand(0).getReg();
8232 bool listContainsBase;
8233 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
8234 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8235 assert (isThumbTwo());
8236 Inst.setOpcode(ARM::t2STMIA_UPD);
8242 bool listContainsBase;
8243 // If the register list contains any high registers, we need to use
8244 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8245 // should have generated an error in validateInstruction().
8246 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
8248 assert (isThumbTwo());
8249 Inst.setOpcode(ARM::t2LDMIA_UPD);
8250 // Add the base register and writeback operands.
8251 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8252 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8256 bool listContainsBase;
8257 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
8259 assert (isThumbTwo());
8260 Inst.setOpcode(ARM::t2STMDB_UPD);
8261 // Add the base register and writeback operands.
8262 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8263 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8267 // If we can use the 16-bit encoding and the user didn't explicitly
8268 // request the 32-bit variant, transform it here.
8269 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8270 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
8271 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
8272 Inst.getOperand(4).getReg() == ARM::CPSR) ||
8273 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
8274 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8275 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8276 // The operands aren't in the same order for tMOVi8...
8278 TmpInst.setOpcode(ARM::tMOVi8);
8279 TmpInst.addOperand(Inst.getOperand(0));
8280 TmpInst.addOperand(Inst.getOperand(4));
8281 TmpInst.addOperand(Inst.getOperand(1));
8282 TmpInst.addOperand(Inst.getOperand(2));
8283 TmpInst.addOperand(Inst.getOperand(3));
8290 // If we can use the 16-bit encoding and the user didn't explicitly
8291 // request the 32-bit variant, transform it here.
8292 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8293 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8294 Inst.getOperand(2).getImm() == ARMCC::AL &&
8295 Inst.getOperand(4).getReg() == ARM::CPSR &&
8296 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8297 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8298 // The operands aren't the same for tMOV[S]r... (no cc_out)
8300 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
8301 TmpInst.addOperand(Inst.getOperand(0));
8302 TmpInst.addOperand(Inst.getOperand(1));
8303 TmpInst.addOperand(Inst.getOperand(2));
8304 TmpInst.addOperand(Inst.getOperand(3));
8314 // If we can use the 16-bit encoding and the user didn't explicitly
8315 // request the 32-bit variant, transform it here.
8316 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8317 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8318 Inst.getOperand(2).getImm() == 0 &&
8319 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8320 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8322 switch (Inst.getOpcode()) {
8323 default: llvm_unreachable("Illegal opcode!");
8324 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8325 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8326 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8327 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
8329 // The operands aren't the same for thumb1 (no rotate operand).
8331 TmpInst.setOpcode(NewOpc);
8332 TmpInst.addOperand(Inst.getOperand(0));
8333 TmpInst.addOperand(Inst.getOperand(1));
8334 TmpInst.addOperand(Inst.getOperand(3));
8335 TmpInst.addOperand(Inst.getOperand(4));
8342 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8343 // rrx shifts and asr/lsr of #32 is encoded as 0
8344 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
8346 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8347 // Shifting by zero is accepted as a vanilla 'MOVr'
8349 TmpInst.setOpcode(ARM::MOVr);
8350 TmpInst.addOperand(Inst.getOperand(0));
8351 TmpInst.addOperand(Inst.getOperand(1));
8352 TmpInst.addOperand(Inst.getOperand(3));
8353 TmpInst.addOperand(Inst.getOperand(4));
8354 TmpInst.addOperand(Inst.getOperand(5));
8367 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8368 if (SOpc == ARM_AM::rrx) return false;
8369 switch (Inst.getOpcode()) {
8370 default: llvm_unreachable("unexpected opcode!");
8371 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
8372 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
8373 case ARM::EORrsi: newOpc = ARM::EORrr; break;
8374 case ARM::BICrsi: newOpc = ARM::BICrr; break;
8375 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
8376 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
8378 // If the shift is by zero, use the non-shifted instruction definition.
8379 // The exception is for right shifts, where 0 == 32
8380 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8381 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
8383 TmpInst.setOpcode(newOpc);
8384 TmpInst.addOperand(Inst.getOperand(0));
8385 TmpInst.addOperand(Inst.getOperand(1));
8386 TmpInst.addOperand(Inst.getOperand(2));
8387 TmpInst.addOperand(Inst.getOperand(4));
8388 TmpInst.addOperand(Inst.getOperand(5));
8389 TmpInst.addOperand(Inst.getOperand(6));
8397 // The mask bits for all but the first condition are represented as
8398 // the low bit of the condition code value implies 't'. We currently
8399 // always have 1 implies 't', so XOR toggle the bits if the low bit
8400 // of the condition code is zero.
8401 MCOperand &MO = Inst.getOperand(1);
8402 unsigned Mask = MO.getImm();
8403 unsigned OrigMask = Mask;
8404 unsigned TZ = countTrailingZeros(Mask);
8405 if ((Inst.getOperand(0).getImm() & 1) == 0) {
8406 assert(Mask && TZ <= 3 && "illegal IT mask value!");
8407 Mask ^= (0xE << TZ) & 0xF;
8411 // Set up the IT block state according to the IT instruction we just
8413 assert(!inITBlock() && "nested IT blocks?!");
8414 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8415 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
8416 ITState.CurPosition = 0;
8417 ITState.FirstCond = true;
8427 // Assemblers should use the narrow encodings of these instructions when permissible.
8428 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8429 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8430 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8431 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8432 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8433 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8434 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8437 switch (Inst.getOpcode()) {
8438 default: llvm_unreachable("unexpected opcode");
8439 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8440 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8441 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8442 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8443 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8444 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8447 TmpInst.setOpcode(NewOpc);
8448 TmpInst.addOperand(Inst.getOperand(0));
8449 TmpInst.addOperand(Inst.getOperand(5));
8450 TmpInst.addOperand(Inst.getOperand(1));
8451 TmpInst.addOperand(Inst.getOperand(2));
8452 TmpInst.addOperand(Inst.getOperand(3));
8453 TmpInst.addOperand(Inst.getOperand(4));
8464 // Assemblers should use the narrow encodings of these instructions when permissible.
8465 // These instructions are special in that they are commutable, so shorter encodings
8466 // are available more often.
8467 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8468 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8469 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8470 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8471 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8472 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8473 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8474 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8477 switch (Inst.getOpcode()) {
8478 default: llvm_unreachable("unexpected opcode");
8479 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8480 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8481 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8482 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8485 TmpInst.setOpcode(NewOpc);
8486 TmpInst.addOperand(Inst.getOperand(0));
8487 TmpInst.addOperand(Inst.getOperand(5));
8488 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8489 TmpInst.addOperand(Inst.getOperand(1));
8490 TmpInst.addOperand(Inst.getOperand(2));
8492 TmpInst.addOperand(Inst.getOperand(2));
8493 TmpInst.addOperand(Inst.getOperand(1));
8495 TmpInst.addOperand(Inst.getOperand(3));
8496 TmpInst.addOperand(Inst.getOperand(4));
8506 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8507 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8508 // suffix depending on whether they're in an IT block or not.
8509 unsigned Opc = Inst.getOpcode();
8510 const MCInstrDesc &MCID = MII.get(Opc);
8511 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8512 assert(MCID.hasOptionalDef() &&
8513 "optionally flag setting instruction missing optional def operand");
8514 assert(MCID.NumOperands == Inst.getNumOperands() &&
8515 "operand count mismatch!");
8516 // Find the optional-def operand (cc_out).
8519 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8522 // If we're parsing Thumb1, reject it completely.
8523 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8524 return Match_MnemonicFail;
8525 // If we're parsing Thumb2, which form is legal depends on whether we're
8527 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8529 return Match_RequiresITBlock;
8530 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8532 return Match_RequiresNotITBlock;
8533 } else if (isThumbOne()) {
8534 // Some high-register supporting Thumb1 encodings only allow both registers
8535 // to be from r0-r7 when in Thumb2.
8536 if (Opc == ARM::tADDhirr && !hasV6MOps() &&
8537 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8538 isARMLowRegister(Inst.getOperand(2).getReg()))
8539 return Match_RequiresThumb2;
8540 // Others only require ARMv6 or later.
8541 else if (Opc == ARM::tMOVr && !hasV6Ops() &&
8542 isARMLowRegister(Inst.getOperand(0).getReg()) &&
8543 isARMLowRegister(Inst.getOperand(1).getReg()))
8544 return Match_RequiresV6;
8547 for (unsigned I = 0; I < MCID.NumOperands; ++I)
8548 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
8549 // rGPRRegClass excludes PC, and also excluded SP before ARMv8
8550 if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())
8551 return Match_RequiresV8;
8552 else if (Inst.getOperand(I).getReg() == ARM::PC)
8553 return Match_InvalidOperand;
8556 return Match_Success;
8560 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8561 return true; // In an assembly source, no need to second-guess
8565 static const char *getSubtargetFeatureName(uint64_t Val);
8566 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8567 OperandVector &Operands,
8568 MCStreamer &Out, uint64_t &ErrorInfo,
8569 bool MatchingInlineAsm) {
8571 unsigned MatchResult;
8573 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8575 switch (MatchResult) {
8577 // Context sensitive operand constraints aren't handled by the matcher,
8578 // so check them here.
8579 if (validateInstruction(Inst, Operands)) {
8580 // Still progress the IT block, otherwise one wrong condition causes
8581 // nasty cascading errors.
8582 forwardITPosition();
8586 { // processInstruction() updates inITBlock state, we need to save it away
8587 bool wasInITBlock = inITBlock();
8589 // Some instructions need post-processing to, for example, tweak which
8590 // encoding is selected. Loop on it while changes happen so the
8591 // individual transformations can chain off each other. E.g.,
8592 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8593 while (processInstruction(Inst, Operands, Out))
8596 // Only after the instruction is fully processed, we can validate it
8597 if (wasInITBlock && hasV8Ops() && isThumb() &&
8598 !isV8EligibleForIT(&Inst)) {
8599 Warning(IDLoc, "deprecated instruction in IT block");
8603 // Only move forward at the very end so that everything in validate
8604 // and process gets a consistent answer about whether we're in an IT
8606 forwardITPosition();
8608 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8609 // doesn't actually encode.
8610 if (Inst.getOpcode() == ARM::ITasm)
8614 Out.EmitInstruction(Inst, STI);
8616 case Match_MissingFeature: {
8617 assert(ErrorInfo && "Unknown missing feature!");
8618 // Special case the error message for the very common case where only
8619 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8620 std::string Msg = "instruction requires:";
8622 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8623 if (ErrorInfo & Mask) {
8625 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8629 return Error(IDLoc, Msg);
8631 case Match_InvalidOperand: {
8632 SMLoc ErrorLoc = IDLoc;
8633 if (ErrorInfo != ~0ULL) {
8634 if (ErrorInfo >= Operands.size())
8635 return Error(IDLoc, "too few operands for instruction");
8637 ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8638 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8641 return Error(ErrorLoc, "invalid operand for instruction");
8643 case Match_MnemonicFail:
8644 return Error(IDLoc, "invalid instruction",
8645 ((ARMOperand &)*Operands[0]).getLocRange());
8646 case Match_RequiresNotITBlock:
8647 return Error(IDLoc, "flag setting instruction only valid outside IT block");
8648 case Match_RequiresITBlock:
8649 return Error(IDLoc, "instruction only valid inside IT block");
8650 case Match_RequiresV6:
8651 return Error(IDLoc, "instruction variant requires ARMv6 or later");
8652 case Match_RequiresThumb2:
8653 return Error(IDLoc, "instruction variant requires Thumb2");
8654 case Match_RequiresV8:
8655 return Error(IDLoc, "instruction variant requires ARMv8 or later");
8656 case Match_ImmRange0_15: {
8657 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8658 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8659 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8661 case Match_ImmRange0_239: {
8662 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8663 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8664 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8666 case Match_AlignedMemoryRequiresNone:
8667 case Match_DupAlignedMemoryRequiresNone:
8668 case Match_AlignedMemoryRequires16:
8669 case Match_DupAlignedMemoryRequires16:
8670 case Match_AlignedMemoryRequires32:
8671 case Match_DupAlignedMemoryRequires32:
8672 case Match_AlignedMemoryRequires64:
8673 case Match_DupAlignedMemoryRequires64:
8674 case Match_AlignedMemoryRequires64or128:
8675 case Match_DupAlignedMemoryRequires64or128:
8676 case Match_AlignedMemoryRequires64or128or256:
8678 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
8679 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8680 switch (MatchResult) {
8682 llvm_unreachable("Missing Match_Aligned type");
8683 case Match_AlignedMemoryRequiresNone:
8684 case Match_DupAlignedMemoryRequiresNone:
8685 return Error(ErrorLoc, "alignment must be omitted");
8686 case Match_AlignedMemoryRequires16:
8687 case Match_DupAlignedMemoryRequires16:
8688 return Error(ErrorLoc, "alignment must be 16 or omitted");
8689 case Match_AlignedMemoryRequires32:
8690 case Match_DupAlignedMemoryRequires32:
8691 return Error(ErrorLoc, "alignment must be 32 or omitted");
8692 case Match_AlignedMemoryRequires64:
8693 case Match_DupAlignedMemoryRequires64:
8694 return Error(ErrorLoc, "alignment must be 64 or omitted");
8695 case Match_AlignedMemoryRequires64or128:
8696 case Match_DupAlignedMemoryRequires64or128:
8697 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8698 case Match_AlignedMemoryRequires64or128or256:
8699 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8704 llvm_unreachable("Implement any new match types added!");
8707 /// parseDirective parses the arm specific directives
8708 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8709 const MCObjectFileInfo::Environment Format =
8710 getContext().getObjectFileInfo()->getObjectFileType();
8711 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8712 bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
8714 StringRef IDVal = DirectiveID.getIdentifier();
8715 if (IDVal == ".word")
8716 return parseLiteralValues(4, DirectiveID.getLoc());
8717 else if (IDVal == ".short" || IDVal == ".hword")
8718 return parseLiteralValues(2, DirectiveID.getLoc());
8719 else if (IDVal == ".thumb")
8720 return parseDirectiveThumb(DirectiveID.getLoc());
8721 else if (IDVal == ".arm")
8722 return parseDirectiveARM(DirectiveID.getLoc());
8723 else if (IDVal == ".thumb_func")
8724 return parseDirectiveThumbFunc(DirectiveID.getLoc());
8725 else if (IDVal == ".code")
8726 return parseDirectiveCode(DirectiveID.getLoc());
8727 else if (IDVal == ".syntax")
8728 return parseDirectiveSyntax(DirectiveID.getLoc());
8729 else if (IDVal == ".unreq")
8730 return parseDirectiveUnreq(DirectiveID.getLoc());
8731 else if (IDVal == ".fnend")
8732 return parseDirectiveFnEnd(DirectiveID.getLoc());
8733 else if (IDVal == ".cantunwind")
8734 return parseDirectiveCantUnwind(DirectiveID.getLoc());
8735 else if (IDVal == ".personality")
8736 return parseDirectivePersonality(DirectiveID.getLoc());
8737 else if (IDVal == ".handlerdata")
8738 return parseDirectiveHandlerData(DirectiveID.getLoc());
8739 else if (IDVal == ".setfp")
8740 return parseDirectiveSetFP(DirectiveID.getLoc());
8741 else if (IDVal == ".pad")
8742 return parseDirectivePad(DirectiveID.getLoc());
8743 else if (IDVal == ".save")
8744 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8745 else if (IDVal == ".vsave")
8746 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8747 else if (IDVal == ".ltorg" || IDVal == ".pool")
8748 return parseDirectiveLtorg(DirectiveID.getLoc());
8749 else if (IDVal == ".even")
8750 return parseDirectiveEven(DirectiveID.getLoc());
8751 else if (IDVal == ".personalityindex")
8752 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8753 else if (IDVal == ".unwind_raw")
8754 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8755 else if (IDVal == ".movsp")
8756 return parseDirectiveMovSP(DirectiveID.getLoc());
8757 else if (IDVal == ".arch_extension")
8758 return parseDirectiveArchExtension(DirectiveID.getLoc());
8759 else if (IDVal == ".align")
8760 return parseDirectiveAlign(DirectiveID.getLoc());
8761 else if (IDVal == ".thumb_set")
8762 return parseDirectiveThumbSet(DirectiveID.getLoc());
8764 if (!IsMachO && !IsCOFF) {
8765 if (IDVal == ".arch")
8766 return parseDirectiveArch(DirectiveID.getLoc());
8767 else if (IDVal == ".cpu")
8768 return parseDirectiveCPU(DirectiveID.getLoc());
8769 else if (IDVal == ".eabi_attribute")
8770 return parseDirectiveEabiAttr(DirectiveID.getLoc());
8771 else if (IDVal == ".fpu")
8772 return parseDirectiveFPU(DirectiveID.getLoc());
8773 else if (IDVal == ".fnstart")
8774 return parseDirectiveFnStart(DirectiveID.getLoc());
8775 else if (IDVal == ".inst")
8776 return parseDirectiveInst(DirectiveID.getLoc());
8777 else if (IDVal == ".inst.n")
8778 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8779 else if (IDVal == ".inst.w")
8780 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8781 else if (IDVal == ".object_arch")
8782 return parseDirectiveObjectArch(DirectiveID.getLoc());
8783 else if (IDVal == ".tlsdescseq")
8784 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8790 /// parseLiteralValues
8791 /// ::= .hword expression [, expression]*
8792 /// ::= .short expression [, expression]*
8793 /// ::= .word expression [, expression]*
8794 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8795 MCAsmParser &Parser = getParser();
8796 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8798 const MCExpr *Value;
8799 if (getParser().parseExpression(Value)) {
8800 Parser.eatToEndOfStatement();
8804 getParser().getStreamer().EmitValue(Value, Size);
8806 if (getLexer().is(AsmToken::EndOfStatement))
8809 // FIXME: Improve diagnostic.
8810 if (getLexer().isNot(AsmToken::Comma)) {
8811 Error(L, "unexpected token in directive");
8822 /// parseDirectiveThumb
8824 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8825 MCAsmParser &Parser = getParser();
8826 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8827 Error(L, "unexpected token in directive");
8833 Error(L, "target does not support Thumb mode");
8840 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8844 /// parseDirectiveARM
8846 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8847 MCAsmParser &Parser = getParser();
8848 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8849 Error(L, "unexpected token in directive");
8855 Error(L, "target does not support ARM mode");
8862 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8866 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8867 if (NextSymbolIsThumb) {
8868 getParser().getStreamer().EmitThumbFunc(Symbol);
8869 NextSymbolIsThumb = false;
8873 /// parseDirectiveThumbFunc
8874 /// ::= .thumbfunc symbol_name
8875 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8876 MCAsmParser &Parser = getParser();
8877 const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
8878 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8880 // Darwin asm has (optionally) function name after .thumb_func direction
8883 const AsmToken &Tok = Parser.getTok();
8884 if (Tok.isNot(AsmToken::EndOfStatement)) {
8885 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8886 Error(L, "unexpected token in .thumb_func directive");
8891 getParser().getContext().getOrCreateSymbol(Tok.getIdentifier());
8892 getParser().getStreamer().EmitThumbFunc(Func);
8893 Parser.Lex(); // Consume the identifier token.
8898 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8899 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8900 Parser.eatToEndOfStatement();
8904 NextSymbolIsThumb = true;
8908 /// parseDirectiveSyntax
8909 /// ::= .syntax unified | divided
8910 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8911 MCAsmParser &Parser = getParser();
8912 const AsmToken &Tok = Parser.getTok();
8913 if (Tok.isNot(AsmToken::Identifier)) {
8914 Error(L, "unexpected token in .syntax directive");
8918 StringRef Mode = Tok.getString();
8919 if (Mode == "unified" || Mode == "UNIFIED") {
8921 } else if (Mode == "divided" || Mode == "DIVIDED") {
8922 Error(L, "'.syntax divided' arm asssembly not supported");
8925 Error(L, "unrecognized syntax mode in .syntax directive");
8929 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8930 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8935 // TODO tell the MC streamer the mode
8936 // getParser().getStreamer().Emit???();
8940 /// parseDirectiveCode
8941 /// ::= .code 16 | 32
8942 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8943 MCAsmParser &Parser = getParser();
8944 const AsmToken &Tok = Parser.getTok();
8945 if (Tok.isNot(AsmToken::Integer)) {
8946 Error(L, "unexpected token in .code directive");
8949 int64_t Val = Parser.getTok().getIntVal();
8950 if (Val != 16 && Val != 32) {
8951 Error(L, "invalid operand to .code directive");
8956 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8957 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8964 Error(L, "target does not support Thumb mode");
8970 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8973 Error(L, "target does not support ARM mode");
8979 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8985 /// parseDirectiveReq
8986 /// ::= name .req registername
8987 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8988 MCAsmParser &Parser = getParser();
8989 Parser.Lex(); // Eat the '.req' token.
8991 SMLoc SRegLoc, ERegLoc;
8992 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8993 Parser.eatToEndOfStatement();
8994 Error(SRegLoc, "register name expected");
8998 // Shouldn't be anything else.
8999 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
9000 Parser.eatToEndOfStatement();
9001 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
9005 Parser.Lex(); // Consume the EndOfStatement
9007 if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg) {
9008 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
9015 /// parseDirectiveUneq
9016 /// ::= .unreq registername
9017 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
9018 MCAsmParser &Parser = getParser();
9019 if (Parser.getTok().isNot(AsmToken::Identifier)) {
9020 Parser.eatToEndOfStatement();
9021 Error(L, "unexpected input in .unreq directive.");
9024 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
9025 Parser.Lex(); // Eat the identifier.
9029 /// parseDirectiveArch
9031 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
9032 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
9034 unsigned ID = ARM::parseArch(Arch);
9036 if (ID == ARM::AK_INVALID) {
9037 Error(L, "Unknown arch name");
9042 STI.setDefaultFeatures(T.getARMCPUForArch(Arch));
9043 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9045 getTargetStreamer().emitArch(ID);
9049 /// parseDirectiveEabiAttr
9050 /// ::= .eabi_attribute int, int [, "str"]
9051 /// ::= .eabi_attribute Tag_name, int [, "str"]
9052 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
9053 MCAsmParser &Parser = getParser();
9056 TagLoc = Parser.getTok().getLoc();
9057 if (Parser.getTok().is(AsmToken::Identifier)) {
9058 StringRef Name = Parser.getTok().getIdentifier();
9059 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
9061 Error(TagLoc, "attribute name not recognised: " + Name);
9062 Parser.eatToEndOfStatement();
9067 const MCExpr *AttrExpr;
9069 TagLoc = Parser.getTok().getLoc();
9070 if (Parser.parseExpression(AttrExpr)) {
9071 Parser.eatToEndOfStatement();
9075 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
9077 Error(TagLoc, "expected numeric constant");
9078 Parser.eatToEndOfStatement();
9082 Tag = CE->getValue();
9085 if (Parser.getTok().isNot(AsmToken::Comma)) {
9086 Error(Parser.getTok().getLoc(), "comma expected");
9087 Parser.eatToEndOfStatement();
9090 Parser.Lex(); // skip comma
9092 StringRef StringValue = "";
9093 bool IsStringValue = false;
9095 int64_t IntegerValue = 0;
9096 bool IsIntegerValue = false;
9098 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
9099 IsStringValue = true;
9100 else if (Tag == ARMBuildAttrs::compatibility) {
9101 IsStringValue = true;
9102 IsIntegerValue = true;
9103 } else if (Tag < 32 || Tag % 2 == 0)
9104 IsIntegerValue = true;
9105 else if (Tag % 2 == 1)
9106 IsStringValue = true;
9108 llvm_unreachable("invalid tag type");
9110 if (IsIntegerValue) {
9111 const MCExpr *ValueExpr;
9112 SMLoc ValueExprLoc = Parser.getTok().getLoc();
9113 if (Parser.parseExpression(ValueExpr)) {
9114 Parser.eatToEndOfStatement();
9118 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
9120 Error(ValueExprLoc, "expected numeric constant");
9121 Parser.eatToEndOfStatement();
9125 IntegerValue = CE->getValue();
9128 if (Tag == ARMBuildAttrs::compatibility) {
9129 if (Parser.getTok().isNot(AsmToken::Comma))
9130 IsStringValue = false;
9131 if (Parser.getTok().isNot(AsmToken::Comma)) {
9132 Error(Parser.getTok().getLoc(), "comma expected");
9133 Parser.eatToEndOfStatement();
9140 if (IsStringValue) {
9141 if (Parser.getTok().isNot(AsmToken::String)) {
9142 Error(Parser.getTok().getLoc(), "bad string constant");
9143 Parser.eatToEndOfStatement();
9147 StringValue = Parser.getTok().getStringContents();
9151 if (IsIntegerValue && IsStringValue) {
9152 assert(Tag == ARMBuildAttrs::compatibility);
9153 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
9154 } else if (IsIntegerValue)
9155 getTargetStreamer().emitAttribute(Tag, IntegerValue);
9156 else if (IsStringValue)
9157 getTargetStreamer().emitTextAttribute(Tag, StringValue);
9161 /// parseDirectiveCPU
9163 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
9164 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
9165 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
9167 // FIXME: This is using table-gen data, but should be moved to
9168 // ARMTargetParser once that is table-gen'd.
9169 if (!STI.isCPUStringValid(CPU)) {
9170 Error(L, "Unknown CPU name");
9174 STI.setDefaultFeatures(CPU);
9175 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9179 /// parseDirectiveFPU
9181 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
9182 SMLoc FPUNameLoc = getTok().getLoc();
9183 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
9185 unsigned ID = ARM::parseFPU(FPU);
9186 std::vector<const char *> Features;
9187 if (!ARM::getFPUFeatures(ID, Features)) {
9188 Error(FPUNameLoc, "Unknown FPU name");
9192 for (auto Feature : Features)
9193 STI.ApplyFeatureFlag(Feature);
9194 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9196 getTargetStreamer().emitFPU(ID);
9200 /// parseDirectiveFnStart
9202 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
9203 if (UC.hasFnStart()) {
9204 Error(L, ".fnstart starts before the end of previous one");
9205 UC.emitFnStartLocNotes();
9209 // Reset the unwind directives parser state
9212 getTargetStreamer().emitFnStart();
9214 UC.recordFnStart(L);
9218 /// parseDirectiveFnEnd
9220 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
9221 // Check the ordering of unwind directives
9222 if (!UC.hasFnStart()) {
9223 Error(L, ".fnstart must precede .fnend directive");
9227 // Reset the unwind directives parser state
9228 getTargetStreamer().emitFnEnd();
9234 /// parseDirectiveCantUnwind
9236 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
9237 UC.recordCantUnwind(L);
9239 // Check the ordering of unwind directives
9240 if (!UC.hasFnStart()) {
9241 Error(L, ".fnstart must precede .cantunwind directive");
9244 if (UC.hasHandlerData()) {
9245 Error(L, ".cantunwind can't be used with .handlerdata directive");
9246 UC.emitHandlerDataLocNotes();
9249 if (UC.hasPersonality()) {
9250 Error(L, ".cantunwind can't be used with .personality directive");
9251 UC.emitPersonalityLocNotes();
9255 getTargetStreamer().emitCantUnwind();
9259 /// parseDirectivePersonality
9260 /// ::= .personality name
9261 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
9262 MCAsmParser &Parser = getParser();
9263 bool HasExistingPersonality = UC.hasPersonality();
9265 UC.recordPersonality(L);
9267 // Check the ordering of unwind directives
9268 if (!UC.hasFnStart()) {
9269 Error(L, ".fnstart must precede .personality directive");
9272 if (UC.cantUnwind()) {
9273 Error(L, ".personality can't be used with .cantunwind directive");
9274 UC.emitCantUnwindLocNotes();
9277 if (UC.hasHandlerData()) {
9278 Error(L, ".personality must precede .handlerdata directive");
9279 UC.emitHandlerDataLocNotes();
9282 if (HasExistingPersonality) {
9283 Parser.eatToEndOfStatement();
9284 Error(L, "multiple personality directives");
9285 UC.emitPersonalityLocNotes();
9289 // Parse the name of the personality routine
9290 if (Parser.getTok().isNot(AsmToken::Identifier)) {
9291 Parser.eatToEndOfStatement();
9292 Error(L, "unexpected input in .personality directive.");
9295 StringRef Name(Parser.getTok().getIdentifier());
9298 MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name);
9299 getTargetStreamer().emitPersonality(PR);
9303 /// parseDirectiveHandlerData
9304 /// ::= .handlerdata
9305 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
9306 UC.recordHandlerData(L);
9308 // Check the ordering of unwind directives
9309 if (!UC.hasFnStart()) {
9310 Error(L, ".fnstart must precede .personality directive");
9313 if (UC.cantUnwind()) {
9314 Error(L, ".handlerdata can't be used with .cantunwind directive");
9315 UC.emitCantUnwindLocNotes();
9319 getTargetStreamer().emitHandlerData();
9323 /// parseDirectiveSetFP
9324 /// ::= .setfp fpreg, spreg [, offset]
9325 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
9326 MCAsmParser &Parser = getParser();
9327 // Check the ordering of unwind directives
9328 if (!UC.hasFnStart()) {
9329 Error(L, ".fnstart must precede .setfp directive");
9332 if (UC.hasHandlerData()) {
9333 Error(L, ".setfp must precede .handlerdata directive");
9338 SMLoc FPRegLoc = Parser.getTok().getLoc();
9339 int FPReg = tryParseRegister();
9341 Error(FPRegLoc, "frame pointer register expected");
9346 if (Parser.getTok().isNot(AsmToken::Comma)) {
9347 Error(Parser.getTok().getLoc(), "comma expected");
9350 Parser.Lex(); // skip comma
9353 SMLoc SPRegLoc = Parser.getTok().getLoc();
9354 int SPReg = tryParseRegister();
9356 Error(SPRegLoc, "stack pointer register expected");
9360 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
9361 Error(SPRegLoc, "register should be either $sp or the latest fp register");
9365 // Update the frame pointer register
9366 UC.saveFPReg(FPReg);
9370 if (Parser.getTok().is(AsmToken::Comma)) {
9371 Parser.Lex(); // skip comma
9373 if (Parser.getTok().isNot(AsmToken::Hash) &&
9374 Parser.getTok().isNot(AsmToken::Dollar)) {
9375 Error(Parser.getTok().getLoc(), "'#' expected");
9378 Parser.Lex(); // skip hash token.
9380 const MCExpr *OffsetExpr;
9381 SMLoc ExLoc = Parser.getTok().getLoc();
9383 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9384 Error(ExLoc, "malformed setfp offset");
9387 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9389 Error(ExLoc, "setfp offset must be an immediate");
9393 Offset = CE->getValue();
9396 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9397 static_cast<unsigned>(SPReg), Offset);
9403 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9404 MCAsmParser &Parser = getParser();
9405 // Check the ordering of unwind directives
9406 if (!UC.hasFnStart()) {
9407 Error(L, ".fnstart must precede .pad directive");
9410 if (UC.hasHandlerData()) {
9411 Error(L, ".pad must precede .handlerdata directive");
9416 if (Parser.getTok().isNot(AsmToken::Hash) &&
9417 Parser.getTok().isNot(AsmToken::Dollar)) {
9418 Error(Parser.getTok().getLoc(), "'#' expected");
9421 Parser.Lex(); // skip hash token.
9423 const MCExpr *OffsetExpr;
9424 SMLoc ExLoc = Parser.getTok().getLoc();
9426 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9427 Error(ExLoc, "malformed pad offset");
9430 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9432 Error(ExLoc, "pad offset must be an immediate");
9436 getTargetStreamer().emitPad(CE->getValue());
9440 /// parseDirectiveRegSave
9441 /// ::= .save { registers }
9442 /// ::= .vsave { registers }
9443 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9444 // Check the ordering of unwind directives
9445 if (!UC.hasFnStart()) {
9446 Error(L, ".fnstart must precede .save or .vsave directives");
9449 if (UC.hasHandlerData()) {
9450 Error(L, ".save or .vsave must precede .handlerdata directive");
9454 // RAII object to make sure parsed operands are deleted.
9455 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9457 // Parse the register list
9458 if (parseRegisterList(Operands))
9460 ARMOperand &Op = (ARMOperand &)*Operands[0];
9461 if (!IsVector && !Op.isRegList()) {
9462 Error(L, ".save expects GPR registers");
9465 if (IsVector && !Op.isDPRRegList()) {
9466 Error(L, ".vsave expects DPR registers");
9470 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9474 /// parseDirectiveInst
9475 /// ::= .inst opcode [, ...]
9476 /// ::= .inst.n opcode [, ...]
9477 /// ::= .inst.w opcode [, ...]
9478 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
9479 MCAsmParser &Parser = getParser();
9491 Parser.eatToEndOfStatement();
9492 Error(Loc, "cannot determine Thumb instruction size, "
9493 "use inst.n/inst.w instead");
9498 Parser.eatToEndOfStatement();
9499 Error(Loc, "width suffixes are invalid in ARM mode");
9505 if (getLexer().is(AsmToken::EndOfStatement)) {
9506 Parser.eatToEndOfStatement();
9507 Error(Loc, "expected expression following directive");
9514 if (getParser().parseExpression(Expr)) {
9515 Error(Loc, "expected expression");
9519 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9521 Error(Loc, "expected constant expression");
9527 if (Value->getValue() > 0xffff) {
9528 Error(Loc, "inst.n operand is too big, use inst.w instead");
9533 if (Value->getValue() > 0xffffffff) {
9535 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9540 llvm_unreachable("only supported widths are 2 and 4");
9543 getTargetStreamer().emitInst(Value->getValue(), Suffix);
9545 if (getLexer().is(AsmToken::EndOfStatement))
9548 if (getLexer().isNot(AsmToken::Comma)) {
9549 Error(Loc, "unexpected token in directive");
9560 /// parseDirectiveLtorg
9561 /// ::= .ltorg | .pool
9562 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9563 getTargetStreamer().emitCurrentConstantPool();
9567 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9568 const MCSection *Section = getStreamer().getCurrentSection().first;
9570 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9571 TokError("unexpected token in directive");
9576 getStreamer().InitSections(false);
9577 Section = getStreamer().getCurrentSection().first;
9580 assert(Section && "must have section to emit alignment");
9581 if (Section->UseCodeAlign())
9582 getStreamer().EmitCodeAlignment(2);
9584 getStreamer().EmitValueToAlignment(2);
9589 /// parseDirectivePersonalityIndex
9590 /// ::= .personalityindex index
9591 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9592 MCAsmParser &Parser = getParser();
9593 bool HasExistingPersonality = UC.hasPersonality();
9595 UC.recordPersonalityIndex(L);
9597 if (!UC.hasFnStart()) {
9598 Parser.eatToEndOfStatement();
9599 Error(L, ".fnstart must precede .personalityindex directive");
9602 if (UC.cantUnwind()) {
9603 Parser.eatToEndOfStatement();
9604 Error(L, ".personalityindex cannot be used with .cantunwind");
9605 UC.emitCantUnwindLocNotes();
9608 if (UC.hasHandlerData()) {
9609 Parser.eatToEndOfStatement();
9610 Error(L, ".personalityindex must precede .handlerdata directive");
9611 UC.emitHandlerDataLocNotes();
9614 if (HasExistingPersonality) {
9615 Parser.eatToEndOfStatement();
9616 Error(L, "multiple personality directives");
9617 UC.emitPersonalityLocNotes();
9621 const MCExpr *IndexExpression;
9622 SMLoc IndexLoc = Parser.getTok().getLoc();
9623 if (Parser.parseExpression(IndexExpression)) {
9624 Parser.eatToEndOfStatement();
9628 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9630 Parser.eatToEndOfStatement();
9631 Error(IndexLoc, "index must be a constant number");
9634 if (CE->getValue() < 0 ||
9635 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9636 Parser.eatToEndOfStatement();
9637 Error(IndexLoc, "personality routine index should be in range [0-3]");
9641 getTargetStreamer().emitPersonalityIndex(CE->getValue());
9645 /// parseDirectiveUnwindRaw
9646 /// ::= .unwind_raw offset, opcode [, opcode...]
9647 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9648 MCAsmParser &Parser = getParser();
9649 if (!UC.hasFnStart()) {
9650 Parser.eatToEndOfStatement();
9651 Error(L, ".fnstart must precede .unwind_raw directives");
9655 int64_t StackOffset;
9657 const MCExpr *OffsetExpr;
9658 SMLoc OffsetLoc = getLexer().getLoc();
9659 if (getLexer().is(AsmToken::EndOfStatement) ||
9660 getParser().parseExpression(OffsetExpr)) {
9661 Error(OffsetLoc, "expected expression");
9662 Parser.eatToEndOfStatement();
9666 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9668 Error(OffsetLoc, "offset must be a constant");
9669 Parser.eatToEndOfStatement();
9673 StackOffset = CE->getValue();
9675 if (getLexer().isNot(AsmToken::Comma)) {
9676 Error(getLexer().getLoc(), "expected comma");
9677 Parser.eatToEndOfStatement();
9682 SmallVector<uint8_t, 16> Opcodes;
9686 SMLoc OpcodeLoc = getLexer().getLoc();
9687 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9688 Error(OpcodeLoc, "expected opcode expression");
9689 Parser.eatToEndOfStatement();
9693 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9695 Error(OpcodeLoc, "opcode value must be a constant");
9696 Parser.eatToEndOfStatement();
9700 const int64_t Opcode = OC->getValue();
9701 if (Opcode & ~0xff) {
9702 Error(OpcodeLoc, "invalid opcode");
9703 Parser.eatToEndOfStatement();
9707 Opcodes.push_back(uint8_t(Opcode));
9709 if (getLexer().is(AsmToken::EndOfStatement))
9712 if (getLexer().isNot(AsmToken::Comma)) {
9713 Error(getLexer().getLoc(), "unexpected token in directive");
9714 Parser.eatToEndOfStatement();
9721 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9727 /// parseDirectiveTLSDescSeq
9728 /// ::= .tlsdescseq tls-variable
9729 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9730 MCAsmParser &Parser = getParser();
9732 if (getLexer().isNot(AsmToken::Identifier)) {
9733 TokError("expected variable after '.tlsdescseq' directive");
9734 Parser.eatToEndOfStatement();
9738 const MCSymbolRefExpr *SRE =
9739 MCSymbolRefExpr::create(Parser.getTok().getIdentifier(),
9740 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9743 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9744 Error(Parser.getTok().getLoc(), "unexpected token");
9745 Parser.eatToEndOfStatement();
9749 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9753 /// parseDirectiveMovSP
9754 /// ::= .movsp reg [, #offset]
9755 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9756 MCAsmParser &Parser = getParser();
9757 if (!UC.hasFnStart()) {
9758 Parser.eatToEndOfStatement();
9759 Error(L, ".fnstart must precede .movsp directives");
9762 if (UC.getFPReg() != ARM::SP) {
9763 Parser.eatToEndOfStatement();
9764 Error(L, "unexpected .movsp directive");
9768 SMLoc SPRegLoc = Parser.getTok().getLoc();
9769 int SPReg = tryParseRegister();
9771 Parser.eatToEndOfStatement();
9772 Error(SPRegLoc, "register expected");
9776 if (SPReg == ARM::SP || SPReg == ARM::PC) {
9777 Parser.eatToEndOfStatement();
9778 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9783 if (Parser.getTok().is(AsmToken::Comma)) {
9786 if (Parser.getTok().isNot(AsmToken::Hash)) {
9787 Error(Parser.getTok().getLoc(), "expected #constant");
9788 Parser.eatToEndOfStatement();
9793 const MCExpr *OffsetExpr;
9794 SMLoc OffsetLoc = Parser.getTok().getLoc();
9795 if (Parser.parseExpression(OffsetExpr)) {
9796 Parser.eatToEndOfStatement();
9797 Error(OffsetLoc, "malformed offset expression");
9801 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9803 Parser.eatToEndOfStatement();
9804 Error(OffsetLoc, "offset must be an immediate constant");
9808 Offset = CE->getValue();
9811 getTargetStreamer().emitMovSP(SPReg, Offset);
9812 UC.saveFPReg(SPReg);
9817 /// parseDirectiveObjectArch
9818 /// ::= .object_arch name
9819 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9820 MCAsmParser &Parser = getParser();
9821 if (getLexer().isNot(AsmToken::Identifier)) {
9822 Error(getLexer().getLoc(), "unexpected token");
9823 Parser.eatToEndOfStatement();
9827 StringRef Arch = Parser.getTok().getString();
9828 SMLoc ArchLoc = Parser.getTok().getLoc();
9831 unsigned ID = ARM::parseArch(Arch);
9833 if (ID == ARM::AK_INVALID) {
9834 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9835 Parser.eatToEndOfStatement();
9839 getTargetStreamer().emitObjectArch(ID);
9841 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9842 Error(getLexer().getLoc(), "unexpected token");
9843 Parser.eatToEndOfStatement();
9849 /// parseDirectiveAlign
9851 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9852 // NOTE: if this is not the end of the statement, fall back to the target
9853 // agnostic handling for this directive which will correctly handle this.
9854 if (getLexer().isNot(AsmToken::EndOfStatement))
9857 // '.align' is target specifically handled to mean 2**2 byte alignment.
9858 if (getStreamer().getCurrentSection().first->UseCodeAlign())
9859 getStreamer().EmitCodeAlignment(4, 0);
9861 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9866 /// parseDirectiveThumbSet
9867 /// ::= .thumb_set name, value
9868 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9869 MCAsmParser &Parser = getParser();
9872 if (Parser.parseIdentifier(Name)) {
9873 TokError("expected identifier after '.thumb_set'");
9874 Parser.eatToEndOfStatement();
9878 if (getLexer().isNot(AsmToken::Comma)) {
9879 TokError("expected comma after name '" + Name + "'");
9880 Parser.eatToEndOfStatement();
9886 const MCExpr *Value;
9887 if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true,
9888 Parser, Sym, Value))
9891 getTargetStreamer().emitThumbSet(Sym, Value);
9895 /// Force static initialization.
9896 extern "C" void LLVMInitializeARMAsmParser() {
9897 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9898 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9899 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9900 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9903 #define GET_REGISTER_MATCHER
9904 #define GET_SUBTARGET_FEATURE_NAME
9905 #define GET_MATCHER_IMPLEMENTATION
9906 #include "ARMGenAsmMatcher.inc"
9908 // FIXME: This structure should be moved inside ARMTargetParser
9909 // when we start to table-generate them, and we can use the ARM
9910 // flags below, that were generated by table-gen.
9911 static const struct {
9912 const unsigned Kind;
9913 const unsigned ArchCheck;
9914 const FeatureBitset Features;
9916 { ARM::AEK_CRC, Feature_HasV8, {ARM::FeatureCRC} },
9917 { ARM::AEK_CRYPTO, Feature_HasV8,
9918 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
9919 { ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} },
9920 { (ARM::AEK_HWDIV | ARM::AEK_HWDIVARM), Feature_HasV7 | Feature_IsNotMClass,
9921 {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} },
9922 { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
9923 { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
9924 { ARM::AEK_SEC, Feature_HasV6K, {ARM::FeatureTrustZone} },
9925 // FIXME: Only available in A-class, isel not predicated
9926 { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} },
9927 // FIXME: Unsupported extensions.
9928 { ARM::AEK_OS, Feature_None, {} },
9929 { ARM::AEK_IWMMXT, Feature_None, {} },
9930 { ARM::AEK_IWMMXT2, Feature_None, {} },
9931 { ARM::AEK_MAVERICK, Feature_None, {} },
9932 { ARM::AEK_XSCALE, Feature_None, {} },
9935 /// parseDirectiveArchExtension
9936 /// ::= .arch_extension [no]feature
9937 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9938 MCAsmParser &Parser = getParser();
9940 if (getLexer().isNot(AsmToken::Identifier)) {
9941 Error(getLexer().getLoc(), "unexpected token");
9942 Parser.eatToEndOfStatement();
9946 StringRef Name = Parser.getTok().getString();
9947 SMLoc ExtLoc = Parser.getTok().getLoc();
9950 bool EnableFeature = true;
9951 if (Name.startswith_lower("no")) {
9952 EnableFeature = false;
9953 Name = Name.substr(2);
9955 unsigned FeatureKind = ARM::parseArchExt(Name);
9956 if (FeatureKind == ARM::AEK_INVALID)
9957 Error(ExtLoc, "unknown architectural extension: " + Name);
9959 for (const auto &Extension : Extensions) {
9960 if (Extension.Kind != FeatureKind)
9963 if (Extension.Features.none())
9964 report_fatal_error("unsupported architectural extension: " + Name);
9966 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
9967 Error(ExtLoc, "architectural extension '" + Name + "' is not "
9968 "allowed for the current base architecture");
9972 FeatureBitset ToggleFeatures = EnableFeature
9973 ? (~STI.getFeatureBits() & Extension.Features)
9974 : ( STI.getFeatureBits() & Extension.Features);
9977 ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
9978 setAvailableFeatures(Features);
9982 Error(ExtLoc, "unknown architectural extension: " + Name);
9983 Parser.eatToEndOfStatement();
9987 // Define this matcher function after the auto-generated include so we
9988 // have the match class enum definitions.
9989 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
9991 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
9992 // If the kind is a token for a literal immediate, check if our asm
9993 // operand matches. This is for InstAliases which have a fixed-value
9994 // immediate in the syntax.
9999 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
10000 if (CE->getValue() == 0)
10001 return Match_Success;
10005 const MCExpr *SOExpr = Op.getImm();
10007 if (!SOExpr->evaluateAsAbsolute(Value))
10008 return Match_Success;
10009 assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
10010 "expression value must be representable in 32 bits");
10014 if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
10015 return Match_Success;
10019 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
10020 return Match_Success;
10023 return Match_InvalidOperand;