1 //===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMREGISTERINFO_H
15 #define ARMREGISTERINFO_H
17 #include "llvm/Target/MRegisterInfo.h"
18 #include "ARMGenRegisterInfo.h.inc"
22 class TargetInstrInfo;
25 struct ARMRegisterInfo : public ARMGenRegisterInfo {
26 const TargetInstrInfo &TII;
27 const ARMSubtarget &STI;
29 /// FramePtr - ARM physical register used as frame ptr.
33 ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
35 /// getRegisterNumbering - Given the enum value for some register, e.g.
36 /// ARM::LR, return the number that it corresponds to (e.g. 14).
37 static unsigned getRegisterNumbering(unsigned RegEnum);
39 /// Code Generation virtual methods...
40 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
41 MachineBasicBlock::iterator MI,
42 const std::vector<CalleeSavedInfo> &CSI) const;
44 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
45 MachineBasicBlock::iterator MI,
46 const std::vector<CalleeSavedInfo> &CSI) const;
48 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
49 unsigned DestReg, const MachineInstr *Orig) const;
51 MachineInstr* foldMemoryOperand(MachineInstr* MI,
52 SmallVectorImpl<unsigned> &Ops,
53 int FrameIndex) const;
55 MachineInstr* foldMemoryOperand(MachineInstr* MI,
56 SmallVectorImpl<unsigned> &Ops,
57 MachineInstr* LoadMI) const {
61 bool canFoldMemoryOperand(MachineInstr *MI,
62 SmallVectorImpl<unsigned> &Ops) const;
64 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
66 const TargetRegisterClass* const*
67 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
69 BitVector getReservedRegs(const MachineFunction &MF) const;
71 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
73 bool requiresRegisterScavenging(const MachineFunction &MF) const;
75 bool hasFP(const MachineFunction &MF) const;
77 bool hasReservedCallFrame(MachineFunction &MF) const;
79 void eliminateCallFramePseudoInstr(MachineFunction &MF,
80 MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator I) const;
83 void eliminateFrameIndex(MachineBasicBlock::iterator II,
84 int SPAdj, RegScavenger *RS = NULL) const;
86 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
87 RegScavenger *RS = NULL) const;
89 void emitPrologue(MachineFunction &MF) const;
90 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
92 // Debug information queries.
93 unsigned getRARegister() const;
94 unsigned getFrameRegister(MachineFunction &MF) const;
96 // Exception handling queries.
97 unsigned getEHExceptionRegister() const;
98 unsigned getEHHandlerRegister() const;
100 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
103 } // end namespace llvm