1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ",
69 SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>;
71 def SDTARMVLD2 : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
72 def SDTARMVLD3 : SDTypeProfile<3, 1, [SDTCisSameAs<0, 1>,
73 SDTCisSameAs<0, 2>, SDTCisPtrTy<3>]>;
74 def SDTARMVLD4 : SDTypeProfile<4, 1, [SDTCisSameAs<0, 1>,
76 SDTCisSameAs<0, 3>, SDTCisPtrTy<4>]>;
77 def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD2,
78 [SDNPHasChain, SDNPMayLoad]>;
79 def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD3,
80 [SDNPHasChain, SDNPMayLoad]>;
81 def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD4,
82 [SDNPHasChain, SDNPMayLoad]>;
84 def SDTARMVST2 : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>]>;
85 def SDTARMVST3 : SDTypeProfile<0, 4, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
87 def SDTARMVST4 : SDTypeProfile<0, 5, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
91 def NEONvst2d : SDNode<"ARMISD::VST2D", SDTARMVST2,
92 [SDNPHasChain, SDNPMayStore]>;
93 def NEONvst3d : SDNode<"ARMISD::VST3D", SDTARMVST3,
94 [SDNPHasChain, SDNPMayStore]>;
95 def NEONvst4d : SDNode<"ARMISD::VST4D", SDTARMVST4,
96 [SDNPHasChain, SDNPMayStore]>;
98 //===----------------------------------------------------------------------===//
99 // NEON operand definitions
100 //===----------------------------------------------------------------------===//
102 // addrmode_neonldstm := reg
104 /* TODO: Take advantage of vldm.
105 def addrmode_neonldstm : Operand<i32>,
106 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
107 let PrintMethod = "printAddrNeonLdStMOperand";
108 let MIOperandInfo = (ops GPR, i32imm);
112 //===----------------------------------------------------------------------===//
113 // NEON load / store instructions
114 //===----------------------------------------------------------------------===//
116 /* TODO: Take advantage of vldm.
118 def VLDMD : NI<(outs),
119 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
121 "vldm${addr:submode} ${addr:base}, $dst1",
123 let Inst{27-25} = 0b110;
125 let Inst{11-9} = 0b101;
128 def VLDMS : NI<(outs),
129 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
131 "vldm${addr:submode} ${addr:base}, $dst1",
133 let Inst{27-25} = 0b110;
135 let Inst{11-9} = 0b101;
140 // Use vldmia to load a Q register as a D register pair.
141 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
143 "vldmia $addr, ${dst:dregpair}",
144 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
145 let Inst{27-25} = 0b110;
146 let Inst{24} = 0; // P bit
147 let Inst{23} = 1; // U bit
149 let Inst{11-9} = 0b101;
152 // Use vstmia to store a Q register as a D register pair.
153 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
155 "vstmia $addr, ${src:dregpair}",
156 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
157 let Inst{27-25} = 0b110;
158 let Inst{24} = 0; // P bit
159 let Inst{23} = 1; // U bit
161 let Inst{11-9} = 0b101;
164 // VLD1 : Vector Load (multiple single elements)
165 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
166 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
168 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"),
169 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
170 class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
171 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
173 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
174 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
176 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1>;
177 def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1>;
178 def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1>;
179 def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1>;
180 def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1>;
182 def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1>;
183 def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1>;
184 def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1>;
185 def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1>;
186 def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1>;
190 // VLD2 : Vector Load (multiple 2-element structures)
191 class VLD2D<string OpcodeStr>
192 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr),
194 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), []>;
196 def VLD2d8 : VLD2D<"vld2.8">;
197 def VLD2d16 : VLD2D<"vld2.16">;
198 def VLD2d32 : VLD2D<"vld2.32">;
200 // VLD3 : Vector Load (multiple 3-element structures)
201 class VLD3D<string OpcodeStr>
202 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
204 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), []>;
206 def VLD3d8 : VLD3D<"vld3.8">;
207 def VLD3d16 : VLD3D<"vld3.16">;
208 def VLD3d32 : VLD3D<"vld3.32">;
210 // VLD4 : Vector Load (multiple 4-element structures)
211 class VLD4D<string OpcodeStr>
212 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
213 (ins addrmode6:$addr),
215 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), []>;
217 def VLD4d8 : VLD4D<"vld4.8">;
218 def VLD4d16 : VLD4D<"vld4.16">;
219 def VLD4d32 : VLD4D<"vld4.32">;
222 // VST1 : Vector Store (multiple single elements)
223 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
224 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
226 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
227 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
228 class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
229 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
231 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
232 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
234 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1>;
235 def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1>;
236 def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1>;
237 def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1>;
238 def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1>;
240 def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1>;
241 def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1>;
242 def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1>;
243 def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1>;
244 def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1>;
246 let mayStore = 1 in {
248 // VST2 : Vector Store (multiple 2-element structures)
249 class VST2D<string OpcodeStr>
250 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
251 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), []>;
253 def VST2d8 : VST2D<"vst2.8">;
254 def VST2d16 : VST2D<"vst2.16">;
255 def VST2d32 : VST2D<"vst2.32">;
257 // VST3 : Vector Store (multiple 3-element structures)
258 class VST3D<string OpcodeStr>
259 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
261 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), []>;
263 def VST3d8 : VST3D<"vst3.8">;
264 def VST3d16 : VST3D<"vst3.16">;
265 def VST3d32 : VST3D<"vst3.32">;
267 // VST4 : Vector Store (multiple 4-element structures)
268 class VST4D<string OpcodeStr>
269 : NLdSt<(outs), (ins addrmode6:$addr,
270 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary,
271 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), []>;
273 def VST4d8 : VST4D<"vst4.8">;
274 def VST4d16 : VST4D<"vst4.16">;
275 def VST4d32 : VST4D<"vst4.32">;
279 //===----------------------------------------------------------------------===//
280 // NEON pattern fragments
281 //===----------------------------------------------------------------------===//
283 // Extract D sub-registers of Q registers.
284 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
285 def DSubReg_i8_reg : SDNodeXForm<imm, [{
286 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
288 def DSubReg_i16_reg : SDNodeXForm<imm, [{
289 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
291 def DSubReg_i32_reg : SDNodeXForm<imm, [{
292 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
294 def DSubReg_f64_reg : SDNodeXForm<imm, [{
295 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
298 // Extract S sub-registers of Q registers.
299 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
300 def SSubReg_f32_reg : SDNodeXForm<imm, [{
301 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
304 // Translate lane numbers from Q registers to D subregs.
305 def SubReg_i8_lane : SDNodeXForm<imm, [{
306 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
308 def SubReg_i16_lane : SDNodeXForm<imm, [{
309 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
311 def SubReg_i32_lane : SDNodeXForm<imm, [{
312 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
315 //===----------------------------------------------------------------------===//
316 // Instruction Classes
317 //===----------------------------------------------------------------------===//
319 // Basic 2-register operations, both double- and quad-register.
320 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
321 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
322 ValueType ResTy, ValueType OpTy, SDNode OpNode>
323 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
324 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
325 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
326 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
327 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
328 ValueType ResTy, ValueType OpTy, SDNode OpNode>
329 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
330 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
331 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
333 // Basic 2-register operations, scalar single-precision.
334 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
335 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
336 ValueType ResTy, ValueType OpTy, SDNode OpNode>
337 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
338 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
339 NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
341 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
342 : NEONFPPat<(ResTy (OpNode SPR:$a)),
344 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
347 // Basic 2-register intrinsics, both double- and quad-register.
348 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
349 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
350 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
351 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
352 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
353 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
354 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
355 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
356 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
357 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
358 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
359 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
361 // Basic 2-register intrinsics, scalar single-precision
362 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
363 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
364 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
365 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
366 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
367 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
369 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
370 : NEONFPPat<(f32 (OpNode SPR:$a)),
372 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
375 // Narrow 2-register intrinsics.
376 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
377 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
378 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
379 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
380 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
381 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
383 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
384 // derived from N2VImm instead of N2V because of the way the size is encoded.)
385 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
386 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
388 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
389 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
390 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
392 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
393 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
394 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
395 (ins DPR:$src1, DPR:$src2), NoItinerary,
396 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
397 "$src1 = $dst1, $src2 = $dst2", []>;
398 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
399 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
400 (ins QPR:$src1, QPR:$src2), NoItinerary,
401 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
402 "$src1 = $dst1, $src2 = $dst2", []>;
404 // Basic 3-register operations, both double- and quad-register.
405 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
406 string OpcodeStr, ValueType ResTy, ValueType OpTy,
407 SDNode OpNode, bit Commutable>
408 : N3V<op24, op23, op21_20, op11_8, 0, op4,
409 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
410 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
411 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
412 let isCommutable = Commutable;
414 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
415 string OpcodeStr, ValueType ResTy, ValueType OpTy,
416 SDNode OpNode, bit Commutable>
417 : N3V<op24, op23, op21_20, op11_8, 1, op4,
418 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
419 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
420 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
421 let isCommutable = Commutable;
424 // Basic 3-register operations, scalar single-precision
425 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
426 string OpcodeStr, ValueType ResTy, ValueType OpTy,
427 SDNode OpNode, bit Commutable>
428 : N3V<op24, op23, op21_20, op11_8, 0, op4,
429 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), NoItinerary,
430 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
431 let isCommutable = Commutable;
433 class N3VDsPat<SDNode OpNode, NeonI Inst>
434 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
436 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
437 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
440 // Basic 3-register intrinsics, both double- and quad-register.
441 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
442 string OpcodeStr, ValueType ResTy, ValueType OpTy,
443 Intrinsic IntOp, bit Commutable>
444 : N3V<op24, op23, op21_20, op11_8, 0, op4,
445 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
446 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
447 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
448 let isCommutable = Commutable;
450 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
451 string OpcodeStr, ValueType ResTy, ValueType OpTy,
452 Intrinsic IntOp, bit Commutable>
453 : N3V<op24, op23, op21_20, op11_8, 1, op4,
454 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
455 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
456 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
457 let isCommutable = Commutable;
460 // Multiply-Add/Sub operations, both double- and quad-register.
461 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
462 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
463 : N3V<op24, op23, op21_20, op11_8, 0, op4,
464 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
465 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
466 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
467 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
468 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
469 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
470 : N3V<op24, op23, op21_20, op11_8, 1, op4,
471 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
472 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
473 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
474 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
476 // Multiply-Add/Sub operations, scalar single-precision
477 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
478 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
479 : N3V<op24, op23, op21_20, op11_8, 0, op4,
480 (outs DPR_VFP2:$dst),
481 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), NoItinerary,
482 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
484 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
485 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
487 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
488 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
489 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
492 // Neon 3-argument intrinsics, both double- and quad-register.
493 // The destination register is also used as the first source operand register.
494 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
495 string OpcodeStr, ValueType ResTy, ValueType OpTy,
497 : N3V<op24, op23, op21_20, op11_8, 0, op4,
498 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
499 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
500 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
501 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
502 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
503 string OpcodeStr, ValueType ResTy, ValueType OpTy,
505 : N3V<op24, op23, op21_20, op11_8, 1, op4,
506 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
507 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
508 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
509 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
511 // Neon Long 3-argument intrinsic. The destination register is
512 // a quad-register and is also used as the first source operand register.
513 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
514 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
515 : N3V<op24, op23, op21_20, op11_8, 0, op4,
516 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
517 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
519 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
521 // Narrowing 3-register intrinsics.
522 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
523 string OpcodeStr, ValueType TyD, ValueType TyQ,
524 Intrinsic IntOp, bit Commutable>
525 : N3V<op24, op23, op21_20, op11_8, 0, op4,
526 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
527 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
528 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
529 let isCommutable = Commutable;
532 // Long 3-register intrinsics.
533 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
534 string OpcodeStr, ValueType TyQ, ValueType TyD,
535 Intrinsic IntOp, bit Commutable>
536 : N3V<op24, op23, op21_20, op11_8, 0, op4,
537 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
538 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
539 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
540 let isCommutable = Commutable;
543 // Wide 3-register intrinsics.
544 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
545 string OpcodeStr, ValueType TyQ, ValueType TyD,
546 Intrinsic IntOp, bit Commutable>
547 : N3V<op24, op23, op21_20, op11_8, 0, op4,
548 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), NoItinerary,
549 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
550 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
551 let isCommutable = Commutable;
554 // Pairwise long 2-register intrinsics, both double- and quad-register.
555 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
556 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
557 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
558 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
559 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
560 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
561 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
562 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
563 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
564 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
565 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
566 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
568 // Pairwise long 2-register accumulate intrinsics,
569 // both double- and quad-register.
570 // The destination register is also used as the first source operand register.
571 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
572 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
573 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
574 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
575 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
576 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
577 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
578 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
579 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
580 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
581 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
582 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
583 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
584 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
586 // Shift by immediate,
587 // both double- and quad-register.
588 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
589 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
590 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
591 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
592 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
593 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
594 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
595 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
596 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
597 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
598 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
599 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
601 // Long shift by immediate.
602 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
603 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
604 ValueType OpTy, SDNode OpNode>
605 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
606 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
607 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
608 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
609 (i32 imm:$SIMM))))]>;
611 // Narrow shift by immediate.
612 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
613 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
614 ValueType OpTy, SDNode OpNode>
615 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
616 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
617 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
618 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
619 (i32 imm:$SIMM))))]>;
621 // Shift right by immediate and accumulate,
622 // both double- and quad-register.
623 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
624 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
625 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
626 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
628 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
629 [(set DPR:$dst, (Ty (add DPR:$src1,
630 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
631 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
632 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
633 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
634 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
636 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
637 [(set QPR:$dst, (Ty (add QPR:$src1,
638 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
640 // Shift by immediate and insert,
641 // both double- and quad-register.
642 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
643 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
644 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
645 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
647 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
648 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
649 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
650 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
651 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
652 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
654 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
655 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
657 // Convert, with fractional bits immediate,
658 // both double- and quad-register.
659 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
660 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
662 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
663 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
664 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
665 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
666 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
667 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
669 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
670 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
671 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
672 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
674 //===----------------------------------------------------------------------===//
676 //===----------------------------------------------------------------------===//
678 // Neon 3-register vector operations.
680 // First with only element sizes of 8, 16 and 32 bits:
681 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
682 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
683 // 64-bit vector types.
684 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
685 v8i8, v8i8, OpNode, Commutable>;
686 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
687 v4i16, v4i16, OpNode, Commutable>;
688 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
689 v2i32, v2i32, OpNode, Commutable>;
691 // 128-bit vector types.
692 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
693 v16i8, v16i8, OpNode, Commutable>;
694 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
695 v8i16, v8i16, OpNode, Commutable>;
696 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
697 v4i32, v4i32, OpNode, Commutable>;
700 // ....then also with element size 64 bits:
701 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
702 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
703 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
704 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
705 v1i64, v1i64, OpNode, Commutable>;
706 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
707 v2i64, v2i64, OpNode, Commutable>;
711 // Neon Narrowing 2-register vector intrinsics,
712 // source operand element sizes of 16, 32 and 64 bits:
713 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
714 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
716 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
717 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
718 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
719 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
720 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
721 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
725 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
726 // source operand element sizes of 16, 32 and 64 bits:
727 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
728 bit op4, string OpcodeStr, Intrinsic IntOp> {
729 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
730 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
731 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
732 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
733 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
734 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
738 // Neon 3-register vector intrinsics.
740 // First with only element sizes of 16 and 32 bits:
741 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
742 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
743 // 64-bit vector types.
744 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
745 v4i16, v4i16, IntOp, Commutable>;
746 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
747 v2i32, v2i32, IntOp, Commutable>;
749 // 128-bit vector types.
750 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
751 v8i16, v8i16, IntOp, Commutable>;
752 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
753 v4i32, v4i32, IntOp, Commutable>;
756 // ....then also with element size of 8 bits:
757 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
758 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
759 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
760 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
761 v8i8, v8i8, IntOp, Commutable>;
762 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
763 v16i8, v16i8, IntOp, Commutable>;
766 // ....then also with element size of 64 bits:
767 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
768 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
769 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
770 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
771 v1i64, v1i64, IntOp, Commutable>;
772 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
773 v2i64, v2i64, IntOp, Commutable>;
777 // Neon Narrowing 3-register vector intrinsics,
778 // source operand element sizes of 16, 32 and 64 bits:
779 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
780 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
781 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
782 v8i8, v8i16, IntOp, Commutable>;
783 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
784 v4i16, v4i32, IntOp, Commutable>;
785 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
786 v2i32, v2i64, IntOp, Commutable>;
790 // Neon Long 3-register vector intrinsics.
792 // First with only element sizes of 16 and 32 bits:
793 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
794 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
795 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
796 v4i32, v4i16, IntOp, Commutable>;
797 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
798 v2i64, v2i32, IntOp, Commutable>;
801 // ....then also with element size of 8 bits:
802 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
803 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
804 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
805 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
806 v8i16, v8i8, IntOp, Commutable>;
810 // Neon Wide 3-register vector intrinsics,
811 // source operand element sizes of 8, 16 and 32 bits:
812 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
813 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
814 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
815 v8i16, v8i8, IntOp, Commutable>;
816 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
817 v4i32, v4i16, IntOp, Commutable>;
818 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
819 v2i64, v2i32, IntOp, Commutable>;
823 // Neon Multiply-Op vector operations,
824 // element sizes of 8, 16 and 32 bits:
825 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
826 string OpcodeStr, SDNode OpNode> {
827 // 64-bit vector types.
828 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
829 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
830 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
831 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
832 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
833 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
835 // 128-bit vector types.
836 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
837 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
838 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
839 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
840 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
841 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
845 // Neon 3-argument intrinsics,
846 // element sizes of 8, 16 and 32 bits:
847 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
848 string OpcodeStr, Intrinsic IntOp> {
849 // 64-bit vector types.
850 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
851 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
852 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
853 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
854 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
855 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
857 // 128-bit vector types.
858 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
859 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
860 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
861 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
862 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
863 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
867 // Neon Long 3-argument intrinsics.
869 // First with only element sizes of 16 and 32 bits:
870 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
871 string OpcodeStr, Intrinsic IntOp> {
872 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
873 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
874 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
875 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
878 // ....then also with element size of 8 bits:
879 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
880 string OpcodeStr, Intrinsic IntOp>
881 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
882 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
883 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
887 // Neon 2-register vector intrinsics,
888 // element sizes of 8, 16 and 32 bits:
889 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
890 bits<5> op11_7, bit op4, string OpcodeStr,
892 // 64-bit vector types.
893 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
894 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
895 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
896 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
897 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
898 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
900 // 128-bit vector types.
901 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
902 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
903 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
904 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
905 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
906 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
910 // Neon Pairwise long 2-register intrinsics,
911 // element sizes of 8, 16 and 32 bits:
912 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
913 bits<5> op11_7, bit op4,
914 string OpcodeStr, Intrinsic IntOp> {
915 // 64-bit vector types.
916 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
917 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
918 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
919 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
920 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
921 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
923 // 128-bit vector types.
924 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
925 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
926 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
927 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
928 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
929 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
933 // Neon Pairwise long 2-register accumulate intrinsics,
934 // element sizes of 8, 16 and 32 bits:
935 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
936 bits<5> op11_7, bit op4,
937 string OpcodeStr, Intrinsic IntOp> {
938 // 64-bit vector types.
939 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
940 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
941 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
942 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
943 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
944 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
946 // 128-bit vector types.
947 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
948 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
949 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
950 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
951 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
952 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
956 // Neon 2-register vector shift by immediate,
957 // element sizes of 8, 16, 32 and 64 bits:
958 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
959 string OpcodeStr, SDNode OpNode> {
960 // 64-bit vector types.
961 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
962 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
963 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
964 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
965 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
966 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
967 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
968 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
970 // 128-bit vector types.
971 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
972 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
973 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
974 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
975 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
976 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
977 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
978 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
982 // Neon Shift-Accumulate vector operations,
983 // element sizes of 8, 16, 32 and 64 bits:
984 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
985 string OpcodeStr, SDNode ShOp> {
986 // 64-bit vector types.
987 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
988 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
989 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
990 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
991 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
992 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
993 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
994 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
996 // 128-bit vector types.
997 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
998 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
999 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1000 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1001 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1002 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1003 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1004 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1008 // Neon Shift-Insert vector operations,
1009 // element sizes of 8, 16, 32 and 64 bits:
1010 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1011 string OpcodeStr, SDNode ShOp> {
1012 // 64-bit vector types.
1013 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
1014 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1015 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
1016 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1017 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
1018 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1019 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
1020 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1022 // 128-bit vector types.
1023 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
1024 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1025 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
1026 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1027 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
1028 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1029 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
1030 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1033 //===----------------------------------------------------------------------===//
1034 // Instruction Definitions.
1035 //===----------------------------------------------------------------------===//
1037 // Vector Add Operations.
1039 // VADD : Vector Add (integer and floating-point)
1040 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
1041 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
1042 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
1043 // VADDL : Vector Add Long (Q = D + D)
1044 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
1045 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
1046 // VADDW : Vector Add Wide (Q = Q + D)
1047 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1048 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1049 // VHADD : Vector Halving Add
1050 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
1051 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
1052 // VRHADD : Vector Rounding Halving Add
1053 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1054 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1055 // VQADD : Vector Saturating Add
1056 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
1057 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
1058 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1059 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1060 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1061 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1063 // Vector Multiply Operations.
1065 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1066 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
1067 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
1068 int_arm_neon_vmulp, 1>;
1069 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
1070 int_arm_neon_vmulp, 1>;
1071 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
1072 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
1073 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1074 defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1075 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1076 defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1077 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1078 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
1079 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
1080 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
1081 int_arm_neon_vmullp, 1>;
1082 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1083 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1085 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1087 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1088 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
1089 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
1090 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
1091 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1092 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1093 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1094 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1095 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1096 // VMLS : Vector Multiply Subtract (integer and floating-point)
1097 defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
1098 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
1099 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
1100 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1101 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1102 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1103 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1104 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1106 // Vector Subtract Operations.
1108 // VSUB : Vector Subtract (integer and floating-point)
1109 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
1110 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
1111 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
1112 // VSUBL : Vector Subtract Long (Q = D - D)
1113 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
1114 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
1115 // VSUBW : Vector Subtract Wide (Q = Q - D)
1116 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1117 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1118 // VHSUB : Vector Halving Subtract
1119 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
1120 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
1121 // VQSUB : Vector Saturing Subtract
1122 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
1123 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
1124 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1125 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1126 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1127 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1129 // Vector Comparisons.
1131 // VCEQ : Vector Compare Equal
1132 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
1133 def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1134 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1135 // VCGE : Vector Compare Greater Than or Equal
1136 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
1137 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
1138 def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1139 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1140 // VCGT : Vector Compare Greater Than
1141 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
1142 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
1143 def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1144 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1145 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1146 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
1147 int_arm_neon_vacged, 0>;
1148 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
1149 int_arm_neon_vacgeq, 0>;
1150 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1151 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
1152 int_arm_neon_vacgtd, 0>;
1153 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
1154 int_arm_neon_vacgtq, 0>;
1155 // VTST : Vector Test Bits
1156 defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
1158 // Vector Bitwise Operations.
1160 // VAND : Vector Bitwise AND
1161 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
1162 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
1164 // VEOR : Vector Bitwise Exclusive OR
1165 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
1166 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
1168 // VORR : Vector Bitwise OR
1169 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
1170 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
1172 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1173 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1174 (ins DPR:$src1, DPR:$src2), NoItinerary,
1175 "vbic\t$dst, $src1, $src2", "",
1176 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1177 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1178 (ins QPR:$src1, QPR:$src2), NoItinerary,
1179 "vbic\t$dst, $src1, $src2", "",
1180 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1182 // VORN : Vector Bitwise OR NOT
1183 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1184 (ins DPR:$src1, DPR:$src2), NoItinerary,
1185 "vorn\t$dst, $src1, $src2", "",
1186 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1187 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1188 (ins QPR:$src1, QPR:$src2), NoItinerary,
1189 "vorn\t$dst, $src1, $src2", "",
1190 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1192 // VMVN : Vector Bitwise NOT
1193 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1194 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1195 "vmvn\t$dst, $src", "",
1196 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1197 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1198 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1199 "vmvn\t$dst, $src", "",
1200 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1201 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1202 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1204 // VBSL : Vector Bitwise Select
1205 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1206 (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
1207 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1209 (v2i32 (or (and DPR:$src2, DPR:$src1),
1210 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1211 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1212 (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
1213 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1215 (v4i32 (or (and QPR:$src2, QPR:$src1),
1216 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1218 // VBIF : Vector Bitwise Insert if False
1219 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1220 // VBIT : Vector Bitwise Insert if True
1221 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1222 // These are not yet implemented. The TwoAddress pass will not go looking
1223 // for equivalent operations with different register constraints; it just
1226 // Vector Absolute Differences.
1228 // VABD : Vector Absolute Difference
1229 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1230 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1231 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1232 int_arm_neon_vabds, 0>;
1233 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1234 int_arm_neon_vabds, 0>;
1236 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1237 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1238 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1240 // VABA : Vector Absolute Difference and Accumulate
1241 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1242 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1244 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1245 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1246 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1248 // Vector Maximum and Minimum.
1250 // VMAX : Vector Maximum
1251 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1252 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1253 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1254 int_arm_neon_vmaxs, 1>;
1255 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1256 int_arm_neon_vmaxs, 1>;
1258 // VMIN : Vector Minimum
1259 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1260 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1261 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1262 int_arm_neon_vmins, 1>;
1263 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1264 int_arm_neon_vmins, 1>;
1266 // Vector Pairwise Operations.
1268 // VPADD : Vector Pairwise Add
1269 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1270 int_arm_neon_vpadd, 0>;
1271 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1272 int_arm_neon_vpadd, 0>;
1273 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1274 int_arm_neon_vpadd, 0>;
1275 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1276 int_arm_neon_vpadd, 0>;
1278 // VPADDL : Vector Pairwise Add Long
1279 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1280 int_arm_neon_vpaddls>;
1281 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1282 int_arm_neon_vpaddlu>;
1284 // VPADAL : Vector Pairwise Add and Accumulate Long
1285 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1286 int_arm_neon_vpadals>;
1287 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1288 int_arm_neon_vpadalu>;
1290 // VPMAX : Vector Pairwise Maximum
1291 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1292 int_arm_neon_vpmaxs, 0>;
1293 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1294 int_arm_neon_vpmaxs, 0>;
1295 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1296 int_arm_neon_vpmaxs, 0>;
1297 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1298 int_arm_neon_vpmaxu, 0>;
1299 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1300 int_arm_neon_vpmaxu, 0>;
1301 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1302 int_arm_neon_vpmaxu, 0>;
1303 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1304 int_arm_neon_vpmaxs, 0>;
1306 // VPMIN : Vector Pairwise Minimum
1307 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1308 int_arm_neon_vpmins, 0>;
1309 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1310 int_arm_neon_vpmins, 0>;
1311 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1312 int_arm_neon_vpmins, 0>;
1313 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1314 int_arm_neon_vpminu, 0>;
1315 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1316 int_arm_neon_vpminu, 0>;
1317 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1318 int_arm_neon_vpminu, 0>;
1319 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1320 int_arm_neon_vpmins, 0>;
1322 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1324 // VRECPE : Vector Reciprocal Estimate
1325 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1326 v2i32, v2i32, int_arm_neon_vrecpe>;
1327 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1328 v4i32, v4i32, int_arm_neon_vrecpe>;
1329 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1330 v2f32, v2f32, int_arm_neon_vrecpe>;
1331 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1332 v4f32, v4f32, int_arm_neon_vrecpe>;
1334 // VRECPS : Vector Reciprocal Step
1335 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1336 int_arm_neon_vrecps, 1>;
1337 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1338 int_arm_neon_vrecps, 1>;
1340 // VRSQRTE : Vector Reciprocal Square Root Estimate
1341 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1342 v2i32, v2i32, int_arm_neon_vrsqrte>;
1343 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1344 v4i32, v4i32, int_arm_neon_vrsqrte>;
1345 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1346 v2f32, v2f32, int_arm_neon_vrsqrte>;
1347 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1348 v4f32, v4f32, int_arm_neon_vrsqrte>;
1350 // VRSQRTS : Vector Reciprocal Square Root Step
1351 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1352 int_arm_neon_vrsqrts, 1>;
1353 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1354 int_arm_neon_vrsqrts, 1>;
1358 // VSHL : Vector Shift
1359 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1360 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1361 // VSHL : Vector Shift Left (Immediate)
1362 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1363 // VSHR : Vector Shift Right (Immediate)
1364 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1365 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1367 // VSHLL : Vector Shift Left Long
1368 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1369 v8i16, v8i8, NEONvshlls>;
1370 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1371 v4i32, v4i16, NEONvshlls>;
1372 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1373 v2i64, v2i32, NEONvshlls>;
1374 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1375 v8i16, v8i8, NEONvshllu>;
1376 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1377 v4i32, v4i16, NEONvshllu>;
1378 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1379 v2i64, v2i32, NEONvshllu>;
1381 // VSHLL : Vector Shift Left Long (with maximum shift count)
1382 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1383 v8i16, v8i8, NEONvshlli>;
1384 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1385 v4i32, v4i16, NEONvshlli>;
1386 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1387 v2i64, v2i32, NEONvshlli>;
1389 // VSHRN : Vector Shift Right and Narrow
1390 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1391 v8i8, v8i16, NEONvshrn>;
1392 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1393 v4i16, v4i32, NEONvshrn>;
1394 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1395 v2i32, v2i64, NEONvshrn>;
1397 // VRSHL : Vector Rounding Shift
1398 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1399 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1400 // VRSHR : Vector Rounding Shift Right
1401 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1402 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1404 // VRSHRN : Vector Rounding Shift Right and Narrow
1405 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1406 v8i8, v8i16, NEONvrshrn>;
1407 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1408 v4i16, v4i32, NEONvrshrn>;
1409 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1410 v2i32, v2i64, NEONvrshrn>;
1412 // VQSHL : Vector Saturating Shift
1413 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1414 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1415 // VQSHL : Vector Saturating Shift Left (Immediate)
1416 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1417 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1418 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1419 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1421 // VQSHRN : Vector Saturating Shift Right and Narrow
1422 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1423 v8i8, v8i16, NEONvqshrns>;
1424 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1425 v4i16, v4i32, NEONvqshrns>;
1426 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1427 v2i32, v2i64, NEONvqshrns>;
1428 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1429 v8i8, v8i16, NEONvqshrnu>;
1430 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1431 v4i16, v4i32, NEONvqshrnu>;
1432 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1433 v2i32, v2i64, NEONvqshrnu>;
1435 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1436 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1437 v8i8, v8i16, NEONvqshrnsu>;
1438 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1439 v4i16, v4i32, NEONvqshrnsu>;
1440 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1441 v2i32, v2i64, NEONvqshrnsu>;
1443 // VQRSHL : Vector Saturating Rounding Shift
1444 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1445 int_arm_neon_vqrshifts, 0>;
1446 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1447 int_arm_neon_vqrshiftu, 0>;
1449 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1450 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1451 v8i8, v8i16, NEONvqrshrns>;
1452 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1453 v4i16, v4i32, NEONvqrshrns>;
1454 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1455 v2i32, v2i64, NEONvqrshrns>;
1456 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1457 v8i8, v8i16, NEONvqrshrnu>;
1458 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1459 v4i16, v4i32, NEONvqrshrnu>;
1460 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1461 v2i32, v2i64, NEONvqrshrnu>;
1463 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1464 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1465 v8i8, v8i16, NEONvqrshrnsu>;
1466 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1467 v4i16, v4i32, NEONvqrshrnsu>;
1468 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1469 v2i32, v2i64, NEONvqrshrnsu>;
1471 // VSRA : Vector Shift Right and Accumulate
1472 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1473 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1474 // VRSRA : Vector Rounding Shift Right and Accumulate
1475 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1476 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1478 // VSLI : Vector Shift Left and Insert
1479 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1480 // VSRI : Vector Shift Right and Insert
1481 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1483 // Vector Absolute and Saturating Absolute.
1485 // VABS : Vector Absolute Value
1486 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1488 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1489 v2f32, v2f32, int_arm_neon_vabs>;
1490 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1491 v4f32, v4f32, int_arm_neon_vabs>;
1493 // VQABS : Vector Saturating Absolute Value
1494 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1495 int_arm_neon_vqabs>;
1499 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1500 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1502 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1503 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1505 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1506 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1507 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1508 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1510 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1511 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1513 // VNEG : Vector Negate
1514 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1515 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1516 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1517 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1518 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1519 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1521 // VNEG : Vector Negate (floating-point)
1522 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1523 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1524 "vneg.f32\t$dst, $src", "",
1525 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1526 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1527 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1528 "vneg.f32\t$dst, $src", "",
1529 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1531 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1532 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1533 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1534 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1535 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1536 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1538 // VQNEG : Vector Saturating Negate
1539 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1540 int_arm_neon_vqneg>;
1542 // Vector Bit Counting Operations.
1544 // VCLS : Vector Count Leading Sign Bits
1545 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1547 // VCLZ : Vector Count Leading Zeros
1548 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1550 // VCNT : Vector Count One Bits
1551 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1552 v8i8, v8i8, int_arm_neon_vcnt>;
1553 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1554 v16i8, v16i8, int_arm_neon_vcnt>;
1556 // Vector Move Operations.
1558 // VMOV : Vector Move (Register)
1560 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1561 NoItinerary, "vmov\t$dst, $src", "", []>;
1562 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1563 NoItinerary, "vmov\t$dst, $src", "", []>;
1565 // VMOV : Vector Move (Immediate)
1567 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1568 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1569 return ARM::getVMOVImm(N, 1, *CurDAG);
1571 def vmovImm8 : PatLeaf<(build_vector), [{
1572 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1575 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1576 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1577 return ARM::getVMOVImm(N, 2, *CurDAG);
1579 def vmovImm16 : PatLeaf<(build_vector), [{
1580 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1581 }], VMOV_get_imm16>;
1583 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1584 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1585 return ARM::getVMOVImm(N, 4, *CurDAG);
1587 def vmovImm32 : PatLeaf<(build_vector), [{
1588 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1589 }], VMOV_get_imm32>;
1591 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1592 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1593 return ARM::getVMOVImm(N, 8, *CurDAG);
1595 def vmovImm64 : PatLeaf<(build_vector), [{
1596 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1597 }], VMOV_get_imm64>;
1599 // Note: Some of the cmode bits in the following VMOV instructions need to
1600 // be encoded based on the immed values.
1602 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1603 (ins i8imm:$SIMM), NoItinerary,
1604 "vmov.i8\t$dst, $SIMM", "",
1605 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1606 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1607 (ins i8imm:$SIMM), NoItinerary,
1608 "vmov.i8\t$dst, $SIMM", "",
1609 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1611 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1612 (ins i16imm:$SIMM), NoItinerary,
1613 "vmov.i16\t$dst, $SIMM", "",
1614 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1615 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1616 (ins i16imm:$SIMM), NoItinerary,
1617 "vmov.i16\t$dst, $SIMM", "",
1618 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1620 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1621 (ins i32imm:$SIMM), NoItinerary,
1622 "vmov.i32\t$dst, $SIMM", "",
1623 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1624 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1625 (ins i32imm:$SIMM), NoItinerary,
1626 "vmov.i32\t$dst, $SIMM", "",
1627 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1629 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1630 (ins i64imm:$SIMM), NoItinerary,
1631 "vmov.i64\t$dst, $SIMM", "",
1632 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1633 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1634 (ins i64imm:$SIMM), NoItinerary,
1635 "vmov.i64\t$dst, $SIMM", "",
1636 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1638 // VMOV : Vector Get Lane (move scalar to ARM core register)
1640 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1641 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1642 NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
1643 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1645 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1646 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1647 NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
1648 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1650 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1651 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1652 NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
1653 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1655 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1656 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1657 NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
1658 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1660 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1661 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1662 NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
1663 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1665 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1666 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1667 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1668 (DSubReg_i8_reg imm:$lane))),
1669 (SubReg_i8_lane imm:$lane))>;
1670 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1671 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1672 (DSubReg_i16_reg imm:$lane))),
1673 (SubReg_i16_lane imm:$lane))>;
1674 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1675 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1676 (DSubReg_i8_reg imm:$lane))),
1677 (SubReg_i8_lane imm:$lane))>;
1678 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1679 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1680 (DSubReg_i16_reg imm:$lane))),
1681 (SubReg_i16_lane imm:$lane))>;
1682 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1683 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1684 (DSubReg_i32_reg imm:$lane))),
1685 (SubReg_i32_lane imm:$lane))>;
1686 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
1687 (EXTRACT_SUBREG QPR:$src1, (SSubReg_f32_reg imm:$src2))>;
1688 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1689 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1690 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1691 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1694 // VMOV : Vector Set Lane (move ARM core register to scalar)
1696 let Constraints = "$src1 = $dst" in {
1697 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1698 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1699 NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
1700 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1701 GPR:$src2, imm:$lane))]>;
1702 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1703 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1704 NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
1705 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1706 GPR:$src2, imm:$lane))]>;
1707 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1708 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1709 NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
1710 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1711 GPR:$src2, imm:$lane))]>;
1713 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1714 (v16i8 (INSERT_SUBREG QPR:$src1,
1715 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1716 (DSubReg_i8_reg imm:$lane))),
1717 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1718 (DSubReg_i8_reg imm:$lane)))>;
1719 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1720 (v8i16 (INSERT_SUBREG QPR:$src1,
1721 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1722 (DSubReg_i16_reg imm:$lane))),
1723 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1724 (DSubReg_i16_reg imm:$lane)))>;
1725 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1726 (v4i32 (INSERT_SUBREG QPR:$src1,
1727 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1728 (DSubReg_i32_reg imm:$lane))),
1729 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1730 (DSubReg_i32_reg imm:$lane)))>;
1732 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
1733 (INSERT_SUBREG QPR:$src1, SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
1735 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1736 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1737 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1738 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1740 // VDUP : Vector Duplicate (from ARM core register to all elements)
1742 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
1743 (vector_shuffle node:$lhs, node:$rhs), [{
1744 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1745 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
1748 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1749 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1750 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1751 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1752 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1753 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1754 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1755 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1757 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1758 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1759 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1760 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1761 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1762 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1764 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1765 NoItinerary, "vdup", ".32\t$dst, $src",
1766 [(set DPR:$dst, (v2f32 (splat_lo
1768 (f32 (bitconvert GPR:$src))),
1770 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1771 NoItinerary, "vdup", ".32\t$dst, $src",
1772 [(set QPR:$dst, (v4f32 (splat_lo
1774 (f32 (bitconvert GPR:$src))),
1777 // VDUP : Vector Duplicate Lane (from scalar to all elements)
1779 def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
1780 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1781 return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
1784 def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
1785 (vector_shuffle node:$lhs, node:$rhs), [{
1786 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1787 return SVOp->isSplat();
1788 }], SHUFFLE_get_splat_lane>;
1790 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1791 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1792 (outs DPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
1793 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1794 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>;
1796 // vector_shuffle requires that the source and destination types match, so
1797 // VDUP to a 128-bit result uses a target-specific VDUPLANEQ node.
1798 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1799 ValueType ResTy, ValueType OpTy>
1800 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1801 (outs QPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
1802 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1803 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>;
1805 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1806 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1807 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1808 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1809 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1810 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1811 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1812 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1814 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
1815 (outs DPR:$dst), (ins SPR:$src),
1816 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1817 [(set DPR:$dst, (v2f32 (splat_lo
1818 (scalar_to_vector SPR:$src),
1821 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
1822 (outs QPR:$dst), (ins SPR:$src),
1823 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1824 [(set QPR:$dst, (v4f32 (splat_lo
1825 (scalar_to_vector SPR:$src),
1828 // VMOVN : Vector Narrowing Move
1829 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1830 int_arm_neon_vmovn>;
1831 // VQMOVN : Vector Saturating Narrowing Move
1832 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1833 int_arm_neon_vqmovns>;
1834 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1835 int_arm_neon_vqmovnu>;
1836 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1837 int_arm_neon_vqmovnsu>;
1838 // VMOVL : Vector Lengthening Move
1839 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1840 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1842 // Vector Conversions.
1844 // VCVT : Vector Convert Between Floating-Point and Integers
1845 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1846 v2i32, v2f32, fp_to_sint>;
1847 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1848 v2i32, v2f32, fp_to_uint>;
1849 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1850 v2f32, v2i32, sint_to_fp>;
1851 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1852 v2f32, v2i32, uint_to_fp>;
1854 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1855 v4i32, v4f32, fp_to_sint>;
1856 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1857 v4i32, v4f32, fp_to_uint>;
1858 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1859 v4f32, v4i32, sint_to_fp>;
1860 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1861 v4f32, v4i32, uint_to_fp>;
1863 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1864 // Note: Some of the opcode bits in the following VCVT instructions need to
1865 // be encoded based on the immed values.
1866 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1867 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1868 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1869 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1870 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1871 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1872 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1873 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1875 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1876 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1877 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1878 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1879 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1880 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1881 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1882 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1884 // VREV : Vector Reverse
1886 def vrev64_shuffle : PatFrag<(ops node:$in),
1887 (vector_shuffle node:$in, undef), [{
1888 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1889 return ARM::isVREVMask(SVOp, 64);
1892 def vrev32_shuffle : PatFrag<(ops node:$in),
1893 (vector_shuffle node:$in, undef), [{
1894 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1895 return ARM::isVREVMask(SVOp, 32);
1898 def vrev16_shuffle : PatFrag<(ops node:$in),
1899 (vector_shuffle node:$in, undef), [{
1900 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1901 return ARM::isVREVMask(SVOp, 16);
1904 // VREV64 : Vector Reverse elements within 64-bit doublewords
1906 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1907 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1908 (ins DPR:$src), NoItinerary,
1909 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1910 [(set DPR:$dst, (Ty (vrev64_shuffle (Ty DPR:$src))))]>;
1911 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1912 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1913 (ins QPR:$src), NoItinerary,
1914 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1915 [(set QPR:$dst, (Ty (vrev64_shuffle (Ty QPR:$src))))]>;
1917 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1918 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1919 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1920 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1922 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1923 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1924 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1925 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1927 // VREV32 : Vector Reverse elements within 32-bit words
1929 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1930 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1931 (ins DPR:$src), NoItinerary,
1932 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1933 [(set DPR:$dst, (Ty (vrev32_shuffle (Ty DPR:$src))))]>;
1934 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1935 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1936 (ins QPR:$src), NoItinerary,
1937 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1938 [(set QPR:$dst, (Ty (vrev32_shuffle (Ty QPR:$src))))]>;
1940 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1941 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1943 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1944 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1946 // VREV16 : Vector Reverse elements within 16-bit halfwords
1948 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1949 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1950 (ins DPR:$src), NoItinerary,
1951 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1952 [(set DPR:$dst, (Ty (vrev16_shuffle (Ty DPR:$src))))]>;
1953 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1954 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1955 (ins QPR:$src), NoItinerary,
1956 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1957 [(set QPR:$dst, (Ty (vrev16_shuffle (Ty QPR:$src))))]>;
1959 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1960 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1962 // VTRN : Vector Transpose
1964 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
1965 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
1966 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
1968 def VTRNq8 : N2VQShuffle<0b00, 0b00001, "vtrn.8">;
1969 def VTRNq16 : N2VQShuffle<0b01, 0b00001, "vtrn.16">;
1970 def VTRNq32 : N2VQShuffle<0b10, 0b00001, "vtrn.32">;
1972 // VUZP : Vector Unzip (Deinterleave)
1974 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
1975 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
1976 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
1978 def VUZPq8 : N2VQShuffle<0b00, 0b00010, "vuzp.8">;
1979 def VUZPq16 : N2VQShuffle<0b01, 0b00010, "vuzp.16">;
1980 def VUZPq32 : N2VQShuffle<0b10, 0b00010, "vuzp.32">;
1982 // VZIP : Vector Zip (Interleave)
1984 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
1985 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
1986 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
1988 def VZIPq8 : N2VQShuffle<0b00, 0b00011, "vzip.8">;
1989 def VZIPq16 : N2VQShuffle<0b01, 0b00011, "vzip.16">;
1990 def VZIPq32 : N2VQShuffle<0b10, 0b00011, "vzip.32">;
1992 //===----------------------------------------------------------------------===//
1993 // NEON instructions for single-precision FP math
1994 //===----------------------------------------------------------------------===//
1996 // These need separate instructions because they must use DPR_VFP2 register
1997 // class which have SPR sub-registers.
1999 // Vector Add Operations used for single-precision FP
2000 let neverHasSideEffects = 1 in
2001 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
2002 def : N3VDsPat<fadd, VADDfd_sfp>;
2004 // Vector Sub Operations used for single-precision FP
2005 let neverHasSideEffects = 1 in
2006 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
2007 def : N3VDsPat<fsub, VSUBfd_sfp>;
2009 // Vector Multiply Operations used for single-precision FP
2010 let neverHasSideEffects = 1 in
2011 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
2012 def : N3VDsPat<fmul, VMULfd_sfp>;
2014 // Vector Multiply-Accumulate/Subtract used for single-precision FP
2015 let neverHasSideEffects = 1 in
2016 def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32,fmul,fadd>;
2017 def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
2019 let neverHasSideEffects = 1 in
2020 def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32,fmul,fsub>;
2021 def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
2023 // Vector Absolute used for single-precision FP
2024 let neverHasSideEffects = 1 in
2025 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
2026 v2f32, v2f32, int_arm_neon_vabs>;
2027 def : N2VDIntsPat<fabs, VABSfd_sfp>;
2029 // Vector Negate used for single-precision FP
2030 let neverHasSideEffects = 1 in
2031 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2032 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
2033 "vneg.f32\t$dst, $src", "", []>;
2034 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
2036 // Vector Convert between single-precision FP and integer
2037 let neverHasSideEffects = 1 in
2038 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2039 v2i32, v2f32, fp_to_sint>;
2040 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
2042 let neverHasSideEffects = 1 in
2043 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2044 v2i32, v2f32, fp_to_uint>;
2045 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
2047 let neverHasSideEffects = 1 in
2048 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2049 v2f32, v2i32, sint_to_fp>;
2050 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
2052 let neverHasSideEffects = 1 in
2053 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2054 v2f32, v2i32, uint_to_fp>;
2055 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
2057 //===----------------------------------------------------------------------===//
2058 // Non-Instruction Patterns
2059 //===----------------------------------------------------------------------===//
2062 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
2063 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
2064 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
2065 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
2066 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
2067 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
2068 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
2069 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
2070 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
2071 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
2072 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
2073 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
2074 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
2075 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
2076 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
2077 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
2078 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
2079 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
2080 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
2081 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
2082 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
2083 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
2084 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
2085 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
2086 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
2087 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
2088 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
2089 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
2090 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
2091 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
2093 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
2094 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
2095 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
2096 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
2097 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
2098 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
2099 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
2100 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
2101 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
2102 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
2103 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
2104 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
2105 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
2106 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
2107 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
2108 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
2109 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
2110 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
2111 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
2112 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
2113 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
2114 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
2115 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
2116 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
2117 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
2118 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
2119 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
2120 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
2121 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
2122 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;