1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
66 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
68 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
69 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
74 SDTCisInt<0>, SDTCisVT<1, i32>]>;
76 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
77 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
84 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
85 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
86 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
87 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
89 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
90 [SDNPHasChain, SDNPOutGlue]>;
91 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
92 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
94 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
95 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
97 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
98 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
100 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
101 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
104 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
105 [SDNPHasChain, SDNPOptInGlue]>;
107 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
110 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
113 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
115 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
118 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
121 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
124 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
125 [SDNPOutGlue, SDNPCommutative]>;
127 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
129 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
130 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
131 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
133 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
135 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
136 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
137 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
139 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
140 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
141 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
142 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
143 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
145 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
147 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
149 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
150 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
152 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
154 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
158 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
160 //===----------------------------------------------------------------------===//
161 // ARM Instruction Predicate Definitions.
163 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
164 AssemblerPredicate<"HasV4TOps">;
165 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
166 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
167 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
168 AssemblerPredicate<"HasV5TEOps">;
169 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
170 AssemblerPredicate<"HasV6Ops">;
171 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
172 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
173 AssemblerPredicate<"HasV6T2Ops">;
174 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
175 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
176 AssemblerPredicate<"HasV7Ops">;
177 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
178 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
179 AssemblerPredicate<"FeatureVFP2">;
180 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
181 AssemblerPredicate<"FeatureVFP3">;
182 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
183 AssemblerPredicate<"FeatureVFP4">;
184 def HasNEON : Predicate<"Subtarget->hasNEON()">,
185 AssemblerPredicate<"FeatureNEON">;
186 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
187 AssemblerPredicate<"FeatureFP16">;
188 def HasDivide : Predicate<"Subtarget->hasDivide()">,
189 AssemblerPredicate<"FeatureHWDiv">;
190 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
191 AssemblerPredicate<"FeatureT2XtPk">;
192 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
193 AssemblerPredicate<"FeatureDSPThumb2">;
194 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
195 AssemblerPredicate<"FeatureDB">;
196 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
197 AssemblerPredicate<"FeatureMP">;
198 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
199 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
200 def IsThumb : Predicate<"Subtarget->isThumb()">,
201 AssemblerPredicate<"ModeThumb">;
202 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
203 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
204 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
205 def IsMClass : Predicate<"Subtarget->isMClass()">,
206 AssemblerPredicate<"FeatureMClass">;
207 def IsARClass : Predicate<"!Subtarget->isMClass()">,
208 AssemblerPredicate<"!FeatureMClass">;
209 def IsARM : Predicate<"!Subtarget->isThumb()">,
210 AssemblerPredicate<"!ModeThumb">;
211 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
212 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
213 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
215 // FIXME: Eventually this will be just "hasV6T2Ops".
216 def UseMovt : Predicate<"Subtarget->useMovt()">;
217 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
218 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
220 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
221 // But only select them if more precision in FP computation is allowed.
222 // Do not use them for Darwin platforms.
223 def UseFusedMAC : Predicate<"!TM.Options.NoExcessFPPrecision && "
224 "!Subtarget->isTargetDarwin()">;
225 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
226 "Subtarget->isTargetDarwin()">;
228 //===----------------------------------------------------------------------===//
229 // ARM Flag Definitions.
231 class RegConstraint<string C> {
232 string Constraints = C;
235 //===----------------------------------------------------------------------===//
236 // ARM specific transformation functions and pattern fragments.
239 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
240 // so_imm_neg def below.
241 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
242 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
245 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
246 // so_imm_not def below.
247 def so_imm_not_XFORM : SDNodeXForm<imm, [{
248 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
251 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
252 def imm16_31 : ImmLeaf<i32, [{
253 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
256 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
257 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
258 int64_t Value = -(int)N->getZExtValue();
259 return Value && ARM_AM::getSOImmVal(Value) != -1;
260 }], so_imm_neg_XFORM> {
261 let ParserMatchClass = so_imm_neg_asmoperand;
264 // Note: this pattern doesn't require an encoder method and such, as it's
265 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
266 // is handled by the destination instructions, which use so_imm.
267 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
268 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
269 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
270 }], so_imm_not_XFORM> {
271 let ParserMatchClass = so_imm_not_asmoperand;
274 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
275 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
276 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
279 /// Split a 32-bit immediate into two 16 bit parts.
280 def hi16 : SDNodeXForm<imm, [{
281 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
284 def lo16AllZero : PatLeaf<(i32 imm), [{
285 // Returns true if all low 16-bits are 0.
286 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
289 class BinOpWithFlagFrag<dag res> :
290 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
291 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
292 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
294 // An 'and' node with a single use.
295 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
296 return N->hasOneUse();
299 // An 'xor' node with a single use.
300 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
301 return N->hasOneUse();
304 // An 'fmul' node with a single use.
305 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
306 return N->hasOneUse();
309 // An 'fadd' node which checks for single non-hazardous use.
310 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
311 return hasNoVMLxHazardUse(N);
314 // An 'fsub' node which checks for single non-hazardous use.
315 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
316 return hasNoVMLxHazardUse(N);
319 //===----------------------------------------------------------------------===//
320 // Operand Definitions.
323 // Immediate operands with a shared generic asm render method.
324 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
327 // FIXME: rename brtarget to t2_brtarget
328 def brtarget : Operand<OtherVT> {
329 let EncoderMethod = "getBranchTargetOpValue";
330 let OperandType = "OPERAND_PCREL";
331 let DecoderMethod = "DecodeT2BROperand";
334 // FIXME: get rid of this one?
335 def uncondbrtarget : Operand<OtherVT> {
336 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
337 let OperandType = "OPERAND_PCREL";
340 // Branch target for ARM. Handles conditional/unconditional
341 def br_target : Operand<OtherVT> {
342 let EncoderMethod = "getARMBranchTargetOpValue";
343 let OperandType = "OPERAND_PCREL";
347 // FIXME: rename bltarget to t2_bl_target?
348 def bltarget : Operand<i32> {
349 // Encoded the same as branch targets.
350 let EncoderMethod = "getBranchTargetOpValue";
351 let OperandType = "OPERAND_PCREL";
354 // Call target for ARM. Handles conditional/unconditional
355 // FIXME: rename bl_target to t2_bltarget?
356 def bl_target : Operand<i32> {
357 let EncoderMethod = "getARMBLTargetOpValue";
358 let OperandType = "OPERAND_PCREL";
361 def blx_target : Operand<i32> {
362 let EncoderMethod = "getARMBLXTargetOpValue";
363 let OperandType = "OPERAND_PCREL";
366 // A list of registers separated by comma. Used by load/store multiple.
367 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
368 def reglist : Operand<i32> {
369 let EncoderMethod = "getRegisterListOpValue";
370 let ParserMatchClass = RegListAsmOperand;
371 let PrintMethod = "printRegisterList";
372 let DecoderMethod = "DecodeRegListOperand";
375 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
376 def dpr_reglist : Operand<i32> {
377 let EncoderMethod = "getRegisterListOpValue";
378 let ParserMatchClass = DPRRegListAsmOperand;
379 let PrintMethod = "printRegisterList";
380 let DecoderMethod = "DecodeDPRRegListOperand";
383 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
384 def spr_reglist : Operand<i32> {
385 let EncoderMethod = "getRegisterListOpValue";
386 let ParserMatchClass = SPRRegListAsmOperand;
387 let PrintMethod = "printRegisterList";
388 let DecoderMethod = "DecodeSPRRegListOperand";
391 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
392 def cpinst_operand : Operand<i32> {
393 let PrintMethod = "printCPInstOperand";
397 def pclabel : Operand<i32> {
398 let PrintMethod = "printPCLabel";
401 // ADR instruction labels.
402 def adrlabel : Operand<i32> {
403 let EncoderMethod = "getAdrLabelOpValue";
406 def neon_vcvt_imm32 : Operand<i32> {
407 let EncoderMethod = "getNEONVcvtImm32OpValue";
408 let DecoderMethod = "DecodeVCVTImmOperand";
411 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
412 def rot_imm_XFORM: SDNodeXForm<imm, [{
413 switch (N->getZExtValue()){
415 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
416 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
417 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
418 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
421 def RotImmAsmOperand : AsmOperandClass {
423 let ParserMethod = "parseRotImm";
425 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
426 int32_t v = N->getZExtValue();
427 return v == 8 || v == 16 || v == 24; }],
429 let PrintMethod = "printRotImmOperand";
430 let ParserMatchClass = RotImmAsmOperand;
433 // shift_imm: An integer that encodes a shift amount and the type of shift
434 // (asr or lsl). The 6-bit immediate encodes as:
437 // {4-0} imm5 shift amount.
438 // asr #32 encoded as imm5 == 0.
439 def ShifterImmAsmOperand : AsmOperandClass {
440 let Name = "ShifterImm";
441 let ParserMethod = "parseShifterImm";
443 def shift_imm : Operand<i32> {
444 let PrintMethod = "printShiftImmOperand";
445 let ParserMatchClass = ShifterImmAsmOperand;
448 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
449 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
450 def so_reg_reg : Operand<i32>, // reg reg imm
451 ComplexPattern<i32, 3, "SelectRegShifterOperand",
452 [shl, srl, sra, rotr]> {
453 let EncoderMethod = "getSORegRegOpValue";
454 let PrintMethod = "printSORegRegOperand";
455 let DecoderMethod = "DecodeSORegRegOperand";
456 let ParserMatchClass = ShiftedRegAsmOperand;
457 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
460 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
461 def so_reg_imm : Operand<i32>, // reg imm
462 ComplexPattern<i32, 2, "SelectImmShifterOperand",
463 [shl, srl, sra, rotr]> {
464 let EncoderMethod = "getSORegImmOpValue";
465 let PrintMethod = "printSORegImmOperand";
466 let DecoderMethod = "DecodeSORegImmOperand";
467 let ParserMatchClass = ShiftedImmAsmOperand;
468 let MIOperandInfo = (ops GPR, i32imm);
471 // FIXME: Does this need to be distinct from so_reg?
472 def shift_so_reg_reg : Operand<i32>, // reg reg imm
473 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
474 [shl,srl,sra,rotr]> {
475 let EncoderMethod = "getSORegRegOpValue";
476 let PrintMethod = "printSORegRegOperand";
477 let DecoderMethod = "DecodeSORegRegOperand";
478 let ParserMatchClass = ShiftedRegAsmOperand;
479 let MIOperandInfo = (ops GPR, GPR, i32imm);
482 // FIXME: Does this need to be distinct from so_reg?
483 def shift_so_reg_imm : Operand<i32>, // reg reg imm
484 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
485 [shl,srl,sra,rotr]> {
486 let EncoderMethod = "getSORegImmOpValue";
487 let PrintMethod = "printSORegImmOperand";
488 let DecoderMethod = "DecodeSORegImmOperand";
489 let ParserMatchClass = ShiftedImmAsmOperand;
490 let MIOperandInfo = (ops GPR, i32imm);
494 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
495 // 8-bit immediate rotated by an arbitrary number of bits.
496 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
497 def so_imm : Operand<i32>, ImmLeaf<i32, [{
498 return ARM_AM::getSOImmVal(Imm) != -1;
500 let EncoderMethod = "getSOImmOpValue";
501 let ParserMatchClass = SOImmAsmOperand;
502 let DecoderMethod = "DecodeSOImmOperand";
505 // Break so_imm's up into two pieces. This handles immediates with up to 16
506 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
507 // get the first/second pieces.
508 def so_imm2part : PatLeaf<(imm), [{
509 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
512 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
514 def arm_i32imm : PatLeaf<(imm), [{
515 if (Subtarget->hasV6T2Ops())
517 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
520 /// imm0_1 predicate - Immediate in the range [0,1].
521 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
522 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
524 /// imm0_3 predicate - Immediate in the range [0,3].
525 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
526 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
528 /// imm0_7 predicate - Immediate in the range [0,7].
529 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
530 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
531 return Imm >= 0 && Imm < 8;
533 let ParserMatchClass = Imm0_7AsmOperand;
536 /// imm8 predicate - Immediate is exactly 8.
537 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
538 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
539 let ParserMatchClass = Imm8AsmOperand;
542 /// imm16 predicate - Immediate is exactly 16.
543 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
544 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
545 let ParserMatchClass = Imm16AsmOperand;
548 /// imm32 predicate - Immediate is exactly 32.
549 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
550 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
551 let ParserMatchClass = Imm32AsmOperand;
554 /// imm1_7 predicate - Immediate in the range [1,7].
555 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
556 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
557 let ParserMatchClass = Imm1_7AsmOperand;
560 /// imm1_15 predicate - Immediate in the range [1,15].
561 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
562 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
563 let ParserMatchClass = Imm1_15AsmOperand;
566 /// imm1_31 predicate - Immediate in the range [1,31].
567 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
568 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
569 let ParserMatchClass = Imm1_31AsmOperand;
572 /// imm0_15 predicate - Immediate in the range [0,15].
573 def Imm0_15AsmOperand: ImmAsmOperand { let Name = "Imm0_15"; }
574 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
575 return Imm >= 0 && Imm < 16;
577 let ParserMatchClass = Imm0_15AsmOperand;
580 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
581 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
582 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
583 return Imm >= 0 && Imm < 32;
585 let ParserMatchClass = Imm0_31AsmOperand;
588 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
589 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
590 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
591 return Imm >= 0 && Imm < 32;
593 let ParserMatchClass = Imm0_32AsmOperand;
596 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
597 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
598 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
599 return Imm >= 0 && Imm < 64;
601 let ParserMatchClass = Imm0_63AsmOperand;
604 /// imm0_255 predicate - Immediate in the range [0,255].
605 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
606 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
607 let ParserMatchClass = Imm0_255AsmOperand;
610 /// imm0_65535 - An immediate is in the range [0.65535].
611 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
612 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
613 return Imm >= 0 && Imm < 65536;
615 let ParserMatchClass = Imm0_65535AsmOperand;
618 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
619 // a relocatable expression.
621 // FIXME: This really needs a Thumb version separate from the ARM version.
622 // While the range is the same, and can thus use the same match class,
623 // the encoding is different so it should have a different encoder method.
624 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
625 def imm0_65535_expr : Operand<i32> {
626 let EncoderMethod = "getHiLo16ImmOpValue";
627 let ParserMatchClass = Imm0_65535ExprAsmOperand;
630 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
631 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
632 def imm24b : Operand<i32>, ImmLeaf<i32, [{
633 return Imm >= 0 && Imm <= 0xffffff;
635 let ParserMatchClass = Imm24bitAsmOperand;
639 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
641 def BitfieldAsmOperand : AsmOperandClass {
642 let Name = "Bitfield";
643 let ParserMethod = "parseBitfield";
646 def bf_inv_mask_imm : Operand<i32>,
648 return ARM::isBitFieldInvertedMask(N->getZExtValue());
650 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
651 let PrintMethod = "printBitfieldInvMaskImmOperand";
652 let DecoderMethod = "DecodeBitfieldMaskOperand";
653 let ParserMatchClass = BitfieldAsmOperand;
656 def imm1_32_XFORM: SDNodeXForm<imm, [{
657 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
659 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
660 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
661 uint64_t Imm = N->getZExtValue();
662 return Imm > 0 && Imm <= 32;
665 let PrintMethod = "printImmPlusOneOperand";
666 let ParserMatchClass = Imm1_32AsmOperand;
669 def imm1_16_XFORM: SDNodeXForm<imm, [{
670 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
672 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
673 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
675 let PrintMethod = "printImmPlusOneOperand";
676 let ParserMatchClass = Imm1_16AsmOperand;
679 // Define ARM specific addressing modes.
680 // addrmode_imm12 := reg +/- imm12
682 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
683 def addrmode_imm12 : Operand<i32>,
684 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
685 // 12-bit immediate operand. Note that instructions using this encode
686 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
687 // immediate values are as normal.
689 let EncoderMethod = "getAddrModeImm12OpValue";
690 let PrintMethod = "printAddrModeImm12Operand";
691 let DecoderMethod = "DecodeAddrModeImm12Operand";
692 let ParserMatchClass = MemImm12OffsetAsmOperand;
693 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
695 // ldst_so_reg := reg +/- reg shop imm
697 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
698 def ldst_so_reg : Operand<i32>,
699 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
700 let EncoderMethod = "getLdStSORegOpValue";
701 // FIXME: Simplify the printer
702 let PrintMethod = "printAddrMode2Operand";
703 let DecoderMethod = "DecodeSORegMemOperand";
704 let ParserMatchClass = MemRegOffsetAsmOperand;
705 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
708 // postidx_imm8 := +/- [0,255]
711 // {8} 1 is imm8 is non-negative. 0 otherwise.
712 // {7-0} [0,255] imm8 value.
713 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
714 def postidx_imm8 : Operand<i32> {
715 let PrintMethod = "printPostIdxImm8Operand";
716 let ParserMatchClass = PostIdxImm8AsmOperand;
717 let MIOperandInfo = (ops i32imm);
720 // postidx_imm8s4 := +/- [0,1020]
723 // {8} 1 is imm8 is non-negative. 0 otherwise.
724 // {7-0} [0,255] imm8 value, scaled by 4.
725 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
726 def postidx_imm8s4 : Operand<i32> {
727 let PrintMethod = "printPostIdxImm8s4Operand";
728 let ParserMatchClass = PostIdxImm8s4AsmOperand;
729 let MIOperandInfo = (ops i32imm);
733 // postidx_reg := +/- reg
735 def PostIdxRegAsmOperand : AsmOperandClass {
736 let Name = "PostIdxReg";
737 let ParserMethod = "parsePostIdxReg";
739 def postidx_reg : Operand<i32> {
740 let EncoderMethod = "getPostIdxRegOpValue";
741 let DecoderMethod = "DecodePostIdxReg";
742 let PrintMethod = "printPostIdxRegOperand";
743 let ParserMatchClass = PostIdxRegAsmOperand;
744 let MIOperandInfo = (ops GPRnopc, i32imm);
748 // addrmode2 := reg +/- imm12
749 // := reg +/- reg shop imm
751 // FIXME: addrmode2 should be refactored the rest of the way to always
752 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
753 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
754 def addrmode2 : Operand<i32>,
755 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
756 let EncoderMethod = "getAddrMode2OpValue";
757 let PrintMethod = "printAddrMode2Operand";
758 let ParserMatchClass = AddrMode2AsmOperand;
759 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
762 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
763 let Name = "PostIdxRegShifted";
764 let ParserMethod = "parsePostIdxReg";
766 def am2offset_reg : Operand<i32>,
767 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
768 [], [SDNPWantRoot]> {
769 let EncoderMethod = "getAddrMode2OffsetOpValue";
770 let PrintMethod = "printAddrMode2OffsetOperand";
771 // When using this for assembly, it's always as a post-index offset.
772 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
773 let MIOperandInfo = (ops GPRnopc, i32imm);
776 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
777 // the GPR is purely vestigal at this point.
778 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
779 def am2offset_imm : Operand<i32>,
780 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
781 [], [SDNPWantRoot]> {
782 let EncoderMethod = "getAddrMode2OffsetOpValue";
783 let PrintMethod = "printAddrMode2OffsetOperand";
784 let ParserMatchClass = AM2OffsetImmAsmOperand;
785 let MIOperandInfo = (ops GPRnopc, i32imm);
789 // addrmode3 := reg +/- reg
790 // addrmode3 := reg +/- imm8
792 // FIXME: split into imm vs. reg versions.
793 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
794 def addrmode3 : Operand<i32>,
795 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
796 let EncoderMethod = "getAddrMode3OpValue";
797 let PrintMethod = "printAddrMode3Operand";
798 let ParserMatchClass = AddrMode3AsmOperand;
799 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
802 // FIXME: split into imm vs. reg versions.
803 // FIXME: parser method to handle +/- register.
804 def AM3OffsetAsmOperand : AsmOperandClass {
805 let Name = "AM3Offset";
806 let ParserMethod = "parseAM3Offset";
808 def am3offset : Operand<i32>,
809 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
810 [], [SDNPWantRoot]> {
811 let EncoderMethod = "getAddrMode3OffsetOpValue";
812 let PrintMethod = "printAddrMode3OffsetOperand";
813 let ParserMatchClass = AM3OffsetAsmOperand;
814 let MIOperandInfo = (ops GPR, i32imm);
817 // ldstm_mode := {ia, ib, da, db}
819 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
820 let EncoderMethod = "getLdStmModeOpValue";
821 let PrintMethod = "printLdStmModeOperand";
824 // addrmode5 := reg +/- imm8*4
826 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
827 def addrmode5 : Operand<i32>,
828 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
829 let PrintMethod = "printAddrMode5Operand";
830 let EncoderMethod = "getAddrMode5OpValue";
831 let DecoderMethod = "DecodeAddrMode5Operand";
832 let ParserMatchClass = AddrMode5AsmOperand;
833 let MIOperandInfo = (ops GPR:$base, i32imm);
836 // addrmode6 := reg with optional alignment
838 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
839 def addrmode6 : Operand<i32>,
840 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
841 let PrintMethod = "printAddrMode6Operand";
842 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
843 let EncoderMethod = "getAddrMode6AddressOpValue";
844 let DecoderMethod = "DecodeAddrMode6Operand";
845 let ParserMatchClass = AddrMode6AsmOperand;
848 def am6offset : Operand<i32>,
849 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
850 [], [SDNPWantRoot]> {
851 let PrintMethod = "printAddrMode6OffsetOperand";
852 let MIOperandInfo = (ops GPR);
853 let EncoderMethod = "getAddrMode6OffsetOpValue";
854 let DecoderMethod = "DecodeGPRRegisterClass";
857 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
858 // (single element from one lane) for size 32.
859 def addrmode6oneL32 : Operand<i32>,
860 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
861 let PrintMethod = "printAddrMode6Operand";
862 let MIOperandInfo = (ops GPR:$addr, i32imm);
863 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
866 // Special version of addrmode6 to handle alignment encoding for VLD-dup
867 // instructions, specifically VLD4-dup.
868 def addrmode6dup : Operand<i32>,
869 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
870 let PrintMethod = "printAddrMode6Operand";
871 let MIOperandInfo = (ops GPR:$addr, i32imm);
872 let EncoderMethod = "getAddrMode6DupAddressOpValue";
873 // FIXME: This is close, but not quite right. The alignment specifier is
875 let ParserMatchClass = AddrMode6AsmOperand;
878 // addrmodepc := pc + reg
880 def addrmodepc : Operand<i32>,
881 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
882 let PrintMethod = "printAddrModePCOperand";
883 let MIOperandInfo = (ops GPR, i32imm);
886 // addr_offset_none := reg
888 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
889 def addr_offset_none : Operand<i32>,
890 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
891 let PrintMethod = "printAddrMode7Operand";
892 let DecoderMethod = "DecodeAddrMode7Operand";
893 let ParserMatchClass = MemNoOffsetAsmOperand;
894 let MIOperandInfo = (ops GPR:$base);
897 def nohash_imm : Operand<i32> {
898 let PrintMethod = "printNoHashImmediate";
901 def CoprocNumAsmOperand : AsmOperandClass {
902 let Name = "CoprocNum";
903 let ParserMethod = "parseCoprocNumOperand";
905 def p_imm : Operand<i32> {
906 let PrintMethod = "printPImmediate";
907 let ParserMatchClass = CoprocNumAsmOperand;
908 let DecoderMethod = "DecodeCoprocessor";
911 def pf_imm : Operand<i32> {
912 let PrintMethod = "printPImmediate";
913 let ParserMatchClass = CoprocNumAsmOperand;
916 def CoprocRegAsmOperand : AsmOperandClass {
917 let Name = "CoprocReg";
918 let ParserMethod = "parseCoprocRegOperand";
920 def c_imm : Operand<i32> {
921 let PrintMethod = "printCImmediate";
922 let ParserMatchClass = CoprocRegAsmOperand;
924 def CoprocOptionAsmOperand : AsmOperandClass {
925 let Name = "CoprocOption";
926 let ParserMethod = "parseCoprocOptionOperand";
928 def coproc_option_imm : Operand<i32> {
929 let PrintMethod = "printCoprocOptionImm";
930 let ParserMatchClass = CoprocOptionAsmOperand;
933 //===----------------------------------------------------------------------===//
935 include "ARMInstrFormats.td"
937 //===----------------------------------------------------------------------===//
938 // Multiclass helpers...
941 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
942 /// binop that produces a value.
943 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
944 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
945 PatFrag opnode, string baseOpc, bit Commutable = 0> {
946 // The register-immediate version is re-materializable. This is useful
947 // in particular for taking the address of a local.
948 let isReMaterializable = 1 in {
949 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
950 iii, opc, "\t$Rd, $Rn, $imm",
951 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
956 let Inst{19-16} = Rn;
957 let Inst{15-12} = Rd;
958 let Inst{11-0} = imm;
961 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
962 iir, opc, "\t$Rd, $Rn, $Rm",
963 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
968 let isCommutable = Commutable;
969 let Inst{19-16} = Rn;
970 let Inst{15-12} = Rd;
971 let Inst{11-4} = 0b00000000;
975 def rsi : AsI1<opcod, (outs GPR:$Rd),
976 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
977 iis, opc, "\t$Rd, $Rn, $shift",
978 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
983 let Inst{19-16} = Rn;
984 let Inst{15-12} = Rd;
985 let Inst{11-5} = shift{11-5};
987 let Inst{3-0} = shift{3-0};
990 def rsr : AsI1<opcod, (outs GPR:$Rd),
991 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
992 iis, opc, "\t$Rd, $Rn, $shift",
993 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
998 let Inst{19-16} = Rn;
999 let Inst{15-12} = Rd;
1000 let Inst{11-8} = shift{11-8};
1002 let Inst{6-5} = shift{6-5};
1004 let Inst{3-0} = shift{3-0};
1007 // Assembly aliases for optional destination operand when it's the same
1008 // as the source operand.
1009 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1010 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1011 so_imm:$imm, pred:$p,
1014 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1015 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1019 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1020 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1021 so_reg_imm:$shift, pred:$p,
1024 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1025 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1026 so_reg_reg:$shift, pred:$p,
1032 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1033 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1034 /// it is equivalent to the AsI1_bin_irs counterpart.
1035 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1036 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1037 PatFrag opnode, string baseOpc, bit Commutable = 0> {
1038 // The register-immediate version is re-materializable. This is useful
1039 // in particular for taking the address of a local.
1040 let isReMaterializable = 1 in {
1041 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1042 iii, opc, "\t$Rd, $Rn, $imm",
1043 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1048 let Inst{19-16} = Rn;
1049 let Inst{15-12} = Rd;
1050 let Inst{11-0} = imm;
1053 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1054 iir, opc, "\t$Rd, $Rn, $Rm",
1055 [/* pattern left blank */]> {
1059 let Inst{11-4} = 0b00000000;
1062 let Inst{15-12} = Rd;
1063 let Inst{19-16} = Rn;
1066 def rsi : AsI1<opcod, (outs GPR:$Rd),
1067 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1068 iis, opc, "\t$Rd, $Rn, $shift",
1069 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1074 let Inst{19-16} = Rn;
1075 let Inst{15-12} = Rd;
1076 let Inst{11-5} = shift{11-5};
1078 let Inst{3-0} = shift{3-0};
1081 def rsr : AsI1<opcod, (outs GPR:$Rd),
1082 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1083 iis, opc, "\t$Rd, $Rn, $shift",
1084 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1089 let Inst{19-16} = Rn;
1090 let Inst{15-12} = Rd;
1091 let Inst{11-8} = shift{11-8};
1093 let Inst{6-5} = shift{6-5};
1095 let Inst{3-0} = shift{3-0};
1098 // Assembly aliases for optional destination operand when it's the same
1099 // as the source operand.
1100 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1101 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1102 so_imm:$imm, pred:$p,
1105 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1106 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1110 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1111 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1112 so_reg_imm:$shift, pred:$p,
1115 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1116 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1117 so_reg_reg:$shift, pred:$p,
1123 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1125 /// These opcodes will be converted to the real non-S opcodes by
1126 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1127 let hasPostISelHook = 1, Defs = [CPSR] in {
1128 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1129 InstrItinClass iis, PatFrag opnode,
1130 bit Commutable = 0> {
1131 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1133 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1135 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1137 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1138 let isCommutable = Commutable;
1140 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1141 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1143 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1144 so_reg_imm:$shift))]>;
1146 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1147 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1149 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1150 so_reg_reg:$shift))]>;
1154 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1155 /// operands are reversed.
1156 let hasPostISelHook = 1, Defs = [CPSR] in {
1157 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1158 InstrItinClass iis, PatFrag opnode,
1159 bit Commutable = 0> {
1160 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1162 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1164 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1165 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1167 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1170 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1171 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1173 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1178 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1179 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1180 /// a explicit result, only implicitly set CPSR.
1181 let isCompare = 1, Defs = [CPSR] in {
1182 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1183 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1184 PatFrag opnode, bit Commutable = 0> {
1185 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1187 [(opnode GPR:$Rn, so_imm:$imm)]> {
1192 let Inst{19-16} = Rn;
1193 let Inst{15-12} = 0b0000;
1194 let Inst{11-0} = imm;
1196 let Unpredictable{15-12} = 0b1111;
1198 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1200 [(opnode GPR:$Rn, GPR:$Rm)]> {
1203 let isCommutable = Commutable;
1206 let Inst{19-16} = Rn;
1207 let Inst{15-12} = 0b0000;
1208 let Inst{11-4} = 0b00000000;
1211 let Unpredictable{15-12} = 0b1111;
1213 def rsi : AI1<opcod, (outs),
1214 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1215 opc, "\t$Rn, $shift",
1216 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1221 let Inst{19-16} = Rn;
1222 let Inst{15-12} = 0b0000;
1223 let Inst{11-5} = shift{11-5};
1225 let Inst{3-0} = shift{3-0};
1227 let Unpredictable{15-12} = 0b1111;
1229 def rsr : AI1<opcod, (outs),
1230 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1231 opc, "\t$Rn, $shift",
1232 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> {
1237 let Inst{19-16} = Rn;
1238 let Inst{15-12} = 0b0000;
1239 let Inst{11-8} = shift{11-8};
1241 let Inst{6-5} = shift{6-5};
1243 let Inst{3-0} = shift{3-0};
1245 let Unpredictable{15-12} = 0b1111;
1251 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1252 /// register and one whose operand is a register rotated by 8/16/24.
1253 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1254 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1255 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1256 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1257 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1258 Requires<[IsARM, HasV6]> {
1262 let Inst{19-16} = 0b1111;
1263 let Inst{15-12} = Rd;
1264 let Inst{11-10} = rot;
1268 class AI_ext_rrot_np<bits<8> opcod, string opc>
1269 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1270 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1271 Requires<[IsARM, HasV6]> {
1273 let Inst{19-16} = 0b1111;
1274 let Inst{11-10} = rot;
1277 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1278 /// register and one whose operand is a register rotated by 8/16/24.
1279 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1280 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1281 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1282 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1283 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1284 Requires<[IsARM, HasV6]> {
1289 let Inst{19-16} = Rn;
1290 let Inst{15-12} = Rd;
1291 let Inst{11-10} = rot;
1292 let Inst{9-4} = 0b000111;
1296 class AI_exta_rrot_np<bits<8> opcod, string opc>
1297 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1298 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1299 Requires<[IsARM, HasV6]> {
1302 let Inst{19-16} = Rn;
1303 let Inst{11-10} = rot;
1306 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1307 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1308 string baseOpc, bit Commutable = 0> {
1309 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1310 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1311 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1312 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1318 let Inst{15-12} = Rd;
1319 let Inst{19-16} = Rn;
1320 let Inst{11-0} = imm;
1322 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1323 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1324 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1329 let Inst{11-4} = 0b00000000;
1331 let isCommutable = Commutable;
1333 let Inst{15-12} = Rd;
1334 let Inst{19-16} = Rn;
1336 def rsi : AsI1<opcod, (outs GPR:$Rd),
1337 (ins GPR:$Rn, so_reg_imm:$shift),
1338 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1339 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1345 let Inst{19-16} = Rn;
1346 let Inst{15-12} = Rd;
1347 let Inst{11-5} = shift{11-5};
1349 let Inst{3-0} = shift{3-0};
1351 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1352 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1353 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1354 [(set GPRnopc:$Rd, CPSR, (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1360 let Inst{19-16} = Rn;
1361 let Inst{15-12} = Rd;
1362 let Inst{11-8} = shift{11-8};
1364 let Inst{6-5} = shift{6-5};
1366 let Inst{3-0} = shift{3-0};
1370 // Assembly aliases for optional destination operand when it's the same
1371 // as the source operand.
1372 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1373 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1374 so_imm:$imm, pred:$p,
1377 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1378 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1382 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1383 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1384 so_reg_imm:$shift, pred:$p,
1387 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1388 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPRnopc:$Rdn, GPRnopc:$Rdn,
1389 so_reg_reg:$shift, pred:$p,
1394 /// AI1_rsc_irs - Define instructions and patterns for rsc
1395 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1397 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1398 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1399 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1400 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1406 let Inst{15-12} = Rd;
1407 let Inst{19-16} = Rn;
1408 let Inst{11-0} = imm;
1410 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1411 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1412 [/* pattern left blank */]> {
1416 let Inst{11-4} = 0b00000000;
1419 let Inst{15-12} = Rd;
1420 let Inst{19-16} = Rn;
1422 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1423 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1424 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1430 let Inst{19-16} = Rn;
1431 let Inst{15-12} = Rd;
1432 let Inst{11-5} = shift{11-5};
1434 let Inst{3-0} = shift{3-0};
1436 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1437 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1438 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1444 let Inst{19-16} = Rn;
1445 let Inst{15-12} = Rd;
1446 let Inst{11-8} = shift{11-8};
1448 let Inst{6-5} = shift{6-5};
1450 let Inst{3-0} = shift{3-0};
1454 // Assembly aliases for optional destination operand when it's the same
1455 // as the source operand.
1456 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1457 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1458 so_imm:$imm, pred:$p,
1461 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1462 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1466 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1467 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1468 so_reg_imm:$shift, pred:$p,
1471 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1472 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1473 so_reg_reg:$shift, pred:$p,
1478 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1479 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1480 InstrItinClass iir, PatFrag opnode> {
1481 // Note: We use the complex addrmode_imm12 rather than just an input
1482 // GPR and a constrained immediate so that we can use this to match
1483 // frame index references and avoid matching constant pool references.
1484 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1485 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1486 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1489 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1490 let Inst{19-16} = addr{16-13}; // Rn
1491 let Inst{15-12} = Rt;
1492 let Inst{11-0} = addr{11-0}; // imm12
1494 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1495 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1496 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1499 let shift{4} = 0; // Inst{4} = 0
1500 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1501 let Inst{19-16} = shift{16-13}; // Rn
1502 let Inst{15-12} = Rt;
1503 let Inst{11-0} = shift{11-0};
1508 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1509 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1510 InstrItinClass iir, PatFrag opnode> {
1511 // Note: We use the complex addrmode_imm12 rather than just an input
1512 // GPR and a constrained immediate so that we can use this to match
1513 // frame index references and avoid matching constant pool references.
1514 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
1515 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1516 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1519 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1520 let Inst{19-16} = addr{16-13}; // Rn
1521 let Inst{15-12} = Rt;
1522 let Inst{11-0} = addr{11-0}; // imm12
1524 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
1525 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1526 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1529 let shift{4} = 0; // Inst{4} = 0
1530 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1531 let Inst{19-16} = shift{16-13}; // Rn
1532 let Inst{15-12} = Rt;
1533 let Inst{11-0} = shift{11-0};
1539 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1540 InstrItinClass iir, PatFrag opnode> {
1541 // Note: We use the complex addrmode_imm12 rather than just an input
1542 // GPR and a constrained immediate so that we can use this to match
1543 // frame index references and avoid matching constant pool references.
1544 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1545 (ins GPR:$Rt, addrmode_imm12:$addr),
1546 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1547 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1550 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1551 let Inst{19-16} = addr{16-13}; // Rn
1552 let Inst{15-12} = Rt;
1553 let Inst{11-0} = addr{11-0}; // imm12
1555 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1556 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1557 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1560 let shift{4} = 0; // Inst{4} = 0
1561 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1562 let Inst{19-16} = shift{16-13}; // Rn
1563 let Inst{15-12} = Rt;
1564 let Inst{11-0} = shift{11-0};
1568 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1569 InstrItinClass iir, PatFrag opnode> {
1570 // Note: We use the complex addrmode_imm12 rather than just an input
1571 // GPR and a constrained immediate so that we can use this to match
1572 // frame index references and avoid matching constant pool references.
1573 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1574 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1575 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1576 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1579 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1580 let Inst{19-16} = addr{16-13}; // Rn
1581 let Inst{15-12} = Rt;
1582 let Inst{11-0} = addr{11-0}; // imm12
1584 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1585 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1586 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1589 let shift{4} = 0; // Inst{4} = 0
1590 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1591 let Inst{19-16} = shift{16-13}; // Rn
1592 let Inst{15-12} = Rt;
1593 let Inst{11-0} = shift{11-0};
1598 //===----------------------------------------------------------------------===//
1600 //===----------------------------------------------------------------------===//
1602 //===----------------------------------------------------------------------===//
1603 // Miscellaneous Instructions.
1606 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1607 /// the function. The first operand is the ID# for this instruction, the second
1608 /// is the index into the MachineConstantPool that this is, the third is the
1609 /// size in bytes of this constant pool entry.
1610 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1611 def CONSTPOOL_ENTRY :
1612 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1613 i32imm:$size), NoItinerary, []>;
1615 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1616 // from removing one half of the matched pairs. That breaks PEI, which assumes
1617 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1618 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1619 def ADJCALLSTACKUP :
1620 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1621 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1623 def ADJCALLSTACKDOWN :
1624 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1625 [(ARMcallseq_start timm:$amt)]>;
1628 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1629 // (These pseudos use a hand-written selection code).
1630 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1631 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1632 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1634 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1635 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1637 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1638 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1640 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1641 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1643 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1644 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1646 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1647 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1649 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1650 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1652 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1653 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1654 GPR:$set1, GPR:$set2),
1658 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1659 Requires<[IsARM, HasV6T2]> {
1660 let Inst{27-16} = 0b001100100000;
1661 let Inst{15-8} = 0b11110000;
1662 let Inst{7-0} = 0b00000000;
1665 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1666 Requires<[IsARM, HasV6T2]> {
1667 let Inst{27-16} = 0b001100100000;
1668 let Inst{15-8} = 0b11110000;
1669 let Inst{7-0} = 0b00000001;
1672 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1673 Requires<[IsARM, HasV6T2]> {
1674 let Inst{27-16} = 0b001100100000;
1675 let Inst{15-8} = 0b11110000;
1676 let Inst{7-0} = 0b00000010;
1679 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1680 Requires<[IsARM, HasV6T2]> {
1681 let Inst{27-16} = 0b001100100000;
1682 let Inst{15-8} = 0b11110000;
1683 let Inst{7-0} = 0b00000011;
1686 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1687 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1692 let Inst{15-12} = Rd;
1693 let Inst{19-16} = Rn;
1694 let Inst{27-20} = 0b01101000;
1695 let Inst{7-4} = 0b1011;
1696 let Inst{11-8} = 0b1111;
1699 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1700 []>, Requires<[IsARM, HasV6T2]> {
1701 let Inst{27-16} = 0b001100100000;
1702 let Inst{15-8} = 0b11110000;
1703 let Inst{7-0} = 0b00000100;
1706 // The i32imm operand $val can be used by a debugger to store more information
1707 // about the breakpoint.
1708 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1709 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1711 let Inst{3-0} = val{3-0};
1712 let Inst{19-8} = val{15-4};
1713 let Inst{27-20} = 0b00010010;
1714 let Inst{7-4} = 0b0111;
1717 // Change Processor State
1718 // FIXME: We should use InstAlias to handle the optional operands.
1719 class CPS<dag iops, string asm_ops>
1720 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1721 []>, Requires<[IsARM]> {
1727 let Inst{31-28} = 0b1111;
1728 let Inst{27-20} = 0b00010000;
1729 let Inst{19-18} = imod;
1730 let Inst{17} = M; // Enabled if mode is set;
1731 let Inst{16-9} = 0b00000000;
1732 let Inst{8-6} = iflags;
1734 let Inst{4-0} = mode;
1737 let DecoderMethod = "DecodeCPSInstruction" in {
1739 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1740 "$imod\t$iflags, $mode">;
1741 let mode = 0, M = 0 in
1742 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1744 let imod = 0, iflags = 0, M = 1 in
1745 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1748 // Preload signals the memory system of possible future data/instruction access.
1749 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1751 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1752 !strconcat(opc, "\t$addr"),
1753 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1756 let Inst{31-26} = 0b111101;
1757 let Inst{25} = 0; // 0 for immediate form
1758 let Inst{24} = data;
1759 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1760 let Inst{22} = read;
1761 let Inst{21-20} = 0b01;
1762 let Inst{19-16} = addr{16-13}; // Rn
1763 let Inst{15-12} = 0b1111;
1764 let Inst{11-0} = addr{11-0}; // imm12
1767 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1768 !strconcat(opc, "\t$shift"),
1769 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1771 let Inst{31-26} = 0b111101;
1772 let Inst{25} = 1; // 1 for register form
1773 let Inst{24} = data;
1774 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1775 let Inst{22} = read;
1776 let Inst{21-20} = 0b01;
1777 let Inst{19-16} = shift{16-13}; // Rn
1778 let Inst{15-12} = 0b1111;
1779 let Inst{11-0} = shift{11-0};
1784 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1785 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1786 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1788 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1789 "setend\t$end", []>, Requires<[IsARM]> {
1791 let Inst{31-10} = 0b1111000100000001000000;
1796 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1797 []>, Requires<[IsARM, HasV7]> {
1799 let Inst{27-4} = 0b001100100000111100001111;
1800 let Inst{3-0} = opt;
1803 // A5.4 Permanently UNDEFINED instructions.
1804 let isBarrier = 1, isTerminator = 1 in
1805 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1808 let Inst = 0xe7ffdefe;
1811 // Address computation and loads and stores in PIC mode.
1812 let isNotDuplicable = 1 in {
1813 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1815 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1817 let AddedComplexity = 10 in {
1818 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1820 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1822 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1824 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1826 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1828 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1830 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1832 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1834 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1836 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1838 let AddedComplexity = 10 in {
1839 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1840 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1842 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1843 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1844 addrmodepc:$addr)]>;
1846 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1847 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1849 } // isNotDuplicable = 1
1852 // LEApcrel - Load a pc-relative address into a register without offending the
1854 let neverHasSideEffects = 1, isReMaterializable = 1 in
1855 // The 'adr' mnemonic encodes differently if the label is before or after
1856 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1857 // know until then which form of the instruction will be used.
1858 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1859 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1862 let Inst{27-25} = 0b001;
1864 let Inst{23-22} = label{13-12};
1867 let Inst{19-16} = 0b1111;
1868 let Inst{15-12} = Rd;
1869 let Inst{11-0} = label{11-0};
1871 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1874 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1875 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1878 //===----------------------------------------------------------------------===//
1879 // Control Flow Instructions.
1882 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1884 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1885 "bx", "\tlr", [(ARMretflag)]>,
1886 Requires<[IsARM, HasV4T]> {
1887 let Inst{27-0} = 0b0001001011111111111100011110;
1891 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1892 "mov", "\tpc, lr", [(ARMretflag)]>,
1893 Requires<[IsARM, NoV4T]> {
1894 let Inst{27-0} = 0b0001101000001111000000001110;
1898 // Indirect branches
1899 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1901 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1902 [(brind GPR:$dst)]>,
1903 Requires<[IsARM, HasV4T]> {
1905 let Inst{31-4} = 0b1110000100101111111111110001;
1906 let Inst{3-0} = dst;
1909 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1910 "bx", "\t$dst", [/* pattern left blank */]>,
1911 Requires<[IsARM, HasV4T]> {
1913 let Inst{27-4} = 0b000100101111111111110001;
1914 let Inst{3-0} = dst;
1918 // SP is marked as a use to prevent stack-pointer assignments that appear
1919 // immediately before calls from potentially appearing dead.
1921 // FIXME: Do we really need a non-predicated version? If so, it should
1922 // at least be a pseudo instruction expanding to the predicated version
1923 // at MC lowering time.
1924 Defs = [LR], Uses = [SP] in {
1925 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1926 IIC_Br, "bl\t$func",
1927 [(ARMcall tglobaladdr:$func)]>,
1929 let Inst{31-28} = 0b1110;
1931 let Inst{23-0} = func;
1932 let DecoderMethod = "DecodeBranchImmInstruction";
1935 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1936 IIC_Br, "bl", "\t$func",
1937 [(ARMcall_pred tglobaladdr:$func)]>,
1940 let Inst{23-0} = func;
1941 let DecoderMethod = "DecodeBranchImmInstruction";
1945 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1946 IIC_Br, "blx\t$func",
1947 [(ARMcall GPR:$func)]>,
1948 Requires<[IsARM, HasV5T]> {
1950 let Inst{31-4} = 0b1110000100101111111111110011;
1951 let Inst{3-0} = func;
1954 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1955 IIC_Br, "blx", "\t$func",
1956 [(ARMcall_pred GPR:$func)]>,
1957 Requires<[IsARM, HasV5T]> {
1959 let Inst{27-4} = 0b000100101111111111110011;
1960 let Inst{3-0} = func;
1964 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1965 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1966 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1967 Requires<[IsARM, HasV4T]>;
1970 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1971 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1972 Requires<[IsARM, NoV4T]>;
1974 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1975 // return stack predictor.
1976 def BMOVPCB_CALL : ARMPseudoInst<(outs),
1977 (ins bl_target:$func, variable_ops),
1978 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1982 let isBranch = 1, isTerminator = 1 in {
1983 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1984 // a two-value operand where a dag node expects two operands. :(
1985 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1986 IIC_Br, "b", "\t$target",
1987 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1989 let Inst{23-0} = target;
1990 let DecoderMethod = "DecodeBranchImmInstruction";
1993 let isBarrier = 1 in {
1994 // B is "predicable" since it's just a Bcc with an 'always' condition.
1995 let isPredicable = 1 in
1996 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1997 // should be sufficient.
1998 // FIXME: Is B really a Barrier? That doesn't seem right.
1999 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2000 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
2002 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2003 def BR_JTr : ARMPseudoInst<(outs),
2004 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2006 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
2007 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2008 // into i12 and rs suffixed versions.
2009 def BR_JTm : ARMPseudoInst<(outs),
2010 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2012 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2014 def BR_JTadd : ARMPseudoInst<(outs),
2015 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2017 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2019 } // isNotDuplicable = 1, isIndirectBranch = 1
2025 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2026 "blx\t$target", []>,
2027 Requires<[IsARM, HasV5T]> {
2028 let Inst{31-25} = 0b1111101;
2030 let Inst{23-0} = target{24-1};
2031 let Inst{24} = target{0};
2034 // Branch and Exchange Jazelle
2035 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2036 [/* pattern left blank */]> {
2038 let Inst{23-20} = 0b0010;
2039 let Inst{19-8} = 0xfff;
2040 let Inst{7-4} = 0b0010;
2041 let Inst{3-0} = func;
2046 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2047 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2050 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2053 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
2055 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2058 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2064 // Secure Monitor Call is a system instruction.
2065 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2068 let Inst{23-4} = 0b01100000000000000111;
2069 let Inst{3-0} = opt;
2072 // Supervisor Call (Software Interrupt)
2073 let isCall = 1, Uses = [SP] in {
2074 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2076 let Inst{23-0} = svc;
2080 // Store Return State
2081 class SRSI<bit wb, string asm>
2082 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2083 NoItinerary, asm, "", []> {
2085 let Inst{31-28} = 0b1111;
2086 let Inst{27-25} = 0b100;
2090 let Inst{19-16} = 0b1101; // SP
2091 let Inst{15-5} = 0b00000101000;
2092 let Inst{4-0} = mode;
2095 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2096 let Inst{24-23} = 0;
2098 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2099 let Inst{24-23} = 0;
2101 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2102 let Inst{24-23} = 0b10;
2104 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2105 let Inst{24-23} = 0b10;
2107 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2108 let Inst{24-23} = 0b01;
2110 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2111 let Inst{24-23} = 0b01;
2113 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2114 let Inst{24-23} = 0b11;
2116 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2117 let Inst{24-23} = 0b11;
2120 // Return From Exception
2121 class RFEI<bit wb, string asm>
2122 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2123 NoItinerary, asm, "", []> {
2125 let Inst{31-28} = 0b1111;
2126 let Inst{27-25} = 0b100;
2130 let Inst{19-16} = Rn;
2131 let Inst{15-0} = 0xa00;
2134 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2135 let Inst{24-23} = 0;
2137 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2138 let Inst{24-23} = 0;
2140 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2141 let Inst{24-23} = 0b10;
2143 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2144 let Inst{24-23} = 0b10;
2146 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2147 let Inst{24-23} = 0b01;
2149 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2150 let Inst{24-23} = 0b01;
2152 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2153 let Inst{24-23} = 0b11;
2155 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2156 let Inst{24-23} = 0b11;
2159 //===----------------------------------------------------------------------===//
2160 // Load / Store Instructions.
2166 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2167 UnOpFrag<(load node:$Src)>>;
2168 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2169 UnOpFrag<(zextloadi8 node:$Src)>>;
2170 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2171 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2172 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2173 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2175 // Special LDR for loads from non-pc-relative constpools.
2176 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2177 isReMaterializable = 1, isCodeGenOnly = 1 in
2178 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2179 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2183 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2184 let Inst{19-16} = 0b1111;
2185 let Inst{15-12} = Rt;
2186 let Inst{11-0} = addr{11-0}; // imm12
2189 // Loads with zero extension
2190 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2191 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2192 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2194 // Loads with sign extension
2195 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2196 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2197 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2199 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2200 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2201 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2203 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2205 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2206 (ins addrmode3:$addr), LdMiscFrm,
2207 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2208 []>, Requires<[IsARM, HasV5TE]>;
2212 multiclass AI2_ldridx<bit isByte, string opc,
2213 InstrItinClass iii, InstrItinClass iir> {
2214 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2215 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2216 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2219 let Inst{23} = addr{12};
2220 let Inst{19-16} = addr{16-13};
2221 let Inst{11-0} = addr{11-0};
2222 let DecoderMethod = "DecodeLDRPreImm";
2223 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2226 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2227 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2228 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2231 let Inst{23} = addr{12};
2232 let Inst{19-16} = addr{16-13};
2233 let Inst{11-0} = addr{11-0};
2235 let DecoderMethod = "DecodeLDRPreReg";
2236 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2239 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2240 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2241 IndexModePost, LdFrm, iir,
2242 opc, "\t$Rt, $addr, $offset",
2243 "$addr.base = $Rn_wb", []> {
2249 let Inst{23} = offset{12};
2250 let Inst{19-16} = addr;
2251 let Inst{11-0} = offset{11-0};
2253 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2256 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2257 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2258 IndexModePost, LdFrm, iii,
2259 opc, "\t$Rt, $addr, $offset",
2260 "$addr.base = $Rn_wb", []> {
2266 let Inst{23} = offset{12};
2267 let Inst{19-16} = addr;
2268 let Inst{11-0} = offset{11-0};
2270 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2275 let mayLoad = 1, neverHasSideEffects = 1 in {
2276 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2277 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2278 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2279 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2282 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2283 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2284 (ins addrmode3:$addr), IndexModePre,
2286 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2288 let Inst{23} = addr{8}; // U bit
2289 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2290 let Inst{19-16} = addr{12-9}; // Rn
2291 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2292 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2293 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2294 let DecoderMethod = "DecodeAddrMode3Instruction";
2296 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2297 (ins addr_offset_none:$addr, am3offset:$offset),
2298 IndexModePost, LdMiscFrm, itin,
2299 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2303 let Inst{23} = offset{8}; // U bit
2304 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2305 let Inst{19-16} = addr;
2306 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2307 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2308 let DecoderMethod = "DecodeAddrMode3Instruction";
2312 let mayLoad = 1, neverHasSideEffects = 1 in {
2313 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2314 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2315 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2316 let hasExtraDefRegAllocReq = 1 in {
2317 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2318 (ins addrmode3:$addr), IndexModePre,
2319 LdMiscFrm, IIC_iLoad_d_ru,
2320 "ldrd", "\t$Rt, $Rt2, $addr!",
2321 "$addr.base = $Rn_wb", []> {
2323 let Inst{23} = addr{8}; // U bit
2324 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2325 let Inst{19-16} = addr{12-9}; // Rn
2326 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2327 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2328 let DecoderMethod = "DecodeAddrMode3Instruction";
2329 let AsmMatchConverter = "cvtLdrdPre";
2331 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2332 (ins addr_offset_none:$addr, am3offset:$offset),
2333 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2334 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2335 "$addr.base = $Rn_wb", []> {
2338 let Inst{23} = offset{8}; // U bit
2339 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2340 let Inst{19-16} = addr;
2341 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2342 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2343 let DecoderMethod = "DecodeAddrMode3Instruction";
2345 } // hasExtraDefRegAllocReq = 1
2346 } // mayLoad = 1, neverHasSideEffects = 1
2348 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2349 let mayLoad = 1, neverHasSideEffects = 1 in {
2350 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2351 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2352 IndexModePost, LdFrm, IIC_iLoad_ru,
2353 "ldrt", "\t$Rt, $addr, $offset",
2354 "$addr.base = $Rn_wb", []> {
2360 let Inst{23} = offset{12};
2361 let Inst{21} = 1; // overwrite
2362 let Inst{19-16} = addr;
2363 let Inst{11-5} = offset{11-5};
2365 let Inst{3-0} = offset{3-0};
2366 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2369 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2370 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2371 IndexModePost, LdFrm, IIC_iLoad_ru,
2372 "ldrt", "\t$Rt, $addr, $offset",
2373 "$addr.base = $Rn_wb", []> {
2379 let Inst{23} = offset{12};
2380 let Inst{21} = 1; // overwrite
2381 let Inst{19-16} = addr;
2382 let Inst{11-0} = offset{11-0};
2383 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2386 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2387 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2388 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2389 "ldrbt", "\t$Rt, $addr, $offset",
2390 "$addr.base = $Rn_wb", []> {
2396 let Inst{23} = offset{12};
2397 let Inst{21} = 1; // overwrite
2398 let Inst{19-16} = addr;
2399 let Inst{11-5} = offset{11-5};
2401 let Inst{3-0} = offset{3-0};
2402 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2405 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2406 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2407 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2408 "ldrbt", "\t$Rt, $addr, $offset",
2409 "$addr.base = $Rn_wb", []> {
2415 let Inst{23} = offset{12};
2416 let Inst{21} = 1; // overwrite
2417 let Inst{19-16} = addr;
2418 let Inst{11-0} = offset{11-0};
2419 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2422 multiclass AI3ldrT<bits<4> op, string opc> {
2423 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2424 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2425 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2426 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2428 let Inst{23} = offset{8};
2430 let Inst{11-8} = offset{7-4};
2431 let Inst{3-0} = offset{3-0};
2432 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2434 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2435 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2436 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2437 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2439 let Inst{23} = Rm{4};
2442 let Unpredictable{11-8} = 0b1111;
2443 let Inst{3-0} = Rm{3-0};
2444 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2445 let DecoderMethod = "DecodeLDR";
2449 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2450 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2451 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2456 // Stores with truncate
2457 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2458 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2459 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2462 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2463 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2464 StMiscFrm, IIC_iStore_d_r,
2465 "strd", "\t$Rt, $src2, $addr", []>,
2466 Requires<[IsARM, HasV5TE]> {
2471 multiclass AI2_stridx<bit isByte, string opc,
2472 InstrItinClass iii, InstrItinClass iir> {
2473 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2474 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2476 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2479 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2480 let Inst{19-16} = addr{16-13}; // Rn
2481 let Inst{11-0} = addr{11-0}; // imm12
2482 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2483 let DecoderMethod = "DecodeSTRPreImm";
2486 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2487 (ins GPR:$Rt, ldst_so_reg:$addr),
2488 IndexModePre, StFrm, iir,
2489 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2492 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2493 let Inst{19-16} = addr{16-13}; // Rn
2494 let Inst{11-0} = addr{11-0};
2495 let Inst{4} = 0; // Inst{4} = 0
2496 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2497 let DecoderMethod = "DecodeSTRPreReg";
2499 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2500 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2501 IndexModePost, StFrm, iir,
2502 opc, "\t$Rt, $addr, $offset",
2503 "$addr.base = $Rn_wb", []> {
2509 let Inst{23} = offset{12};
2510 let Inst{19-16} = addr;
2511 let Inst{11-0} = offset{11-0};
2513 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2516 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2517 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2518 IndexModePost, StFrm, iii,
2519 opc, "\t$Rt, $addr, $offset",
2520 "$addr.base = $Rn_wb", []> {
2526 let Inst{23} = offset{12};
2527 let Inst{19-16} = addr;
2528 let Inst{11-0} = offset{11-0};
2530 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2534 let mayStore = 1, neverHasSideEffects = 1 in {
2535 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2536 // IIC_iStore_siu depending on whether it the offset register is shifted.
2537 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2538 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2541 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2542 am2offset_reg:$offset),
2543 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2544 am2offset_reg:$offset)>;
2545 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2546 am2offset_imm:$offset),
2547 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2548 am2offset_imm:$offset)>;
2549 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2550 am2offset_reg:$offset),
2551 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2552 am2offset_reg:$offset)>;
2553 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2554 am2offset_imm:$offset),
2555 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2556 am2offset_imm:$offset)>;
2558 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2559 // put the patterns on the instruction definitions directly as ISel wants
2560 // the address base and offset to be separate operands, not a single
2561 // complex operand like we represent the instructions themselves. The
2562 // pseudos map between the two.
2563 let usesCustomInserter = 1,
2564 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2565 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2566 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2569 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2570 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2571 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2574 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2575 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2576 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2579 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2580 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2581 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2584 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2585 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2586 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2589 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2594 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2595 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2596 StMiscFrm, IIC_iStore_bh_ru,
2597 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2599 let Inst{23} = addr{8}; // U bit
2600 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2601 let Inst{19-16} = addr{12-9}; // Rn
2602 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2603 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2604 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2605 let DecoderMethod = "DecodeAddrMode3Instruction";
2608 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2609 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2610 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2611 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2612 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2613 addr_offset_none:$addr,
2614 am3offset:$offset))]> {
2617 let Inst{23} = offset{8}; // U bit
2618 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2619 let Inst{19-16} = addr;
2620 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2621 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2622 let DecoderMethod = "DecodeAddrMode3Instruction";
2625 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2626 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2627 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2628 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2629 "strd", "\t$Rt, $Rt2, $addr!",
2630 "$addr.base = $Rn_wb", []> {
2632 let Inst{23} = addr{8}; // U bit
2633 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2634 let Inst{19-16} = addr{12-9}; // Rn
2635 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2636 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2637 let DecoderMethod = "DecodeAddrMode3Instruction";
2638 let AsmMatchConverter = "cvtStrdPre";
2641 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2642 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2644 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2645 "strd", "\t$Rt, $Rt2, $addr, $offset",
2646 "$addr.base = $Rn_wb", []> {
2649 let Inst{23} = offset{8}; // U bit
2650 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2651 let Inst{19-16} = addr;
2652 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2653 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2654 let DecoderMethod = "DecodeAddrMode3Instruction";
2656 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2658 // STRT, STRBT, and STRHT
2660 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2661 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2662 IndexModePost, StFrm, IIC_iStore_bh_ru,
2663 "strbt", "\t$Rt, $addr, $offset",
2664 "$addr.base = $Rn_wb", []> {
2670 let Inst{23} = offset{12};
2671 let Inst{21} = 1; // overwrite
2672 let Inst{19-16} = addr;
2673 let Inst{11-5} = offset{11-5};
2675 let Inst{3-0} = offset{3-0};
2676 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2679 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2680 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2681 IndexModePost, StFrm, IIC_iStore_bh_ru,
2682 "strbt", "\t$Rt, $addr, $offset",
2683 "$addr.base = $Rn_wb", []> {
2689 let Inst{23} = offset{12};
2690 let Inst{21} = 1; // overwrite
2691 let Inst{19-16} = addr;
2692 let Inst{11-0} = offset{11-0};
2693 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2696 let mayStore = 1, neverHasSideEffects = 1 in {
2697 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2698 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2699 IndexModePost, StFrm, IIC_iStore_ru,
2700 "strt", "\t$Rt, $addr, $offset",
2701 "$addr.base = $Rn_wb", []> {
2707 let Inst{23} = offset{12};
2708 let Inst{21} = 1; // overwrite
2709 let Inst{19-16} = addr;
2710 let Inst{11-5} = offset{11-5};
2712 let Inst{3-0} = offset{3-0};
2713 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2716 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2717 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2718 IndexModePost, StFrm, IIC_iStore_ru,
2719 "strt", "\t$Rt, $addr, $offset",
2720 "$addr.base = $Rn_wb", []> {
2726 let Inst{23} = offset{12};
2727 let Inst{21} = 1; // overwrite
2728 let Inst{19-16} = addr;
2729 let Inst{11-0} = offset{11-0};
2730 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2735 multiclass AI3strT<bits<4> op, string opc> {
2736 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2737 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2738 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2739 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2741 let Inst{23} = offset{8};
2743 let Inst{11-8} = offset{7-4};
2744 let Inst{3-0} = offset{3-0};
2745 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2747 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2748 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2749 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2750 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2752 let Inst{23} = Rm{4};
2755 let Inst{3-0} = Rm{3-0};
2756 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2761 defm STRHT : AI3strT<0b1011, "strht">;
2764 //===----------------------------------------------------------------------===//
2765 // Load / store multiple Instructions.
2768 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2769 InstrItinClass itin, InstrItinClass itin_upd> {
2770 // IA is the default, so no need for an explicit suffix on the
2771 // mnemonic here. Without it is the cannonical spelling.
2773 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2774 IndexModeNone, f, itin,
2775 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2776 let Inst{24-23} = 0b01; // Increment After
2777 let Inst{22} = P_bit;
2778 let Inst{21} = 0; // No writeback
2779 let Inst{20} = L_bit;
2782 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2783 IndexModeUpd, f, itin_upd,
2784 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2785 let Inst{24-23} = 0b01; // Increment After
2786 let Inst{22} = P_bit;
2787 let Inst{21} = 1; // Writeback
2788 let Inst{20} = L_bit;
2790 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2793 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2794 IndexModeNone, f, itin,
2795 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2796 let Inst{24-23} = 0b00; // Decrement After
2797 let Inst{22} = P_bit;
2798 let Inst{21} = 0; // No writeback
2799 let Inst{20} = L_bit;
2802 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2803 IndexModeUpd, f, itin_upd,
2804 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2805 let Inst{24-23} = 0b00; // Decrement After
2806 let Inst{22} = P_bit;
2807 let Inst{21} = 1; // Writeback
2808 let Inst{20} = L_bit;
2810 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2813 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2814 IndexModeNone, f, itin,
2815 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2816 let Inst{24-23} = 0b10; // Decrement Before
2817 let Inst{22} = P_bit;
2818 let Inst{21} = 0; // No writeback
2819 let Inst{20} = L_bit;
2822 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2823 IndexModeUpd, f, itin_upd,
2824 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2825 let Inst{24-23} = 0b10; // Decrement Before
2826 let Inst{22} = P_bit;
2827 let Inst{21} = 1; // Writeback
2828 let Inst{20} = L_bit;
2830 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2833 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2834 IndexModeNone, f, itin,
2835 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2836 let Inst{24-23} = 0b11; // Increment Before
2837 let Inst{22} = P_bit;
2838 let Inst{21} = 0; // No writeback
2839 let Inst{20} = L_bit;
2842 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2843 IndexModeUpd, f, itin_upd,
2844 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2845 let Inst{24-23} = 0b11; // Increment Before
2846 let Inst{22} = P_bit;
2847 let Inst{21} = 1; // Writeback
2848 let Inst{20} = L_bit;
2850 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2854 let neverHasSideEffects = 1 in {
2856 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2857 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2860 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2861 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2864 } // neverHasSideEffects
2866 // FIXME: remove when we have a way to marking a MI with these properties.
2867 // FIXME: Should pc be an implicit operand like PICADD, etc?
2868 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2869 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2870 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2871 reglist:$regs, variable_ops),
2872 4, IIC_iLoad_mBr, [],
2873 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2874 RegConstraint<"$Rn = $wb">;
2876 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2877 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2880 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2881 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2886 //===----------------------------------------------------------------------===//
2887 // Move Instructions.
2890 let neverHasSideEffects = 1 in
2891 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2892 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2896 let Inst{19-16} = 0b0000;
2897 let Inst{11-4} = 0b00000000;
2900 let Inst{15-12} = Rd;
2903 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2904 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2906 // A version for the smaller set of tail call registers.
2907 let neverHasSideEffects = 1 in
2908 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2909 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2913 let Inst{11-4} = 0b00000000;
2916 let Inst{15-12} = Rd;
2919 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2920 DPSoRegRegFrm, IIC_iMOVsr,
2921 "mov", "\t$Rd, $src",
2922 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2925 let Inst{15-12} = Rd;
2926 let Inst{19-16} = 0b0000;
2927 let Inst{11-8} = src{11-8};
2929 let Inst{6-5} = src{6-5};
2931 let Inst{3-0} = src{3-0};
2935 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2936 DPSoRegImmFrm, IIC_iMOVsr,
2937 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2941 let Inst{15-12} = Rd;
2942 let Inst{19-16} = 0b0000;
2943 let Inst{11-5} = src{11-5};
2945 let Inst{3-0} = src{3-0};
2949 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2950 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2951 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2955 let Inst{15-12} = Rd;
2956 let Inst{19-16} = 0b0000;
2957 let Inst{11-0} = imm;
2960 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2961 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2963 "movw", "\t$Rd, $imm",
2964 [(set GPR:$Rd, imm0_65535:$imm)]>,
2965 Requires<[IsARM, HasV6T2]>, UnaryDP {
2968 let Inst{15-12} = Rd;
2969 let Inst{11-0} = imm{11-0};
2970 let Inst{19-16} = imm{15-12};
2973 let DecoderMethod = "DecodeArmMOVTWInstruction";
2976 def : InstAlias<"mov${p} $Rd, $imm",
2977 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2980 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2981 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2983 let Constraints = "$src = $Rd" in {
2984 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2985 (ins GPR:$src, imm0_65535_expr:$imm),
2987 "movt", "\t$Rd, $imm",
2989 (or (and GPR:$src, 0xffff),
2990 lo16AllZero:$imm))]>, UnaryDP,
2991 Requires<[IsARM, HasV6T2]> {
2994 let Inst{15-12} = Rd;
2995 let Inst{11-0} = imm{11-0};
2996 let Inst{19-16} = imm{15-12};
2999 let DecoderMethod = "DecodeArmMOVTWInstruction";
3002 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3003 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3007 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3008 Requires<[IsARM, HasV6T2]>;
3010 let Uses = [CPSR] in
3011 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3012 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3015 // These aren't really mov instructions, but we have to define them this way
3016 // due to flag operands.
3018 let Defs = [CPSR] in {
3019 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3020 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3022 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3023 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3027 //===----------------------------------------------------------------------===//
3028 // Extend Instructions.
3033 def SXTB : AI_ext_rrot<0b01101010,
3034 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3035 def SXTH : AI_ext_rrot<0b01101011,
3036 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3038 def SXTAB : AI_exta_rrot<0b01101010,
3039 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3040 def SXTAH : AI_exta_rrot<0b01101011,
3041 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3043 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3045 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3049 let AddedComplexity = 16 in {
3050 def UXTB : AI_ext_rrot<0b01101110,
3051 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3052 def UXTH : AI_ext_rrot<0b01101111,
3053 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3054 def UXTB16 : AI_ext_rrot<0b01101100,
3055 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3057 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3058 // The transformation should probably be done as a combiner action
3059 // instead so we can include a check for masking back in the upper
3060 // eight bits of the source into the lower eight bits of the result.
3061 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3062 // (UXTB16r_rot GPR:$Src, 3)>;
3063 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3064 (UXTB16 GPR:$Src, 1)>;
3066 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3067 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3068 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3069 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3072 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3073 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3076 def SBFX : I<(outs GPRnopc:$Rd),
3077 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3078 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3079 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3080 Requires<[IsARM, HasV6T2]> {
3085 let Inst{27-21} = 0b0111101;
3086 let Inst{6-4} = 0b101;
3087 let Inst{20-16} = width;
3088 let Inst{15-12} = Rd;
3089 let Inst{11-7} = lsb;
3093 def UBFX : I<(outs GPR:$Rd),
3094 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3095 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3096 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3097 Requires<[IsARM, HasV6T2]> {
3102 let Inst{27-21} = 0b0111111;
3103 let Inst{6-4} = 0b101;
3104 let Inst{20-16} = width;
3105 let Inst{15-12} = Rd;
3106 let Inst{11-7} = lsb;
3110 //===----------------------------------------------------------------------===//
3111 // Arithmetic Instructions.
3114 defm ADD : AsI1_bin_irs<0b0100, "add",
3115 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3116 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3117 defm SUB : AsI1_bin_irs<0b0010, "sub",
3118 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3119 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3121 // ADD and SUB with 's' bit set.
3123 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3124 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3125 // AdjustInstrPostInstrSelection where we determine whether or not to
3126 // set the "s" bit based on CPSR liveness.
3128 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3129 // support for an optional CPSR definition that corresponds to the DAG
3130 // node's second value. We can then eliminate the implicit def of CPSR.
3131 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3132 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3133 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3134 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3136 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3137 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3139 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3140 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3143 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3144 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3145 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3147 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3148 // CPSR and the implicit def of CPSR is not needed.
3149 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3150 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3152 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3153 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3156 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3157 // The assume-no-carry-in form uses the negation of the input since add/sub
3158 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3159 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3161 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3162 (SUBri GPR:$src, so_imm_neg:$imm)>;
3163 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3164 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3166 // The with-carry-in form matches bitwise not instead of the negation.
3167 // Effectively, the inverse interpretation of the carry flag already accounts
3168 // for part of the negation.
3169 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3170 (SBCri GPR:$src, so_imm_not:$imm)>;
3172 // Note: These are implemented in C++ code, because they have to generate
3173 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3175 // (mul X, 2^n+1) -> (add (X << n), X)
3176 // (mul X, 2^n-1) -> (rsb X, (X << n))
3178 // ARM Arithmetic Instruction
3179 // GPR:$dst = GPR:$a op GPR:$b
3180 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3181 list<dag> pattern = [],
3182 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3183 string asm = "\t$Rd, $Rn, $Rm">
3184 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3188 let Inst{27-20} = op27_20;
3189 let Inst{11-4} = op11_4;
3190 let Inst{19-16} = Rn;
3191 let Inst{15-12} = Rd;
3194 let Unpredictable{11-8} = 0b1111;
3197 // Saturating add/subtract
3199 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3200 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3201 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3202 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3203 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3204 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3205 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3206 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3208 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3209 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3212 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3213 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3214 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3215 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3216 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3217 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3218 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3219 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3220 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3221 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3222 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3223 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3225 // Signed/Unsigned add/subtract
3227 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3228 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3229 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3230 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3231 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3232 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3233 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3234 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3235 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3236 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3237 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3238 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3240 // Signed/Unsigned halving add/subtract
3242 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3243 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3244 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3245 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3246 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3247 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3248 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3249 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3250 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3251 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3252 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3253 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3255 // Unsigned Sum of Absolute Differences [and Accumulate].
3257 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3258 MulFrm /* for convenience */, NoItinerary, "usad8",
3259 "\t$Rd, $Rn, $Rm", []>,
3260 Requires<[IsARM, HasV6]> {
3264 let Inst{27-20} = 0b01111000;
3265 let Inst{15-12} = 0b1111;
3266 let Inst{7-4} = 0b0001;
3267 let Inst{19-16} = Rd;
3268 let Inst{11-8} = Rm;
3271 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3272 MulFrm /* for convenience */, NoItinerary, "usada8",
3273 "\t$Rd, $Rn, $Rm, $Ra", []>,
3274 Requires<[IsARM, HasV6]> {
3279 let Inst{27-20} = 0b01111000;
3280 let Inst{7-4} = 0b0001;
3281 let Inst{19-16} = Rd;
3282 let Inst{15-12} = Ra;
3283 let Inst{11-8} = Rm;
3287 // Signed/Unsigned saturate
3289 def SSAT : AI<(outs GPRnopc:$Rd),
3290 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3291 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3296 let Inst{27-21} = 0b0110101;
3297 let Inst{5-4} = 0b01;
3298 let Inst{20-16} = sat_imm;
3299 let Inst{15-12} = Rd;
3300 let Inst{11-7} = sh{4-0};
3301 let Inst{6} = sh{5};
3305 def SSAT16 : AI<(outs GPRnopc:$Rd),
3306 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3307 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3311 let Inst{27-20} = 0b01101010;
3312 let Inst{11-4} = 0b11110011;
3313 let Inst{15-12} = Rd;
3314 let Inst{19-16} = sat_imm;
3318 def USAT : AI<(outs GPRnopc:$Rd),
3319 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3320 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3325 let Inst{27-21} = 0b0110111;
3326 let Inst{5-4} = 0b01;
3327 let Inst{15-12} = Rd;
3328 let Inst{11-7} = sh{4-0};
3329 let Inst{6} = sh{5};
3330 let Inst{20-16} = sat_imm;
3334 def USAT16 : AI<(outs GPRnopc:$Rd),
3335 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3336 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3340 let Inst{27-20} = 0b01101110;
3341 let Inst{11-4} = 0b11110011;
3342 let Inst{15-12} = Rd;
3343 let Inst{19-16} = sat_imm;
3347 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3348 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3349 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3350 (USAT imm:$pos, GPRnopc:$a, 0)>;
3352 //===----------------------------------------------------------------------===//
3353 // Bitwise Instructions.
3356 defm AND : AsI1_bin_irs<0b0000, "and",
3357 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3358 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3359 defm ORR : AsI1_bin_irs<0b1100, "orr",
3360 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3361 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3362 defm EOR : AsI1_bin_irs<0b0001, "eor",
3363 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3364 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3365 defm BIC : AsI1_bin_irs<0b1110, "bic",
3366 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3367 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3369 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3370 // like in the actual instruction encoding. The complexity of mapping the mask
3371 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3372 // instruction description.
3373 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3374 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3375 "bfc", "\t$Rd, $imm", "$src = $Rd",
3376 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3377 Requires<[IsARM, HasV6T2]> {
3380 let Inst{27-21} = 0b0111110;
3381 let Inst{6-0} = 0b0011111;
3382 let Inst{15-12} = Rd;
3383 let Inst{11-7} = imm{4-0}; // lsb
3384 let Inst{20-16} = imm{9-5}; // msb
3387 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3388 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3389 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3390 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3391 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3392 bf_inv_mask_imm:$imm))]>,
3393 Requires<[IsARM, HasV6T2]> {
3397 let Inst{27-21} = 0b0111110;
3398 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3399 let Inst{15-12} = Rd;
3400 let Inst{11-7} = imm{4-0}; // lsb
3401 let Inst{20-16} = imm{9-5}; // width
3405 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3406 "mvn", "\t$Rd, $Rm",
3407 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3411 let Inst{19-16} = 0b0000;
3412 let Inst{11-4} = 0b00000000;
3413 let Inst{15-12} = Rd;
3416 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3417 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3418 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3422 let Inst{19-16} = 0b0000;
3423 let Inst{15-12} = Rd;
3424 let Inst{11-5} = shift{11-5};
3426 let Inst{3-0} = shift{3-0};
3428 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3429 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3430 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3434 let Inst{19-16} = 0b0000;
3435 let Inst{15-12} = Rd;
3436 let Inst{11-8} = shift{11-8};
3438 let Inst{6-5} = shift{6-5};
3440 let Inst{3-0} = shift{3-0};
3442 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3443 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3444 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3445 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3449 let Inst{19-16} = 0b0000;
3450 let Inst{15-12} = Rd;
3451 let Inst{11-0} = imm;
3454 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3455 (BICri GPR:$src, so_imm_not:$imm)>;
3457 //===----------------------------------------------------------------------===//
3458 // Multiply Instructions.
3460 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3461 string opc, string asm, list<dag> pattern>
3462 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3466 let Inst{19-16} = Rd;
3467 let Inst{11-8} = Rm;
3470 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3471 string opc, string asm, list<dag> pattern>
3472 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3477 let Inst{19-16} = RdHi;
3478 let Inst{15-12} = RdLo;
3479 let Inst{11-8} = Rm;
3483 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3484 // property. Remove them when it's possible to add those properties
3485 // on an individual MachineInstr, not just an instuction description.
3486 let isCommutable = 1 in {
3487 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3488 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3489 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3490 Requires<[IsARM, HasV6]> {
3491 let Inst{15-12} = 0b0000;
3492 let Unpredictable{15-12} = 0b1111;
3495 let Constraints = "@earlyclobber $Rd" in
3496 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3497 pred:$p, cc_out:$s),
3499 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3500 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3501 Requires<[IsARM, NoV6]>;
3504 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3505 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3506 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3507 Requires<[IsARM, HasV6]> {
3509 let Inst{15-12} = Ra;
3512 let Constraints = "@earlyclobber $Rd" in
3513 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3514 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3516 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3517 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3518 Requires<[IsARM, NoV6]>;
3520 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3521 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3522 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3523 Requires<[IsARM, HasV6T2]> {
3528 let Inst{19-16} = Rd;
3529 let Inst{15-12} = Ra;
3530 let Inst{11-8} = Rm;
3534 // Extra precision multiplies with low / high results
3535 let neverHasSideEffects = 1 in {
3536 let isCommutable = 1 in {
3537 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3538 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3539 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3540 Requires<[IsARM, HasV6]>;
3542 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3543 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3544 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3545 Requires<[IsARM, HasV6]>;
3547 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3548 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3549 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3551 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3552 Requires<[IsARM, NoV6]>;
3554 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3555 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3557 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3558 Requires<[IsARM, NoV6]>;
3562 // Multiply + accumulate
3563 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3564 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3565 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3566 Requires<[IsARM, HasV6]>;
3567 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3568 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3569 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3570 Requires<[IsARM, HasV6]>;
3572 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3573 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3574 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3575 Requires<[IsARM, HasV6]> {
3580 let Inst{19-16} = RdHi;
3581 let Inst{15-12} = RdLo;
3582 let Inst{11-8} = Rm;
3586 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3587 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3588 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3590 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3591 Requires<[IsARM, NoV6]>;
3592 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3593 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3595 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3596 Requires<[IsARM, NoV6]>;
3597 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3598 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3600 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3601 Requires<[IsARM, NoV6]>;
3604 } // neverHasSideEffects
3606 // Most significant word multiply
3607 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3608 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3609 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3610 Requires<[IsARM, HasV6]> {
3611 let Inst{15-12} = 0b1111;
3614 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3615 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3616 Requires<[IsARM, HasV6]> {
3617 let Inst{15-12} = 0b1111;
3620 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3621 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3622 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3623 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3624 Requires<[IsARM, HasV6]>;
3626 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3627 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3628 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3629 Requires<[IsARM, HasV6]>;
3631 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3632 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3633 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3634 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3635 Requires<[IsARM, HasV6]>;
3637 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3638 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3639 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3640 Requires<[IsARM, HasV6]>;
3642 multiclass AI_smul<string opc, PatFrag opnode> {
3643 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3644 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3645 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3646 (sext_inreg GPR:$Rm, i16)))]>,
3647 Requires<[IsARM, HasV5TE]>;
3649 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3650 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3651 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3652 (sra GPR:$Rm, (i32 16))))]>,
3653 Requires<[IsARM, HasV5TE]>;
3655 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3656 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3657 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3658 (sext_inreg GPR:$Rm, i16)))]>,
3659 Requires<[IsARM, HasV5TE]>;
3661 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3662 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3663 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3664 (sra GPR:$Rm, (i32 16))))]>,
3665 Requires<[IsARM, HasV5TE]>;
3667 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3668 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3669 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3670 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3671 Requires<[IsARM, HasV5TE]>;
3673 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3674 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3675 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3676 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3677 Requires<[IsARM, HasV5TE]>;
3681 multiclass AI_smla<string opc, PatFrag opnode> {
3682 let DecoderMethod = "DecodeSMLAInstruction" in {
3683 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3684 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3685 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3686 [(set GPRnopc:$Rd, (add GPR:$Ra,
3687 (opnode (sext_inreg GPRnopc:$Rn, i16),
3688 (sext_inreg GPRnopc:$Rm, i16))))]>,
3689 Requires<[IsARM, HasV5TE]>;
3691 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3692 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3693 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3695 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3696 (sra GPRnopc:$Rm, (i32 16)))))]>,
3697 Requires<[IsARM, HasV5TE]>;
3699 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3700 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3701 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3703 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3704 (sext_inreg GPRnopc:$Rm, i16))))]>,
3705 Requires<[IsARM, HasV5TE]>;
3707 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3708 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3709 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3711 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3712 (sra GPRnopc:$Rm, (i32 16)))))]>,
3713 Requires<[IsARM, HasV5TE]>;
3715 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3716 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3717 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3719 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3720 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3721 Requires<[IsARM, HasV5TE]>;
3723 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3724 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3725 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3727 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3728 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3729 Requires<[IsARM, HasV5TE]>;
3733 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3734 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3736 // Halfword multiply accumulate long: SMLAL<x><y>.
3737 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3738 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3739 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3740 Requires<[IsARM, HasV5TE]>;
3742 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3743 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3744 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3745 Requires<[IsARM, HasV5TE]>;
3747 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3748 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3749 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3750 Requires<[IsARM, HasV5TE]>;
3752 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3753 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3754 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3755 Requires<[IsARM, HasV5TE]>;
3757 // Helper class for AI_smld.
3758 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3759 InstrItinClass itin, string opc, string asm>
3760 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3763 let Inst{27-23} = 0b01110;
3764 let Inst{22} = long;
3765 let Inst{21-20} = 0b00;
3766 let Inst{11-8} = Rm;
3773 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3774 InstrItinClass itin, string opc, string asm>
3775 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3777 let Inst{15-12} = 0b1111;
3778 let Inst{19-16} = Rd;
3780 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3781 InstrItinClass itin, string opc, string asm>
3782 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3785 let Inst{19-16} = Rd;
3786 let Inst{15-12} = Ra;
3788 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3789 InstrItinClass itin, string opc, string asm>
3790 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3793 let Inst{19-16} = RdHi;
3794 let Inst{15-12} = RdLo;
3797 multiclass AI_smld<bit sub, string opc> {
3799 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3800 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3801 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3803 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3804 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3805 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3807 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3808 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3809 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3811 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3812 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3813 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3817 defm SMLA : AI_smld<0, "smla">;
3818 defm SMLS : AI_smld<1, "smls">;
3820 multiclass AI_sdml<bit sub, string opc> {
3822 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3823 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3824 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3825 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3828 defm SMUA : AI_sdml<0, "smua">;
3829 defm SMUS : AI_sdml<1, "smus">;
3831 //===----------------------------------------------------------------------===//
3832 // Misc. Arithmetic Instructions.
3835 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3836 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3837 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3839 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3840 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3841 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3842 Requires<[IsARM, HasV6T2]>;
3844 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3845 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3846 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3848 let AddedComplexity = 5 in
3849 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3850 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3851 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3852 Requires<[IsARM, HasV6]>;
3854 let AddedComplexity = 5 in
3855 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3856 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3857 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3858 Requires<[IsARM, HasV6]>;
3860 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3861 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3864 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3865 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3866 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3867 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3868 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3870 Requires<[IsARM, HasV6]>;
3872 // Alternate cases for PKHBT where identities eliminate some nodes.
3873 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3874 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3875 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3876 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3878 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3879 // will match the pattern below.
3880 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3881 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3882 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3883 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3884 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3886 Requires<[IsARM, HasV6]>;
3888 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3889 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3890 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3891 (srl GPRnopc:$src2, imm16_31:$sh)),
3892 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3893 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3894 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3895 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3897 //===----------------------------------------------------------------------===//
3898 // Comparison Instructions...
3901 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3902 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3903 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3905 // ARMcmpZ can re-use the above instruction definitions.
3906 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3907 (CMPri GPR:$src, so_imm:$imm)>;
3908 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3909 (CMPrr GPR:$src, GPR:$rhs)>;
3910 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3911 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3912 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3913 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3915 // FIXME: We have to be careful when using the CMN instruction and comparison
3916 // with 0. One would expect these two pieces of code should give identical
3932 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3933 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3934 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3935 // value of r0 and the carry bit (because the "carry bit" parameter to
3936 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3937 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3938 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3939 // parameter to AddWithCarry is defined as 0).
3941 // When x is 0 and unsigned:
3945 // ~x + 1 = 0x1 0000 0000
3946 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3948 // Therefore, we should disable CMN when comparing against zero, until we can
3949 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3950 // when it's a comparison which doesn't look at the 'carry' flag).
3952 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3954 // This is related to <rdar://problem/7569620>.
3956 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3957 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3959 // Note that TST/TEQ don't set all the same flags that CMP does!
3960 defm TST : AI1_cmp_irs<0b1000, "tst",
3961 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3962 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3963 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3964 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3965 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3967 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3968 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3969 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3971 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3972 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3974 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3975 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3977 // Pseudo i64 compares for some floating point compares.
3978 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3980 def BCCi64 : PseudoInst<(outs),
3981 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3983 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3985 def BCCZi64 : PseudoInst<(outs),
3986 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3987 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3988 } // usesCustomInserter
3991 // Conditional moves
3992 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3993 // a two-value operand where a dag node expects two operands. :(
3994 let neverHasSideEffects = 1 in {
3996 let isCommutable = 1 in
3997 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3999 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4000 RegConstraint<"$false = $Rd">;
4002 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4003 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4005 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4006 imm:$cc, CCR:$ccr))*/]>,
4007 RegConstraint<"$false = $Rd">;
4008 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4009 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4011 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4012 imm:$cc, CCR:$ccr))*/]>,
4013 RegConstraint<"$false = $Rd">;
4016 let isMoveImm = 1 in
4017 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4018 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4021 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4023 let isMoveImm = 1 in
4024 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4025 (ins GPR:$false, so_imm:$imm, pred:$p),
4027 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4028 RegConstraint<"$false = $Rd">;
4030 // Two instruction predicate mov immediate.
4031 let isMoveImm = 1 in
4032 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4033 (ins GPR:$false, i32imm:$src, pred:$p),
4034 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4036 let isMoveImm = 1 in
4037 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4038 (ins GPR:$false, so_imm:$imm, pred:$p),
4040 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4041 RegConstraint<"$false = $Rd">;
4043 // Conditional instructions
4044 multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi,
4046 InstrItinClass iii, InstrItinClass iir,
4047 InstrItinClass iis> {
4048 def ri : ARMPseudoExpand<(outs GPR:$Rd),
4049 (ins GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s),
4051 (iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>,
4052 RegConstraint<"$Rn = $Rd">;
4053 def rr : ARMPseudoExpand<(outs GPR:$Rd),
4054 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4056 (irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4057 RegConstraint<"$Rn = $Rd">;
4058 def rsi : ARMPseudoExpand<(outs GPR:$Rd),
4059 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s),
4061 (irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>,
4062 RegConstraint<"$Rn = $Rd">;
4063 def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd),
4064 (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s),
4066 (irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>,
4067 RegConstraint<"$Rn = $Rd">;
4070 defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr,
4071 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4072 defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
4073 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4074 defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
4075 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4077 } // neverHasSideEffects
4080 //===----------------------------------------------------------------------===//
4081 // Atomic operations intrinsics
4084 def MemBarrierOptOperand : AsmOperandClass {
4085 let Name = "MemBarrierOpt";
4086 let ParserMethod = "parseMemBarrierOptOperand";
4088 def memb_opt : Operand<i32> {
4089 let PrintMethod = "printMemBOption";
4090 let ParserMatchClass = MemBarrierOptOperand;
4091 let DecoderMethod = "DecodeMemBarrierOption";
4094 // memory barriers protect the atomic sequences
4095 let hasSideEffects = 1 in {
4096 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4097 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4098 Requires<[IsARM, HasDB]> {
4100 let Inst{31-4} = 0xf57ff05;
4101 let Inst{3-0} = opt;
4105 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4106 "dsb", "\t$opt", []>,
4107 Requires<[IsARM, HasDB]> {
4109 let Inst{31-4} = 0xf57ff04;
4110 let Inst{3-0} = opt;
4113 // ISB has only full system option
4114 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4115 "isb", "\t$opt", []>,
4116 Requires<[IsARM, HasDB]> {
4118 let Inst{31-4} = 0xf57ff06;
4119 let Inst{3-0} = opt;
4122 // Pseudo instruction that combines movs + predicated rsbmi
4123 // to implement integer ABS
4124 let usesCustomInserter = 1, Defs = [CPSR] in {
4125 def ABS : ARMPseudoInst<
4126 (outs GPR:$dst), (ins GPR:$src),
4127 8, NoItinerary, []>;
4130 let usesCustomInserter = 1 in {
4131 let Defs = [CPSR] in {
4132 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4133 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4134 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4135 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4136 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4137 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4138 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4139 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4140 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4141 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4142 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4143 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4144 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4145 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4146 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4147 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4148 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4149 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4150 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4151 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4152 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4153 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4154 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4155 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4156 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4157 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4158 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4159 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4160 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4161 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4162 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4163 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4164 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4165 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4166 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4167 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4168 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4169 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4170 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4171 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4172 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4173 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4174 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4175 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4176 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4177 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4178 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4179 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4180 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4181 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4182 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4183 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4184 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4185 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4186 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4187 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4188 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4189 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4190 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4191 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4192 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4193 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4194 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4195 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4196 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4197 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4198 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4199 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4200 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4201 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4202 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4203 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4204 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4205 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4206 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4207 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4208 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4209 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4210 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4211 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4212 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4213 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4214 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4215 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4216 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4217 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4218 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4219 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4220 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4221 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4223 def ATOMIC_SWAP_I8 : PseudoInst<
4224 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4225 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4226 def ATOMIC_SWAP_I16 : PseudoInst<
4227 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4228 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4229 def ATOMIC_SWAP_I32 : PseudoInst<
4230 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4231 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4233 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4234 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4235 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4236 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4237 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4238 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4239 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4240 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4241 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4245 let mayLoad = 1 in {
4246 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4248 "ldrexb", "\t$Rt, $addr", []>;
4249 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4250 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4251 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4252 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4253 let hasExtraDefRegAllocReq = 1 in
4254 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4255 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4256 let DecoderMethod = "DecodeDoubleRegLoad";
4260 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4261 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4262 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4263 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4264 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4265 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4266 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4267 let hasExtraSrcRegAllocReq = 1 in
4268 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4269 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4270 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4271 let DecoderMethod = "DecodeDoubleRegStore";
4276 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4277 Requires<[IsARM, HasV7]> {
4278 let Inst{31-0} = 0b11110101011111111111000000011111;
4281 // SWP/SWPB are deprecated in V6/V7.
4282 let mayLoad = 1, mayStore = 1 in {
4283 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4285 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4289 //===----------------------------------------------------------------------===//
4290 // Coprocessor Instructions.
4293 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4294 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4295 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4296 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4297 imm:$CRm, imm:$opc2)]> {
4305 let Inst{3-0} = CRm;
4307 let Inst{7-5} = opc2;
4308 let Inst{11-8} = cop;
4309 let Inst{15-12} = CRd;
4310 let Inst{19-16} = CRn;
4311 let Inst{23-20} = opc1;
4314 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4315 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4316 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4317 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4318 imm:$CRm, imm:$opc2)]> {
4319 let Inst{31-28} = 0b1111;
4327 let Inst{3-0} = CRm;
4329 let Inst{7-5} = opc2;
4330 let Inst{11-8} = cop;
4331 let Inst{15-12} = CRd;
4332 let Inst{19-16} = CRn;
4333 let Inst{23-20} = opc1;
4336 class ACI<dag oops, dag iops, string opc, string asm,
4337 IndexMode im = IndexModeNone>
4338 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4340 let Inst{27-25} = 0b110;
4342 class ACInoP<dag oops, dag iops, string opc, string asm,
4343 IndexMode im = IndexModeNone>
4344 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4346 let Inst{31-28} = 0b1111;
4347 let Inst{27-25} = 0b110;
4349 multiclass LdStCop<bit load, bit Dbit, string asm> {
4350 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4351 asm, "\t$cop, $CRd, $addr"> {
4355 let Inst{24} = 1; // P = 1
4356 let Inst{23} = addr{8};
4357 let Inst{22} = Dbit;
4358 let Inst{21} = 0; // W = 0
4359 let Inst{20} = load;
4360 let Inst{19-16} = addr{12-9};
4361 let Inst{15-12} = CRd;
4362 let Inst{11-8} = cop;
4363 let Inst{7-0} = addr{7-0};
4364 let DecoderMethod = "DecodeCopMemInstruction";
4366 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4367 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4371 let Inst{24} = 1; // P = 1
4372 let Inst{23} = addr{8};
4373 let Inst{22} = Dbit;
4374 let Inst{21} = 1; // W = 1
4375 let Inst{20} = load;
4376 let Inst{19-16} = addr{12-9};
4377 let Inst{15-12} = CRd;
4378 let Inst{11-8} = cop;
4379 let Inst{7-0} = addr{7-0};
4380 let DecoderMethod = "DecodeCopMemInstruction";
4382 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4383 postidx_imm8s4:$offset),
4384 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4389 let Inst{24} = 0; // P = 0
4390 let Inst{23} = offset{8};
4391 let Inst{22} = Dbit;
4392 let Inst{21} = 1; // W = 1
4393 let Inst{20} = load;
4394 let Inst{19-16} = addr;
4395 let Inst{15-12} = CRd;
4396 let Inst{11-8} = cop;
4397 let Inst{7-0} = offset{7-0};
4398 let DecoderMethod = "DecodeCopMemInstruction";
4400 def _OPTION : ACI<(outs),
4401 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4402 coproc_option_imm:$option),
4403 asm, "\t$cop, $CRd, $addr, $option"> {
4408 let Inst{24} = 0; // P = 0
4409 let Inst{23} = 1; // U = 1
4410 let Inst{22} = Dbit;
4411 let Inst{21} = 0; // W = 0
4412 let Inst{20} = load;
4413 let Inst{19-16} = addr;
4414 let Inst{15-12} = CRd;
4415 let Inst{11-8} = cop;
4416 let Inst{7-0} = option;
4417 let DecoderMethod = "DecodeCopMemInstruction";
4420 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4421 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4422 asm, "\t$cop, $CRd, $addr"> {
4426 let Inst{24} = 1; // P = 1
4427 let Inst{23} = addr{8};
4428 let Inst{22} = Dbit;
4429 let Inst{21} = 0; // W = 0
4430 let Inst{20} = load;
4431 let Inst{19-16} = addr{12-9};
4432 let Inst{15-12} = CRd;
4433 let Inst{11-8} = cop;
4434 let Inst{7-0} = addr{7-0};
4435 let DecoderMethod = "DecodeCopMemInstruction";
4437 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4438 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4442 let Inst{24} = 1; // P = 1
4443 let Inst{23} = addr{8};
4444 let Inst{22} = Dbit;
4445 let Inst{21} = 1; // W = 1
4446 let Inst{20} = load;
4447 let Inst{19-16} = addr{12-9};
4448 let Inst{15-12} = CRd;
4449 let Inst{11-8} = cop;
4450 let Inst{7-0} = addr{7-0};
4451 let DecoderMethod = "DecodeCopMemInstruction";
4453 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4454 postidx_imm8s4:$offset),
4455 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4460 let Inst{24} = 0; // P = 0
4461 let Inst{23} = offset{8};
4462 let Inst{22} = Dbit;
4463 let Inst{21} = 1; // W = 1
4464 let Inst{20} = load;
4465 let Inst{19-16} = addr;
4466 let Inst{15-12} = CRd;
4467 let Inst{11-8} = cop;
4468 let Inst{7-0} = offset{7-0};
4469 let DecoderMethod = "DecodeCopMemInstruction";
4471 def _OPTION : ACInoP<(outs),
4472 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4473 coproc_option_imm:$option),
4474 asm, "\t$cop, $CRd, $addr, $option"> {
4479 let Inst{24} = 0; // P = 0
4480 let Inst{23} = 1; // U = 1
4481 let Inst{22} = Dbit;
4482 let Inst{21} = 0; // W = 0
4483 let Inst{20} = load;
4484 let Inst{19-16} = addr;
4485 let Inst{15-12} = CRd;
4486 let Inst{11-8} = cop;
4487 let Inst{7-0} = option;
4488 let DecoderMethod = "DecodeCopMemInstruction";
4492 defm LDC : LdStCop <1, 0, "ldc">;
4493 defm LDCL : LdStCop <1, 1, "ldcl">;
4494 defm STC : LdStCop <0, 0, "stc">;
4495 defm STCL : LdStCop <0, 1, "stcl">;
4496 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4497 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4498 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4499 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4501 //===----------------------------------------------------------------------===//
4502 // Move between coprocessor and ARM core register.
4505 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4507 : ABI<0b1110, oops, iops, NoItinerary, opc,
4508 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4509 let Inst{20} = direction;
4519 let Inst{15-12} = Rt;
4520 let Inst{11-8} = cop;
4521 let Inst{23-21} = opc1;
4522 let Inst{7-5} = opc2;
4523 let Inst{3-0} = CRm;
4524 let Inst{19-16} = CRn;
4527 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4529 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4530 c_imm:$CRm, imm0_7:$opc2),
4531 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4532 imm:$CRm, imm:$opc2)]>;
4533 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4534 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4535 c_imm:$CRm, 0, pred:$p)>;
4536 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4538 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4540 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4541 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4542 c_imm:$CRm, 0, pred:$p)>;
4544 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4545 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4547 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4549 : ABXI<0b1110, oops, iops, NoItinerary,
4550 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4551 let Inst{31-28} = 0b1111;
4552 let Inst{20} = direction;
4562 let Inst{15-12} = Rt;
4563 let Inst{11-8} = cop;
4564 let Inst{23-21} = opc1;
4565 let Inst{7-5} = opc2;
4566 let Inst{3-0} = CRm;
4567 let Inst{19-16} = CRn;
4570 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4572 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4573 c_imm:$CRm, imm0_7:$opc2),
4574 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4575 imm:$CRm, imm:$opc2)]>;
4576 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4577 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4579 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4581 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4583 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4584 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4587 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4588 imm:$CRm, imm:$opc2),
4589 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4591 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4592 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4593 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4594 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4595 let Inst{23-21} = 0b010;
4596 let Inst{20} = direction;
4604 let Inst{15-12} = Rt;
4605 let Inst{19-16} = Rt2;
4606 let Inst{11-8} = cop;
4607 let Inst{7-4} = opc1;
4608 let Inst{3-0} = CRm;
4611 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4612 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4614 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4616 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4617 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4618 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4619 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4620 let Inst{31-28} = 0b1111;
4621 let Inst{23-21} = 0b010;
4622 let Inst{20} = direction;
4630 let Inst{15-12} = Rt;
4631 let Inst{19-16} = Rt2;
4632 let Inst{11-8} = cop;
4633 let Inst{7-4} = opc1;
4634 let Inst{3-0} = CRm;
4637 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4638 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4640 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4642 //===----------------------------------------------------------------------===//
4643 // Move between special register and ARM core register
4646 // Move to ARM core register from Special Register
4647 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4648 "mrs", "\t$Rd, apsr", []> {
4650 let Inst{23-16} = 0b00001111;
4651 let Inst{15-12} = Rd;
4652 let Inst{7-4} = 0b0000;
4655 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4657 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4658 "mrs", "\t$Rd, spsr", []> {
4660 let Inst{23-16} = 0b01001111;
4661 let Inst{15-12} = Rd;
4662 let Inst{7-4} = 0b0000;
4665 // Move from ARM core register to Special Register
4667 // No need to have both system and application versions, the encodings are the
4668 // same and the assembly parser has no way to distinguish between them. The mask
4669 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4670 // the mask with the fields to be accessed in the special register.
4671 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4672 "msr", "\t$mask, $Rn", []> {
4677 let Inst{22} = mask{4}; // R bit
4678 let Inst{21-20} = 0b10;
4679 let Inst{19-16} = mask{3-0};
4680 let Inst{15-12} = 0b1111;
4681 let Inst{11-4} = 0b00000000;
4685 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4686 "msr", "\t$mask, $a", []> {
4691 let Inst{22} = mask{4}; // R bit
4692 let Inst{21-20} = 0b10;
4693 let Inst{19-16} = mask{3-0};
4694 let Inst{15-12} = 0b1111;
4698 //===----------------------------------------------------------------------===//
4702 // __aeabi_read_tp preserves the registers r1-r3.
4703 // This is a pseudo inst so that we can get the encoding right,
4704 // complete with fixup for the aeabi_read_tp function.
4706 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4707 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4708 [(set R0, ARMthread_pointer)]>;
4711 //===----------------------------------------------------------------------===//
4712 // SJLJ Exception handling intrinsics
4713 // eh_sjlj_setjmp() is an instruction sequence to store the return
4714 // address and save #0 in R0 for the non-longjmp case.
4715 // Since by its nature we may be coming from some other function to get
4716 // here, and we're using the stack frame for the containing function to
4717 // save/restore registers, we can't keep anything live in regs across
4718 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4719 // when we get here from a longjmp(). We force everything out of registers
4720 // except for our own input by listing the relevant registers in Defs. By
4721 // doing so, we also cause the prologue/epilogue code to actively preserve
4722 // all of the callee-saved resgisters, which is exactly what we want.
4723 // A constant value is passed in $val, and we use the location as a scratch.
4725 // These are pseudo-instructions and are lowered to individual MC-insts, so
4726 // no encoding information is necessary.
4728 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4729 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4730 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4731 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4733 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4734 Requires<[IsARM, HasVFP2]>;
4738 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4739 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4740 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4742 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4743 Requires<[IsARM, NoVFP]>;
4746 // FIXME: Non-IOS version(s)
4747 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4748 Defs = [ R7, LR, SP ] in {
4749 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4751 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4752 Requires<[IsARM, IsIOS]>;
4755 // eh.sjlj.dispatchsetup pseudo-instructions.
4756 // These pseudos are used for both ARM and Thumb2. Any differences are
4757 // handled when the pseudo is expanded (which happens before any passes
4758 // that need the instruction size).
4760 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4761 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4763 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4766 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4768 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
4771 //===----------------------------------------------------------------------===//
4772 // Non-Instruction Patterns
4775 // ARMv4 indirect branch using (MOVr PC, dst)
4776 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4777 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4778 4, IIC_Br, [(brind GPR:$dst)],
4779 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4780 Requires<[IsARM, NoV4T]>;
4782 // Large immediate handling.
4784 // 32-bit immediate using two piece so_imms or movw + movt.
4785 // This is a single pseudo instruction, the benefit is that it can be remat'd
4786 // as a single unit instead of having to handle reg inputs.
4787 // FIXME: Remove this when we can do generalized remat.
4788 let isReMaterializable = 1, isMoveImm = 1 in
4789 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4790 [(set GPR:$dst, (arm_i32imm:$src))]>,
4793 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4794 // It also makes it possible to rematerialize the instructions.
4795 // FIXME: Remove this when we can do generalized remat and when machine licm
4796 // can properly the instructions.
4797 let isReMaterializable = 1 in {
4798 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4800 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4801 Requires<[IsARM, UseMovt]>;
4803 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4805 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4806 Requires<[IsARM, UseMovt]>;
4808 let AddedComplexity = 10 in
4809 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4811 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4812 Requires<[IsARM, UseMovt]>;
4813 } // isReMaterializable
4815 // ConstantPool, GlobalAddress, and JumpTable
4816 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4817 Requires<[IsARM, DontUseMovt]>;
4818 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4819 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4820 Requires<[IsARM, UseMovt]>;
4821 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4822 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4824 // TODO: add,sub,and, 3-instr forms?
4826 // Tail calls. These patterns also apply to Thumb mode.
4827 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4828 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4829 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4832 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4833 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4834 (BMOVPCB_CALL texternalsym:$func)>;
4836 // zextload i1 -> zextload i8
4837 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4838 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4840 // extload -> zextload
4841 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4842 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4843 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4844 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4846 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4848 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4849 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4852 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4853 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4854 (SMULBB GPR:$a, GPR:$b)>;
4855 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4856 (SMULBB GPR:$a, GPR:$b)>;
4857 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4858 (sra GPR:$b, (i32 16))),
4859 (SMULBT GPR:$a, GPR:$b)>;
4860 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4861 (SMULBT GPR:$a, GPR:$b)>;
4862 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4863 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4864 (SMULTB GPR:$a, GPR:$b)>;
4865 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4866 (SMULTB GPR:$a, GPR:$b)>;
4867 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4869 (SMULWB GPR:$a, GPR:$b)>;
4870 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4871 (SMULWB GPR:$a, GPR:$b)>;
4873 def : ARMV5TEPat<(add GPR:$acc,
4874 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4875 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4876 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4877 def : ARMV5TEPat<(add GPR:$acc,
4878 (mul sext_16_node:$a, sext_16_node:$b)),
4879 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4880 def : ARMV5TEPat<(add GPR:$acc,
4881 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4882 (sra GPR:$b, (i32 16)))),
4883 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4884 def : ARMV5TEPat<(add GPR:$acc,
4885 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4886 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4887 def : ARMV5TEPat<(add GPR:$acc,
4888 (mul (sra GPR:$a, (i32 16)),
4889 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4890 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4891 def : ARMV5TEPat<(add GPR:$acc,
4892 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4893 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4894 def : ARMV5TEPat<(add GPR:$acc,
4895 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4897 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4898 def : ARMV5TEPat<(add GPR:$acc,
4899 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4900 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4903 // Pre-v7 uses MCR for synchronization barriers.
4904 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4905 Requires<[IsARM, HasV6]>;
4907 // SXT/UXT with no rotate
4908 let AddedComplexity = 16 in {
4909 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4910 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4911 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4912 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4913 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4914 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4915 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4918 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4919 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4921 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4922 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4923 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4924 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4926 // Atomic load/store patterns
4927 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4928 (LDRBrs ldst_so_reg:$src)>;
4929 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4930 (LDRBi12 addrmode_imm12:$src)>;
4931 def : ARMPat<(atomic_load_16 addrmode3:$src),
4932 (LDRH addrmode3:$src)>;
4933 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4934 (LDRrs ldst_so_reg:$src)>;
4935 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4936 (LDRi12 addrmode_imm12:$src)>;
4937 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4938 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4939 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4940 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4941 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4942 (STRH GPR:$val, addrmode3:$ptr)>;
4943 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4944 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4945 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4946 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4949 //===----------------------------------------------------------------------===//
4953 include "ARMInstrThumb.td"
4955 //===----------------------------------------------------------------------===//
4959 include "ARMInstrThumb2.td"
4961 //===----------------------------------------------------------------------===//
4962 // Floating Point Support
4965 include "ARMInstrVFP.td"
4967 //===----------------------------------------------------------------------===//
4968 // Advanced SIMD (NEON) Support
4971 include "ARMInstrNEON.td"
4973 //===----------------------------------------------------------------------===//
4974 // Assembler aliases
4978 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4979 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4980 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4982 // System instructions
4983 def : MnemonicAlias<"swi", "svc">;
4985 // Load / Store Multiple
4986 def : MnemonicAlias<"ldmfd", "ldm">;
4987 def : MnemonicAlias<"ldmia", "ldm">;
4988 def : MnemonicAlias<"ldmea", "ldmdb">;
4989 def : MnemonicAlias<"stmfd", "stmdb">;
4990 def : MnemonicAlias<"stmia", "stm">;
4991 def : MnemonicAlias<"stmea", "stm">;
4993 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4994 // shift amount is zero (i.e., unspecified).
4995 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4996 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4997 Requires<[IsARM, HasV6]>;
4998 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4999 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5000 Requires<[IsARM, HasV6]>;
5002 // PUSH/POP aliases for STM/LDM
5003 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5004 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5006 // SSAT/USAT optional shift operand.
5007 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5008 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5009 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5010 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5013 // Extend instruction optional rotate operand.
5014 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5015 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5016 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5017 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5018 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5019 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5020 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5021 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5022 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5023 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5024 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5025 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5027 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5028 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5029 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5030 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5031 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5032 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5033 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5034 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5035 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5036 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5037 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5038 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5042 def : MnemonicAlias<"rfefa", "rfeda">;
5043 def : MnemonicAlias<"rfeea", "rfedb">;
5044 def : MnemonicAlias<"rfefd", "rfeia">;
5045 def : MnemonicAlias<"rfeed", "rfeib">;
5046 def : MnemonicAlias<"rfe", "rfeia">;
5049 def : MnemonicAlias<"srsfa", "srsda">;
5050 def : MnemonicAlias<"srsea", "srsdb">;
5051 def : MnemonicAlias<"srsfd", "srsia">;
5052 def : MnemonicAlias<"srsed", "srsib">;
5053 def : MnemonicAlias<"srs", "srsia">;
5056 def : MnemonicAlias<"qsubaddx", "qsax">;
5058 def : MnemonicAlias<"saddsubx", "sasx">;
5059 // SHASX == SHADDSUBX
5060 def : MnemonicAlias<"shaddsubx", "shasx">;
5061 // SHSAX == SHSUBADDX
5062 def : MnemonicAlias<"shsubaddx", "shsax">;
5064 def : MnemonicAlias<"ssubaddx", "ssax">;
5066 def : MnemonicAlias<"uaddsubx", "uasx">;
5067 // UHASX == UHADDSUBX
5068 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5069 // UHSAX == UHSUBADDX
5070 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5071 // UQASX == UQADDSUBX
5072 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5073 // UQSAX == UQSUBADDX
5074 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5076 def : MnemonicAlias<"usubaddx", "usax">;
5078 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5080 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5081 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5082 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5083 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5084 // Same for AND <--> BIC
5085 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5086 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5087 pred:$p, cc_out:$s)>;
5088 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5089 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5090 pred:$p, cc_out:$s)>;
5091 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5092 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5093 pred:$p, cc_out:$s)>;
5094 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5095 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5096 pred:$p, cc_out:$s)>;
5098 // Likewise, "add Rd, so_imm_neg" -> sub
5099 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5100 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5101 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5102 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5103 // Same for CMP <--> CMN via so_imm_neg
5104 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5105 (CMNzri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5106 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5107 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5109 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5110 // LSR, ROR, and RRX instructions.
5111 // FIXME: We need C++ parser hooks to map the alias to the MOV
5112 // encoding. It seems we should be able to do that sort of thing
5113 // in tblgen, but it could get ugly.
5114 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5115 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5117 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5118 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5120 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5121 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5123 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5124 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5126 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5127 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5128 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5129 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5131 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5132 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5134 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5135 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5137 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5138 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5140 // shifter instructions also support a two-operand form.
5141 def : ARMInstAlias<"asr${s}${p} $Rm, $imm",
5142 (ASRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
5143 def : ARMInstAlias<"lsr${s}${p} $Rm, $imm",
5144 (LSRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
5145 def : ARMInstAlias<"lsl${s}${p} $Rm, $imm",
5146 (LSLi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
5147 def : ARMInstAlias<"ror${s}${p} $Rm, $imm",
5148 (RORi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
5149 def : ARMInstAlias<"asr${s}${p} $Rn, $Rm",
5150 (ASRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5152 def : ARMInstAlias<"lsr${s}${p} $Rn, $Rm",
5153 (LSRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5155 def : ARMInstAlias<"lsl${s}${p} $Rn, $Rm",
5156 (LSLr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5158 def : ARMInstAlias<"ror${s}${p} $Rn, $Rm",
5159 (RORr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5163 // 'mul' instruction can be specified with only two operands.
5164 def : ARMInstAlias<"mul${s}${p} $Rn, $Rm",
5165 (MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p, cc_out:$s)>;
5167 // "neg" is and alias for "rsb rd, rn, #0"
5168 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5169 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5171 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5172 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5173 Requires<[IsARM, NoV6]>;
5175 // UMULL/SMULL are available on all arches, but the instruction definitions
5176 // need difference constraints pre-v6. Use these aliases for the assembly
5177 // parsing on pre-v6.
5178 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5179 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5180 Requires<[IsARM, NoV6]>;
5181 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5182 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5183 Requires<[IsARM, NoV6]>;
5185 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5187 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;