1 //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMINSTRUCTIONINFO_H
15 #define ARMINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "ARMRegisterInfo.h"
24 /// ARMII - This namespace holds all of the target specific flags that
25 /// instruction info tracks.
29 //===------------------------------------------------------------------===//
32 //===------------------------------------------------------------------===//
33 // This four-bit field describes the addressing mode used.
45 AddrModeTs = 9, // i8 * 4 for pc and sp relative data
47 // Size* - Flags to keep track of the size of an instruction.
49 SizeMask = 7 << SizeShift,
50 SizeSpecial = 1, // 0 byte pseudo or special case.
55 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
58 IndexModeMask = 3 << IndexModeShift,
62 //===------------------------------------------------------------------===//
65 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
66 // it doesn't have a Rn operand.
69 //===------------------------------------------------------------------===//
70 // Instruction encoding formats.
73 FormMask = 0x1f << FormShift,
75 // Pseudo instructions
76 Pseudo = 1 << FormShift,
78 // Multiply instructions
79 MulFrm = 2 << FormShift,
81 // Branch instructions
82 BrFrm = 3 << FormShift,
83 BrMiscFrm = 4 << FormShift,
85 // Data Processing instructions
86 DPFrm = 5 << FormShift,
87 DPSoRegFrm = 6 << FormShift,
90 LdStFrm = 7 << FormShift,
91 LdStMiscFrm = 8 << FormShift,
92 LdStMulFrm = 9 << FormShift,
94 // Miscellaneous arithmetic instructions
95 ArithMiscFrm = 10 << FormShift,
97 // Extend instructions
98 ExtFrm = 11 << FormShift,
101 VFPUnaryFrm = 12 << FormShift,
102 VFPBinaryFrm = 13 << FormShift,
103 VFPConv1Frm = 14 << FormShift,
104 VFPConv2Frm = 15 << FormShift,
105 VFPConv3Frm = 16 << FormShift,
106 VFPConv4Frm = 17 << FormShift,
107 VFPConv5Frm = 18 << FormShift,
108 VFPLdStFrm = 19 << FormShift,
109 VFPLdStMulFrm = 20 << FormShift,
110 VFPMiscFrm = 21 << FormShift,
113 ThumbFrm = 22 << FormShift,
115 //===------------------------------------------------------------------===//
116 // Field shifts - such shifts are used to set field while generating
117 // machine instructions.
141 class ARMInstrInfo : public TargetInstrInfoImpl {
142 const ARMRegisterInfo RI;
144 explicit ARMInstrInfo(const ARMSubtarget &STI);
146 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
147 /// such, whenever a client has an instance of instruction info, it should
148 /// always be able to get register info as well (through this method).
150 virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
152 /// getPointerRegClass - Return the register class to use to hold pointers.
153 /// This is used for addressing modes.
154 virtual const TargetRegisterClass *getPointerRegClass() const;
156 /// Return true if the instruction is a register to register move and
157 /// leave the source and dest operands in the passed parameters.
159 virtual bool isMoveInstr(const MachineInstr &MI,
160 unsigned &SrcReg, unsigned &DstReg) const;
161 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
162 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
164 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
165 unsigned DestReg, const MachineInstr *Orig) const;
167 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
168 MachineBasicBlock::iterator &MBBI,
169 LiveVariables *LV) const;
172 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
173 MachineBasicBlock *&FBB,
174 SmallVectorImpl<MachineOperand> &Cond) const;
175 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
176 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
177 MachineBasicBlock *FBB,
178 const SmallVectorImpl<MachineOperand> &Cond) const;
179 virtual bool copyRegToReg(MachineBasicBlock &MBB,
180 MachineBasicBlock::iterator I,
181 unsigned DestReg, unsigned SrcReg,
182 const TargetRegisterClass *DestRC,
183 const TargetRegisterClass *SrcRC) const;
184 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
185 MachineBasicBlock::iterator MBBI,
186 unsigned SrcReg, bool isKill, int FrameIndex,
187 const TargetRegisterClass *RC) const;
189 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
190 SmallVectorImpl<MachineOperand> &Addr,
191 const TargetRegisterClass *RC,
192 SmallVectorImpl<MachineInstr*> &NewMIs) const;
194 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
195 MachineBasicBlock::iterator MBBI,
196 unsigned DestReg, int FrameIndex,
197 const TargetRegisterClass *RC) const;
199 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
200 SmallVectorImpl<MachineOperand> &Addr,
201 const TargetRegisterClass *RC,
202 SmallVectorImpl<MachineInstr*> &NewMIs) const;
203 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
204 MachineBasicBlock::iterator MI,
205 const std::vector<CalleeSavedInfo> &CSI) const;
206 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
207 MachineBasicBlock::iterator MI,
208 const std::vector<CalleeSavedInfo> &CSI) const;
210 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
212 const SmallVectorImpl<unsigned> &Ops,
213 int FrameIndex) const;
215 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
217 const SmallVectorImpl<unsigned> &Ops,
218 MachineInstr* LoadMI) const {
222 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
223 const SmallVectorImpl<unsigned> &Ops) const;
225 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
227 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
229 // Predication support.
230 virtual bool isPredicated(const MachineInstr *MI) const;
232 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
233 int PIdx = MI->findFirstPredOperandIdx();
234 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
239 bool PredicateInstruction(MachineInstr *MI,
240 const SmallVectorImpl<MachineOperand> &Pred) const;
243 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
244 const SmallVectorImpl<MachineOperand> &Pred2) const;
246 virtual bool DefinesPredicate(MachineInstr *MI,
247 std::vector<MachineOperand> &Pred) const;
249 /// GetInstSize - Returns the size of the specified MachineInstr.
251 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;