Fix address mode 3 immediate offset mode encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59109 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index c842a961efc6fed13fff66cf825e2da1cf2feae8..e877aa707aad69c894912e31d203a7944e1d9f3e 100644 (file)
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -736,11 +736,11 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
   // Set bit[3:0] to the corresponding Rm register
   Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
 
-  // if this instr is in scaled register offset/index instruction, set
+  // If this instr is in scaled register offset/index instruction, set
   // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
   if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
-    Binary |= getShiftOp(AM2Opc) << 5;  // shift
-    Binary |= ShImm              << 7;  // shift_immed
+    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
+    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
   }
 
   emitWordLE(Binary);
@@ -792,8 +792,8 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
   Binary |= 1 << ARMII::AM3_I_BitShift;
   if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
     // Set operands
-    Binary |= (ImmOffs >> 4) << 8;  // immedH
-    Binary |= (ImmOffs & ~0xF);     // immedL
+    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
+    Binary |= (ImmOffs & 0xF);                      // immedL
   }
 
   emitWordLE(Binary);

diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h
index 4a0065dce519565d8b5b35b5fe25aba7d10fe583..1ef965c5556a30c4f031eeb1e2d3dc33861c5b70 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.h
+++ b/lib/Target/ARM/ARMInstrInfo.h
@@ -116,8 +116,10 @@ namespace ARMII {
     // Field shifts - such shifts are used to set field while generating
     // machine instructions.
     M_BitShift     = 5,
+    ShiftImmShift  = 5,
     ShiftShift     = 7,
     N_BitShift     = 7,
+    ImmHiShift     = 8,
     SoRotImmShift  = 8,
     RegRsShift     = 8,
     ExtRotImmShift = 10,