1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMCallingConv.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMPerfectShuffle.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalValue.h"
40 #include "llvm/IR/IRBuilder.h"
41 #include "llvm/IR/Instruction.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/IR/Type.h"
45 #include "llvm/MC/MCSectionMachO.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 #define DEBUG_TYPE "arm-isel"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
58 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
61 EnableARMLongCalls("arm-long-calls", cl::Hidden,
62 cl::desc("Generate calls via indirect call instructions"),
66 ARMInterworking("arm-interworking", cl::Hidden,
67 cl::desc("Enable / disable ARM interworking (for debugging only)"),
71 class ARMCCState : public CCState {
73 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
74 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
76 : CCState(CC, isVarArg, MF, locs, C) {
77 assert(((PC == Call) || (PC == Prologue)) &&
78 "ARMCCState users must specify whether their context is call"
79 "or prologue generation.");
85 // The APCS parameter registers.
86 static const MCPhysReg GPRArgRegs[] = {
87 ARM::R0, ARM::R1, ARM::R2, ARM::R3
90 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
91 MVT PromotedBitwiseVT) {
92 if (VT != PromotedLdStVT) {
93 setOperationAction(ISD::LOAD, VT, Promote);
94 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
96 setOperationAction(ISD::STORE, VT, Promote);
97 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
100 MVT ElemTy = VT.getVectorElementType();
101 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
102 setOperationAction(ISD::SETCC, VT, Custom);
103 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
104 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
105 if (ElemTy == MVT::i32) {
106 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
107 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
108 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
109 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
111 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
112 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
113 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
114 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
116 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
117 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
118 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
119 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
120 setOperationAction(ISD::SELECT, VT, Expand);
121 setOperationAction(ISD::SELECT_CC, VT, Expand);
122 setOperationAction(ISD::VSELECT, VT, Expand);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
124 if (VT.isInteger()) {
125 setOperationAction(ISD::SHL, VT, Custom);
126 setOperationAction(ISD::SRA, VT, Custom);
127 setOperationAction(ISD::SRL, VT, Custom);
130 // Promote all bit-wise operations.
131 if (VT.isInteger() && VT != PromotedBitwiseVT) {
132 setOperationAction(ISD::AND, VT, Promote);
133 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
134 setOperationAction(ISD::OR, VT, Promote);
135 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
136 setOperationAction(ISD::XOR, VT, Promote);
137 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
140 // Neon does not support vector divide/remainder operations.
141 setOperationAction(ISD::SDIV, VT, Expand);
142 setOperationAction(ISD::UDIV, VT, Expand);
143 setOperationAction(ISD::FDIV, VT, Expand);
144 setOperationAction(ISD::SREM, VT, Expand);
145 setOperationAction(ISD::UREM, VT, Expand);
146 setOperationAction(ISD::FREM, VT, Expand);
149 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
150 addRegisterClass(VT, &ARM::DPRRegClass);
151 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
154 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
155 addRegisterClass(VT, &ARM::DPairRegClass);
156 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
159 ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM)
160 : TargetLowering(TM) {
161 Subtarget = &TM.getSubtarget<ARMSubtarget>();
162 RegInfo = TM.getSubtargetImpl()->getRegisterInfo();
163 Itins = TM.getSubtargetImpl()->getInstrItineraryData();
165 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
167 if (Subtarget->isTargetMachO()) {
168 // Uses VFP for Thumb libfuncs if available.
169 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
170 Subtarget->hasARMOps() && !TM.Options.UseSoftFloat) {
171 // Single-precision floating-point arithmetic.
172 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
173 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
174 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
175 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
177 // Double-precision floating-point arithmetic.
178 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
179 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
180 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
181 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
183 // Single-precision comparisons.
184 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
185 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
186 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
187 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
188 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
189 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
190 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
191 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
193 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
194 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
195 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
196 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
199 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
200 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
202 // Double-precision comparisons.
203 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
204 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
205 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
206 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
207 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
208 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
209 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
210 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
212 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
218 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
219 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
221 // Floating-point to integer conversions.
222 // i64 conversions are done via library routines even when generating VFP
223 // instructions, so use the same ones.
224 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
225 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
226 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
227 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
229 // Conversions between floating types.
230 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
231 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
233 // Integer to floating-point conversions.
234 // i64 conversions are done via library routines even when generating VFP
235 // instructions, so use the same ones.
236 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
237 // e.g., __floatunsidf vs. __floatunssidfvfp.
238 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
239 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
240 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
241 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
245 // These libcalls are not available in 32-bit.
246 setLibcallName(RTLIB::SHL_I128, nullptr);
247 setLibcallName(RTLIB::SRL_I128, nullptr);
248 setLibcallName(RTLIB::SRA_I128, nullptr);
250 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO() &&
251 !Subtarget->isTargetWindows()) {
252 static const struct {
253 const RTLIB::Libcall Op;
254 const char * const Name;
255 const CallingConv::ID CC;
256 const ISD::CondCode Cond;
258 // Double-precision floating-point arithmetic helper functions
259 // RTABI chapter 4.1.2, Table 2
260 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
261 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
262 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
263 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
265 // Double-precision floating-point comparison helper functions
266 // RTABI chapter 4.1.2, Table 3
267 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
268 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
269 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
270 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
271 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
272 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
273 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
274 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
276 // Single-precision floating-point arithmetic helper functions
277 // RTABI chapter 4.1.2, Table 4
278 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
279 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
280 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
281 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
283 // Single-precision floating-point comparison helper functions
284 // RTABI chapter 4.1.2, Table 5
285 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
286 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
287 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
288 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
289 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
290 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
291 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
292 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
294 // Floating-point to integer conversions.
295 // RTABI chapter 4.1.2, Table 6
296 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
297 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
298 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
299 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
300 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
301 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
302 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
303 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
305 // Conversions between floating types.
306 // RTABI chapter 4.1.2, Table 7
307 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
308 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
309 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
311 // Integer to floating-point conversions.
312 // RTABI chapter 4.1.2, Table 8
313 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
314 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
315 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
316 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
317 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
318 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
319 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
320 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
322 // Long long helper functions
323 // RTABI chapter 4.2, Table 9
324 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
325 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
326 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
327 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
329 // Integer division functions
330 // RTABI chapter 4.3.1
331 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
332 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
333 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
334 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
335 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
336 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
337 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
338 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
341 // RTABI chapter 4.3.4
342 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
343 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
344 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
347 for (const auto &LC : LibraryCalls) {
348 setLibcallName(LC.Op, LC.Name);
349 setLibcallCallingConv(LC.Op, LC.CC);
350 if (LC.Cond != ISD::SETCC_INVALID)
351 setCmpLibcallCC(LC.Op, LC.Cond);
355 if (Subtarget->isTargetWindows()) {
356 static const struct {
357 const RTLIB::Libcall Op;
358 const char * const Name;
359 const CallingConv::ID CC;
361 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
362 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
363 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
364 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
365 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
366 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
367 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
368 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
371 for (const auto &LC : LibraryCalls) {
372 setLibcallName(LC.Op, LC.Name);
373 setLibcallCallingConv(LC.Op, LC.CC);
377 // Use divmod compiler-rt calls for iOS 5.0 and later.
378 if (Subtarget->getTargetTriple().isiOS() &&
379 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
380 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
381 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
384 // The half <-> float conversion functions are always soft-float, but are
385 // needed for some targets which use a hard-float calling convention by
387 if (Subtarget->isAAPCS_ABI()) {
388 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
393 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
394 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
397 if (Subtarget->isThumb1Only())
398 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
400 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
401 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
402 !Subtarget->isThumb1Only()) {
403 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
404 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
407 for (MVT VT : MVT::vector_valuetypes()) {
408 for (MVT InnerVT : MVT::vector_valuetypes()) {
409 setTruncStoreAction(VT, InnerVT, Expand);
410 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
411 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
412 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
415 setOperationAction(ISD::MULHS, VT, Expand);
416 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
417 setOperationAction(ISD::MULHU, VT, Expand);
418 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
420 setOperationAction(ISD::BSWAP, VT, Expand);
423 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
424 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
426 if (Subtarget->hasNEON()) {
427 addDRTypeForNEON(MVT::v2f32);
428 addDRTypeForNEON(MVT::v8i8);
429 addDRTypeForNEON(MVT::v4i16);
430 addDRTypeForNEON(MVT::v2i32);
431 addDRTypeForNEON(MVT::v1i64);
433 addQRTypeForNEON(MVT::v4f32);
434 addQRTypeForNEON(MVT::v2f64);
435 addQRTypeForNEON(MVT::v16i8);
436 addQRTypeForNEON(MVT::v8i16);
437 addQRTypeForNEON(MVT::v4i32);
438 addQRTypeForNEON(MVT::v2i64);
440 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
441 // neither Neon nor VFP support any arithmetic operations on it.
442 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
443 // supported for v4f32.
444 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
445 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
446 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
447 // FIXME: Code duplication: FDIV and FREM are expanded always, see
448 // ARMTargetLowering::addTypeForNEON method for details.
449 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
450 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
451 // FIXME: Create unittest.
452 // In another words, find a way when "copysign" appears in DAG with vector
454 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
455 // FIXME: Code duplication: SETCC has custom operation action, see
456 // ARMTargetLowering::addTypeForNEON method for details.
457 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
458 // FIXME: Create unittest for FNEG and for FABS.
459 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
460 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
461 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
462 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
463 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
464 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
465 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
466 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
467 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
468 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
469 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
470 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
471 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
472 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
473 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
474 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
475 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
476 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
477 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
479 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
480 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
481 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
482 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
483 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
484 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
485 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
486 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
487 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
488 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
489 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
490 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
491 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
492 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
493 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
495 // Mark v2f32 intrinsics.
496 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
497 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
498 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
499 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
500 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
501 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
502 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
503 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
504 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
505 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
506 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
507 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
508 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
509 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
510 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
512 // Neon does not support some operations on v1i64 and v2i64 types.
513 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
514 // Custom handling for some quad-vector types to detect VMULL.
515 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
516 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
517 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
518 // Custom handling for some vector types to avoid expensive expansions
519 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
520 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
521 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
522 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
523 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
524 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
525 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
526 // a destination type that is wider than the source, and nor does
527 // it have a FP_TO_[SU]INT instruction with a narrower destination than
529 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
530 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
531 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
532 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
534 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
535 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
537 // NEON does not have single instruction CTPOP for vectors with element
538 // types wider than 8-bits. However, custom lowering can leverage the
539 // v8i8/v16i8 vcnt instruction.
540 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
541 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
542 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
543 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
545 // NEON only has FMA instructions as of VFP4.
546 if (!Subtarget->hasVFP4()) {
547 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
548 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
551 setTargetDAGCombine(ISD::INTRINSIC_VOID);
552 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
553 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
554 setTargetDAGCombine(ISD::SHL);
555 setTargetDAGCombine(ISD::SRL);
556 setTargetDAGCombine(ISD::SRA);
557 setTargetDAGCombine(ISD::SIGN_EXTEND);
558 setTargetDAGCombine(ISD::ZERO_EXTEND);
559 setTargetDAGCombine(ISD::ANY_EXTEND);
560 setTargetDAGCombine(ISD::SELECT_CC);
561 setTargetDAGCombine(ISD::BUILD_VECTOR);
562 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
563 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
564 setTargetDAGCombine(ISD::STORE);
565 setTargetDAGCombine(ISD::FP_TO_SINT);
566 setTargetDAGCombine(ISD::FP_TO_UINT);
567 setTargetDAGCombine(ISD::FDIV);
568 setTargetDAGCombine(ISD::LOAD);
570 // It is legal to extload from v4i8 to v4i16 or v4i32.
571 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
572 MVT::v4i16, MVT::v2i16,
574 for (unsigned i = 0; i < 6; ++i) {
575 for (MVT VT : MVT::integer_vector_valuetypes()) {
576 setLoadExtAction(ISD::EXTLOAD, VT, Tys[i], Legal);
577 setLoadExtAction(ISD::ZEXTLOAD, VT, Tys[i], Legal);
578 setLoadExtAction(ISD::SEXTLOAD, VT, Tys[i], Legal);
583 // ARM and Thumb2 support UMLAL/SMLAL.
584 if (!Subtarget->isThumb1Only())
585 setTargetDAGCombine(ISD::ADDC);
587 if (Subtarget->isFPOnlySP()) {
588 // When targetting a floating-point unit with only single-precision
589 // operations, f64 is legal for the few double-precision instructions which
590 // are present However, no double-precision operations other than moves,
591 // loads and stores are provided by the hardware.
592 setOperationAction(ISD::FADD, MVT::f64, Expand);
593 setOperationAction(ISD::FSUB, MVT::f64, Expand);
594 setOperationAction(ISD::FMUL, MVT::f64, Expand);
595 setOperationAction(ISD::FMA, MVT::f64, Expand);
596 setOperationAction(ISD::FDIV, MVT::f64, Expand);
597 setOperationAction(ISD::FREM, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
599 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
600 setOperationAction(ISD::FNEG, MVT::f64, Expand);
601 setOperationAction(ISD::FABS, MVT::f64, Expand);
602 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
603 setOperationAction(ISD::FSIN, MVT::f64, Expand);
604 setOperationAction(ISD::FCOS, MVT::f64, Expand);
605 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
606 setOperationAction(ISD::FPOW, MVT::f64, Expand);
607 setOperationAction(ISD::FLOG, MVT::f64, Expand);
608 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
609 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
610 setOperationAction(ISD::FEXP, MVT::f64, Expand);
611 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
612 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
613 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
614 setOperationAction(ISD::FRINT, MVT::f64, Expand);
615 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
616 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
617 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
618 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
621 computeRegisterProperties();
623 // ARM does not have floating-point extending loads.
624 for (MVT VT : MVT::fp_valuetypes()) {
625 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
626 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
629 // ... or truncating stores
630 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
631 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
632 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
634 // ARM does not have i1 sign extending load.
635 for (MVT VT : MVT::integer_valuetypes())
636 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
638 // ARM supports all 4 flavors of integer indexed load / store.
639 if (!Subtarget->isThumb1Only()) {
640 for (unsigned im = (unsigned)ISD::PRE_INC;
641 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
642 setIndexedLoadAction(im, MVT::i1, Legal);
643 setIndexedLoadAction(im, MVT::i8, Legal);
644 setIndexedLoadAction(im, MVT::i16, Legal);
645 setIndexedLoadAction(im, MVT::i32, Legal);
646 setIndexedStoreAction(im, MVT::i1, Legal);
647 setIndexedStoreAction(im, MVT::i8, Legal);
648 setIndexedStoreAction(im, MVT::i16, Legal);
649 setIndexedStoreAction(im, MVT::i32, Legal);
653 setOperationAction(ISD::SADDO, MVT::i32, Custom);
654 setOperationAction(ISD::UADDO, MVT::i32, Custom);
655 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
656 setOperationAction(ISD::USUBO, MVT::i32, Custom);
658 // i64 operation support.
659 setOperationAction(ISD::MUL, MVT::i64, Expand);
660 setOperationAction(ISD::MULHU, MVT::i32, Expand);
661 if (Subtarget->isThumb1Only()) {
662 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
663 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
665 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
666 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
667 setOperationAction(ISD::MULHS, MVT::i32, Expand);
669 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
670 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
671 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
672 setOperationAction(ISD::SRL, MVT::i64, Custom);
673 setOperationAction(ISD::SRA, MVT::i64, Custom);
675 if (!Subtarget->isThumb1Only()) {
676 // FIXME: We should do this for Thumb1 as well.
677 setOperationAction(ISD::ADDC, MVT::i32, Custom);
678 setOperationAction(ISD::ADDE, MVT::i32, Custom);
679 setOperationAction(ISD::SUBC, MVT::i32, Custom);
680 setOperationAction(ISD::SUBE, MVT::i32, Custom);
683 // ARM does not have ROTL.
684 setOperationAction(ISD::ROTL, MVT::i32, Expand);
685 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
686 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
687 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
688 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
690 // These just redirect to CTTZ and CTLZ on ARM.
691 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
692 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
694 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
696 // Only ARMv6 has BSWAP.
697 if (!Subtarget->hasV6Ops())
698 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
700 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
701 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
702 // These are expanded into libcalls if the cpu doesn't have HW divider.
703 setOperationAction(ISD::SDIV, MVT::i32, Expand);
704 setOperationAction(ISD::UDIV, MVT::i32, Expand);
707 // FIXME: Also set divmod for SREM on EABI
708 setOperationAction(ISD::SREM, MVT::i32, Expand);
709 setOperationAction(ISD::UREM, MVT::i32, Expand);
710 // Register based DivRem for AEABI (RTABI 4.2)
711 if (Subtarget->isTargetAEABI()) {
712 setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
713 setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
714 setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
715 setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
716 setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
717 setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
718 setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
719 setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
721 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
722 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
723 setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
724 setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
725 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
726 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
727 setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
728 setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
730 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
731 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
733 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
734 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
737 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
738 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
739 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
740 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
741 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
743 setOperationAction(ISD::TRAP, MVT::Other, Legal);
745 // Use the default implementation.
746 setOperationAction(ISD::VASTART, MVT::Other, Custom);
747 setOperationAction(ISD::VAARG, MVT::Other, Expand);
748 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
749 setOperationAction(ISD::VAEND, MVT::Other, Expand);
750 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
751 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
753 if (!Subtarget->isTargetMachO()) {
754 // Non-MachO platforms may return values in these registers via the
755 // personality function.
756 setExceptionPointerRegister(ARM::R0);
757 setExceptionSelectorRegister(ARM::R1);
760 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
761 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
763 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
765 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
766 // the default expansion. If we are targeting a single threaded system,
767 // then set them all for expand so we can lower them later into their
769 if (TM.Options.ThreadModel == ThreadModel::Single)
770 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
771 else if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
772 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
773 // to ldrex/strex loops already.
774 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
776 // On v8, we have particularly efficient implementations of atomic fences
777 // if they can be combined with nearby atomic loads and stores.
778 if (!Subtarget->hasV8Ops()) {
779 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
780 setInsertFencesForAtomic(true);
783 // If there's anything we can use as a barrier, go through custom lowering
785 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
786 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
788 // Set them all for expansion, which will force libcalls.
789 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
790 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
791 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
792 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
793 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
794 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
795 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
796 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
797 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
798 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
799 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
800 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
801 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
802 // Unordered/Monotonic case.
803 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
804 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
807 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
809 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
810 if (!Subtarget->hasV6Ops()) {
811 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
812 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
814 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
816 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
817 !Subtarget->isThumb1Only()) {
818 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
819 // iff target supports vfp2.
820 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
821 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
824 // We want to custom lower some of our intrinsics.
825 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
826 if (Subtarget->isTargetDarwin()) {
827 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
828 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
829 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
832 setOperationAction(ISD::SETCC, MVT::i32, Expand);
833 setOperationAction(ISD::SETCC, MVT::f32, Expand);
834 setOperationAction(ISD::SETCC, MVT::f64, Expand);
835 setOperationAction(ISD::SELECT, MVT::i32, Custom);
836 setOperationAction(ISD::SELECT, MVT::f32, Custom);
837 setOperationAction(ISD::SELECT, MVT::f64, Custom);
838 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
839 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
840 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
842 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
843 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
844 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
845 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
846 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
848 // We don't support sin/cos/fmod/copysign/pow
849 setOperationAction(ISD::FSIN, MVT::f64, Expand);
850 setOperationAction(ISD::FSIN, MVT::f32, Expand);
851 setOperationAction(ISD::FCOS, MVT::f32, Expand);
852 setOperationAction(ISD::FCOS, MVT::f64, Expand);
853 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
854 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
855 setOperationAction(ISD::FREM, MVT::f64, Expand);
856 setOperationAction(ISD::FREM, MVT::f32, Expand);
857 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
858 !Subtarget->isThumb1Only()) {
859 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
860 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
862 setOperationAction(ISD::FPOW, MVT::f64, Expand);
863 setOperationAction(ISD::FPOW, MVT::f32, Expand);
865 if (!Subtarget->hasVFP4()) {
866 setOperationAction(ISD::FMA, MVT::f64, Expand);
867 setOperationAction(ISD::FMA, MVT::f32, Expand);
870 // Various VFP goodness
871 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
872 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
873 if (Subtarget->hasVFP2()) {
874 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
875 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
876 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
877 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
880 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
881 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
882 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
883 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
886 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
887 if (!Subtarget->hasFP16()) {
888 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
889 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
893 // Combine sin / cos into one node or libcall if possible.
894 if (Subtarget->hasSinCos()) {
895 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
896 setLibcallName(RTLIB::SINCOS_F64, "sincos");
897 if (Subtarget->getTargetTriple().isiOS()) {
898 // For iOS, we don't want to the normal expansion of a libcall to
899 // sincos. We want to issue a libcall to __sincos_stret.
900 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
901 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
905 // FP-ARMv8 implements a lot of rounding-like FP operations.
906 if (Subtarget->hasFPARMv8()) {
907 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
908 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
909 setOperationAction(ISD::FROUND, MVT::f32, Legal);
910 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
911 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
912 setOperationAction(ISD::FRINT, MVT::f32, Legal);
913 if (!Subtarget->isFPOnlySP()) {
914 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
915 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
916 setOperationAction(ISD::FROUND, MVT::f64, Legal);
917 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
918 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
919 setOperationAction(ISD::FRINT, MVT::f64, Legal);
922 // We have target-specific dag combine patterns for the following nodes:
923 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
924 setTargetDAGCombine(ISD::ADD);
925 setTargetDAGCombine(ISD::SUB);
926 setTargetDAGCombine(ISD::MUL);
927 setTargetDAGCombine(ISD::AND);
928 setTargetDAGCombine(ISD::OR);
929 setTargetDAGCombine(ISD::XOR);
931 if (Subtarget->hasV6Ops())
932 setTargetDAGCombine(ISD::SRL);
934 setStackPointerRegisterToSaveRestore(ARM::SP);
936 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||
937 !Subtarget->hasVFP2())
938 setSchedulingPreference(Sched::RegPressure);
940 setSchedulingPreference(Sched::Hybrid);
942 //// temporary - rewrite interface to use type
943 MaxStoresPerMemset = 8;
944 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
945 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
946 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
947 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
948 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
950 // On ARM arguments smaller than 4 bytes are extended, so all arguments
951 // are at least 4 bytes aligned.
952 setMinStackArgumentAlignment(4);
954 // Prefer likely predicted branches to selects on out-of-order cores.
955 PredictableSelectIsExpensive = Subtarget->isLikeA9();
957 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
960 // FIXME: It might make sense to define the representative register class as the
961 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
962 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
963 // SPR's representative would be DPR_VFP2. This should work well if register
964 // pressure tracking were modified such that a register use would increment the
965 // pressure of the register class's representative and all of it's super
966 // classes' representatives transitively. We have not implemented this because
967 // of the difficulty prior to coalescing of modeling operand register classes
968 // due to the common occurrence of cross class copies and subregister insertions
970 std::pair<const TargetRegisterClass*, uint8_t>
971 ARMTargetLowering::findRepresentativeClass(MVT VT) const{
972 const TargetRegisterClass *RRC = nullptr;
974 switch (VT.SimpleTy) {
976 return TargetLowering::findRepresentativeClass(VT);
977 // Use DPR as representative register class for all floating point
978 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
979 // the cost is 1 for both f32 and f64.
980 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
981 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
982 RRC = &ARM::DPRRegClass;
983 // When NEON is used for SP, only half of the register file is available
984 // because operations that define both SP and DP results will be constrained
985 // to the VFP2 class (D0-D15). We currently model this constraint prior to
986 // coalescing by double-counting the SP regs. See the FIXME above.
987 if (Subtarget->useNEONForSinglePrecisionFP())
990 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
991 case MVT::v4f32: case MVT::v2f64:
992 RRC = &ARM::DPRRegClass;
996 RRC = &ARM::DPRRegClass;
1000 RRC = &ARM::DPRRegClass;
1004 return std::make_pair(RRC, Cost);
1007 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1009 default: return nullptr;
1010 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1011 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1012 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1013 case ARMISD::CALL: return "ARMISD::CALL";
1014 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1015 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1016 case ARMISD::tCALL: return "ARMISD::tCALL";
1017 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1018 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1019 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1020 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1021 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1022 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1023 case ARMISD::CMP: return "ARMISD::CMP";
1024 case ARMISD::CMN: return "ARMISD::CMN";
1025 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1026 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1027 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1028 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1029 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1031 case ARMISD::CMOV: return "ARMISD::CMOV";
1033 case ARMISD::RBIT: return "ARMISD::RBIT";
1035 case ARMISD::FTOSI: return "ARMISD::FTOSI";
1036 case ARMISD::FTOUI: return "ARMISD::FTOUI";
1037 case ARMISD::SITOF: return "ARMISD::SITOF";
1038 case ARMISD::UITOF: return "ARMISD::UITOF";
1040 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1041 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1042 case ARMISD::RRX: return "ARMISD::RRX";
1044 case ARMISD::ADDC: return "ARMISD::ADDC";
1045 case ARMISD::ADDE: return "ARMISD::ADDE";
1046 case ARMISD::SUBC: return "ARMISD::SUBC";
1047 case ARMISD::SUBE: return "ARMISD::SUBE";
1049 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1050 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1052 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1053 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
1055 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1057 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1059 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1061 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1063 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1065 case ARMISD::WIN__CHKSTK: return "ARMISD:::WIN__CHKSTK";
1067 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1068 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1069 case ARMISD::VCGE: return "ARMISD::VCGE";
1070 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1071 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1072 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1073 case ARMISD::VCGT: return "ARMISD::VCGT";
1074 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1075 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1076 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1077 case ARMISD::VTST: return "ARMISD::VTST";
1079 case ARMISD::VSHL: return "ARMISD::VSHL";
1080 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1081 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1082 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1083 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1084 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1085 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1086 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1087 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1088 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1089 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1090 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1091 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1092 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1093 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1094 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1095 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1096 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1097 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1098 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1099 case ARMISD::VDUP: return "ARMISD::VDUP";
1100 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1101 case ARMISD::VEXT: return "ARMISD::VEXT";
1102 case ARMISD::VREV64: return "ARMISD::VREV64";
1103 case ARMISD::VREV32: return "ARMISD::VREV32";
1104 case ARMISD::VREV16: return "ARMISD::VREV16";
1105 case ARMISD::VZIP: return "ARMISD::VZIP";
1106 case ARMISD::VUZP: return "ARMISD::VUZP";
1107 case ARMISD::VTRN: return "ARMISD::VTRN";
1108 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1109 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1110 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1111 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1112 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1113 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1114 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1115 case ARMISD::FMAX: return "ARMISD::FMAX";
1116 case ARMISD::FMIN: return "ARMISD::FMIN";
1117 case ARMISD::VMAXNM: return "ARMISD::VMAX";
1118 case ARMISD::VMINNM: return "ARMISD::VMIN";
1119 case ARMISD::BFI: return "ARMISD::BFI";
1120 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1121 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1122 case ARMISD::VBSL: return "ARMISD::VBSL";
1123 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1124 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1125 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1126 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1127 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1128 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1129 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1130 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1131 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1132 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1133 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1134 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1135 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1136 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1137 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1138 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1139 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1140 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1141 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1142 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1146 EVT ARMTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1147 if (!VT.isVector()) return getPointerTy();
1148 return VT.changeVectorElementTypeToInteger();
1151 /// getRegClassFor - Return the register class that should be used for the
1152 /// specified value type.
1153 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1154 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1155 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1156 // load / store 4 to 8 consecutive D registers.
1157 if (Subtarget->hasNEON()) {
1158 if (VT == MVT::v4i64)
1159 return &ARM::QQPRRegClass;
1160 if (VT == MVT::v8i64)
1161 return &ARM::QQQQPRRegClass;
1163 return TargetLowering::getRegClassFor(VT);
1166 // Create a fast isel object.
1168 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1169 const TargetLibraryInfo *libInfo) const {
1170 return ARM::createFastISel(funcInfo, libInfo);
1173 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
1174 /// be used for loads / stores from the global.
1175 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
1176 return (Subtarget->isThumb1Only() ? 127 : 4095);
1179 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1180 unsigned NumVals = N->getNumValues();
1182 return Sched::RegPressure;
1184 for (unsigned i = 0; i != NumVals; ++i) {
1185 EVT VT = N->getValueType(i);
1186 if (VT == MVT::Glue || VT == MVT::Other)
1188 if (VT.isFloatingPoint() || VT.isVector())
1192 if (!N->isMachineOpcode())
1193 return Sched::RegPressure;
1195 // Load are scheduled for latency even if there instruction itinerary
1196 // is not available.
1197 const TargetInstrInfo *TII =
1198 getTargetMachine().getSubtargetImpl()->getInstrInfo();
1199 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1201 if (MCID.getNumDefs() == 0)
1202 return Sched::RegPressure;
1203 if (!Itins->isEmpty() &&
1204 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1207 return Sched::RegPressure;
1210 //===----------------------------------------------------------------------===//
1212 //===----------------------------------------------------------------------===//
1214 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1215 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1217 default: llvm_unreachable("Unknown condition code!");
1218 case ISD::SETNE: return ARMCC::NE;
1219 case ISD::SETEQ: return ARMCC::EQ;
1220 case ISD::SETGT: return ARMCC::GT;
1221 case ISD::SETGE: return ARMCC::GE;
1222 case ISD::SETLT: return ARMCC::LT;
1223 case ISD::SETLE: return ARMCC::LE;
1224 case ISD::SETUGT: return ARMCC::HI;
1225 case ISD::SETUGE: return ARMCC::HS;
1226 case ISD::SETULT: return ARMCC::LO;
1227 case ISD::SETULE: return ARMCC::LS;
1231 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1232 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1233 ARMCC::CondCodes &CondCode2) {
1234 CondCode2 = ARMCC::AL;
1236 default: llvm_unreachable("Unknown FP condition!");
1238 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1240 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1242 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1243 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1244 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1245 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1246 case ISD::SETO: CondCode = ARMCC::VC; break;
1247 case ISD::SETUO: CondCode = ARMCC::VS; break;
1248 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1249 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1250 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1252 case ISD::SETULT: CondCode = ARMCC::LT; break;
1254 case ISD::SETULE: CondCode = ARMCC::LE; break;
1256 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1260 //===----------------------------------------------------------------------===//
1261 // Calling Convention Implementation
1262 //===----------------------------------------------------------------------===//
1264 #include "ARMGenCallingConv.inc"
1266 /// getEffectiveCallingConv - Get the effective calling convention, taking into
1267 /// account presence of floating point hardware and calling convention
1268 /// limitations, such as support for variadic functions.
1270 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1271 bool isVarArg) const {
1274 llvm_unreachable("Unsupported calling convention");
1275 case CallingConv::ARM_AAPCS:
1276 case CallingConv::ARM_APCS:
1277 case CallingConv::GHC:
1279 case CallingConv::ARM_AAPCS_VFP:
1280 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1281 case CallingConv::C:
1282 if (!Subtarget->isAAPCS_ABI())
1283 return CallingConv::ARM_APCS;
1284 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1285 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1287 return CallingConv::ARM_AAPCS_VFP;
1289 return CallingConv::ARM_AAPCS;
1290 case CallingConv::Fast:
1291 if (!Subtarget->isAAPCS_ABI()) {
1292 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1293 return CallingConv::Fast;
1294 return CallingConv::ARM_APCS;
1295 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1296 return CallingConv::ARM_AAPCS_VFP;
1298 return CallingConv::ARM_AAPCS;
1302 /// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1303 /// CallingConvention.
1304 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1306 bool isVarArg) const {
1307 switch (getEffectiveCallingConv(CC, isVarArg)) {
1309 llvm_unreachable("Unsupported calling convention");
1310 case CallingConv::ARM_APCS:
1311 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1312 case CallingConv::ARM_AAPCS:
1313 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1314 case CallingConv::ARM_AAPCS_VFP:
1315 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1316 case CallingConv::Fast:
1317 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1318 case CallingConv::GHC:
1319 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1323 /// LowerCallResult - Lower the result values of a call into the
1324 /// appropriate copies out of appropriate physical registers.
1326 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1327 CallingConv::ID CallConv, bool isVarArg,
1328 const SmallVectorImpl<ISD::InputArg> &Ins,
1329 SDLoc dl, SelectionDAG &DAG,
1330 SmallVectorImpl<SDValue> &InVals,
1331 bool isThisReturn, SDValue ThisVal) const {
1333 // Assign locations to each value returned by this call.
1334 SmallVector<CCValAssign, 16> RVLocs;
1335 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1336 *DAG.getContext(), Call);
1337 CCInfo.AnalyzeCallResult(Ins,
1338 CCAssignFnForNode(CallConv, /* Return*/ true,
1341 // Copy all of the result registers out of their specified physreg.
1342 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1343 CCValAssign VA = RVLocs[i];
1345 // Pass 'this' value directly from the argument to return value, to avoid
1346 // reg unit interference
1347 if (i == 0 && isThisReturn) {
1348 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1349 "unexpected return calling convention register assignment");
1350 InVals.push_back(ThisVal);
1355 if (VA.needsCustom()) {
1356 // Handle f64 or half of a v2f64.
1357 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1359 Chain = Lo.getValue(1);
1360 InFlag = Lo.getValue(2);
1361 VA = RVLocs[++i]; // skip ahead to next loc
1362 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1364 Chain = Hi.getValue(1);
1365 InFlag = Hi.getValue(2);
1366 if (!Subtarget->isLittle())
1368 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1370 if (VA.getLocVT() == MVT::v2f64) {
1371 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1372 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1373 DAG.getConstant(0, MVT::i32));
1375 VA = RVLocs[++i]; // skip ahead to next loc
1376 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1377 Chain = Lo.getValue(1);
1378 InFlag = Lo.getValue(2);
1379 VA = RVLocs[++i]; // skip ahead to next loc
1380 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1381 Chain = Hi.getValue(1);
1382 InFlag = Hi.getValue(2);
1383 if (!Subtarget->isLittle())
1385 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1386 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1387 DAG.getConstant(1, MVT::i32));
1390 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1392 Chain = Val.getValue(1);
1393 InFlag = Val.getValue(2);
1396 switch (VA.getLocInfo()) {
1397 default: llvm_unreachable("Unknown loc info!");
1398 case CCValAssign::Full: break;
1399 case CCValAssign::BCvt:
1400 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1404 InVals.push_back(Val);
1410 /// LowerMemOpCallTo - Store the argument to the stack.
1412 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1413 SDValue StackPtr, SDValue Arg,
1414 SDLoc dl, SelectionDAG &DAG,
1415 const CCValAssign &VA,
1416 ISD::ArgFlagsTy Flags) const {
1417 unsigned LocMemOffset = VA.getLocMemOffset();
1418 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1419 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1420 return DAG.getStore(Chain, dl, Arg, PtrOff,
1421 MachinePointerInfo::getStack(LocMemOffset),
1425 void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
1426 SDValue Chain, SDValue &Arg,
1427 RegsToPassVector &RegsToPass,
1428 CCValAssign &VA, CCValAssign &NextVA,
1430 SmallVectorImpl<SDValue> &MemOpChains,
1431 ISD::ArgFlagsTy Flags) const {
1433 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1434 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1435 unsigned id = Subtarget->isLittle() ? 0 : 1;
1436 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1438 if (NextVA.isRegLoc())
1439 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1441 assert(NextVA.isMemLoc());
1442 if (!StackPtr.getNode())
1443 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1445 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1451 /// LowerCall - Lowering a call into a callseq_start <-
1452 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1455 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1456 SmallVectorImpl<SDValue> &InVals) const {
1457 SelectionDAG &DAG = CLI.DAG;
1459 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1460 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1461 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1462 SDValue Chain = CLI.Chain;
1463 SDValue Callee = CLI.Callee;
1464 bool &isTailCall = CLI.IsTailCall;
1465 CallingConv::ID CallConv = CLI.CallConv;
1466 bool doesNotRet = CLI.DoesNotReturn;
1467 bool isVarArg = CLI.IsVarArg;
1469 MachineFunction &MF = DAG.getMachineFunction();
1470 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1471 bool isThisReturn = false;
1472 bool isSibCall = false;
1474 // Disable tail calls if they're not supported.
1475 if (!Subtarget->supportsTailCall() || MF.getTarget().Options.DisableTailCalls)
1479 // Check if it's really possible to do a tail call.
1480 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1481 isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
1482 Outs, OutVals, Ins, DAG);
1483 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
1484 report_fatal_error("failed to perform tail call elimination on a call "
1485 "site marked musttail");
1486 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1487 // detected sibcalls.
1494 // Analyze operands of the call, assigning locations to each operand.
1495 SmallVector<CCValAssign, 16> ArgLocs;
1496 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1497 *DAG.getContext(), Call);
1498 CCInfo.AnalyzeCallOperands(Outs,
1499 CCAssignFnForNode(CallConv, /* Return*/ false,
1502 // Get a count of how many bytes are to be pushed on the stack.
1503 unsigned NumBytes = CCInfo.getNextStackOffset();
1505 // For tail calls, memory operands are available in our caller's stack.
1509 // Adjust the stack pointer for the new arguments...
1510 // These operations are automatically eliminated by the prolog/epilog pass
1512 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1515 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1517 RegsToPassVector RegsToPass;
1518 SmallVector<SDValue, 8> MemOpChains;
1520 // Walk the register/memloc assignments, inserting copies/loads. In the case
1521 // of tail call optimization, arguments are handled later.
1522 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1524 ++i, ++realArgIdx) {
1525 CCValAssign &VA = ArgLocs[i];
1526 SDValue Arg = OutVals[realArgIdx];
1527 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1528 bool isByVal = Flags.isByVal();
1530 // Promote the value if needed.
1531 switch (VA.getLocInfo()) {
1532 default: llvm_unreachable("Unknown loc info!");
1533 case CCValAssign::Full: break;
1534 case CCValAssign::SExt:
1535 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1537 case CCValAssign::ZExt:
1538 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1540 case CCValAssign::AExt:
1541 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1543 case CCValAssign::BCvt:
1544 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1548 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1549 if (VA.needsCustom()) {
1550 if (VA.getLocVT() == MVT::v2f64) {
1551 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1552 DAG.getConstant(0, MVT::i32));
1553 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1554 DAG.getConstant(1, MVT::i32));
1556 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1557 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1559 VA = ArgLocs[++i]; // skip ahead to next loc
1560 if (VA.isRegLoc()) {
1561 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1562 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1564 assert(VA.isMemLoc());
1566 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1567 dl, DAG, VA, Flags));
1570 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1571 StackPtr, MemOpChains, Flags);
1573 } else if (VA.isRegLoc()) {
1574 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1575 assert(VA.getLocVT() == MVT::i32 &&
1576 "unexpected calling convention register assignment");
1577 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1578 "unexpected use of 'returned'");
1579 isThisReturn = true;
1581 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1582 } else if (isByVal) {
1583 assert(VA.isMemLoc());
1584 unsigned offset = 0;
1586 // True if this byval aggregate will be split between registers
1588 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1589 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1591 if (CurByValIdx < ByValArgsCount) {
1593 unsigned RegBegin, RegEnd;
1594 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1596 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1598 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1599 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1600 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1601 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1602 MachinePointerInfo(),
1603 false, false, false,
1604 DAG.InferPtrAlignment(AddArg));
1605 MemOpChains.push_back(Load.getValue(1));
1606 RegsToPass.push_back(std::make_pair(j, Load));
1609 // If parameter size outsides register area, "offset" value
1610 // helps us to calculate stack slot for remained part properly.
1611 offset = RegEnd - RegBegin;
1613 CCInfo.nextInRegsParam();
1616 if (Flags.getByValSize() > 4*offset) {
1617 unsigned LocMemOffset = VA.getLocMemOffset();
1618 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1619 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1621 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1622 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1623 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1625 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
1627 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1628 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1629 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1632 } else if (!isSibCall) {
1633 assert(VA.isMemLoc());
1635 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1636 dl, DAG, VA, Flags));
1640 if (!MemOpChains.empty())
1641 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1643 // Build a sequence of copy-to-reg nodes chained together with token chain
1644 // and flag operands which copy the outgoing args into the appropriate regs.
1646 // Tail call byval lowering might overwrite argument registers so in case of
1647 // tail call optimization the copies to registers are lowered later.
1649 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1650 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1651 RegsToPass[i].second, InFlag);
1652 InFlag = Chain.getValue(1);
1655 // For tail calls lower the arguments to the 'real' stack slot.
1657 // Force all the incoming stack arguments to be loaded from the stack
1658 // before any new outgoing arguments are stored to the stack, because the
1659 // outgoing stack slots may alias the incoming argument stack slots, and
1660 // the alias isn't otherwise explicit. This is slightly more conservative
1661 // than necessary, because it means that each store effectively depends
1662 // on every argument instead of just those arguments it would clobber.
1664 // Do not flag preceding copytoreg stuff together with the following stuff.
1666 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1667 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1668 RegsToPass[i].second, InFlag);
1669 InFlag = Chain.getValue(1);
1674 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1675 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1676 // node so that legalize doesn't hack it.
1677 bool isDirect = false;
1678 bool isARMFunc = false;
1679 bool isLocalARMFunc = false;
1680 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1682 if (EnableARMLongCalls) {
1683 assert((Subtarget->isTargetWindows() ||
1684 getTargetMachine().getRelocationModel() == Reloc::Static) &&
1685 "long-calls with non-static relocation model!");
1686 // Handle a global address or an external symbol. If it's not one of
1687 // those, the target's already in a register, so we don't need to do
1689 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1690 const GlobalValue *GV = G->getGlobal();
1691 // Create a constant pool entry for the callee address
1692 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1693 ARMConstantPoolValue *CPV =
1694 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1696 // Get the address of the callee into a register
1697 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1698 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1699 Callee = DAG.getLoad(getPointerTy(), dl,
1700 DAG.getEntryNode(), CPAddr,
1701 MachinePointerInfo::getConstantPool(),
1702 false, false, false, 0);
1703 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1704 const char *Sym = S->getSymbol();
1706 // Create a constant pool entry for the callee address
1707 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1708 ARMConstantPoolValue *CPV =
1709 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1710 ARMPCLabelIndex, 0);
1711 // Get the address of the callee into a register
1712 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1713 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1714 Callee = DAG.getLoad(getPointerTy(), dl,
1715 DAG.getEntryNode(), CPAddr,
1716 MachinePointerInfo::getConstantPool(),
1717 false, false, false, 0);
1719 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1720 const GlobalValue *GV = G->getGlobal();
1722 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1723 bool isStub = (isExt && Subtarget->isTargetMachO()) &&
1724 getTargetMachine().getRelocationModel() != Reloc::Static;
1725 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1726 // ARM call to a local ARM function is predicable.
1727 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1728 // tBX takes a register source operand.
1729 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1730 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
1731 Callee = DAG.getNode(ARMISD::WrapperPIC, dl, getPointerTy(),
1732 DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
1733 0, ARMII::MO_NONLAZY));
1734 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
1735 MachinePointerInfo::getGOT(), false, false, true, 0);
1736 } else if (Subtarget->isTargetCOFF()) {
1737 assert(Subtarget->isTargetWindows() &&
1738 "Windows is the only supported COFF target");
1739 unsigned TargetFlags = GV->hasDLLImportStorageClass()
1740 ? ARMII::MO_DLLIMPORT
1741 : ARMII::MO_NO_FLAG;
1742 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), /*Offset=*/0,
1744 if (GV->hasDLLImportStorageClass())
1745 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1746 DAG.getNode(ARMISD::Wrapper, dl, getPointerTy(),
1747 Callee), MachinePointerInfo::getGOT(),
1748 false, false, false, 0);
1750 // On ELF targets for PIC code, direct calls should go through the PLT
1751 unsigned OpFlags = 0;
1752 if (Subtarget->isTargetELF() &&
1753 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1754 OpFlags = ARMII::MO_PLT;
1755 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1757 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1759 bool isStub = Subtarget->isTargetMachO() &&
1760 getTargetMachine().getRelocationModel() != Reloc::Static;
1761 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1762 // tBX takes a register source operand.
1763 const char *Sym = S->getSymbol();
1764 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1765 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1766 ARMConstantPoolValue *CPV =
1767 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1768 ARMPCLabelIndex, 4);
1769 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1770 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1771 Callee = DAG.getLoad(getPointerTy(), dl,
1772 DAG.getEntryNode(), CPAddr,
1773 MachinePointerInfo::getConstantPool(),
1774 false, false, false, 0);
1775 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1776 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1777 getPointerTy(), Callee, PICLabel);
1779 unsigned OpFlags = 0;
1780 // On ELF targets for PIC code, direct calls should go through the PLT
1781 if (Subtarget->isTargetELF() &&
1782 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1783 OpFlags = ARMII::MO_PLT;
1784 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1788 // FIXME: handle tail calls differently.
1790 bool HasMinSizeAttr = MF.getFunction()->getAttributes().hasAttribute(
1791 AttributeSet::FunctionIndex, Attribute::MinSize);
1792 if (Subtarget->isThumb()) {
1793 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1794 CallOpc = ARMISD::CALL_NOLINK;
1796 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1798 if (!isDirect && !Subtarget->hasV5TOps())
1799 CallOpc = ARMISD::CALL_NOLINK;
1800 else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1801 // Emit regular call when code size is the priority
1803 // "mov lr, pc; b _foo" to avoid confusing the RSP
1804 CallOpc = ARMISD::CALL_NOLINK;
1806 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1809 std::vector<SDValue> Ops;
1810 Ops.push_back(Chain);
1811 Ops.push_back(Callee);
1813 // Add argument registers to the end of the list so that they are known live
1815 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1816 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1817 RegsToPass[i].second.getValueType()));
1819 // Add a register mask operand representing the call-preserved registers.
1821 const uint32_t *Mask;
1822 const TargetRegisterInfo *TRI =
1823 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
1824 const ARMBaseRegisterInfo *ARI = static_cast<const ARMBaseRegisterInfo*>(TRI);
1826 // For 'this' returns, use the R0-preserving mask if applicable
1827 Mask = ARI->getThisReturnPreservedMask(CallConv);
1829 // Set isThisReturn to false if the calling convention is not one that
1830 // allows 'returned' to be modeled in this way, so LowerCallResult does
1831 // not try to pass 'this' straight through
1832 isThisReturn = false;
1833 Mask = ARI->getCallPreservedMask(CallConv);
1836 Mask = ARI->getCallPreservedMask(CallConv);
1838 assert(Mask && "Missing call preserved mask for calling convention");
1839 Ops.push_back(DAG.getRegisterMask(Mask));
1842 if (InFlag.getNode())
1843 Ops.push_back(InFlag);
1845 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1847 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
1849 // Returns a chain and a flag for retval copy to use.
1850 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
1851 InFlag = Chain.getValue(1);
1853 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1854 DAG.getIntPtrConstant(0, true), InFlag, dl);
1856 InFlag = Chain.getValue(1);
1858 // Handle result values, copying them out of physregs into vregs that we
1860 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
1861 InVals, isThisReturn,
1862 isThisReturn ? OutVals[0] : SDValue());
1865 /// HandleByVal - Every parameter *after* a byval parameter is passed
1866 /// on the stack. Remember the next parameter register to allocate,
1867 /// and then confiscate the rest of the parameter registers to insure
1870 ARMTargetLowering::HandleByVal(
1871 CCState *State, unsigned &size, unsigned Align) const {
1872 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1873 assert((State->getCallOrPrologue() == Prologue ||
1874 State->getCallOrPrologue() == Call) &&
1875 "unhandled ParmContext");
1877 if ((ARM::R0 <= reg) && (reg <= ARM::R3)) {
1878 if (Subtarget->isAAPCS_ABI() && Align > 4) {
1879 unsigned AlignInRegs = Align / 4;
1880 unsigned Waste = (ARM::R4 - reg) % AlignInRegs;
1881 for (unsigned i = 0; i < Waste; ++i)
1882 reg = State->AllocateReg(GPRArgRegs, 4);
1885 unsigned excess = 4 * (ARM::R4 - reg);
1887 // Special case when NSAA != SP and parameter size greater than size of
1888 // all remained GPR regs. In that case we can't split parameter, we must
1889 // send it to stack. We also must set NCRN to R4, so waste all
1890 // remained registers.
1891 const unsigned NSAAOffset = State->getNextStackOffset();
1892 if (Subtarget->isAAPCS_ABI() && NSAAOffset != 0 && size > excess) {
1893 while (State->AllocateReg(GPRArgRegs, 4))
1898 // First register for byval parameter is the first register that wasn't
1899 // allocated before this method call, so it would be "reg".
1900 // If parameter is small enough to be saved in range [reg, r4), then
1901 // the end (first after last) register would be reg + param-size-in-regs,
1902 // else parameter would be splitted between registers and stack,
1903 // end register would be r4 in this case.
1904 unsigned ByValRegBegin = reg;
1905 unsigned ByValRegEnd = (size < excess) ? reg + size/4 : (unsigned)ARM::R4;
1906 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
1907 // Note, first register is allocated in the beginning of function already,
1908 // allocate remained amount of registers we need.
1909 for (unsigned i = reg+1; i != ByValRegEnd; ++i)
1910 State->AllocateReg(GPRArgRegs, 4);
1911 // A byval parameter that is split between registers and memory needs its
1912 // size truncated here.
1913 // In the case where the entire structure fits in registers, we set the
1914 // size in memory to zero.
1923 /// MatchingStackOffset - Return true if the given stack call argument is
1924 /// already available in the same position (relatively) of the caller's
1925 /// incoming argument stack.
1927 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1928 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1929 const TargetInstrInfo *TII) {
1930 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1932 if (Arg.getOpcode() == ISD::CopyFromReg) {
1933 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1934 if (!TargetRegisterInfo::isVirtualRegister(VR))
1936 MachineInstr *Def = MRI->getVRegDef(VR);
1939 if (!Flags.isByVal()) {
1940 if (!TII->isLoadFromStackSlot(Def, FI))
1945 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1946 if (Flags.isByVal())
1947 // ByVal argument is passed in as a pointer but it's now being
1948 // dereferenced. e.g.
1949 // define @foo(%struct.X* %A) {
1950 // tail call @bar(%struct.X* byval %A)
1953 SDValue Ptr = Ld->getBasePtr();
1954 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1957 FI = FINode->getIndex();
1961 assert(FI != INT_MAX);
1962 if (!MFI->isFixedObjectIndex(FI))
1964 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1967 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1968 /// for tail call optimization. Targets which want to do tail call
1969 /// optimization should implement this function.
1971 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1972 CallingConv::ID CalleeCC,
1974 bool isCalleeStructRet,
1975 bool isCallerStructRet,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 const SmallVectorImpl<ISD::InputArg> &Ins,
1979 SelectionDAG& DAG) const {
1980 const Function *CallerF = DAG.getMachineFunction().getFunction();
1981 CallingConv::ID CallerCC = CallerF->getCallingConv();
1982 bool CCMatch = CallerCC == CalleeCC;
1984 // Look for obvious safe cases to perform tail call optimization that do not
1985 // require ABI changes. This is what gcc calls sibcall.
1987 // Do not sibcall optimize vararg calls unless the call site is not passing
1989 if (isVarArg && !Outs.empty())
1992 // Exception-handling functions need a special set of instructions to indicate
1993 // a return to the hardware. Tail-calling another function would probably
1995 if (CallerF->hasFnAttribute("interrupt"))
1998 // Also avoid sibcall optimization if either caller or callee uses struct
1999 // return semantics.
2000 if (isCalleeStructRet || isCallerStructRet)
2003 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
2004 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
2005 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
2006 // support in the assembler and linker to be used. This would need to be
2007 // fixed to fully support tail calls in Thumb1.
2009 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
2010 // LR. This means if we need to reload LR, it takes an extra instructions,
2011 // which outweighs the value of the tail call; but here we don't know yet
2012 // whether LR is going to be used. Probably the right approach is to
2013 // generate the tail call here and turn it back into CALL/RET in
2014 // emitEpilogue if LR is used.
2016 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
2017 // but we need to make sure there are enough registers; the only valid
2018 // registers are the 4 used for parameters. We don't currently do this
2020 if (Subtarget->isThumb1Only())
2023 // Externally-defined functions with weak linkage should not be
2024 // tail-called on ARM when the OS does not support dynamic
2025 // pre-emption of symbols, as the AAELF spec requires normal calls
2026 // to undefined weak functions to be replaced with a NOP or jump to the
2027 // next instruction. The behaviour of branch instructions in this
2028 // situation (as used for tail calls) is implementation-defined, so we
2029 // cannot rely on the linker replacing the tail call with a return.
2030 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2031 const GlobalValue *GV = G->getGlobal();
2032 const Triple TT(getTargetMachine().getTargetTriple());
2033 if (GV->hasExternalWeakLinkage() &&
2034 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2038 // If the calling conventions do not match, then we'd better make sure the
2039 // results are returned in the same way as what the caller expects.
2041 SmallVector<CCValAssign, 16> RVLocs1;
2042 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2043 *DAG.getContext(), Call);
2044 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
2046 SmallVector<CCValAssign, 16> RVLocs2;
2047 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2048 *DAG.getContext(), Call);
2049 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
2051 if (RVLocs1.size() != RVLocs2.size())
2053 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2054 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2056 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2058 if (RVLocs1[i].isRegLoc()) {
2059 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2062 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2068 // If Caller's vararg or byval argument has been split between registers and
2069 // stack, do not perform tail call, since part of the argument is in caller's
2071 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
2072 getInfo<ARMFunctionInfo>();
2073 if (AFI_Caller->getArgRegsSaveSize())
2076 // If the callee takes no arguments then go on to check the results of the
2078 if (!Outs.empty()) {
2079 // Check if stack adjustment is needed. For now, do not do this if any
2080 // argument is passed on the stack.
2081 SmallVector<CCValAssign, 16> ArgLocs;
2082 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2083 *DAG.getContext(), Call);
2084 CCInfo.AnalyzeCallOperands(Outs,
2085 CCAssignFnForNode(CalleeCC, false, isVarArg));
2086 if (CCInfo.getNextStackOffset()) {
2087 MachineFunction &MF = DAG.getMachineFunction();
2089 // Check if the arguments are already laid out in the right way as
2090 // the caller's fixed stack objects.
2091 MachineFrameInfo *MFI = MF.getFrameInfo();
2092 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2093 const TargetInstrInfo *TII =
2094 getTargetMachine().getSubtargetImpl()->getInstrInfo();
2095 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2097 ++i, ++realArgIdx) {
2098 CCValAssign &VA = ArgLocs[i];
2099 EVT RegVT = VA.getLocVT();
2100 SDValue Arg = OutVals[realArgIdx];
2101 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2102 if (VA.getLocInfo() == CCValAssign::Indirect)
2104 if (VA.needsCustom()) {
2105 // f64 and vector types are split into multiple registers or
2106 // register/stack-slot combinations. The types will not match
2107 // the registers; give up on memory f64 refs until we figure
2108 // out what to do about this.
2111 if (!ArgLocs[++i].isRegLoc())
2113 if (RegVT == MVT::v2f64) {
2114 if (!ArgLocs[++i].isRegLoc())
2116 if (!ArgLocs[++i].isRegLoc())
2119 } else if (!VA.isRegLoc()) {
2120 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2132 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2133 MachineFunction &MF, bool isVarArg,
2134 const SmallVectorImpl<ISD::OutputArg> &Outs,
2135 LLVMContext &Context) const {
2136 SmallVector<CCValAssign, 16> RVLocs;
2137 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2138 return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
2142 static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2143 SDLoc DL, SelectionDAG &DAG) {
2144 const MachineFunction &MF = DAG.getMachineFunction();
2145 const Function *F = MF.getFunction();
2147 StringRef IntKind = F->getFnAttribute("interrupt").getValueAsString();
2149 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2150 // version of the "preferred return address". These offsets affect the return
2151 // instruction if this is a return from PL1 without hypervisor extensions.
2152 // IRQ/FIQ: +4 "subs pc, lr, #4"
2153 // SWI: 0 "subs pc, lr, #0"
2154 // ABORT: +4 "subs pc, lr, #4"
2155 // UNDEF: +4/+2 "subs pc, lr, #0"
2156 // UNDEF varies depending on where the exception came from ARM or Thumb
2157 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2160 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2163 else if (IntKind == "SWI" || IntKind == "UNDEF")
2166 report_fatal_error("Unsupported interrupt attribute. If present, value "
2167 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2169 RetOps.insert(RetOps.begin() + 1, DAG.getConstant(LROffset, MVT::i32, false));
2171 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2175 ARMTargetLowering::LowerReturn(SDValue Chain,
2176 CallingConv::ID CallConv, bool isVarArg,
2177 const SmallVectorImpl<ISD::OutputArg> &Outs,
2178 const SmallVectorImpl<SDValue> &OutVals,
2179 SDLoc dl, SelectionDAG &DAG) const {
2181 // CCValAssign - represent the assignment of the return value to a location.
2182 SmallVector<CCValAssign, 16> RVLocs;
2184 // CCState - Info about the registers and stack slots.
2185 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2186 *DAG.getContext(), Call);
2188 // Analyze outgoing return values.
2189 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
2193 SmallVector<SDValue, 4> RetOps;
2194 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2195 bool isLittleEndian = Subtarget->isLittle();
2197 MachineFunction &MF = DAG.getMachineFunction();
2198 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2199 AFI->setReturnRegsCount(RVLocs.size());
2201 // Copy the result values into the output registers.
2202 for (unsigned i = 0, realRVLocIdx = 0;
2204 ++i, ++realRVLocIdx) {
2205 CCValAssign &VA = RVLocs[i];
2206 assert(VA.isRegLoc() && "Can only return in registers!");
2208 SDValue Arg = OutVals[realRVLocIdx];
2210 switch (VA.getLocInfo()) {
2211 default: llvm_unreachable("Unknown loc info!");
2212 case CCValAssign::Full: break;
2213 case CCValAssign::BCvt:
2214 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2218 if (VA.needsCustom()) {
2219 if (VA.getLocVT() == MVT::v2f64) {
2220 // Extract the first half and return it in two registers.
2221 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2222 DAG.getConstant(0, MVT::i32));
2223 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2224 DAG.getVTList(MVT::i32, MVT::i32), Half);
2226 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2227 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2229 Flag = Chain.getValue(1);
2230 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2231 VA = RVLocs[++i]; // skip ahead to next loc
2232 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2233 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2235 Flag = Chain.getValue(1);
2236 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2237 VA = RVLocs[++i]; // skip ahead to next loc
2239 // Extract the 2nd half and fall through to handle it as an f64 value.
2240 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2241 DAG.getConstant(1, MVT::i32));
2243 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2245 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2246 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2247 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2248 fmrrd.getValue(isLittleEndian ? 0 : 1),
2250 Flag = Chain.getValue(1);
2251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2252 VA = RVLocs[++i]; // skip ahead to next loc
2253 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2254 fmrrd.getValue(isLittleEndian ? 1 : 0),
2257 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2259 // Guarantee that all emitted copies are
2260 // stuck together, avoiding something bad.
2261 Flag = Chain.getValue(1);
2262 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2265 // Update chain and glue.
2268 RetOps.push_back(Flag);
2270 // CPUs which aren't M-class use a special sequence to return from
2271 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2272 // though we use "subs pc, lr, #N").
2274 // M-class CPUs actually use a normal return sequence with a special
2275 // (hardware-provided) value in LR, so the normal code path works.
2276 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
2277 !Subtarget->isMClass()) {
2278 if (Subtarget->isThumb1Only())
2279 report_fatal_error("interrupt attribute is not supported in Thumb1");
2280 return LowerInterruptReturn(RetOps, dl, DAG);
2283 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2286 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2287 if (N->getNumValues() != 1)
2289 if (!N->hasNUsesOfValue(1, 0))
2292 SDValue TCChain = Chain;
2293 SDNode *Copy = *N->use_begin();
2294 if (Copy->getOpcode() == ISD::CopyToReg) {
2295 // If the copy has a glue operand, we conservatively assume it isn't safe to
2296 // perform a tail call.
2297 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2299 TCChain = Copy->getOperand(0);
2300 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2301 SDNode *VMov = Copy;
2302 // f64 returned in a pair of GPRs.
2303 SmallPtrSet<SDNode*, 2> Copies;
2304 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2306 if (UI->getOpcode() != ISD::CopyToReg)
2310 if (Copies.size() > 2)
2313 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2315 SDValue UseChain = UI->getOperand(0);
2316 if (Copies.count(UseChain.getNode()))
2320 // We are at the top of this chain.
2321 // If the copy has a glue operand, we conservatively assume it
2322 // isn't safe to perform a tail call.
2323 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2329 } else if (Copy->getOpcode() == ISD::BITCAST) {
2330 // f32 returned in a single GPR.
2331 if (!Copy->hasOneUse())
2333 Copy = *Copy->use_begin();
2334 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2336 // If the copy has a glue operand, we conservatively assume it isn't safe to
2337 // perform a tail call.
2338 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2340 TCChain = Copy->getOperand(0);
2345 bool HasRet = false;
2346 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2348 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2349 UI->getOpcode() != ARMISD::INTRET_FLAG)
2361 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2362 if (!Subtarget->supportsTailCall())
2365 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2368 return !Subtarget->isThumb1Only();
2371 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2372 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2373 // one of the above mentioned nodes. It has to be wrapped because otherwise
2374 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2375 // be used to form addressing mode. These wrapped nodes will be selected
2377 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2378 EVT PtrVT = Op.getValueType();
2379 // FIXME there is no actual debug info here
2381 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2383 if (CP->isMachineConstantPoolEntry())
2384 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2385 CP->getAlignment());
2387 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2388 CP->getAlignment());
2389 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2392 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2393 return MachineJumpTableInfo::EK_Inline;
2396 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2397 SelectionDAG &DAG) const {
2398 MachineFunction &MF = DAG.getMachineFunction();
2399 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2400 unsigned ARMPCLabelIndex = 0;
2402 EVT PtrVT = getPointerTy();
2403 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2404 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2406 if (RelocM == Reloc::Static) {
2407 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2409 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2410 ARMPCLabelIndex = AFI->createPICLabelUId();
2411 ARMConstantPoolValue *CPV =
2412 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2413 ARMCP::CPBlockAddress, PCAdj);
2414 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2416 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2417 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2418 MachinePointerInfo::getConstantPool(),
2419 false, false, false, 0);
2420 if (RelocM == Reloc::Static)
2422 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2423 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2426 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2428 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2429 SelectionDAG &DAG) const {
2431 EVT PtrVT = getPointerTy();
2432 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2433 MachineFunction &MF = DAG.getMachineFunction();
2434 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2435 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2436 ARMConstantPoolValue *CPV =
2437 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2438 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2439 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2440 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2441 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2442 MachinePointerInfo::getConstantPool(),
2443 false, false, false, 0);
2444 SDValue Chain = Argument.getValue(1);
2446 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2447 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2449 // call __tls_get_addr.
2452 Entry.Node = Argument;
2453 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2454 Args.push_back(Entry);
2456 // FIXME: is there useful debug info available here?
2457 TargetLowering::CallLoweringInfo CLI(DAG);
2458 CLI.setDebugLoc(dl).setChain(Chain)
2459 .setCallee(CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2460 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args),
2463 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2464 return CallResult.first;
2467 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2468 // "local exec" model.
2470 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2472 TLSModel::Model model) const {
2473 const GlobalValue *GV = GA->getGlobal();
2476 SDValue Chain = DAG.getEntryNode();
2477 EVT PtrVT = getPointerTy();
2478 // Get the Thread Pointer
2479 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2481 if (model == TLSModel::InitialExec) {
2482 MachineFunction &MF = DAG.getMachineFunction();
2483 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2484 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2485 // Initial exec model.
2486 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2487 ARMConstantPoolValue *CPV =
2488 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2489 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2491 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2492 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2493 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2494 MachinePointerInfo::getConstantPool(),
2495 false, false, false, 0);
2496 Chain = Offset.getValue(1);
2498 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2499 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2501 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2502 MachinePointerInfo::getConstantPool(),
2503 false, false, false, 0);
2506 assert(model == TLSModel::LocalExec);
2507 ARMConstantPoolValue *CPV =
2508 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2509 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2510 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2511 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2512 MachinePointerInfo::getConstantPool(),
2513 false, false, false, 0);
2516 // The address of the thread local variable is the add of the thread
2517 // pointer with the offset of the variable.
2518 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2522 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2523 // TODO: implement the "local dynamic" model
2524 assert(Subtarget->isTargetELF() &&
2525 "TLS not implemented for non-ELF targets");
2526 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2528 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2531 case TLSModel::GeneralDynamic:
2532 case TLSModel::LocalDynamic:
2533 return LowerToTLSGeneralDynamicModel(GA, DAG);
2534 case TLSModel::InitialExec:
2535 case TLSModel::LocalExec:
2536 return LowerToTLSExecModels(GA, DAG, model);
2538 llvm_unreachable("bogus TLS model");
2541 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2542 SelectionDAG &DAG) const {
2543 EVT PtrVT = getPointerTy();
2545 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2546 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2547 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2548 ARMConstantPoolValue *CPV =
2549 ARMConstantPoolConstant::Create(GV,
2550 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2551 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2552 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2553 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2555 MachinePointerInfo::getConstantPool(),
2556 false, false, false, 0);
2557 SDValue Chain = Result.getValue(1);
2558 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2559 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2561 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2562 MachinePointerInfo::getGOT(),
2563 false, false, false, 0);
2567 // If we have T2 ops, we can materialize the address directly via movt/movw
2568 // pair. This is always cheaper.
2569 if (Subtarget->useMovt(DAG.getMachineFunction())) {
2571 // FIXME: Once remat is capable of dealing with instructions with register
2572 // operands, expand this into two nodes.
2573 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2574 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2576 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2577 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2578 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2579 MachinePointerInfo::getConstantPool(),
2580 false, false, false, 0);
2584 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2585 SelectionDAG &DAG) const {
2586 EVT PtrVT = getPointerTy();
2588 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2589 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2591 if (Subtarget->useMovt(DAG.getMachineFunction()))
2594 // FIXME: Once remat is capable of dealing with instructions with register
2595 // operands, expand this into multiple nodes
2597 RelocM == Reloc::PIC_ ? ARMISD::WrapperPIC : ARMISD::Wrapper;
2599 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
2600 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
2602 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2603 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2604 MachinePointerInfo::getGOT(), false, false, false, 0);
2608 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
2609 SelectionDAG &DAG) const {
2610 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
2611 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&
2612 "Windows on ARM expects to use movw/movt");
2614 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2615 const ARMII::TOF TargetFlags =
2616 (GV->hasDLLImportStorageClass() ? ARMII::MO_DLLIMPORT : ARMII::MO_NO_FLAG);
2617 EVT PtrVT = getPointerTy();
2623 // FIXME: Once remat is capable of dealing with instructions with register
2624 // operands, expand this into two nodes.
2625 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
2626 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
2628 if (GV->hasDLLImportStorageClass())
2629 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2630 MachinePointerInfo::getGOT(), false, false, false, 0);
2634 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2635 SelectionDAG &DAG) const {
2636 assert(Subtarget->isTargetELF() &&
2637 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2638 MachineFunction &MF = DAG.getMachineFunction();
2639 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2640 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2641 EVT PtrVT = getPointerTy();
2643 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2644 ARMConstantPoolValue *CPV =
2645 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2646 ARMPCLabelIndex, PCAdj);
2647 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2648 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2649 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2650 MachinePointerInfo::getConstantPool(),
2651 false, false, false, 0);
2652 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2653 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2657 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2659 SDValue Val = DAG.getConstant(0, MVT::i32);
2660 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2661 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2662 Op.getOperand(1), Val);
2666 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2668 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2669 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2673 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2674 const ARMSubtarget *Subtarget) const {
2675 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2678 default: return SDValue(); // Don't custom lower most intrinsics.
2679 case Intrinsic::arm_rbit: {
2680 assert(Op.getOperand(1).getValueType() == MVT::i32 &&
2681 "RBIT intrinsic must have i32 type!");
2682 return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(1));
2684 case Intrinsic::arm_thread_pointer: {
2685 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2686 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2688 case Intrinsic::eh_sjlj_lsda: {
2689 MachineFunction &MF = DAG.getMachineFunction();
2690 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2691 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2692 EVT PtrVT = getPointerTy();
2693 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2695 unsigned PCAdj = (RelocM != Reloc::PIC_)
2696 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2697 ARMConstantPoolValue *CPV =
2698 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2699 ARMCP::CPLSDA, PCAdj);
2700 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2701 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2703 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2704 MachinePointerInfo::getConstantPool(),
2705 false, false, false, 0);
2707 if (RelocM == Reloc::PIC_) {
2708 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2709 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2713 case Intrinsic::arm_neon_vmulls:
2714 case Intrinsic::arm_neon_vmullu: {
2715 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2716 ? ARMISD::VMULLs : ARMISD::VMULLu;
2717 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2718 Op.getOperand(1), Op.getOperand(2));
2723 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2724 const ARMSubtarget *Subtarget) {
2725 // FIXME: handle "fence singlethread" more efficiently.
2727 if (!Subtarget->hasDataBarrier()) {
2728 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2729 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2731 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2732 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
2733 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2734 DAG.getConstant(0, MVT::i32));
2737 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
2738 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
2739 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
2740 if (Subtarget->isMClass()) {
2741 // Only a full system barrier exists in the M-class architectures.
2742 Domain = ARM_MB::SY;
2743 } else if (Subtarget->isSwift() && Ord == Release) {
2744 // Swift happens to implement ISHST barriers in a way that's compatible with
2745 // Release semantics but weaker than ISH so we'd be fools not to use
2746 // it. Beware: other processors probably don't!
2747 Domain = ARM_MB::ISHST;
2750 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
2751 DAG.getConstant(Intrinsic::arm_dmb, MVT::i32),
2752 DAG.getConstant(Domain, MVT::i32));
2755 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2756 const ARMSubtarget *Subtarget) {
2757 // ARM pre v5TE and Thumb1 does not have preload instructions.
2758 if (!(Subtarget->isThumb2() ||
2759 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2760 // Just preserve the chain.
2761 return Op.getOperand(0);
2764 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2766 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2767 // ARMv7 with MP extension has PLDW.
2768 return Op.getOperand(0);
2770 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2771 if (Subtarget->isThumb()) {
2773 isRead = ~isRead & 1;
2774 isData = ~isData & 1;
2777 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2778 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2779 DAG.getConstant(isData, MVT::i32));
2782 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2783 MachineFunction &MF = DAG.getMachineFunction();
2784 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2786 // vastart just stores the address of the VarArgsFrameIndex slot into the
2787 // memory location argument.
2789 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2790 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2791 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2792 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2793 MachinePointerInfo(SV), false, false, 0);
2797 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2798 SDValue &Root, SelectionDAG &DAG,
2800 MachineFunction &MF = DAG.getMachineFunction();
2801 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2803 const TargetRegisterClass *RC;
2804 if (AFI->isThumb1OnlyFunction())
2805 RC = &ARM::tGPRRegClass;
2807 RC = &ARM::GPRRegClass;
2809 // Transform the arguments stored in physical registers into virtual ones.
2810 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2811 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2814 if (NextVA.isMemLoc()) {
2815 MachineFrameInfo *MFI = MF.getFrameInfo();
2816 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2818 // Create load node to retrieve arguments from the stack.
2819 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2820 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2821 MachinePointerInfo::getFixedStack(FI),
2822 false, false, false, 0);
2824 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2825 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2827 if (!Subtarget->isLittle())
2828 std::swap (ArgValue, ArgValue2);
2829 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2833 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2834 unsigned InRegsParamRecordIdx,
2836 unsigned &ArgRegsSize,
2837 unsigned &ArgRegsSaveSize)
2840 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2841 unsigned RBegin, REnd;
2842 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2843 NumGPRs = REnd - RBegin;
2845 unsigned int firstUnalloced;
2846 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2847 sizeof(GPRArgRegs) /
2848 sizeof(GPRArgRegs[0]));
2849 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2852 unsigned Align = MF.getTarget()
2854 ->getFrameLowering()
2855 ->getStackAlignment();
2856 ArgRegsSize = NumGPRs * 4;
2858 // If parameter is split between stack and GPRs...
2859 if (NumGPRs && Align > 4 &&
2860 (ArgRegsSize < ArgSize ||
2861 InRegsParamRecordIdx >= CCInfo.getInRegsParamsCount())) {
2862 // Add padding for part of param recovered from GPRs. For example,
2863 // if Align == 8, its last byte must be at address K*8 - 1.
2864 // We need to do it, since remained (stack) part of parameter has
2865 // stack alignment, and we need to "attach" "GPRs head" without gaps
2868 // |---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
2869 // [ [padding] [GPRs head] ] [ Tail passed via stack ....
2871 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2873 OffsetToAlignment(ArgRegsSize + AFI->getArgRegsSaveSize(), Align);
2874 ArgRegsSaveSize = ArgRegsSize + Padding;
2876 // We don't need to extend regs save size for byval parameters if they
2877 // are passed via GPRs only.
2878 ArgRegsSaveSize = ArgRegsSize;
2881 // The remaining GPRs hold either the beginning of variable-argument
2882 // data, or the beginning of an aggregate passed by value (usually
2883 // byval). Either way, we allocate stack slots adjacent to the data
2884 // provided by our caller, and store the unallocated registers there.
2885 // If this is a variadic function, the va_list pointer will begin with
2886 // these values; otherwise, this reassembles a (byval) structure that
2887 // was split between registers and memory.
2888 // Return: The frame index registers were stored into.
2890 ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
2891 SDLoc dl, SDValue &Chain,
2892 const Value *OrigArg,
2893 unsigned InRegsParamRecordIdx,
2894 unsigned OffsetFromOrigArg,
2898 unsigned ByValStoreOffset,
2899 unsigned TotalArgRegsSaveSize) const {
2901 // Currently, two use-cases possible:
2902 // Case #1. Non-var-args function, and we meet first byval parameter.
2903 // Setup first unallocated register as first byval register;
2904 // eat all remained registers
2905 // (these two actions are performed by HandleByVal method).
2906 // Then, here, we initialize stack frame with
2907 // "store-reg" instructions.
2908 // Case #2. Var-args function, that doesn't contain byval parameters.
2909 // The same: eat all remained unallocated registers,
2910 // initialize stack frame.
2912 MachineFunction &MF = DAG.getMachineFunction();
2913 MachineFrameInfo *MFI = MF.getFrameInfo();
2914 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2915 unsigned firstRegToSaveIndex, lastRegToSaveIndex;
2916 unsigned RBegin, REnd;
2917 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2918 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2919 firstRegToSaveIndex = RBegin - ARM::R0;
2920 lastRegToSaveIndex = REnd - ARM::R0;
2922 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2923 (GPRArgRegs, array_lengthof(GPRArgRegs));
2924 lastRegToSaveIndex = 4;
2927 unsigned ArgRegsSize, ArgRegsSaveSize;
2928 computeRegArea(CCInfo, MF, InRegsParamRecordIdx, ArgSize,
2929 ArgRegsSize, ArgRegsSaveSize);
2931 // Store any by-val regs to their spots on the stack so that they may be
2932 // loaded by deferencing the result of formal parameter pointer or va_next.
2933 // Note: once stack area for byval/varargs registers
2934 // was initialized, it can't be initialized again.
2935 if (ArgRegsSaveSize) {
2936 unsigned Padding = ArgRegsSaveSize - ArgRegsSize;
2939 assert(AFI->getStoredByValParamsPadding() == 0 &&
2940 "The only parameter may be padded.");
2941 AFI->setStoredByValParamsPadding(Padding);
2944 int FrameIndex = MFI->CreateFixedObject(ArgRegsSaveSize,
2947 (int64_t)TotalArgRegsSaveSize,
2949 SDValue FIN = DAG.getFrameIndex(FrameIndex, getPointerTy());
2951 MFI->CreateFixedObject(Padding,
2952 ArgOffset + ByValStoreOffset -
2953 (int64_t)ArgRegsSaveSize,
2957 SmallVector<SDValue, 4> MemOps;
2958 for (unsigned i = 0; firstRegToSaveIndex < lastRegToSaveIndex;
2959 ++firstRegToSaveIndex, ++i) {
2960 const TargetRegisterClass *RC;
2961 if (AFI->isThumb1OnlyFunction())
2962 RC = &ARM::tGPRRegClass;
2964 RC = &ARM::GPRRegClass;
2966 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2967 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2969 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2970 MachinePointerInfo(OrigArg, OffsetFromOrigArg + 4*i),
2972 MemOps.push_back(Store);
2973 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2974 DAG.getConstant(4, getPointerTy()));
2977 AFI->setArgRegsSaveSize(ArgRegsSaveSize + AFI->getArgRegsSaveSize());
2979 if (!MemOps.empty())
2980 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2984 // We cannot allocate a zero-byte object for the first variadic argument,
2985 // so just make up a size.
2988 // This will point to the next argument passed via stack.
2989 return MFI->CreateFixedObject(
2990 ArgSize, ArgOffset, !ForceMutable);
2994 // Setup stack frame, the va_list pointer will start from.
2996 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2997 SDLoc dl, SDValue &Chain,
2999 unsigned TotalArgRegsSaveSize,
3000 bool ForceMutable) const {
3001 MachineFunction &MF = DAG.getMachineFunction();
3002 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3004 // Try to store any remaining integer argument regs
3005 // to their spots on the stack so that they may be loaded by deferencing
3006 // the result of va_next.
3007 // If there is no regs to be stored, just point address after last
3008 // argument passed via stack.
3010 StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3011 CCInfo.getInRegsParamsCount(), 0, ArgOffset, 0, ForceMutable,
3012 0, TotalArgRegsSaveSize);
3014 AFI->setVarArgsFrameIndex(FrameIndex);
3018 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
3019 CallingConv::ID CallConv, bool isVarArg,
3020 const SmallVectorImpl<ISD::InputArg>
3022 SDLoc dl, SelectionDAG &DAG,
3023 SmallVectorImpl<SDValue> &InVals)
3025 MachineFunction &MF = DAG.getMachineFunction();
3026 MachineFrameInfo *MFI = MF.getFrameInfo();
3028 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3030 // Assign locations to all of the incoming arguments.
3031 SmallVector<CCValAssign, 16> ArgLocs;
3032 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3033 *DAG.getContext(), Prologue);
3034 CCInfo.AnalyzeFormalArguments(Ins,
3035 CCAssignFnForNode(CallConv, /* Return*/ false,
3038 SmallVector<SDValue, 16> ArgValues;
3039 int lastInsIndex = -1;
3041 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
3042 unsigned CurArgIdx = 0;
3044 // Initially ArgRegsSaveSize is zero.
3045 // Then we increase this value each time we meet byval parameter.
3046 // We also increase this value in case of varargs function.
3047 AFI->setArgRegsSaveSize(0);
3049 unsigned ByValStoreOffset = 0;
3050 unsigned TotalArgRegsSaveSize = 0;
3051 unsigned ArgRegsSaveSizeMaxAlign = 4;
3053 // Calculate the amount of stack space that we need to allocate to store
3054 // byval and variadic arguments that are passed in registers.
3055 // We need to know this before we allocate the first byval or variadic
3056 // argument, as they will be allocated a stack slot below the CFA (Canonical
3057 // Frame Address, the stack pointer at entry to the function).
3058 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3059 CCValAssign &VA = ArgLocs[i];
3060 if (VA.isMemLoc()) {
3061 int index = VA.getValNo();
3062 if (index != lastInsIndex) {
3063 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3064 if (Flags.isByVal()) {
3065 unsigned ExtraArgRegsSize;
3066 unsigned ExtraArgRegsSaveSize;
3067 computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsProcessed(),
3068 Flags.getByValSize(),
3069 ExtraArgRegsSize, ExtraArgRegsSaveSize);
3071 TotalArgRegsSaveSize += ExtraArgRegsSaveSize;
3072 if (Flags.getByValAlign() > ArgRegsSaveSizeMaxAlign)
3073 ArgRegsSaveSizeMaxAlign = Flags.getByValAlign();
3074 CCInfo.nextInRegsParam();
3076 lastInsIndex = index;
3080 CCInfo.rewindByValRegsInfo();
3082 if (isVarArg && MFI->hasVAStart()) {
3083 unsigned ExtraArgRegsSize;
3084 unsigned ExtraArgRegsSaveSize;
3085 computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsCount(), 0,
3086 ExtraArgRegsSize, ExtraArgRegsSaveSize);
3087 TotalArgRegsSaveSize += ExtraArgRegsSaveSize;
3089 // If the arg regs save area contains N-byte aligned values, the
3090 // bottom of it must be at least N-byte aligned.
3091 TotalArgRegsSaveSize = RoundUpToAlignment(TotalArgRegsSaveSize, ArgRegsSaveSizeMaxAlign);
3092 TotalArgRegsSaveSize = std::min(TotalArgRegsSaveSize, 16U);
3094 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3095 CCValAssign &VA = ArgLocs[i];
3096 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
3097 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
3098 // Arguments stored in registers.
3099 if (VA.isRegLoc()) {
3100 EVT RegVT = VA.getLocVT();
3102 if (VA.needsCustom()) {
3103 // f64 and vector types are split up into multiple registers or
3104 // combinations of registers and stack slots.
3105 if (VA.getLocVT() == MVT::v2f64) {
3106 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3108 VA = ArgLocs[++i]; // skip ahead to next loc
3110 if (VA.isMemLoc()) {
3111 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
3112 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3113 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3114 MachinePointerInfo::getFixedStack(FI),
3115 false, false, false, 0);
3117 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3120 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3121 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3122 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
3123 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3124 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
3126 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3129 const TargetRegisterClass *RC;
3131 if (RegVT == MVT::f32)
3132 RC = &ARM::SPRRegClass;
3133 else if (RegVT == MVT::f64)
3134 RC = &ARM::DPRRegClass;
3135 else if (RegVT == MVT::v2f64)
3136 RC = &ARM::QPRRegClass;
3137 else if (RegVT == MVT::i32)
3138 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3139 : &ARM::GPRRegClass;
3141 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
3143 // Transform the arguments in physical registers into virtual ones.
3144 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3145 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3148 // If this is an 8 or 16-bit value, it is really passed promoted
3149 // to 32 bits. Insert an assert[sz]ext to capture this, then
3150 // truncate to the right size.
3151 switch (VA.getLocInfo()) {
3152 default: llvm_unreachable("Unknown loc info!");
3153 case CCValAssign::Full: break;
3154 case CCValAssign::BCvt:
3155 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3157 case CCValAssign::SExt:
3158 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3159 DAG.getValueType(VA.getValVT()));
3160 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3162 case CCValAssign::ZExt:
3163 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3164 DAG.getValueType(VA.getValVT()));
3165 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3169 InVals.push_back(ArgValue);
3171 } else { // VA.isRegLoc()
3174 assert(VA.isMemLoc());
3175 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3177 int index = ArgLocs[i].getValNo();
3179 // Some Ins[] entries become multiple ArgLoc[] entries.
3180 // Process them only once.
3181 if (index != lastInsIndex)
3183 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3184 // FIXME: For now, all byval parameter objects are marked mutable.
3185 // This can be changed with more analysis.
3186 // In case of tail call optimization mark all arguments mutable.
3187 // Since they could be overwritten by lowering of arguments in case of
3189 if (Flags.isByVal()) {
3190 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3192 ByValStoreOffset = RoundUpToAlignment(ByValStoreOffset, Flags.getByValAlign());
3193 int FrameIndex = StoreByValRegs(
3194 CCInfo, DAG, dl, Chain, CurOrigArg,
3196 Ins[VA.getValNo()].PartOffset,
3197 VA.getLocMemOffset(),
3198 Flags.getByValSize(),
3199 true /*force mutable frames*/,
3201 TotalArgRegsSaveSize);
3202 ByValStoreOffset += Flags.getByValSize();
3203 ByValStoreOffset = std::min(ByValStoreOffset, 16U);
3204 InVals.push_back(DAG.getFrameIndex(FrameIndex, getPointerTy()));
3205 CCInfo.nextInRegsParam();
3207 unsigned FIOffset = VA.getLocMemOffset();
3208 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3211 // Create load nodes to retrieve arguments from the stack.
3212 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3213 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3214 MachinePointerInfo::getFixedStack(FI),
3215 false, false, false, 0));
3217 lastInsIndex = index;
3223 if (isVarArg && MFI->hasVAStart())
3224 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3225 CCInfo.getNextStackOffset(),
3226 TotalArgRegsSaveSize);
3228 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3233 /// isFloatingPointZero - Return true if this is +0.0.
3234 static bool isFloatingPointZero(SDValue Op) {
3235 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3236 return CFP->getValueAPF().isPosZero();
3237 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3238 // Maybe this has already been legalized into the constant pool?
3239 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3240 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3241 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3242 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3243 return CFP->getValueAPF().isPosZero();
3245 } else if (Op->getOpcode() == ISD::BITCAST &&
3246 Op->getValueType(0) == MVT::f64) {
3247 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3248 // created by LowerConstantFP().
3249 SDValue BitcastOp = Op->getOperand(0);
3250 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM) {
3251 SDValue MoveOp = BitcastOp->getOperand(0);
3252 if (MoveOp->getOpcode() == ISD::TargetConstant &&
3253 cast<ConstantSDNode>(MoveOp)->getZExtValue() == 0) {
3261 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3262 /// the given operands.
3264 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3265 SDValue &ARMcc, SelectionDAG &DAG,
3267 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3268 unsigned C = RHSC->getZExtValue();
3269 if (!isLegalICmpImmediate(C)) {
3270 // Constant does not fit, try adjusting it by one?
3275 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3276 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3277 RHS = DAG.getConstant(C-1, MVT::i32);
3282 if (C != 0 && isLegalICmpImmediate(C-1)) {
3283 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3284 RHS = DAG.getConstant(C-1, MVT::i32);
3289 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3290 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3291 RHS = DAG.getConstant(C+1, MVT::i32);
3296 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3297 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3298 RHS = DAG.getConstant(C+1, MVT::i32);
3305 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3306 ARMISD::NodeType CompareType;
3309 CompareType = ARMISD::CMP;
3314 CompareType = ARMISD::CMPZ;
3317 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3318 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3321 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3323 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
3325 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64);
3327 if (!isFloatingPointZero(RHS))
3328 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3330 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3331 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3334 /// duplicateCmp - Glue values can have only one use, so this function
3335 /// duplicates a comparison node.
3337 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3338 unsigned Opc = Cmp.getOpcode();
3340 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3341 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3343 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3344 Cmp = Cmp.getOperand(0);
3345 Opc = Cmp.getOpcode();
3346 if (Opc == ARMISD::CMPFP)
3347 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3349 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3350 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3352 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3355 std::pair<SDValue, SDValue>
3356 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3357 SDValue &ARMcc) const {
3358 assert(Op.getValueType() == MVT::i32 && "Unsupported value type");
3360 SDValue Value, OverflowCmp;
3361 SDValue LHS = Op.getOperand(0);
3362 SDValue RHS = Op.getOperand(1);
3365 // FIXME: We are currently always generating CMPs because we don't support
3366 // generating CMN through the backend. This is not as good as the natural
3367 // CMP case because it causes a register dependency and cannot be folded
3370 switch (Op.getOpcode()) {
3372 llvm_unreachable("Unknown overflow instruction!");
3374 ARMcc = DAG.getConstant(ARMCC::VC, MVT::i32);
3375 Value = DAG.getNode(ISD::ADD, SDLoc(Op), Op.getValueType(), LHS, RHS);
3376 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, Value, LHS);
3379 ARMcc = DAG.getConstant(ARMCC::HS, MVT::i32);
3380 Value = DAG.getNode(ISD::ADD, SDLoc(Op), Op.getValueType(), LHS, RHS);
3381 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, Value, LHS);
3384 ARMcc = DAG.getConstant(ARMCC::VC, MVT::i32);
3385 Value = DAG.getNode(ISD::SUB, SDLoc(Op), Op.getValueType(), LHS, RHS);
3386 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, LHS, RHS);
3389 ARMcc = DAG.getConstant(ARMCC::HS, MVT::i32);
3390 Value = DAG.getNode(ISD::SUB, SDLoc(Op), Op.getValueType(), LHS, RHS);
3391 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, LHS, RHS);
3395 return std::make_pair(Value, OverflowCmp);
3400 ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
3401 // Let legalize expand this if it isn't a legal type yet.
3402 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
3405 SDValue Value, OverflowCmp;
3407 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
3408 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3409 // We use 0 and 1 as false and true values.
3410 SDValue TVal = DAG.getConstant(1, MVT::i32);
3411 SDValue FVal = DAG.getConstant(0, MVT::i32);
3412 EVT VT = Op.getValueType();
3414 SDValue Overflow = DAG.getNode(ARMISD::CMOV, SDLoc(Op), VT, TVal, FVal,
3415 ARMcc, CCR, OverflowCmp);
3417 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
3418 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
3422 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3423 SDValue Cond = Op.getOperand(0);
3424 SDValue SelectTrue = Op.getOperand(1);
3425 SDValue SelectFalse = Op.getOperand(2);
3427 unsigned Opc = Cond.getOpcode();
3429 if (Cond.getResNo() == 1 &&
3430 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3431 Opc == ISD::USUBO)) {
3432 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
3435 SDValue Value, OverflowCmp;
3437 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
3438 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3439 EVT VT = Op.getValueType();
3441 return getCMOV(SDLoc(Op), VT, SelectTrue, SelectFalse, ARMcc, CCR,
3447 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
3448 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
3450 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3451 const ConstantSDNode *CMOVTrue =
3452 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
3453 const ConstantSDNode *CMOVFalse =
3454 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3456 if (CMOVTrue && CMOVFalse) {
3457 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
3458 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
3462 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
3464 False = SelectFalse;
3465 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
3470 if (True.getNode() && False.getNode()) {
3471 EVT VT = Op.getValueType();
3472 SDValue ARMcc = Cond.getOperand(2);
3473 SDValue CCR = Cond.getOperand(3);
3474 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
3475 assert(True.getValueType() == VT);
3476 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
3481 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
3482 // undefined bits before doing a full-word comparison with zero.
3483 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
3484 DAG.getConstant(1, Cond.getValueType()));
3486 return DAG.getSelectCC(dl, Cond,
3487 DAG.getConstant(0, Cond.getValueType()),
3488 SelectTrue, SelectFalse, ISD::SETNE);
3491 static ISD::CondCode getInverseCCForVSEL(ISD::CondCode CC) {
3492 if (CC == ISD::SETNE)
3494 return ISD::getSetCCInverse(CC, true);
3497 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
3498 bool &swpCmpOps, bool &swpVselOps) {
3499 // Start by selecting the GE condition code for opcodes that return true for
3501 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
3503 CondCode = ARMCC::GE;
3505 // and GT for opcodes that return false for 'equality'.
3506 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
3508 CondCode = ARMCC::GT;
3510 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3511 // to swap the compare operands.
3512 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3516 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
3517 // If we have an unordered opcode, we need to swap the operands to the VSEL
3518 // instruction (effectively negating the condition).
3520 // This also has the effect of swapping which one of 'less' or 'greater'
3521 // returns true, so we also swap the compare operands. It also switches
3522 // whether we return true for 'equality', so we compensate by picking the
3523 // opposite condition code to our original choice.
3524 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
3525 CC == ISD::SETUGT) {
3526 swpCmpOps = !swpCmpOps;
3527 swpVselOps = !swpVselOps;
3528 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
3531 // 'ordered' is 'anything but unordered', so use the VS condition code and
3532 // swap the VSEL operands.
3533 if (CC == ISD::SETO) {
3534 CondCode = ARMCC::VS;
3538 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
3539 // code and swap the VSEL operands.
3540 if (CC == ISD::SETUNE) {
3541 CondCode = ARMCC::EQ;
3546 SDValue ARMTargetLowering::getCMOV(SDLoc dl, EVT VT, SDValue FalseVal,
3547 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
3548 SDValue Cmp, SelectionDAG &DAG) const {
3549 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
3550 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3551 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
3552 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3553 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
3555 SDValue TrueLow = TrueVal.getValue(0);
3556 SDValue TrueHigh = TrueVal.getValue(1);
3557 SDValue FalseLow = FalseVal.getValue(0);
3558 SDValue FalseHigh = FalseVal.getValue(1);
3560 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
3562 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
3563 ARMcc, CCR, duplicateCmp(Cmp, DAG));
3565 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
3567 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3572 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3573 EVT VT = Op.getValueType();
3574 SDValue LHS = Op.getOperand(0);
3575 SDValue RHS = Op.getOperand(1);
3576 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3577 SDValue TrueVal = Op.getOperand(2);
3578 SDValue FalseVal = Op.getOperand(3);
3581 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3582 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3585 // If softenSetCCOperands only returned one value, we should compare it to
3587 if (!RHS.getNode()) {
3588 RHS = DAG.getConstant(0, LHS.getValueType());
3593 if (LHS.getValueType() == MVT::i32) {
3594 // Try to generate VSEL on ARMv8.
3595 // The VSEL instruction can't use all the usual ARM condition
3596 // codes: it only has two bits to select the condition code, so it's
3597 // constrained to use only GE, GT, VS and EQ.
3599 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
3600 // swap the operands of the previous compare instruction (effectively
3601 // inverting the compare condition, swapping 'less' and 'greater') and
3602 // sometimes need to swap the operands to the VSEL (which inverts the
3603 // condition in the sense of firing whenever the previous condition didn't)
3604 if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3605 TrueVal.getValueType() == MVT::f64)) {
3606 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3607 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
3608 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
3609 CC = getInverseCCForVSEL(CC);
3610 std::swap(TrueVal, FalseVal);
3615 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3616 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3617 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3620 ARMCC::CondCodes CondCode, CondCode2;
3621 FPCCToARMCC(CC, CondCode, CondCode2);
3623 // Try to generate VSEL on ARMv8.
3624 if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3625 TrueVal.getValueType() == MVT::f64)) {
3626 // We can select VMAXNM/VMINNM from a compare followed by a select with the
3627 // same operands, as follows:
3628 // c = fcmp [ogt, olt, ugt, ult] a, b
3630 // We only do this in unsafe-fp-math, because signed zeros and NaNs are
3631 // handled differently than the original code sequence.
3632 if (getTargetMachine().Options.UnsafeFPMath) {
3633 if (LHS == TrueVal && RHS == FalseVal) {
3634 if (CC == ISD::SETOGT || CC == ISD::SETUGT)
3635 return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3636 if (CC == ISD::SETOLT || CC == ISD::SETULT)
3637 return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3638 } else if (LHS == FalseVal && RHS == TrueVal) {
3639 if (CC == ISD::SETOLT || CC == ISD::SETULT)
3640 return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3641 if (CC == ISD::SETOGT || CC == ISD::SETUGT)
3642 return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3646 bool swpCmpOps = false;
3647 bool swpVselOps = false;
3648 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
3650 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
3651 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3653 std::swap(LHS, RHS);
3655 std::swap(TrueVal, FalseVal);
3659 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3660 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3661 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3662 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3663 if (CondCode2 != ARMCC::AL) {
3664 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
3665 // FIXME: Needs another CMP because flag can have but one use.
3666 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
3667 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
3672 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
3673 /// to morph to an integer compare sequence.
3674 static bool canChangeToInt(SDValue Op, bool &SeenZero,
3675 const ARMSubtarget *Subtarget) {
3676 SDNode *N = Op.getNode();
3677 if (!N->hasOneUse())
3678 // Otherwise it requires moving the value from fp to integer registers.
3680 if (!N->getNumValues())
3682 EVT VT = Op.getValueType();
3683 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3684 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
3685 // vmrs are very slow, e.g. cortex-a8.
3688 if (isFloatingPointZero(Op)) {
3692 return ISD::isNormalLoad(N);
3695 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3696 if (isFloatingPointZero(Op))
3697 return DAG.getConstant(0, MVT::i32);
3699 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
3700 return DAG.getLoad(MVT::i32, SDLoc(Op),
3701 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3702 Ld->isVolatile(), Ld->isNonTemporal(),
3703 Ld->isInvariant(), Ld->getAlignment());
3705 llvm_unreachable("Unknown VFP cmp argument!");
3708 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3709 SDValue &RetVal1, SDValue &RetVal2) {
3710 if (isFloatingPointZero(Op)) {
3711 RetVal1 = DAG.getConstant(0, MVT::i32);
3712 RetVal2 = DAG.getConstant(0, MVT::i32);
3716 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3717 SDValue Ptr = Ld->getBasePtr();
3718 RetVal1 = DAG.getLoad(MVT::i32, SDLoc(Op),
3719 Ld->getChain(), Ptr,
3720 Ld->getPointerInfo(),
3721 Ld->isVolatile(), Ld->isNonTemporal(),
3722 Ld->isInvariant(), Ld->getAlignment());
3724 EVT PtrType = Ptr.getValueType();
3725 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
3726 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(Op),
3727 PtrType, Ptr, DAG.getConstant(4, PtrType));
3728 RetVal2 = DAG.getLoad(MVT::i32, SDLoc(Op),
3729 Ld->getChain(), NewPtr,
3730 Ld->getPointerInfo().getWithOffset(4),
3731 Ld->isVolatile(), Ld->isNonTemporal(),
3732 Ld->isInvariant(), NewAlign);
3736 llvm_unreachable("Unknown VFP cmp argument!");
3739 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3740 /// f32 and even f64 comparisons to integer ones.
3742 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3743 SDValue Chain = Op.getOperand(0);
3744 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3745 SDValue LHS = Op.getOperand(2);
3746 SDValue RHS = Op.getOperand(3);
3747 SDValue Dest = Op.getOperand(4);
3750 bool LHSSeenZero = false;
3751 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3752 bool RHSSeenZero = false;
3753 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3754 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3755 // If unsafe fp math optimization is enabled and there are no other uses of
3756 // the CMP operands, and the condition code is EQ or NE, we can optimize it
3757 // to an integer comparison.
3758 if (CC == ISD::SETOEQ)
3760 else if (CC == ISD::SETUNE)
3763 SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32);
3765 if (LHS.getValueType() == MVT::f32) {
3766 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3767 bitcastf32Toi32(LHS, DAG), Mask);
3768 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3769 bitcastf32Toi32(RHS, DAG), Mask);
3770 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3771 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3772 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3773 Chain, Dest, ARMcc, CCR, Cmp);
3778 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3779 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3780 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3781 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3782 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3783 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3784 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3785 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3786 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
3792 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3793 SDValue Chain = Op.getOperand(0);
3794 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3795 SDValue LHS = Op.getOperand(2);
3796 SDValue RHS = Op.getOperand(3);
3797 SDValue Dest = Op.getOperand(4);
3800 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3801 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3804 // If softenSetCCOperands only returned one value, we should compare it to
3806 if (!RHS.getNode()) {
3807 RHS = DAG.getConstant(0, LHS.getValueType());
3812 if (LHS.getValueType() == MVT::i32) {
3814 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3815 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3816 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3817 Chain, Dest, ARMcc, CCR, Cmp);
3820 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3822 if (getTargetMachine().Options.UnsafeFPMath &&
3823 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3824 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3825 SDValue Result = OptimizeVFPBrcond(Op, DAG);
3826 if (Result.getNode())
3830 ARMCC::CondCodes CondCode, CondCode2;
3831 FPCCToARMCC(CC, CondCode, CondCode2);
3833 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3834 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3835 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3836 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3837 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3838 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3839 if (CondCode2 != ARMCC::AL) {
3840 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3841 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3842 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3847 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3848 SDValue Chain = Op.getOperand(0);
3849 SDValue Table = Op.getOperand(1);
3850 SDValue Index = Op.getOperand(2);
3853 EVT PTy = getPointerTy();
3854 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3855 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3856 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
3857 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3858 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3859 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
3860 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3861 if (Subtarget->isThumb2()) {
3862 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3863 // which does another jump to the destination. This also makes it easier
3864 // to translate it to TBB / TBH later.
3865 // FIXME: This might not work if the function is extremely large.
3866 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3867 Addr, Op.getOperand(2), JTI, UId);
3869 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3870 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3871 MachinePointerInfo::getJumpTable(),
3872 false, false, false, 0);
3873 Chain = Addr.getValue(1);
3874 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3875 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3877 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3878 MachinePointerInfo::getJumpTable(),
3879 false, false, false, 0);
3880 Chain = Addr.getValue(1);
3881 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3885 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3886 EVT VT = Op.getValueType();
3889 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3890 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3892 return DAG.UnrollVectorOp(Op.getNode());
3895 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3896 "Invalid type for custom lowering!");
3897 if (VT != MVT::v4i16)
3898 return DAG.UnrollVectorOp(Op.getNode());
3900 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3901 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3904 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
3905 EVT VT = Op.getValueType();
3907 return LowerVectorFP_TO_INT(Op, DAG);
3909 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
3911 if (Op.getOpcode() == ISD::FP_TO_SINT)
3912 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
3915 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
3917 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3918 /*isSigned*/ false, SDLoc(Op)).first;
3924 switch (Op.getOpcode()) {
3925 default: llvm_unreachable("Invalid opcode!");
3926 case ISD::FP_TO_SINT:
3927 Opc = ARMISD::FTOSI;
3929 case ISD::FP_TO_UINT:
3930 Opc = ARMISD::FTOUI;
3933 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3934 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3937 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3938 EVT VT = Op.getValueType();
3941 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3942 if (VT.getVectorElementType() == MVT::f32)
3944 return DAG.UnrollVectorOp(Op.getNode());
3947 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3948 "Invalid type for custom lowering!");
3949 if (VT != MVT::v4f32)
3950 return DAG.UnrollVectorOp(Op.getNode());
3954 switch (Op.getOpcode()) {
3955 default: llvm_unreachable("Invalid opcode!");
3956 case ISD::SINT_TO_FP:
3957 CastOpc = ISD::SIGN_EXTEND;
3958 Opc = ISD::SINT_TO_FP;
3960 case ISD::UINT_TO_FP:
3961 CastOpc = ISD::ZERO_EXTEND;
3962 Opc = ISD::UINT_TO_FP;
3966 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3967 return DAG.getNode(Opc, dl, VT, Op);
3970 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
3971 EVT VT = Op.getValueType();
3973 return LowerVectorINT_TO_FP(Op, DAG);
3975 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
3977 if (Op.getOpcode() == ISD::SINT_TO_FP)
3978 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
3981 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
3983 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3984 /*isSigned*/ false, SDLoc(Op)).first;
3990 switch (Op.getOpcode()) {
3991 default: llvm_unreachable("Invalid opcode!");
3992 case ISD::SINT_TO_FP:
3993 Opc = ARMISD::SITOF;
3995 case ISD::UINT_TO_FP:
3996 Opc = ARMISD::UITOF;
4000 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
4001 return DAG.getNode(Opc, dl, VT, Op);
4004 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
4005 // Implement fcopysign with a fabs and a conditional fneg.
4006 SDValue Tmp0 = Op.getOperand(0);
4007 SDValue Tmp1 = Op.getOperand(1);
4009 EVT VT = Op.getValueType();
4010 EVT SrcVT = Tmp1.getValueType();
4011 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
4012 Tmp0.getOpcode() == ARMISD::VMOVDRR;
4013 bool UseNEON = !InGPR && Subtarget->hasNEON();
4016 // Use VBSL to copy the sign bit.
4017 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
4018 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
4019 DAG.getTargetConstant(EncodedVal, MVT::i32));
4020 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4022 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4023 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
4024 DAG.getConstant(32, MVT::i32));
4025 else /*if (VT == MVT::f32)*/
4026 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
4027 if (SrcVT == MVT::f32) {
4028 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
4030 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4031 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4032 DAG.getConstant(32, MVT::i32));
4033 } else if (VT == MVT::f32)
4034 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4035 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4036 DAG.getConstant(32, MVT::i32));
4037 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4038 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4040 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4042 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4043 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4044 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4046 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4047 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4048 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4049 if (VT == MVT::f32) {
4050 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4051 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4052 DAG.getConstant(0, MVT::i32));
4054 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4060 // Bitcast operand 1 to i32.
4061 if (SrcVT == MVT::f64)
4062 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4064 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4066 // Or in the signbit with integer operations.
4067 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
4068 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
4069 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
4070 if (VT == MVT::f32) {
4071 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
4072 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
4073 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4074 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
4077 // f64: Or the high part with signbit and then combine two parts.
4078 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4080 SDValue Lo = Tmp0.getValue(0);
4081 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
4082 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
4083 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
4086 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
4087 MachineFunction &MF = DAG.getMachineFunction();
4088 MachineFrameInfo *MFI = MF.getFrameInfo();
4089 MFI->setReturnAddressIsTaken(true);
4091 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
4094 EVT VT = Op.getValueType();
4096 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4098 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4099 SDValue Offset = DAG.getConstant(4, MVT::i32);
4100 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
4101 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
4102 MachinePointerInfo(), false, false, false, 0);
4105 // Return LR, which contains the return address. Mark it an implicit live-in.
4106 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4107 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
4110 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
4111 const ARMBaseRegisterInfo &ARI =
4112 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
4113 MachineFunction &MF = DAG.getMachineFunction();
4114 MachineFrameInfo *MFI = MF.getFrameInfo();
4115 MFI->setFrameAddressIsTaken(true);
4117 EVT VT = Op.getValueType();
4118 SDLoc dl(Op); // FIXME probably not meaningful
4119 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4120 unsigned FrameReg = ARI.getFrameRegister(MF);
4121 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
4123 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
4124 MachinePointerInfo(),
4125 false, false, false, 0);
4129 // FIXME? Maybe this could be a TableGen attribute on some registers and
4130 // this table could be generated automatically from RegInfo.
4131 unsigned ARMTargetLowering::getRegisterByName(const char* RegName,
4133 unsigned Reg = StringSwitch<unsigned>(RegName)
4134 .Case("sp", ARM::SP)
4138 report_fatal_error("Invalid register name global variable");
4141 /// ExpandBITCAST - If the target supports VFP, this function is called to
4142 /// expand a bit convert where either the source or destination type is i64 to
4143 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
4144 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
4145 /// vectors), since the legalizer won't know what to do with that.
4146 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
4147 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4149 SDValue Op = N->getOperand(0);
4151 // This function is only supposed to be called for i64 types, either as the
4152 // source or destination of the bit convert.
4153 EVT SrcVT = Op.getValueType();
4154 EVT DstVT = N->getValueType(0);
4155 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
4156 "ExpandBITCAST called for non-i64 type");
4158 // Turn i64->f64 into VMOVDRR.
4159 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
4160 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4161 DAG.getConstant(0, MVT::i32));
4162 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4163 DAG.getConstant(1, MVT::i32));
4164 return DAG.getNode(ISD::BITCAST, dl, DstVT,
4165 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
4168 // Turn f64->i64 into VMOVRRD.
4169 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
4171 if (TLI.isBigEndian() && SrcVT.isVector() &&
4172 SrcVT.getVectorNumElements() > 1)
4173 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4174 DAG.getVTList(MVT::i32, MVT::i32),
4175 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
4177 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4178 DAG.getVTList(MVT::i32, MVT::i32), Op);
4179 // Merge the pieces into a single i64 value.
4180 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
4186 /// getZeroVector - Returns a vector of specified type with all zero elements.
4187 /// Zero vectors are used to represent vector negation and in those cases
4188 /// will be implemented with the NEON VNEG instruction. However, VNEG does
4189 /// not support i64 elements, so sometimes the zero vectors will need to be
4190 /// explicitly constructed. Regardless, use a canonical VMOV to create the
4192 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) {
4193 assert(VT.isVector() && "Expected a vector type");
4194 // The canonical modified immediate encoding of a zero vector is....0!
4195 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
4196 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
4197 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
4198 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4201 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4202 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4203 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
4204 SelectionDAG &DAG) const {
4205 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4206 EVT VT = Op.getValueType();
4207 unsigned VTBits = VT.getSizeInBits();
4209 SDValue ShOpLo = Op.getOperand(0);
4210 SDValue ShOpHi = Op.getOperand(1);
4211 SDValue ShAmt = Op.getOperand(2);
4213 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4215 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4217 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4218 DAG.getConstant(VTBits, MVT::i32), ShAmt);
4219 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4220 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4221 DAG.getConstant(VTBits, MVT::i32));
4222 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4223 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4224 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4226 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4227 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
4229 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4230 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
4233 SDValue Ops[2] = { Lo, Hi };
4234 return DAG.getMergeValues(Ops, dl);
4237 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4238 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4239 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
4240 SelectionDAG &DAG) const {
4241 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4242 EVT VT = Op.getValueType();
4243 unsigned VTBits = VT.getSizeInBits();
4245 SDValue ShOpLo = Op.getOperand(0);
4246 SDValue ShOpHi = Op.getOperand(1);
4247 SDValue ShAmt = Op.getOperand(2);
4250 assert(Op.getOpcode() == ISD::SHL_PARTS);
4251 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4252 DAG.getConstant(VTBits, MVT::i32), ShAmt);
4253 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4254 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4255 DAG.getConstant(VTBits, MVT::i32));
4256 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4257 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4259 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4260 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4261 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
4263 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4264 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
4267 SDValue Ops[2] = { Lo, Hi };
4268 return DAG.getMergeValues(Ops, dl);
4271 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4272 SelectionDAG &DAG) const {
4273 // The rounding mode is in bits 23:22 of the FPSCR.
4274 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
4275 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
4276 // so that the shift + and get folded into a bitfield extract.
4278 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
4279 DAG.getConstant(Intrinsic::arm_get_fpscr,
4281 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
4282 DAG.getConstant(1U << 22, MVT::i32));
4283 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
4284 DAG.getConstant(22, MVT::i32));
4285 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
4286 DAG.getConstant(3, MVT::i32));
4289 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
4290 const ARMSubtarget *ST) {
4291 EVT VT = N->getValueType(0);
4294 if (!ST->hasV6T2Ops())
4297 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
4298 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
4301 /// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
4302 /// for each 16-bit element from operand, repeated. The basic idea is to
4303 /// leverage vcnt to get the 8-bit counts, gather and add the results.
4305 /// Trace for v4i16:
4306 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4307 /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
4308 /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
4309 /// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
4310 /// [b0 b1 b2 b3 b4 b5 b6 b7]
4311 /// +[b1 b0 b3 b2 b5 b4 b7 b6]
4312 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
4313 /// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
4314 static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
4315 EVT VT = N->getValueType(0);
4318 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
4319 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
4320 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
4321 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
4322 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
4323 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
4326 /// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
4327 /// bit-count for each 16-bit element from the operand. We need slightly
4328 /// different sequencing for v4i16 and v8i16 to stay within NEON's available
4329 /// 64/128-bit registers.
4331 /// Trace for v4i16:
4332 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4333 /// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
4334 /// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
4335 /// v4i16:Extracted = [k0 k1 k2 k3 ]
4336 static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
4337 EVT VT = N->getValueType(0);
4340 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
4341 if (VT.is64BitVector()) {
4342 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
4343 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
4344 DAG.getIntPtrConstant(0));
4346 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
4347 BitCounts, DAG.getIntPtrConstant(0));
4348 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
4352 /// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
4353 /// bit-count for each 32-bit element from the operand. The idea here is
4354 /// to split the vector into 16-bit elements, leverage the 16-bit count
4355 /// routine, and then combine the results.
4357 /// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
4358 /// input = [v0 v1 ] (vi: 32-bit elements)
4359 /// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
4360 /// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
4361 /// vrev: N0 = [k1 k0 k3 k2 ]
4363 /// N1 =+[k1 k0 k3 k2 ]
4365 /// N2 =+[k1 k3 k0 k2 ]
4367 /// Extended =+[k1 k3 k0 k2 ]
4369 /// Extracted=+[k1 k3 ]
4371 static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
4372 EVT VT = N->getValueType(0);
4375 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4377 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
4378 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
4379 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4380 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
4381 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
4383 if (VT.is64BitVector()) {
4384 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
4385 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
4386 DAG.getIntPtrConstant(0));
4388 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
4389 DAG.getIntPtrConstant(0));
4390 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
4394 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
4395 const ARMSubtarget *ST) {
4396 EVT VT = N->getValueType(0);
4398 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
4399 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
4400 VT == MVT::v4i16 || VT == MVT::v8i16) &&
4401 "Unexpected type for custom ctpop lowering");
4403 if (VT.getVectorElementType() == MVT::i32)
4404 return lowerCTPOP32BitElements(N, DAG);
4406 return lowerCTPOP16BitElements(N, DAG);
4409 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
4410 const ARMSubtarget *ST) {
4411 EVT VT = N->getValueType(0);
4417 // Lower vector shifts on NEON to use VSHL.
4418 assert(ST->hasNEON() && "unexpected vector shift");
4420 // Left shifts translate directly to the vshiftu intrinsic.
4421 if (N->getOpcode() == ISD::SHL)
4422 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4423 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
4424 N->getOperand(0), N->getOperand(1));
4426 assert((N->getOpcode() == ISD::SRA ||
4427 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
4429 // NEON uses the same intrinsics for both left and right shifts. For
4430 // right shifts, the shift amounts are negative, so negate the vector of
4432 EVT ShiftVT = N->getOperand(1).getValueType();
4433 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
4434 getZeroVector(ShiftVT, DAG, dl),
4436 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
4437 Intrinsic::arm_neon_vshifts :
4438 Intrinsic::arm_neon_vshiftu);
4439 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4440 DAG.getConstant(vshiftInt, MVT::i32),
4441 N->getOperand(0), NegatedCount);
4444 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
4445 const ARMSubtarget *ST) {
4446 EVT VT = N->getValueType(0);
4449 // We can get here for a node like i32 = ISD::SHL i32, i64
4453 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
4454 "Unknown shift to lower!");
4456 // We only lower SRA, SRL of 1 here, all others use generic lowering.
4457 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
4458 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
4461 // If we are in thumb mode, we don't have RRX.
4462 if (ST->isThumb1Only()) return SDValue();
4464 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
4465 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4466 DAG.getConstant(0, MVT::i32));
4467 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4468 DAG.getConstant(1, MVT::i32));
4470 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
4471 // captures the result into a carry flag.
4472 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
4473 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
4475 // The low part is an ARMISD::RRX operand, which shifts the carry in.
4476 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4478 // Merge the pieces into a single i64 value.
4479 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4482 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4483 SDValue TmpOp0, TmpOp1;
4484 bool Invert = false;
4488 SDValue Op0 = Op.getOperand(0);
4489 SDValue Op1 = Op.getOperand(1);
4490 SDValue CC = Op.getOperand(2);
4491 EVT VT = Op.getValueType();
4492 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4495 if (Op1.getValueType().isFloatingPoint()) {
4496 switch (SetCCOpcode) {
4497 default: llvm_unreachable("Illegal FP comparison");
4499 case ISD::SETNE: Invert = true; // Fallthrough
4501 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4503 case ISD::SETLT: Swap = true; // Fallthrough
4505 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4507 case ISD::SETLE: Swap = true; // Fallthrough
4509 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4510 case ISD::SETUGE: Swap = true; // Fallthrough
4511 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4512 case ISD::SETUGT: Swap = true; // Fallthrough
4513 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
4514 case ISD::SETUEQ: Invert = true; // Fallthrough
4516 // Expand this to (OLT | OGT).
4520 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4521 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
4523 case ISD::SETUO: Invert = true; // Fallthrough
4525 // Expand this to (OLT | OGE).
4529 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4530 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
4534 // Integer comparisons.
4535 switch (SetCCOpcode) {
4536 default: llvm_unreachable("Illegal integer comparison");
4537 case ISD::SETNE: Invert = true;
4538 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4539 case ISD::SETLT: Swap = true;
4540 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4541 case ISD::SETLE: Swap = true;
4542 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4543 case ISD::SETULT: Swap = true;
4544 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
4545 case ISD::SETULE: Swap = true;
4546 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
4549 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
4550 if (Opc == ARMISD::VCEQ) {
4553 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4555 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
4558 // Ignore bitconvert.
4559 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
4560 AndOp = AndOp.getOperand(0);
4562 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4564 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
4565 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
4572 std::swap(Op0, Op1);
4574 // If one of the operands is a constant vector zero, attempt to fold the
4575 // comparison to a specialized compare-against-zero form.
4577 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4579 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
4580 if (Opc == ARMISD::VCGE)
4581 Opc = ARMISD::VCLEZ;
4582 else if (Opc == ARMISD::VCGT)
4583 Opc = ARMISD::VCLTZ;
4588 if (SingleOp.getNode()) {
4591 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
4593 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
4595 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
4597 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
4599 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
4601 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4604 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4608 Result = DAG.getNOT(dl, Result, VT);
4613 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
4614 /// valid vector constant for a NEON instruction with a "modified immediate"
4615 /// operand (e.g., VMOV). If so, return the encoded value.
4616 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
4617 unsigned SplatBitSize, SelectionDAG &DAG,
4618 EVT &VT, bool is128Bits, NEONModImmType type) {
4619 unsigned OpCmode, Imm;
4621 // SplatBitSize is set to the smallest size that splats the vector, so a
4622 // zero vector will always have SplatBitSize == 8. However, NEON modified
4623 // immediate instructions others than VMOV do not support the 8-bit encoding
4624 // of a zero vector, and the default encoding of zero is supposed to be the
4629 switch (SplatBitSize) {
4631 if (type != VMOVModImm)
4633 // Any 1-byte value is OK. Op=0, Cmode=1110.
4634 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
4637 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
4641 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
4642 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4643 if ((SplatBits & ~0xff) == 0) {
4644 // Value = 0x00nn: Op=x, Cmode=100x.
4649 if ((SplatBits & ~0xff00) == 0) {
4650 // Value = 0xnn00: Op=x, Cmode=101x.
4652 Imm = SplatBits >> 8;
4658 // NEON's 32-bit VMOV supports splat values where:
4659 // * only one byte is nonzero, or
4660 // * the least significant byte is 0xff and the second byte is nonzero, or
4661 // * the least significant 2 bytes are 0xff and the third is nonzero.
4662 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
4663 if ((SplatBits & ~0xff) == 0) {
4664 // Value = 0x000000nn: Op=x, Cmode=000x.
4669 if ((SplatBits & ~0xff00) == 0) {
4670 // Value = 0x0000nn00: Op=x, Cmode=001x.
4672 Imm = SplatBits >> 8;
4675 if ((SplatBits & ~0xff0000) == 0) {
4676 // Value = 0x00nn0000: Op=x, Cmode=010x.
4678 Imm = SplatBits >> 16;
4681 if ((SplatBits & ~0xff000000) == 0) {
4682 // Value = 0xnn000000: Op=x, Cmode=011x.
4684 Imm = SplatBits >> 24;
4688 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
4689 if (type == OtherModImm) return SDValue();
4691 if ((SplatBits & ~0xffff) == 0 &&
4692 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
4693 // Value = 0x0000nnff: Op=x, Cmode=1100.
4695 Imm = SplatBits >> 8;
4699 if ((SplatBits & ~0xffffff) == 0 &&
4700 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
4701 // Value = 0x00nnffff: Op=x, Cmode=1101.
4703 Imm = SplatBits >> 16;
4707 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
4708 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
4709 // VMOV.I32. A (very) minor optimization would be to replicate the value
4710 // and fall through here to test for a valid 64-bit splat. But, then the
4711 // caller would also need to check and handle the change in size.
4715 if (type != VMOVModImm)
4717 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
4718 uint64_t BitMask = 0xff;
4720 unsigned ImmMask = 1;
4722 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
4723 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
4726 } else if ((SplatBits & BitMask) != 0) {
4733 if (DAG.getTargetLoweringInfo().isBigEndian())
4734 // swap higher and lower 32 bit word
4735 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
4737 // Op=1, Cmode=1110.
4739 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
4744 llvm_unreachable("unexpected size for isNEONModifiedImm");
4747 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4748 return DAG.getTargetConstant(EncodedVal, MVT::i32);
4751 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
4752 const ARMSubtarget *ST) const {
4756 bool IsDouble = Op.getValueType() == MVT::f64;
4757 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
4759 // Use the default (constant pool) lowering for double constants when we have
4761 if (IsDouble && Subtarget->isFPOnlySP())
4764 // Try splatting with a VMOV.f32...
4765 APFloat FPVal = CFP->getValueAPF();
4766 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
4769 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
4770 // We have code in place to select a valid ConstantFP already, no need to
4775 // It's a float and we are trying to use NEON operations where
4776 // possible. Lower it to a splat followed by an extract.
4778 SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32);
4779 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4781 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4782 DAG.getConstant(0, MVT::i32));
4785 // The rest of our options are NEON only, make sure that's allowed before
4787 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
4791 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
4793 // It wouldn't really be worth bothering for doubles except for one very
4794 // important value, which does happen to match: 0.0. So make sure we don't do
4796 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
4799 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
4800 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4802 if (NewVal != SDValue()) {
4804 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
4807 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4809 // It's a float: cast and extract a vector element.
4810 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4812 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4813 DAG.getConstant(0, MVT::i32));
4816 // Finally, try a VMVN.i32
4817 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4819 if (NewVal != SDValue()) {
4821 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
4824 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4826 // It's a float: cast and extract a vector element.
4827 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4829 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4830 DAG.getConstant(0, MVT::i32));
4836 // check if an VEXT instruction can handle the shuffle mask when the
4837 // vector sources of the shuffle are the same.
4838 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4839 unsigned NumElts = VT.getVectorNumElements();
4841 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4847 // If this is a VEXT shuffle, the immediate value is the index of the first
4848 // element. The other shuffle indices must be the successive elements after
4850 unsigned ExpectedElt = Imm;
4851 for (unsigned i = 1; i < NumElts; ++i) {
4852 // Increment the expected index. If it wraps around, just follow it
4853 // back to index zero and keep going.
4855 if (ExpectedElt == NumElts)
4858 if (M[i] < 0) continue; // ignore UNDEF indices
4859 if (ExpectedElt != static_cast<unsigned>(M[i]))
4867 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
4868 bool &ReverseVEXT, unsigned &Imm) {
4869 unsigned NumElts = VT.getVectorNumElements();
4870 ReverseVEXT = false;
4872 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4878 // If this is a VEXT shuffle, the immediate value is the index of the first
4879 // element. The other shuffle indices must be the successive elements after
4881 unsigned ExpectedElt = Imm;
4882 for (unsigned i = 1; i < NumElts; ++i) {
4883 // Increment the expected index. If it wraps around, it may still be
4884 // a VEXT but the source vectors must be swapped.
4886 if (ExpectedElt == NumElts * 2) {
4891 if (M[i] < 0) continue; // ignore UNDEF indices
4892 if (ExpectedElt != static_cast<unsigned>(M[i]))
4896 // Adjust the index value if the source operands will be swapped.
4903 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
4904 /// instruction with the specified blocksize. (The order of the elements
4905 /// within each block of the vector is reversed.)
4906 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4907 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
4908 "Only possible block sizes for VREV are: 16, 32, 64");
4910 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4914 unsigned NumElts = VT.getVectorNumElements();
4915 unsigned BlockElts = M[0] + 1;
4916 // If the first shuffle index is UNDEF, be optimistic.
4918 BlockElts = BlockSize / EltSz;
4920 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4923 for (unsigned i = 0; i < NumElts; ++i) {
4924 if (M[i] < 0) continue; // ignore UNDEF indices
4925 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
4932 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
4933 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
4934 // range, then 0 is placed into the resulting vector. So pretty much any mask
4935 // of 8 elements can work here.
4936 return VT == MVT::v8i8 && M.size() == 8;
4939 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4940 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4944 unsigned NumElts = VT.getVectorNumElements();
4945 WhichResult = (M[0] == 0 ? 0 : 1);
4946 for (unsigned i = 0; i < NumElts; i += 2) {
4947 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4948 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
4954 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
4955 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4956 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4957 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4958 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4962 unsigned NumElts = VT.getVectorNumElements();
4963 WhichResult = (M[0] == 0 ? 0 : 1);
4964 for (unsigned i = 0; i < NumElts; i += 2) {
4965 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4966 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
4972 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4973 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4977 unsigned NumElts = VT.getVectorNumElements();
4978 WhichResult = (M[0] == 0 ? 0 : 1);
4979 for (unsigned i = 0; i != NumElts; ++i) {
4980 if (M[i] < 0) continue; // ignore UNDEF indices
4981 if ((unsigned) M[i] != 2 * i + WhichResult)
4985 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4986 if (VT.is64BitVector() && EltSz == 32)
4992 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
4993 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4994 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4995 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4996 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5000 unsigned Half = VT.getVectorNumElements() / 2;
5001 WhichResult = (M[0] == 0 ? 0 : 1);
5002 for (unsigned j = 0; j != 2; ++j) {
5003 unsigned Idx = WhichResult;
5004 for (unsigned i = 0; i != Half; ++i) {
5005 int MIdx = M[i + j * Half];
5006 if (MIdx >= 0 && (unsigned) MIdx != Idx)
5012 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5013 if (VT.is64BitVector() && EltSz == 32)
5019 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5020 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5024 unsigned NumElts = VT.getVectorNumElements();
5025 WhichResult = (M[0] == 0 ? 0 : 1);
5026 unsigned Idx = WhichResult * NumElts / 2;
5027 for (unsigned i = 0; i != NumElts; i += 2) {
5028 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
5029 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
5034 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5035 if (VT.is64BitVector() && EltSz == 32)
5041 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
5042 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5043 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5044 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
5045 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5049 unsigned NumElts = VT.getVectorNumElements();
5050 WhichResult = (M[0] == 0 ? 0 : 1);
5051 unsigned Idx = WhichResult * NumElts / 2;
5052 for (unsigned i = 0; i != NumElts; i += 2) {
5053 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
5054 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
5059 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5060 if (VT.is64BitVector() && EltSz == 32)
5066 /// \return true if this is a reverse operation on an vector.
5067 static bool isReverseMask(ArrayRef<int> M, EVT VT) {
5068 unsigned NumElts = VT.getVectorNumElements();
5069 // Make sure the mask has the right size.
5070 if (NumElts != M.size())
5073 // Look for <15, ..., 3, -1, 1, 0>.
5074 for (unsigned i = 0; i != NumElts; ++i)
5075 if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
5081 // If N is an integer constant that can be moved into a register in one
5082 // instruction, return an SDValue of such a constant (will become a MOV
5083 // instruction). Otherwise return null.
5084 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
5085 const ARMSubtarget *ST, SDLoc dl) {
5087 if (!isa<ConstantSDNode>(N))
5089 Val = cast<ConstantSDNode>(N)->getZExtValue();
5091 if (ST->isThumb1Only()) {
5092 if (Val <= 255 || ~Val <= 255)
5093 return DAG.getConstant(Val, MVT::i32);
5095 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
5096 return DAG.getConstant(Val, MVT::i32);
5101 // If this is a case we can't handle, return null and let the default
5102 // expansion code take care of it.
5103 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
5104 const ARMSubtarget *ST) const {
5105 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5107 EVT VT = Op.getValueType();
5109 APInt SplatBits, SplatUndef;
5110 unsigned SplatBitSize;
5112 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5113 if (SplatBitSize <= 64) {
5114 // Check if an immediate VMOV works.
5116 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5117 SplatUndef.getZExtValue(), SplatBitSize,
5118 DAG, VmovVT, VT.is128BitVector(),
5120 if (Val.getNode()) {
5121 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
5122 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5125 // Try an immediate VMVN.
5126 uint64_t NegatedImm = (~SplatBits).getZExtValue();
5127 Val = isNEONModifiedImm(NegatedImm,
5128 SplatUndef.getZExtValue(), SplatBitSize,
5129 DAG, VmovVT, VT.is128BitVector(),
5131 if (Val.getNode()) {
5132 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
5133 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5136 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
5137 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
5138 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
5140 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
5141 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
5147 // Scan through the operands to see if only one value is used.
5149 // As an optimisation, even if more than one value is used it may be more
5150 // profitable to splat with one value then change some lanes.
5152 // Heuristically we decide to do this if the vector has a "dominant" value,
5153 // defined as splatted to more than half of the lanes.
5154 unsigned NumElts = VT.getVectorNumElements();
5155 bool isOnlyLowElement = true;
5156 bool usesOnlyOneValue = true;
5157 bool hasDominantValue = false;
5158 bool isConstant = true;
5160 // Map of the number of times a particular SDValue appears in the
5162 DenseMap<SDValue, unsigned> ValueCounts;
5164 for (unsigned i = 0; i < NumElts; ++i) {
5165 SDValue V = Op.getOperand(i);
5166 if (V.getOpcode() == ISD::UNDEF)
5169 isOnlyLowElement = false;
5170 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5173 ValueCounts.insert(std::make_pair(V, 0));
5174 unsigned &Count = ValueCounts[V];
5176 // Is this value dominant? (takes up more than half of the lanes)
5177 if (++Count > (NumElts / 2)) {
5178 hasDominantValue = true;
5182 if (ValueCounts.size() != 1)
5183 usesOnlyOneValue = false;
5184 if (!Value.getNode() && ValueCounts.size() > 0)
5185 Value = ValueCounts.begin()->first;
5187 if (ValueCounts.size() == 0)
5188 return DAG.getUNDEF(VT);
5190 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
5191 // Keep going if we are hitting this case.
5192 if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
5193 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5195 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5197 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
5198 // i32 and try again.
5199 if (hasDominantValue && EltSize <= 32) {
5203 // If we are VDUPing a value that comes directly from a vector, that will
5204 // cause an unnecessary move to and from a GPR, where instead we could
5205 // just use VDUPLANE. We can only do this if the lane being extracted
5206 // is at a constant index, as the VDUP from lane instructions only have
5207 // constant-index forms.
5208 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5209 isa<ConstantSDNode>(Value->getOperand(1))) {
5210 // We need to create a new undef vector to use for the VDUPLANE if the
5211 // size of the vector from which we get the value is different than the
5212 // size of the vector that we need to create. We will insert the element
5213 // such that the register coalescer will remove unnecessary copies.
5214 if (VT != Value->getOperand(0).getValueType()) {
5215 ConstantSDNode *constIndex;
5216 constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
5217 assert(constIndex && "The index is not a constant!");
5218 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
5219 VT.getVectorNumElements();
5220 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5221 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
5222 Value, DAG.getConstant(index, MVT::i32)),
5223 DAG.getConstant(index, MVT::i32));
5225 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5226 Value->getOperand(0), Value->getOperand(1));
5228 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
5230 if (!usesOnlyOneValue) {
5231 // The dominant value was splatted as 'N', but we now have to insert
5232 // all differing elements.
5233 for (unsigned I = 0; I < NumElts; ++I) {
5234 if (Op.getOperand(I) == Value)
5236 SmallVector<SDValue, 3> Ops;
5238 Ops.push_back(Op.getOperand(I));
5239 Ops.push_back(DAG.getConstant(I, MVT::i32));
5240 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
5245 if (VT.getVectorElementType().isFloatingPoint()) {
5246 SmallVector<SDValue, 8> Ops;
5247 for (unsigned i = 0; i < NumElts; ++i)
5248 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
5250 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
5251 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5252 Val = LowerBUILD_VECTOR(Val, DAG, ST);
5254 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5256 if (usesOnlyOneValue) {
5257 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
5258 if (isConstant && Val.getNode())
5259 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
5263 // If all elements are constants and the case above didn't get hit, fall back
5264 // to the default expansion, which will generate a load from the constant
5269 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5271 SDValue shuffle = ReconstructShuffle(Op, DAG);
5272 if (shuffle != SDValue())
5276 // Vectors with 32- or 64-bit elements can be built by directly assigning
5277 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
5278 // will be legalized.
5279 if (EltSize >= 32) {
5280 // Do the expansion with floating-point types, since that is what the VFP
5281 // registers are defined to use, and since i64 is not legal.
5282 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5283 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5284 SmallVector<SDValue, 8> Ops;
5285 for (unsigned i = 0; i < NumElts; ++i)
5286 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
5287 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5288 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5291 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5292 // know the default expansion would otherwise fall back on something even
5293 // worse. For a vector with one or two non-undef values, that's
5294 // scalar_to_vector for the elements followed by a shuffle (provided the
5295 // shuffle is valid for the target) and materialization element by element
5296 // on the stack followed by a load for everything else.
5297 if (!isConstant && !usesOnlyOneValue) {
5298 SDValue Vec = DAG.getUNDEF(VT);
5299 for (unsigned i = 0 ; i < NumElts; ++i) {
5300 SDValue V = Op.getOperand(i);
5301 if (V.getOpcode() == ISD::UNDEF)
5303 SDValue LaneIdx = DAG.getConstant(i, MVT::i32);
5304 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5312 // Gather data to see if the operation can be modelled as a
5313 // shuffle in combination with VEXTs.
5314 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
5315 SelectionDAG &DAG) const {
5317 EVT VT = Op.getValueType();
5318 unsigned NumElts = VT.getVectorNumElements();
5320 SmallVector<SDValue, 2> SourceVecs;
5321 SmallVector<unsigned, 2> MinElts;
5322 SmallVector<unsigned, 2> MaxElts;
5324 for (unsigned i = 0; i < NumElts; ++i) {
5325 SDValue V = Op.getOperand(i);
5326 if (V.getOpcode() == ISD::UNDEF)
5328 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
5329 // A shuffle can only come from building a vector from various
5330 // elements of other vectors.
5332 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
5333 VT.getVectorElementType()) {
5334 // This code doesn't know how to handle shuffles where the vector
5335 // element types do not match (this happens because type legalization
5336 // promotes the return type of EXTRACT_VECTOR_ELT).
5337 // FIXME: It might be appropriate to extend this code to handle
5338 // mismatched types.
5342 // Record this extraction against the appropriate vector if possible...
5343 SDValue SourceVec = V.getOperand(0);
5344 // If the element number isn't a constant, we can't effectively
5345 // analyze what's going on.
5346 if (!isa<ConstantSDNode>(V.getOperand(1)))
5348 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
5349 bool FoundSource = false;
5350 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
5351 if (SourceVecs[j] == SourceVec) {
5352 if (MinElts[j] > EltNo)
5354 if (MaxElts[j] < EltNo)
5361 // Or record a new source if not...
5363 SourceVecs.push_back(SourceVec);
5364 MinElts.push_back(EltNo);
5365 MaxElts.push_back(EltNo);
5369 // Currently only do something sane when at most two source vectors
5371 if (SourceVecs.size() > 2)
5374 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
5375 int VEXTOffsets[2] = {0, 0};
5377 // This loop extracts the usage patterns of the source vectors
5378 // and prepares appropriate SDValues for a shuffle if possible.
5379 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
5380 if (SourceVecs[i].getValueType() == VT) {
5381 // No VEXT necessary
5382 ShuffleSrcs[i] = SourceVecs[i];
5385 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
5386 // It probably isn't worth padding out a smaller vector just to
5387 // break it down again in a shuffle.
5391 // Since only 64-bit and 128-bit vectors are legal on ARM and
5392 // we've eliminated the other cases...
5393 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
5394 "unexpected vector sizes in ReconstructShuffle");
5396 if (MaxElts[i] - MinElts[i] >= NumElts) {
5397 // Span too large for a VEXT to cope
5401 if (MinElts[i] >= NumElts) {
5402 // The extraction can just take the second half
5403 VEXTOffsets[i] = NumElts;
5404 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5406 DAG.getIntPtrConstant(NumElts));
5407 } else if (MaxElts[i] < NumElts) {
5408 // The extraction can just take the first half
5410 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5412 DAG.getIntPtrConstant(0));
5414 // An actual VEXT is needed
5415 VEXTOffsets[i] = MinElts[i];
5416 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5418 DAG.getIntPtrConstant(0));
5419 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5421 DAG.getIntPtrConstant(NumElts));
5422 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
5423 DAG.getConstant(VEXTOffsets[i], MVT::i32));
5427 SmallVector<int, 8> Mask;
5429 for (unsigned i = 0; i < NumElts; ++i) {
5430 SDValue Entry = Op.getOperand(i);
5431 if (Entry.getOpcode() == ISD::UNDEF) {
5436 SDValue ExtractVec = Entry.getOperand(0);
5437 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
5438 .getOperand(1))->getSExtValue();
5439 if (ExtractVec == SourceVecs[0]) {
5440 Mask.push_back(ExtractElt - VEXTOffsets[0]);
5442 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
5446 // Final check before we try to produce nonsense...
5447 if (isShuffleMaskLegal(Mask, VT))
5448 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
5454 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5455 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5456 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5457 /// are assumed to be legal.
5459 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5461 if (VT.getVectorNumElements() == 4 &&
5462 (VT.is128BitVector() || VT.is64BitVector())) {
5463 unsigned PFIndexes[4];
5464 for (unsigned i = 0; i != 4; ++i) {
5468 PFIndexes[i] = M[i];
5471 // Compute the index in the perfect shuffle table.
5472 unsigned PFTableIndex =
5473 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5474 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5475 unsigned Cost = (PFEntry >> 30);
5482 unsigned Imm, WhichResult;
5484 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5485 return (EltSize >= 32 ||
5486 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
5487 isVREVMask(M, VT, 64) ||
5488 isVREVMask(M, VT, 32) ||
5489 isVREVMask(M, VT, 16) ||
5490 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
5491 isVTBLMask(M, VT) ||
5492 isVTRNMask(M, VT, WhichResult) ||
5493 isVUZPMask(M, VT, WhichResult) ||
5494 isVZIPMask(M, VT, WhichResult) ||
5495 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
5496 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
5497 isVZIP_v_undef_Mask(M, VT, WhichResult) ||
5498 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
5501 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5502 /// the specified operations to build the shuffle.
5503 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5504 SDValue RHS, SelectionDAG &DAG,
5506 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5507 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5508 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5511 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5520 OP_VUZPL, // VUZP, left result
5521 OP_VUZPR, // VUZP, right result
5522 OP_VZIPL, // VZIP, left result
5523 OP_VZIPR, // VZIP, right result
5524 OP_VTRNL, // VTRN, left result
5525 OP_VTRNR // VTRN, right result
5528 if (OpNum == OP_COPY) {
5529 if (LHSID == (1*9+2)*9+3) return LHS;
5530 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5534 SDValue OpLHS, OpRHS;
5535 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5536 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5537 EVT VT = OpLHS.getValueType();
5540 default: llvm_unreachable("Unknown shuffle opcode!");
5542 // VREV divides the vector in half and swaps within the half.
5543 if (VT.getVectorElementType() == MVT::i32 ||
5544 VT.getVectorElementType() == MVT::f32)
5545 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
5546 // vrev <4 x i16> -> VREV32
5547 if (VT.getVectorElementType() == MVT::i16)
5548 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
5549 // vrev <4 x i8> -> VREV16
5550 assert(VT.getVectorElementType() == MVT::i8);
5551 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
5556 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5557 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
5561 return DAG.getNode(ARMISD::VEXT, dl, VT,
5563 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
5566 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5567 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
5570 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5571 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
5574 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5575 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
5579 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
5580 ArrayRef<int> ShuffleMask,
5581 SelectionDAG &DAG) {
5582 // Check to see if we can use the VTBL instruction.
5583 SDValue V1 = Op.getOperand(0);
5584 SDValue V2 = Op.getOperand(1);
5587 SmallVector<SDValue, 8> VTBLMask;
5588 for (ArrayRef<int>::iterator
5589 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
5590 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
5592 if (V2.getNode()->getOpcode() == ISD::UNDEF)
5593 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
5594 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5596 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
5597 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5600 static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
5601 SelectionDAG &DAG) {
5603 SDValue OpLHS = Op.getOperand(0);
5604 EVT VT = OpLHS.getValueType();
5606 assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
5607 "Expect an v8i16/v16i8 type");
5608 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
5609 // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
5610 // extract the first 8 bytes into the top double word and the last 8 bytes
5611 // into the bottom double word. The v8i16 case is similar.
5612 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
5613 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
5614 DAG.getConstant(ExtractNum, MVT::i32));
5617 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
5618 SDValue V1 = Op.getOperand(0);
5619 SDValue V2 = Op.getOperand(1);
5621 EVT VT = Op.getValueType();
5622 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5624 // Convert shuffles that are directly supported on NEON to target-specific
5625 // DAG nodes, instead of keeping them as shuffles and matching them again
5626 // during code selection. This is more efficient and avoids the possibility
5627 // of inconsistencies between legalization and selection.
5628 // FIXME: floating-point vectors should be canonicalized to integer vectors
5629 // of the same time so that they get CSEd properly.
5630 ArrayRef<int> ShuffleMask = SVN->getMask();
5632 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5633 if (EltSize <= 32) {
5634 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
5635 int Lane = SVN->getSplatIndex();
5636 // If this is undef splat, generate it via "just" vdup, if possible.
5637 if (Lane == -1) Lane = 0;
5639 // Test if V1 is a SCALAR_TO_VECTOR.
5640 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5641 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5643 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
5644 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
5646 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5647 !isa<ConstantSDNode>(V1.getOperand(0))) {
5648 bool IsScalarToVector = true;
5649 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
5650 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
5651 IsScalarToVector = false;
5654 if (IsScalarToVector)
5655 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5657 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
5658 DAG.getConstant(Lane, MVT::i32));
5663 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
5666 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
5667 DAG.getConstant(Imm, MVT::i32));
5670 if (isVREVMask(ShuffleMask, VT, 64))
5671 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
5672 if (isVREVMask(ShuffleMask, VT, 32))
5673 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
5674 if (isVREVMask(ShuffleMask, VT, 16))
5675 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
5677 if (V2->getOpcode() == ISD::UNDEF &&
5678 isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
5679 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
5680 DAG.getConstant(Imm, MVT::i32));
5683 // Check for Neon shuffles that modify both input vectors in place.
5684 // If both results are used, i.e., if there are two shuffles with the same
5685 // source operands and with masks corresponding to both results of one of
5686 // these operations, DAG memoization will ensure that a single node is
5687 // used for both shuffles.
5688 unsigned WhichResult;
5689 if (isVTRNMask(ShuffleMask, VT, WhichResult))
5690 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5691 V1, V2).getValue(WhichResult);
5692 if (isVUZPMask(ShuffleMask, VT, WhichResult))
5693 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5694 V1, V2).getValue(WhichResult);
5695 if (isVZIPMask(ShuffleMask, VT, WhichResult))
5696 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5697 V1, V2).getValue(WhichResult);
5699 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
5700 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5701 V1, V1).getValue(WhichResult);
5702 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5703 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5704 V1, V1).getValue(WhichResult);
5705 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5706 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5707 V1, V1).getValue(WhichResult);
5710 // If the shuffle is not directly supported and it has 4 elements, use
5711 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5712 unsigned NumElts = VT.getVectorNumElements();
5714 unsigned PFIndexes[4];
5715 for (unsigned i = 0; i != 4; ++i) {
5716 if (ShuffleMask[i] < 0)
5719 PFIndexes[i] = ShuffleMask[i];
5722 // Compute the index in the perfect shuffle table.
5723 unsigned PFTableIndex =
5724 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5725 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5726 unsigned Cost = (PFEntry >> 30);
5729 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5732 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
5733 if (EltSize >= 32) {
5734 // Do the expansion with floating-point types, since that is what the VFP
5735 // registers are defined to use, and since i64 is not legal.
5736 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5737 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5738 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
5739 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
5740 SmallVector<SDValue, 8> Ops;
5741 for (unsigned i = 0; i < NumElts; ++i) {
5742 if (ShuffleMask[i] < 0)
5743 Ops.push_back(DAG.getUNDEF(EltVT));
5745 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
5746 ShuffleMask[i] < (int)NumElts ? V1 : V2,
5747 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
5750 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5751 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5754 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
5755 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
5757 if (VT == MVT::v8i8) {
5758 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
5759 if (NewOp.getNode())
5766 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5767 // INSERT_VECTOR_ELT is legal only for immediate indexes.
5768 SDValue Lane = Op.getOperand(2);
5769 if (!isa<ConstantSDNode>(Lane))
5775 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5776 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
5777 SDValue Lane = Op.getOperand(1);
5778 if (!isa<ConstantSDNode>(Lane))
5781 SDValue Vec = Op.getOperand(0);
5782 if (Op.getValueType() == MVT::i32 &&
5783 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
5785 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
5791 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5792 // The only time a CONCAT_VECTORS operation can have legal types is when
5793 // two 64-bit vectors are concatenated to a 128-bit vector.
5794 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
5795 "unexpected CONCAT_VECTORS");
5797 SDValue Val = DAG.getUNDEF(MVT::v2f64);
5798 SDValue Op0 = Op.getOperand(0);
5799 SDValue Op1 = Op.getOperand(1);
5800 if (Op0.getOpcode() != ISD::UNDEF)
5801 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5802 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
5803 DAG.getIntPtrConstant(0));
5804 if (Op1.getOpcode() != ISD::UNDEF)
5805 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5806 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
5807 DAG.getIntPtrConstant(1));
5808 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
5811 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
5812 /// element has been zero/sign-extended, depending on the isSigned parameter,
5813 /// from an integer type half its size.
5814 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
5816 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
5817 EVT VT = N->getValueType(0);
5818 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
5819 SDNode *BVN = N->getOperand(0).getNode();
5820 if (BVN->getValueType(0) != MVT::v4i32 ||
5821 BVN->getOpcode() != ISD::BUILD_VECTOR)
5823 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5824 unsigned HiElt = 1 - LoElt;
5825 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
5826 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
5827 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
5828 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
5829 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
5832 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
5833 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
5836 if (Hi0->isNullValue() && Hi1->isNullValue())
5842 if (N->getOpcode() != ISD::BUILD_VECTOR)
5845 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5846 SDNode *Elt = N->getOperand(i).getNode();
5847 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
5848 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5849 unsigned HalfSize = EltSize / 2;
5851 if (!isIntN(HalfSize, C->getSExtValue()))
5854 if (!isUIntN(HalfSize, C->getZExtValue()))
5865 /// isSignExtended - Check if a node is a vector value that is sign-extended
5866 /// or a constant BUILD_VECTOR with sign-extended elements.
5867 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
5868 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
5870 if (isExtendedBUILD_VECTOR(N, DAG, true))
5875 /// isZeroExtended - Check if a node is a vector value that is zero-extended
5876 /// or a constant BUILD_VECTOR with zero-extended elements.
5877 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
5878 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
5880 if (isExtendedBUILD_VECTOR(N, DAG, false))
5885 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
5886 if (OrigVT.getSizeInBits() >= 64)
5889 assert(OrigVT.isSimple() && "Expecting a simple value type");
5891 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
5892 switch (OrigSimpleTy) {
5893 default: llvm_unreachable("Unexpected Vector Type");
5902 /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
5903 /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
5904 /// We insert the required extension here to get the vector to fill a D register.
5905 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
5908 unsigned ExtOpcode) {
5909 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
5910 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
5911 // 64-bits we need to insert a new extension so that it will be 64-bits.
5912 assert(ExtTy.is128BitVector() && "Unexpected extension size");
5913 if (OrigTy.getSizeInBits() >= 64)
5916 // Must extend size to at least 64 bits to be used as an operand for VMULL.
5917 EVT NewVT = getExtensionTo64Bits(OrigTy);
5919 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
5922 /// SkipLoadExtensionForVMULL - return a load of the original vector size that
5923 /// does not do any sign/zero extension. If the original vector is less
5924 /// than 64 bits, an appropriate extension will be added after the load to
5925 /// reach a total size of 64 bits. We have to add the extension separately
5926 /// because ARM does not have a sign/zero extending load for vectors.
5927 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
5928 EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
5930 // The load already has the right type.
5931 if (ExtendedTy == LD->getMemoryVT())
5932 return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
5933 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
5934 LD->isNonTemporal(), LD->isInvariant(),
5935 LD->getAlignment());
5937 // We need to create a zextload/sextload. We cannot just create a load
5938 // followed by a zext/zext node because LowerMUL is also run during normal
5939 // operation legalization where we can't create illegal types.
5940 return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
5941 LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
5942 LD->getMemoryVT(), LD->isVolatile(), LD->isInvariant(),
5943 LD->isNonTemporal(), LD->getAlignment());
5946 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
5947 /// extending load, or BUILD_VECTOR with extended elements, return the
5948 /// unextended value. The unextended vector should be 64 bits so that it can
5949 /// be used as an operand to a VMULL instruction. If the original vector size
5950 /// before extension is less than 64 bits we add a an extension to resize
5951 /// the vector to 64 bits.
5952 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
5953 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
5954 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
5955 N->getOperand(0)->getValueType(0),
5959 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
5960 return SkipLoadExtensionForVMULL(LD, DAG);
5962 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
5963 // have been legalized as a BITCAST from v4i32.
5964 if (N->getOpcode() == ISD::BITCAST) {
5965 SDNode *BVN = N->getOperand(0).getNode();
5966 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
5967 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
5968 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5969 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
5970 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
5972 // Construct a new BUILD_VECTOR with elements truncated to half the size.
5973 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
5974 EVT VT = N->getValueType(0);
5975 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
5976 unsigned NumElts = VT.getVectorNumElements();
5977 MVT TruncVT = MVT::getIntegerVT(EltSize);
5978 SmallVector<SDValue, 8> Ops;
5979 for (unsigned i = 0; i != NumElts; ++i) {
5980 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
5981 const APInt &CInt = C->getAPIntValue();
5982 // Element types smaller than 32 bits are not legal, so use i32 elements.
5983 // The values are implicitly truncated so sext vs. zext doesn't matter.
5984 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
5986 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
5987 MVT::getVectorVT(TruncVT, NumElts), Ops);
5990 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
5991 unsigned Opcode = N->getOpcode();
5992 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5993 SDNode *N0 = N->getOperand(0).getNode();
5994 SDNode *N1 = N->getOperand(1).getNode();
5995 return N0->hasOneUse() && N1->hasOneUse() &&
5996 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
6001 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
6002 unsigned Opcode = N->getOpcode();
6003 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
6004 SDNode *N0 = N->getOperand(0).getNode();
6005 SDNode *N1 = N->getOperand(1).getNode();
6006 return N0->hasOneUse() && N1->hasOneUse() &&
6007 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
6012 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
6013 // Multiplications are only custom-lowered for 128-bit vectors so that
6014 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
6015 EVT VT = Op.getValueType();
6016 assert(VT.is128BitVector() && VT.isInteger() &&
6017 "unexpected type for custom-lowering ISD::MUL");
6018 SDNode *N0 = Op.getOperand(0).getNode();
6019 SDNode *N1 = Op.getOperand(1).getNode();
6020 unsigned NewOpc = 0;
6022 bool isN0SExt = isSignExtended(N0, DAG);
6023 bool isN1SExt = isSignExtended(N1, DAG);
6024 if (isN0SExt && isN1SExt)
6025 NewOpc = ARMISD::VMULLs;
6027 bool isN0ZExt = isZeroExtended(N0, DAG);
6028 bool isN1ZExt = isZeroExtended(N1, DAG);
6029 if (isN0ZExt && isN1ZExt)
6030 NewOpc = ARMISD::VMULLu;
6031 else if (isN1SExt || isN1ZExt) {
6032 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
6033 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
6034 if (isN1SExt && isAddSubSExt(N0, DAG)) {
6035 NewOpc = ARMISD::VMULLs;
6037 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
6038 NewOpc = ARMISD::VMULLu;
6040 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
6042 NewOpc = ARMISD::VMULLu;
6048 if (VT == MVT::v2i64)
6049 // Fall through to expand this. It is not legal.
6052 // Other vector multiplications are legal.
6057 // Legalize to a VMULL instruction.
6060 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
6062 Op0 = SkipExtensionForVMULL(N0, DAG);
6063 assert(Op0.getValueType().is64BitVector() &&
6064 Op1.getValueType().is64BitVector() &&
6065 "unexpected types for extended operands to VMULL");
6066 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
6069 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
6070 // isel lowering to take advantage of no-stall back to back vmul + vmla.
6077 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
6078 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
6079 EVT Op1VT = Op1.getValueType();
6080 return DAG.getNode(N0->getOpcode(), DL, VT,
6081 DAG.getNode(NewOpc, DL, VT,
6082 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
6083 DAG.getNode(NewOpc, DL, VT,
6084 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
6088 LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) {
6090 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
6091 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
6092 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
6093 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
6094 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
6095 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
6096 // Get reciprocal estimate.
6097 // float4 recip = vrecpeq_f32(yf);
6098 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6099 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
6100 // Because char has a smaller range than uchar, we can actually get away
6101 // without any newton steps. This requires that we use a weird bias
6102 // of 0xb000, however (again, this has been exhaustively tested).
6103 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
6104 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
6105 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
6106 Y = DAG.getConstant(0xb000, MVT::i32);
6107 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
6108 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
6109 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
6110 // Convert back to short.
6111 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
6112 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
6117 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
6119 // Convert to float.
6120 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
6121 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
6122 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
6123 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
6124 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6125 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6127 // Use reciprocal estimate and one refinement step.
6128 // float4 recip = vrecpeq_f32(yf);
6129 // recip *= vrecpsq_f32(yf, recip);
6130 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6131 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
6132 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6133 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
6135 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6136 // Because short has a smaller range than ushort, we can actually get away
6137 // with only a single newton step. This requires that we use a weird bias
6138 // of 89, however (again, this has been exhaustively tested).
6139 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
6140 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6141 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6142 N1 = DAG.getConstant(0x89, MVT::i32);
6143 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6144 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6145 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6146 // Convert back to integer and return.
6147 // return vmovn_s32(vcvt_s32_f32(result));
6148 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6149 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6153 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
6154 EVT VT = Op.getValueType();
6155 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6156 "unexpected type for custom-lowering ISD::SDIV");
6159 SDValue N0 = Op.getOperand(0);
6160 SDValue N1 = Op.getOperand(1);
6163 if (VT == MVT::v8i8) {
6164 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
6165 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
6167 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6168 DAG.getIntPtrConstant(4));
6169 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6170 DAG.getIntPtrConstant(4));
6171 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6172 DAG.getIntPtrConstant(0));
6173 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6174 DAG.getIntPtrConstant(0));
6176 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
6177 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
6179 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6180 N0 = LowerCONCAT_VECTORS(N0, DAG);
6182 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
6185 return LowerSDIV_v4i16(N0, N1, dl, DAG);
6188 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
6189 EVT VT = Op.getValueType();
6190 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6191 "unexpected type for custom-lowering ISD::UDIV");
6194 SDValue N0 = Op.getOperand(0);
6195 SDValue N1 = Op.getOperand(1);
6198 if (VT == MVT::v8i8) {
6199 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
6200 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
6202 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6203 DAG.getIntPtrConstant(4));
6204 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6205 DAG.getIntPtrConstant(4));
6206 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6207 DAG.getIntPtrConstant(0));
6208 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6209 DAG.getIntPtrConstant(0));
6211 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
6212 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
6214 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6215 N0 = LowerCONCAT_VECTORS(N0, DAG);
6217 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
6218 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
6223 // v4i16 sdiv ... Convert to float.
6224 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
6225 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
6226 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
6227 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
6228 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6229 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6231 // Use reciprocal estimate and two refinement steps.
6232 // float4 recip = vrecpeq_f32(yf);
6233 // recip *= vrecpsq_f32(yf, recip);
6234 // recip *= vrecpsq_f32(yf, recip);
6235 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6236 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
6237 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6238 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
6240 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6241 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6242 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
6244 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6245 // Simply multiplying by the reciprocal estimate can leave us a few ulps
6246 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
6247 // and that it will never cause us to return an answer too large).
6248 // float4 result = as_float4(as_int4(xf*recip) + 2);
6249 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6250 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6251 N1 = DAG.getConstant(2, MVT::i32);
6252 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6253 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6254 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6255 // Convert back to integer and return.
6256 // return vmovn_u32(vcvt_s32_f32(result));
6257 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6258 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6262 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
6263 EVT VT = Op.getNode()->getValueType(0);
6264 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
6267 bool ExtraOp = false;
6268 switch (Op.getOpcode()) {
6269 default: llvm_unreachable("Invalid code");
6270 case ISD::ADDC: Opc = ARMISD::ADDC; break;
6271 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
6272 case ISD::SUBC: Opc = ARMISD::SUBC; break;
6273 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
6277 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6279 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6280 Op.getOperand(1), Op.getOperand(2));
6283 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
6284 assert(Subtarget->isTargetDarwin());
6286 // For iOS, we want to call an alternative entry point: __sincos_stret,
6287 // return values are passed via sret.
6289 SDValue Arg = Op.getOperand(0);
6290 EVT ArgVT = Arg.getValueType();
6291 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
6293 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6294 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6296 // Pair of floats / doubles used to pass the result.
6297 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
6299 // Create stack object for sret.
6300 const uint64_t ByteSize = TLI.getDataLayout()->getTypeAllocSize(RetTy);
6301 const unsigned StackAlign = TLI.getDataLayout()->getPrefTypeAlignment(RetTy);
6302 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false);
6303 SDValue SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
6309 Entry.Ty = RetTy->getPointerTo();
6310 Entry.isSExt = false;
6311 Entry.isZExt = false;
6312 Entry.isSRet = true;
6313 Args.push_back(Entry);
6317 Entry.isSExt = false;
6318 Entry.isZExt = false;
6319 Args.push_back(Entry);
6321 const char *LibcallName = (ArgVT == MVT::f64)
6322 ? "__sincos_stret" : "__sincosf_stret";
6323 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
6325 TargetLowering::CallLoweringInfo CLI(DAG);
6326 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
6327 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), Callee,
6329 .setDiscardResult();
6331 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
6333 SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet,
6334 MachinePointerInfo(), false, false, false, 0);
6336 // Address of cos field.
6337 SDValue Add = DAG.getNode(ISD::ADD, dl, getPointerTy(), SRet,
6338 DAG.getIntPtrConstant(ArgVT.getStoreSize()));
6339 SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
6340 MachinePointerInfo(), false, false, false, 0);
6342 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
6343 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
6344 LoadSin.getValue(0), LoadCos.getValue(0));
6347 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
6348 // Monotonic load/store is legal for all targets
6349 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
6352 // Acquire/Release load/store is not legal for targets without a
6353 // dmb or equivalent available.
6357 static void ReplaceREADCYCLECOUNTER(SDNode *N,
6358 SmallVectorImpl<SDValue> &Results,
6360 const ARMSubtarget *Subtarget) {
6362 SDValue Cycles32, OutChain;
6364 if (Subtarget->hasPerfMon()) {
6365 // Under Power Management extensions, the cycle-count is:
6366 // mrc p15, #0, <Rt>, c9, c13, #0
6367 SDValue Ops[] = { N->getOperand(0), // Chain
6368 DAG.getConstant(Intrinsic::arm_mrc, MVT::i32),
6369 DAG.getConstant(15, MVT::i32),
6370 DAG.getConstant(0, MVT::i32),
6371 DAG.getConstant(9, MVT::i32),
6372 DAG.getConstant(13, MVT::i32),
6373 DAG.getConstant(0, MVT::i32)
6376 Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
6377 DAG.getVTList(MVT::i32, MVT::Other), Ops);
6378 OutChain = Cycles32.getValue(1);
6380 // Intrinsic is defined to return 0 on unsupported platforms. Technically
6381 // there are older ARM CPUs that have implementation-specific ways of
6382 // obtaining this information (FIXME!).
6383 Cycles32 = DAG.getConstant(0, MVT::i32);
6384 OutChain = DAG.getEntryNode();
6388 SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
6389 Cycles32, DAG.getConstant(0, MVT::i32));
6390 Results.push_back(Cycles64);
6391 Results.push_back(OutChain);
6394 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6395 switch (Op.getOpcode()) {
6396 default: llvm_unreachable("Don't know how to custom lower this!");
6397 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6398 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6399 case ISD::GlobalAddress:
6400 switch (Subtarget->getTargetTriple().getObjectFormat()) {
6401 default: llvm_unreachable("unknown object format");
6403 return LowerGlobalAddressWindows(Op, DAG);
6405 return LowerGlobalAddressELF(Op, DAG);
6407 return LowerGlobalAddressDarwin(Op, DAG);
6409 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6410 case ISD::SELECT: return LowerSELECT(Op, DAG);
6411 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6412 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
6413 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
6414 case ISD::VASTART: return LowerVASTART(Op, DAG);
6415 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
6416 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
6417 case ISD::SINT_TO_FP:
6418 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6419 case ISD::FP_TO_SINT:
6420 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
6421 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6422 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6423 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6424 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
6425 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
6426 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
6427 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
6429 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
6432 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
6433 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
6434 case ISD::SRL_PARTS:
6435 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
6436 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
6437 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
6438 case ISD::SETCC: return LowerVSETCC(Op, DAG);
6439 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
6440 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
6441 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6442 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6443 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6444 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
6445 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6446 case ISD::MUL: return LowerMUL(Op, DAG);
6447 case ISD::SDIV: return LowerSDIV(Op, DAG);
6448 case ISD::UDIV: return LowerUDIV(Op, DAG);
6452 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
6457 return LowerXALUO(Op, DAG);
6458 case ISD::ATOMIC_LOAD:
6459 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
6460 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
6462 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
6463 case ISD::DYNAMIC_STACKALLOC:
6464 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
6465 return LowerDYNAMIC_STACKALLOC(Op, DAG);
6466 llvm_unreachable("Don't know how to custom lower this!");
6467 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
6468 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
6472 /// ReplaceNodeResults - Replace the results of node with an illegal result
6473 /// type with new values built out of custom code.
6474 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
6475 SmallVectorImpl<SDValue>&Results,
6476 SelectionDAG &DAG) const {
6478 switch (N->getOpcode()) {
6480 llvm_unreachable("Don't know how to custom expand this!");
6482 Res = ExpandBITCAST(N, DAG);
6486 Res = Expand64BitShift(N, DAG, Subtarget);
6488 case ISD::READCYCLECOUNTER:
6489 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
6493 Results.push_back(Res);
6496 //===----------------------------------------------------------------------===//
6497 // ARM Scheduler Hooks
6498 //===----------------------------------------------------------------------===//
6500 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
6501 /// registers the function context.
6502 void ARMTargetLowering::
6503 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
6504 MachineBasicBlock *DispatchBB, int FI) const {
6505 const TargetInstrInfo *TII =
6506 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6507 DebugLoc dl = MI->getDebugLoc();
6508 MachineFunction *MF = MBB->getParent();
6509 MachineRegisterInfo *MRI = &MF->getRegInfo();
6510 MachineConstantPool *MCP = MF->getConstantPool();
6511 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6512 const Function *F = MF->getFunction();
6514 bool isThumb = Subtarget->isThumb();
6515 bool isThumb2 = Subtarget->isThumb2();
6517 unsigned PCLabelId = AFI->createPICLabelUId();
6518 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
6519 ARMConstantPoolValue *CPV =
6520 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
6521 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
6523 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass
6524 : &ARM::GPRRegClass;
6526 // Grab constant pool and fixed stack memory operands.
6527 MachineMemOperand *CPMMO =
6528 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
6529 MachineMemOperand::MOLoad, 4, 4);
6531 MachineMemOperand *FIMMOSt =
6532 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6533 MachineMemOperand::MOStore, 4, 4);
6535 // Load the address of the dispatch MBB into the jump buffer.
6537 // Incoming value: jbuf
6538 // ldr.n r5, LCPI1_1
6541 // str r5, [$jbuf, #+4] ; &jbuf[1]
6542 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6543 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6544 .addConstantPoolIndex(CPI)
6545 .addMemOperand(CPMMO));
6546 // Set the low bit because of thumb mode.
6547 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6549 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6550 .addReg(NewVReg1, RegState::Kill)
6552 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6553 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
6554 .addReg(NewVReg2, RegState::Kill)
6556 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6557 .addReg(NewVReg3, RegState::Kill)
6559 .addImm(36) // &jbuf[1] :: pc
6560 .addMemOperand(FIMMOSt));
6561 } else if (isThumb) {
6562 // Incoming value: jbuf
6563 // ldr.n r1, LCPI1_4
6567 // add r2, $jbuf, #+4 ; &jbuf[1]
6569 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6570 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6571 .addConstantPoolIndex(CPI)
6572 .addMemOperand(CPMMO));
6573 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6574 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
6575 .addReg(NewVReg1, RegState::Kill)
6577 // Set the low bit because of thumb mode.
6578 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6579 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6580 .addReg(ARM::CPSR, RegState::Define)
6582 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6583 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6584 .addReg(ARM::CPSR, RegState::Define)
6585 .addReg(NewVReg2, RegState::Kill)
6586 .addReg(NewVReg3, RegState::Kill));
6587 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6588 BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5)
6590 .addImm(36); // &jbuf[1] :: pc
6591 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6592 .addReg(NewVReg4, RegState::Kill)
6593 .addReg(NewVReg5, RegState::Kill)
6595 .addMemOperand(FIMMOSt));
6597 // Incoming value: jbuf
6600 // str r1, [$jbuf, #+4] ; &jbuf[1]
6601 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6602 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6603 .addConstantPoolIndex(CPI)
6605 .addMemOperand(CPMMO));
6606 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6607 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6608 .addReg(NewVReg1, RegState::Kill)
6609 .addImm(PCLabelId));
6610 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6611 .addReg(NewVReg2, RegState::Kill)
6613 .addImm(36) // &jbuf[1] :: pc
6614 .addMemOperand(FIMMOSt));
6618 MachineBasicBlock *ARMTargetLowering::
6619 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
6620 const TargetInstrInfo *TII =
6621 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6622 DebugLoc dl = MI->getDebugLoc();
6623 MachineFunction *MF = MBB->getParent();
6624 MachineRegisterInfo *MRI = &MF->getRegInfo();
6625 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6626 MachineFrameInfo *MFI = MF->getFrameInfo();
6627 int FI = MFI->getFunctionContextIndex();
6629 const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass
6630 : &ARM::GPRnopcRegClass;
6632 // Get a mapping of the call site numbers to all of the landing pads they're
6634 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
6635 unsigned MaxCSNum = 0;
6636 MachineModuleInfo &MMI = MF->getMMI();
6637 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
6639 if (!BB->isLandingPad()) continue;
6641 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
6643 for (MachineBasicBlock::iterator
6644 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
6645 if (!II->isEHLabel()) continue;
6647 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
6648 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
6650 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
6651 for (SmallVectorImpl<unsigned>::iterator
6652 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
6653 CSI != CSE; ++CSI) {
6654 CallSiteNumToLPad[*CSI].push_back(BB);
6655 MaxCSNum = std::max(MaxCSNum, *CSI);
6661 // Get an ordered list of the machine basic blocks for the jump table.
6662 std::vector<MachineBasicBlock*> LPadList;
6663 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
6664 LPadList.reserve(CallSiteNumToLPad.size());
6665 for (unsigned I = 1; I <= MaxCSNum; ++I) {
6666 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
6667 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6668 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
6669 LPadList.push_back(*II);
6670 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6674 assert(!LPadList.empty() &&
6675 "No landing pad destinations for the dispatch jump table!");
6677 // Create the jump table and associated information.
6678 MachineJumpTableInfo *JTI =
6679 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
6680 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6681 unsigned UId = AFI->createJumpTableUId();
6682 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
6684 // Create the MBBs for the dispatch code.
6686 // Shove the dispatch's address into the return slot in the function context.
6687 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6688 DispatchBB->setIsLandingPad();
6690 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
6691 unsigned trap_opcode;
6692 if (Subtarget->isThumb())
6693 trap_opcode = ARM::tTRAP;
6695 trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
6697 BuildMI(TrapBB, dl, TII->get(trap_opcode));
6698 DispatchBB->addSuccessor(TrapBB);
6700 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6701 DispatchBB->addSuccessor(DispContBB);
6704 MF->insert(MF->end(), DispatchBB);
6705 MF->insert(MF->end(), DispContBB);
6706 MF->insert(MF->end(), TrapBB);
6708 // Insert code into the entry block that creates and registers the function
6710 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
6712 MachineMemOperand *FIMMOLd =
6713 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6714 MachineMemOperand::MOLoad |
6715 MachineMemOperand::MOVolatile, 4, 4);
6717 MachineInstrBuilder MIB;
6718 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6720 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6721 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6723 // Add a register mask with no preserved registers. This results in all
6724 // registers being marked as clobbered.
6725 MIB.addRegMask(RI.getNoPreservedMask());
6727 unsigned NumLPads = LPadList.size();
6728 if (Subtarget->isThumb2()) {
6729 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6730 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6733 .addMemOperand(FIMMOLd));
6735 if (NumLPads < 256) {
6736 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6738 .addImm(LPadList.size()));
6740 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6741 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6742 .addImm(NumLPads & 0xFFFF));
6744 unsigned VReg2 = VReg1;
6745 if ((NumLPads & 0xFFFF0000) != 0) {
6746 VReg2 = MRI->createVirtualRegister(TRC);
6747 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6749 .addImm(NumLPads >> 16));
6752 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6757 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
6762 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6763 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
6764 .addJumpTableIndex(MJTI)
6767 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6770 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
6771 .addReg(NewVReg3, RegState::Kill)
6773 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6775 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
6776 .addReg(NewVReg4, RegState::Kill)
6778 .addJumpTableIndex(MJTI)
6780 } else if (Subtarget->isThumb()) {
6781 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6782 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6785 .addMemOperand(FIMMOLd));
6787 if (NumLPads < 256) {
6788 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6792 MachineConstantPool *ConstantPool = MF->getConstantPool();
6793 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6794 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6796 // MachineConstantPool wants an explicit alignment.
6797 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6799 Align = getDataLayout()->getTypeAllocSize(C->getType());
6800 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6802 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6803 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
6804 .addReg(VReg1, RegState::Define)
6805 .addConstantPoolIndex(Idx));
6806 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
6811 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
6816 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6817 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
6818 .addReg(ARM::CPSR, RegState::Define)
6822 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6823 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
6824 .addJumpTableIndex(MJTI)
6827 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6828 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
6829 .addReg(ARM::CPSR, RegState::Define)
6830 .addReg(NewVReg2, RegState::Kill)
6833 MachineMemOperand *JTMMOLd =
6834 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6835 MachineMemOperand::MOLoad, 4, 4);
6837 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6838 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
6839 .addReg(NewVReg4, RegState::Kill)
6841 .addMemOperand(JTMMOLd));
6843 unsigned NewVReg6 = NewVReg5;
6844 if (RelocM == Reloc::PIC_) {
6845 NewVReg6 = MRI->createVirtualRegister(TRC);
6846 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
6847 .addReg(ARM::CPSR, RegState::Define)
6848 .addReg(NewVReg5, RegState::Kill)
6852 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
6853 .addReg(NewVReg6, RegState::Kill)
6854 .addJumpTableIndex(MJTI)
6857 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6858 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
6861 .addMemOperand(FIMMOLd));
6863 if (NumLPads < 256) {
6864 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
6867 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
6868 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6869 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
6870 .addImm(NumLPads & 0xFFFF));
6872 unsigned VReg2 = VReg1;
6873 if ((NumLPads & 0xFFFF0000) != 0) {
6874 VReg2 = MRI->createVirtualRegister(TRC);
6875 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
6877 .addImm(NumLPads >> 16));
6880 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6884 MachineConstantPool *ConstantPool = MF->getConstantPool();
6885 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6886 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6888 // MachineConstantPool wants an explicit alignment.
6889 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6891 Align = getDataLayout()->getTypeAllocSize(C->getType());
6892 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6894 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6895 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
6896 .addReg(VReg1, RegState::Define)
6897 .addConstantPoolIndex(Idx)
6899 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6901 .addReg(VReg1, RegState::Kill));
6904 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
6909 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6911 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
6913 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6914 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6915 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
6916 .addJumpTableIndex(MJTI)
6919 MachineMemOperand *JTMMOLd =
6920 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6921 MachineMemOperand::MOLoad, 4, 4);
6922 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6924 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
6925 .addReg(NewVReg3, RegState::Kill)
6928 .addMemOperand(JTMMOLd));
6930 if (RelocM == Reloc::PIC_) {
6931 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
6932 .addReg(NewVReg5, RegState::Kill)
6934 .addJumpTableIndex(MJTI)
6937 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
6938 .addReg(NewVReg5, RegState::Kill)
6939 .addJumpTableIndex(MJTI)
6944 // Add the jump table entries as successors to the MBB.
6945 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
6946 for (std::vector<MachineBasicBlock*>::iterator
6947 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
6948 MachineBasicBlock *CurMBB = *I;
6949 if (SeenMBBs.insert(CurMBB).second)
6950 DispContBB->addSuccessor(CurMBB);
6953 // N.B. the order the invoke BBs are processed in doesn't matter here.
6954 const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
6955 SmallVector<MachineBasicBlock*, 64> MBBLPads;
6956 for (MachineBasicBlock *BB : InvokeBBs) {
6958 // Remove the landing pad successor from the invoke block and replace it
6959 // with the new dispatch block.
6960 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
6962 while (!Successors.empty()) {
6963 MachineBasicBlock *SMBB = Successors.pop_back_val();
6964 if (SMBB->isLandingPad()) {
6965 BB->removeSuccessor(SMBB);
6966 MBBLPads.push_back(SMBB);
6970 BB->addSuccessor(DispatchBB);
6972 // Find the invoke call and mark all of the callee-saved registers as
6973 // 'implicit defined' so that they're spilled. This prevents code from
6974 // moving instructions to before the EH block, where they will never be
6976 for (MachineBasicBlock::reverse_iterator
6977 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
6978 if (!II->isCall()) continue;
6980 DenseMap<unsigned, bool> DefRegs;
6981 for (MachineInstr::mop_iterator
6982 OI = II->operands_begin(), OE = II->operands_end();
6984 if (!OI->isReg()) continue;
6985 DefRegs[OI->getReg()] = true;
6988 MachineInstrBuilder MIB(*MF, &*II);
6990 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
6991 unsigned Reg = SavedRegs[i];
6992 if (Subtarget->isThumb2() &&
6993 !ARM::tGPRRegClass.contains(Reg) &&
6994 !ARM::hGPRRegClass.contains(Reg))
6996 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
6998 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
7001 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
7008 // Mark all former landing pads as non-landing pads. The dispatch is the only
7010 for (SmallVectorImpl<MachineBasicBlock*>::iterator
7011 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
7012 (*I)->setIsLandingPad(false);
7014 // The instruction is gone now.
7015 MI->eraseFromParent();
7021 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
7022 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
7023 E = MBB->succ_end(); I != E; ++I)
7026 llvm_unreachable("Expecting a BB with two successors!");
7029 /// Return the load opcode for a given load size. If load size >= 8,
7030 /// neon opcode will be returned.
7031 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
7033 return LdSize == 16 ? ARM::VLD1q32wb_fixed
7034 : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
7036 return LdSize == 4 ? ARM::tLDRi
7037 : LdSize == 2 ? ARM::tLDRHi
7038 : LdSize == 1 ? ARM::tLDRBi : 0;
7040 return LdSize == 4 ? ARM::t2LDR_POST
7041 : LdSize == 2 ? ARM::t2LDRH_POST
7042 : LdSize == 1 ? ARM::t2LDRB_POST : 0;
7043 return LdSize == 4 ? ARM::LDR_POST_IMM
7044 : LdSize == 2 ? ARM::LDRH_POST
7045 : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
7048 /// Return the store opcode for a given store size. If store size >= 8,
7049 /// neon opcode will be returned.
7050 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
7052 return StSize == 16 ? ARM::VST1q32wb_fixed
7053 : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
7055 return StSize == 4 ? ARM::tSTRi
7056 : StSize == 2 ? ARM::tSTRHi
7057 : StSize == 1 ? ARM::tSTRBi : 0;
7059 return StSize == 4 ? ARM::t2STR_POST
7060 : StSize == 2 ? ARM::t2STRH_POST
7061 : StSize == 1 ? ARM::t2STRB_POST : 0;
7062 return StSize == 4 ? ARM::STR_POST_IMM
7063 : StSize == 2 ? ARM::STRH_POST
7064 : StSize == 1 ? ARM::STRB_POST_IMM : 0;
7067 /// Emit a post-increment load operation with given size. The instructions
7068 /// will be added to BB at Pos.
7069 static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos,
7070 const TargetInstrInfo *TII, DebugLoc dl,
7071 unsigned LdSize, unsigned Data, unsigned AddrIn,
7072 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7073 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
7074 assert(LdOpc != 0 && "Should have a load opcode");
7076 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7077 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7079 } else if (IsThumb1) {
7080 // load + update AddrIn
7081 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7082 .addReg(AddrIn).addImm(0));
7083 MachineInstrBuilder MIB =
7084 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7085 MIB = AddDefaultT1CC(MIB);
7086 MIB.addReg(AddrIn).addImm(LdSize);
7087 AddDefaultPred(MIB);
7088 } else if (IsThumb2) {
7089 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7090 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7093 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7094 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7095 .addReg(0).addImm(LdSize));
7099 /// Emit a post-increment store operation with given size. The instructions
7100 /// will be added to BB at Pos.
7101 static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos,
7102 const TargetInstrInfo *TII, DebugLoc dl,
7103 unsigned StSize, unsigned Data, unsigned AddrIn,
7104 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7105 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
7106 assert(StOpc != 0 && "Should have a store opcode");
7108 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7109 .addReg(AddrIn).addImm(0).addReg(Data));
7110 } else if (IsThumb1) {
7111 // store + update AddrIn
7112 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
7113 .addReg(AddrIn).addImm(0));
7114 MachineInstrBuilder MIB =
7115 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7116 MIB = AddDefaultT1CC(MIB);
7117 MIB.addReg(AddrIn).addImm(StSize);
7118 AddDefaultPred(MIB);
7119 } else if (IsThumb2) {
7120 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7121 .addReg(Data).addReg(AddrIn).addImm(StSize));
7123 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7124 .addReg(Data).addReg(AddrIn).addReg(0)
7130 ARMTargetLowering::EmitStructByval(MachineInstr *MI,
7131 MachineBasicBlock *BB) const {
7132 // This pseudo instruction has 3 operands: dst, src, size
7133 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
7134 // Otherwise, we will generate unrolled scalar copies.
7135 const TargetInstrInfo *TII =
7136 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7137 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7138 MachineFunction::iterator It = BB;
7141 unsigned dest = MI->getOperand(0).getReg();
7142 unsigned src = MI->getOperand(1).getReg();
7143 unsigned SizeVal = MI->getOperand(2).getImm();
7144 unsigned Align = MI->getOperand(3).getImm();
7145 DebugLoc dl = MI->getDebugLoc();
7147 MachineFunction *MF = BB->getParent();
7148 MachineRegisterInfo &MRI = MF->getRegInfo();
7149 unsigned UnitSize = 0;
7150 const TargetRegisterClass *TRC = nullptr;
7151 const TargetRegisterClass *VecTRC = nullptr;
7153 bool IsThumb1 = Subtarget->isThumb1Only();
7154 bool IsThumb2 = Subtarget->isThumb2();
7158 } else if (Align & 2) {
7161 // Check whether we can use NEON instructions.
7162 if (!MF->getFunction()->getAttributes().
7163 hasAttribute(AttributeSet::FunctionIndex,
7164 Attribute::NoImplicitFloat) &&
7165 Subtarget->hasNEON()) {
7166 if ((Align % 16 == 0) && SizeVal >= 16)
7168 else if ((Align % 8 == 0) && SizeVal >= 8)
7171 // Can't use NEON instructions.
7176 // Select the correct opcode and register class for unit size load/store
7177 bool IsNeon = UnitSize >= 8;
7178 TRC = (IsThumb1 || IsThumb2) ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
7180 VecTRC = UnitSize == 16 ? &ARM::DPairRegClass
7181 : UnitSize == 8 ? &ARM::DPRRegClass
7184 unsigned BytesLeft = SizeVal % UnitSize;
7185 unsigned LoopSize = SizeVal - BytesLeft;
7187 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
7188 // Use LDR and STR to copy.
7189 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
7190 // [destOut] = STR_POST(scratch, destIn, UnitSize)
7191 unsigned srcIn = src;
7192 unsigned destIn = dest;
7193 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
7194 unsigned srcOut = MRI.createVirtualRegister(TRC);
7195 unsigned destOut = MRI.createVirtualRegister(TRC);
7196 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7197 emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
7198 IsThumb1, IsThumb2);
7199 emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
7200 IsThumb1, IsThumb2);
7205 // Handle the leftover bytes with LDRB and STRB.
7206 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
7207 // [destOut] = STRB_POST(scratch, destIn, 1)
7208 for (unsigned i = 0; i < BytesLeft; i++) {
7209 unsigned srcOut = MRI.createVirtualRegister(TRC);
7210 unsigned destOut = MRI.createVirtualRegister(TRC);
7211 unsigned scratch = MRI.createVirtualRegister(TRC);
7212 emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
7213 IsThumb1, IsThumb2);
7214 emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
7215 IsThumb1, IsThumb2);
7219 MI->eraseFromParent(); // The instruction is gone now.
7223 // Expand the pseudo op to a loop.
7226 // movw varEnd, # --> with thumb2
7228 // ldrcp varEnd, idx --> without thumb2
7229 // fallthrough --> loopMBB
7231 // PHI varPhi, varEnd, varLoop
7232 // PHI srcPhi, src, srcLoop
7233 // PHI destPhi, dst, destLoop
7234 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7235 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
7236 // subs varLoop, varPhi, #UnitSize
7238 // fallthrough --> exitMBB
7240 // epilogue to handle left-over bytes
7241 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7242 // [destOut] = STRB_POST(scratch, destLoop, 1)
7243 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7244 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7245 MF->insert(It, loopMBB);
7246 MF->insert(It, exitMBB);
7248 // Transfer the remainder of BB and its successor edges to exitMBB.
7249 exitMBB->splice(exitMBB->begin(), BB,
7250 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7251 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7253 // Load an immediate to varEnd.
7254 unsigned varEnd = MRI.createVirtualRegister(TRC);
7256 unsigned Vtmp = varEnd;
7257 if ((LoopSize & 0xFFFF0000) != 0)
7258 Vtmp = MRI.createVirtualRegister(TRC);
7259 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), Vtmp)
7260 .addImm(LoopSize & 0xFFFF));
7262 if ((LoopSize & 0xFFFF0000) != 0)
7263 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
7264 .addReg(Vtmp).addImm(LoopSize >> 16));
7266 MachineConstantPool *ConstantPool = MF->getConstantPool();
7267 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7268 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
7270 // MachineConstantPool wants an explicit alignment.
7271 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
7273 Align = getDataLayout()->getTypeAllocSize(C->getType());
7274 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7277 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
7278 varEnd, RegState::Define).addConstantPoolIndex(Idx));
7280 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
7281 varEnd, RegState::Define).addConstantPoolIndex(Idx).addImm(0));
7283 BB->addSuccessor(loopMBB);
7285 // Generate the loop body:
7286 // varPhi = PHI(varLoop, varEnd)
7287 // srcPhi = PHI(srcLoop, src)
7288 // destPhi = PHI(destLoop, dst)
7289 MachineBasicBlock *entryBB = BB;
7291 unsigned varLoop = MRI.createVirtualRegister(TRC);
7292 unsigned varPhi = MRI.createVirtualRegister(TRC);
7293 unsigned srcLoop = MRI.createVirtualRegister(TRC);
7294 unsigned srcPhi = MRI.createVirtualRegister(TRC);
7295 unsigned destLoop = MRI.createVirtualRegister(TRC);
7296 unsigned destPhi = MRI.createVirtualRegister(TRC);
7298 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
7299 .addReg(varLoop).addMBB(loopMBB)
7300 .addReg(varEnd).addMBB(entryBB);
7301 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
7302 .addReg(srcLoop).addMBB(loopMBB)
7303 .addReg(src).addMBB(entryBB);
7304 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
7305 .addReg(destLoop).addMBB(loopMBB)
7306 .addReg(dest).addMBB(entryBB);
7308 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7309 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
7310 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7311 emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
7312 IsThumb1, IsThumb2);
7313 emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
7314 IsThumb1, IsThumb2);
7316 // Decrement loop variable by UnitSize.
7318 MachineInstrBuilder MIB =
7319 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
7320 MIB = AddDefaultT1CC(MIB);
7321 MIB.addReg(varPhi).addImm(UnitSize);
7322 AddDefaultPred(MIB);
7324 MachineInstrBuilder MIB =
7325 BuildMI(*BB, BB->end(), dl,
7326 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
7327 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7328 MIB->getOperand(5).setReg(ARM::CPSR);
7329 MIB->getOperand(5).setIsDef(true);
7331 BuildMI(*BB, BB->end(), dl,
7332 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
7333 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
7335 // loopMBB can loop back to loopMBB or fall through to exitMBB.
7336 BB->addSuccessor(loopMBB);
7337 BB->addSuccessor(exitMBB);
7339 // Add epilogue to handle BytesLeft.
7341 MachineInstr *StartOfExit = exitMBB->begin();
7343 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7344 // [destOut] = STRB_POST(scratch, destLoop, 1)
7345 unsigned srcIn = srcLoop;
7346 unsigned destIn = destLoop;
7347 for (unsigned i = 0; i < BytesLeft; i++) {
7348 unsigned srcOut = MRI.createVirtualRegister(TRC);
7349 unsigned destOut = MRI.createVirtualRegister(TRC);
7350 unsigned scratch = MRI.createVirtualRegister(TRC);
7351 emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
7352 IsThumb1, IsThumb2);
7353 emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
7354 IsThumb1, IsThumb2);
7359 MI->eraseFromParent(); // The instruction is gone now.
7364 ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI,
7365 MachineBasicBlock *MBB) const {
7366 const TargetMachine &TM = getTargetMachine();
7367 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
7368 DebugLoc DL = MI->getDebugLoc();
7370 assert(Subtarget->isTargetWindows() &&
7371 "__chkstk is only supported on Windows");
7372 assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
7374 // __chkstk takes the number of words to allocate on the stack in R4, and
7375 // returns the stack adjustment in number of bytes in R4. This will not
7376 // clober any other registers (other than the obvious lr).
7378 // Although, technically, IP should be considered a register which may be
7379 // clobbered, the call itself will not touch it. Windows on ARM is a pure
7380 // thumb-2 environment, so there is no interworking required. As a result, we
7381 // do not expect a veneer to be emitted by the linker, clobbering IP.
7383 // Each module receives its own copy of __chkstk, so no import thunk is
7384 // required, again, ensuring that IP is not clobbered.
7386 // Finally, although some linkers may theoretically provide a trampoline for
7387 // out of range calls (which is quite common due to a 32M range limitation of
7388 // branches for Thumb), we can generate the long-call version via
7389 // -mcmodel=large, alleviating the need for the trampoline which may clobber
7392 switch (TM.getCodeModel()) {
7393 case CodeModel::Small:
7394 case CodeModel::Medium:
7395 case CodeModel::Default:
7396 case CodeModel::Kernel:
7397 BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
7398 .addImm((unsigned)ARMCC::AL).addReg(0)
7399 .addExternalSymbol("__chkstk")
7400 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7401 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7402 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7404 case CodeModel::Large:
7405 case CodeModel::JITDefault: {
7406 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
7407 unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
7409 BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
7410 .addExternalSymbol("__chkstk");
7411 BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
7412 .addImm((unsigned)ARMCC::AL).addReg(0)
7413 .addReg(Reg, RegState::Kill)
7414 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7415 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7416 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7421 AddDefaultCC(AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr),
7423 .addReg(ARM::SP).addReg(ARM::R4)));
7425 MI->eraseFromParent();
7430 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7431 MachineBasicBlock *BB) const {
7432 const TargetInstrInfo *TII =
7433 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7434 DebugLoc dl = MI->getDebugLoc();
7435 bool isThumb2 = Subtarget->isThumb2();
7436 switch (MI->getOpcode()) {
7439 llvm_unreachable("Unexpected instr type to insert");
7441 // The Thumb2 pre-indexed stores have the same MI operands, they just
7442 // define them differently in the .td files from the isel patterns, so
7443 // they need pseudos.
7444 case ARM::t2STR_preidx:
7445 MI->setDesc(TII->get(ARM::t2STR_PRE));
7447 case ARM::t2STRB_preidx:
7448 MI->setDesc(TII->get(ARM::t2STRB_PRE));
7450 case ARM::t2STRH_preidx:
7451 MI->setDesc(TII->get(ARM::t2STRH_PRE));
7454 case ARM::STRi_preidx:
7455 case ARM::STRBi_preidx: {
7456 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7457 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
7458 // Decode the offset.
7459 unsigned Offset = MI->getOperand(4).getImm();
7460 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
7461 Offset = ARM_AM::getAM2Offset(Offset);
7465 MachineMemOperand *MMO = *MI->memoperands_begin();
7466 BuildMI(*BB, MI, dl, TII->get(NewOpc))
7467 .addOperand(MI->getOperand(0)) // Rn_wb
7468 .addOperand(MI->getOperand(1)) // Rt
7469 .addOperand(MI->getOperand(2)) // Rn
7470 .addImm(Offset) // offset (skip GPR==zero_reg)
7471 .addOperand(MI->getOperand(5)) // pred
7472 .addOperand(MI->getOperand(6))
7473 .addMemOperand(MMO);
7474 MI->eraseFromParent();
7477 case ARM::STRr_preidx:
7478 case ARM::STRBr_preidx:
7479 case ARM::STRH_preidx: {
7481 switch (MI->getOpcode()) {
7482 default: llvm_unreachable("unexpected opcode!");
7483 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7484 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7485 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7487 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7488 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
7489 MIB.addOperand(MI->getOperand(i));
7490 MI->eraseFromParent();
7494 case ARM::tMOVCCr_pseudo: {
7495 // To "insert" a SELECT_CC instruction, we actually have to insert the
7496 // diamond control-flow pattern. The incoming instruction knows the
7497 // destination vreg to set, the condition code register to branch on, the
7498 // true/false values to select between, and a branch opcode to use.
7499 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7500 MachineFunction::iterator It = BB;
7506 // cmpTY ccX, r1, r2
7508 // fallthrough --> copy0MBB
7509 MachineBasicBlock *thisMBB = BB;
7510 MachineFunction *F = BB->getParent();
7511 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7512 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7513 F->insert(It, copy0MBB);
7514 F->insert(It, sinkMBB);
7516 // Transfer the remainder of BB and its successor edges to sinkMBB.
7517 sinkMBB->splice(sinkMBB->begin(), BB,
7518 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7519 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7521 BB->addSuccessor(copy0MBB);
7522 BB->addSuccessor(sinkMBB);
7524 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
7525 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7528 // %FalseValue = ...
7529 // # fallthrough to sinkMBB
7532 // Update machine-CFG edges
7533 BB->addSuccessor(sinkMBB);
7536 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7539 BuildMI(*BB, BB->begin(), dl,
7540 TII->get(ARM::PHI), MI->getOperand(0).getReg())
7541 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7542 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7544 MI->eraseFromParent(); // The pseudo instruction is gone now.
7549 case ARM::BCCZi64: {
7550 // If there is an unconditional branch to the other successor, remove it.
7551 BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
7553 // Compare both parts that make up the double comparison separately for
7555 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7557 unsigned LHS1 = MI->getOperand(1).getReg();
7558 unsigned LHS2 = MI->getOperand(2).getReg();
7560 AddDefaultPred(BuildMI(BB, dl,
7561 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7562 .addReg(LHS1).addImm(0));
7563 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7564 .addReg(LHS2).addImm(0)
7565 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7567 unsigned RHS1 = MI->getOperand(3).getReg();
7568 unsigned RHS2 = MI->getOperand(4).getReg();
7569 AddDefaultPred(BuildMI(BB, dl,
7570 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7571 .addReg(LHS1).addReg(RHS1));
7572 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7573 .addReg(LHS2).addReg(RHS2)
7574 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7577 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
7578 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
7579 if (MI->getOperand(0).getImm() == ARMCC::NE)
7580 std::swap(destMBB, exitMBB);
7582 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
7583 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
7585 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7587 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
7589 MI->eraseFromParent(); // The pseudo instruction is gone now.
7593 case ARM::Int_eh_sjlj_setjmp:
7594 case ARM::Int_eh_sjlj_setjmp_nofp:
7595 case ARM::tInt_eh_sjlj_setjmp:
7596 case ARM::t2Int_eh_sjlj_setjmp:
7597 case ARM::t2Int_eh_sjlj_setjmp_nofp:
7598 EmitSjLjDispatchBlock(MI, BB);
7603 // To insert an ABS instruction, we have to insert the
7604 // diamond control-flow pattern. The incoming instruction knows the
7605 // source vreg to test against 0, the destination vreg to set,
7606 // the condition code register to branch on, the
7607 // true/false values to select between, and a branch opcode to use.
7612 // BCC (branch to SinkBB if V0 >= 0)
7613 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
7614 // SinkBB: V1 = PHI(V2, V3)
7615 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7616 MachineFunction::iterator BBI = BB;
7618 MachineFunction *Fn = BB->getParent();
7619 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7620 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7621 Fn->insert(BBI, RSBBB);
7622 Fn->insert(BBI, SinkBB);
7624 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7625 unsigned int ABSDstReg = MI->getOperand(0).getReg();
7626 bool isThumb2 = Subtarget->isThumb2();
7627 MachineRegisterInfo &MRI = Fn->getRegInfo();
7628 // In Thumb mode S must not be specified if source register is the SP or
7629 // PC and if destination register is the SP, so restrict register class
7630 unsigned NewRsbDstReg =
7631 MRI.createVirtualRegister(isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass);
7633 // Transfer the remainder of BB and its successor edges to sinkMBB.
7634 SinkBB->splice(SinkBB->begin(), BB,
7635 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7636 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
7638 BB->addSuccessor(RSBBB);
7639 BB->addSuccessor(SinkBB);
7641 // fall through to SinkMBB
7642 RSBBB->addSuccessor(SinkBB);
7644 // insert a cmp at the end of BB
7645 AddDefaultPred(BuildMI(BB, dl,
7646 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7647 .addReg(ABSSrcReg).addImm(0));
7649 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
7651 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
7652 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
7654 // insert rsbri in RSBBB
7655 // Note: BCC and rsbri will be converted into predicated rsbmi
7656 // by if-conversion pass
7657 BuildMI(*RSBBB, RSBBB->begin(), dl,
7658 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
7659 .addReg(ABSSrcReg, RegState::Kill)
7660 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
7662 // insert PHI in SinkBB,
7663 // reuse ABSDstReg to not change uses of ABS instruction
7664 BuildMI(*SinkBB, SinkBB->begin(), dl,
7665 TII->get(ARM::PHI), ABSDstReg)
7666 .addReg(NewRsbDstReg).addMBB(RSBBB)
7667 .addReg(ABSSrcReg).addMBB(BB);
7669 // remove ABS instruction
7670 MI->eraseFromParent();
7672 // return last added BB
7675 case ARM::COPY_STRUCT_BYVAL_I32:
7677 return EmitStructByval(MI, BB);
7678 case ARM::WIN__CHKSTK:
7679 return EmitLowered__chkstk(MI, BB);
7683 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
7684 SDNode *Node) const {
7685 const MCInstrDesc *MCID = &MI->getDesc();
7686 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7687 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7688 // operand is still set to noreg. If needed, set the optional operand's
7689 // register to CPSR, and remove the redundant implicit def.
7691 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
7693 // Rename pseudo opcodes.
7694 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7696 const ARMBaseInstrInfo *TII = static_cast<const ARMBaseInstrInfo *>(
7697 getTargetMachine().getSubtargetImpl()->getInstrInfo());
7698 MCID = &TII->get(NewOpc);
7700 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7701 "converted opcode should be the same except for cc_out");
7705 // Add the optional cc_out operand
7706 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
7708 unsigned ccOutIdx = MCID->getNumOperands() - 1;
7710 // Any ARM instruction that sets the 's' bit should specify an optional
7711 // "cc_out" operand in the last operand position.
7712 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
7713 assert(!NewOpc && "Optional cc_out operand required");
7716 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
7717 // since we already have an optional CPSR def.
7718 bool definesCPSR = false;
7719 bool deadCPSR = false;
7720 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
7722 const MachineOperand &MO = MI->getOperand(i);
7723 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
7727 MI->RemoveOperand(i);
7732 assert(!NewOpc && "Optional cc_out operand required");
7735 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
7737 assert(!MI->getOperand(ccOutIdx).getReg() &&
7738 "expect uninitialized optional cc_out operand");
7742 // If this instruction was defined with an optional CPSR def and its dag node
7743 // had a live implicit CPSR def, then activate the optional CPSR def.
7744 MachineOperand &MO = MI->getOperand(ccOutIdx);
7745 MO.setReg(ARM::CPSR);
7749 //===----------------------------------------------------------------------===//
7750 // ARM Optimization Hooks
7751 //===----------------------------------------------------------------------===//
7753 // Helper function that checks if N is a null or all ones constant.
7754 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
7755 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
7758 return AllOnes ? C->isAllOnesValue() : C->isNullValue();
7761 // Return true if N is conditionally 0 or all ones.
7762 // Detects these expressions where cc is an i1 value:
7764 // (select cc 0, y) [AllOnes=0]
7765 // (select cc y, 0) [AllOnes=0]
7766 // (zext cc) [AllOnes=0]
7767 // (sext cc) [AllOnes=0/1]
7768 // (select cc -1, y) [AllOnes=1]
7769 // (select cc y, -1) [AllOnes=1]
7771 // Invert is set when N is the null/all ones constant when CC is false.
7772 // OtherOp is set to the alternative value of N.
7773 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
7774 SDValue &CC, bool &Invert,
7776 SelectionDAG &DAG) {
7777 switch (N->getOpcode()) {
7778 default: return false;
7780 CC = N->getOperand(0);
7781 SDValue N1 = N->getOperand(1);
7782 SDValue N2 = N->getOperand(2);
7783 if (isZeroOrAllOnes(N1, AllOnes)) {
7788 if (isZeroOrAllOnes(N2, AllOnes)) {
7795 case ISD::ZERO_EXTEND:
7796 // (zext cc) can never be the all ones value.
7800 case ISD::SIGN_EXTEND: {
7801 EVT VT = N->getValueType(0);
7802 CC = N->getOperand(0);
7803 if (CC.getValueType() != MVT::i1)
7807 // When looking for an AllOnes constant, N is an sext, and the 'other'
7809 OtherOp = DAG.getConstant(0, VT);
7810 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7811 // When looking for a 0 constant, N can be zext or sext.
7812 OtherOp = DAG.getConstant(1, VT);
7814 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
7820 // Combine a constant select operand into its use:
7822 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
7823 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
7824 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
7825 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
7826 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
7828 // The transform is rejected if the select doesn't have a constant operand that
7829 // is null, or all ones when AllOnes is set.
7831 // Also recognize sext/zext from i1:
7833 // (add (zext cc), x) -> (select cc (add x, 1), x)
7834 // (add (sext cc), x) -> (select cc (add x, -1), x)
7836 // These transformations eventually create predicated instructions.
7838 // @param N The node to transform.
7839 // @param Slct The N operand that is a select.
7840 // @param OtherOp The other N operand (x above).
7841 // @param DCI Context.
7842 // @param AllOnes Require the select constant to be all ones instead of null.
7843 // @returns The new node, or SDValue() on failure.
7845 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
7846 TargetLowering::DAGCombinerInfo &DCI,
7847 bool AllOnes = false) {
7848 SelectionDAG &DAG = DCI.DAG;
7849 EVT VT = N->getValueType(0);
7850 SDValue NonConstantVal;
7853 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
7854 NonConstantVal, DAG))
7857 // Slct is now know to be the desired identity constant when CC is true.
7858 SDValue TrueVal = OtherOp;
7859 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
7860 OtherOp, NonConstantVal);
7861 // Unless SwapSelectOps says CC should be false.
7863 std::swap(TrueVal, FalseVal);
7865 return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
7866 CCOp, TrueVal, FalseVal);
7869 // Attempt combineSelectAndUse on each operand of a commutative operator N.
7871 SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
7872 TargetLowering::DAGCombinerInfo &DCI) {
7873 SDValue N0 = N->getOperand(0);
7874 SDValue N1 = N->getOperand(1);
7875 if (N0.getNode()->hasOneUse()) {
7876 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
7877 if (Result.getNode())
7880 if (N1.getNode()->hasOneUse()) {
7881 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
7882 if (Result.getNode())
7888 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
7889 // (only after legalization).
7890 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
7891 TargetLowering::DAGCombinerInfo &DCI,
7892 const ARMSubtarget *Subtarget) {
7894 // Only perform optimization if after legalize, and if NEON is available. We
7895 // also expected both operands to be BUILD_VECTORs.
7896 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
7897 || N0.getOpcode() != ISD::BUILD_VECTOR
7898 || N1.getOpcode() != ISD::BUILD_VECTOR)
7901 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
7902 EVT VT = N->getValueType(0);
7903 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
7906 // Check that the vector operands are of the right form.
7907 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
7908 // operands, where N is the size of the formed vector.
7909 // Each EXTRACT_VECTOR should have the same input vector and odd or even
7910 // index such that we have a pair wise add pattern.
7912 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
7913 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7915 SDValue Vec = N0->getOperand(0)->getOperand(0);
7916 SDNode *V = Vec.getNode();
7917 unsigned nextIndex = 0;
7919 // For each operands to the ADD which are BUILD_VECTORs,
7920 // check to see if each of their operands are an EXTRACT_VECTOR with
7921 // the same vector and appropriate index.
7922 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
7923 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
7924 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7926 SDValue ExtVec0 = N0->getOperand(i);
7927 SDValue ExtVec1 = N1->getOperand(i);
7929 // First operand is the vector, verify its the same.
7930 if (V != ExtVec0->getOperand(0).getNode() ||
7931 V != ExtVec1->getOperand(0).getNode())
7934 // Second is the constant, verify its correct.
7935 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
7936 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
7938 // For the constant, we want to see all the even or all the odd.
7939 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
7940 || C1->getZExtValue() != nextIndex+1)
7949 // Create VPADDL node.
7950 SelectionDAG &DAG = DCI.DAG;
7951 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7953 // Build operand list.
7954 SmallVector<SDValue, 8> Ops;
7955 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
7956 TLI.getPointerTy()));
7958 // Input is the vector.
7961 // Get widened type and narrowed type.
7963 unsigned numElem = VT.getVectorNumElements();
7965 EVT inputLaneType = Vec.getValueType().getVectorElementType();
7966 switch (inputLaneType.getSimpleVT().SimpleTy) {
7967 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
7968 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
7969 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
7971 llvm_unreachable("Invalid vector element type for padd optimization.");
7974 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), widenType, Ops);
7975 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
7976 return DAG.getNode(ExtOp, SDLoc(N), VT, tmp);
7979 static SDValue findMUL_LOHI(SDValue V) {
7980 if (V->getOpcode() == ISD::UMUL_LOHI ||
7981 V->getOpcode() == ISD::SMUL_LOHI)
7986 static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
7987 TargetLowering::DAGCombinerInfo &DCI,
7988 const ARMSubtarget *Subtarget) {
7990 if (Subtarget->isThumb1Only()) return SDValue();
7992 // Only perform the checks after legalize when the pattern is available.
7993 if (DCI.isBeforeLegalize()) return SDValue();
7995 // Look for multiply add opportunities.
7996 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
7997 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
7998 // a glue link from the first add to the second add.
7999 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
8000 // a S/UMLAL instruction.
8003 // \ / \ [no multiline comment]
8009 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
8010 SDValue AddcOp0 = AddcNode->getOperand(0);
8011 SDValue AddcOp1 = AddcNode->getOperand(1);
8013 // Check if the two operands are from the same mul_lohi node.
8014 if (AddcOp0.getNode() == AddcOp1.getNode())
8017 assert(AddcNode->getNumValues() == 2 &&
8018 AddcNode->getValueType(0) == MVT::i32 &&
8019 "Expect ADDC with two result values. First: i32");
8021 // Check that we have a glued ADDC node.
8022 if (AddcNode->getValueType(1) != MVT::Glue)
8025 // Check that the ADDC adds the low result of the S/UMUL_LOHI.
8026 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
8027 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
8028 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
8029 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
8032 // Look for the glued ADDE.
8033 SDNode* AddeNode = AddcNode->getGluedUser();
8037 // Make sure it is really an ADDE.
8038 if (AddeNode->getOpcode() != ISD::ADDE)
8041 assert(AddeNode->getNumOperands() == 3 &&
8042 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
8043 "ADDE node has the wrong inputs");
8045 // Check for the triangle shape.
8046 SDValue AddeOp0 = AddeNode->getOperand(0);
8047 SDValue AddeOp1 = AddeNode->getOperand(1);
8049 // Make sure that the ADDE operands are not coming from the same node.
8050 if (AddeOp0.getNode() == AddeOp1.getNode())
8053 // Find the MUL_LOHI node walking up ADDE's operands.
8054 bool IsLeftOperandMUL = false;
8055 SDValue MULOp = findMUL_LOHI(AddeOp0);
8056 if (MULOp == SDValue())
8057 MULOp = findMUL_LOHI(AddeOp1);
8059 IsLeftOperandMUL = true;
8060 if (MULOp == SDValue())
8063 // Figure out the right opcode.
8064 unsigned Opc = MULOp->getOpcode();
8065 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
8067 // Figure out the high and low input values to the MLAL node.
8068 SDValue* HiMul = &MULOp;
8069 SDValue* HiAdd = nullptr;
8070 SDValue* LoMul = nullptr;
8071 SDValue* LowAdd = nullptr;
8073 if (IsLeftOperandMUL)
8079 if (AddcOp0->getOpcode() == Opc) {
8083 if (AddcOp1->getOpcode() == Opc) {
8091 if (LoMul->getNode() != HiMul->getNode())
8094 // Create the merged node.
8095 SelectionDAG &DAG = DCI.DAG;
8097 // Build operand list.
8098 SmallVector<SDValue, 8> Ops;
8099 Ops.push_back(LoMul->getOperand(0));
8100 Ops.push_back(LoMul->getOperand(1));
8101 Ops.push_back(*LowAdd);
8102 Ops.push_back(*HiAdd);
8104 SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode),
8105 DAG.getVTList(MVT::i32, MVT::i32), Ops);
8107 // Replace the ADDs' nodes uses by the MLA node's values.
8108 SDValue HiMLALResult(MLALNode.getNode(), 1);
8109 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
8111 SDValue LoMLALResult(MLALNode.getNode(), 0);
8112 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
8114 // Return original node to notify the driver to stop replacing.
8115 SDValue resNode(AddcNode, 0);
8119 /// PerformADDCCombine - Target-specific dag combine transform from
8120 /// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
8121 static SDValue PerformADDCCombine(SDNode *N,
8122 TargetLowering::DAGCombinerInfo &DCI,
8123 const ARMSubtarget *Subtarget) {
8125 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
8129 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
8130 /// operands N0 and N1. This is a helper for PerformADDCombine that is
8131 /// called with the default operands, and if that fails, with commuted
8133 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
8134 TargetLowering::DAGCombinerInfo &DCI,
8135 const ARMSubtarget *Subtarget){
8137 // Attempt to create vpaddl for this add.
8138 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8139 if (Result.getNode())
8142 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8143 if (N0.getNode()->hasOneUse()) {
8144 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8145 if (Result.getNode()) return Result;
8150 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
8152 static SDValue PerformADDCombine(SDNode *N,
8153 TargetLowering::DAGCombinerInfo &DCI,
8154 const ARMSubtarget *Subtarget) {
8155 SDValue N0 = N->getOperand(0);
8156 SDValue N1 = N->getOperand(1);
8158 // First try with the default operand order.
8159 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8160 if (Result.getNode())
8163 // If that didn't work, try again with the operands commuted.
8164 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
8167 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
8169 static SDValue PerformSUBCombine(SDNode *N,
8170 TargetLowering::DAGCombinerInfo &DCI) {
8171 SDValue N0 = N->getOperand(0);
8172 SDValue N1 = N->getOperand(1);
8174 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8175 if (N1.getNode()->hasOneUse()) {
8176 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8177 if (Result.getNode()) return Result;
8183 /// PerformVMULCombine
8184 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
8185 /// special multiplier accumulator forwarding.
8191 // However, for (A + B) * (A + B),
8198 static SDValue PerformVMULCombine(SDNode *N,
8199 TargetLowering::DAGCombinerInfo &DCI,
8200 const ARMSubtarget *Subtarget) {
8201 if (!Subtarget->hasVMLxForwarding())
8204 SelectionDAG &DAG = DCI.DAG;
8205 SDValue N0 = N->getOperand(0);
8206 SDValue N1 = N->getOperand(1);
8207 unsigned Opcode = N0.getOpcode();
8208 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8209 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
8210 Opcode = N1.getOpcode();
8211 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8212 Opcode != ISD::FADD && Opcode != ISD::FSUB)
8220 EVT VT = N->getValueType(0);
8222 SDValue N00 = N0->getOperand(0);
8223 SDValue N01 = N0->getOperand(1);
8224 return DAG.getNode(Opcode, DL, VT,
8225 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
8226 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
8229 static SDValue PerformMULCombine(SDNode *N,
8230 TargetLowering::DAGCombinerInfo &DCI,
8231 const ARMSubtarget *Subtarget) {
8232 SelectionDAG &DAG = DCI.DAG;
8234 if (Subtarget->isThumb1Only())
8237 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8240 EVT VT = N->getValueType(0);
8241 if (VT.is64BitVector() || VT.is128BitVector())
8242 return PerformVMULCombine(N, DCI, Subtarget);
8246 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8250 int64_t MulAmt = C->getSExtValue();
8251 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
8253 ShiftAmt = ShiftAmt & (32 - 1);
8254 SDValue V = N->getOperand(0);
8258 MulAmt >>= ShiftAmt;
8261 if (isPowerOf2_32(MulAmt - 1)) {
8262 // (mul x, 2^N + 1) => (add (shl x, N), x)
8263 Res = DAG.getNode(ISD::ADD, DL, VT,
8265 DAG.getNode(ISD::SHL, DL, VT,
8267 DAG.getConstant(Log2_32(MulAmt - 1),
8269 } else if (isPowerOf2_32(MulAmt + 1)) {
8270 // (mul x, 2^N - 1) => (sub (shl x, N), x)
8271 Res = DAG.getNode(ISD::SUB, DL, VT,
8272 DAG.getNode(ISD::SHL, DL, VT,
8274 DAG.getConstant(Log2_32(MulAmt + 1),
8280 uint64_t MulAmtAbs = -MulAmt;
8281 if (isPowerOf2_32(MulAmtAbs + 1)) {
8282 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
8283 Res = DAG.getNode(ISD::SUB, DL, VT,
8285 DAG.getNode(ISD::SHL, DL, VT,
8287 DAG.getConstant(Log2_32(MulAmtAbs + 1),
8289 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
8290 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
8291 Res = DAG.getNode(ISD::ADD, DL, VT,
8293 DAG.getNode(ISD::SHL, DL, VT,
8295 DAG.getConstant(Log2_32(MulAmtAbs-1),
8297 Res = DAG.getNode(ISD::SUB, DL, VT,
8298 DAG.getConstant(0, MVT::i32),Res);
8305 Res = DAG.getNode(ISD::SHL, DL, VT,
8306 Res, DAG.getConstant(ShiftAmt, MVT::i32));
8308 // Do not add new nodes to DAG combiner worklist.
8309 DCI.CombineTo(N, Res, false);
8313 static SDValue PerformANDCombine(SDNode *N,
8314 TargetLowering::DAGCombinerInfo &DCI,
8315 const ARMSubtarget *Subtarget) {
8317 // Attempt to use immediate-form VBIC
8318 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8320 EVT VT = N->getValueType(0);
8321 SelectionDAG &DAG = DCI.DAG;
8323 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8326 APInt SplatBits, SplatUndef;
8327 unsigned SplatBitSize;
8330 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8331 if (SplatBitSize <= 64) {
8333 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
8334 SplatUndef.getZExtValue(), SplatBitSize,
8335 DAG, VbicVT, VT.is128BitVector(),
8337 if (Val.getNode()) {
8339 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
8340 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
8341 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
8346 if (!Subtarget->isThumb1Only()) {
8347 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
8348 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
8349 if (Result.getNode())
8356 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
8357 static SDValue PerformORCombine(SDNode *N,
8358 TargetLowering::DAGCombinerInfo &DCI,
8359 const ARMSubtarget *Subtarget) {
8360 // Attempt to use immediate-form VORR
8361 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8363 EVT VT = N->getValueType(0);
8364 SelectionDAG &DAG = DCI.DAG;
8366 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8369 APInt SplatBits, SplatUndef;
8370 unsigned SplatBitSize;
8372 if (BVN && Subtarget->hasNEON() &&
8373 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8374 if (SplatBitSize <= 64) {
8376 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
8377 SplatUndef.getZExtValue(), SplatBitSize,
8378 DAG, VorrVT, VT.is128BitVector(),
8380 if (Val.getNode()) {
8382 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
8383 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
8384 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
8389 if (!Subtarget->isThumb1Only()) {
8390 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8391 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8392 if (Result.getNode())
8396 // The code below optimizes (or (and X, Y), Z).
8397 // The AND operand needs to have a single user to make these optimizations
8399 SDValue N0 = N->getOperand(0);
8400 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8402 SDValue N1 = N->getOperand(1);
8404 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
8405 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8406 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
8408 unsigned SplatBitSize;
8411 APInt SplatBits0, SplatBits1;
8412 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
8413 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
8414 // Ensure that the second operand of both ands are constants
8415 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
8416 HasAnyUndefs) && !HasAnyUndefs) {
8417 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
8418 HasAnyUndefs) && !HasAnyUndefs) {
8419 // Ensure that the bit width of the constants are the same and that
8420 // the splat arguments are logical inverses as per the pattern we
8421 // are trying to simplify.
8422 if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
8423 SplatBits0 == ~SplatBits1) {
8424 // Canonicalize the vector type to make instruction selection
8426 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
8427 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
8431 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
8437 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
8440 // BFI is only available on V6T2+
8441 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
8445 // 1) or (and A, mask), val => ARMbfi A, val, mask
8446 // iff (val & mask) == val
8448 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8449 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
8450 // && mask == ~mask2
8451 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
8452 // && ~mask == mask2
8453 // (i.e., copy a bitfield value into another bitfield of the same width)
8458 SDValue N00 = N0.getOperand(0);
8460 // The value and the mask need to be constants so we can verify this is
8461 // actually a bitfield set. If the mask is 0xffff, we can do better
8462 // via a movt instruction, so don't use BFI in that case.
8463 SDValue MaskOp = N0.getOperand(1);
8464 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
8467 unsigned Mask = MaskC->getZExtValue();
8471 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
8472 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8474 unsigned Val = N1C->getZExtValue();
8475 if ((Val & ~Mask) != Val)
8478 if (ARM::isBitFieldInvertedMask(Mask)) {
8479 Val >>= countTrailingZeros(~Mask);
8481 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
8482 DAG.getConstant(Val, MVT::i32),
8483 DAG.getConstant(Mask, MVT::i32));
8485 // Do not add new nodes to DAG combiner worklist.
8486 DCI.CombineTo(N, Res, false);
8489 } else if (N1.getOpcode() == ISD::AND) {
8490 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8491 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8494 unsigned Mask2 = N11C->getZExtValue();
8496 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8498 if (ARM::isBitFieldInvertedMask(Mask) &&
8500 // The pack halfword instruction works better for masks that fit it,
8501 // so use that when it's available.
8502 if (Subtarget->hasT2ExtractPack() &&
8503 (Mask == 0xffff || Mask == 0xffff0000))
8506 unsigned amt = countTrailingZeros(Mask2);
8507 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
8508 DAG.getConstant(amt, MVT::i32));
8509 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
8510 DAG.getConstant(Mask, MVT::i32));
8511 // Do not add new nodes to DAG combiner worklist.
8512 DCI.CombineTo(N, Res, false);
8514 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
8516 // The pack halfword instruction works better for masks that fit it,
8517 // so use that when it's available.
8518 if (Subtarget->hasT2ExtractPack() &&
8519 (Mask2 == 0xffff || Mask2 == 0xffff0000))
8522 unsigned lsb = countTrailingZeros(Mask);
8523 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
8524 DAG.getConstant(lsb, MVT::i32));
8525 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
8526 DAG.getConstant(Mask2, MVT::i32));
8527 // Do not add new nodes to DAG combiner worklist.
8528 DCI.CombineTo(N, Res, false);
8533 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
8534 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
8535 ARM::isBitFieldInvertedMask(~Mask)) {
8536 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
8537 // where lsb(mask) == #shamt and masked bits of B are known zero.
8538 SDValue ShAmt = N00.getOperand(1);
8539 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
8540 unsigned LSB = countTrailingZeros(Mask);
8544 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
8545 DAG.getConstant(~Mask, MVT::i32));
8547 // Do not add new nodes to DAG combiner worklist.
8548 DCI.CombineTo(N, Res, false);
8554 static SDValue PerformXORCombine(SDNode *N,
8555 TargetLowering::DAGCombinerInfo &DCI,
8556 const ARMSubtarget *Subtarget) {
8557 EVT VT = N->getValueType(0);
8558 SelectionDAG &DAG = DCI.DAG;
8560 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8563 if (!Subtarget->isThumb1Only()) {
8564 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8565 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8566 if (Result.getNode())
8573 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
8574 /// the bits being cleared by the AND are not demanded by the BFI.
8575 static SDValue PerformBFICombine(SDNode *N,
8576 TargetLowering::DAGCombinerInfo &DCI) {
8577 SDValue N1 = N->getOperand(1);
8578 if (N1.getOpcode() == ISD::AND) {
8579 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8582 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
8583 unsigned LSB = countTrailingZeros(~InvMask);
8584 unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
8586 static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
8587 "undefined behavior");
8588 unsigned Mask = (1u << Width) - 1;
8589 unsigned Mask2 = N11C->getZExtValue();
8590 if ((Mask & (~Mask2)) == 0)
8591 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
8592 N->getOperand(0), N1.getOperand(0),
8598 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
8599 /// ARMISD::VMOVRRD.
8600 static SDValue PerformVMOVRRDCombine(SDNode *N,
8601 TargetLowering::DAGCombinerInfo &DCI,
8602 const ARMSubtarget *Subtarget) {
8603 // vmovrrd(vmovdrr x, y) -> x,y
8604 SDValue InDouble = N->getOperand(0);
8605 if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP())
8606 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
8608 // vmovrrd(load f64) -> (load i32), (load i32)
8609 SDNode *InNode = InDouble.getNode();
8610 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
8611 InNode->getValueType(0) == MVT::f64 &&
8612 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
8613 !cast<LoadSDNode>(InNode)->isVolatile()) {
8614 // TODO: Should this be done for non-FrameIndex operands?
8615 LoadSDNode *LD = cast<LoadSDNode>(InNode);
8617 SelectionDAG &DAG = DCI.DAG;
8619 SDValue BasePtr = LD->getBasePtr();
8620 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8621 LD->getPointerInfo(), LD->isVolatile(),
8622 LD->isNonTemporal(), LD->isInvariant(),
8623 LD->getAlignment());
8625 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8626 DAG.getConstant(4, MVT::i32));
8627 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
8628 LD->getPointerInfo(), LD->isVolatile(),
8629 LD->isNonTemporal(), LD->isInvariant(),
8630 std::min(4U, LD->getAlignment() / 2));
8632 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
8633 if (DCI.DAG.getTargetLoweringInfo().isBigEndian())
8634 std::swap (NewLD1, NewLD2);
8635 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
8642 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
8643 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
8644 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
8645 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
8646 SDValue Op0 = N->getOperand(0);
8647 SDValue Op1 = N->getOperand(1);
8648 if (Op0.getOpcode() == ISD::BITCAST)
8649 Op0 = Op0.getOperand(0);
8650 if (Op1.getOpcode() == ISD::BITCAST)
8651 Op1 = Op1.getOperand(0);
8652 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8653 Op0.getNode() == Op1.getNode() &&
8654 Op0.getResNo() == 0 && Op1.getResNo() == 1)
8655 return DAG.getNode(ISD::BITCAST, SDLoc(N),
8656 N->getValueType(0), Op0.getOperand(0));
8660 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
8661 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
8662 /// i64 vector to have f64 elements, since the value can then be loaded
8663 /// directly into a VFP register.
8664 static bool hasNormalLoadOperand(SDNode *N) {
8665 unsigned NumElts = N->getValueType(0).getVectorNumElements();
8666 for (unsigned i = 0; i < NumElts; ++i) {
8667 SDNode *Elt = N->getOperand(i).getNode();
8668 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
8674 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
8675 /// ISD::BUILD_VECTOR.
8676 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
8677 TargetLowering::DAGCombinerInfo &DCI,
8678 const ARMSubtarget *Subtarget) {
8679 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
8680 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
8681 // into a pair of GPRs, which is fine when the value is used as a scalar,
8682 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
8683 SelectionDAG &DAG = DCI.DAG;
8684 if (N->getNumOperands() == 2) {
8685 SDValue RV = PerformVMOVDRRCombine(N, DAG);
8690 // Load i64 elements as f64 values so that type legalization does not split
8691 // them up into i32 values.
8692 EVT VT = N->getValueType(0);
8693 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
8696 SmallVector<SDValue, 8> Ops;
8697 unsigned NumElts = VT.getVectorNumElements();
8698 for (unsigned i = 0; i < NumElts; ++i) {
8699 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
8701 // Make the DAGCombiner fold the bitcast.
8702 DCI.AddToWorklist(V.getNode());
8704 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
8705 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops);
8706 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8709 /// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
8711 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
8712 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
8713 // At that time, we may have inserted bitcasts from integer to float.
8714 // If these bitcasts have survived DAGCombine, change the lowering of this
8715 // BUILD_VECTOR in something more vector friendly, i.e., that does not
8716 // force to use floating point types.
8718 // Make sure we can change the type of the vector.
8719 // This is possible iff:
8720 // 1. The vector is only used in a bitcast to a integer type. I.e.,
8721 // 1.1. Vector is used only once.
8722 // 1.2. Use is a bit convert to an integer type.
8723 // 2. The size of its operands are 32-bits (64-bits are not legal).
8724 EVT VT = N->getValueType(0);
8725 EVT EltVT = VT.getVectorElementType();
8727 // Check 1.1. and 2.
8728 if (EltVT.getSizeInBits() != 32 || !N->hasOneUse())
8731 // By construction, the input type must be float.
8732 assert(EltVT == MVT::f32 && "Unexpected type!");
8735 SDNode *Use = *N->use_begin();
8736 if (Use->getOpcode() != ISD::BITCAST ||
8737 Use->getValueType(0).isFloatingPoint())
8740 // Check profitability.
8741 // Model is, if more than half of the relevant operands are bitcast from
8742 // i32, turn the build_vector into a sequence of insert_vector_elt.
8743 // Relevant operands are everything that is not statically
8744 // (i.e., at compile time) bitcasted.
8745 unsigned NumOfBitCastedElts = 0;
8746 unsigned NumElts = VT.getVectorNumElements();
8747 unsigned NumOfRelevantElts = NumElts;
8748 for (unsigned Idx = 0; Idx < NumElts; ++Idx) {
8749 SDValue Elt = N->getOperand(Idx);
8750 if (Elt->getOpcode() == ISD::BITCAST) {
8751 // Assume only bit cast to i32 will go away.
8752 if (Elt->getOperand(0).getValueType() == MVT::i32)
8753 ++NumOfBitCastedElts;
8754 } else if (Elt.getOpcode() == ISD::UNDEF || isa<ConstantSDNode>(Elt))
8755 // Constants are statically casted, thus do not count them as
8756 // relevant operands.
8757 --NumOfRelevantElts;
8760 // Check if more than half of the elements require a non-free bitcast.
8761 if (NumOfBitCastedElts <= NumOfRelevantElts / 2)
8764 SelectionDAG &DAG = DCI.DAG;
8765 // Create the new vector type.
8766 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
8767 // Check if the type is legal.
8768 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8769 if (!TLI.isTypeLegal(VecVT))
8773 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
8774 // => BITCAST INSERT_VECTOR_ELT
8775 // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
8777 SDValue Vec = DAG.getUNDEF(VecVT);
8779 for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) {
8780 SDValue V = N->getOperand(Idx);
8781 if (V.getOpcode() == ISD::UNDEF)
8783 if (V.getOpcode() == ISD::BITCAST &&
8784 V->getOperand(0).getValueType() == MVT::i32)
8785 // Fold obvious case.
8786 V = V.getOperand(0);
8788 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
8789 // Make the DAGCombiner fold the bitcasts.
8790 DCI.AddToWorklist(V.getNode());
8792 SDValue LaneIdx = DAG.getConstant(Idx, MVT::i32);
8793 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
8795 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);
8796 // Make the DAGCombiner fold the bitcasts.
8797 DCI.AddToWorklist(Vec.getNode());
8801 /// PerformInsertEltCombine - Target-specific dag combine xforms for
8802 /// ISD::INSERT_VECTOR_ELT.
8803 static SDValue PerformInsertEltCombine(SDNode *N,
8804 TargetLowering::DAGCombinerInfo &DCI) {
8805 // Bitcast an i64 load inserted into a vector to f64.
8806 // Otherwise, the i64 value will be legalized to a pair of i32 values.
8807 EVT VT = N->getValueType(0);
8808 SDNode *Elt = N->getOperand(1).getNode();
8809 if (VT.getVectorElementType() != MVT::i64 ||
8810 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
8813 SelectionDAG &DAG = DCI.DAG;
8815 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8816 VT.getVectorNumElements());
8817 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
8818 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
8819 // Make the DAGCombiner fold the bitcasts.
8820 DCI.AddToWorklist(Vec.getNode());
8821 DCI.AddToWorklist(V.getNode());
8822 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
8823 Vec, V, N->getOperand(2));
8824 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
8827 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
8828 /// ISD::VECTOR_SHUFFLE.
8829 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
8830 // The LLVM shufflevector instruction does not require the shuffle mask
8831 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
8832 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
8833 // operands do not match the mask length, they are extended by concatenating
8834 // them with undef vectors. That is probably the right thing for other
8835 // targets, but for NEON it is better to concatenate two double-register
8836 // size vector operands into a single quad-register size vector. Do that
8837 // transformation here:
8838 // shuffle(concat(v1, undef), concat(v2, undef)) ->
8839 // shuffle(concat(v1, v2), undef)
8840 SDValue Op0 = N->getOperand(0);
8841 SDValue Op1 = N->getOperand(1);
8842 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
8843 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
8844 Op0.getNumOperands() != 2 ||
8845 Op1.getNumOperands() != 2)
8847 SDValue Concat0Op1 = Op0.getOperand(1);
8848 SDValue Concat1Op1 = Op1.getOperand(1);
8849 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
8850 Concat1Op1.getOpcode() != ISD::UNDEF)
8852 // Skip the transformation if any of the types are illegal.
8853 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8854 EVT VT = N->getValueType(0);
8855 if (!TLI.isTypeLegal(VT) ||
8856 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
8857 !TLI.isTypeLegal(Concat1Op1.getValueType()))
8860 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
8861 Op0.getOperand(0), Op1.getOperand(0));
8862 // Translate the shuffle mask.
8863 SmallVector<int, 16> NewMask;
8864 unsigned NumElts = VT.getVectorNumElements();
8865 unsigned HalfElts = NumElts/2;
8866 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8867 for (unsigned n = 0; n < NumElts; ++n) {
8868 int MaskElt = SVN->getMaskElt(n);
8870 if (MaskElt < (int)HalfElts)
8872 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
8873 NewElt = HalfElts + MaskElt - NumElts;
8874 NewMask.push_back(NewElt);
8876 return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
8877 DAG.getUNDEF(VT), NewMask.data());
8880 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP,
8881 /// NEON load/store intrinsics, and generic vector load/stores, to merge
8882 /// base address updates.
8883 /// For generic load/stores, the memory type is assumed to be a vector.
8884 /// The caller is assumed to have checked legality.
8885 static SDValue CombineBaseUpdate(SDNode *N,
8886 TargetLowering::DAGCombinerInfo &DCI) {
8887 SelectionDAG &DAG = DCI.DAG;
8888 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
8889 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
8890 bool isStore = N->getOpcode() == ISD::STORE;
8891 unsigned AddrOpIdx = ((isIntrinsic || isStore) ? 2 : 1);
8892 SDValue Addr = N->getOperand(AddrOpIdx);
8894 // Search for a use of the address operand that is an increment.
8895 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8896 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8898 if (User->getOpcode() != ISD::ADD ||
8899 UI.getUse().getResNo() != Addr.getResNo())
8902 // Check that the add is independent of the load/store. Otherwise, folding
8903 // it would create a cycle.
8904 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8907 // Find the new opcode for the updating load/store.
8909 bool isLaneOp = false;
8910 unsigned NewOpc = 0;
8911 unsigned NumVecs = 0;
8913 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8915 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8916 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
8918 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
8920 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
8922 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
8924 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
8925 NumVecs = 2; isLaneOp = true; break;
8926 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
8927 NumVecs = 3; isLaneOp = true; break;
8928 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
8929 NumVecs = 4; isLaneOp = true; break;
8930 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
8931 NumVecs = 1; isLoad = false; break;
8932 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
8933 NumVecs = 2; isLoad = false; break;
8934 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
8935 NumVecs = 3; isLoad = false; break;
8936 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
8937 NumVecs = 4; isLoad = false; break;
8938 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
8939 NumVecs = 2; isLoad = false; isLaneOp = true; break;
8940 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
8941 NumVecs = 3; isLoad = false; isLaneOp = true; break;
8942 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
8943 NumVecs = 4; isLoad = false; isLaneOp = true; break;
8947 switch (N->getOpcode()) {
8948 default: llvm_unreachable("unexpected opcode for Neon base update");
8949 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
8950 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
8951 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
8952 case ISD::LOAD: NewOpc = ARMISD::VLD1_UPD;
8953 NumVecs = 1; isLaneOp = false; break;
8954 case ISD::STORE: NewOpc = ARMISD::VST1_UPD;
8955 NumVecs = 1; isLoad = false; isLaneOp = false; break;
8959 // Find the size of memory referenced by the load/store.
8962 VecTy = N->getValueType(0);
8963 else if (isIntrinsic)
8964 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
8966 VecTy = N->getOperand(1).getValueType();
8968 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8970 NumBytes /= VecTy.getVectorNumElements();
8972 // If the increment is a constant, it must match the memory ref size.
8973 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8974 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8975 uint64_t IncVal = CInc->getZExtValue();
8976 if (IncVal != NumBytes)
8978 } else if (NumBytes >= 3 * 16) {
8979 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
8980 // separate instructions that make it harder to use a non-constant update.
8984 EVT AlignedVecTy = VecTy;
8986 // If this is a less-than-standard-aligned load/store, change the type to
8987 // match the standard alignment.
8988 // The alignment is overlooked when selecting _UPD variants; and it's
8989 // easier to introduce bitcasts here than fix that.
8990 // There are 3 ways to get to this base-update combine:
8991 // - intrinsics: they are assumed to be properly aligned (to the standard
8992 // alignment of the memory type), so we don't need to do anything.
8993 // - ARMISD::VLDx nodes: they are only generated from the aforementioned
8994 // intrinsics, so, likewise, there's nothing to do.
8995 // - generic load/store instructions: the alignment is specified as an
8996 // explicit operand, rather than implicitly as the standard alignment
8997 // of the memory type (like the intrisics). We need to change the
8998 // memory type to match the explicit alignment. That way, we don't
8999 // generate non-standard-aligned ARMISD::VLDx nodes.
9000 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(N)) {
9001 unsigned Alignment = LSN->getAlignment();
9004 if (Alignment < VecTy.getScalarSizeInBits() / 8) {
9005 MVT EltTy = MVT::getIntegerVT(Alignment * 8);
9006 assert(NumVecs == 1 && "Unexpected multi-element generic load/store.");
9007 assert(!isLaneOp && "Unexpected generic load/store lane.");
9008 unsigned NumElts = NumBytes / (EltTy.getSizeInBits() / 8);
9009 AlignedVecTy = MVT::getVectorVT(EltTy, NumElts);
9013 // Create the new updating load/store node.
9014 // First, create an SDVTList for the new updating node's results.
9016 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
9018 for (n = 0; n < NumResultVecs; ++n)
9019 Tys[n] = AlignedVecTy;
9020 Tys[n++] = MVT::i32;
9021 Tys[n] = MVT::Other;
9022 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2));
9024 // Then, gather the new node's operands.
9025 SmallVector<SDValue, 8> Ops;
9026 Ops.push_back(N->getOperand(0)); // incoming chain
9027 Ops.push_back(N->getOperand(AddrOpIdx));
9029 if (StoreSDNode *StN = dyn_cast<StoreSDNode>(N)) {
9030 // Try to match the intrinsic's signature
9031 Ops.push_back(StN->getValue());
9032 Ops.push_back(DAG.getConstant(StN->getAlignment(), MVT::i32));
9034 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i)
9035 Ops.push_back(N->getOperand(i));
9038 // If this is a non-standard-aligned store, the penultimate operand is the
9039 // stored value. Bitcast it to the aligned type.
9040 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::STORE) {
9041 SDValue &StVal = Ops[Ops.size()-2];
9042 StVal = DAG.getNode(ISD::BITCAST, SDLoc(N), AlignedVecTy, StVal);
9045 MemSDNode *MemInt = cast<MemSDNode>(N);
9046 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
9048 MemInt->getMemOperand());
9051 std::vector<SDValue> NewResults;
9052 for (unsigned i = 0; i < NumResultVecs; ++i) {
9053 NewResults.push_back(SDValue(UpdN.getNode(), i));
9056 // If this is an non-standard-aligned load, the first result is the loaded
9057 // value. Bitcast it to the expected result type.
9058 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::LOAD) {
9059 SDValue &LdVal = NewResults[0];
9060 LdVal = DAG.getNode(ISD::BITCAST, SDLoc(N), VecTy, LdVal);
9063 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
9064 DCI.CombineTo(N, NewResults);
9065 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
9072 static SDValue PerformVLDCombine(SDNode *N,
9073 TargetLowering::DAGCombinerInfo &DCI) {
9074 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9077 return CombineBaseUpdate(N, DCI);
9080 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
9081 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
9082 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
9084 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9085 SelectionDAG &DAG = DCI.DAG;
9086 EVT VT = N->getValueType(0);
9087 // vldN-dup instructions only support 64-bit vectors for N > 1.
9088 if (!VT.is64BitVector())
9091 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
9092 SDNode *VLD = N->getOperand(0).getNode();
9093 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
9095 unsigned NumVecs = 0;
9096 unsigned NewOpc = 0;
9097 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
9098 if (IntNo == Intrinsic::arm_neon_vld2lane) {
9100 NewOpc = ARMISD::VLD2DUP;
9101 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
9103 NewOpc = ARMISD::VLD3DUP;
9104 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
9106 NewOpc = ARMISD::VLD4DUP;
9111 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
9112 // numbers match the load.
9113 unsigned VLDLaneNo =
9114 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
9115 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9117 // Ignore uses of the chain result.
9118 if (UI.getUse().getResNo() == NumVecs)
9121 if (User->getOpcode() != ARMISD::VDUPLANE ||
9122 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
9126 // Create the vldN-dup node.
9129 for (n = 0; n < NumVecs; ++n)
9131 Tys[n] = MVT::Other;
9132 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumVecs+1));
9133 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
9134 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
9135 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
9136 Ops, VLDMemInt->getMemoryVT(),
9137 VLDMemInt->getMemOperand());
9140 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9142 unsigned ResNo = UI.getUse().getResNo();
9143 // Ignore uses of the chain result.
9144 if (ResNo == NumVecs)
9147 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
9150 // Now the vldN-lane intrinsic is dead except for its chain result.
9151 // Update uses of the chain.
9152 std::vector<SDValue> VLDDupResults;
9153 for (unsigned n = 0; n < NumVecs; ++n)
9154 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
9155 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
9156 DCI.CombineTo(VLD, VLDDupResults);
9161 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
9162 /// ARMISD::VDUPLANE.
9163 static SDValue PerformVDUPLANECombine(SDNode *N,
9164 TargetLowering::DAGCombinerInfo &DCI) {
9165 SDValue Op = N->getOperand(0);
9167 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
9168 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
9169 if (CombineVLDDUP(N, DCI))
9170 return SDValue(N, 0);
9172 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
9173 // redundant. Ignore bit_converts for now; element sizes are checked below.
9174 while (Op.getOpcode() == ISD::BITCAST)
9175 Op = Op.getOperand(0);
9176 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
9179 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
9180 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
9181 // The canonical VMOV for a zero vector uses a 32-bit element size.
9182 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9184 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
9186 EVT VT = N->getValueType(0);
9187 if (EltSize > VT.getVectorElementType().getSizeInBits())
9190 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
9193 static SDValue PerformLOADCombine(SDNode *N,
9194 TargetLowering::DAGCombinerInfo &DCI) {
9195 EVT VT = N->getValueType(0);
9197 // If this is a legal vector load, try to combine it into a VLD1_UPD.
9198 if (ISD::isNormalLoad(N) && VT.isVector() &&
9199 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
9200 return CombineBaseUpdate(N, DCI);
9205 /// PerformSTORECombine - Target-specific dag combine xforms for
9207 static SDValue PerformSTORECombine(SDNode *N,
9208 TargetLowering::DAGCombinerInfo &DCI) {
9209 StoreSDNode *St = cast<StoreSDNode>(N);
9210 if (St->isVolatile())
9213 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
9214 // pack all of the elements in one place. Next, store to memory in fewer
9216 SDValue StVal = St->getValue();
9217 EVT VT = StVal.getValueType();
9218 if (St->isTruncatingStore() && VT.isVector()) {
9219 SelectionDAG &DAG = DCI.DAG;
9220 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9221 EVT StVT = St->getMemoryVT();
9222 unsigned NumElems = VT.getVectorNumElements();
9223 assert(StVT != VT && "Cannot truncate to the same type");
9224 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
9225 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
9227 // From, To sizes and ElemCount must be pow of two
9228 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
9230 // We are going to use the original vector elt for storing.
9231 // Accumulated smaller vector elements must be a multiple of the store size.
9232 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
9234 unsigned SizeRatio = FromEltSz / ToEltSz;
9235 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
9237 // Create a type on which we perform the shuffle.
9238 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
9239 NumElems*SizeRatio);
9240 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
9243 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
9244 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
9245 for (unsigned i = 0; i < NumElems; ++i)
9246 ShuffleVec[i] = TLI.isBigEndian() ? (i+1) * SizeRatio - 1 : i * SizeRatio;
9248 // Can't shuffle using an illegal type.
9249 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
9251 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
9252 DAG.getUNDEF(WideVec.getValueType()),
9254 // At this point all of the data is stored at the bottom of the
9255 // register. We now need to save it to mem.
9257 // Find the largest store unit
9258 MVT StoreType = MVT::i8;
9259 for (MVT Tp : MVT::integer_valuetypes()) {
9260 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
9263 // Didn't find a legal store type.
9264 if (!TLI.isTypeLegal(StoreType))
9267 // Bitcast the original vector into a vector of store-size units
9268 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
9269 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
9270 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
9271 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
9272 SmallVector<SDValue, 8> Chains;
9273 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
9274 TLI.getPointerTy());
9275 SDValue BasePtr = St->getBasePtr();
9277 // Perform one or more big stores into memory.
9278 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
9279 for (unsigned I = 0; I < E; I++) {
9280 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
9281 StoreType, ShuffWide,
9282 DAG.getIntPtrConstant(I));
9283 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
9284 St->getPointerInfo(), St->isVolatile(),
9285 St->isNonTemporal(), St->getAlignment());
9286 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
9288 Chains.push_back(Ch);
9290 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
9293 if (!ISD::isNormalStore(St))
9296 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
9297 // ARM stores of arguments in the same cache line.
9298 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
9299 StVal.getNode()->hasOneUse()) {
9300 SelectionDAG &DAG = DCI.DAG;
9301 bool isBigEndian = DAG.getTargetLoweringInfo().isBigEndian();
9303 SDValue BasePtr = St->getBasePtr();
9304 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
9305 StVal.getNode()->getOperand(isBigEndian ? 1 : 0 ),
9306 BasePtr, St->getPointerInfo(), St->isVolatile(),
9307 St->isNonTemporal(), St->getAlignment());
9309 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
9310 DAG.getConstant(4, MVT::i32));
9311 return DAG.getStore(NewST1.getValue(0), DL,
9312 StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
9313 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
9314 St->isNonTemporal(),
9315 std::min(4U, St->getAlignment() / 2));
9318 if (StVal.getValueType() == MVT::i64 &&
9319 StVal.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9321 // Bitcast an i64 store extracted from a vector to f64.
9322 // Otherwise, the i64 value will be legalized to a pair of i32 values.
9323 SelectionDAG &DAG = DCI.DAG;
9325 SDValue IntVec = StVal.getOperand(0);
9326 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
9327 IntVec.getValueType().getVectorNumElements());
9328 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
9329 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
9330 Vec, StVal.getOperand(1));
9332 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
9333 // Make the DAGCombiner fold the bitcasts.
9334 DCI.AddToWorklist(Vec.getNode());
9335 DCI.AddToWorklist(ExtElt.getNode());
9336 DCI.AddToWorklist(V.getNode());
9337 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
9338 St->getPointerInfo(), St->isVolatile(),
9339 St->isNonTemporal(), St->getAlignment(),
9343 // If this is a legal vector store, try to combine it into a VST1_UPD.
9344 if (ISD::isNormalStore(N) && VT.isVector() &&
9345 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
9346 return CombineBaseUpdate(N, DCI);
9351 // isConstVecPow2 - Return true if each vector element is a power of 2, all
9352 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
9353 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
9357 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
9359 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
9364 APFloat APF = C->getValueAPF();
9365 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
9366 != APFloat::opOK || !isExact)
9369 c0 = (I == 0) ? cN : c0;
9370 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
9377 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
9378 /// can replace combinations of VMUL and VCVT (floating-point to integer)
9379 /// when the VMUL has a constant operand that is a power of 2.
9381 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9382 /// vmul.f32 d16, d17, d16
9383 /// vcvt.s32.f32 d16, d16
9385 /// vcvt.s32.f32 d16, d16, #3
9386 static SDValue PerformVCVTCombine(SDNode *N,
9387 TargetLowering::DAGCombinerInfo &DCI,
9388 const ARMSubtarget *Subtarget) {
9389 SelectionDAG &DAG = DCI.DAG;
9390 SDValue Op = N->getOperand(0);
9392 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
9393 Op.getOpcode() != ISD::FMUL)
9397 SDValue N0 = Op->getOperand(0);
9398 SDValue ConstVec = Op->getOperand(1);
9399 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
9401 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9402 !isConstVecPow2(ConstVec, isSigned, C))
9405 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
9406 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
9407 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9408 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32 ||
9410 // These instructions only exist converting from f32 to i32. We can handle
9411 // smaller integers by generating an extra truncate, but larger ones would
9412 // be lossy. We also can't handle more then 4 lanes, since these intructions
9413 // only support v2i32/v4i32 types.
9417 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
9418 Intrinsic::arm_neon_vcvtfp2fxu;
9419 SDValue FixConv = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
9420 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9421 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
9422 DAG.getConstant(Log2_64(C), MVT::i32));
9424 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9425 FixConv = DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), FixConv);
9430 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
9431 /// can replace combinations of VCVT (integer to floating-point) and VDIV
9432 /// when the VDIV has a constant operand that is a power of 2.
9434 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9435 /// vcvt.f32.s32 d16, d16
9436 /// vdiv.f32 d16, d17, d16
9438 /// vcvt.f32.s32 d16, d16, #3
9439 static SDValue PerformVDIVCombine(SDNode *N,
9440 TargetLowering::DAGCombinerInfo &DCI,
9441 const ARMSubtarget *Subtarget) {
9442 SelectionDAG &DAG = DCI.DAG;
9443 SDValue Op = N->getOperand(0);
9444 unsigned OpOpcode = Op.getNode()->getOpcode();
9446 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
9447 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
9451 SDValue ConstVec = N->getOperand(1);
9452 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
9454 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9455 !isConstVecPow2(ConstVec, isSigned, C))
9458 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
9459 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
9460 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9461 // These instructions only exist converting from i32 to f32. We can handle
9462 // smaller integers by generating an extra extend, but larger ones would
9467 SDValue ConvInput = Op.getOperand(0);
9468 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9469 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9470 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
9471 SDLoc(N), NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9474 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
9475 Intrinsic::arm_neon_vcvtfxu2fp;
9476 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
9478 DAG.getConstant(IntrinsicOpcode, MVT::i32),
9479 ConvInput, DAG.getConstant(Log2_64(C), MVT::i32));
9482 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
9483 /// operand of a vector shift operation, where all the elements of the
9484 /// build_vector must have the same constant integer value.
9485 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
9486 // Ignore bit_converts.
9487 while (Op.getOpcode() == ISD::BITCAST)
9488 Op = Op.getOperand(0);
9489 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
9490 APInt SplatBits, SplatUndef;
9491 unsigned SplatBitSize;
9493 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
9494 HasAnyUndefs, ElementBits) ||
9495 SplatBitSize > ElementBits)
9497 Cnt = SplatBits.getSExtValue();
9501 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
9502 /// operand of a vector shift left operation. That value must be in the range:
9503 /// 0 <= Value < ElementBits for a left shift; or
9504 /// 0 <= Value <= ElementBits for a long left shift.
9505 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
9506 assert(VT.isVector() && "vector shift count is not a vector type");
9507 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9508 if (! getVShiftImm(Op, ElementBits, Cnt))
9510 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
9513 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
9514 /// operand of a vector shift right operation. For a shift opcode, the value
9515 /// is positive, but for an intrinsic the value count must be negative. The
9516 /// absolute value must be in the range:
9517 /// 1 <= |Value| <= ElementBits for a right shift; or
9518 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
9519 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
9521 assert(VT.isVector() && "vector shift count is not a vector type");
9522 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9523 if (! getVShiftImm(Op, ElementBits, Cnt))
9527 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
9530 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
9531 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
9532 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
9535 // Don't do anything for most intrinsics.
9538 // Vector shifts: check for immediate versions and lower them.
9539 // Note: This is done during DAG combining instead of DAG legalizing because
9540 // the build_vectors for 64-bit vector element shift counts are generally
9541 // not legal, and it is hard to see their values after they get legalized to
9542 // loads from a constant pool.
9543 case Intrinsic::arm_neon_vshifts:
9544 case Intrinsic::arm_neon_vshiftu:
9545 case Intrinsic::arm_neon_vrshifts:
9546 case Intrinsic::arm_neon_vrshiftu:
9547 case Intrinsic::arm_neon_vrshiftn:
9548 case Intrinsic::arm_neon_vqshifts:
9549 case Intrinsic::arm_neon_vqshiftu:
9550 case Intrinsic::arm_neon_vqshiftsu:
9551 case Intrinsic::arm_neon_vqshiftns:
9552 case Intrinsic::arm_neon_vqshiftnu:
9553 case Intrinsic::arm_neon_vqshiftnsu:
9554 case Intrinsic::arm_neon_vqrshiftns:
9555 case Intrinsic::arm_neon_vqrshiftnu:
9556 case Intrinsic::arm_neon_vqrshiftnsu: {
9557 EVT VT = N->getOperand(1).getValueType();
9559 unsigned VShiftOpc = 0;
9562 case Intrinsic::arm_neon_vshifts:
9563 case Intrinsic::arm_neon_vshiftu:
9564 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
9565 VShiftOpc = ARMISD::VSHL;
9568 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
9569 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
9570 ARMISD::VSHRs : ARMISD::VSHRu);
9575 case Intrinsic::arm_neon_vrshifts:
9576 case Intrinsic::arm_neon_vrshiftu:
9577 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
9581 case Intrinsic::arm_neon_vqshifts:
9582 case Intrinsic::arm_neon_vqshiftu:
9583 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9587 case Intrinsic::arm_neon_vqshiftsu:
9588 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9590 llvm_unreachable("invalid shift count for vqshlu intrinsic");
9592 case Intrinsic::arm_neon_vrshiftn:
9593 case Intrinsic::arm_neon_vqshiftns:
9594 case Intrinsic::arm_neon_vqshiftnu:
9595 case Intrinsic::arm_neon_vqshiftnsu:
9596 case Intrinsic::arm_neon_vqrshiftns:
9597 case Intrinsic::arm_neon_vqrshiftnu:
9598 case Intrinsic::arm_neon_vqrshiftnsu:
9599 // Narrowing shifts require an immediate right shift.
9600 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
9602 llvm_unreachable("invalid shift count for narrowing vector shift "
9606 llvm_unreachable("unhandled vector shift");
9610 case Intrinsic::arm_neon_vshifts:
9611 case Intrinsic::arm_neon_vshiftu:
9612 // Opcode already set above.
9614 case Intrinsic::arm_neon_vrshifts:
9615 VShiftOpc = ARMISD::VRSHRs; break;
9616 case Intrinsic::arm_neon_vrshiftu:
9617 VShiftOpc = ARMISD::VRSHRu; break;
9618 case Intrinsic::arm_neon_vrshiftn:
9619 VShiftOpc = ARMISD::VRSHRN; break;
9620 case Intrinsic::arm_neon_vqshifts:
9621 VShiftOpc = ARMISD::VQSHLs; break;
9622 case Intrinsic::arm_neon_vqshiftu:
9623 VShiftOpc = ARMISD::VQSHLu; break;
9624 case Intrinsic::arm_neon_vqshiftsu:
9625 VShiftOpc = ARMISD::VQSHLsu; break;
9626 case Intrinsic::arm_neon_vqshiftns:
9627 VShiftOpc = ARMISD::VQSHRNs; break;
9628 case Intrinsic::arm_neon_vqshiftnu:
9629 VShiftOpc = ARMISD::VQSHRNu; break;
9630 case Intrinsic::arm_neon_vqshiftnsu:
9631 VShiftOpc = ARMISD::VQSHRNsu; break;
9632 case Intrinsic::arm_neon_vqrshiftns:
9633 VShiftOpc = ARMISD::VQRSHRNs; break;
9634 case Intrinsic::arm_neon_vqrshiftnu:
9635 VShiftOpc = ARMISD::VQRSHRNu; break;
9636 case Intrinsic::arm_neon_vqrshiftnsu:
9637 VShiftOpc = ARMISD::VQRSHRNsu; break;
9640 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
9641 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
9644 case Intrinsic::arm_neon_vshiftins: {
9645 EVT VT = N->getOperand(1).getValueType();
9647 unsigned VShiftOpc = 0;
9649 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
9650 VShiftOpc = ARMISD::VSLI;
9651 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
9652 VShiftOpc = ARMISD::VSRI;
9654 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
9657 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
9658 N->getOperand(1), N->getOperand(2),
9659 DAG.getConstant(Cnt, MVT::i32));
9662 case Intrinsic::arm_neon_vqrshifts:
9663 case Intrinsic::arm_neon_vqrshiftu:
9664 // No immediate versions of these to check for.
9671 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
9672 /// lowers them. As with the vector shift intrinsics, this is done during DAG
9673 /// combining instead of DAG legalizing because the build_vectors for 64-bit
9674 /// vector element shift counts are generally not legal, and it is hard to see
9675 /// their values after they get legalized to loads from a constant pool.
9676 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
9677 const ARMSubtarget *ST) {
9678 EVT VT = N->getValueType(0);
9679 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9680 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
9681 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
9682 SDValue N1 = N->getOperand(1);
9683 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
9684 SDValue N0 = N->getOperand(0);
9685 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9686 DAG.MaskedValueIsZero(N0.getOperand(0),
9687 APInt::getHighBitsSet(32, 16)))
9688 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
9692 // Nothing to be done for scalar shifts.
9693 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9694 if (!VT.isVector() || !TLI.isTypeLegal(VT))
9697 assert(ST->hasNEON() && "unexpected vector shift");
9700 switch (N->getOpcode()) {
9701 default: llvm_unreachable("unexpected shift opcode");
9704 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
9705 return DAG.getNode(ARMISD::VSHL, SDLoc(N), VT, N->getOperand(0),
9706 DAG.getConstant(Cnt, MVT::i32));
9711 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
9712 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
9713 ARMISD::VSHRs : ARMISD::VSHRu);
9714 return DAG.getNode(VShiftOpc, SDLoc(N), VT, N->getOperand(0),
9715 DAG.getConstant(Cnt, MVT::i32));
9721 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
9722 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
9723 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
9724 const ARMSubtarget *ST) {
9725 SDValue N0 = N->getOperand(0);
9727 // Check for sign- and zero-extensions of vector extract operations of 8-
9728 // and 16-bit vector elements. NEON supports these directly. They are
9729 // handled during DAG combining because type legalization will promote them
9730 // to 32-bit types and it is messy to recognize the operations after that.
9731 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9732 SDValue Vec = N0.getOperand(0);
9733 SDValue Lane = N0.getOperand(1);
9734 EVT VT = N->getValueType(0);
9735 EVT EltVT = N0.getValueType();
9736 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9738 if (VT == MVT::i32 &&
9739 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
9740 TLI.isTypeLegal(Vec.getValueType()) &&
9741 isa<ConstantSDNode>(Lane)) {
9744 switch (N->getOpcode()) {
9745 default: llvm_unreachable("unexpected opcode");
9746 case ISD::SIGN_EXTEND:
9747 Opc = ARMISD::VGETLANEs;
9749 case ISD::ZERO_EXTEND:
9750 case ISD::ANY_EXTEND:
9751 Opc = ARMISD::VGETLANEu;
9754 return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);
9761 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
9762 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
9763 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
9764 const ARMSubtarget *ST) {
9765 // If the target supports NEON, try to use vmax/vmin instructions for f32
9766 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
9767 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
9768 // a NaN; only do the transformation when it matches that behavior.
9770 // For now only do this when using NEON for FP operations; if using VFP, it
9771 // is not obvious that the benefit outweighs the cost of switching to the
9773 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
9774 N->getValueType(0) != MVT::f32)
9777 SDValue CondLHS = N->getOperand(0);
9778 SDValue CondRHS = N->getOperand(1);
9779 SDValue LHS = N->getOperand(2);
9780 SDValue RHS = N->getOperand(3);
9781 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9783 unsigned Opcode = 0;
9785 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
9786 IsReversed = false; // x CC y ? x : y
9787 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
9788 IsReversed = true ; // x CC y ? y : x
9802 // If LHS is NaN, an ordered comparison will be false and the result will
9803 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
9804 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9805 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
9806 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9808 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
9809 // will return -0, so vmin can only be used for unsafe math or if one of
9810 // the operands is known to be nonzero.
9811 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
9812 !DAG.getTarget().Options.UnsafeFPMath &&
9813 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9815 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
9824 // If LHS is NaN, an ordered comparison will be false and the result will
9825 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
9826 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9827 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
9828 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9830 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
9831 // will return +0, so vmax can only be used for unsafe math or if one of
9832 // the operands is known to be nonzero.
9833 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
9834 !DAG.getTarget().Options.UnsafeFPMath &&
9835 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9837 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
9843 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
9846 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
9848 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
9849 SDValue Cmp = N->getOperand(4);
9850 if (Cmp.getOpcode() != ARMISD::CMPZ)
9851 // Only looking at EQ and NE cases.
9854 EVT VT = N->getValueType(0);
9856 SDValue LHS = Cmp.getOperand(0);
9857 SDValue RHS = Cmp.getOperand(1);
9858 SDValue FalseVal = N->getOperand(0);
9859 SDValue TrueVal = N->getOperand(1);
9860 SDValue ARMcc = N->getOperand(2);
9861 ARMCC::CondCodes CC =
9862 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
9880 /// FIXME: Turn this into a target neutral optimization?
9882 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
9883 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
9884 N->getOperand(3), Cmp);
9885 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
9887 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
9888 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
9889 N->getOperand(3), NewCmp);
9892 if (Res.getNode()) {
9893 APInt KnownZero, KnownOne;
9894 DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
9895 // Capture demanded bits information that would be otherwise lost.
9896 if (KnownZero == 0xfffffffe)
9897 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9898 DAG.getValueType(MVT::i1));
9899 else if (KnownZero == 0xffffff00)
9900 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9901 DAG.getValueType(MVT::i8));
9902 else if (KnownZero == 0xffff0000)
9903 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9904 DAG.getValueType(MVT::i16));
9910 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
9911 DAGCombinerInfo &DCI) const {
9912 switch (N->getOpcode()) {
9914 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
9915 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
9916 case ISD::SUB: return PerformSUBCombine(N, DCI);
9917 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
9918 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
9919 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
9920 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
9921 case ARMISD::BFI: return PerformBFICombine(N, DCI);
9922 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
9923 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
9924 case ISD::STORE: return PerformSTORECombine(N, DCI);
9925 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
9926 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
9927 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
9928 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
9929 case ISD::FP_TO_SINT:
9930 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
9931 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
9932 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
9935 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
9936 case ISD::SIGN_EXTEND:
9937 case ISD::ZERO_EXTEND:
9938 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
9939 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
9940 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
9941 case ISD::LOAD: return PerformLOADCombine(N, DCI);
9942 case ARMISD::VLD2DUP:
9943 case ARMISD::VLD3DUP:
9944 case ARMISD::VLD4DUP:
9945 return PerformVLDCombine(N, DCI);
9946 case ARMISD::BUILD_VECTOR:
9947 return PerformARMBUILD_VECTORCombine(N, DCI);
9948 case ISD::INTRINSIC_VOID:
9949 case ISD::INTRINSIC_W_CHAIN:
9950 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9951 case Intrinsic::arm_neon_vld1:
9952 case Intrinsic::arm_neon_vld2:
9953 case Intrinsic::arm_neon_vld3:
9954 case Intrinsic::arm_neon_vld4:
9955 case Intrinsic::arm_neon_vld2lane:
9956 case Intrinsic::arm_neon_vld3lane:
9957 case Intrinsic::arm_neon_vld4lane:
9958 case Intrinsic::arm_neon_vst1:
9959 case Intrinsic::arm_neon_vst2:
9960 case Intrinsic::arm_neon_vst3:
9961 case Intrinsic::arm_neon_vst4:
9962 case Intrinsic::arm_neon_vst2lane:
9963 case Intrinsic::arm_neon_vst3lane:
9964 case Intrinsic::arm_neon_vst4lane:
9965 return PerformVLDCombine(N, DCI);
9973 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
9975 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
9978 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9982 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
9983 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
9985 switch (VT.getSimpleVT().SimpleTy) {
9991 // Unaligned access can use (for example) LRDB, LRDH, LDR
9992 if (AllowsUnaligned) {
9994 *Fast = Subtarget->hasV7Ops();
10001 // For any little-endian targets with neon, we can support unaligned ld/st
10002 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
10003 // A big-endian target may also explicitly support unaligned accesses
10004 if (Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian())) {
10014 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
10015 unsigned AlignCheck) {
10016 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
10017 (DstAlign == 0 || DstAlign % AlignCheck == 0));
10020 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
10021 unsigned DstAlign, unsigned SrcAlign,
10022 bool IsMemset, bool ZeroMemset,
10024 MachineFunction &MF) const {
10025 const Function *F = MF.getFunction();
10027 // See if we can use NEON instructions for this...
10028 if ((!IsMemset || ZeroMemset) &&
10029 Subtarget->hasNEON() &&
10030 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
10031 Attribute::NoImplicitFloat)) {
10034 (memOpAlign(SrcAlign, DstAlign, 16) ||
10035 (allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1, &Fast) && Fast))) {
10037 } else if (Size >= 8 &&
10038 (memOpAlign(SrcAlign, DstAlign, 8) ||
10039 (allowsMisalignedMemoryAccesses(MVT::f64, 0, 1, &Fast) &&
10045 // Lowering to i32/i16 if the size permits.
10048 else if (Size >= 2)
10051 // Let the target-independent logic figure it out.
10055 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
10056 if (Val.getOpcode() != ISD::LOAD)
10059 EVT VT1 = Val.getValueType();
10060 if (!VT1.isSimple() || !VT1.isInteger() ||
10061 !VT2.isSimple() || !VT2.isInteger())
10064 switch (VT1.getSimpleVT().SimpleTy) {
10069 // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
10076 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
10077 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10080 if (!isTypeLegal(EVT::getEVT(Ty1)))
10083 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
10085 // Assuming the caller doesn't have a zeroext or signext return parameter,
10086 // truncation all the way down to i1 is valid.
10091 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
10095 unsigned Scale = 1;
10096 switch (VT.getSimpleVT().SimpleTy) {
10097 default: return false;
10112 if ((V & (Scale - 1)) != 0)
10115 return V == (V & ((1LL << 5) - 1));
10118 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
10119 const ARMSubtarget *Subtarget) {
10120 bool isNeg = false;
10126 switch (VT.getSimpleVT().SimpleTy) {
10127 default: return false;
10132 // + imm12 or - imm8
10134 return V == (V & ((1LL << 8) - 1));
10135 return V == (V & ((1LL << 12) - 1));
10138 // Same as ARM mode. FIXME: NEON?
10139 if (!Subtarget->hasVFP2())
10144 return V == (V & ((1LL << 8) - 1));
10148 /// isLegalAddressImmediate - Return true if the integer value can be used
10149 /// as the offset of the target addressing mode for load / store of the
10151 static bool isLegalAddressImmediate(int64_t V, EVT VT,
10152 const ARMSubtarget *Subtarget) {
10156 if (!VT.isSimple())
10159 if (Subtarget->isThumb1Only())
10160 return isLegalT1AddressImmediate(V, VT);
10161 else if (Subtarget->isThumb2())
10162 return isLegalT2AddressImmediate(V, VT, Subtarget);
10167 switch (VT.getSimpleVT().SimpleTy) {
10168 default: return false;
10173 return V == (V & ((1LL << 12) - 1));
10176 return V == (V & ((1LL << 8) - 1));
10179 if (!Subtarget->hasVFP2()) // FIXME: NEON?
10184 return V == (V & ((1LL << 8) - 1));
10188 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
10190 int Scale = AM.Scale;
10194 switch (VT.getSimpleVT().SimpleTy) {
10195 default: return false;
10203 Scale = Scale & ~1;
10204 return Scale == 2 || Scale == 4 || Scale == 8;
10207 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10211 // Note, we allow "void" uses (basically, uses that aren't loads or
10212 // stores), because arm allows folding a scale into many arithmetic
10213 // operations. This should be made more precise and revisited later.
10215 // Allow r << imm, but the imm has to be a multiple of two.
10216 if (Scale & 1) return false;
10217 return isPowerOf2_32(Scale);
10221 /// isLegalAddressingMode - Return true if the addressing mode represented
10222 /// by AM is legal for this target, for a load/store of the specified type.
10223 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
10225 EVT VT = getValueType(Ty, true);
10226 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
10229 // Can never fold addr of global into load/store.
10233 switch (AM.Scale) {
10234 case 0: // no scale reg, must be "r+i" or "r", or "i".
10237 if (Subtarget->isThumb1Only())
10241 // ARM doesn't support any R+R*scale+imm addr modes.
10245 if (!VT.isSimple())
10248 if (Subtarget->isThumb2())
10249 return isLegalT2ScaledAddressingMode(AM, VT);
10251 int Scale = AM.Scale;
10252 switch (VT.getSimpleVT().SimpleTy) {
10253 default: return false;
10257 if (Scale < 0) Scale = -Scale;
10261 return isPowerOf2_32(Scale & ~1);
10265 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10270 // Note, we allow "void" uses (basically, uses that aren't loads or
10271 // stores), because arm allows folding a scale into many arithmetic
10272 // operations. This should be made more precise and revisited later.
10274 // Allow r << imm, but the imm has to be a multiple of two.
10275 if (Scale & 1) return false;
10276 return isPowerOf2_32(Scale);
10282 /// isLegalICmpImmediate - Return true if the specified immediate is legal
10283 /// icmp immediate, that is the target has icmp instructions which can compare
10284 /// a register against the immediate without having to materialize the
10285 /// immediate into a register.
10286 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
10287 // Thumb2 and ARM modes can use cmn for negative immediates.
10288 if (!Subtarget->isThumb())
10289 return ARM_AM::getSOImmVal(llvm::abs64(Imm)) != -1;
10290 if (Subtarget->isThumb2())
10291 return ARM_AM::getT2SOImmVal(llvm::abs64(Imm)) != -1;
10292 // Thumb1 doesn't have cmn, and only 8-bit immediates.
10293 return Imm >= 0 && Imm <= 255;
10296 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
10297 /// *or sub* immediate, that is the target has add or sub instructions which can
10298 /// add a register with the immediate without having to materialize the
10299 /// immediate into a register.
10300 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
10301 // Same encoding for add/sub, just flip the sign.
10302 int64_t AbsImm = llvm::abs64(Imm);
10303 if (!Subtarget->isThumb())
10304 return ARM_AM::getSOImmVal(AbsImm) != -1;
10305 if (Subtarget->isThumb2())
10306 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
10307 // Thumb1 only has 8-bit unsigned immediate.
10308 return AbsImm >= 0 && AbsImm <= 255;
10311 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
10312 bool isSEXTLoad, SDValue &Base,
10313 SDValue &Offset, bool &isInc,
10314 SelectionDAG &DAG) {
10315 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10318 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
10319 // AddressingMode 3
10320 Base = Ptr->getOperand(0);
10321 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10322 int RHSC = (int)RHS->getZExtValue();
10323 if (RHSC < 0 && RHSC > -256) {
10324 assert(Ptr->getOpcode() == ISD::ADD);
10326 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10330 isInc = (Ptr->getOpcode() == ISD::ADD);
10331 Offset = Ptr->getOperand(1);
10333 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
10334 // AddressingMode 2
10335 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10336 int RHSC = (int)RHS->getZExtValue();
10337 if (RHSC < 0 && RHSC > -0x1000) {
10338 assert(Ptr->getOpcode() == ISD::ADD);
10340 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10341 Base = Ptr->getOperand(0);
10346 if (Ptr->getOpcode() == ISD::ADD) {
10348 ARM_AM::ShiftOpc ShOpcVal=
10349 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
10350 if (ShOpcVal != ARM_AM::no_shift) {
10351 Base = Ptr->getOperand(1);
10352 Offset = Ptr->getOperand(0);
10354 Base = Ptr->getOperand(0);
10355 Offset = Ptr->getOperand(1);
10360 isInc = (Ptr->getOpcode() == ISD::ADD);
10361 Base = Ptr->getOperand(0);
10362 Offset = Ptr->getOperand(1);
10366 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
10370 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
10371 bool isSEXTLoad, SDValue &Base,
10372 SDValue &Offset, bool &isInc,
10373 SelectionDAG &DAG) {
10374 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10377 Base = Ptr->getOperand(0);
10378 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10379 int RHSC = (int)RHS->getZExtValue();
10380 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
10381 assert(Ptr->getOpcode() == ISD::ADD);
10383 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10385 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
10386 isInc = Ptr->getOpcode() == ISD::ADD;
10387 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
10395 /// getPreIndexedAddressParts - returns true by value, base pointer and
10396 /// offset pointer and addressing mode by reference if the node's address
10397 /// can be legally represented as pre-indexed load / store address.
10399 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
10401 ISD::MemIndexedMode &AM,
10402 SelectionDAG &DAG) const {
10403 if (Subtarget->isThumb1Only())
10408 bool isSEXTLoad = false;
10409 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10410 Ptr = LD->getBasePtr();
10411 VT = LD->getMemoryVT();
10412 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10413 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10414 Ptr = ST->getBasePtr();
10415 VT = ST->getMemoryVT();
10420 bool isLegal = false;
10421 if (Subtarget->isThumb2())
10422 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10423 Offset, isInc, DAG);
10425 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10426 Offset, isInc, DAG);
10430 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
10434 /// getPostIndexedAddressParts - returns true by value, base pointer and
10435 /// offset pointer and addressing mode by reference if this node can be
10436 /// combined with a load / store to form a post-indexed load / store.
10437 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
10440 ISD::MemIndexedMode &AM,
10441 SelectionDAG &DAG) const {
10442 if (Subtarget->isThumb1Only())
10447 bool isSEXTLoad = false;
10448 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10449 VT = LD->getMemoryVT();
10450 Ptr = LD->getBasePtr();
10451 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10452 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10453 VT = ST->getMemoryVT();
10454 Ptr = ST->getBasePtr();
10459 bool isLegal = false;
10460 if (Subtarget->isThumb2())
10461 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10464 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10470 // Swap base ptr and offset to catch more post-index load / store when
10471 // it's legal. In Thumb2 mode, offset must be an immediate.
10472 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
10473 !Subtarget->isThumb2())
10474 std::swap(Base, Offset);
10476 // Post-indexed load / store update the base pointer.
10481 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
10485 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10488 const SelectionDAG &DAG,
10489 unsigned Depth) const {
10490 unsigned BitWidth = KnownOne.getBitWidth();
10491 KnownZero = KnownOne = APInt(BitWidth, 0);
10492 switch (Op.getOpcode()) {
10498 // These nodes' second result is a boolean
10499 if (Op.getResNo() == 0)
10501 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
10503 case ARMISD::CMOV: {
10504 // Bits are known zero/one if known on the LHS and RHS.
10505 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
10506 if (KnownZero == 0 && KnownOne == 0) return;
10508 APInt KnownZeroRHS, KnownOneRHS;
10509 DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
10510 KnownZero &= KnownZeroRHS;
10511 KnownOne &= KnownOneRHS;
10514 case ISD::INTRINSIC_W_CHAIN: {
10515 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
10516 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
10519 case Intrinsic::arm_ldaex:
10520 case Intrinsic::arm_ldrex: {
10521 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
10522 unsigned MemBits = VT.getScalarType().getSizeInBits();
10523 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
10531 //===----------------------------------------------------------------------===//
10532 // ARM Inline Assembly Support
10533 //===----------------------------------------------------------------------===//
10535 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
10536 // Looking for "rev" which is V6+.
10537 if (!Subtarget->hasV6Ops())
10540 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10541 std::string AsmStr = IA->getAsmString();
10542 SmallVector<StringRef, 4> AsmPieces;
10543 SplitString(AsmStr, AsmPieces, ";\n");
10545 switch (AsmPieces.size()) {
10546 default: return false;
10548 AsmStr = AsmPieces[0];
10550 SplitString(AsmStr, AsmPieces, " \t,");
10553 if (AsmPieces.size() == 3 &&
10554 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
10555 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
10556 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10557 if (Ty && Ty->getBitWidth() == 32)
10558 return IntrinsicLowering::LowerToByteSwap(CI);
10566 /// getConstraintType - Given a constraint letter, return the type of
10567 /// constraint it is for this target.
10568 ARMTargetLowering::ConstraintType
10569 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
10570 if (Constraint.size() == 1) {
10571 switch (Constraint[0]) {
10573 case 'l': return C_RegisterClass;
10574 case 'w': return C_RegisterClass;
10575 case 'h': return C_RegisterClass;
10576 case 'x': return C_RegisterClass;
10577 case 't': return C_RegisterClass;
10578 case 'j': return C_Other; // Constant for movw.
10579 // An address with a single base register. Due to the way we
10580 // currently handle addresses it is the same as an 'r' memory constraint.
10581 case 'Q': return C_Memory;
10583 } else if (Constraint.size() == 2) {
10584 switch (Constraint[0]) {
10586 // All 'U+' constraints are addresses.
10587 case 'U': return C_Memory;
10590 return TargetLowering::getConstraintType(Constraint);
10593 /// Examine constraint type and operand type and determine a weight value.
10594 /// This object must already have been set up with the operand type
10595 /// and the current alternative constraint selected.
10596 TargetLowering::ConstraintWeight
10597 ARMTargetLowering::getSingleConstraintMatchWeight(
10598 AsmOperandInfo &info, const char *constraint) const {
10599 ConstraintWeight weight = CW_Invalid;
10600 Value *CallOperandVal = info.CallOperandVal;
10601 // If we don't have a value, we can't do a match,
10602 // but allow it at the lowest weight.
10603 if (!CallOperandVal)
10605 Type *type = CallOperandVal->getType();
10606 // Look at the constraint type.
10607 switch (*constraint) {
10609 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10612 if (type->isIntegerTy()) {
10613 if (Subtarget->isThumb())
10614 weight = CW_SpecificReg;
10616 weight = CW_Register;
10620 if (type->isFloatingPointTy())
10621 weight = CW_Register;
10627 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
10629 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10631 if (Constraint.size() == 1) {
10632 // GCC ARM Constraint Letters
10633 switch (Constraint[0]) {
10634 case 'l': // Low regs or general regs.
10635 if (Subtarget->isThumb())
10636 return RCPair(0U, &ARM::tGPRRegClass);
10637 return RCPair(0U, &ARM::GPRRegClass);
10638 case 'h': // High regs or no regs.
10639 if (Subtarget->isThumb())
10640 return RCPair(0U, &ARM::hGPRRegClass);
10643 if (Subtarget->isThumb1Only())
10644 return RCPair(0U, &ARM::tGPRRegClass);
10645 return RCPair(0U, &ARM::GPRRegClass);
10647 if (VT == MVT::Other)
10649 if (VT == MVT::f32)
10650 return RCPair(0U, &ARM::SPRRegClass);
10651 if (VT.getSizeInBits() == 64)
10652 return RCPair(0U, &ARM::DPRRegClass);
10653 if (VT.getSizeInBits() == 128)
10654 return RCPair(0U, &ARM::QPRRegClass);
10657 if (VT == MVT::Other)
10659 if (VT == MVT::f32)
10660 return RCPair(0U, &ARM::SPR_8RegClass);
10661 if (VT.getSizeInBits() == 64)
10662 return RCPair(0U, &ARM::DPR_8RegClass);
10663 if (VT.getSizeInBits() == 128)
10664 return RCPair(0U, &ARM::QPR_8RegClass);
10667 if (VT == MVT::f32)
10668 return RCPair(0U, &ARM::SPRRegClass);
10672 if (StringRef("{cc}").equals_lower(Constraint))
10673 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
10675 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10678 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10679 /// vector. If it is invalid, don't add anything to Ops.
10680 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10681 std::string &Constraint,
10682 std::vector<SDValue>&Ops,
10683 SelectionDAG &DAG) const {
10686 // Currently only support length 1 constraints.
10687 if (Constraint.length() != 1) return;
10689 char ConstraintLetter = Constraint[0];
10690 switch (ConstraintLetter) {
10693 case 'I': case 'J': case 'K': case 'L':
10694 case 'M': case 'N': case 'O':
10695 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
10699 int64_t CVal64 = C->getSExtValue();
10700 int CVal = (int) CVal64;
10701 // None of these constraints allow values larger than 32 bits. Check
10702 // that the value fits in an int.
10703 if (CVal != CVal64)
10706 switch (ConstraintLetter) {
10708 // Constant suitable for movw, must be between 0 and
10710 if (Subtarget->hasV6T2Ops())
10711 if (CVal >= 0 && CVal <= 65535)
10715 if (Subtarget->isThumb1Only()) {
10716 // This must be a constant between 0 and 255, for ADD
10718 if (CVal >= 0 && CVal <= 255)
10720 } else if (Subtarget->isThumb2()) {
10721 // A constant that can be used as an immediate value in a
10722 // data-processing instruction.
10723 if (ARM_AM::getT2SOImmVal(CVal) != -1)
10726 // A constant that can be used as an immediate value in a
10727 // data-processing instruction.
10728 if (ARM_AM::getSOImmVal(CVal) != -1)
10734 if (Subtarget->isThumb()) { // FIXME thumb2
10735 // This must be a constant between -255 and -1, for negated ADD
10736 // immediates. This can be used in GCC with an "n" modifier that
10737 // prints the negated value, for use with SUB instructions. It is
10738 // not useful otherwise but is implemented for compatibility.
10739 if (CVal >= -255 && CVal <= -1)
10742 // This must be a constant between -4095 and 4095. It is not clear
10743 // what this constraint is intended for. Implemented for
10744 // compatibility with GCC.
10745 if (CVal >= -4095 && CVal <= 4095)
10751 if (Subtarget->isThumb1Only()) {
10752 // A 32-bit value where only one byte has a nonzero value. Exclude
10753 // zero to match GCC. This constraint is used by GCC internally for
10754 // constants that can be loaded with a move/shift combination.
10755 // It is not useful otherwise but is implemented for compatibility.
10756 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
10758 } else if (Subtarget->isThumb2()) {
10759 // A constant whose bitwise inverse can be used as an immediate
10760 // value in a data-processing instruction. This can be used in GCC
10761 // with a "B" modifier that prints the inverted value, for use with
10762 // BIC and MVN instructions. It is not useful otherwise but is
10763 // implemented for compatibility.
10764 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
10767 // A constant whose bitwise inverse can be used as an immediate
10768 // value in a data-processing instruction. This can be used in GCC
10769 // with a "B" modifier that prints the inverted value, for use with
10770 // BIC and MVN instructions. It is not useful otherwise but is
10771 // implemented for compatibility.
10772 if (ARM_AM::getSOImmVal(~CVal) != -1)
10778 if (Subtarget->isThumb1Only()) {
10779 // This must be a constant between -7 and 7,
10780 // for 3-operand ADD/SUB immediate instructions.
10781 if (CVal >= -7 && CVal < 7)
10783 } else if (Subtarget->isThumb2()) {
10784 // A constant whose negation can be used as an immediate value in a
10785 // data-processing instruction. This can be used in GCC with an "n"
10786 // modifier that prints the negated value, for use with SUB
10787 // instructions. It is not useful otherwise but is implemented for
10789 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
10792 // A constant whose negation can be used as an immediate value in a
10793 // data-processing instruction. This can be used in GCC with an "n"
10794 // modifier that prints the negated value, for use with SUB
10795 // instructions. It is not useful otherwise but is implemented for
10797 if (ARM_AM::getSOImmVal(-CVal) != -1)
10803 if (Subtarget->isThumb()) { // FIXME thumb2
10804 // This must be a multiple of 4 between 0 and 1020, for
10805 // ADD sp + immediate.
10806 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
10809 // A power of two or a constant between 0 and 32. This is used in
10810 // GCC for the shift amount on shifted register operands, but it is
10811 // useful in general for any shift amounts.
10812 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
10818 if (Subtarget->isThumb()) { // FIXME thumb2
10819 // This must be a constant between 0 and 31, for shift amounts.
10820 if (CVal >= 0 && CVal <= 31)
10826 if (Subtarget->isThumb()) { // FIXME thumb2
10827 // This must be a multiple of 4 between -508 and 508, for
10828 // ADD/SUB sp = sp + immediate.
10829 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
10834 Result = DAG.getTargetConstant(CVal, Op.getValueType());
10838 if (Result.getNode()) {
10839 Ops.push_back(Result);
10842 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10845 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
10846 assert(Subtarget->isTargetAEABI() && "Register-based DivRem lowering only");
10847 unsigned Opcode = Op->getOpcode();
10848 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
10849 "Invalid opcode for Div/Rem lowering");
10850 bool isSigned = (Opcode == ISD::SDIVREM);
10851 EVT VT = Op->getValueType(0);
10852 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
10855 switch (VT.getSimpleVT().SimpleTy) {
10856 default: llvm_unreachable("Unexpected request for libcall!");
10857 case MVT::i8: LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
10858 case MVT::i16: LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
10859 case MVT::i32: LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
10860 case MVT::i64: LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
10863 SDValue InChain = DAG.getEntryNode();
10865 TargetLowering::ArgListTy Args;
10866 TargetLowering::ArgListEntry Entry;
10867 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
10868 EVT ArgVT = Op->getOperand(i).getValueType();
10869 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10870 Entry.Node = Op->getOperand(i);
10872 Entry.isSExt = isSigned;
10873 Entry.isZExt = !isSigned;
10874 Args.push_back(Entry);
10877 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
10880 Type *RetTy = (Type*)StructType::get(Ty, Ty, nullptr);
10883 TargetLowering::CallLoweringInfo CLI(DAG);
10884 CLI.setDebugLoc(dl).setChain(InChain)
10885 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
10886 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
10888 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
10889 return CallInfo.first;
10893 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
10894 assert(Subtarget->isTargetWindows() && "unsupported target platform");
10898 SDValue Chain = Op.getOperand(0);
10899 SDValue Size = Op.getOperand(1);
10901 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size,
10902 DAG.getConstant(2, MVT::i32));
10905 Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag);
10906 Flag = Chain.getValue(1);
10908 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10909 Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
10911 SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
10912 Chain = NewSP.getValue(1);
10914 SDValue Ops[2] = { NewSP, Chain };
10915 return DAG.getMergeValues(Ops, DL);
10918 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
10919 assert(Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() &&
10920 "Unexpected type for custom-lowering FP_EXTEND");
10923 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
10925 SDValue SrcVal = Op.getOperand(0);
10926 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
10927 /*isSigned*/ false, SDLoc(Op)).first;
10930 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
10931 assert(Op.getOperand(0).getValueType() == MVT::f64 &&
10932 Subtarget->isFPOnlySP() &&
10933 "Unexpected type for custom-lowering FP_ROUND");
10936 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
10938 SDValue SrcVal = Op.getOperand(0);
10939 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
10940 /*isSigned*/ false, SDLoc(Op)).first;
10944 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
10945 // The ARM target isn't yet aware of offsets.
10949 bool ARM::isBitFieldInvertedMask(unsigned v) {
10950 if (v == 0xffffffff)
10953 // there can be 1's on either or both "outsides", all the "inside"
10954 // bits must be 0's
10955 unsigned TO = CountTrailingOnes_32(v);
10956 unsigned LO = CountLeadingOnes_32(v);
10957 v = (v >> TO) << TO;
10958 v = (v << LO) >> LO;
10962 /// isFPImmLegal - Returns true if the target can instruction select the
10963 /// specified FP immediate natively. If false, the legalizer will
10964 /// materialize the FP immediate as a load from a constant pool.
10965 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
10966 if (!Subtarget->hasVFP3())
10968 if (VT == MVT::f32)
10969 return ARM_AM::getFP32Imm(Imm) != -1;
10970 if (VT == MVT::f64 && !Subtarget->isFPOnlySP())
10971 return ARM_AM::getFP64Imm(Imm) != -1;
10975 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
10976 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
10977 /// specified in the intrinsic calls.
10978 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
10980 unsigned Intrinsic) const {
10981 switch (Intrinsic) {
10982 case Intrinsic::arm_neon_vld1:
10983 case Intrinsic::arm_neon_vld2:
10984 case Intrinsic::arm_neon_vld3:
10985 case Intrinsic::arm_neon_vld4:
10986 case Intrinsic::arm_neon_vld2lane:
10987 case Intrinsic::arm_neon_vld3lane:
10988 case Intrinsic::arm_neon_vld4lane: {
10989 Info.opc = ISD::INTRINSIC_W_CHAIN;
10990 // Conservatively set memVT to the entire set of vectors loaded.
10991 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
10992 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10993 Info.ptrVal = I.getArgOperand(0);
10995 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10996 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10997 Info.vol = false; // volatile loads with NEON intrinsics not supported
10998 Info.readMem = true;
10999 Info.writeMem = false;
11002 case Intrinsic::arm_neon_vst1:
11003 case Intrinsic::arm_neon_vst2:
11004 case Intrinsic::arm_neon_vst3:
11005 case Intrinsic::arm_neon_vst4:
11006 case Intrinsic::arm_neon_vst2lane:
11007 case Intrinsic::arm_neon_vst3lane:
11008 case Intrinsic::arm_neon_vst4lane: {
11009 Info.opc = ISD::INTRINSIC_VOID;
11010 // Conservatively set memVT to the entire set of vectors stored.
11011 unsigned NumElts = 0;
11012 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
11013 Type *ArgTy = I.getArgOperand(ArgI)->getType();
11014 if (!ArgTy->isVectorTy())
11016 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
11018 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11019 Info.ptrVal = I.getArgOperand(0);
11021 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
11022 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
11023 Info.vol = false; // volatile stores with NEON intrinsics not supported
11024 Info.readMem = false;
11025 Info.writeMem = true;
11028 case Intrinsic::arm_ldaex:
11029 case Intrinsic::arm_ldrex: {
11030 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
11031 Info.opc = ISD::INTRINSIC_W_CHAIN;
11032 Info.memVT = MVT::getVT(PtrTy->getElementType());
11033 Info.ptrVal = I.getArgOperand(0);
11035 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
11037 Info.readMem = true;
11038 Info.writeMem = false;
11041 case Intrinsic::arm_stlex:
11042 case Intrinsic::arm_strex: {
11043 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
11044 Info.opc = ISD::INTRINSIC_W_CHAIN;
11045 Info.memVT = MVT::getVT(PtrTy->getElementType());
11046 Info.ptrVal = I.getArgOperand(1);
11048 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
11050 Info.readMem = false;
11051 Info.writeMem = true;
11054 case Intrinsic::arm_stlexd:
11055 case Intrinsic::arm_strexd: {
11056 Info.opc = ISD::INTRINSIC_W_CHAIN;
11057 Info.memVT = MVT::i64;
11058 Info.ptrVal = I.getArgOperand(2);
11062 Info.readMem = false;
11063 Info.writeMem = true;
11066 case Intrinsic::arm_ldaexd:
11067 case Intrinsic::arm_ldrexd: {
11068 Info.opc = ISD::INTRINSIC_W_CHAIN;
11069 Info.memVT = MVT::i64;
11070 Info.ptrVal = I.getArgOperand(0);
11074 Info.readMem = true;
11075 Info.writeMem = false;
11085 /// \brief Returns true if it is beneficial to convert a load of a constant
11086 /// to just the constant itself.
11087 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11089 assert(Ty->isIntegerTy());
11091 unsigned Bits = Ty->getPrimitiveSizeInBits();
11092 if (Bits == 0 || Bits > 32)
11097 bool ARMTargetLowering::hasLoadLinkedStoreConditional() const { return true; }
11099 Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
11100 ARM_MB::MemBOpt Domain) const {
11101 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11103 // First, if the target has no DMB, see what fallback we can use.
11104 if (!Subtarget->hasDataBarrier()) {
11105 // Some ARMv6 cpus can support data barriers with an mcr instruction.
11106 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
11108 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {
11109 Function *MCR = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_mcr);
11110 Value* args[6] = {Builder.getInt32(15), Builder.getInt32(0),
11111 Builder.getInt32(0), Builder.getInt32(7),
11112 Builder.getInt32(10), Builder.getInt32(5)};
11113 return Builder.CreateCall(MCR, args);
11115 // Instead of using barriers, atomic accesses on these subtargets use
11117 llvm_unreachable("makeDMB on a target so old that it has no barriers");
11120 Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
11121 // Only a full system barrier exists in the M-class architectures.
11122 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain;
11123 Constant *CDomain = Builder.getInt32(Domain);
11124 return Builder.CreateCall(DMB, CDomain);
11128 // Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
11129 Instruction* ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
11130 AtomicOrdering Ord, bool IsStore,
11131 bool IsLoad) const {
11132 if (!getInsertFencesForAtomic())
11138 llvm_unreachable("Invalid fence: unordered/non-atomic");
11141 return nullptr; // Nothing to do
11142 case SequentiallyConsistent:
11144 return nullptr; // Nothing to do
11147 case AcquireRelease:
11148 if (Subtarget->isSwift())
11149 return makeDMB(Builder, ARM_MB::ISHST);
11150 // FIXME: add a comment with a link to documentation justifying this.
11152 return makeDMB(Builder, ARM_MB::ISH);
11154 llvm_unreachable("Unknown fence ordering in emitLeadingFence");
11157 Instruction* ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
11158 AtomicOrdering Ord, bool IsStore,
11159 bool IsLoad) const {
11160 if (!getInsertFencesForAtomic())
11166 llvm_unreachable("Invalid fence: unordered/not-atomic");
11169 return nullptr; // Nothing to do
11171 case AcquireRelease:
11172 case SequentiallyConsistent:
11173 return makeDMB(Builder, ARM_MB::ISH);
11175 llvm_unreachable("Unknown fence ordering in emitTrailingFence");
11178 // Loads and stores less than 64-bits are already atomic; ones above that
11179 // are doomed anyway, so defer to the default libcall and blame the OS when
11180 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11181 // anything for those.
11182 bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
11183 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
11184 return (Size == 64) && !Subtarget->isMClass();
11187 // Loads and stores less than 64-bits are already atomic; ones above that
11188 // are doomed anyway, so defer to the default libcall and blame the OS when
11189 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11190 // anything for those.
11191 // FIXME: ldrd and strd are atomic if the CPU has LPAE (e.g. A15 has that
11192 // guarantee, see DDI0406C ARM architecture reference manual,
11193 // sections A8.8.72-74 LDRD)
11194 bool ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
11195 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
11196 return (Size == 64) && !Subtarget->isMClass();
11199 // For the real atomic operations, we have ldrex/strex up to 32 bits,
11200 // and up to 64 bits on the non-M profiles
11201 bool ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
11202 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
11203 return Size <= (Subtarget->isMClass() ? 32U : 64U);
11206 // This has so far only been implemented for MachO.
11207 bool ARMTargetLowering::useLoadStackGuardNode() const {
11208 return Subtarget->isTargetMachO();
11211 bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
11212 unsigned &Cost) const {
11213 // If we do not have NEON, vector types are not natively supported.
11214 if (!Subtarget->hasNEON())
11217 // Floating point values and vector values map to the same register file.
11218 // Therefore, althought we could do a store extract of a vector type, this is
11219 // better to leave at float as we have more freedom in the addressing mode for
11221 if (VectorTy->isFPOrFPVectorTy())
11224 // If the index is unknown at compile time, this is very expensive to lower
11225 // and it is not possible to combine the store with the extract.
11226 if (!isa<ConstantInt>(Idx))
11229 assert(VectorTy->isVectorTy() && "VectorTy is not a vector type");
11230 unsigned BitWidth = cast<VectorType>(VectorTy)->getBitWidth();
11231 // We can do a store + vector extract on any vector that fits perfectly in a D
11233 if (BitWidth == 64 || BitWidth == 128) {
11240 Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
11241 AtomicOrdering Ord) const {
11242 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11243 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
11244 bool IsAcquire = isAtLeastAcquire(Ord);
11246 // Since i64 isn't legal and intrinsics don't get type-lowered, the ldrexd
11247 // intrinsic must return {i32, i32} and we have to recombine them into a
11248 // single i64 here.
11249 if (ValTy->getPrimitiveSizeInBits() == 64) {
11250 Intrinsic::ID Int =
11251 IsAcquire ? Intrinsic::arm_ldaexd : Intrinsic::arm_ldrexd;
11252 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int);
11254 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11255 Value *LoHi = Builder.CreateCall(Ldrex, Addr, "lohi");
11257 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
11258 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
11259 if (!Subtarget->isLittle())
11260 std::swap (Lo, Hi);
11261 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
11262 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
11263 return Builder.CreateOr(
11264 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 32)), "val64");
11267 Type *Tys[] = { Addr->getType() };
11268 Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex;
11269 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int, Tys);
11271 return Builder.CreateTruncOrBitCast(
11272 Builder.CreateCall(Ldrex, Addr),
11273 cast<PointerType>(Addr->getType())->getElementType());
11276 Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,
11278 AtomicOrdering Ord) const {
11279 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11280 bool IsRelease = isAtLeastRelease(Ord);
11282 // Since the intrinsics must have legal type, the i64 intrinsics take two
11283 // parameters: "i32, i32". We must marshal Val into the appropriate form
11284 // before the call.
11285 if (Val->getType()->getPrimitiveSizeInBits() == 64) {
11286 Intrinsic::ID Int =
11287 IsRelease ? Intrinsic::arm_stlexd : Intrinsic::arm_strexd;
11288 Function *Strex = Intrinsic::getDeclaration(M, Int);
11289 Type *Int32Ty = Type::getInt32Ty(M->getContext());
11291 Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo");
11292 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi");
11293 if (!Subtarget->isLittle())
11294 std::swap (Lo, Hi);
11295 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11296 return Builder.CreateCall3(Strex, Lo, Hi, Addr);
11299 Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex;
11300 Type *Tys[] = { Addr->getType() };
11301 Function *Strex = Intrinsic::getDeclaration(M, Int, Tys);
11303 return Builder.CreateCall2(
11304 Strex, Builder.CreateZExtOrBitCast(
11305 Val, Strex->getFunctionType()->getParamType(0)),
11317 static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base,
11318 uint64_t &Members) {
11319 if (const StructType *ST = dyn_cast<StructType>(Ty)) {
11320 for (unsigned i = 0; i < ST->getNumElements(); ++i) {
11321 uint64_t SubMembers = 0;
11322 if (!isHomogeneousAggregate(ST->getElementType(i), Base, SubMembers))
11324 Members += SubMembers;
11326 } else if (const ArrayType *AT = dyn_cast<ArrayType>(Ty)) {
11327 uint64_t SubMembers = 0;
11328 if (!isHomogeneousAggregate(AT->getElementType(), Base, SubMembers))
11330 Members += SubMembers * AT->getNumElements();
11331 } else if (Ty->isFloatTy()) {
11332 if (Base != HA_UNKNOWN && Base != HA_FLOAT)
11336 } else if (Ty->isDoubleTy()) {
11337 if (Base != HA_UNKNOWN && Base != HA_DOUBLE)
11341 } else if (const VectorType *VT = dyn_cast<VectorType>(Ty)) {
11348 return VT->getBitWidth() == 64;
11350 return VT->getBitWidth() == 128;
11352 switch (VT->getBitWidth()) {
11365 return (Members > 0 && Members <= 4);
11368 /// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate.
11369 bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(
11370 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
11371 if (getEffectiveCallingConv(CallConv, isVarArg) !=
11372 CallingConv::ARM_AAPCS_VFP)
11375 HABaseType Base = HA_UNKNOWN;
11376 uint64_t Members = 0;
11377 bool result = isHomogeneousAggregate(Ty, Base, Members);
11378 DEBUG(dbgs() << "isHA: " << result << " "; Ty->dump());