1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMPerfectShuffle.h"
21 #include "ARMRegisterInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Function.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Instruction.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Type.h"
32 #include "llvm/CodeGen/CallingConvLower.h"
33 #include "llvm/CodeGen/MachineBasicBlock.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineFunction.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/ADT/VectorExtras.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/raw_ostream.h"
51 EnableARMLongCalls("arm-long-calls", cl::Hidden,
52 cl::desc("Generate calls via indirect call instructions."),
55 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
56 CCValAssign::LocInfo &LocInfo,
57 ISD::ArgFlagsTy &ArgFlags,
59 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
60 CCValAssign::LocInfo &LocInfo,
61 ISD::ArgFlagsTy &ArgFlags,
63 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
64 CCValAssign::LocInfo &LocInfo,
65 ISD::ArgFlagsTy &ArgFlags,
67 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
68 CCValAssign::LocInfo &LocInfo,
69 ISD::ArgFlagsTy &ArgFlags,
72 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
73 EVT PromotedBitwiseVT) {
74 if (VT != PromotedLdStVT) {
75 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
76 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
77 PromotedLdStVT.getSimpleVT());
79 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
80 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
81 PromotedLdStVT.getSimpleVT());
84 EVT ElemTy = VT.getVectorElementType();
85 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
86 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
87 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
88 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
89 if (ElemTy != MVT::i32) {
90 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
91 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
92 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
93 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
95 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
96 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
97 if (llvm::ModelWithRegSequence())
98 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
100 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
101 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
102 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
103 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
104 if (VT.isInteger()) {
105 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
106 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
107 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
110 // Promote all bit-wise operations.
111 if (VT.isInteger() && VT != PromotedBitwiseVT) {
112 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
113 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
114 PromotedBitwiseVT.getSimpleVT());
115 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
116 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
117 PromotedBitwiseVT.getSimpleVT());
118 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
119 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
120 PromotedBitwiseVT.getSimpleVT());
123 // Neon does not support vector divide/remainder operations.
124 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
125 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
126 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
127 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
128 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
129 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
132 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
133 addRegisterClass(VT, ARM::DPRRegisterClass);
134 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
137 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
138 addRegisterClass(VT, ARM::QPRRegisterClass);
139 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
142 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
143 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
144 return new TargetLoweringObjectFileMachO();
146 return new ARMElfTargetObjectFile();
149 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
150 : TargetLowering(TM, createTLOF(TM)) {
151 Subtarget = &TM.getSubtarget<ARMSubtarget>();
153 if (Subtarget->isTargetDarwin()) {
154 // Uses VFP for Thumb libfuncs if available.
155 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
156 // Single-precision floating-point arithmetic.
157 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
158 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
159 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
160 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
162 // Double-precision floating-point arithmetic.
163 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
164 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
165 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
166 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
168 // Single-precision comparisons.
169 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
170 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
171 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
172 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
173 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
174 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
175 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
176 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
178 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
179 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
180 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
181 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
182 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
183 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
184 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
185 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
187 // Double-precision comparisons.
188 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
189 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
190 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
191 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
192 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
193 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
194 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
195 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
197 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
199 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
200 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
201 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
202 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
204 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
206 // Floating-point to integer conversions.
207 // i64 conversions are done via library routines even when generating VFP
208 // instructions, so use the same ones.
209 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
210 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
211 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
212 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
214 // Conversions between floating types.
215 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
216 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
218 // Integer to floating-point conversions.
219 // i64 conversions are done via library routines even when generating VFP
220 // instructions, so use the same ones.
221 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
222 // e.g., __floatunsidf vs. __floatunssidfvfp.
223 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
224 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
225 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
226 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
230 // These libcalls are not available in 32-bit.
231 setLibcallName(RTLIB::SHL_I128, 0);
232 setLibcallName(RTLIB::SRL_I128, 0);
233 setLibcallName(RTLIB::SRA_I128, 0);
235 // Libcalls should use the AAPCS base standard ABI, even if hard float
236 // is in effect, as per the ARM RTABI specification, section 4.1.2.
237 if (Subtarget->isAAPCS_ABI()) {
238 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
239 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
240 CallingConv::ARM_AAPCS);
244 if (Subtarget->isThumb1Only())
245 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
247 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
248 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
249 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
250 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
252 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
255 if (Subtarget->hasNEON()) {
256 addDRTypeForNEON(MVT::v2f32);
257 addDRTypeForNEON(MVT::v8i8);
258 addDRTypeForNEON(MVT::v4i16);
259 addDRTypeForNEON(MVT::v2i32);
260 addDRTypeForNEON(MVT::v1i64);
262 addQRTypeForNEON(MVT::v4f32);
263 addQRTypeForNEON(MVT::v2f64);
264 addQRTypeForNEON(MVT::v16i8);
265 addQRTypeForNEON(MVT::v8i16);
266 addQRTypeForNEON(MVT::v4i32);
267 addQRTypeForNEON(MVT::v2i64);
269 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
270 // neither Neon nor VFP support any arithmetic operations on it.
271 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
272 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
273 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
274 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
275 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
276 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
277 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
278 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
279 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
280 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
281 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
282 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
283 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
284 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
285 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
286 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
287 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
288 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
289 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
290 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
291 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
292 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
293 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
294 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
296 // Neon does not support some operations on v1i64 and v2i64 types.
297 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
298 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
299 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
300 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
302 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
303 setTargetDAGCombine(ISD::SHL);
304 setTargetDAGCombine(ISD::SRL);
305 setTargetDAGCombine(ISD::SRA);
306 setTargetDAGCombine(ISD::SIGN_EXTEND);
307 setTargetDAGCombine(ISD::ZERO_EXTEND);
308 setTargetDAGCombine(ISD::ANY_EXTEND);
309 setTargetDAGCombine(ISD::SELECT_CC);
312 computeRegisterProperties();
314 // ARM does not have f32 extending load.
315 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
317 // ARM does not have i1 sign extending load.
318 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
320 // ARM supports all 4 flavors of integer indexed load / store.
321 if (!Subtarget->isThumb1Only()) {
322 for (unsigned im = (unsigned)ISD::PRE_INC;
323 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
324 setIndexedLoadAction(im, MVT::i1, Legal);
325 setIndexedLoadAction(im, MVT::i8, Legal);
326 setIndexedLoadAction(im, MVT::i16, Legal);
327 setIndexedLoadAction(im, MVT::i32, Legal);
328 setIndexedStoreAction(im, MVT::i1, Legal);
329 setIndexedStoreAction(im, MVT::i8, Legal);
330 setIndexedStoreAction(im, MVT::i16, Legal);
331 setIndexedStoreAction(im, MVT::i32, Legal);
335 // i64 operation support.
336 if (Subtarget->isThumb1Only()) {
337 setOperationAction(ISD::MUL, MVT::i64, Expand);
338 setOperationAction(ISD::MULHU, MVT::i32, Expand);
339 setOperationAction(ISD::MULHS, MVT::i32, Expand);
340 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
341 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
343 setOperationAction(ISD::MUL, MVT::i64, Expand);
344 setOperationAction(ISD::MULHU, MVT::i32, Expand);
345 if (!Subtarget->hasV6Ops())
346 setOperationAction(ISD::MULHS, MVT::i32, Expand);
348 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
349 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
350 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
351 setOperationAction(ISD::SRL, MVT::i64, Custom);
352 setOperationAction(ISD::SRA, MVT::i64, Custom);
354 // ARM does not have ROTL.
355 setOperationAction(ISD::ROTL, MVT::i32, Expand);
356 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
357 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
358 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
359 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
361 // Only ARMv6 has BSWAP.
362 if (!Subtarget->hasV6Ops())
363 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
365 // These are expanded into libcalls.
366 if (!Subtarget->hasDivide()) {
367 // v7M has a hardware divider
368 setOperationAction(ISD::SDIV, MVT::i32, Expand);
369 setOperationAction(ISD::UDIV, MVT::i32, Expand);
371 setOperationAction(ISD::SREM, MVT::i32, Expand);
372 setOperationAction(ISD::UREM, MVT::i32, Expand);
373 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
374 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
376 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
377 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
378 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
379 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
380 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
382 setOperationAction(ISD::TRAP, MVT::Other, Legal);
384 // Use the default implementation.
385 setOperationAction(ISD::VASTART, MVT::Other, Custom);
386 setOperationAction(ISD::VAARG, MVT::Other, Expand);
387 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
388 setOperationAction(ISD::VAEND, MVT::Other, Expand);
389 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
390 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
391 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
392 // FIXME: Shouldn't need this, since no register is used, but the legalizer
393 // doesn't yet know how to not do that for SjLj.
394 setExceptionSelectorRegister(ARM::R0);
395 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
396 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
398 // If the subtarget does not have extract instructions, sign_extend_inreg
399 // needs to be expanded. Extract is available in ARM mode on v6 and up,
400 // and on most Thumb2 implementations.
401 if ((!Subtarget->isThumb() && !Subtarget->hasV6Ops())
402 || (Subtarget->isThumb2() && !Subtarget->hasT2ExtractPack())) {
403 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
404 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
408 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
409 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
410 // iff target supports vfp2.
411 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
413 // We want to custom lower some of our intrinsics.
414 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
416 setOperationAction(ISD::SETCC, MVT::i32, Expand);
417 setOperationAction(ISD::SETCC, MVT::f32, Expand);
418 setOperationAction(ISD::SETCC, MVT::f64, Expand);
419 setOperationAction(ISD::SELECT, MVT::i32, Expand);
420 setOperationAction(ISD::SELECT, MVT::f32, Expand);
421 setOperationAction(ISD::SELECT, MVT::f64, Expand);
422 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
423 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
424 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
426 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
427 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
428 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
429 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
430 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
432 // We don't support sin/cos/fmod/copysign/pow
433 setOperationAction(ISD::FSIN, MVT::f64, Expand);
434 setOperationAction(ISD::FSIN, MVT::f32, Expand);
435 setOperationAction(ISD::FCOS, MVT::f32, Expand);
436 setOperationAction(ISD::FCOS, MVT::f64, Expand);
437 setOperationAction(ISD::FREM, MVT::f64, Expand);
438 setOperationAction(ISD::FREM, MVT::f32, Expand);
439 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
440 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
441 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
443 setOperationAction(ISD::FPOW, MVT::f64, Expand);
444 setOperationAction(ISD::FPOW, MVT::f32, Expand);
446 // Various VFP goodness
447 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
448 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
449 if (Subtarget->hasVFP2()) {
450 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
451 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
452 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
453 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
455 // Special handling for half-precision FP.
456 if (!Subtarget->hasFP16()) {
457 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
458 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
462 // We have target-specific dag combine patterns for the following nodes:
463 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
464 setTargetDAGCombine(ISD::ADD);
465 setTargetDAGCombine(ISD::SUB);
466 setTargetDAGCombine(ISD::MUL);
468 setStackPointerRegisterToSaveRestore(ARM::SP);
470 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
471 setSchedulingPreference(Sched::RegPressure);
473 setSchedulingPreference(Sched::Hybrid);
475 // FIXME: If-converter should use instruction latency to determine
476 // profitability rather than relying on fixed limits.
477 if (Subtarget->getCPUString() == "generic") {
478 // Generic (and overly aggressive) if-conversion limits.
479 setIfCvtBlockSizeLimit(10);
480 setIfCvtDupBlockSizeLimit(2);
481 } else if (Subtarget->hasV7Ops()) {
482 setIfCvtBlockSizeLimit(3);
483 setIfCvtDupBlockSizeLimit(1);
484 } else if (Subtarget->hasV6Ops()) {
485 setIfCvtBlockSizeLimit(2);
486 setIfCvtDupBlockSizeLimit(1);
488 setIfCvtBlockSizeLimit(3);
489 setIfCvtDupBlockSizeLimit(2);
492 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
493 // Do not enable CodePlacementOpt for now: it currently runs after the
494 // ARMConstantIslandPass and messes up branch relaxation and placement
495 // of constant islands.
496 // benefitFromCodePlacementOpt = true;
499 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
502 case ARMISD::Wrapper: return "ARMISD::Wrapper";
503 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
504 case ARMISD::CALL: return "ARMISD::CALL";
505 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
506 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
507 case ARMISD::tCALL: return "ARMISD::tCALL";
508 case ARMISD::BRCOND: return "ARMISD::BRCOND";
509 case ARMISD::BR_JT: return "ARMISD::BR_JT";
510 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
511 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
512 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
513 case ARMISD::CMP: return "ARMISD::CMP";
514 case ARMISD::CMPZ: return "ARMISD::CMPZ";
515 case ARMISD::CMPFP: return "ARMISD::CMPFP";
516 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
517 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
518 case ARMISD::CMOV: return "ARMISD::CMOV";
519 case ARMISD::CNEG: return "ARMISD::CNEG";
521 case ARMISD::RBIT: return "ARMISD::RBIT";
523 case ARMISD::FTOSI: return "ARMISD::FTOSI";
524 case ARMISD::FTOUI: return "ARMISD::FTOUI";
525 case ARMISD::SITOF: return "ARMISD::SITOF";
526 case ARMISD::UITOF: return "ARMISD::UITOF";
528 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
529 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
530 case ARMISD::RRX: return "ARMISD::RRX";
532 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
533 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
535 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
536 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
538 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
540 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
542 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
543 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
545 case ARMISD::VCEQ: return "ARMISD::VCEQ";
546 case ARMISD::VCGE: return "ARMISD::VCGE";
547 case ARMISD::VCGEU: return "ARMISD::VCGEU";
548 case ARMISD::VCGT: return "ARMISD::VCGT";
549 case ARMISD::VCGTU: return "ARMISD::VCGTU";
550 case ARMISD::VTST: return "ARMISD::VTST";
552 case ARMISD::VSHL: return "ARMISD::VSHL";
553 case ARMISD::VSHRs: return "ARMISD::VSHRs";
554 case ARMISD::VSHRu: return "ARMISD::VSHRu";
555 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
556 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
557 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
558 case ARMISD::VSHRN: return "ARMISD::VSHRN";
559 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
560 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
561 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
562 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
563 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
564 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
565 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
566 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
567 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
568 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
569 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
570 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
571 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
572 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
573 case ARMISD::VDUP: return "ARMISD::VDUP";
574 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
575 case ARMISD::VEXT: return "ARMISD::VEXT";
576 case ARMISD::VREV64: return "ARMISD::VREV64";
577 case ARMISD::VREV32: return "ARMISD::VREV32";
578 case ARMISD::VREV16: return "ARMISD::VREV16";
579 case ARMISD::VZIP: return "ARMISD::VZIP";
580 case ARMISD::VUZP: return "ARMISD::VUZP";
581 case ARMISD::VTRN: return "ARMISD::VTRN";
582 case ARMISD::FMAX: return "ARMISD::FMAX";
583 case ARMISD::FMIN: return "ARMISD::FMIN";
587 /// getRegClassFor - Return the register class that should be used for the
588 /// specified value type.
589 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
590 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
591 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
592 // load / store 4 to 8 consecutive D registers.
593 if (Subtarget->hasNEON()) {
594 if (VT == MVT::v4i64)
595 return ARM::QQPRRegisterClass;
596 else if (VT == MVT::v8i64)
597 return ARM::QQQQPRRegisterClass;
599 return TargetLowering::getRegClassFor(VT);
602 /// getFunctionAlignment - Return the Log2 alignment of this function.
603 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
604 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1;
607 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
608 unsigned NumVals = N->getNumValues();
610 return Sched::RegPressure;
612 for (unsigned i = 0; i != NumVals; ++i) {
613 EVT VT = N->getValueType(i);
614 if (VT.isFloatingPoint() || VT.isVector())
615 return Sched::Latency;
618 if (!N->isMachineOpcode())
619 return Sched::RegPressure;
621 // Load are scheduled for latency even if there instruction itinerary
623 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
624 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
626 return Sched::Latency;
628 const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData();
629 if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2)
630 return Sched::Latency;
631 return Sched::RegPressure;
634 //===----------------------------------------------------------------------===//
636 //===----------------------------------------------------------------------===//
638 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
639 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
641 default: llvm_unreachable("Unknown condition code!");
642 case ISD::SETNE: return ARMCC::NE;
643 case ISD::SETEQ: return ARMCC::EQ;
644 case ISD::SETGT: return ARMCC::GT;
645 case ISD::SETGE: return ARMCC::GE;
646 case ISD::SETLT: return ARMCC::LT;
647 case ISD::SETLE: return ARMCC::LE;
648 case ISD::SETUGT: return ARMCC::HI;
649 case ISD::SETUGE: return ARMCC::HS;
650 case ISD::SETULT: return ARMCC::LO;
651 case ISD::SETULE: return ARMCC::LS;
655 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
656 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
657 ARMCC::CondCodes &CondCode2) {
658 CondCode2 = ARMCC::AL;
660 default: llvm_unreachable("Unknown FP condition!");
662 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
664 case ISD::SETOGT: CondCode = ARMCC::GT; break;
666 case ISD::SETOGE: CondCode = ARMCC::GE; break;
667 case ISD::SETOLT: CondCode = ARMCC::MI; break;
668 case ISD::SETOLE: CondCode = ARMCC::LS; break;
669 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
670 case ISD::SETO: CondCode = ARMCC::VC; break;
671 case ISD::SETUO: CondCode = ARMCC::VS; break;
672 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
673 case ISD::SETUGT: CondCode = ARMCC::HI; break;
674 case ISD::SETUGE: CondCode = ARMCC::PL; break;
676 case ISD::SETULT: CondCode = ARMCC::LT; break;
678 case ISD::SETULE: CondCode = ARMCC::LE; break;
680 case ISD::SETUNE: CondCode = ARMCC::NE; break;
684 //===----------------------------------------------------------------------===//
685 // Calling Convention Implementation
686 //===----------------------------------------------------------------------===//
688 #include "ARMGenCallingConv.inc"
690 // APCS f64 is in register pairs, possibly split to stack
691 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
692 CCValAssign::LocInfo &LocInfo,
693 CCState &State, bool CanFail) {
694 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
696 // Try to get the first register.
697 if (unsigned Reg = State.AllocateReg(RegList, 4))
698 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
700 // For the 2nd half of a v2f64, do not fail.
704 // Put the whole thing on the stack.
705 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
706 State.AllocateStack(8, 4),
711 // Try to get the second register.
712 if (unsigned Reg = State.AllocateReg(RegList, 4))
713 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
715 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
716 State.AllocateStack(4, 4),
721 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
722 CCValAssign::LocInfo &LocInfo,
723 ISD::ArgFlagsTy &ArgFlags,
725 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
727 if (LocVT == MVT::v2f64 &&
728 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
730 return true; // we handled it
733 // AAPCS f64 is in aligned register pairs
734 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
735 CCValAssign::LocInfo &LocInfo,
736 CCState &State, bool CanFail) {
737 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
738 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
740 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
742 // For the 2nd half of a v2f64, do not just fail.
746 // Put the whole thing on the stack.
747 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
748 State.AllocateStack(8, 8),
754 for (i = 0; i < 2; ++i)
755 if (HiRegList[i] == Reg)
758 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
759 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
764 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
765 CCValAssign::LocInfo &LocInfo,
766 ISD::ArgFlagsTy &ArgFlags,
768 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
770 if (LocVT == MVT::v2f64 &&
771 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
773 return true; // we handled it
776 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
777 CCValAssign::LocInfo &LocInfo, CCState &State) {
778 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
779 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
781 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
783 return false; // we didn't handle it
786 for (i = 0; i < 2; ++i)
787 if (HiRegList[i] == Reg)
790 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
791 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
796 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
797 CCValAssign::LocInfo &LocInfo,
798 ISD::ArgFlagsTy &ArgFlags,
800 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
802 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
804 return true; // we handled it
807 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
808 CCValAssign::LocInfo &LocInfo,
809 ISD::ArgFlagsTy &ArgFlags,
811 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
815 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
816 /// given CallingConvention value.
817 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
819 bool isVarArg) const {
822 llvm_unreachable("Unsupported calling convention");
824 case CallingConv::Fast:
825 // Use target triple & subtarget features to do actual dispatch.
826 if (Subtarget->isAAPCS_ABI()) {
827 if (Subtarget->hasVFP2() &&
828 FloatABIType == FloatABI::Hard && !isVarArg)
829 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
831 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
833 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
834 case CallingConv::ARM_AAPCS_VFP:
835 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
836 case CallingConv::ARM_AAPCS:
837 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
838 case CallingConv::ARM_APCS:
839 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
843 /// LowerCallResult - Lower the result values of a call into the
844 /// appropriate copies out of appropriate physical registers.
846 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
847 CallingConv::ID CallConv, bool isVarArg,
848 const SmallVectorImpl<ISD::InputArg> &Ins,
849 DebugLoc dl, SelectionDAG &DAG,
850 SmallVectorImpl<SDValue> &InVals) const {
852 // Assign locations to each value returned by this call.
853 SmallVector<CCValAssign, 16> RVLocs;
854 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
855 RVLocs, *DAG.getContext());
856 CCInfo.AnalyzeCallResult(Ins,
857 CCAssignFnForNode(CallConv, /* Return*/ true,
860 // Copy all of the result registers out of their specified physreg.
861 for (unsigned i = 0; i != RVLocs.size(); ++i) {
862 CCValAssign VA = RVLocs[i];
865 if (VA.needsCustom()) {
866 // Handle f64 or half of a v2f64.
867 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
869 Chain = Lo.getValue(1);
870 InFlag = Lo.getValue(2);
871 VA = RVLocs[++i]; // skip ahead to next loc
872 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
874 Chain = Hi.getValue(1);
875 InFlag = Hi.getValue(2);
876 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
878 if (VA.getLocVT() == MVT::v2f64) {
879 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
880 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
881 DAG.getConstant(0, MVT::i32));
883 VA = RVLocs[++i]; // skip ahead to next loc
884 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
885 Chain = Lo.getValue(1);
886 InFlag = Lo.getValue(2);
887 VA = RVLocs[++i]; // skip ahead to next loc
888 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
889 Chain = Hi.getValue(1);
890 InFlag = Hi.getValue(2);
891 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
892 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
893 DAG.getConstant(1, MVT::i32));
896 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
898 Chain = Val.getValue(1);
899 InFlag = Val.getValue(2);
902 switch (VA.getLocInfo()) {
903 default: llvm_unreachable("Unknown loc info!");
904 case CCValAssign::Full: break;
905 case CCValAssign::BCvt:
906 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
910 InVals.push_back(Val);
916 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
917 /// by "Src" to address "Dst" of size "Size". Alignment information is
918 /// specified by the specific parameter attribute. The copy will be passed as
919 /// a byval function parameter.
920 /// Sometimes what we are copying is the end of a larger object, the part that
921 /// does not fit in registers.
923 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
924 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
926 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
927 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
928 /*isVolatile=*/false, /*AlwaysInline=*/false,
932 /// LowerMemOpCallTo - Store the argument to the stack.
934 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
935 SDValue StackPtr, SDValue Arg,
936 DebugLoc dl, SelectionDAG &DAG,
937 const CCValAssign &VA,
938 ISD::ArgFlagsTy Flags) const {
939 unsigned LocMemOffset = VA.getLocMemOffset();
940 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
941 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
942 if (Flags.isByVal()) {
943 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
945 return DAG.getStore(Chain, dl, Arg, PtrOff,
946 PseudoSourceValue::getStack(), LocMemOffset,
950 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
951 SDValue Chain, SDValue &Arg,
952 RegsToPassVector &RegsToPass,
953 CCValAssign &VA, CCValAssign &NextVA,
955 SmallVector<SDValue, 8> &MemOpChains,
956 ISD::ArgFlagsTy Flags) const {
958 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
959 DAG.getVTList(MVT::i32, MVT::i32), Arg);
960 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
962 if (NextVA.isRegLoc())
963 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
965 assert(NextVA.isMemLoc());
966 if (StackPtr.getNode() == 0)
967 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
969 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
975 /// LowerCall - Lowering a call into a callseq_start <-
976 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
979 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
980 CallingConv::ID CallConv, bool isVarArg,
982 const SmallVectorImpl<ISD::OutputArg> &Outs,
983 const SmallVectorImpl<ISD::InputArg> &Ins,
984 DebugLoc dl, SelectionDAG &DAG,
985 SmallVectorImpl<SDValue> &InVals) const {
986 // ARM target does not yet support tail call optimization.
989 // Analyze operands of the call, assigning locations to each operand.
990 SmallVector<CCValAssign, 16> ArgLocs;
991 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
993 CCInfo.AnalyzeCallOperands(Outs,
994 CCAssignFnForNode(CallConv, /* Return*/ false,
997 // Get a count of how many bytes are to be pushed on the stack.
998 unsigned NumBytes = CCInfo.getNextStackOffset();
1000 // Adjust the stack pointer for the new arguments...
1001 // These operations are automatically eliminated by the prolog/epilog pass
1002 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1004 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1006 RegsToPassVector RegsToPass;
1007 SmallVector<SDValue, 8> MemOpChains;
1009 // Walk the register/memloc assignments, inserting copies/loads. In the case
1010 // of tail call optimization, arguments are handled later.
1011 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1013 ++i, ++realArgIdx) {
1014 CCValAssign &VA = ArgLocs[i];
1015 SDValue Arg = Outs[realArgIdx].Val;
1016 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1018 // Promote the value if needed.
1019 switch (VA.getLocInfo()) {
1020 default: llvm_unreachable("Unknown loc info!");
1021 case CCValAssign::Full: break;
1022 case CCValAssign::SExt:
1023 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1025 case CCValAssign::ZExt:
1026 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1028 case CCValAssign::AExt:
1029 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1031 case CCValAssign::BCvt:
1032 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1036 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1037 if (VA.needsCustom()) {
1038 if (VA.getLocVT() == MVT::v2f64) {
1039 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1040 DAG.getConstant(0, MVT::i32));
1041 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1042 DAG.getConstant(1, MVT::i32));
1044 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1045 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1047 VA = ArgLocs[++i]; // skip ahead to next loc
1048 if (VA.isRegLoc()) {
1049 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1050 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1052 assert(VA.isMemLoc());
1054 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1055 dl, DAG, VA, Flags));
1058 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1059 StackPtr, MemOpChains, Flags);
1061 } else if (VA.isRegLoc()) {
1062 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1064 assert(VA.isMemLoc());
1066 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1067 dl, DAG, VA, Flags));
1071 if (!MemOpChains.empty())
1072 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1073 &MemOpChains[0], MemOpChains.size());
1075 // Build a sequence of copy-to-reg nodes chained together with token chain
1076 // and flag operands which copy the outgoing args into the appropriate regs.
1078 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1079 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1080 RegsToPass[i].second, InFlag);
1081 InFlag = Chain.getValue(1);
1084 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1085 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1086 // node so that legalize doesn't hack it.
1087 bool isDirect = false;
1088 bool isARMFunc = false;
1089 bool isLocalARMFunc = false;
1090 MachineFunction &MF = DAG.getMachineFunction();
1091 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1093 if (EnableARMLongCalls) {
1094 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1095 && "long-calls with non-static relocation model!");
1096 // Handle a global address or an external symbol. If it's not one of
1097 // those, the target's already in a register, so we don't need to do
1099 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1100 const GlobalValue *GV = G->getGlobal();
1101 // Create a constant pool entry for the callee address
1102 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1103 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1106 // Get the address of the callee into a register
1107 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1108 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1109 Callee = DAG.getLoad(getPointerTy(), dl,
1110 DAG.getEntryNode(), CPAddr,
1111 PseudoSourceValue::getConstantPool(), 0,
1113 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1114 const char *Sym = S->getSymbol();
1116 // Create a constant pool entry for the callee address
1117 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1118 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1119 Sym, ARMPCLabelIndex, 0);
1120 // Get the address of the callee into a register
1121 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1122 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1123 Callee = DAG.getLoad(getPointerTy(), dl,
1124 DAG.getEntryNode(), CPAddr,
1125 PseudoSourceValue::getConstantPool(), 0,
1128 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1129 const GlobalValue *GV = G->getGlobal();
1131 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1132 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1133 getTargetMachine().getRelocationModel() != Reloc::Static;
1134 isARMFunc = !Subtarget->isThumb() || isStub;
1135 // ARM call to a local ARM function is predicable.
1136 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
1137 // tBX takes a register source operand.
1138 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1139 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1140 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1143 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1144 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1145 Callee = DAG.getLoad(getPointerTy(), dl,
1146 DAG.getEntryNode(), CPAddr,
1147 PseudoSourceValue::getConstantPool(), 0,
1149 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1150 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1151 getPointerTy(), Callee, PICLabel);
1153 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
1154 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1156 bool isStub = Subtarget->isTargetDarwin() &&
1157 getTargetMachine().getRelocationModel() != Reloc::Static;
1158 isARMFunc = !Subtarget->isThumb() || isStub;
1159 // tBX takes a register source operand.
1160 const char *Sym = S->getSymbol();
1161 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1162 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1163 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1164 Sym, ARMPCLabelIndex, 4);
1165 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1166 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1167 Callee = DAG.getLoad(getPointerTy(), dl,
1168 DAG.getEntryNode(), CPAddr,
1169 PseudoSourceValue::getConstantPool(), 0,
1171 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1172 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1173 getPointerTy(), Callee, PICLabel);
1175 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1178 // FIXME: handle tail calls differently.
1180 if (Subtarget->isThumb()) {
1181 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1182 CallOpc = ARMISD::CALL_NOLINK;
1184 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1186 CallOpc = (isDirect || Subtarget->hasV5TOps())
1187 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1188 : ARMISD::CALL_NOLINK;
1190 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1191 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1192 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1193 InFlag = Chain.getValue(1);
1196 std::vector<SDValue> Ops;
1197 Ops.push_back(Chain);
1198 Ops.push_back(Callee);
1200 // Add argument registers to the end of the list so that they are known live
1202 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1203 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1204 RegsToPass[i].second.getValueType()));
1206 if (InFlag.getNode())
1207 Ops.push_back(InFlag);
1208 // Returns a chain and a flag for retval copy to use.
1209 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1210 &Ops[0], Ops.size());
1211 InFlag = Chain.getValue(1);
1213 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1214 DAG.getIntPtrConstant(0, true), InFlag);
1216 InFlag = Chain.getValue(1);
1218 // Handle result values, copying them out of physregs into vregs that we
1220 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1225 ARMTargetLowering::LowerReturn(SDValue Chain,
1226 CallingConv::ID CallConv, bool isVarArg,
1227 const SmallVectorImpl<ISD::OutputArg> &Outs,
1228 DebugLoc dl, SelectionDAG &DAG) const {
1230 // CCValAssign - represent the assignment of the return value to a location.
1231 SmallVector<CCValAssign, 16> RVLocs;
1233 // CCState - Info about the registers and stack slots.
1234 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1237 // Analyze outgoing return values.
1238 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1241 // If this is the first return lowered for this function, add
1242 // the regs to the liveout set for the function.
1243 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1244 for (unsigned i = 0; i != RVLocs.size(); ++i)
1245 if (RVLocs[i].isRegLoc())
1246 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1251 // Copy the result values into the output registers.
1252 for (unsigned i = 0, realRVLocIdx = 0;
1254 ++i, ++realRVLocIdx) {
1255 CCValAssign &VA = RVLocs[i];
1256 assert(VA.isRegLoc() && "Can only return in registers!");
1258 SDValue Arg = Outs[realRVLocIdx].Val;
1260 switch (VA.getLocInfo()) {
1261 default: llvm_unreachable("Unknown loc info!");
1262 case CCValAssign::Full: break;
1263 case CCValAssign::BCvt:
1264 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1268 if (VA.needsCustom()) {
1269 if (VA.getLocVT() == MVT::v2f64) {
1270 // Extract the first half and return it in two registers.
1271 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1272 DAG.getConstant(0, MVT::i32));
1273 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1274 DAG.getVTList(MVT::i32, MVT::i32), Half);
1276 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1277 Flag = Chain.getValue(1);
1278 VA = RVLocs[++i]; // skip ahead to next loc
1279 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1280 HalfGPRs.getValue(1), Flag);
1281 Flag = Chain.getValue(1);
1282 VA = RVLocs[++i]; // skip ahead to next loc
1284 // Extract the 2nd half and fall through to handle it as an f64 value.
1285 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1286 DAG.getConstant(1, MVT::i32));
1288 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1290 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1291 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1292 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1293 Flag = Chain.getValue(1);
1294 VA = RVLocs[++i]; // skip ahead to next loc
1295 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1298 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1300 // Guarantee that all emitted copies are
1301 // stuck together, avoiding something bad.
1302 Flag = Chain.getValue(1);
1307 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1309 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1314 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1315 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1316 // one of the above mentioned nodes. It has to be wrapped because otherwise
1317 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1318 // be used to form addressing mode. These wrapped nodes will be selected
1320 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1321 EVT PtrVT = Op.getValueType();
1322 // FIXME there is no actual debug info here
1323 DebugLoc dl = Op.getDebugLoc();
1324 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1326 if (CP->isMachineConstantPoolEntry())
1327 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1328 CP->getAlignment());
1330 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1331 CP->getAlignment());
1332 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1335 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1336 SelectionDAG &DAG) const {
1337 MachineFunction &MF = DAG.getMachineFunction();
1338 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1339 unsigned ARMPCLabelIndex = 0;
1340 DebugLoc DL = Op.getDebugLoc();
1341 EVT PtrVT = getPointerTy();
1342 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1343 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1345 if (RelocM == Reloc::Static) {
1346 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1348 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1349 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1350 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1351 ARMCP::CPBlockAddress,
1353 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1355 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1356 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1357 PseudoSourceValue::getConstantPool(), 0,
1359 if (RelocM == Reloc::Static)
1361 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1362 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1365 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1367 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1368 SelectionDAG &DAG) const {
1369 DebugLoc dl = GA->getDebugLoc();
1370 EVT PtrVT = getPointerTy();
1371 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1372 MachineFunction &MF = DAG.getMachineFunction();
1373 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1374 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1375 ARMConstantPoolValue *CPV =
1376 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1377 ARMCP::CPValue, PCAdj, "tlsgd", true);
1378 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1379 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1380 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1381 PseudoSourceValue::getConstantPool(), 0,
1383 SDValue Chain = Argument.getValue(1);
1385 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1386 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1388 // call __tls_get_addr.
1391 Entry.Node = Argument;
1392 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1393 Args.push_back(Entry);
1394 // FIXME: is there useful debug info available here?
1395 std::pair<SDValue, SDValue> CallResult =
1396 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1397 false, false, false, false,
1398 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1399 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1400 return CallResult.first;
1403 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1404 // "local exec" model.
1406 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1407 SelectionDAG &DAG) const {
1408 const GlobalValue *GV = GA->getGlobal();
1409 DebugLoc dl = GA->getDebugLoc();
1411 SDValue Chain = DAG.getEntryNode();
1412 EVT PtrVT = getPointerTy();
1413 // Get the Thread Pointer
1414 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1416 if (GV->isDeclaration()) {
1417 MachineFunction &MF = DAG.getMachineFunction();
1418 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1419 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1420 // Initial exec model.
1421 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1422 ARMConstantPoolValue *CPV =
1423 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1424 ARMCP::CPValue, PCAdj, "gottpoff", true);
1425 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1426 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1427 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1428 PseudoSourceValue::getConstantPool(), 0,
1430 Chain = Offset.getValue(1);
1432 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1433 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1435 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1436 PseudoSourceValue::getConstantPool(), 0,
1440 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1441 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1442 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1443 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1444 PseudoSourceValue::getConstantPool(), 0,
1448 // The address of the thread local variable is the add of the thread
1449 // pointer with the offset of the variable.
1450 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1454 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1455 // TODO: implement the "local dynamic" model
1456 assert(Subtarget->isTargetELF() &&
1457 "TLS not implemented for non-ELF targets");
1458 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1459 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1460 // otherwise use the "Local Exec" TLS Model
1461 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1462 return LowerToTLSGeneralDynamicModel(GA, DAG);
1464 return LowerToTLSExecModels(GA, DAG);
1467 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1468 SelectionDAG &DAG) const {
1469 EVT PtrVT = getPointerTy();
1470 DebugLoc dl = Op.getDebugLoc();
1471 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1472 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1473 if (RelocM == Reloc::PIC_) {
1474 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1475 ARMConstantPoolValue *CPV =
1476 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1477 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1478 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1479 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1481 PseudoSourceValue::getConstantPool(), 0,
1483 SDValue Chain = Result.getValue(1);
1484 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1485 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1487 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1488 PseudoSourceValue::getGOT(), 0,
1492 // If we have T2 ops, we can materialize the address directly via movt/movw
1493 // pair. This is always cheaper.
1494 if (Subtarget->useMovt()) {
1495 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1496 DAG.getTargetGlobalAddress(GV, PtrVT));
1498 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1499 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1500 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1501 PseudoSourceValue::getConstantPool(), 0,
1507 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1508 SelectionDAG &DAG) const {
1509 MachineFunction &MF = DAG.getMachineFunction();
1510 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1511 unsigned ARMPCLabelIndex = 0;
1512 EVT PtrVT = getPointerTy();
1513 DebugLoc dl = Op.getDebugLoc();
1514 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1515 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1517 if (RelocM == Reloc::Static)
1518 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1520 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1521 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1522 ARMConstantPoolValue *CPV =
1523 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1524 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1526 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1528 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1529 PseudoSourceValue::getConstantPool(), 0,
1531 SDValue Chain = Result.getValue(1);
1533 if (RelocM == Reloc::PIC_) {
1534 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1535 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1538 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1539 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1540 PseudoSourceValue::getGOT(), 0,
1546 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1547 SelectionDAG &DAG) const {
1548 assert(Subtarget->isTargetELF() &&
1549 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1550 MachineFunction &MF = DAG.getMachineFunction();
1551 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1552 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1553 EVT PtrVT = getPointerTy();
1554 DebugLoc dl = Op.getDebugLoc();
1555 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1556 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1557 "_GLOBAL_OFFSET_TABLE_",
1558 ARMPCLabelIndex, PCAdj);
1559 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1560 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1561 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1562 PseudoSourceValue::getConstantPool(), 0,
1564 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1565 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1569 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1570 DebugLoc dl = Op.getDebugLoc();
1571 SDValue Val = DAG.getConstant(0, MVT::i32);
1572 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1573 Op.getOperand(1), Val);
1577 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1578 DebugLoc dl = Op.getDebugLoc();
1579 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1580 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1584 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1585 const ARMSubtarget *Subtarget)
1587 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1588 DebugLoc dl = Op.getDebugLoc();
1590 default: return SDValue(); // Don't custom lower most intrinsics.
1591 case Intrinsic::arm_thread_pointer: {
1592 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1593 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1595 case Intrinsic::eh_sjlj_lsda: {
1596 MachineFunction &MF = DAG.getMachineFunction();
1597 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1598 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1599 EVT PtrVT = getPointerTy();
1600 DebugLoc dl = Op.getDebugLoc();
1601 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1603 unsigned PCAdj = (RelocM != Reloc::PIC_)
1604 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1605 ARMConstantPoolValue *CPV =
1606 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1607 ARMCP::CPLSDA, PCAdj);
1608 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1609 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1611 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1612 PseudoSourceValue::getConstantPool(), 0,
1614 SDValue Chain = Result.getValue(1);
1616 if (RelocM == Reloc::PIC_) {
1617 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1618 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1625 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
1626 const ARMSubtarget *Subtarget) {
1627 DebugLoc dl = Op.getDebugLoc();
1628 SDValue Op5 = Op.getOperand(5);
1630 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
1631 if (isDeviceBarrier) {
1632 if (Subtarget->hasV7Ops())
1633 Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other, Op.getOperand(0));
1635 Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other, Op.getOperand(0),
1636 DAG.getConstant(0, MVT::i32));
1638 if (Subtarget->hasV7Ops())
1639 Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
1641 Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
1642 DAG.getConstant(0, MVT::i32));
1647 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
1648 MachineFunction &MF = DAG.getMachineFunction();
1649 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
1651 // vastart just stores the address of the VarArgsFrameIndex slot into the
1652 // memory location argument.
1653 DebugLoc dl = Op.getDebugLoc();
1654 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1655 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1656 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1657 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
1662 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1663 SelectionDAG &DAG) const {
1664 SDNode *Node = Op.getNode();
1665 DebugLoc dl = Node->getDebugLoc();
1666 EVT VT = Node->getValueType(0);
1667 SDValue Chain = Op.getOperand(0);
1668 SDValue Size = Op.getOperand(1);
1669 SDValue Align = Op.getOperand(2);
1671 // Chain the dynamic stack allocation so that it doesn't modify the stack
1672 // pointer when other instructions are using the stack.
1673 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1675 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1676 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1677 if (AlignVal > StackAlign)
1678 // Do this now since selection pass cannot introduce new target
1679 // independent node.
1680 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1682 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1683 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1684 // do even more horrible hack later.
1685 MachineFunction &MF = DAG.getMachineFunction();
1686 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1687 if (AFI->isThumb1OnlyFunction()) {
1689 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1691 uint32_t Val = C->getZExtValue();
1692 if (Val <= 508 && ((Val & 3) == 0))
1696 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1699 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1700 SDValue Ops1[] = { Chain, Size, Align };
1701 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1702 Chain = Res.getValue(1);
1703 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1704 DAG.getIntPtrConstant(0, true), SDValue());
1705 SDValue Ops2[] = { Res, Chain };
1706 return DAG.getMergeValues(Ops2, 2, dl);
1710 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1711 SDValue &Root, SelectionDAG &DAG,
1712 DebugLoc dl) const {
1713 MachineFunction &MF = DAG.getMachineFunction();
1714 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1716 TargetRegisterClass *RC;
1717 if (AFI->isThumb1OnlyFunction())
1718 RC = ARM::tGPRRegisterClass;
1720 RC = ARM::GPRRegisterClass;
1722 // Transform the arguments stored in physical registers into virtual ones.
1723 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1724 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1727 if (NextVA.isMemLoc()) {
1728 MachineFrameInfo *MFI = MF.getFrameInfo();
1729 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true, false);
1731 // Create load node to retrieve arguments from the stack.
1732 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1733 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
1734 PseudoSourceValue::getFixedStack(FI), 0,
1737 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1738 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1741 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
1745 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1746 CallingConv::ID CallConv, bool isVarArg,
1747 const SmallVectorImpl<ISD::InputArg>
1749 DebugLoc dl, SelectionDAG &DAG,
1750 SmallVectorImpl<SDValue> &InVals)
1753 MachineFunction &MF = DAG.getMachineFunction();
1754 MachineFrameInfo *MFI = MF.getFrameInfo();
1756 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1758 // Assign locations to all of the incoming arguments.
1759 SmallVector<CCValAssign, 16> ArgLocs;
1760 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1762 CCInfo.AnalyzeFormalArguments(Ins,
1763 CCAssignFnForNode(CallConv, /* Return*/ false,
1766 SmallVector<SDValue, 16> ArgValues;
1768 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1769 CCValAssign &VA = ArgLocs[i];
1771 // Arguments stored in registers.
1772 if (VA.isRegLoc()) {
1773 EVT RegVT = VA.getLocVT();
1776 if (VA.needsCustom()) {
1777 // f64 and vector types are split up into multiple registers or
1778 // combinations of registers and stack slots.
1779 if (VA.getLocVT() == MVT::v2f64) {
1780 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1782 VA = ArgLocs[++i]; // skip ahead to next loc
1784 if (VA.isMemLoc()) {
1785 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(),
1787 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1788 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
1789 PseudoSourceValue::getFixedStack(FI), 0,
1792 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1795 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1796 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1797 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1798 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1799 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1801 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1804 TargetRegisterClass *RC;
1806 if (RegVT == MVT::f32)
1807 RC = ARM::SPRRegisterClass;
1808 else if (RegVT == MVT::f64)
1809 RC = ARM::DPRRegisterClass;
1810 else if (RegVT == MVT::v2f64)
1811 RC = ARM::QPRRegisterClass;
1812 else if (RegVT == MVT::i32)
1813 RC = (AFI->isThumb1OnlyFunction() ?
1814 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
1816 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1818 // Transform the arguments in physical registers into virtual ones.
1819 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1820 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1823 // If this is an 8 or 16-bit value, it is really passed promoted
1824 // to 32 bits. Insert an assert[sz]ext to capture this, then
1825 // truncate to the right size.
1826 switch (VA.getLocInfo()) {
1827 default: llvm_unreachable("Unknown loc info!");
1828 case CCValAssign::Full: break;
1829 case CCValAssign::BCvt:
1830 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1832 case CCValAssign::SExt:
1833 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1834 DAG.getValueType(VA.getValVT()));
1835 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1837 case CCValAssign::ZExt:
1838 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1839 DAG.getValueType(VA.getValVT()));
1840 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1844 InVals.push_back(ArgValue);
1846 } else { // VA.isRegLoc()
1849 assert(VA.isMemLoc());
1850 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1852 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1853 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1856 // Create load nodes to retrieve arguments from the stack.
1857 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1858 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1859 PseudoSourceValue::getFixedStack(FI), 0,
1866 static const unsigned GPRArgRegs[] = {
1867 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1870 unsigned NumGPRs = CCInfo.getFirstUnallocated
1871 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1873 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1874 unsigned VARegSize = (4 - NumGPRs) * 4;
1875 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1876 unsigned ArgOffset = CCInfo.getNextStackOffset();
1877 if (VARegSaveSize) {
1878 // If this function is vararg, store any remaining integer argument regs
1879 // to their spots on the stack so that they may be loaded by deferencing
1880 // the result of va_next.
1881 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1882 AFI->setVarArgsFrameIndex(
1883 MFI->CreateFixedObject(VARegSaveSize,
1884 ArgOffset + VARegSaveSize - VARegSize,
1886 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
1889 SmallVector<SDValue, 4> MemOps;
1890 for (; NumGPRs < 4; ++NumGPRs) {
1891 TargetRegisterClass *RC;
1892 if (AFI->isThumb1OnlyFunction())
1893 RC = ARM::tGPRRegisterClass;
1895 RC = ARM::GPRRegisterClass;
1897 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1898 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1900 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1901 PseudoSourceValue::getFixedStack(AFI->getVarArgsFrameIndex()),
1902 0, false, false, 0);
1903 MemOps.push_back(Store);
1904 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1905 DAG.getConstant(4, getPointerTy()));
1907 if (!MemOps.empty())
1908 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1909 &MemOps[0], MemOps.size());
1911 // This will point to the next argument passed via stack.
1912 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset,
1919 /// isFloatingPointZero - Return true if this is +0.0.
1920 static bool isFloatingPointZero(SDValue Op) {
1921 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1922 return CFP->getValueAPF().isPosZero();
1923 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1924 // Maybe this has already been legalized into the constant pool?
1925 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1926 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1927 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1928 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1929 return CFP->getValueAPF().isPosZero();
1935 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1936 /// the given operands.
1938 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1939 SDValue &ARMCC, SelectionDAG &DAG,
1940 DebugLoc dl) const {
1941 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1942 unsigned C = RHSC->getZExtValue();
1943 if (!isLegalICmpImmediate(C)) {
1944 // Constant does not fit, try adjusting it by one?
1949 if (isLegalICmpImmediate(C-1)) {
1950 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1951 RHS = DAG.getConstant(C-1, MVT::i32);
1956 if (C > 0 && isLegalICmpImmediate(C-1)) {
1957 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1958 RHS = DAG.getConstant(C-1, MVT::i32);
1963 if (isLegalICmpImmediate(C+1)) {
1964 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1965 RHS = DAG.getConstant(C+1, MVT::i32);
1970 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
1971 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1972 RHS = DAG.getConstant(C+1, MVT::i32);
1979 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1980 ARMISD::NodeType CompareType;
1983 CompareType = ARMISD::CMP;
1988 CompareType = ARMISD::CMPZ;
1991 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1992 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1995 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1996 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1999 if (!isFloatingPointZero(RHS))
2000 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2002 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2003 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2006 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2007 EVT VT = Op.getValueType();
2008 SDValue LHS = Op.getOperand(0);
2009 SDValue RHS = Op.getOperand(1);
2010 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2011 SDValue TrueVal = Op.getOperand(2);
2012 SDValue FalseVal = Op.getOperand(3);
2013 DebugLoc dl = Op.getDebugLoc();
2015 if (LHS.getValueType() == MVT::i32) {
2017 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2018 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2019 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
2022 ARMCC::CondCodes CondCode, CondCode2;
2023 FPCCToARMCC(CC, CondCode, CondCode2);
2025 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
2026 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2027 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2028 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2030 if (CondCode2 != ARMCC::AL) {
2031 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
2032 // FIXME: Needs another CMP because flag can have but one use.
2033 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2034 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2035 Result, TrueVal, ARMCC2, CCR, Cmp2);
2040 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2041 SDValue Chain = Op.getOperand(0);
2042 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2043 SDValue LHS = Op.getOperand(2);
2044 SDValue RHS = Op.getOperand(3);
2045 SDValue Dest = Op.getOperand(4);
2046 DebugLoc dl = Op.getDebugLoc();
2048 if (LHS.getValueType() == MVT::i32) {
2050 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2051 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2052 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2053 Chain, Dest, ARMCC, CCR,Cmp);
2056 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2057 ARMCC::CondCodes CondCode, CondCode2;
2058 FPCCToARMCC(CC, CondCode, CondCode2);
2060 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2061 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
2062 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2063 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2064 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
2065 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2066 if (CondCode2 != ARMCC::AL) {
2067 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
2068 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
2069 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2074 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2075 SDValue Chain = Op.getOperand(0);
2076 SDValue Table = Op.getOperand(1);
2077 SDValue Index = Op.getOperand(2);
2078 DebugLoc dl = Op.getDebugLoc();
2080 EVT PTy = getPointerTy();
2081 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2082 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2083 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2084 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2085 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2086 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2087 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2088 if (Subtarget->isThumb2()) {
2089 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2090 // which does another jump to the destination. This also makes it easier
2091 // to translate it to TBB / TBH later.
2092 // FIXME: This might not work if the function is extremely large.
2093 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2094 Addr, Op.getOperand(2), JTI, UId);
2096 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2097 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2098 PseudoSourceValue::getJumpTable(), 0,
2100 Chain = Addr.getValue(1);
2101 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2102 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2104 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2105 PseudoSourceValue::getJumpTable(), 0, false, false, 0);
2106 Chain = Addr.getValue(1);
2107 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2111 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2112 DebugLoc dl = Op.getDebugLoc();
2115 switch (Op.getOpcode()) {
2117 assert(0 && "Invalid opcode!");
2118 case ISD::FP_TO_SINT:
2119 Opc = ARMISD::FTOSI;
2121 case ISD::FP_TO_UINT:
2122 Opc = ARMISD::FTOUI;
2125 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2126 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2129 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2130 EVT VT = Op.getValueType();
2131 DebugLoc dl = Op.getDebugLoc();
2134 switch (Op.getOpcode()) {
2136 assert(0 && "Invalid opcode!");
2137 case ISD::SINT_TO_FP:
2138 Opc = ARMISD::SITOF;
2140 case ISD::UINT_TO_FP:
2141 Opc = ARMISD::UITOF;
2145 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2146 return DAG.getNode(Opc, dl, VT, Op);
2149 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
2150 // Implement fcopysign with a fabs and a conditional fneg.
2151 SDValue Tmp0 = Op.getOperand(0);
2152 SDValue Tmp1 = Op.getOperand(1);
2153 DebugLoc dl = Op.getDebugLoc();
2154 EVT VT = Op.getValueType();
2155 EVT SrcVT = Tmp1.getValueType();
2156 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2157 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
2158 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
2159 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2160 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
2163 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2164 MachineFunction &MF = DAG.getMachineFunction();
2165 MachineFrameInfo *MFI = MF.getFrameInfo();
2166 MFI->setReturnAddressIsTaken(true);
2168 EVT VT = Op.getValueType();
2169 DebugLoc dl = Op.getDebugLoc();
2170 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2172 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2173 SDValue Offset = DAG.getConstant(4, MVT::i32);
2174 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2175 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2176 NULL, 0, false, false, 0);
2179 // Return LR, which contains the return address. Mark it an implicit live-in.
2180 unsigned Reg = MF.addLiveIn(ARM::LR, ARM::GPRRegisterClass);
2181 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2184 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2185 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2186 MFI->setFrameAddressIsTaken(true);
2188 EVT VT = Op.getValueType();
2189 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2190 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2191 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2192 ? ARM::R7 : ARM::R11;
2193 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2195 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
2200 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2201 /// expand a bit convert where either the source or destination type is i64 to
2202 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2203 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2204 /// vectors), since the legalizer won't know what to do with that.
2205 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2206 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2207 DebugLoc dl = N->getDebugLoc();
2208 SDValue Op = N->getOperand(0);
2210 // This function is only supposed to be called for i64 types, either as the
2211 // source or destination of the bit convert.
2212 EVT SrcVT = Op.getValueType();
2213 EVT DstVT = N->getValueType(0);
2214 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2215 "ExpandBIT_CONVERT called for non-i64 type");
2217 // Turn i64->f64 into VMOVDRR.
2218 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2219 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2220 DAG.getConstant(0, MVT::i32));
2221 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2222 DAG.getConstant(1, MVT::i32));
2223 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2226 // Turn f64->i64 into VMOVRRD.
2227 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2228 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2229 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2230 // Merge the pieces into a single i64 value.
2231 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2237 /// getZeroVector - Returns a vector of specified type with all zero elements.
2239 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2240 assert(VT.isVector() && "Expected a vector type");
2242 // Zero vectors are used to represent vector negation and in those cases
2243 // will be implemented with the NEON VNEG instruction. However, VNEG does
2244 // not support i64 elements, so sometimes the zero vectors will need to be
2245 // explicitly constructed. For those cases, and potentially other uses in
2246 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted
2247 // to their dest type. This ensures they get CSE'd.
2249 SDValue Cst = DAG.getTargetConstant(0, MVT::i8);
2250 SmallVector<SDValue, 8> Ops;
2253 if (VT.getSizeInBits() == 64) {
2254 Ops.assign(8, Cst); TVT = MVT::v8i8;
2256 Ops.assign(16, Cst); TVT = MVT::v16i8;
2258 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2260 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2263 /// getOnesVector - Returns a vector of specified type with all bits set.
2265 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2266 assert(VT.isVector() && "Expected a vector type");
2268 // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their
2269 // dest type. This ensures they get CSE'd.
2271 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
2272 SmallVector<SDValue, 8> Ops;
2275 if (VT.getSizeInBits() == 64) {
2276 Ops.assign(8, Cst); TVT = MVT::v8i8;
2278 Ops.assign(16, Cst); TVT = MVT::v16i8;
2280 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2282 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2285 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2286 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2287 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2288 SelectionDAG &DAG) const {
2289 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2290 EVT VT = Op.getValueType();
2291 unsigned VTBits = VT.getSizeInBits();
2292 DebugLoc dl = Op.getDebugLoc();
2293 SDValue ShOpLo = Op.getOperand(0);
2294 SDValue ShOpHi = Op.getOperand(1);
2295 SDValue ShAmt = Op.getOperand(2);
2297 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2299 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2301 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2302 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2303 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2304 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2305 DAG.getConstant(VTBits, MVT::i32));
2306 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2307 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2308 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2310 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2311 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2313 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2314 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC,
2317 SDValue Ops[2] = { Lo, Hi };
2318 return DAG.getMergeValues(Ops, 2, dl);
2321 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2322 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2323 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2324 SelectionDAG &DAG) const {
2325 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2326 EVT VT = Op.getValueType();
2327 unsigned VTBits = VT.getSizeInBits();
2328 DebugLoc dl = Op.getDebugLoc();
2329 SDValue ShOpLo = Op.getOperand(0);
2330 SDValue ShOpHi = Op.getOperand(1);
2331 SDValue ShAmt = Op.getOperand(2);
2334 assert(Op.getOpcode() == ISD::SHL_PARTS);
2335 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2336 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2337 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2338 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2339 DAG.getConstant(VTBits, MVT::i32));
2340 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2341 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2343 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2344 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2345 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2347 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2348 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC,
2351 SDValue Ops[2] = { Lo, Hi };
2352 return DAG.getMergeValues(Ops, 2, dl);
2355 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2356 const ARMSubtarget *ST) {
2357 EVT VT = N->getValueType(0);
2358 DebugLoc dl = N->getDebugLoc();
2360 if (!ST->hasV6T2Ops())
2363 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2364 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2367 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2368 const ARMSubtarget *ST) {
2369 EVT VT = N->getValueType(0);
2370 DebugLoc dl = N->getDebugLoc();
2372 // Lower vector shifts on NEON to use VSHL.
2373 if (VT.isVector()) {
2374 assert(ST->hasNEON() && "unexpected vector shift");
2376 // Left shifts translate directly to the vshiftu intrinsic.
2377 if (N->getOpcode() == ISD::SHL)
2378 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2379 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2380 N->getOperand(0), N->getOperand(1));
2382 assert((N->getOpcode() == ISD::SRA ||
2383 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2385 // NEON uses the same intrinsics for both left and right shifts. For
2386 // right shifts, the shift amounts are negative, so negate the vector of
2388 EVT ShiftVT = N->getOperand(1).getValueType();
2389 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2390 getZeroVector(ShiftVT, DAG, dl),
2392 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2393 Intrinsic::arm_neon_vshifts :
2394 Intrinsic::arm_neon_vshiftu);
2395 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2396 DAG.getConstant(vshiftInt, MVT::i32),
2397 N->getOperand(0), NegatedCount);
2400 // We can get here for a node like i32 = ISD::SHL i32, i64
2404 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2405 "Unknown shift to lower!");
2407 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2408 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2409 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2412 // If we are in thumb mode, we don't have RRX.
2413 if (ST->isThumb1Only()) return SDValue();
2415 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2416 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2417 DAG.getConstant(0, MVT::i32));
2418 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2419 DAG.getConstant(1, MVT::i32));
2421 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2422 // captures the result into a carry flag.
2423 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2424 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2426 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2427 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2429 // Merge the pieces into a single i64 value.
2430 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2433 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2434 SDValue TmpOp0, TmpOp1;
2435 bool Invert = false;
2439 SDValue Op0 = Op.getOperand(0);
2440 SDValue Op1 = Op.getOperand(1);
2441 SDValue CC = Op.getOperand(2);
2442 EVT VT = Op.getValueType();
2443 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2444 DebugLoc dl = Op.getDebugLoc();
2446 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2447 switch (SetCCOpcode) {
2448 default: llvm_unreachable("Illegal FP comparison"); break;
2450 case ISD::SETNE: Invert = true; // Fallthrough
2452 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2454 case ISD::SETLT: Swap = true; // Fallthrough
2456 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2458 case ISD::SETLE: Swap = true; // Fallthrough
2460 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2461 case ISD::SETUGE: Swap = true; // Fallthrough
2462 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2463 case ISD::SETUGT: Swap = true; // Fallthrough
2464 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2465 case ISD::SETUEQ: Invert = true; // Fallthrough
2467 // Expand this to (OLT | OGT).
2471 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2472 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2474 case ISD::SETUO: Invert = true; // Fallthrough
2476 // Expand this to (OLT | OGE).
2480 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2481 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2485 // Integer comparisons.
2486 switch (SetCCOpcode) {
2487 default: llvm_unreachable("Illegal integer comparison"); break;
2488 case ISD::SETNE: Invert = true;
2489 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2490 case ISD::SETLT: Swap = true;
2491 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2492 case ISD::SETLE: Swap = true;
2493 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2494 case ISD::SETULT: Swap = true;
2495 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2496 case ISD::SETULE: Swap = true;
2497 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2500 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2501 if (Opc == ARMISD::VCEQ) {
2504 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2506 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2509 // Ignore bitconvert.
2510 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2511 AndOp = AndOp.getOperand(0);
2513 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2515 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2516 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2523 std::swap(Op0, Op1);
2525 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2528 Result = DAG.getNOT(dl, Result, VT);
2533 /// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2534 /// VMOV instruction, and if so, return the constant being splatted.
2535 static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2536 unsigned SplatBitSize, SelectionDAG &DAG) {
2537 switch (SplatBitSize) {
2539 // Any 1-byte value is OK.
2540 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2541 return DAG.getTargetConstant(SplatBits, MVT::i8);
2544 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2545 if ((SplatBits & ~0xff) == 0 ||
2546 (SplatBits & ~0xff00) == 0)
2547 return DAG.getTargetConstant(SplatBits, MVT::i16);
2551 // NEON's 32-bit VMOV supports splat values where:
2552 // * only one byte is nonzero, or
2553 // * the least significant byte is 0xff and the second byte is nonzero, or
2554 // * the least significant 2 bytes are 0xff and the third is nonzero.
2555 if ((SplatBits & ~0xff) == 0 ||
2556 (SplatBits & ~0xff00) == 0 ||
2557 (SplatBits & ~0xff0000) == 0 ||
2558 (SplatBits & ~0xff000000) == 0)
2559 return DAG.getTargetConstant(SplatBits, MVT::i32);
2561 if ((SplatBits & ~0xffff) == 0 &&
2562 ((SplatBits | SplatUndef) & 0xff) == 0xff)
2563 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2565 if ((SplatBits & ~0xffffff) == 0 &&
2566 ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2567 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2569 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2570 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2571 // VMOV.I32. A (very) minor optimization would be to replicate the value
2572 // and fall through here to test for a valid 64-bit splat. But, then the
2573 // caller would also need to check and handle the change in size.
2577 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2578 uint64_t BitMask = 0xff;
2580 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2581 if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2583 else if ((SplatBits & BitMask) != 0)
2587 return DAG.getTargetConstant(Val, MVT::i64);
2591 llvm_unreachable("unexpected size for isVMOVSplat");
2598 /// getVMOVImm - If this is a build_vector of constants which can be
2599 /// formed by using a VMOV instruction of the specified element size,
2600 /// return the constant being splatted. The ByteSize field indicates the
2601 /// number of bytes of each element [1248].
2602 SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2603 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2604 APInt SplatBits, SplatUndef;
2605 unsigned SplatBitSize;
2607 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2608 HasAnyUndefs, ByteSize * 8))
2611 if (SplatBitSize > ByteSize * 8)
2614 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2618 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
2619 bool &ReverseVEXT, unsigned &Imm) {
2620 unsigned NumElts = VT.getVectorNumElements();
2621 ReverseVEXT = false;
2624 // If this is a VEXT shuffle, the immediate value is the index of the first
2625 // element. The other shuffle indices must be the successive elements after
2627 unsigned ExpectedElt = Imm;
2628 for (unsigned i = 1; i < NumElts; ++i) {
2629 // Increment the expected index. If it wraps around, it may still be
2630 // a VEXT but the source vectors must be swapped.
2632 if (ExpectedElt == NumElts * 2) {
2637 if (ExpectedElt != static_cast<unsigned>(M[i]))
2641 // Adjust the index value if the source operands will be swapped.
2648 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2649 /// instruction with the specified blocksize. (The order of the elements
2650 /// within each block of the vector is reversed.)
2651 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
2652 unsigned BlockSize) {
2653 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2654 "Only possible block sizes for VREV are: 16, 32, 64");
2656 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2660 unsigned NumElts = VT.getVectorNumElements();
2661 unsigned BlockElts = M[0] + 1;
2663 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2666 for (unsigned i = 0; i < NumElts; ++i) {
2667 if ((unsigned) M[i] !=
2668 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2675 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
2676 unsigned &WhichResult) {
2677 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2681 unsigned NumElts = VT.getVectorNumElements();
2682 WhichResult = (M[0] == 0 ? 0 : 1);
2683 for (unsigned i = 0; i < NumElts; i += 2) {
2684 if ((unsigned) M[i] != i + WhichResult ||
2685 (unsigned) M[i+1] != i + NumElts + WhichResult)
2691 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
2692 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2693 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
2694 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2695 unsigned &WhichResult) {
2696 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2700 unsigned NumElts = VT.getVectorNumElements();
2701 WhichResult = (M[0] == 0 ? 0 : 1);
2702 for (unsigned i = 0; i < NumElts; i += 2) {
2703 if ((unsigned) M[i] != i + WhichResult ||
2704 (unsigned) M[i+1] != i + WhichResult)
2710 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
2711 unsigned &WhichResult) {
2712 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2716 unsigned NumElts = VT.getVectorNumElements();
2717 WhichResult = (M[0] == 0 ? 0 : 1);
2718 for (unsigned i = 0; i != NumElts; ++i) {
2719 if ((unsigned) M[i] != 2 * i + WhichResult)
2723 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2724 if (VT.is64BitVector() && EltSz == 32)
2730 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
2731 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2732 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
2733 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2734 unsigned &WhichResult) {
2735 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2739 unsigned Half = VT.getVectorNumElements() / 2;
2740 WhichResult = (M[0] == 0 ? 0 : 1);
2741 for (unsigned j = 0; j != 2; ++j) {
2742 unsigned Idx = WhichResult;
2743 for (unsigned i = 0; i != Half; ++i) {
2744 if ((unsigned) M[i + j * Half] != Idx)
2750 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2751 if (VT.is64BitVector() && EltSz == 32)
2757 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
2758 unsigned &WhichResult) {
2759 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2763 unsigned NumElts = VT.getVectorNumElements();
2764 WhichResult = (M[0] == 0 ? 0 : 1);
2765 unsigned Idx = WhichResult * NumElts / 2;
2766 for (unsigned i = 0; i != NumElts; i += 2) {
2767 if ((unsigned) M[i] != Idx ||
2768 (unsigned) M[i+1] != Idx + NumElts)
2773 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2774 if (VT.is64BitVector() && EltSz == 32)
2780 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
2781 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2782 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
2783 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2784 unsigned &WhichResult) {
2785 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2789 unsigned NumElts = VT.getVectorNumElements();
2790 WhichResult = (M[0] == 0 ? 0 : 1);
2791 unsigned Idx = WhichResult * NumElts / 2;
2792 for (unsigned i = 0; i != NumElts; i += 2) {
2793 if ((unsigned) M[i] != Idx ||
2794 (unsigned) M[i+1] != Idx)
2799 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2800 if (VT.is64BitVector() && EltSz == 32)
2807 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2808 // Canonicalize all-zeros and all-ones vectors.
2809 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
2810 if (ConstVal->isNullValue())
2811 return getZeroVector(VT, DAG, dl);
2812 if (ConstVal->isAllOnesValue())
2813 return getOnesVector(VT, DAG, dl);
2816 if (VT.is64BitVector()) {
2817 switch (Val.getValueType().getSizeInBits()) {
2818 case 8: CanonicalVT = MVT::v8i8; break;
2819 case 16: CanonicalVT = MVT::v4i16; break;
2820 case 32: CanonicalVT = MVT::v2i32; break;
2821 case 64: CanonicalVT = MVT::v1i64; break;
2822 default: llvm_unreachable("unexpected splat element type"); break;
2825 assert(VT.is128BitVector() && "unknown splat vector size");
2826 switch (Val.getValueType().getSizeInBits()) {
2827 case 8: CanonicalVT = MVT::v16i8; break;
2828 case 16: CanonicalVT = MVT::v8i16; break;
2829 case 32: CanonicalVT = MVT::v4i32; break;
2830 case 64: CanonicalVT = MVT::v2i64; break;
2831 default: llvm_unreachable("unexpected splat element type"); break;
2835 // Build a canonical splat for this value.
2836 SmallVector<SDValue, 8> Ops;
2837 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2838 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2840 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2843 // If this is a case we can't handle, return null and let the default
2844 // expansion code take care of it.
2845 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2846 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2847 DebugLoc dl = Op.getDebugLoc();
2848 EVT VT = Op.getValueType();
2850 APInt SplatBits, SplatUndef;
2851 unsigned SplatBitSize;
2853 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2854 if (SplatBitSize <= 64) {
2855 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2856 SplatUndef.getZExtValue(), SplatBitSize, DAG);
2858 return BuildSplat(Val, VT, DAG, dl);
2862 // Scan through the operands to see if only one value is used.
2863 unsigned NumElts = VT.getVectorNumElements();
2864 bool isOnlyLowElement = true;
2865 bool usesOnlyOneValue = true;
2866 bool isConstant = true;
2868 for (unsigned i = 0; i < NumElts; ++i) {
2869 SDValue V = Op.getOperand(i);
2870 if (V.getOpcode() == ISD::UNDEF)
2873 isOnlyLowElement = false;
2874 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
2877 if (!Value.getNode())
2879 else if (V != Value)
2880 usesOnlyOneValue = false;
2883 if (!Value.getNode())
2884 return DAG.getUNDEF(VT);
2886 if (isOnlyLowElement)
2887 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
2889 // If all elements are constants, fall back to the default expansion, which
2890 // will generate a load from the constant pool.
2894 // Use VDUP for non-constant splats.
2895 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
2896 if (usesOnlyOneValue && EltSize <= 32)
2897 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
2899 // Vectors with 32- or 64-bit elements can be built by directly assigning
2900 // the subregisters.
2901 if (EltSize >= 32) {
2902 // Do the expansion with floating-point types, since that is what the VFP
2903 // registers are defined to use, and since i64 is not legal.
2904 EVT EltVT = EVT::getFloatingPointVT(EltSize);
2905 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
2906 SDValue Val = DAG.getUNDEF(VecVT);
2907 for (unsigned i = 0; i < NumElts; ++i) {
2908 SDValue Elt = Op.getOperand(i);
2909 if (Elt.getOpcode() == ISD::UNDEF)
2911 Elt = DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Elt);
2912 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Val, Elt,
2913 DAG.getConstant(i, MVT::i32));
2915 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
2921 /// isShuffleMaskLegal - Targets can use this to indicate that they only
2922 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
2923 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
2924 /// are assumed to be legal.
2926 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
2928 if (VT.getVectorNumElements() == 4 &&
2929 (VT.is128BitVector() || VT.is64BitVector())) {
2930 unsigned PFIndexes[4];
2931 for (unsigned i = 0; i != 4; ++i) {
2935 PFIndexes[i] = M[i];
2938 // Compute the index in the perfect shuffle table.
2939 unsigned PFTableIndex =
2940 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2941 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2942 unsigned Cost = (PFEntry >> 30);
2949 unsigned Imm, WhichResult;
2951 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
2952 isVREVMask(M, VT, 64) ||
2953 isVREVMask(M, VT, 32) ||
2954 isVREVMask(M, VT, 16) ||
2955 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
2956 isVTRNMask(M, VT, WhichResult) ||
2957 isVUZPMask(M, VT, WhichResult) ||
2958 isVZIPMask(M, VT, WhichResult) ||
2959 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
2960 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
2961 isVZIP_v_undef_Mask(M, VT, WhichResult));
2964 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2965 /// the specified operations to build the shuffle.
2966 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
2967 SDValue RHS, SelectionDAG &DAG,
2969 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2970 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2971 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2974 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2983 OP_VUZPL, // VUZP, left result
2984 OP_VUZPR, // VUZP, right result
2985 OP_VZIPL, // VZIP, left result
2986 OP_VZIPR, // VZIP, right result
2987 OP_VTRNL, // VTRN, left result
2988 OP_VTRNR // VTRN, right result
2991 if (OpNum == OP_COPY) {
2992 if (LHSID == (1*9+2)*9+3) return LHS;
2993 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2997 SDValue OpLHS, OpRHS;
2998 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
2999 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3000 EVT VT = OpLHS.getValueType();
3003 default: llvm_unreachable("Unknown shuffle opcode!");
3005 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3010 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3011 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3015 return DAG.getNode(ARMISD::VEXT, dl, VT,
3017 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3020 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3021 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3024 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3025 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3028 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3029 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3033 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3034 SDValue V1 = Op.getOperand(0);
3035 SDValue V2 = Op.getOperand(1);
3036 DebugLoc dl = Op.getDebugLoc();
3037 EVT VT = Op.getValueType();
3038 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3039 SmallVector<int, 8> ShuffleMask;
3041 // Convert shuffles that are directly supported on NEON to target-specific
3042 // DAG nodes, instead of keeping them as shuffles and matching them again
3043 // during code selection. This is more efficient and avoids the possibility
3044 // of inconsistencies between legalization and selection.
3045 // FIXME: floating-point vectors should be canonicalized to integer vectors
3046 // of the same time so that they get CSEd properly.
3047 SVN->getMask(ShuffleMask);
3049 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3050 int Lane = SVN->getSplatIndex();
3051 // If this is undef splat, generate it via "just" vdup, if possible.
3052 if (Lane == -1) Lane = 0;
3054 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3055 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3057 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3058 DAG.getConstant(Lane, MVT::i32));
3063 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3066 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3067 DAG.getConstant(Imm, MVT::i32));
3070 if (isVREVMask(ShuffleMask, VT, 64))
3071 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3072 if (isVREVMask(ShuffleMask, VT, 32))
3073 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3074 if (isVREVMask(ShuffleMask, VT, 16))
3075 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3077 // Check for Neon shuffles that modify both input vectors in place.
3078 // If both results are used, i.e., if there are two shuffles with the same
3079 // source operands and with masks corresponding to both results of one of
3080 // these operations, DAG memoization will ensure that a single node is
3081 // used for both shuffles.
3082 unsigned WhichResult;
3083 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3084 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3085 V1, V2).getValue(WhichResult);
3086 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3087 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3088 V1, V2).getValue(WhichResult);
3089 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3090 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3091 V1, V2).getValue(WhichResult);
3093 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3094 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3095 V1, V1).getValue(WhichResult);
3096 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3097 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3098 V1, V1).getValue(WhichResult);
3099 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3100 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3101 V1, V1).getValue(WhichResult);
3103 // If the shuffle is not directly supported and it has 4 elements, use
3104 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3105 unsigned NumElts = VT.getVectorNumElements();
3107 unsigned PFIndexes[4];
3108 for (unsigned i = 0; i != 4; ++i) {
3109 if (ShuffleMask[i] < 0)
3112 PFIndexes[i] = ShuffleMask[i];
3115 // Compute the index in the perfect shuffle table.
3116 unsigned PFTableIndex =
3117 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3118 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3119 unsigned Cost = (PFEntry >> 30);
3122 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3125 // Implement shuffles with 32- or 64-bit elements as subreg copies.
3126 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3127 if (EltSize >= 32) {
3128 // Do the expansion with floating-point types, since that is what the VFP
3129 // registers are defined to use, and since i64 is not legal.
3130 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3131 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3132 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3133 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3134 SDValue Val = DAG.getUNDEF(VecVT);
3135 for (unsigned i = 0; i < NumElts; ++i) {
3136 if (ShuffleMask[i] < 0)
3138 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3139 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3140 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3142 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Val,
3143 Elt, DAG.getConstant(i, MVT::i32));
3145 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3151 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3152 EVT VT = Op.getValueType();
3153 DebugLoc dl = Op.getDebugLoc();
3154 SDValue Vec = Op.getOperand(0);
3155 SDValue Lane = Op.getOperand(1);
3156 assert(VT == MVT::i32 &&
3157 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3158 "unexpected type for custom-lowering vector extract");
3159 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3162 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3163 // The only time a CONCAT_VECTORS operation can have legal types is when
3164 // two 64-bit vectors are concatenated to a 128-bit vector.
3165 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3166 "unexpected CONCAT_VECTORS");
3167 DebugLoc dl = Op.getDebugLoc();
3168 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3169 SDValue Op0 = Op.getOperand(0);
3170 SDValue Op1 = Op.getOperand(1);
3171 if (Op0.getOpcode() != ISD::UNDEF)
3172 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3173 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3174 DAG.getIntPtrConstant(0));
3175 if (Op1.getOpcode() != ISD::UNDEF)
3176 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3177 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3178 DAG.getIntPtrConstant(1));
3179 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3182 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3183 switch (Op.getOpcode()) {
3184 default: llvm_unreachable("Don't know how to custom lower this!");
3185 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3186 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3187 case ISD::GlobalAddress:
3188 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3189 LowerGlobalAddressELF(Op, DAG);
3190 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3191 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3192 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3193 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3194 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3195 case ISD::VASTART: return LowerVASTART(Op, DAG);
3196 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3197 case ISD::SINT_TO_FP:
3198 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3199 case ISD::FP_TO_SINT:
3200 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3201 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3202 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3203 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3204 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3205 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3206 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3207 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3209 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3212 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3213 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3214 case ISD::SRL_PARTS:
3215 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3216 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3217 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3218 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3219 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3220 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3221 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3226 /// ReplaceNodeResults - Replace the results of node with an illegal result
3227 /// type with new values built out of custom code.
3228 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3229 SmallVectorImpl<SDValue>&Results,
3230 SelectionDAG &DAG) const {
3232 switch (N->getOpcode()) {
3234 llvm_unreachable("Don't know how to custom expand this!");
3236 case ISD::BIT_CONVERT:
3237 Res = ExpandBIT_CONVERT(N, DAG);
3241 Res = LowerShift(N, DAG, Subtarget);
3245 Results.push_back(Res);
3248 //===----------------------------------------------------------------------===//
3249 // ARM Scheduler Hooks
3250 //===----------------------------------------------------------------------===//
3253 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3254 MachineBasicBlock *BB,
3255 unsigned Size) const {
3256 unsigned dest = MI->getOperand(0).getReg();
3257 unsigned ptr = MI->getOperand(1).getReg();
3258 unsigned oldval = MI->getOperand(2).getReg();
3259 unsigned newval = MI->getOperand(3).getReg();
3260 unsigned scratch = BB->getParent()->getRegInfo()
3261 .createVirtualRegister(ARM::GPRRegisterClass);
3262 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3263 DebugLoc dl = MI->getDebugLoc();
3264 bool isThumb2 = Subtarget->isThumb2();
3266 unsigned ldrOpc, strOpc;
3268 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3270 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3271 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3274 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3275 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3278 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3279 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3283 MachineFunction *MF = BB->getParent();
3284 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3285 MachineFunction::iterator It = BB;
3286 ++It; // insert the new blocks after the current block
3288 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3289 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3290 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3291 MF->insert(It, loop1MBB);
3292 MF->insert(It, loop2MBB);
3293 MF->insert(It, exitMBB);
3294 exitMBB->transferSuccessors(BB);
3298 // fallthrough --> loop1MBB
3299 BB->addSuccessor(loop1MBB);
3302 // ldrex dest, [ptr]
3306 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3307 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3308 .addReg(dest).addReg(oldval));
3309 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3310 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3311 BB->addSuccessor(loop2MBB);
3312 BB->addSuccessor(exitMBB);
3315 // strex scratch, newval, [ptr]
3319 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3321 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3322 .addReg(scratch).addImm(0));
3323 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3324 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3325 BB->addSuccessor(loop1MBB);
3326 BB->addSuccessor(exitMBB);
3332 MF->DeleteMachineInstr(MI); // The instruction is gone now.
3338 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3339 unsigned Size, unsigned BinOpcode) const {
3340 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3341 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3343 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3344 MachineFunction *MF = BB->getParent();
3345 MachineFunction::iterator It = BB;
3348 unsigned dest = MI->getOperand(0).getReg();
3349 unsigned ptr = MI->getOperand(1).getReg();
3350 unsigned incr = MI->getOperand(2).getReg();
3351 DebugLoc dl = MI->getDebugLoc();
3353 bool isThumb2 = Subtarget->isThumb2();
3354 unsigned ldrOpc, strOpc;
3356 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3358 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3359 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
3362 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3363 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3366 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3367 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3371 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3372 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3373 MF->insert(It, loopMBB);
3374 MF->insert(It, exitMBB);
3375 exitMBB->transferSuccessors(BB);
3377 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3378 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3379 unsigned scratch2 = (!BinOpcode) ? incr :
3380 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3384 // fallthrough --> loopMBB
3385 BB->addSuccessor(loopMBB);
3389 // <binop> scratch2, dest, incr
3390 // strex scratch, scratch2, ptr
3393 // fallthrough --> exitMBB
3395 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3397 // operand order needs to go the other way for NAND
3398 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
3399 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3400 addReg(incr).addReg(dest)).addReg(0);
3402 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3403 addReg(dest).addReg(incr)).addReg(0);
3406 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
3408 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3409 .addReg(scratch).addImm(0));
3410 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3411 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3413 BB->addSuccessor(loopMBB);
3414 BB->addSuccessor(exitMBB);
3420 MF->DeleteMachineInstr(MI); // The instruction is gone now.
3426 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3427 MachineBasicBlock *BB) const {
3428 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3429 DebugLoc dl = MI->getDebugLoc();
3430 bool isThumb2 = Subtarget->isThumb2();
3431 switch (MI->getOpcode()) {
3434 llvm_unreachable("Unexpected instr type to insert");
3436 case ARM::ATOMIC_LOAD_ADD_I8:
3437 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3438 case ARM::ATOMIC_LOAD_ADD_I16:
3439 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3440 case ARM::ATOMIC_LOAD_ADD_I32:
3441 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3443 case ARM::ATOMIC_LOAD_AND_I8:
3444 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3445 case ARM::ATOMIC_LOAD_AND_I16:
3446 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3447 case ARM::ATOMIC_LOAD_AND_I32:
3448 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3450 case ARM::ATOMIC_LOAD_OR_I8:
3451 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3452 case ARM::ATOMIC_LOAD_OR_I16:
3453 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3454 case ARM::ATOMIC_LOAD_OR_I32:
3455 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3457 case ARM::ATOMIC_LOAD_XOR_I8:
3458 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3459 case ARM::ATOMIC_LOAD_XOR_I16:
3460 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3461 case ARM::ATOMIC_LOAD_XOR_I32:
3462 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3464 case ARM::ATOMIC_LOAD_NAND_I8:
3465 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3466 case ARM::ATOMIC_LOAD_NAND_I16:
3467 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3468 case ARM::ATOMIC_LOAD_NAND_I32:
3469 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3471 case ARM::ATOMIC_LOAD_SUB_I8:
3472 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3473 case ARM::ATOMIC_LOAD_SUB_I16:
3474 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3475 case ARM::ATOMIC_LOAD_SUB_I32:
3476 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3478 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
3479 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
3480 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
3482 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
3483 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
3484 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
3486 case ARM::tMOVCCr_pseudo: {
3487 // To "insert" a SELECT_CC instruction, we actually have to insert the
3488 // diamond control-flow pattern. The incoming instruction knows the
3489 // destination vreg to set, the condition code register to branch on, the
3490 // true/false values to select between, and a branch opcode to use.
3491 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3492 MachineFunction::iterator It = BB;
3498 // cmpTY ccX, r1, r2
3500 // fallthrough --> copy0MBB
3501 MachineBasicBlock *thisMBB = BB;
3502 MachineFunction *F = BB->getParent();
3503 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3504 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3505 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
3506 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
3507 F->insert(It, copy0MBB);
3508 F->insert(It, sinkMBB);
3509 // Update machine-CFG edges by first adding all successors of the current
3510 // block to the new block which will contain the Phi node for the select.
3511 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
3512 E = BB->succ_end(); I != E; ++I)
3513 sinkMBB->addSuccessor(*I);
3514 // Next, remove all successors of the current block, and add the true
3515 // and fallthrough blocks as its successors.
3516 while (!BB->succ_empty())
3517 BB->removeSuccessor(BB->succ_begin());
3518 BB->addSuccessor(copy0MBB);
3519 BB->addSuccessor(sinkMBB);
3522 // %FalseValue = ...
3523 // # fallthrough to sinkMBB
3526 // Update machine-CFG edges
3527 BB->addSuccessor(sinkMBB);
3530 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3533 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
3534 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
3535 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3537 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3544 case ARM::t2SUBrSPi_:
3545 case ARM::t2SUBrSPi12_:
3546 case ARM::t2SUBrSPs_: {
3547 MachineFunction *MF = BB->getParent();
3548 unsigned DstReg = MI->getOperand(0).getReg();
3549 unsigned SrcReg = MI->getOperand(1).getReg();
3550 bool DstIsDead = MI->getOperand(0).isDead();
3551 bool SrcIsKill = MI->getOperand(1).isKill();
3553 if (SrcReg != ARM::SP) {
3554 // Copy the source to SP from virtual register.
3555 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
3556 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3557 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
3558 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
3559 .addReg(SrcReg, getKillRegState(SrcIsKill));
3563 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
3564 switch (MI->getOpcode()) {
3566 llvm_unreachable("Unexpected pseudo instruction!");
3572 OpOpc = ARM::tADDspr;
3575 OpOpc = ARM::tSUBspi;
3577 case ARM::t2SUBrSPi_:
3578 OpOpc = ARM::t2SUBrSPi;
3579 NeedPred = true; NeedCC = true;
3581 case ARM::t2SUBrSPi12_:
3582 OpOpc = ARM::t2SUBrSPi12;
3585 case ARM::t2SUBrSPs_:
3586 OpOpc = ARM::t2SUBrSPs;
3587 NeedPred = true; NeedCC = true; NeedOp3 = true;
3590 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
3591 if (OpOpc == ARM::tAND)
3592 AddDefaultT1CC(MIB);
3593 MIB.addReg(ARM::SP);
3594 MIB.addOperand(MI->getOperand(2));
3596 MIB.addOperand(MI->getOperand(3));
3598 AddDefaultPred(MIB);
3602 // Copy the result from SP to virtual register.
3603 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
3604 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3605 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
3606 BuildMI(BB, dl, TII->get(CopyOpc))
3607 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
3609 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3615 //===----------------------------------------------------------------------===//
3616 // ARM Optimization Hooks
3617 //===----------------------------------------------------------------------===//
3620 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
3621 TargetLowering::DAGCombinerInfo &DCI) {
3622 SelectionDAG &DAG = DCI.DAG;
3623 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3624 EVT VT = N->getValueType(0);
3625 unsigned Opc = N->getOpcode();
3626 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
3627 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
3628 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
3629 ISD::CondCode CC = ISD::SETCC_INVALID;
3632 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
3634 SDValue CCOp = Slct.getOperand(0);
3635 if (CCOp.getOpcode() == ISD::SETCC)
3636 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
3639 bool DoXform = false;
3641 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
3644 if (LHS.getOpcode() == ISD::Constant &&
3645 cast<ConstantSDNode>(LHS)->isNullValue()) {
3647 } else if (CC != ISD::SETCC_INVALID &&
3648 RHS.getOpcode() == ISD::Constant &&
3649 cast<ConstantSDNode>(RHS)->isNullValue()) {
3650 std::swap(LHS, RHS);
3651 SDValue Op0 = Slct.getOperand(0);
3652 EVT OpVT = isSlctCC ? Op0.getValueType() :
3653 Op0.getOperand(0).getValueType();
3654 bool isInt = OpVT.isInteger();
3655 CC = ISD::getSetCCInverse(CC, isInt);
3657 if (!TLI.isCondCodeLegal(CC, OpVT))
3658 return SDValue(); // Inverse operator isn't legal.
3665 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
3667 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
3668 Slct.getOperand(0), Slct.getOperand(1), CC);
3669 SDValue CCOp = Slct.getOperand(0);
3671 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
3672 CCOp.getOperand(0), CCOp.getOperand(1), CC);
3673 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3674 CCOp, OtherOp, Result);
3679 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3680 static SDValue PerformADDCombine(SDNode *N,
3681 TargetLowering::DAGCombinerInfo &DCI) {
3682 // added by evan in r37685 with no testcase.
3683 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3685 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
3686 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
3687 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
3688 if (Result.getNode()) return Result;
3690 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3691 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3692 if (Result.getNode()) return Result;
3698 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
3699 static SDValue PerformSUBCombine(SDNode *N,
3700 TargetLowering::DAGCombinerInfo &DCI) {
3701 // added by evan in r37685 with no testcase.
3702 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3704 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
3705 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3706 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3707 if (Result.getNode()) return Result;
3713 static SDValue PerformMULCombine(SDNode *N,
3714 TargetLowering::DAGCombinerInfo &DCI,
3715 const ARMSubtarget *Subtarget) {
3716 SelectionDAG &DAG = DCI.DAG;
3718 if (Subtarget->isThumb1Only())
3721 if (DAG.getMachineFunction().
3722 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
3725 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
3728 EVT VT = N->getValueType(0);
3732 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
3736 uint64_t MulAmt = C->getZExtValue();
3737 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
3738 ShiftAmt = ShiftAmt & (32 - 1);
3739 SDValue V = N->getOperand(0);
3740 DebugLoc DL = N->getDebugLoc();
3743 MulAmt >>= ShiftAmt;
3744 if (isPowerOf2_32(MulAmt - 1)) {
3745 // (mul x, 2^N + 1) => (add (shl x, N), x)
3746 Res = DAG.getNode(ISD::ADD, DL, VT,
3747 V, DAG.getNode(ISD::SHL, DL, VT,
3748 V, DAG.getConstant(Log2_32(MulAmt-1),
3750 } else if (isPowerOf2_32(MulAmt + 1)) {
3751 // (mul x, 2^N - 1) => (sub (shl x, N), x)
3752 Res = DAG.getNode(ISD::SUB, DL, VT,
3753 DAG.getNode(ISD::SHL, DL, VT,
3754 V, DAG.getConstant(Log2_32(MulAmt+1),
3761 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
3762 DAG.getConstant(ShiftAmt, MVT::i32));
3764 // Do not add new nodes to DAG combiner worklist.
3765 DCI.CombineTo(N, Res, false);
3769 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
3770 /// ARMISD::VMOVRRD.
3771 static SDValue PerformVMOVRRDCombine(SDNode *N,
3772 TargetLowering::DAGCombinerInfo &DCI) {
3773 // fmrrd(fmdrr x, y) -> x,y
3774 SDValue InDouble = N->getOperand(0);
3775 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
3776 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
3780 /// getVShiftImm - Check if this is a valid build_vector for the immediate
3781 /// operand of a vector shift operation, where all the elements of the
3782 /// build_vector must have the same constant integer value.
3783 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
3784 // Ignore bit_converts.
3785 while (Op.getOpcode() == ISD::BIT_CONVERT)
3786 Op = Op.getOperand(0);
3787 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3788 APInt SplatBits, SplatUndef;
3789 unsigned SplatBitSize;
3791 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
3792 HasAnyUndefs, ElementBits) ||
3793 SplatBitSize > ElementBits)
3795 Cnt = SplatBits.getSExtValue();
3799 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
3800 /// operand of a vector shift left operation. That value must be in the range:
3801 /// 0 <= Value < ElementBits for a left shift; or
3802 /// 0 <= Value <= ElementBits for a long left shift.
3803 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
3804 assert(VT.isVector() && "vector shift count is not a vector type");
3805 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3806 if (! getVShiftImm(Op, ElementBits, Cnt))
3808 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
3811 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
3812 /// operand of a vector shift right operation. For a shift opcode, the value
3813 /// is positive, but for an intrinsic the value count must be negative. The
3814 /// absolute value must be in the range:
3815 /// 1 <= |Value| <= ElementBits for a right shift; or
3816 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
3817 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
3819 assert(VT.isVector() && "vector shift count is not a vector type");
3820 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3821 if (! getVShiftImm(Op, ElementBits, Cnt))
3825 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
3828 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
3829 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
3830 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3833 // Don't do anything for most intrinsics.
3836 // Vector shifts: check for immediate versions and lower them.
3837 // Note: This is done during DAG combining instead of DAG legalizing because
3838 // the build_vectors for 64-bit vector element shift counts are generally
3839 // not legal, and it is hard to see their values after they get legalized to
3840 // loads from a constant pool.
3841 case Intrinsic::arm_neon_vshifts:
3842 case Intrinsic::arm_neon_vshiftu:
3843 case Intrinsic::arm_neon_vshiftls:
3844 case Intrinsic::arm_neon_vshiftlu:
3845 case Intrinsic::arm_neon_vshiftn:
3846 case Intrinsic::arm_neon_vrshifts:
3847 case Intrinsic::arm_neon_vrshiftu:
3848 case Intrinsic::arm_neon_vrshiftn:
3849 case Intrinsic::arm_neon_vqshifts:
3850 case Intrinsic::arm_neon_vqshiftu:
3851 case Intrinsic::arm_neon_vqshiftsu:
3852 case Intrinsic::arm_neon_vqshiftns:
3853 case Intrinsic::arm_neon_vqshiftnu:
3854 case Intrinsic::arm_neon_vqshiftnsu:
3855 case Intrinsic::arm_neon_vqrshiftns:
3856 case Intrinsic::arm_neon_vqrshiftnu:
3857 case Intrinsic::arm_neon_vqrshiftnsu: {
3858 EVT VT = N->getOperand(1).getValueType();
3860 unsigned VShiftOpc = 0;
3863 case Intrinsic::arm_neon_vshifts:
3864 case Intrinsic::arm_neon_vshiftu:
3865 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
3866 VShiftOpc = ARMISD::VSHL;
3869 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
3870 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
3871 ARMISD::VSHRs : ARMISD::VSHRu);
3876 case Intrinsic::arm_neon_vshiftls:
3877 case Intrinsic::arm_neon_vshiftlu:
3878 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
3880 llvm_unreachable("invalid shift count for vshll intrinsic");
3882 case Intrinsic::arm_neon_vrshifts:
3883 case Intrinsic::arm_neon_vrshiftu:
3884 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
3888 case Intrinsic::arm_neon_vqshifts:
3889 case Intrinsic::arm_neon_vqshiftu:
3890 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3894 case Intrinsic::arm_neon_vqshiftsu:
3895 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3897 llvm_unreachable("invalid shift count for vqshlu intrinsic");
3899 case Intrinsic::arm_neon_vshiftn:
3900 case Intrinsic::arm_neon_vrshiftn:
3901 case Intrinsic::arm_neon_vqshiftns:
3902 case Intrinsic::arm_neon_vqshiftnu:
3903 case Intrinsic::arm_neon_vqshiftnsu:
3904 case Intrinsic::arm_neon_vqrshiftns:
3905 case Intrinsic::arm_neon_vqrshiftnu:
3906 case Intrinsic::arm_neon_vqrshiftnsu:
3907 // Narrowing shifts require an immediate right shift.
3908 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
3910 llvm_unreachable("invalid shift count for narrowing vector shift "
3914 llvm_unreachable("unhandled vector shift");
3918 case Intrinsic::arm_neon_vshifts:
3919 case Intrinsic::arm_neon_vshiftu:
3920 // Opcode already set above.
3922 case Intrinsic::arm_neon_vshiftls:
3923 case Intrinsic::arm_neon_vshiftlu:
3924 if (Cnt == VT.getVectorElementType().getSizeInBits())
3925 VShiftOpc = ARMISD::VSHLLi;
3927 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
3928 ARMISD::VSHLLs : ARMISD::VSHLLu);
3930 case Intrinsic::arm_neon_vshiftn:
3931 VShiftOpc = ARMISD::VSHRN; break;
3932 case Intrinsic::arm_neon_vrshifts:
3933 VShiftOpc = ARMISD::VRSHRs; break;
3934 case Intrinsic::arm_neon_vrshiftu:
3935 VShiftOpc = ARMISD::VRSHRu; break;
3936 case Intrinsic::arm_neon_vrshiftn:
3937 VShiftOpc = ARMISD::VRSHRN; break;
3938 case Intrinsic::arm_neon_vqshifts:
3939 VShiftOpc = ARMISD::VQSHLs; break;
3940 case Intrinsic::arm_neon_vqshiftu:
3941 VShiftOpc = ARMISD::VQSHLu; break;
3942 case Intrinsic::arm_neon_vqshiftsu:
3943 VShiftOpc = ARMISD::VQSHLsu; break;
3944 case Intrinsic::arm_neon_vqshiftns:
3945 VShiftOpc = ARMISD::VQSHRNs; break;
3946 case Intrinsic::arm_neon_vqshiftnu:
3947 VShiftOpc = ARMISD::VQSHRNu; break;
3948 case Intrinsic::arm_neon_vqshiftnsu:
3949 VShiftOpc = ARMISD::VQSHRNsu; break;
3950 case Intrinsic::arm_neon_vqrshiftns:
3951 VShiftOpc = ARMISD::VQRSHRNs; break;
3952 case Intrinsic::arm_neon_vqrshiftnu:
3953 VShiftOpc = ARMISD::VQRSHRNu; break;
3954 case Intrinsic::arm_neon_vqrshiftnsu:
3955 VShiftOpc = ARMISD::VQRSHRNsu; break;
3958 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3959 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
3962 case Intrinsic::arm_neon_vshiftins: {
3963 EVT VT = N->getOperand(1).getValueType();
3965 unsigned VShiftOpc = 0;
3967 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
3968 VShiftOpc = ARMISD::VSLI;
3969 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
3970 VShiftOpc = ARMISD::VSRI;
3972 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
3975 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3976 N->getOperand(1), N->getOperand(2),
3977 DAG.getConstant(Cnt, MVT::i32));
3980 case Intrinsic::arm_neon_vqrshifts:
3981 case Intrinsic::arm_neon_vqrshiftu:
3982 // No immediate versions of these to check for.
3989 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
3990 /// lowers them. As with the vector shift intrinsics, this is done during DAG
3991 /// combining instead of DAG legalizing because the build_vectors for 64-bit
3992 /// vector element shift counts are generally not legal, and it is hard to see
3993 /// their values after they get legalized to loads from a constant pool.
3994 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
3995 const ARMSubtarget *ST) {
3996 EVT VT = N->getValueType(0);
3998 // Nothing to be done for scalar shifts.
3999 if (! VT.isVector())
4002 assert(ST->hasNEON() && "unexpected vector shift");
4005 switch (N->getOpcode()) {
4006 default: llvm_unreachable("unexpected shift opcode");
4009 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4010 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4011 DAG.getConstant(Cnt, MVT::i32));
4016 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4017 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4018 ARMISD::VSHRs : ARMISD::VSHRu);
4019 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4020 DAG.getConstant(Cnt, MVT::i32));
4026 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4027 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4028 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4029 const ARMSubtarget *ST) {
4030 SDValue N0 = N->getOperand(0);
4032 // Check for sign- and zero-extensions of vector extract operations of 8-
4033 // and 16-bit vector elements. NEON supports these directly. They are
4034 // handled during DAG combining because type legalization will promote them
4035 // to 32-bit types and it is messy to recognize the operations after that.
4036 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4037 SDValue Vec = N0.getOperand(0);
4038 SDValue Lane = N0.getOperand(1);
4039 EVT VT = N->getValueType(0);
4040 EVT EltVT = N0.getValueType();
4041 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4043 if (VT == MVT::i32 &&
4044 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4045 TLI.isTypeLegal(Vec.getValueType())) {
4048 switch (N->getOpcode()) {
4049 default: llvm_unreachable("unexpected opcode");
4050 case ISD::SIGN_EXTEND:
4051 Opc = ARMISD::VGETLANEs;
4053 case ISD::ZERO_EXTEND:
4054 case ISD::ANY_EXTEND:
4055 Opc = ARMISD::VGETLANEu;
4058 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4065 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4066 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4067 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4068 const ARMSubtarget *ST) {
4069 // If the target supports NEON, try to use vmax/vmin instructions for f32
4070 // selects like "x < y ? x : y". Unless the FiniteOnlyFPMath option is set,
4071 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4072 // a NaN; only do the transformation when it matches that behavior.
4074 // For now only do this when using NEON for FP operations; if using VFP, it
4075 // is not obvious that the benefit outweighs the cost of switching to the
4077 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4078 N->getValueType(0) != MVT::f32)
4081 SDValue CondLHS = N->getOperand(0);
4082 SDValue CondRHS = N->getOperand(1);
4083 SDValue LHS = N->getOperand(2);
4084 SDValue RHS = N->getOperand(3);
4085 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4087 unsigned Opcode = 0;
4089 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4090 IsReversed = false; // x CC y ? x : y
4091 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4092 IsReversed = true ; // x CC y ? y : x
4106 // If LHS is NaN, an ordered comparison will be false and the result will
4107 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4108 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4109 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4110 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4112 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4113 // will return -0, so vmin can only be used for unsafe math or if one of
4114 // the operands is known to be nonzero.
4115 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4117 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4119 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
4128 // If LHS is NaN, an ordered comparison will be false and the result will
4129 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
4130 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4131 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
4132 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4134 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
4135 // will return +0, so vmax can only be used for unsafe math or if one of
4136 // the operands is known to be nonzero.
4137 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
4139 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4141 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
4147 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
4150 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
4151 DAGCombinerInfo &DCI) const {
4152 switch (N->getOpcode()) {
4154 case ISD::ADD: return PerformADDCombine(N, DCI);
4155 case ISD::SUB: return PerformSUBCombine(N, DCI);
4156 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
4157 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
4158 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
4161 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
4162 case ISD::SIGN_EXTEND:
4163 case ISD::ZERO_EXTEND:
4164 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
4165 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
4170 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
4171 if (!Subtarget->hasV6Ops())
4172 // Pre-v6 does not support unaligned mem access.
4175 // v6+ may or may not support unaligned mem access depending on the system
4177 // FIXME: This is pretty conservative. Should we provide cmdline option to
4178 // control the behaviour?
4179 if (!Subtarget->isTargetDarwin())
4183 switch (VT.getSimpleVT().SimpleTy) {
4190 // FIXME: VLD1 etc with standard alignment is legal.
4194 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
4199 switch (VT.getSimpleVT().SimpleTy) {
4200 default: return false;
4215 if ((V & (Scale - 1)) != 0)
4218 return V == (V & ((1LL << 5) - 1));
4221 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
4222 const ARMSubtarget *Subtarget) {
4229 switch (VT.getSimpleVT().SimpleTy) {
4230 default: return false;
4235 // + imm12 or - imm8
4237 return V == (V & ((1LL << 8) - 1));
4238 return V == (V & ((1LL << 12) - 1));
4241 // Same as ARM mode. FIXME: NEON?
4242 if (!Subtarget->hasVFP2())
4247 return V == (V & ((1LL << 8) - 1));
4251 /// isLegalAddressImmediate - Return true if the integer value can be used
4252 /// as the offset of the target addressing mode for load / store of the
4254 static bool isLegalAddressImmediate(int64_t V, EVT VT,
4255 const ARMSubtarget *Subtarget) {
4262 if (Subtarget->isThumb1Only())
4263 return isLegalT1AddressImmediate(V, VT);
4264 else if (Subtarget->isThumb2())
4265 return isLegalT2AddressImmediate(V, VT, Subtarget);
4270 switch (VT.getSimpleVT().SimpleTy) {
4271 default: return false;
4276 return V == (V & ((1LL << 12) - 1));
4279 return V == (V & ((1LL << 8) - 1));
4282 if (!Subtarget->hasVFP2()) // FIXME: NEON?
4287 return V == (V & ((1LL << 8) - 1));
4291 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
4293 int Scale = AM.Scale;
4297 switch (VT.getSimpleVT().SimpleTy) {
4298 default: return false;
4307 return Scale == 2 || Scale == 4 || Scale == 8;
4310 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4314 // Note, we allow "void" uses (basically, uses that aren't loads or
4315 // stores), because arm allows folding a scale into many arithmetic
4316 // operations. This should be made more precise and revisited later.
4318 // Allow r << imm, but the imm has to be a multiple of two.
4319 if (Scale & 1) return false;
4320 return isPowerOf2_32(Scale);
4324 /// isLegalAddressingMode - Return true if the addressing mode represented
4325 /// by AM is legal for this target, for a load/store of the specified type.
4326 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4327 const Type *Ty) const {
4328 EVT VT = getValueType(Ty, true);
4329 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
4332 // Can never fold addr of global into load/store.
4337 case 0: // no scale reg, must be "r+i" or "r", or "i".
4340 if (Subtarget->isThumb1Only())
4344 // ARM doesn't support any R+R*scale+imm addr modes.
4351 if (Subtarget->isThumb2())
4352 return isLegalT2ScaledAddressingMode(AM, VT);
4354 int Scale = AM.Scale;
4355 switch (VT.getSimpleVT().SimpleTy) {
4356 default: return false;
4360 if (Scale < 0) Scale = -Scale;
4364 return isPowerOf2_32(Scale & ~1);
4368 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4373 // Note, we allow "void" uses (basically, uses that aren't loads or
4374 // stores), because arm allows folding a scale into many arithmetic
4375 // operations. This should be made more precise and revisited later.
4377 // Allow r << imm, but the imm has to be a multiple of two.
4378 if (Scale & 1) return false;
4379 return isPowerOf2_32(Scale);
4386 /// isLegalICmpImmediate - Return true if the specified immediate is legal
4387 /// icmp immediate, that is the target has icmp instructions which can compare
4388 /// a register against the immediate without having to materialize the
4389 /// immediate into a register.
4390 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
4391 if (!Subtarget->isThumb())
4392 return ARM_AM::getSOImmVal(Imm) != -1;
4393 if (Subtarget->isThumb2())
4394 return ARM_AM::getT2SOImmVal(Imm) != -1;
4395 return Imm >= 0 && Imm <= 255;
4398 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
4399 bool isSEXTLoad, SDValue &Base,
4400 SDValue &Offset, bool &isInc,
4401 SelectionDAG &DAG) {
4402 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4405 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
4407 Base = Ptr->getOperand(0);
4408 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4409 int RHSC = (int)RHS->getZExtValue();
4410 if (RHSC < 0 && RHSC > -256) {
4411 assert(Ptr->getOpcode() == ISD::ADD);
4413 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4417 isInc = (Ptr->getOpcode() == ISD::ADD);
4418 Offset = Ptr->getOperand(1);
4420 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
4422 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4423 int RHSC = (int)RHS->getZExtValue();
4424 if (RHSC < 0 && RHSC > -0x1000) {
4425 assert(Ptr->getOpcode() == ISD::ADD);
4427 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4428 Base = Ptr->getOperand(0);
4433 if (Ptr->getOpcode() == ISD::ADD) {
4435 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
4436 if (ShOpcVal != ARM_AM::no_shift) {
4437 Base = Ptr->getOperand(1);
4438 Offset = Ptr->getOperand(0);
4440 Base = Ptr->getOperand(0);
4441 Offset = Ptr->getOperand(1);
4446 isInc = (Ptr->getOpcode() == ISD::ADD);
4447 Base = Ptr->getOperand(0);
4448 Offset = Ptr->getOperand(1);
4452 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
4456 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
4457 bool isSEXTLoad, SDValue &Base,
4458 SDValue &Offset, bool &isInc,
4459 SelectionDAG &DAG) {
4460 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4463 Base = Ptr->getOperand(0);
4464 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4465 int RHSC = (int)RHS->getZExtValue();
4466 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
4467 assert(Ptr->getOpcode() == ISD::ADD);
4469 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4471 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
4472 isInc = Ptr->getOpcode() == ISD::ADD;
4473 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
4481 /// getPreIndexedAddressParts - returns true by value, base pointer and
4482 /// offset pointer and addressing mode by reference if the node's address
4483 /// can be legally represented as pre-indexed load / store address.
4485 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
4487 ISD::MemIndexedMode &AM,
4488 SelectionDAG &DAG) const {
4489 if (Subtarget->isThumb1Only())
4494 bool isSEXTLoad = false;
4495 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4496 Ptr = LD->getBasePtr();
4497 VT = LD->getMemoryVT();
4498 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4499 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4500 Ptr = ST->getBasePtr();
4501 VT = ST->getMemoryVT();
4506 bool isLegal = false;
4507 if (Subtarget->isThumb2())
4508 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4509 Offset, isInc, DAG);
4511 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4512 Offset, isInc, DAG);
4516 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
4520 /// getPostIndexedAddressParts - returns true by value, base pointer and
4521 /// offset pointer and addressing mode by reference if this node can be
4522 /// combined with a load / store to form a post-indexed load / store.
4523 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
4526 ISD::MemIndexedMode &AM,
4527 SelectionDAG &DAG) const {
4528 if (Subtarget->isThumb1Only())
4533 bool isSEXTLoad = false;
4534 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4535 VT = LD->getMemoryVT();
4536 Ptr = LD->getBasePtr();
4537 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4538 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4539 VT = ST->getMemoryVT();
4540 Ptr = ST->getBasePtr();
4545 bool isLegal = false;
4546 if (Subtarget->isThumb2())
4547 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4550 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4556 // Swap base ptr and offset to catch more post-index load / store when
4557 // it's legal. In Thumb2 mode, offset must be an immediate.
4558 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
4559 !Subtarget->isThumb2())
4560 std::swap(Base, Offset);
4562 // Post-indexed load / store update the base pointer.
4567 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
4571 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
4575 const SelectionDAG &DAG,
4576 unsigned Depth) const {
4577 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4578 switch (Op.getOpcode()) {
4580 case ARMISD::CMOV: {
4581 // Bits are known zero/one if known on the LHS and RHS.
4582 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
4583 if (KnownZero == 0 && KnownOne == 0) return;
4585 APInt KnownZeroRHS, KnownOneRHS;
4586 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
4587 KnownZeroRHS, KnownOneRHS, Depth+1);
4588 KnownZero &= KnownZeroRHS;
4589 KnownOne &= KnownOneRHS;
4595 //===----------------------------------------------------------------------===//
4596 // ARM Inline Assembly Support
4597 //===----------------------------------------------------------------------===//
4599 /// getConstraintType - Given a constraint letter, return the type of
4600 /// constraint it is for this target.
4601 ARMTargetLowering::ConstraintType
4602 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
4603 if (Constraint.size() == 1) {
4604 switch (Constraint[0]) {
4606 case 'l': return C_RegisterClass;
4607 case 'w': return C_RegisterClass;
4610 return TargetLowering::getConstraintType(Constraint);
4613 std::pair<unsigned, const TargetRegisterClass*>
4614 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4616 if (Constraint.size() == 1) {
4617 // GCC ARM Constraint Letters
4618 switch (Constraint[0]) {
4620 if (Subtarget->isThumb())
4621 return std::make_pair(0U, ARM::tGPRRegisterClass);
4623 return std::make_pair(0U, ARM::GPRRegisterClass);
4625 return std::make_pair(0U, ARM::GPRRegisterClass);
4628 return std::make_pair(0U, ARM::SPRRegisterClass);
4629 if (VT.getSizeInBits() == 64)
4630 return std::make_pair(0U, ARM::DPRRegisterClass);
4631 if (VT.getSizeInBits() == 128)
4632 return std::make_pair(0U, ARM::QPRRegisterClass);
4636 if (StringRef("{cc}").equals_lower(Constraint))
4637 return std::make_pair(0U, ARM::CCRRegisterClass);
4639 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4642 std::vector<unsigned> ARMTargetLowering::
4643 getRegClassForInlineAsmConstraint(const std::string &Constraint,
4645 if (Constraint.size() != 1)
4646 return std::vector<unsigned>();
4648 switch (Constraint[0]) { // GCC ARM Constraint Letters
4651 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
4652 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
4655 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
4656 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
4657 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
4658 ARM::R12, ARM::LR, 0);
4661 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
4662 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
4663 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
4664 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
4665 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
4666 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
4667 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
4668 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
4669 if (VT.getSizeInBits() == 64)
4670 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
4671 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
4672 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
4673 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
4674 if (VT.getSizeInBits() == 128)
4675 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
4676 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
4680 return std::vector<unsigned>();
4683 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4684 /// vector. If it is invalid, don't add anything to Ops.
4685 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4688 std::vector<SDValue>&Ops,
4689 SelectionDAG &DAG) const {
4690 SDValue Result(0, 0);
4692 switch (Constraint) {
4694 case 'I': case 'J': case 'K': case 'L':
4695 case 'M': case 'N': case 'O':
4696 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4700 int64_t CVal64 = C->getSExtValue();
4701 int CVal = (int) CVal64;
4702 // None of these constraints allow values larger than 32 bits. Check
4703 // that the value fits in an int.
4707 switch (Constraint) {
4709 if (Subtarget->isThumb1Only()) {
4710 // This must be a constant between 0 and 255, for ADD
4712 if (CVal >= 0 && CVal <= 255)
4714 } else if (Subtarget->isThumb2()) {
4715 // A constant that can be used as an immediate value in a
4716 // data-processing instruction.
4717 if (ARM_AM::getT2SOImmVal(CVal) != -1)
4720 // A constant that can be used as an immediate value in a
4721 // data-processing instruction.
4722 if (ARM_AM::getSOImmVal(CVal) != -1)
4728 if (Subtarget->isThumb()) { // FIXME thumb2
4729 // This must be a constant between -255 and -1, for negated ADD
4730 // immediates. This can be used in GCC with an "n" modifier that
4731 // prints the negated value, for use with SUB instructions. It is
4732 // not useful otherwise but is implemented for compatibility.
4733 if (CVal >= -255 && CVal <= -1)
4736 // This must be a constant between -4095 and 4095. It is not clear
4737 // what this constraint is intended for. Implemented for
4738 // compatibility with GCC.
4739 if (CVal >= -4095 && CVal <= 4095)
4745 if (Subtarget->isThumb1Only()) {
4746 // A 32-bit value where only one byte has a nonzero value. Exclude
4747 // zero to match GCC. This constraint is used by GCC internally for
4748 // constants that can be loaded with a move/shift combination.
4749 // It is not useful otherwise but is implemented for compatibility.
4750 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
4752 } else if (Subtarget->isThumb2()) {
4753 // A constant whose bitwise inverse can be used as an immediate
4754 // value in a data-processing instruction. This can be used in GCC
4755 // with a "B" modifier that prints the inverted value, for use with
4756 // BIC and MVN instructions. It is not useful otherwise but is
4757 // implemented for compatibility.
4758 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
4761 // A constant whose bitwise inverse can be used as an immediate
4762 // value in a data-processing instruction. This can be used in GCC
4763 // with a "B" modifier that prints the inverted value, for use with
4764 // BIC and MVN instructions. It is not useful otherwise but is
4765 // implemented for compatibility.
4766 if (ARM_AM::getSOImmVal(~CVal) != -1)
4772 if (Subtarget->isThumb1Only()) {
4773 // This must be a constant between -7 and 7,
4774 // for 3-operand ADD/SUB immediate instructions.
4775 if (CVal >= -7 && CVal < 7)
4777 } else if (Subtarget->isThumb2()) {
4778 // A constant whose negation can be used as an immediate value in a
4779 // data-processing instruction. This can be used in GCC with an "n"
4780 // modifier that prints the negated value, for use with SUB
4781 // instructions. It is not useful otherwise but is implemented for
4783 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
4786 // A constant whose negation can be used as an immediate value in a
4787 // data-processing instruction. This can be used in GCC with an "n"
4788 // modifier that prints the negated value, for use with SUB
4789 // instructions. It is not useful otherwise but is implemented for
4791 if (ARM_AM::getSOImmVal(-CVal) != -1)
4797 if (Subtarget->isThumb()) { // FIXME thumb2
4798 // This must be a multiple of 4 between 0 and 1020, for
4799 // ADD sp + immediate.
4800 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
4803 // A power of two or a constant between 0 and 32. This is used in
4804 // GCC for the shift amount on shifted register operands, but it is
4805 // useful in general for any shift amounts.
4806 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
4812 if (Subtarget->isThumb()) { // FIXME thumb2
4813 // This must be a constant between 0 and 31, for shift amounts.
4814 if (CVal >= 0 && CVal <= 31)
4820 if (Subtarget->isThumb()) { // FIXME thumb2
4821 // This must be a multiple of 4 between -508 and 508, for
4822 // ADD/SUB sp = sp + immediate.
4823 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
4828 Result = DAG.getTargetConstant(CVal, Op.getValueType());
4832 if (Result.getNode()) {
4833 Ops.push_back(Result);
4836 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
4841 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4842 // The ARM target isn't yet aware of offsets.
4846 int ARM::getVFPf32Imm(const APFloat &FPImm) {
4847 APInt Imm = FPImm.bitcastToAPInt();
4848 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
4849 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
4850 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
4852 // We can handle 4 bits of mantissa.
4853 // mantissa = (16+UInt(e:f:g:h))/16.
4854 if (Mantissa & 0x7ffff)
4857 if ((Mantissa & 0xf) != Mantissa)
4860 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
4861 if (Exp < -3 || Exp > 4)
4863 Exp = ((Exp+3) & 0x7) ^ 4;
4865 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
4868 int ARM::getVFPf64Imm(const APFloat &FPImm) {
4869 APInt Imm = FPImm.bitcastToAPInt();
4870 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
4871 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
4872 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
4874 // We can handle 4 bits of mantissa.
4875 // mantissa = (16+UInt(e:f:g:h))/16.
4876 if (Mantissa & 0xffffffffffffLL)
4879 if ((Mantissa & 0xf) != Mantissa)
4882 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
4883 if (Exp < -3 || Exp > 4)
4885 Exp = ((Exp+3) & 0x7) ^ 4;
4887 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
4890 /// isFPImmLegal - Returns true if the target can instruction select the
4891 /// specified FP immediate natively. If false, the legalizer will
4892 /// materialize the FP immediate as a load from a constant pool.
4893 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4894 if (!Subtarget->hasVFP3())
4897 return ARM::getVFPf32Imm(Imm) != -1;
4899 return ARM::getVFPf64Imm(Imm) != -1;