1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMFrameLowering.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMSubtarget.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/LLVMContext.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/RegisterScavenging.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/BitVector.h"
40 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/Support/CommandLine.h"
43 #define GET_REGINFO_MC_DESC
44 #define GET_REGINFO_TARGET_DESC
45 #include "ARMGenRegisterInfo.inc"
50 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
51 cl::desc("Force use of virtual base registers for stack load/store"));
53 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
54 cl::desc("Enable pre-regalloc stack frame index allocation"));
56 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
57 cl::desc("Enable use of a base pointer for complex stack frames"));
59 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
60 const ARMSubtarget &sti)
61 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
63 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
68 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
69 static const unsigned CalleeSavedRegs[] = {
70 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
71 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
73 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
74 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
78 static const unsigned DarwinCalleeSavedRegs[] = {
79 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
81 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
82 ARM::R11, ARM::R10, ARM::R8,
84 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
85 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
88 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
91 BitVector ARMBaseRegisterInfo::
92 getReservedRegs(const MachineFunction &MF) const {
93 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
95 // FIXME: avoid re-calculating this every time.
96 BitVector Reserved(getNumRegs());
97 Reserved.set(ARM::SP);
98 Reserved.set(ARM::PC);
99 Reserved.set(ARM::FPSCR);
101 Reserved.set(FramePtr);
102 if (hasBasePointer(MF))
103 Reserved.set(BasePtr);
104 // Some targets reserve R9.
105 if (STI.isR9Reserved())
106 Reserved.set(ARM::R9);
107 // Reserve D16-D31 if the subtarget doesn't support them.
108 if (!STI.hasVFP3() || STI.hasD16()) {
109 assert(ARM::D31 == ARM::D16 + 15);
110 for (unsigned i = 0; i != 16; ++i)
111 Reserved.set(ARM::D16 + i);
116 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
117 unsigned Reg) const {
118 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
126 if (hasBasePointer(MF))
131 if (FramePtr == Reg && TFI->hasFP(MF))
135 return STI.isR9Reserved();
141 const TargetRegisterClass *
142 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
143 const TargetRegisterClass *B,
144 unsigned SubIdx) const {
152 if (A->getSize() == 8) {
153 if (B == &ARM::SPR_8RegClass)
154 return &ARM::DPR_8RegClass;
155 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
156 if (A == &ARM::DPR_8RegClass)
158 return &ARM::DPR_VFP2RegClass;
161 if (A->getSize() == 16) {
162 if (B == &ARM::SPR_8RegClass)
163 return &ARM::QPR_8RegClass;
164 return &ARM::QPR_VFP2RegClass;
167 if (A->getSize() == 32) {
168 if (B == &ARM::SPR_8RegClass)
169 return 0; // Do not allow coalescing!
170 return &ARM::QQPR_VFP2RegClass;
173 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
174 return 0; // Do not allow coalescing!
181 if (A->getSize() == 16) {
182 if (B == &ARM::DPR_VFP2RegClass)
183 return &ARM::QPR_VFP2RegClass;
184 if (B == &ARM::DPR_8RegClass)
185 return 0; // Do not allow coalescing!
189 if (A->getSize() == 32) {
190 if (B == &ARM::DPR_VFP2RegClass)
191 return &ARM::QQPR_VFP2RegClass;
192 if (B == &ARM::DPR_8RegClass)
193 return 0; // Do not allow coalescing!
197 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
198 if (B != &ARM::DPRRegClass)
199 return 0; // Do not allow coalescing!
206 // D sub-registers of QQQQ registers.
207 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
209 return 0; // Do not allow coalescing!
215 if (A->getSize() == 32) {
216 if (B == &ARM::QPR_VFP2RegClass)
217 return &ARM::QQPR_VFP2RegClass;
218 if (B == &ARM::QPR_8RegClass)
219 return 0; // Do not allow coalescing!
223 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
224 if (B == &ARM::QPRRegClass)
226 return 0; // Do not allow coalescing!
230 // Q sub-registers of QQQQ registers.
231 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
233 return 0; // Do not allow coalescing!
240 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
241 SmallVectorImpl<unsigned> &SubIndices,
242 unsigned &NewSubIdx) const {
244 unsigned Size = RC->getSize() * 8;
248 NewSubIdx = 0; // Whole register.
249 unsigned NumRegs = SubIndices.size();
251 // 8 D registers -> 1 QQQQ register.
252 return (Size == 512 &&
253 SubIndices[0] == ARM::dsub_0 &&
254 SubIndices[1] == ARM::dsub_1 &&
255 SubIndices[2] == ARM::dsub_2 &&
256 SubIndices[3] == ARM::dsub_3 &&
257 SubIndices[4] == ARM::dsub_4 &&
258 SubIndices[5] == ARM::dsub_5 &&
259 SubIndices[6] == ARM::dsub_6 &&
260 SubIndices[7] == ARM::dsub_7);
261 } else if (NumRegs == 4) {
262 if (SubIndices[0] == ARM::qsub_0) {
263 // 4 Q registers -> 1 QQQQ register.
264 return (Size == 512 &&
265 SubIndices[1] == ARM::qsub_1 &&
266 SubIndices[2] == ARM::qsub_2 &&
267 SubIndices[3] == ARM::qsub_3);
268 } else if (SubIndices[0] == ARM::dsub_0) {
269 // 4 D registers -> 1 QQ register.
271 SubIndices[1] == ARM::dsub_1 &&
272 SubIndices[2] == ARM::dsub_2 &&
273 SubIndices[3] == ARM::dsub_3) {
275 NewSubIdx = ARM::qqsub_0;
278 } else if (SubIndices[0] == ARM::dsub_4) {
279 // 4 D registers -> 1 QQ register (2nd).
281 SubIndices[1] == ARM::dsub_5 &&
282 SubIndices[2] == ARM::dsub_6 &&
283 SubIndices[3] == ARM::dsub_7) {
284 NewSubIdx = ARM::qqsub_1;
287 } else if (SubIndices[0] == ARM::ssub_0) {
288 // 4 S registers -> 1 Q register.
290 SubIndices[1] == ARM::ssub_1 &&
291 SubIndices[2] == ARM::ssub_2 &&
292 SubIndices[3] == ARM::ssub_3) {
294 NewSubIdx = ARM::qsub_0;
298 } else if (NumRegs == 2) {
299 if (SubIndices[0] == ARM::qsub_0) {
300 // 2 Q registers -> 1 QQ register.
301 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
303 NewSubIdx = ARM::qqsub_0;
306 } else if (SubIndices[0] == ARM::qsub_2) {
307 // 2 Q registers -> 1 QQ register (2nd).
308 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
309 NewSubIdx = ARM::qqsub_1;
312 } else if (SubIndices[0] == ARM::dsub_0) {
313 // 2 D registers -> 1 Q register.
314 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
316 NewSubIdx = ARM::qsub_0;
319 } else if (SubIndices[0] == ARM::dsub_2) {
320 // 2 D registers -> 1 Q register (2nd).
321 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
322 NewSubIdx = ARM::qsub_1;
325 } else if (SubIndices[0] == ARM::dsub_4) {
326 // 2 D registers -> 1 Q register (3rd).
327 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
328 NewSubIdx = ARM::qsub_2;
331 } else if (SubIndices[0] == ARM::dsub_6) {
332 // 2 D registers -> 1 Q register (3rd).
333 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
334 NewSubIdx = ARM::qsub_3;
337 } else if (SubIndices[0] == ARM::ssub_0) {
338 // 2 S registers -> 1 D register.
339 if (SubIndices[1] == ARM::ssub_1) {
341 NewSubIdx = ARM::dsub_0;
344 } else if (SubIndices[0] == ARM::ssub_2) {
345 // 2 S registers -> 1 D register (2nd).
346 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
347 NewSubIdx = ARM::dsub_1;
355 const TargetRegisterClass*
356 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
358 const TargetRegisterClass *Super = RC;
359 TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
361 switch (Super->getID()) {
362 case ARM::GPRRegClassID:
363 case ARM::SPRRegClassID:
364 case ARM::DPRRegClassID:
365 case ARM::QPRRegClassID:
366 case ARM::QQPRRegClassID:
367 case ARM::QQQQPRRegClassID:
375 const TargetRegisterClass *
376 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
377 return ARM::GPRRegisterClass;
381 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
382 MachineFunction &MF) const {
383 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
385 switch (RC->getID()) {
388 case ARM::tGPRRegClassID:
389 return TFI->hasFP(MF) ? 4 : 5;
390 case ARM::GPRRegClassID: {
391 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
392 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
394 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
395 case ARM::DPRRegClassID:
400 /// getRawAllocationOrder - Returns the register allocation order for a
401 /// specified register class with a target-dependent hint.
403 ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
404 unsigned HintType, unsigned HintReg,
405 const MachineFunction &MF) const {
406 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
407 // Alternative register allocation orders when favoring even / odd registers
408 // of register pairs.
410 // No FP, R9 is available.
411 static const unsigned GPREven1[] = {
412 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
413 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
416 static const unsigned GPROdd1[] = {
417 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
418 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
422 // FP is R7, R9 is available.
423 static const unsigned GPREven2[] = {
424 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
425 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
428 static const unsigned GPROdd2[] = {
429 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
430 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
434 // FP is R11, R9 is available.
435 static const unsigned GPREven3[] = {
436 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
437 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
440 static const unsigned GPROdd3[] = {
441 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
442 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
446 // No FP, R9 is not available.
447 static const unsigned GPREven4[] = {
448 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
449 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
452 static const unsigned GPROdd4[] = {
453 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
454 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
458 // FP is R7, R9 is not available.
459 static const unsigned GPREven5[] = {
460 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
461 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
464 static const unsigned GPROdd5[] = {
465 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
466 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
470 // FP is R11, R9 is not available.
471 static const unsigned GPREven6[] = {
472 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
473 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
475 static const unsigned GPROdd6[] = {
476 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
477 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
480 // We only support even/odd hints for GPR and rGPR.
481 if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
482 return RC->getRawAllocationOrder(MF);
484 if (HintType == ARMRI::RegPairEven) {
485 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
486 // It's no longer possible to fulfill this hint. Return the default
488 return RC->getRawAllocationOrder(MF);
490 if (!TFI->hasFP(MF)) {
491 if (!STI.isR9Reserved())
492 return ArrayRef<unsigned>(GPREven1);
494 return ArrayRef<unsigned>(GPREven4);
495 } else if (FramePtr == ARM::R7) {
496 if (!STI.isR9Reserved())
497 return ArrayRef<unsigned>(GPREven2);
499 return ArrayRef<unsigned>(GPREven5);
500 } else { // FramePtr == ARM::R11
501 if (!STI.isR9Reserved())
502 return ArrayRef<unsigned>(GPREven3);
504 return ArrayRef<unsigned>(GPREven6);
506 } else if (HintType == ARMRI::RegPairOdd) {
507 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
508 // It's no longer possible to fulfill this hint. Return the default
510 return RC->getRawAllocationOrder(MF);
512 if (!TFI->hasFP(MF)) {
513 if (!STI.isR9Reserved())
514 return ArrayRef<unsigned>(GPROdd1);
516 return ArrayRef<unsigned>(GPROdd4);
517 } else if (FramePtr == ARM::R7) {
518 if (!STI.isR9Reserved())
519 return ArrayRef<unsigned>(GPROdd2);
521 return ArrayRef<unsigned>(GPROdd5);
522 } else { // FramePtr == ARM::R11
523 if (!STI.isR9Reserved())
524 return ArrayRef<unsigned>(GPROdd3);
526 return ArrayRef<unsigned>(GPROdd6);
529 return RC->getRawAllocationOrder(MF);
532 /// ResolveRegAllocHint - Resolves the specified register allocation hint
533 /// to a physical register. Returns the physical register if it is successful.
535 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
536 const MachineFunction &MF) const {
537 if (Reg == 0 || !isPhysicalRegister(Reg))
541 else if (Type == (unsigned)ARMRI::RegPairOdd)
543 return getRegisterPairOdd(Reg, MF);
544 else if (Type == (unsigned)ARMRI::RegPairEven)
546 return getRegisterPairEven(Reg, MF);
551 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
552 MachineFunction &MF) const {
553 MachineRegisterInfo *MRI = &MF.getRegInfo();
554 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
555 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
556 Hint.first == (unsigned)ARMRI::RegPairEven) &&
557 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
558 // If 'Reg' is one of the even / odd register pair and it's now changed
559 // (e.g. coalesced) into a different register. The other register of the
560 // pair allocation hint must be updated to reflect the relationship
562 unsigned OtherReg = Hint.second;
563 Hint = MRI->getRegAllocationHint(OtherReg);
564 if (Hint.second == Reg)
565 // Make sure the pair has not already divorced.
566 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
571 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
572 // CortexA9 has a Write-after-write hazard for NEON registers.
573 if (!STI.isCortexA9())
576 switch (RC->getID()) {
577 case ARM::DPRRegClassID:
578 case ARM::DPR_8RegClassID:
579 case ARM::DPR_VFP2RegClassID:
580 case ARM::QPRRegClassID:
581 case ARM::QPR_8RegClassID:
582 case ARM::QPR_VFP2RegClassID:
583 case ARM::SPRRegClassID:
584 case ARM::SPR_8RegClassID:
585 // Avoid reusing S, D, and Q registers.
586 // Don't increase register pressure for QQ and QQQQ.
593 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
594 const MachineFrameInfo *MFI = MF.getFrameInfo();
595 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
597 if (!EnableBasePointer)
600 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
603 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
604 // negative range for ldr/str (255), and thumb1 is positive offsets only.
605 // It's going to be better to use the SP or Base Pointer instead. When there
606 // are variable sized objects, we can't reference off of the SP, so we
607 // reserve a Base Pointer.
608 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
609 // Conservatively estimate whether the negative offset from the frame
610 // pointer will be sufficient to reach. If a function has a smallish
611 // frame, it's less likely to have lots of spills and callee saved
612 // space, so it's all more likely to be within range of the frame pointer.
613 // If it's wrong, the scavenger will still enable access to work, it just
615 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
623 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
624 const MachineFrameInfo *MFI = MF.getFrameInfo();
625 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
626 // We can't realign the stack if:
627 // 1. Dynamic stack realignment is explicitly disabled,
628 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
629 // 3. There are VLAs in the function and the base pointer is disabled.
630 return (RealignStack && !AFI->isThumb1OnlyFunction() &&
631 (!MFI->hasVarSizedObjects() || EnableBasePointer));
634 bool ARMBaseRegisterInfo::
635 needsStackRealignment(const MachineFunction &MF) const {
636 const MachineFrameInfo *MFI = MF.getFrameInfo();
637 const Function *F = MF.getFunction();
638 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
639 bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
640 F->hasFnAttr(Attribute::StackAlignment));
642 return requiresRealignment && canRealignStack(MF);
645 bool ARMBaseRegisterInfo::
646 cannotEliminateFrame(const MachineFunction &MF) const {
647 const MachineFrameInfo *MFI = MF.getFrameInfo();
648 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
650 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
651 || needsStackRealignment(MF);
654 unsigned ARMBaseRegisterInfo::getRARegister() const {
659 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
660 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
667 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
668 llvm_unreachable("What is the exception register");
672 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
673 llvm_unreachable("What is the exception handler register");
677 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
678 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
681 int ARMBaseRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
682 return ARMGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
685 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
686 const MachineFunction &MF) const {
689 // Return 0 if either register of the pair is a special register.
698 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
701 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
703 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
775 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
776 const MachineFunction &MF) const {
779 // Return 0 if either register of the pair is a special register.
788 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
791 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
793 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
865 /// emitLoadConstPool - Emits a load from constpool to materialize the
866 /// specified immediate.
867 void ARMBaseRegisterInfo::
868 emitLoadConstPool(MachineBasicBlock &MBB,
869 MachineBasicBlock::iterator &MBBI,
871 unsigned DestReg, unsigned SubIdx, int Val,
872 ARMCC::CondCodes Pred,
873 unsigned PredReg, unsigned MIFlags) const {
874 MachineFunction &MF = *MBB.getParent();
875 MachineConstantPool *ConstantPool = MF.getConstantPool();
877 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
878 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
880 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
881 .addReg(DestReg, getDefRegState(true), SubIdx)
882 .addConstantPoolIndex(Idx)
883 .addImm(0).addImm(Pred).addReg(PredReg)
884 .setMIFlags(MIFlags);
887 bool ARMBaseRegisterInfo::
888 requiresRegisterScavenging(const MachineFunction &MF) const {
892 bool ARMBaseRegisterInfo::
893 requiresFrameIndexScavenging(const MachineFunction &MF) const {
897 bool ARMBaseRegisterInfo::
898 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
899 return EnableLocalStackAlloc;
903 emitSPUpdate(bool isARM,
904 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
905 DebugLoc dl, const ARMBaseInstrInfo &TII,
907 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
909 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
912 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
917 void ARMBaseRegisterInfo::
918 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
919 MachineBasicBlock::iterator I) const {
920 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
921 if (!TFI->hasReservedCallFrame(MF)) {
922 // If we have alloca, convert as follows:
923 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
924 // ADJCALLSTACKUP -> add, sp, sp, amount
925 MachineInstr *Old = I;
926 DebugLoc dl = Old->getDebugLoc();
927 unsigned Amount = Old->getOperand(0).getImm();
929 // We need to keep the stack aligned properly. To do this, we round the
930 // amount of space needed for the outgoing arguments up to the next
931 // alignment boundary.
932 unsigned Align = TFI->getStackAlignment();
933 Amount = (Amount+Align-1)/Align*Align;
935 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
936 assert(!AFI->isThumb1OnlyFunction() &&
937 "This eliminateCallFramePseudoInstr does not support Thumb1!");
938 bool isARM = !AFI->isThumbFunction();
940 // Replace the pseudo instruction with a new instruction...
941 unsigned Opc = Old->getOpcode();
942 int PIdx = Old->findFirstPredOperandIdx();
943 ARMCC::CondCodes Pred = (PIdx == -1)
944 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
945 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
946 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
947 unsigned PredReg = Old->getOperand(2).getReg();
948 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
950 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
951 unsigned PredReg = Old->getOperand(3).getReg();
952 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
953 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
960 int64_t ARMBaseRegisterInfo::
961 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
962 const MCInstrDesc &Desc = MI->getDesc();
963 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
964 int64_t InstrOffs = 0;;
968 case ARMII::AddrModeT2_i8:
969 case ARMII::AddrModeT2_i12:
970 case ARMII::AddrMode_i12:
971 InstrOffs = MI->getOperand(Idx+1).getImm();
974 case ARMII::AddrMode5: {
976 const MachineOperand &OffOp = MI->getOperand(Idx+1);
977 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
978 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
979 InstrOffs = -InstrOffs;
983 case ARMII::AddrMode2: {
985 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
986 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
987 InstrOffs = -InstrOffs;
990 case ARMII::AddrMode3: {
992 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
993 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
994 InstrOffs = -InstrOffs;
997 case ARMII::AddrModeT1_s: {
999 InstrOffs = MI->getOperand(ImmIdx).getImm();
1004 llvm_unreachable("Unsupported addressing mode!");
1008 return InstrOffs * Scale;
1011 /// needsFrameBaseReg - Returns true if the instruction's frame index
1012 /// reference would be better served by a base register other than FP
1013 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1014 /// references it should create new base registers for.
1015 bool ARMBaseRegisterInfo::
1016 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1017 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
1018 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1021 // It's the load/store FI references that cause issues, as it can be difficult
1022 // to materialize the offset if it won't fit in the literal field. Estimate
1023 // based on the size of the local frame and some conservative assumptions
1024 // about the rest of the stack frame (note, this is pre-regalloc, so
1025 // we don't know everything for certain yet) whether this offset is likely
1026 // to be out of range of the immediate. Return true if so.
1028 // We only generate virtual base registers for loads and stores, so
1029 // return false for everything else.
1030 unsigned Opc = MI->getOpcode();
1032 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
1033 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
1034 case ARM::t2LDRi12: case ARM::t2LDRi8:
1035 case ARM::t2STRi12: case ARM::t2STRi8:
1036 case ARM::VLDRS: case ARM::VLDRD:
1037 case ARM::VSTRS: case ARM::VSTRD:
1038 case ARM::tSTRspi: case ARM::tLDRspi:
1039 if (ForceAllBaseRegAlloc)
1046 // Without a virtual base register, if the function has variable sized
1047 // objects, all fixed-size local references will be via the frame pointer,
1048 // Approximate the offset and see if it's legal for the instruction.
1049 // Note that the incoming offset is based on the SP value at function entry,
1050 // so it'll be negative.
1051 MachineFunction &MF = *MI->getParent()->getParent();
1052 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
1053 MachineFrameInfo *MFI = MF.getFrameInfo();
1054 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1056 // Estimate an offset from the frame pointer.
1057 // Conservatively assume all callee-saved registers get pushed. R4-R6
1058 // will be earlier than the FP, so we ignore those.
1060 int64_t FPOffset = Offset - 8;
1061 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1062 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1064 // Estimate an offset from the stack pointer.
1065 // The incoming offset is relating to the SP at the start of the function,
1066 // but when we access the local it'll be relative to the SP after local
1067 // allocation, so adjust our SP-relative offset by that allocation size.
1069 Offset += MFI->getLocalFrameSize();
1070 // Assume that we'll have at least some spill slots allocated.
1071 // FIXME: This is a total SWAG number. We should run some statistics
1072 // and pick a real one.
1073 Offset += 128; // 128 bytes of spill slots
1075 // If there is a frame pointer, try using it.
1076 // The FP is only available if there is no dynamic realignment. We
1077 // don't know for sure yet whether we'll need that, so we guess based
1078 // on whether there are any local variables that would trigger it.
1079 unsigned StackAlign = TFI->getStackAlignment();
1080 if (TFI->hasFP(MF) &&
1081 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1082 if (isFrameOffsetLegal(MI, FPOffset))
1085 // If we can reference via the stack pointer, try that.
1086 // FIXME: This (and the code that resolves the references) can be improved
1087 // to only disallow SP relative references in the live range of
1088 // the VLA(s). In practice, it's unclear how much difference that
1089 // would make, but it may be worth doing.
1090 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1093 // The offset likely isn't legal, we want to allocate a virtual base register.
1097 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
1098 /// be a pointer to FrameIdx at the beginning of the basic block.
1099 void ARMBaseRegisterInfo::
1100 materializeFrameBaseRegister(MachineBasicBlock *MBB,
1101 unsigned BaseReg, int FrameIdx,
1102 int64_t Offset) const {
1103 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
1104 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1105 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1107 MachineBasicBlock::iterator Ins = MBB->begin();
1108 DebugLoc DL; // Defaults to "unknown"
1109 if (Ins != MBB->end())
1110 DL = Ins->getDebugLoc();
1112 const MCInstrDesc &MCID = TII.get(ADDriOpc);
1113 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1114 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this));
1116 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1117 .addFrameIndex(FrameIdx).addImm(Offset);
1119 if (!AFI->isThumb1OnlyFunction())
1120 AddDefaultCC(AddDefaultPred(MIB));
1124 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1125 unsigned BaseReg, int64_t Offset) const {
1126 MachineInstr &MI = *I;
1127 MachineBasicBlock &MBB = *MI.getParent();
1128 MachineFunction &MF = *MBB.getParent();
1129 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1130 int Off = Offset; // ARM doesn't need the general 64-bit offsets
1133 assert(!AFI->isThumb1OnlyFunction() &&
1134 "This resolveFrameIndex does not support Thumb1!");
1136 while (!MI.getOperand(i).isFI()) {
1138 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1141 if (!AFI->isThumbFunction())
1142 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1144 assert(AFI->isThumb2Function());
1145 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1147 assert (Done && "Unable to resolve frame index!");
1150 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1151 int64_t Offset) const {
1152 const MCInstrDesc &Desc = MI->getDesc();
1153 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1156 while (!MI->getOperand(i).isFI()) {
1158 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1161 // AddrMode4 and AddrMode6 cannot handle any offset.
1162 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1165 unsigned NumBits = 0;
1167 bool isSigned = true;
1169 case ARMII::AddrModeT2_i8:
1170 case ARMII::AddrModeT2_i12:
1171 // i8 supports only negative, and i12 supports only positive, so
1172 // based on Offset sign, consider the appropriate instruction
1181 case ARMII::AddrMode5:
1182 // VFP address mode.
1186 case ARMII::AddrMode_i12:
1187 case ARMII::AddrMode2:
1190 case ARMII::AddrMode3:
1193 case ARMII::AddrModeT1_s:
1199 llvm_unreachable("Unsupported addressing mode!");
1203 Offset += getFrameIndexInstrOffset(MI, i);
1204 // Make sure the offset is encodable for instructions that scale the
1206 if ((Offset & (Scale-1)) != 0)
1209 if (isSigned && Offset < 0)
1212 unsigned Mask = (1 << NumBits) - 1;
1213 if ((unsigned)Offset <= Mask * Scale)
1220 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1221 int SPAdj, RegScavenger *RS) const {
1223 MachineInstr &MI = *II;
1224 MachineBasicBlock &MBB = *MI.getParent();
1225 MachineFunction &MF = *MBB.getParent();
1226 const ARMFrameLowering *TFI =
1227 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1228 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1229 assert(!AFI->isThumb1OnlyFunction() &&
1230 "This eliminateFrameIndex does not support Thumb1!");
1232 while (!MI.getOperand(i).isFI()) {
1234 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1237 int FrameIndex = MI.getOperand(i).getIndex();
1240 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1242 // Special handling of dbg_value instructions.
1243 if (MI.isDebugValue()) {
1244 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1245 MI.getOperand(i+1).ChangeToImmediate(Offset);
1249 // Modify MI as necessary to handle as much of 'Offset' as possible
1251 if (!AFI->isThumbFunction())
1252 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1254 assert(AFI->isThumb2Function());
1255 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1260 // If we get here, the immediate doesn't fit into the instruction. We folded
1261 // as much as possible above, handle the rest, providing a register that is
1264 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1265 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1266 "This code isn't needed if offset already handled!");
1268 unsigned ScratchReg = 0;
1269 int PIdx = MI.findFirstPredOperandIdx();
1270 ARMCC::CondCodes Pred = (PIdx == -1)
1271 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1272 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1274 // Must be addrmode4/6.
1275 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1277 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1278 if (!AFI->isThumbFunction())
1279 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1280 Offset, Pred, PredReg, TII);
1282 assert(AFI->isThumb2Function());
1283 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1284 Offset, Pred, PredReg, TII);
1286 // Update the original instruction to use the scratch register.
1287 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1288 if (MI.getOpcode() == ARM::t2ADDrSPi)
1289 MI.setDesc(TII.get(ARM::t2ADDri));
1290 else if (MI.getOpcode() == ARM::t2SUBrSPi)
1291 MI.setDesc(TII.get(ARM::t2SUBri));