1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
17 #define _USE_MATH_DEFINES
21 #include "SIISelLowering.h"
23 #include "AMDGPUDiagnosticInfoUnsupported.h"
24 #include "AMDGPUIntrinsicInfo.h"
25 #include "AMDGPUSubtarget.h"
26 #include "SIInstrInfo.h"
27 #include "SIMachineFunctionInfo.h"
28 #include "SIRegisterInfo.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/ADT/SmallString.h"
39 SITargetLowering::SITargetLowering(TargetMachine &TM,
40 const AMDGPUSubtarget &STI)
41 : AMDGPUTargetLowering(TM, STI) {
42 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
43 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
45 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
46 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
48 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
49 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
51 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
52 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
53 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
55 addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass);
56 addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass);
58 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
59 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
61 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
62 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
64 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
65 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
67 computeRegisterProperties(STI.getRegisterInfo());
69 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
70 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
71 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
72 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
74 setOperationAction(ISD::ADD, MVT::i32, Legal);
75 setOperationAction(ISD::ADDC, MVT::i32, Legal);
76 setOperationAction(ISD::ADDE, MVT::i32, Legal);
77 setOperationAction(ISD::SUBC, MVT::i32, Legal);
78 setOperationAction(ISD::SUBE, MVT::i32, Legal);
80 setOperationAction(ISD::FSIN, MVT::f32, Custom);
81 setOperationAction(ISD::FCOS, MVT::f32, Custom);
83 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
84 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
86 // We need to custom lower vector stores from local memory
87 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
88 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
89 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
91 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
92 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
94 setOperationAction(ISD::STORE, MVT::i1, Custom);
95 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
97 setOperationAction(ISD::SELECT, MVT::i64, Custom);
98 setOperationAction(ISD::SELECT, MVT::f64, Promote);
99 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
101 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
102 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
103 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
104 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
106 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
107 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
109 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
126 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
127 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
128 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
129 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
131 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
132 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
134 for (MVT VT : MVT::integer_valuetypes()) {
138 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
139 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
141 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
143 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
144 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
145 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
146 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
148 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
149 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
150 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
151 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
154 for (MVT VT : MVT::integer_vector_valuetypes()) {
155 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i16, Expand);
156 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v16i16, Expand);
159 for (MVT VT : MVT::fp_valuetypes())
160 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
162 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
163 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
165 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
166 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
167 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
168 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
171 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
173 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
174 setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand);
176 setOperationAction(ISD::LOAD, MVT::i1, Custom);
178 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
179 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
181 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
182 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
184 setOperationAction(ISD::ConstantPool, MVT::v2i64, Expand);
186 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
187 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
188 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
190 // These should use UDIVREM, so set them to expand
191 setOperationAction(ISD::UDIV, MVT::i64, Expand);
192 setOperationAction(ISD::UREM, MVT::i64, Expand);
194 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
195 setOperationAction(ISD::SELECT, MVT::i1, Promote);
197 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
200 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
202 // We only support LOAD/STORE and vector manipulation ops for vectors
203 // with > 4 elements.
204 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64}) {
205 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
209 case ISD::BUILD_VECTOR:
211 case ISD::EXTRACT_VECTOR_ELT:
212 case ISD::INSERT_VECTOR_ELT:
213 case ISD::INSERT_SUBVECTOR:
214 case ISD::EXTRACT_SUBVECTOR:
215 case ISD::SCALAR_TO_VECTOR:
217 case ISD::CONCAT_VECTORS:
218 setOperationAction(Op, VT, Custom);
221 setOperationAction(Op, VT, Expand);
227 // Most operations are naturally 32-bit vector operations. We only support
228 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
229 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
230 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
231 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
233 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
234 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
236 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
237 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
239 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
240 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
243 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
244 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
245 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
246 setOperationAction(ISD::FRINT, MVT::f64, Legal);
249 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
250 setOperationAction(ISD::FDIV, MVT::f32, Custom);
251 setOperationAction(ISD::FDIV, MVT::f64, Custom);
253 setTargetDAGCombine(ISD::FADD);
254 setTargetDAGCombine(ISD::FSUB);
255 setTargetDAGCombine(ISD::FMINNUM);
256 setTargetDAGCombine(ISD::FMAXNUM);
257 setTargetDAGCombine(ISD::SMIN);
258 setTargetDAGCombine(ISD::SMAX);
259 setTargetDAGCombine(ISD::UMIN);
260 setTargetDAGCombine(ISD::UMAX);
261 setTargetDAGCombine(ISD::SELECT_CC);
262 setTargetDAGCombine(ISD::SETCC);
263 setTargetDAGCombine(ISD::AND);
264 setTargetDAGCombine(ISD::OR);
265 setTargetDAGCombine(ISD::UINT_TO_FP);
267 // All memory operations. Some folding on the pointer operand is done to help
268 // matching the constant offsets in the addressing modes.
269 setTargetDAGCombine(ISD::LOAD);
270 setTargetDAGCombine(ISD::STORE);
271 setTargetDAGCombine(ISD::ATOMIC_LOAD);
272 setTargetDAGCombine(ISD::ATOMIC_STORE);
273 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
274 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
275 setTargetDAGCombine(ISD::ATOMIC_SWAP);
276 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
277 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
278 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
279 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
280 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
281 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
282 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
283 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
284 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
285 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
287 setSchedulingPreference(Sched::RegPressure);
290 //===----------------------------------------------------------------------===//
291 // TargetLowering queries
292 //===----------------------------------------------------------------------===//
294 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
296 // SI has some legal vector types, but no legal vector operations. Say no
297 // shuffles are legal in order to prefer scalarizing some vector operations.
301 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
302 // Flat instructions do not have offsets, and only have the register
304 return AM.BaseOffs == 0 && (AM.Scale == 0 || AM.Scale == 1);
307 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
308 // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
309 // additionally can do r + r + i with addr64. 32-bit has more addressing
310 // mode options. Depending on the resource constant, it can also do
311 // (i64 r0) + (i32 r1) * (i14 i).
313 // Private arrays end up using a scratch buffer most of the time, so also
314 // assume those use MUBUF instructions. Scratch loads / stores are currently
315 // implemented as mubuf instructions with offen bit set, so slightly
316 // different than the normal addr64.
317 if (!isUInt<12>(AM.BaseOffs))
320 // FIXME: Since we can split immediate into soffset and immediate offset,
321 // would it make sense to allow any immediate?
324 case 0: // r + i or just i, depending on HasBaseReg.
327 return true; // We have r + r or r + i.
334 // Allow 2 * r as r + r
335 // Or 2 * r + i is allowed as r + r + i.
337 default: // Don't allow n * r
342 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
343 const AddrMode &AM, Type *Ty,
345 // No global is ever allowed as a base.
350 case AMDGPUAS::GLOBAL_ADDRESS: {
351 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
352 // Assume the we will use FLAT for all global memory accesses
354 // FIXME: This assumption is currently wrong. On VI we still use
355 // MUBUF instructions for the r + i addressing mode. As currently
356 // implemented, the MUBUF instructions only work on buffer < 4GB.
357 // It may be possible to support > 4GB buffers with MUBUF instructions,
358 // by setting the stride value in the resource descriptor which would
359 // increase the size limit to (stride * 4GB). However, this is risky,
360 // because it has never been validated.
361 return isLegalFlatAddressingMode(AM);
364 return isLegalMUBUFAddressingMode(AM);
366 case AMDGPUAS::CONSTANT_ADDRESS: {
367 // If the offset isn't a multiple of 4, it probably isn't going to be
368 // correctly aligned.
369 if (AM.BaseOffs % 4 != 0)
370 return isLegalMUBUFAddressingMode(AM);
372 // There are no SMRD extloads, so if we have to do a small type access we
373 // will use a MUBUF load.
374 // FIXME?: We also need to do this if unaligned, but we don't know the
376 if (DL.getTypeStoreSize(Ty) < 4)
377 return isLegalMUBUFAddressingMode(AM);
379 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
380 // SMRD instructions have an 8-bit, dword offset on SI.
381 if (!isUInt<8>(AM.BaseOffs / 4))
383 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) {
384 // On CI+, this can also be a 32-bit literal constant offset. If it fits
385 // in 8-bits, it can use a smaller encoding.
386 if (!isUInt<32>(AM.BaseOffs / 4))
388 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS) {
389 // On VI, these use the SMEM format and the offset is 20-bit in bytes.
390 if (!isUInt<20>(AM.BaseOffs))
393 llvm_unreachable("unhandled generation");
395 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
398 if (AM.Scale == 1 && AM.HasBaseReg)
404 case AMDGPUAS::PRIVATE_ADDRESS:
405 case AMDGPUAS::UNKNOWN_ADDRESS_SPACE:
406 return isLegalMUBUFAddressingMode(AM);
408 case AMDGPUAS::LOCAL_ADDRESS:
409 case AMDGPUAS::REGION_ADDRESS: {
410 // Basic, single offset DS instructions allow a 16-bit unsigned immediate
412 // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
413 // an 8-bit dword offset but we don't know the alignment here.
414 if (!isUInt<16>(AM.BaseOffs))
417 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
420 if (AM.Scale == 1 && AM.HasBaseReg)
425 case AMDGPUAS::FLAT_ADDRESS:
426 return isLegalFlatAddressingMode(AM);
429 llvm_unreachable("unhandled address space");
433 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
436 bool *IsFast) const {
440 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
441 // which isn't a simple VT.
442 if (!VT.isSimple() || VT == MVT::Other)
445 // TODO - CI+ supports unaligned memory accesses, but this requires driver
448 // XXX - The only mention I see of this in the ISA manual is for LDS direct
449 // reads the "byte address and must be dword aligned". Is it also true for the
450 // normal loads and stores?
451 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS) {
452 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
453 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
454 // with adjacent offsets.
455 bool AlignedBy4 = (Align % 4 == 0);
457 *IsFast = AlignedBy4;
461 // Smaller than dword value must be aligned.
462 // FIXME: This should be allowed on CI+
463 if (VT.bitsLT(MVT::i32))
466 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
467 // byte-address are ignored, thus forcing Dword alignment.
468 // This applies to private, global, and constant memory.
472 return VT.bitsGT(MVT::i32) && Align % 4 == 0;
475 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
476 unsigned SrcAlign, bool IsMemset,
479 MachineFunction &MF) const {
480 // FIXME: Should account for address space here.
482 // The default fallback uses the private pointer size as a guess for a type to
483 // use. Make sure we switch these to 64-bit accesses.
485 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
488 if (Size >= 8 && DstAlign >= 4)
495 static bool isFlatGlobalAddrSpace(unsigned AS) {
496 return AS == AMDGPUAS::GLOBAL_ADDRESS ||
497 AS == AMDGPUAS::FLAT_ADDRESS ||
498 AS == AMDGPUAS::CONSTANT_ADDRESS;
501 bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
502 unsigned DestAS) const {
503 return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
506 TargetLoweringBase::LegalizeTypeAction
507 SITargetLowering::getPreferredVectorAction(EVT VT) const {
508 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
509 return TypeSplitVector;
511 return TargetLoweringBase::getPreferredVectorAction(VT);
514 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
516 const SIInstrInfo *TII =
517 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
518 return TII->isInlineConstant(Imm);
521 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
522 SDLoc SL, SDValue Chain,
523 unsigned Offset, bool Signed) const {
524 const DataLayout &DL = DAG.getDataLayout();
525 MachineFunction &MF = DAG.getMachineFunction();
526 const SIRegisterInfo *TRI =
527 static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
528 unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
530 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
532 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
533 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
534 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
535 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
536 MRI.getLiveInVirtReg(InputPtrReg), PtrVT);
537 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
538 DAG.getConstant(Offset, SL, PtrVT));
539 SDValue PtrOffset = DAG.getUNDEF(PtrVT);
540 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
542 unsigned Align = DL.getABITypeAlignment(Ty);
544 ISD::LoadExtType ExtTy = Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
545 if (MemVT.isFloatingPoint())
546 ExtTy = ISD::EXTLOAD;
548 return DAG.getLoad(ISD::UNINDEXED, ExtTy,
549 VT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemVT,
551 true, // isNonTemporal
556 SDValue SITargetLowering::LowerFormalArguments(
557 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
558 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
559 SmallVectorImpl<SDValue> &InVals) const {
560 const SIRegisterInfo *TRI =
561 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
563 MachineFunction &MF = DAG.getMachineFunction();
564 FunctionType *FType = MF.getFunction()->getFunctionType();
565 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
566 const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
568 if (Subtarget->isAmdHsaOS() && Info->getShaderType() != ShaderType::COMPUTE) {
569 const Function *Fn = MF.getFunction();
570 DiagnosticInfoUnsupported NoGraphicsHSA(*Fn, "non-compute shaders with HSA");
571 DAG.getContext()->diagnose(NoGraphicsHSA);
575 // FIXME: We currently assume all calling conventions are kernels.
577 SmallVector<ISD::InputArg, 16> Splits;
578 BitVector Skipped(Ins.size());
580 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
581 const ISD::InputArg &Arg = Ins[i];
583 // First check if it's a PS input addr
584 if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
585 !Arg.Flags.isByVal()) {
587 assert((PSInputNum <= 15) && "Too many PS inputs!");
590 // We can safely skip PS inputs
596 Info->PSInputAddr |= 1 << PSInputNum++;
599 // Second split vertices into their elements
600 if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) {
601 ISD::InputArg NewArg = Arg;
602 NewArg.Flags.setSplit();
603 NewArg.VT = Arg.VT.getVectorElementType();
605 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
606 // three or five element vertex only needs three or five registers,
607 // NOT four or eight.
608 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
609 unsigned NumElements = ParamType->getVectorNumElements();
611 for (unsigned j = 0; j != NumElements; ++j) {
612 Splits.push_back(NewArg);
613 NewArg.PartOffset += NewArg.VT.getStoreSize();
616 } else if (Info->getShaderType() != ShaderType::COMPUTE) {
617 Splits.push_back(Arg);
621 SmallVector<CCValAssign, 16> ArgLocs;
622 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
625 // At least one interpolation mode must be enabled or else the GPU will hang.
626 if (Info->getShaderType() == ShaderType::PIXEL &&
627 (Info->PSInputAddr & 0x7F) == 0) {
628 Info->PSInputAddr |= 1;
629 CCInfo.AllocateReg(AMDGPU::VGPR0);
630 CCInfo.AllocateReg(AMDGPU::VGPR1);
633 if (Info->getShaderType() == ShaderType::COMPUTE) {
634 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
638 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
639 if (Info->hasPrivateSegmentBuffer()) {
640 unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);
641 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);
642 CCInfo.AllocateReg(PrivateSegmentBufferReg);
645 if (Info->hasDispatchPtr()) {
646 unsigned DispatchPtrReg = Info->addDispatchPtr(*TRI);
647 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SReg_64RegClass);
648 CCInfo.AllocateReg(DispatchPtrReg);
651 if (Info->hasKernargSegmentPtr()) {
652 unsigned InputPtrReg = Info->addKernargSegmentPtr(*TRI);
653 MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
654 CCInfo.AllocateReg(InputPtrReg);
657 AnalyzeFormalArguments(CCInfo, Splits);
659 SmallVector<SDValue, 16> Chains;
661 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
663 const ISD::InputArg &Arg = Ins[i];
665 InVals.push_back(DAG.getUNDEF(Arg.VT));
669 CCValAssign &VA = ArgLocs[ArgIdx++];
670 MVT VT = VA.getLocVT();
674 EVT MemVT = Splits[i].VT;
675 const unsigned Offset = Subtarget->getExplicitKernelArgOffset() +
676 VA.getLocMemOffset();
677 // The first 36 bytes of the input buffer contains information about
678 // thread group and global sizes.
679 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, Chain,
680 Offset, Ins[i].Flags.isSExt());
681 Chains.push_back(Arg.getValue(1));
684 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
685 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
686 ParamTy && ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
687 // On SI local pointers are just offsets into LDS, so they are always
688 // less than 16-bits. On CI and newer they could potentially be
689 // real pointers, so we can't guarantee their size.
690 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
691 DAG.getValueType(MVT::i16));
694 InVals.push_back(Arg);
695 Info->ABIArgOffset = Offset + MemVT.getStoreSize();
698 assert(VA.isRegLoc() && "Parameter must be in a register!");
700 unsigned Reg = VA.getLocReg();
702 if (VT == MVT::i64) {
703 // For now assume it is a pointer
704 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
705 &AMDGPU::SReg_64RegClass);
706 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
707 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
708 InVals.push_back(Copy);
712 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
714 Reg = MF.addLiveIn(Reg, RC);
715 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
717 if (Arg.VT.isVector()) {
719 // Build a vector from the registers
720 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
721 unsigned NumElements = ParamType->getVectorNumElements();
723 SmallVector<SDValue, 4> Regs;
725 for (unsigned j = 1; j != NumElements; ++j) {
726 Reg = ArgLocs[ArgIdx++].getLocReg();
727 Reg = MF.addLiveIn(Reg, RC);
729 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
730 Regs.push_back(Copy);
733 // Fill up the missing vector elements
734 NumElements = Arg.VT.getVectorNumElements() - NumElements;
735 Regs.append(NumElements, DAG.getUNDEF(VT));
737 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
741 InVals.push_back(Val);
744 // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
745 // these from the dispatch pointer.
747 // Start adding system SGPRs.
748 if (Info->hasWorkGroupIDX()) {
749 unsigned Reg = Info->addWorkGroupIDX();
750 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
751 CCInfo.AllocateReg(Reg);
753 llvm_unreachable("work group id x is always enabled");
755 if (Info->hasWorkGroupIDY()) {
756 unsigned Reg = Info->addWorkGroupIDY();
757 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
758 CCInfo.AllocateReg(Reg);
761 if (Info->hasWorkGroupIDZ()) {
762 unsigned Reg = Info->addWorkGroupIDZ();
763 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
764 CCInfo.AllocateReg(Reg);
767 if (Info->hasWorkGroupInfo()) {
768 unsigned Reg = Info->addWorkGroupInfo();
769 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
770 CCInfo.AllocateReg(Reg);
773 if (Info->hasPrivateSegmentWaveByteOffset()) {
774 // Scratch wave offset passed in system SGPR.
775 unsigned PrivateSegmentWaveByteOffsetReg
776 = Info->addPrivateSegmentWaveByteOffset();
778 MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
779 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
782 // Now that we've figured out where the scratch register inputs are, see if
783 // should reserve the arguments and use them directly.
785 bool HasStackObjects = MF.getFrameInfo()->hasStackObjects();
787 if (ST.isAmdHsaOS()) {
788 // TODO: Assume we will spill without optimizations.
789 if (HasStackObjects) {
790 // If we have stack objects, we unquestionably need the private buffer
791 // resource. For the HSA ABI, this will be the first 4 user SGPR
792 // inputs. We can reserve those and use them directly.
794 unsigned PrivateSegmentBufferReg = TRI->getPreloadedValue(
795 MF, SIRegisterInfo::PRIVATE_SEGMENT_BUFFER);
796 Info->setScratchRSrcReg(PrivateSegmentBufferReg);
798 unsigned PrivateSegmentWaveByteOffsetReg = TRI->getPreloadedValue(
799 MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
800 Info->setScratchWaveOffsetReg(PrivateSegmentWaveByteOffsetReg);
802 unsigned ReservedBufferReg
803 = TRI->reservedPrivateSegmentBufferReg(MF);
804 unsigned ReservedOffsetReg
805 = TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
807 // We tentatively reserve the last registers (skipping the last two
808 // which may contain VCC). After register allocation, we'll replace
809 // these with the ones immediately after those which were really
810 // allocated. In the prologue copies will be inserted from the argument
811 // to these reserved registers.
812 Info->setScratchRSrcReg(ReservedBufferReg);
813 Info->setScratchWaveOffsetReg(ReservedOffsetReg);
816 unsigned ReservedBufferReg = TRI->reservedPrivateSegmentBufferReg(MF);
818 // Without HSA, relocations are used for the scratch pointer and the
819 // buffer resource setup is always inserted in the prologue. Scratch wave
820 // offset is still in an input SGPR.
821 Info->setScratchRSrcReg(ReservedBufferReg);
823 if (HasStackObjects) {
824 unsigned ScratchWaveOffsetReg = TRI->getPreloadedValue(
825 MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
826 Info->setScratchWaveOffsetReg(ScratchWaveOffsetReg);
828 unsigned ReservedOffsetReg
829 = TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
830 Info->setScratchWaveOffsetReg(ReservedOffsetReg);
834 if (Info->hasWorkItemIDX()) {
835 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_X);
836 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
837 CCInfo.AllocateReg(Reg);
839 llvm_unreachable("workitem id x should always be enabled");
841 if (Info->hasWorkItemIDY()) {
842 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Y);
843 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
844 CCInfo.AllocateReg(Reg);
847 if (Info->hasWorkItemIDZ()) {
848 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Z);
849 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
850 CCInfo.AllocateReg(Reg);
856 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
859 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
860 MachineInstr * MI, MachineBasicBlock * BB) const {
862 switch (MI->getOpcode()) {
864 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
871 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
872 // This currently forces unfolding various combinations of fsub into fma with
873 // free fneg'd operands. As long as we have fast FMA (controlled by
874 // isFMAFasterThanFMulAndFAdd), we should perform these.
876 // When fma is quarter rate, for f64 where add / sub are at best half rate,
877 // most of these combines appear to be cycle neutral but save on instruction
878 // count / code size.
882 EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
884 if (!VT.isVector()) {
887 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
890 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const {
894 // Answering this is somewhat tricky and depends on the specific device which
895 // have different rates for fma or all f64 operations.
897 // v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
898 // regardless of which device (although the number of cycles differs between
899 // devices), so it is always profitable for f64.
901 // v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
902 // only on full rate devices. Normally, we should prefer selecting v_mad_f32
903 // which we can always do even without fused FP ops since it returns the same
904 // result as the separate operations and since it is always full
905 // rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
906 // however does not support denormals, so we do report fma as faster if we have
907 // a fast fma device and require denormals.
909 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
910 VT = VT.getScalarType();
915 switch (VT.getSimpleVT().SimpleTy) {
917 // This is as fast on some subtargets. However, we always have full rate f32
918 // mad available which returns the same result as the separate operations
919 // which we should prefer over fma. We can't use this if we want to support
920 // denormals, so only report this in these cases.
921 return Subtarget->hasFP32Denormals() && Subtarget->hasFastFMAF32();
931 //===----------------------------------------------------------------------===//
932 // Custom DAG Lowering Operations
933 //===----------------------------------------------------------------------===//
935 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
936 switch (Op.getOpcode()) {
937 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
938 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
939 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
941 SDValue Result = LowerLOAD(Op, DAG);
942 assert((!Result.getNode() ||
943 Result.getNode()->getNumValues() == 2) &&
944 "Load should return a value and a chain");
950 return LowerTrig(Op, DAG);
951 case ISD::SELECT: return LowerSELECT(Op, DAG);
952 case ISD::FDIV: return LowerFDIV(Op, DAG);
953 case ISD::STORE: return LowerSTORE(Op, DAG);
954 case ISD::GlobalAddress: {
955 MachineFunction &MF = DAG.getMachineFunction();
956 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
957 return LowerGlobalAddress(MFI, Op, DAG);
959 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
960 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
965 /// \brief Helper function for LowerBRCOND
966 static SDNode *findUser(SDValue Value, unsigned Opcode) {
968 SDNode *Parent = Value.getNode();
969 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
972 if (I.getUse().get() != Value)
975 if (I->getOpcode() == Opcode)
981 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
984 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
985 unsigned FrameIndex = FINode->getIndex();
987 // A FrameIndex node represents a 32-bit offset into scratch memory. If
988 // the high bit of a frame index offset were to be set, this would mean
989 // that it represented an offset of ~2GB * 64 = ~128GB from the start of the
990 // scratch buffer, with 64 being the number of threads per wave.
992 // If we know the machine uses less than 128GB of scratch, then we can
993 // amrk the high bit of the FrameIndex node as known zero,
994 // which is important, because it means in most situations we can
995 // prove that values derived from FrameIndex nodes are non-negative.
996 // This enables us to take advantage of more addressing modes when
997 // accessing scratch buffers, since for scratch reads/writes, the register
998 // offset must always be positive.
1000 SDValue TFI = DAG.getTargetFrameIndex(FrameIndex, MVT::i32);
1001 if (Subtarget->enableHugeScratchBuffer())
1004 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, TFI,
1005 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 31)));
1008 /// This transforms the control flow intrinsics to get the branch destination as
1009 /// last parameter, also switches branch target with BR if the need arise
1010 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
1011 SelectionDAG &DAG) const {
1015 SDNode *Intr = BRCOND.getOperand(1).getNode();
1016 SDValue Target = BRCOND.getOperand(2);
1017 SDNode *BR = nullptr;
1019 if (Intr->getOpcode() == ISD::SETCC) {
1020 // As long as we negate the condition everything is fine
1021 SDNode *SetCC = Intr;
1022 assert(SetCC->getConstantOperandVal(1) == 1);
1023 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
1025 Intr = SetCC->getOperand(0).getNode();
1028 // Get the target from BR if we don't negate the condition
1029 BR = findUser(BRCOND, ISD::BR);
1030 Target = BR->getOperand(1);
1033 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
1035 // Build the result and
1036 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
1038 // operands of the new intrinsic call
1039 SmallVector<SDValue, 4> Ops;
1040 Ops.push_back(BRCOND.getOperand(0));
1041 Ops.append(Intr->op_begin() + 1, Intr->op_end());
1042 Ops.push_back(Target);
1044 // build the new intrinsic call
1045 SDNode *Result = DAG.getNode(
1046 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
1047 DAG.getVTList(Res), Ops).getNode();
1050 // Give the branch instruction our target
1053 BRCOND.getOperand(2)
1055 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
1056 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
1057 BR = NewBR.getNode();
1060 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
1062 // Copy the intrinsic results to registers
1063 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
1064 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
1068 Chain = DAG.getCopyToReg(
1070 CopyToReg->getOperand(1),
1071 SDValue(Result, i - 1),
1074 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
1077 // Remove the old intrinsic from the chain
1078 DAG.ReplaceAllUsesOfValueWith(
1079 SDValue(Intr, Intr->getNumValues() - 1),
1080 Intr->getOperand(0));
1085 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
1087 SelectionDAG &DAG) const {
1088 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
1090 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
1091 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
1094 const GlobalValue *GV = GSD->getGlobal();
1095 MVT PtrVT = getPointerTy(DAG.getDataLayout(), GSD->getAddressSpace());
1097 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
1098 return DAG.getNode(AMDGPUISD::CONST_DATA_PTR, DL, PtrVT, GA);
1101 SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL,
1103 // We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
1104 // so we will end up with redundant moves to m0.
1106 // We can't use S_MOV_B32, because there is no way to specify m0 as the
1107 // destination register.
1109 // We have to use them both. Machine cse will combine all the S_MOV_B32
1110 // instructions and the register coalescer eliminate the extra copies.
1111 SDNode *M0 = DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, V.getValueType(), V);
1112 return DAG.getCopyToReg(Chain, DL, DAG.getRegister(AMDGPU::M0, MVT::i32),
1113 SDValue(M0, 0), SDValue()); // Glue
1114 // A Null SDValue creates
1118 SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
1121 unsigned Offset) const {
1123 SDValue Param = LowerParameter(DAG, MVT::i32, MVT::i32, SL,
1124 DAG.getEntryNode(), Offset, false);
1125 // The local size values will have the hi 16-bits as zero.
1126 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
1127 DAG.getValueType(VT));
1130 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
1131 SelectionDAG &DAG) const {
1132 MachineFunction &MF = DAG.getMachineFunction();
1133 auto MFI = MF.getInfo<SIMachineFunctionInfo>();
1134 const SIRegisterInfo *TRI =
1135 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
1137 EVT VT = Op.getValueType();
1139 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1141 // TODO: Should this propagate fast-math-flags?
1143 switch (IntrinsicID) {
1144 case Intrinsic::amdgcn_dispatch_ptr:
1145 return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass,
1146 TRI->getPreloadedValue(MF, SIRegisterInfo::DISPATCH_PTR), VT);
1148 case Intrinsic::r600_read_ngroups_x:
1149 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1150 SI::KernelInputOffsets::NGROUPS_X, false);
1151 case Intrinsic::r600_read_ngroups_y:
1152 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1153 SI::KernelInputOffsets::NGROUPS_Y, false);
1154 case Intrinsic::r600_read_ngroups_z:
1155 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1156 SI::KernelInputOffsets::NGROUPS_Z, false);
1157 case Intrinsic::r600_read_global_size_x:
1158 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1159 SI::KernelInputOffsets::GLOBAL_SIZE_X, false);
1160 case Intrinsic::r600_read_global_size_y:
1161 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1162 SI::KernelInputOffsets::GLOBAL_SIZE_Y, false);
1163 case Intrinsic::r600_read_global_size_z:
1164 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1165 SI::KernelInputOffsets::GLOBAL_SIZE_Z, false);
1166 case Intrinsic::r600_read_local_size_x:
1167 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1168 SI::KernelInputOffsets::LOCAL_SIZE_X);
1169 case Intrinsic::r600_read_local_size_y:
1170 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1171 SI::KernelInputOffsets::LOCAL_SIZE_Y);
1172 case Intrinsic::r600_read_local_size_z:
1173 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1174 SI::KernelInputOffsets::LOCAL_SIZE_Z);
1175 case Intrinsic::AMDGPU_read_workdim:
1176 // Really only 2 bits.
1177 return lowerImplicitZextParam(DAG, Op, MVT::i8,
1178 getImplicitParameterOffset(MFI, GRID_DIM));
1179 case Intrinsic::r600_read_tgid_x:
1180 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1181 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_X), VT);
1182 case Intrinsic::r600_read_tgid_y:
1183 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1184 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Y), VT);
1185 case Intrinsic::r600_read_tgid_z:
1186 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1187 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Z), VT);
1188 case Intrinsic::r600_read_tidig_x:
1189 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1190 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_X), VT);
1191 case Intrinsic::r600_read_tidig_y:
1192 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1193 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Y), VT);
1194 case Intrinsic::r600_read_tidig_z:
1195 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1196 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Z), VT);
1197 case AMDGPUIntrinsic::SI_load_const: {
1203 MachineMemOperand *MMO = MF.getMachineMemOperand(
1204 MachinePointerInfo(),
1205 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
1206 VT.getStoreSize(), 4);
1207 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
1208 Op->getVTList(), Ops, VT, MMO);
1210 case AMDGPUIntrinsic::SI_sample:
1211 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
1212 case AMDGPUIntrinsic::SI_sampleb:
1213 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
1214 case AMDGPUIntrinsic::SI_sampled:
1215 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
1216 case AMDGPUIntrinsic::SI_samplel:
1217 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
1218 case AMDGPUIntrinsic::SI_vs_load_input:
1219 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
1224 case AMDGPUIntrinsic::AMDGPU_fract:
1225 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
1226 return DAG.getNode(ISD::FSUB, DL, VT, Op.getOperand(1),
1227 DAG.getNode(ISD::FFLOOR, DL, VT, Op.getOperand(1)));
1228 case AMDGPUIntrinsic::SI_fs_constant: {
1229 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1230 SDValue Glue = M0.getValue(1);
1231 return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32,
1232 DAG.getConstant(2, DL, MVT::i32), // P0
1233 Op.getOperand(1), Op.getOperand(2), Glue);
1235 case AMDGPUIntrinsic::SI_packf16:
1236 if (Op.getOperand(1).isUndef() && Op.getOperand(2).isUndef())
1237 return DAG.getUNDEF(MVT::i32);
1239 case AMDGPUIntrinsic::SI_fs_interp: {
1240 SDValue IJ = Op.getOperand(4);
1241 SDValue I = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
1242 DAG.getConstant(0, DL, MVT::i32));
1243 SDValue J = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
1244 DAG.getConstant(1, DL, MVT::i32));
1245 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1246 SDValue Glue = M0.getValue(1);
1247 SDValue P1 = DAG.getNode(AMDGPUISD::INTERP_P1, DL,
1248 DAG.getVTList(MVT::f32, MVT::Glue),
1249 I, Op.getOperand(1), Op.getOperand(2), Glue);
1250 Glue = SDValue(P1.getNode(), 1);
1251 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, P1, J,
1252 Op.getOperand(1), Op.getOperand(2), Glue);
1255 return AMDGPUTargetLowering::LowerOperation(Op, DAG);
1259 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1260 SelectionDAG &DAG) const {
1261 MachineFunction &MF = DAG.getMachineFunction();
1263 SDValue Chain = Op.getOperand(0);
1264 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1266 switch (IntrinsicID) {
1267 case AMDGPUIntrinsic::SI_sendmsg: {
1268 Chain = copyToM0(DAG, Chain, DL, Op.getOperand(3));
1269 SDValue Glue = Chain.getValue(1);
1270 return DAG.getNode(AMDGPUISD::SENDMSG, DL, MVT::Other, Chain,
1271 Op.getOperand(2), Glue);
1273 case AMDGPUIntrinsic::SI_tbuffer_store: {
1291 EVT VT = Op.getOperand(3).getValueType();
1293 MachineMemOperand *MMO = MF.getMachineMemOperand(
1294 MachinePointerInfo(),
1295 MachineMemOperand::MOStore,
1296 VT.getStoreSize(), 4);
1297 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
1298 Op->getVTList(), Ops, VT, MMO);
1305 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1307 LoadSDNode *Load = cast<LoadSDNode>(Op);
1309 if (Op.getValueType().isVector()) {
1310 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
1311 "Custom lowering for non-i32 vectors hasn't been implemented.");
1312 unsigned NumElements = Op.getValueType().getVectorNumElements();
1313 assert(NumElements != 2 && "v2 loads are supported for all address spaces.");
1315 switch (Load->getAddressSpace()) {
1317 case AMDGPUAS::GLOBAL_ADDRESS:
1318 case AMDGPUAS::PRIVATE_ADDRESS:
1319 if (NumElements >= 8)
1320 return SplitVectorLoad(Op, DAG);
1322 // v4 loads are supported for private and global memory.
1323 if (NumElements <= 4)
1326 case AMDGPUAS::LOCAL_ADDRESS:
1327 // If properly aligned, if we split we might be able to use ds_read_b64.
1328 return SplitVectorLoad(Op, DAG);
1332 return AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1335 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
1337 SelectionDAG &DAG) const {
1338 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
1344 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
1345 if (Op.getValueType() != MVT::i64)
1349 SDValue Cond = Op.getOperand(0);
1351 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1352 SDValue One = DAG.getConstant(1, DL, MVT::i32);
1354 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
1355 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
1357 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
1358 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
1360 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
1362 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
1363 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
1365 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
1367 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
1368 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
1371 // Catch division cases where we can use shortcuts with rcp and rsq
1373 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
1375 SDValue LHS = Op.getOperand(0);
1376 SDValue RHS = Op.getOperand(1);
1377 EVT VT = Op.getValueType();
1378 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
1380 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
1381 if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals())) &&
1382 CLHS->isExactlyValue(1.0)) {
1383 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
1384 // the CI documentation has a worst case error of 1 ulp.
1385 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
1386 // use it as long as we aren't trying to use denormals.
1388 // 1.0 / sqrt(x) -> rsq(x)
1390 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
1391 // error seems really high at 2^29 ULP.
1392 if (RHS.getOpcode() == ISD::FSQRT)
1393 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
1395 // 1.0 / x -> rcp(x)
1396 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1401 // Turn into multiply by the reciprocal.
1402 // x / y -> x * (1.0 / y)
1404 Flags.setUnsafeAlgebra(true);
1405 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1406 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip, &Flags);
1412 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
1413 SDValue FastLowered = LowerFastFDIV(Op, DAG);
1414 if (FastLowered.getNode())
1417 // This uses v_rcp_f32 which does not handle denormals. Let this hit a
1418 // selection error for now rather than do something incorrect.
1419 if (Subtarget->hasFP32Denormals())
1423 SDValue LHS = Op.getOperand(0);
1424 SDValue RHS = Op.getOperand(1);
1426 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
1428 const APFloat K0Val(BitsToFloat(0x6f800000));
1429 const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
1431 const APFloat K1Val(BitsToFloat(0x2f800000));
1432 const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
1434 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
1437 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
1439 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
1441 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
1443 // TODO: Should this propagate fast-math-flags?
1445 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
1447 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
1449 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
1451 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
1454 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
1455 if (DAG.getTarget().Options.UnsafeFPMath)
1456 return LowerFastFDIV(Op, DAG);
1459 SDValue X = Op.getOperand(0);
1460 SDValue Y = Op.getOperand(1);
1462 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1464 SDVTList ScaleVT = DAG.getVTList(MVT::f64, MVT::i1);
1466 SDValue DivScale0 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, Y, Y, X);
1468 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0);
1470 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0);
1472 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One);
1474 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp);
1476 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One);
1478 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X);
1480 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1);
1481 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3);
1483 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64,
1484 NegDivScale0, Mul, DivScale1);
1488 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1489 // Workaround a hardware bug on SI where the condition output from div_scale
1492 const SDValue Hi = DAG.getConstant(1, SL, MVT::i32);
1494 // Figure out if the scale to use for div_fmas.
1495 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
1496 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y);
1497 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0);
1498 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1);
1500 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi);
1501 SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi);
1504 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi);
1506 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi);
1508 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ);
1509 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ);
1510 Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen);
1512 Scale = DivScale1.getValue(1);
1515 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64,
1516 Fma4, Fma3, Mul, Scale);
1518 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f64, Fmas, Y, X);
1521 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
1522 EVT VT = Op.getValueType();
1525 return LowerFDIV32(Op, DAG);
1528 return LowerFDIV64(Op, DAG);
1530 llvm_unreachable("Unexpected type for fdiv");
1533 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1535 StoreSDNode *Store = cast<StoreSDNode>(Op);
1536 EVT VT = Store->getMemoryVT();
1538 // These stores are legal.
1539 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
1540 if (VT.isVector() && VT.getVectorNumElements() > 4)
1541 return ScalarizeVectorStore(Op, DAG);
1545 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1549 if (VT.isVector() && VT.getVectorNumElements() >= 8)
1550 return SplitVectorStore(Op, DAG);
1553 return DAG.getTruncStore(Store->getChain(), DL,
1554 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
1555 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
1560 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1562 EVT VT = Op.getValueType();
1563 SDValue Arg = Op.getOperand(0);
1564 // TODO: Should this propagate fast-math-flags?
1565 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
1566 DAG.getNode(ISD::FMUL, DL, VT, Arg,
1567 DAG.getConstantFP(0.5/M_PI, DL,
1570 switch (Op.getOpcode()) {
1572 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
1574 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
1576 llvm_unreachable("Wrong trig opcode");
1580 //===----------------------------------------------------------------------===//
1581 // Custom DAG optimizations
1582 //===----------------------------------------------------------------------===//
1584 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1585 DAGCombinerInfo &DCI) const {
1586 EVT VT = N->getValueType(0);
1587 EVT ScalarVT = VT.getScalarType();
1588 if (ScalarVT != MVT::f32)
1591 SelectionDAG &DAG = DCI.DAG;
1594 SDValue Src = N->getOperand(0);
1595 EVT SrcVT = Src.getValueType();
1597 // TODO: We could try to match extracting the higher bytes, which would be
1598 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1599 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1600 // about in practice.
1601 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1602 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1603 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1604 DCI.AddToWorklist(Cvt.getNode());
1609 // We are primarily trying to catch operations on illegal vector types
1610 // before they are expanded.
1611 // For scalars, we can use the more flexible method of checking masked bits
1612 // after legalization.
1613 if (!DCI.isBeforeLegalize() ||
1614 !SrcVT.isVector() ||
1615 SrcVT.getVectorElementType() != MVT::i8) {
1619 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1621 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1623 unsigned NElts = SrcVT.getVectorNumElements();
1624 if (!SrcVT.isSimple() && NElts != 3)
1627 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1628 // prevent a mess from expanding to v4i32 and repacking.
1629 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1630 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1631 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1632 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1633 LoadSDNode *Load = cast<LoadSDNode>(Src);
1635 unsigned AS = Load->getAddressSpace();
1636 unsigned Align = Load->getAlignment();
1637 Type *Ty = LoadVT.getTypeForEVT(*DAG.getContext());
1638 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
1640 // Don't try to replace the load if we have to expand it due to alignment
1641 // problems. Otherwise we will end up scalarizing the load, and trying to
1642 // repack into the vector for no real reason.
1643 if (Align < ABIAlignment &&
1644 !allowsMisalignedMemoryAccesses(LoadVT, AS, Align, nullptr)) {
1648 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1652 Load->getMemOperand());
1654 // Make sure successors of the original load stay after it by updating
1655 // them to use the new Chain.
1656 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1658 SmallVector<SDValue, 4> Elts;
1659 if (RegVT.isVector())
1660 DAG.ExtractVectorElements(NewLoad, Elts);
1662 Elts.push_back(NewLoad);
1664 SmallVector<SDValue, 4> Ops;
1666 unsigned EltIdx = 0;
1667 for (SDValue Elt : Elts) {
1668 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1669 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1670 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1671 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1672 DCI.AddToWorklist(Cvt.getNode());
1679 assert(Ops.size() == NElts);
1681 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1687 /// \brief Return true if the given offset Size in bytes can be folded into
1688 /// the immediate offsets of a memory instruction for the given address space.
1689 static bool canFoldOffset(unsigned OffsetSize, unsigned AS,
1690 const AMDGPUSubtarget &STI) {
1692 case AMDGPUAS::GLOBAL_ADDRESS: {
1693 // MUBUF instructions a 12-bit offset in bytes.
1694 return isUInt<12>(OffsetSize);
1696 case AMDGPUAS::CONSTANT_ADDRESS: {
1697 // SMRD instructions have an 8-bit offset in dwords on SI and
1698 // a 20-bit offset in bytes on VI.
1699 if (STI.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1700 return isUInt<20>(OffsetSize);
1702 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
1704 case AMDGPUAS::LOCAL_ADDRESS:
1705 case AMDGPUAS::REGION_ADDRESS: {
1706 // The single offset versions have a 16-bit offset in bytes.
1707 return isUInt<16>(OffsetSize);
1709 case AMDGPUAS::PRIVATE_ADDRESS:
1710 // Indirect register addressing does not use any offsets.
1716 // (shl (add x, c1), c2) -> add (shl x, c2), (shl c1, c2)
1718 // This is a variant of
1719 // (mul (add x, c1), c2) -> add (mul x, c2), (mul c1, c2),
1721 // The normal DAG combiner will do this, but only if the add has one use since
1722 // that would increase the number of instructions.
1724 // This prevents us from seeing a constant offset that can be folded into a
1725 // memory instruction's addressing mode. If we know the resulting add offset of
1726 // a pointer can be folded into an addressing offset, we can replace the pointer
1727 // operand with the add of new constant offset. This eliminates one of the uses,
1728 // and may allow the remaining use to also be simplified.
1730 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
1732 DAGCombinerInfo &DCI) const {
1733 SDValue N0 = N->getOperand(0);
1734 SDValue N1 = N->getOperand(1);
1736 if (N0.getOpcode() != ISD::ADD)
1739 const ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N1);
1743 const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1747 // If the resulting offset is too large, we can't fold it into the addressing
1749 APInt Offset = CAdd->getAPIntValue() << CN1->getAPIntValue();
1750 if (!canFoldOffset(Offset.getZExtValue(), AddrSpace, *Subtarget))
1753 SelectionDAG &DAG = DCI.DAG;
1755 EVT VT = N->getValueType(0);
1757 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
1758 SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32);
1760 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset);
1763 SDValue SITargetLowering::performAndCombine(SDNode *N,
1764 DAGCombinerInfo &DCI) const {
1765 if (DCI.isBeforeLegalize())
1768 SelectionDAG &DAG = DCI.DAG;
1770 // (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
1771 // fp_class x, ~(s_nan | q_nan | n_infinity | p_infinity)
1772 SDValue LHS = N->getOperand(0);
1773 SDValue RHS = N->getOperand(1);
1775 if (LHS.getOpcode() == ISD::SETCC &&
1776 RHS.getOpcode() == ISD::SETCC) {
1777 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
1778 ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
1780 SDValue X = LHS.getOperand(0);
1781 SDValue Y = RHS.getOperand(0);
1782 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
1785 if (LCC == ISD::SETO) {
1786 if (X != LHS.getOperand(1))
1789 if (RCC == ISD::SETUNE) {
1790 const ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(RHS.getOperand(1));
1791 if (!C1 || !C1->isInfinity() || C1->isNegative())
1794 const uint32_t Mask = SIInstrFlags::N_NORMAL |
1795 SIInstrFlags::N_SUBNORMAL |
1796 SIInstrFlags::N_ZERO |
1797 SIInstrFlags::P_ZERO |
1798 SIInstrFlags::P_SUBNORMAL |
1799 SIInstrFlags::P_NORMAL;
1801 static_assert(((~(SIInstrFlags::S_NAN |
1802 SIInstrFlags::Q_NAN |
1803 SIInstrFlags::N_INFINITY |
1804 SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask,
1808 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
1809 X, DAG.getConstant(Mask, DL, MVT::i32));
1817 SDValue SITargetLowering::performOrCombine(SDNode *N,
1818 DAGCombinerInfo &DCI) const {
1819 SelectionDAG &DAG = DCI.DAG;
1820 SDValue LHS = N->getOperand(0);
1821 SDValue RHS = N->getOperand(1);
1823 // or (fp_class x, c1), (fp_class x, c2) -> fp_class x, (c1 | c2)
1824 if (LHS.getOpcode() == AMDGPUISD::FP_CLASS &&
1825 RHS.getOpcode() == AMDGPUISD::FP_CLASS) {
1826 SDValue Src = LHS.getOperand(0);
1827 if (Src != RHS.getOperand(0))
1830 const ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
1831 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
1835 // Only 10 bits are used.
1836 static const uint32_t MaxMask = 0x3ff;
1838 uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask;
1840 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
1841 Src, DAG.getConstant(NewMask, DL, MVT::i32));
1847 SDValue SITargetLowering::performClassCombine(SDNode *N,
1848 DAGCombinerInfo &DCI) const {
1849 SelectionDAG &DAG = DCI.DAG;
1850 SDValue Mask = N->getOperand(1);
1852 // fp_class x, 0 -> false
1853 if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
1854 if (CMask->isNullValue())
1855 return DAG.getConstant(0, SDLoc(N), MVT::i1);
1861 static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
1864 return AMDGPUISD::FMAX3;
1866 return AMDGPUISD::SMAX3;
1868 return AMDGPUISD::UMAX3;
1870 return AMDGPUISD::FMIN3;
1872 return AMDGPUISD::SMIN3;
1874 return AMDGPUISD::UMIN3;
1876 llvm_unreachable("Not a min/max opcode");
1880 SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
1881 DAGCombinerInfo &DCI) const {
1882 SelectionDAG &DAG = DCI.DAG;
1884 unsigned Opc = N->getOpcode();
1885 SDValue Op0 = N->getOperand(0);
1886 SDValue Op1 = N->getOperand(1);
1888 // Only do this if the inner op has one use since this will just increases
1889 // register pressure for no benefit.
1891 // max(max(a, b), c)
1892 if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
1894 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
1902 // max(a, max(b, c))
1903 if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
1905 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
1916 SDValue SITargetLowering::performSetCCCombine(SDNode *N,
1917 DAGCombinerInfo &DCI) const {
1918 SelectionDAG &DAG = DCI.DAG;
1921 SDValue LHS = N->getOperand(0);
1922 SDValue RHS = N->getOperand(1);
1923 EVT VT = LHS.getValueType();
1925 if (VT != MVT::f32 && VT != MVT::f64)
1928 // Match isinf pattern
1929 // (fcmp oeq (fabs x), inf) -> (fp_class x, (p_infinity | n_infinity))
1930 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
1931 if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) {
1932 const ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
1936 const APFloat &APF = CRHS->getValueAPF();
1937 if (APF.isInfinity() && !APF.isNegative()) {
1938 unsigned Mask = SIInstrFlags::P_INFINITY | SIInstrFlags::N_INFINITY;
1939 return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1, LHS.getOperand(0),
1940 DAG.getConstant(Mask, SL, MVT::i32));
1947 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1948 DAGCombinerInfo &DCI) const {
1949 SelectionDAG &DAG = DCI.DAG;
1952 switch (N->getOpcode()) {
1954 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1956 return performSetCCCombine(N, DCI);
1957 case ISD::FMAXNUM: // TODO: What about fmax_legacy?
1963 if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG &&
1964 N->getValueType(0) != MVT::f64 &&
1965 getTargetMachine().getOptLevel() > CodeGenOpt::None)
1966 return performMin3Max3Combine(N, DCI);
1970 case AMDGPUISD::CVT_F32_UBYTE0:
1971 case AMDGPUISD::CVT_F32_UBYTE1:
1972 case AMDGPUISD::CVT_F32_UBYTE2:
1973 case AMDGPUISD::CVT_F32_UBYTE3: {
1974 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
1976 SDValue Src = N->getOperand(0);
1977 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
1979 APInt KnownZero, KnownOne;
1980 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1981 !DCI.isBeforeLegalizeOps());
1982 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1983 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1984 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1985 DCI.CommitTargetLoweringOpt(TLO);
1991 case ISD::UINT_TO_FP: {
1992 return performUCharToFloatCombine(N, DCI);
1995 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
1998 EVT VT = N->getValueType(0);
2002 // Only do this if we are not trying to support denormals. v_mad_f32 does
2003 // not support denormals ever.
2004 if (Subtarget->hasFP32Denormals())
2007 SDValue LHS = N->getOperand(0);
2008 SDValue RHS = N->getOperand(1);
2010 // These should really be instruction patterns, but writing patterns with
2011 // source modiifiers is a pain.
2013 // fadd (fadd (a, a), b) -> mad 2.0, a, b
2014 if (LHS.getOpcode() == ISD::FADD) {
2015 SDValue A = LHS.getOperand(0);
2016 if (A == LHS.getOperand(1)) {
2017 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2018 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS);
2022 // fadd (b, fadd (a, a)) -> mad 2.0, a, b
2023 if (RHS.getOpcode() == ISD::FADD) {
2024 SDValue A = RHS.getOperand(0);
2025 if (A == RHS.getOperand(1)) {
2026 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2027 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS);
2034 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2037 EVT VT = N->getValueType(0);
2039 // Try to get the fneg to fold into the source modifier. This undoes generic
2040 // DAG combines and folds them into the mad.
2042 // Only do this if we are not trying to support denormals. v_mad_f32 does
2043 // not support denormals ever.
2044 if (VT == MVT::f32 &&
2045 !Subtarget->hasFP32Denormals()) {
2046 SDValue LHS = N->getOperand(0);
2047 SDValue RHS = N->getOperand(1);
2048 if (LHS.getOpcode() == ISD::FADD) {
2049 // (fsub (fadd a, a), c) -> mad 2.0, a, (fneg c)
2051 SDValue A = LHS.getOperand(0);
2052 if (A == LHS.getOperand(1)) {
2053 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2054 SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS);
2056 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS);
2060 if (RHS.getOpcode() == ISD::FADD) {
2061 // (fsub c, (fadd a, a)) -> mad -2.0, a, c
2063 SDValue A = RHS.getOperand(0);
2064 if (A == RHS.getOperand(1)) {
2065 const SDValue NegTwo = DAG.getConstantFP(-2.0, DL, MVT::f32);
2066 return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS);
2078 case ISD::ATOMIC_LOAD:
2079 case ISD::ATOMIC_STORE:
2080 case ISD::ATOMIC_CMP_SWAP:
2081 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
2082 case ISD::ATOMIC_SWAP:
2083 case ISD::ATOMIC_LOAD_ADD:
2084 case ISD::ATOMIC_LOAD_SUB:
2085 case ISD::ATOMIC_LOAD_AND:
2086 case ISD::ATOMIC_LOAD_OR:
2087 case ISD::ATOMIC_LOAD_XOR:
2088 case ISD::ATOMIC_LOAD_NAND:
2089 case ISD::ATOMIC_LOAD_MIN:
2090 case ISD::ATOMIC_LOAD_MAX:
2091 case ISD::ATOMIC_LOAD_UMIN:
2092 case ISD::ATOMIC_LOAD_UMAX: { // TODO: Target mem intrinsics.
2093 if (DCI.isBeforeLegalize())
2096 MemSDNode *MemNode = cast<MemSDNode>(N);
2097 SDValue Ptr = MemNode->getBasePtr();
2099 // TODO: We could also do this for multiplies.
2100 unsigned AS = MemNode->getAddressSpace();
2101 if (Ptr.getOpcode() == ISD::SHL && AS != AMDGPUAS::PRIVATE_ADDRESS) {
2102 SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), AS, DCI);
2104 SmallVector<SDValue, 8> NewOps(MemNode->op_begin(), MemNode->op_end());
2106 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
2107 return SDValue(DAG.UpdateNodeOperands(MemNode, NewOps), 0);
2113 return performAndCombine(N, DCI);
2115 return performOrCombine(N, DCI);
2116 case AMDGPUISD::FP_CLASS:
2117 return performClassCombine(N, DCI);
2119 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2122 /// \brief Analyze the possible immediate value Op
2124 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
2125 /// and the immediate value if it's a literal immediate
2126 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
2128 const SIInstrInfo *TII =
2129 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2131 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
2132 if (TII->isInlineConstant(Node->getAPIntValue()))
2135 uint64_t Val = Node->getZExtValue();
2136 return isUInt<32>(Val) ? Val : -1;
2139 if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
2140 if (TII->isInlineConstant(Node->getValueAPF().bitcastToAPInt()))
2143 if (Node->getValueType(0) == MVT::f32)
2144 return FloatToBits(Node->getValueAPF().convertToFloat());
2152 /// \brief Helper function for adjustWritemask
2153 static unsigned SubIdx2Lane(unsigned Idx) {
2156 case AMDGPU::sub0: return 0;
2157 case AMDGPU::sub1: return 1;
2158 case AMDGPU::sub2: return 2;
2159 case AMDGPU::sub3: return 3;
2163 /// \brief Adjust the writemask of MIMG instructions
2164 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
2165 SelectionDAG &DAG) const {
2166 SDNode *Users[4] = { };
2168 unsigned OldDmask = Node->getConstantOperandVal(0);
2169 unsigned NewDmask = 0;
2171 // Try to figure out the used register components
2172 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
2175 // Abort if we can't understand the usage
2176 if (!I->isMachineOpcode() ||
2177 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
2180 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
2181 // Note that subregs are packed, i.e. Lane==0 is the first bit set
2182 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
2184 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
2186 // Set which texture component corresponds to the lane.
2188 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
2190 Comp = countTrailingZeros(Dmask);
2191 Dmask &= ~(1 << Comp);
2194 // Abort if we have more than one user per component
2199 NewDmask |= 1 << Comp;
2202 // Abort if there's no change
2203 if (NewDmask == OldDmask)
2206 // Adjust the writemask in the node
2207 std::vector<SDValue> Ops;
2208 Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
2209 Ops.insert(Ops.end(), Node->op_begin() + 1, Node->op_end());
2210 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
2212 // If we only got one lane, replace it with a copy
2213 // (if NewDmask has only one bit set...)
2214 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
2215 SDValue RC = DAG.getTargetConstant(AMDGPU::VGPR_32RegClassID, SDLoc(),
2217 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
2218 SDLoc(), Users[Lane]->getValueType(0),
2219 SDValue(Node, 0), RC);
2220 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
2224 // Update the users of the node with the new indices
2225 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
2227 SDNode *User = Users[i];
2231 SDValue Op = DAG.getTargetConstant(Idx, SDLoc(User), MVT::i32);
2232 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
2236 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
2237 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
2238 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
2243 static bool isFrameIndexOp(SDValue Op) {
2244 if (Op.getOpcode() == ISD::AssertZext)
2245 Op = Op.getOperand(0);
2247 return isa<FrameIndexSDNode>(Op);
2250 /// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
2251 /// with frame index operands.
2252 /// LLVM assumes that inputs are to these instructions are registers.
2253 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
2254 SelectionDAG &DAG) const {
2256 SmallVector<SDValue, 8> Ops;
2257 for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
2258 if (!isFrameIndexOp(Node->getOperand(i))) {
2259 Ops.push_back(Node->getOperand(i));
2264 Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
2265 Node->getOperand(i).getValueType(),
2266 Node->getOperand(i)), 0));
2269 DAG.UpdateNodeOperands(Node, Ops);
2272 /// \brief Fold the instructions after selecting them.
2273 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
2274 SelectionDAG &DAG) const {
2275 const SIInstrInfo *TII =
2276 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2278 if (TII->isMIMG(Node->getMachineOpcode()))
2279 adjustWritemask(Node, DAG);
2281 if (Node->getMachineOpcode() == AMDGPU::INSERT_SUBREG ||
2282 Node->getMachineOpcode() == AMDGPU::REG_SEQUENCE) {
2283 legalizeTargetIndependentNode(Node, DAG);
2289 /// \brief Assign the register class depending on the number of
2290 /// bits set in the writemask
2291 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
2292 SDNode *Node) const {
2293 const SIInstrInfo *TII =
2294 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2296 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2298 if (TII->isVOP3(MI->getOpcode())) {
2299 // Make sure constant bus requirements are respected.
2300 TII->legalizeOperandsVOP3(MRI, MI);
2304 if (TII->isMIMG(*MI)) {
2305 unsigned VReg = MI->getOperand(0).getReg();
2306 unsigned Writemask = MI->getOperand(1).getImm();
2307 unsigned BitsSet = 0;
2308 for (unsigned i = 0; i < 4; ++i)
2309 BitsSet += Writemask & (1 << i) ? 1 : 0;
2311 const TargetRegisterClass *RC;
2314 case 1: RC = &AMDGPU::VGPR_32RegClass; break;
2315 case 2: RC = &AMDGPU::VReg_64RegClass; break;
2316 case 3: RC = &AMDGPU::VReg_96RegClass; break;
2319 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
2320 MI->setDesc(TII->get(NewOpcode));
2321 MRI.setRegClass(VReg, RC);
2325 // Replace unused atomics with the no return version.
2326 int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI->getOpcode());
2327 if (NoRetAtomicOp != -1) {
2328 if (!Node->hasAnyUseOfValue(0)) {
2329 MI->setDesc(TII->get(NoRetAtomicOp));
2330 MI->RemoveOperand(0);
2337 static SDValue buildSMovImm32(SelectionDAG &DAG, SDLoc DL, uint64_t Val) {
2338 SDValue K = DAG.getTargetConstant(Val, DL, MVT::i32);
2339 return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
2342 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
2344 SDValue Ptr) const {
2345 const SIInstrInfo *TII =
2346 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2348 // Build the half of the subregister with the constants before building the
2349 // full 128-bit register. If we are building multiple resource descriptors,
2350 // this will allow CSEing of the 2-component register.
2351 const SDValue Ops0[] = {
2352 DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, DL, MVT::i32),
2353 buildSMovImm32(DAG, DL, 0),
2354 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
2355 buildSMovImm32(DAG, DL, TII->getDefaultRsrcDataFormat() >> 32),
2356 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
2359 SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL,
2360 MVT::v2i32, Ops0), 0);
2362 // Combine the constants and the pointer.
2363 const SDValue Ops1[] = {
2364 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
2366 DAG.getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32),
2368 DAG.getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32)
2371 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
2374 /// \brief Return a resource descriptor with the 'Add TID' bit enabled
2375 /// The TID (Thread ID) is multiplied by the stride value (bits [61:48]
2376 /// of the resource descriptor) to create an offset, which is added to
2377 /// the resource pointer.
2378 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,
2381 uint32_t RsrcDword1,
2382 uint64_t RsrcDword2And3) const {
2383 SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
2384 SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
2386 PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
2387 DAG.getConstant(RsrcDword1, DL, MVT::i32)),
2391 SDValue DataLo = buildSMovImm32(DAG, DL,
2392 RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
2393 SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
2395 const SDValue Ops[] = {
2396 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
2398 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
2400 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32),
2402 DAG.getTargetConstant(AMDGPU::sub2, DL, MVT::i32),
2404 DAG.getTargetConstant(AMDGPU::sub3, DL, MVT::i32)
2407 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
2410 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2411 const TargetRegisterClass *RC,
2412 unsigned Reg, EVT VT) const {
2413 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
2415 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
2416 cast<RegisterSDNode>(VReg)->getReg(), VT);
2419 //===----------------------------------------------------------------------===//
2420 // SI Inline Assembly Support
2421 //===----------------------------------------------------------------------===//
2423 std::pair<unsigned, const TargetRegisterClass *>
2424 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2425 StringRef Constraint,
2428 if (Constraint.size() == 1) {
2429 switch (Constraint[0]) {
2432 switch (VT.getSizeInBits()) {
2434 return std::make_pair(0U, nullptr);
2436 return std::make_pair(0U, &AMDGPU::SGPR_32RegClass);
2438 return std::make_pair(0U, &AMDGPU::SGPR_64RegClass);
2440 return std::make_pair(0U, &AMDGPU::SReg_128RegClass);
2442 return std::make_pair(0U, &AMDGPU::SReg_256RegClass);
2446 switch (VT.getSizeInBits()) {
2448 return std::make_pair(0U, nullptr);
2450 return std::make_pair(0U, &AMDGPU::VGPR_32RegClass);
2452 return std::make_pair(0U, &AMDGPU::VReg_64RegClass);
2454 return std::make_pair(0U, &AMDGPU::VReg_96RegClass);
2456 return std::make_pair(0U, &AMDGPU::VReg_128RegClass);
2458 return std::make_pair(0U, &AMDGPU::VReg_256RegClass);
2460 return std::make_pair(0U, &AMDGPU::VReg_512RegClass);
2465 if (Constraint.size() > 1) {
2466 const TargetRegisterClass *RC = nullptr;
2467 if (Constraint[1] == 'v') {
2468 RC = &AMDGPU::VGPR_32RegClass;
2469 } else if (Constraint[1] == 's') {
2470 RC = &AMDGPU::SGPR_32RegClass;
2475 bool Failed = Constraint.substr(2).getAsInteger(10, Idx);
2476 if (!Failed && Idx < RC->getNumRegs())
2477 return std::make_pair(RC->getRegister(Idx), RC);
2480 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2483 SITargetLowering::ConstraintType
2484 SITargetLowering::getConstraintType(StringRef Constraint) const {
2485 if (Constraint.size() == 1) {
2486 switch (Constraint[0]) {
2490 return C_RegisterClass;
2493 return TargetLowering::getConstraintType(Constraint);