1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
17 #define _USE_MATH_DEFINES
21 #include "SIISelLowering.h"
23 #include "AMDGPUDiagnosticInfoUnsupported.h"
24 #include "AMDGPUIntrinsicInfo.h"
25 #include "AMDGPUSubtarget.h"
26 #include "SIInstrInfo.h"
27 #include "SIMachineFunctionInfo.h"
28 #include "SIRegisterInfo.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/ADT/SmallString.h"
39 SITargetLowering::SITargetLowering(TargetMachine &TM,
40 const AMDGPUSubtarget &STI)
41 : AMDGPUTargetLowering(TM, STI) {
42 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
43 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
45 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
46 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
48 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
49 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
51 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
52 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
53 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
55 addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass);
56 addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass);
58 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
59 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
61 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
62 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
64 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
65 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
67 computeRegisterProperties(STI.getRegisterInfo());
69 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
70 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
71 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
72 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
74 setOperationAction(ISD::ADD, MVT::i32, Legal);
75 setOperationAction(ISD::ADDC, MVT::i32, Legal);
76 setOperationAction(ISD::ADDE, MVT::i32, Legal);
77 setOperationAction(ISD::SUBC, MVT::i32, Legal);
78 setOperationAction(ISD::SUBE, MVT::i32, Legal);
80 setOperationAction(ISD::FSIN, MVT::f32, Custom);
81 setOperationAction(ISD::FCOS, MVT::f32, Custom);
83 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
84 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
86 // We need to custom lower vector stores from local memory
87 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
88 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
89 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
91 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
92 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
94 setOperationAction(ISD::STORE, MVT::i1, Custom);
95 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
97 setOperationAction(ISD::SELECT, MVT::i64, Custom);
98 setOperationAction(ISD::SELECT, MVT::f64, Promote);
99 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
101 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
102 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
103 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
104 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
106 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
107 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
109 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
110 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
114 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
127 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
128 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
129 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
130 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
132 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
133 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
135 for (MVT VT : MVT::integer_valuetypes()) {
139 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
141 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
142 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
144 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
145 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
146 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
147 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
149 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
150 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
151 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
152 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
155 for (MVT VT : MVT::integer_vector_valuetypes()) {
156 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i16, Expand);
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v16i16, Expand);
160 for (MVT VT : MVT::fp_valuetypes())
161 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
163 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
164 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
166 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
167 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
168 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
169 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
172 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
174 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
175 setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand);
177 setOperationAction(ISD::LOAD, MVT::i1, Custom);
179 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
180 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
182 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
183 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
185 setOperationAction(ISD::ConstantPool, MVT::v2i64, Expand);
187 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
188 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
189 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
191 // These should use UDIVREM, so set them to expand
192 setOperationAction(ISD::UDIV, MVT::i64, Expand);
193 setOperationAction(ISD::UREM, MVT::i64, Expand);
195 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
196 setOperationAction(ISD::SELECT, MVT::i1, Promote);
198 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
201 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
203 // We only support LOAD/STORE and vector manipulation ops for vectors
204 // with > 4 elements.
205 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64}) {
206 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
210 case ISD::BUILD_VECTOR:
212 case ISD::EXTRACT_VECTOR_ELT:
213 case ISD::INSERT_VECTOR_ELT:
214 case ISD::INSERT_SUBVECTOR:
215 case ISD::EXTRACT_SUBVECTOR:
216 case ISD::SCALAR_TO_VECTOR:
218 case ISD::CONCAT_VECTORS:
219 setOperationAction(Op, VT, Custom);
222 setOperationAction(Op, VT, Expand);
228 // Most operations are naturally 32-bit vector operations. We only support
229 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
230 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
231 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
232 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
234 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
235 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
237 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
238 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
240 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
241 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
244 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
245 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
246 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
247 setOperationAction(ISD::FRINT, MVT::f64, Legal);
250 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
251 setOperationAction(ISD::FDIV, MVT::f32, Custom);
252 setOperationAction(ISD::FDIV, MVT::f64, Custom);
254 setTargetDAGCombine(ISD::FADD);
255 setTargetDAGCombine(ISD::FSUB);
256 setTargetDAGCombine(ISD::FMINNUM);
257 setTargetDAGCombine(ISD::FMAXNUM);
258 setTargetDAGCombine(ISD::SMIN);
259 setTargetDAGCombine(ISD::SMAX);
260 setTargetDAGCombine(ISD::UMIN);
261 setTargetDAGCombine(ISD::UMAX);
262 setTargetDAGCombine(ISD::SELECT_CC);
263 setTargetDAGCombine(ISD::SETCC);
264 setTargetDAGCombine(ISD::AND);
265 setTargetDAGCombine(ISD::OR);
266 setTargetDAGCombine(ISD::UINT_TO_FP);
268 // All memory operations. Some folding on the pointer operand is done to help
269 // matching the constant offsets in the addressing modes.
270 setTargetDAGCombine(ISD::LOAD);
271 setTargetDAGCombine(ISD::STORE);
272 setTargetDAGCombine(ISD::ATOMIC_LOAD);
273 setTargetDAGCombine(ISD::ATOMIC_STORE);
274 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
275 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
276 setTargetDAGCombine(ISD::ATOMIC_SWAP);
277 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
278 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
279 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
280 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
281 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
282 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
283 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
284 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
285 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
286 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
288 setSchedulingPreference(Sched::RegPressure);
291 //===----------------------------------------------------------------------===//
292 // TargetLowering queries
293 //===----------------------------------------------------------------------===//
295 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
297 // SI has some legal vector types, but no legal vector operations. Say no
298 // shuffles are legal in order to prefer scalarizing some vector operations.
302 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
303 // Flat instructions do not have offsets, and only have the register
305 return AM.BaseOffs == 0 && (AM.Scale == 0 || AM.Scale == 1);
308 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
309 // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
310 // additionally can do r + r + i with addr64. 32-bit has more addressing
311 // mode options. Depending on the resource constant, it can also do
312 // (i64 r0) + (i32 r1) * (i14 i).
314 // Private arrays end up using a scratch buffer most of the time, so also
315 // assume those use MUBUF instructions. Scratch loads / stores are currently
316 // implemented as mubuf instructions with offen bit set, so slightly
317 // different than the normal addr64.
318 if (!isUInt<12>(AM.BaseOffs))
321 // FIXME: Since we can split immediate into soffset and immediate offset,
322 // would it make sense to allow any immediate?
325 case 0: // r + i or just i, depending on HasBaseReg.
328 return true; // We have r + r or r + i.
335 // Allow 2 * r as r + r
336 // Or 2 * r + i is allowed as r + r + i.
338 default: // Don't allow n * r
343 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
344 const AddrMode &AM, Type *Ty,
346 // No global is ever allowed as a base.
351 case AMDGPUAS::GLOBAL_ADDRESS: {
352 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
353 // Assume the we will use FLAT for all global memory accesses
355 // FIXME: This assumption is currently wrong. On VI we still use
356 // MUBUF instructions for the r + i addressing mode. As currently
357 // implemented, the MUBUF instructions only work on buffer < 4GB.
358 // It may be possible to support > 4GB buffers with MUBUF instructions,
359 // by setting the stride value in the resource descriptor which would
360 // increase the size limit to (stride * 4GB). However, this is risky,
361 // because it has never been validated.
362 return isLegalFlatAddressingMode(AM);
365 return isLegalMUBUFAddressingMode(AM);
367 case AMDGPUAS::CONSTANT_ADDRESS: {
368 // If the offset isn't a multiple of 4, it probably isn't going to be
369 // correctly aligned.
370 if (AM.BaseOffs % 4 != 0)
371 return isLegalMUBUFAddressingMode(AM);
373 // There are no SMRD extloads, so if we have to do a small type access we
374 // will use a MUBUF load.
375 // FIXME?: We also need to do this if unaligned, but we don't know the
377 if (DL.getTypeStoreSize(Ty) < 4)
378 return isLegalMUBUFAddressingMode(AM);
380 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
381 // SMRD instructions have an 8-bit, dword offset on SI.
382 if (!isUInt<8>(AM.BaseOffs / 4))
384 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) {
385 // On CI+, this can also be a 32-bit literal constant offset. If it fits
386 // in 8-bits, it can use a smaller encoding.
387 if (!isUInt<32>(AM.BaseOffs / 4))
389 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS) {
390 // On VI, these use the SMEM format and the offset is 20-bit in bytes.
391 if (!isUInt<20>(AM.BaseOffs))
394 llvm_unreachable("unhandled generation");
396 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
399 if (AM.Scale == 1 && AM.HasBaseReg)
405 case AMDGPUAS::PRIVATE_ADDRESS:
406 case AMDGPUAS::UNKNOWN_ADDRESS_SPACE:
407 return isLegalMUBUFAddressingMode(AM);
409 case AMDGPUAS::LOCAL_ADDRESS:
410 case AMDGPUAS::REGION_ADDRESS: {
411 // Basic, single offset DS instructions allow a 16-bit unsigned immediate
413 // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
414 // an 8-bit dword offset but we don't know the alignment here.
415 if (!isUInt<16>(AM.BaseOffs))
418 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
421 if (AM.Scale == 1 && AM.HasBaseReg)
426 case AMDGPUAS::FLAT_ADDRESS:
427 return isLegalFlatAddressingMode(AM);
430 llvm_unreachable("unhandled address space");
434 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
437 bool *IsFast) const {
441 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
442 // which isn't a simple VT.
443 if (!VT.isSimple() || VT == MVT::Other)
446 // TODO - CI+ supports unaligned memory accesses, but this requires driver
449 // XXX - The only mention I see of this in the ISA manual is for LDS direct
450 // reads the "byte address and must be dword aligned". Is it also true for the
451 // normal loads and stores?
452 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS) {
453 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
454 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
455 // with adjacent offsets.
456 bool AlignedBy4 = (Align % 4 == 0);
458 *IsFast = AlignedBy4;
462 // Smaller than dword value must be aligned.
463 // FIXME: This should be allowed on CI+
464 if (VT.bitsLT(MVT::i32))
467 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
468 // byte-address are ignored, thus forcing Dword alignment.
469 // This applies to private, global, and constant memory.
473 return VT.bitsGT(MVT::i32) && Align % 4 == 0;
476 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
477 unsigned SrcAlign, bool IsMemset,
480 MachineFunction &MF) const {
481 // FIXME: Should account for address space here.
483 // The default fallback uses the private pointer size as a guess for a type to
484 // use. Make sure we switch these to 64-bit accesses.
486 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
489 if (Size >= 8 && DstAlign >= 4)
496 static bool isFlatGlobalAddrSpace(unsigned AS) {
497 return AS == AMDGPUAS::GLOBAL_ADDRESS ||
498 AS == AMDGPUAS::FLAT_ADDRESS ||
499 AS == AMDGPUAS::CONSTANT_ADDRESS;
502 bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
503 unsigned DestAS) const {
504 return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
507 TargetLoweringBase::LegalizeTypeAction
508 SITargetLowering::getPreferredVectorAction(EVT VT) const {
509 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
510 return TypeSplitVector;
512 return TargetLoweringBase::getPreferredVectorAction(VT);
515 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
517 const SIInstrInfo *TII =
518 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
519 return TII->isInlineConstant(Imm);
522 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
523 SDLoc SL, SDValue Chain,
524 unsigned Offset, bool Signed) const {
525 const DataLayout &DL = DAG.getDataLayout();
526 MachineFunction &MF = DAG.getMachineFunction();
527 const SIRegisterInfo *TRI =
528 static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
529 unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
531 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
533 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
534 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
535 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
536 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
537 MRI.getLiveInVirtReg(InputPtrReg), PtrVT);
538 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
539 DAG.getConstant(Offset, SL, PtrVT));
540 SDValue PtrOffset = DAG.getUNDEF(PtrVT);
541 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
543 unsigned Align = DL.getABITypeAlignment(Ty);
545 ISD::LoadExtType ExtTy = Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
546 if (MemVT.isFloatingPoint())
547 ExtTy = ISD::EXTLOAD;
549 return DAG.getLoad(ISD::UNINDEXED, ExtTy,
550 VT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemVT,
552 true, // isNonTemporal
557 SDValue SITargetLowering::LowerFormalArguments(
558 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
559 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
560 SmallVectorImpl<SDValue> &InVals) const {
561 const SIRegisterInfo *TRI =
562 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
564 MachineFunction &MF = DAG.getMachineFunction();
565 FunctionType *FType = MF.getFunction()->getFunctionType();
566 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
567 const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
569 if (Subtarget->isAmdHsaOS() && Info->getShaderType() != ShaderType::COMPUTE) {
570 const Function *Fn = MF.getFunction();
571 DiagnosticInfoUnsupported NoGraphicsHSA(*Fn, "non-compute shaders with HSA");
572 DAG.getContext()->diagnose(NoGraphicsHSA);
576 // FIXME: We currently assume all calling conventions are kernels.
578 SmallVector<ISD::InputArg, 16> Splits;
579 BitVector Skipped(Ins.size());
581 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
582 const ISD::InputArg &Arg = Ins[i];
584 // First check if it's a PS input addr
585 if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
586 !Arg.Flags.isByVal()) {
588 assert((PSInputNum <= 15) && "Too many PS inputs!");
591 // We can safely skip PS inputs
597 Info->PSInputAddr |= 1 << PSInputNum++;
600 // Second split vertices into their elements
601 if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) {
602 ISD::InputArg NewArg = Arg;
603 NewArg.Flags.setSplit();
604 NewArg.VT = Arg.VT.getVectorElementType();
606 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
607 // three or five element vertex only needs three or five registers,
608 // NOT four or eight.
609 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
610 unsigned NumElements = ParamType->getVectorNumElements();
612 for (unsigned j = 0; j != NumElements; ++j) {
613 Splits.push_back(NewArg);
614 NewArg.PartOffset += NewArg.VT.getStoreSize();
617 } else if (Info->getShaderType() != ShaderType::COMPUTE) {
618 Splits.push_back(Arg);
622 SmallVector<CCValAssign, 16> ArgLocs;
623 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
626 // At least one interpolation mode must be enabled or else the GPU will hang.
627 if (Info->getShaderType() == ShaderType::PIXEL &&
628 (Info->PSInputAddr & 0x7F) == 0) {
629 Info->PSInputAddr |= 1;
630 CCInfo.AllocateReg(AMDGPU::VGPR0);
631 CCInfo.AllocateReg(AMDGPU::VGPR1);
634 if (Info->getShaderType() == ShaderType::COMPUTE) {
635 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
639 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
640 if (Info->hasPrivateSegmentBuffer()) {
641 unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);
642 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);
643 CCInfo.AllocateReg(PrivateSegmentBufferReg);
646 if (Info->hasDispatchPtr()) {
647 unsigned DispatchPtrReg = Info->addDispatchPtr(*TRI);
648 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SReg_64RegClass);
649 CCInfo.AllocateReg(DispatchPtrReg);
652 if (Info->hasKernargSegmentPtr()) {
653 unsigned InputPtrReg = Info->addKernargSegmentPtr(*TRI);
654 MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
655 CCInfo.AllocateReg(InputPtrReg);
658 AnalyzeFormalArguments(CCInfo, Splits);
660 SmallVector<SDValue, 16> Chains;
662 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
664 const ISD::InputArg &Arg = Ins[i];
666 InVals.push_back(DAG.getUNDEF(Arg.VT));
670 CCValAssign &VA = ArgLocs[ArgIdx++];
671 MVT VT = VA.getLocVT();
675 EVT MemVT = Splits[i].VT;
676 const unsigned Offset = Subtarget->getExplicitKernelArgOffset() +
677 VA.getLocMemOffset();
678 // The first 36 bytes of the input buffer contains information about
679 // thread group and global sizes.
680 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, Chain,
681 Offset, Ins[i].Flags.isSExt());
682 Chains.push_back(Arg.getValue(1));
685 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
686 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
687 ParamTy && ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
688 // On SI local pointers are just offsets into LDS, so they are always
689 // less than 16-bits. On CI and newer they could potentially be
690 // real pointers, so we can't guarantee their size.
691 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
692 DAG.getValueType(MVT::i16));
695 InVals.push_back(Arg);
696 Info->ABIArgOffset = Offset + MemVT.getStoreSize();
699 assert(VA.isRegLoc() && "Parameter must be in a register!");
701 unsigned Reg = VA.getLocReg();
703 if (VT == MVT::i64) {
704 // For now assume it is a pointer
705 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
706 &AMDGPU::SReg_64RegClass);
707 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
708 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
709 InVals.push_back(Copy);
713 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
715 Reg = MF.addLiveIn(Reg, RC);
716 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
718 if (Arg.VT.isVector()) {
720 // Build a vector from the registers
721 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
722 unsigned NumElements = ParamType->getVectorNumElements();
724 SmallVector<SDValue, 4> Regs;
726 for (unsigned j = 1; j != NumElements; ++j) {
727 Reg = ArgLocs[ArgIdx++].getLocReg();
728 Reg = MF.addLiveIn(Reg, RC);
730 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
731 Regs.push_back(Copy);
734 // Fill up the missing vector elements
735 NumElements = Arg.VT.getVectorNumElements() - NumElements;
736 Regs.append(NumElements, DAG.getUNDEF(VT));
738 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
742 InVals.push_back(Val);
745 // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
746 // these from the dispatch pointer.
748 // Start adding system SGPRs.
749 if (Info->hasWorkGroupIDX()) {
750 unsigned Reg = Info->addWorkGroupIDX();
751 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
752 CCInfo.AllocateReg(Reg);
754 llvm_unreachable("work group id x is always enabled");
756 if (Info->hasWorkGroupIDY()) {
757 unsigned Reg = Info->addWorkGroupIDY();
758 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
759 CCInfo.AllocateReg(Reg);
762 if (Info->hasWorkGroupIDZ()) {
763 unsigned Reg = Info->addWorkGroupIDZ();
764 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
765 CCInfo.AllocateReg(Reg);
768 if (Info->hasWorkGroupInfo()) {
769 unsigned Reg = Info->addWorkGroupInfo();
770 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
771 CCInfo.AllocateReg(Reg);
774 if (Info->hasPrivateSegmentWaveByteOffset()) {
775 // Scratch wave offset passed in system SGPR.
776 unsigned PrivateSegmentWaveByteOffsetReg
777 = Info->addPrivateSegmentWaveByteOffset();
779 MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
780 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
783 // Now that we've figured out where the scratch register inputs are, see if
784 // should reserve the arguments and use them directly.
786 bool HasStackObjects = MF.getFrameInfo()->hasStackObjects();
788 if (ST.isAmdHsaOS()) {
789 // TODO: Assume we will spill without optimizations.
790 if (HasStackObjects) {
791 // If we have stack objects, we unquestionably need the private buffer
792 // resource. For the HSA ABI, this will be the first 4 user SGPR
793 // inputs. We can reserve those and use them directly.
795 unsigned PrivateSegmentBufferReg = TRI->getPreloadedValue(
796 MF, SIRegisterInfo::PRIVATE_SEGMENT_BUFFER);
797 Info->setScratchRSrcReg(PrivateSegmentBufferReg);
799 unsigned PrivateSegmentWaveByteOffsetReg = TRI->getPreloadedValue(
800 MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
801 Info->setScratchWaveOffsetReg(PrivateSegmentWaveByteOffsetReg);
803 unsigned ReservedBufferReg
804 = TRI->reservedPrivateSegmentBufferReg(MF);
805 unsigned ReservedOffsetReg
806 = TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
808 // We tentatively reserve the last registers (skipping the last two
809 // which may contain VCC). After register allocation, we'll replace
810 // these with the ones immediately after those which were really
811 // allocated. In the prologue copies will be inserted from the argument
812 // to these reserved registers.
813 Info->setScratchRSrcReg(ReservedBufferReg);
814 Info->setScratchWaveOffsetReg(ReservedOffsetReg);
817 unsigned ReservedBufferReg = TRI->reservedPrivateSegmentBufferReg(MF);
819 // Without HSA, relocations are used for the scratch pointer and the
820 // buffer resource setup is always inserted in the prologue. Scratch wave
821 // offset is still in an input SGPR.
822 Info->setScratchRSrcReg(ReservedBufferReg);
824 if (HasStackObjects) {
825 unsigned ScratchWaveOffsetReg = TRI->getPreloadedValue(
826 MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
827 Info->setScratchWaveOffsetReg(ScratchWaveOffsetReg);
829 unsigned ReservedOffsetReg
830 = TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
831 Info->setScratchWaveOffsetReg(ReservedOffsetReg);
835 if (Info->hasWorkItemIDX()) {
836 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_X);
837 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
838 CCInfo.AllocateReg(Reg);
840 llvm_unreachable("workitem id x should always be enabled");
842 if (Info->hasWorkItemIDY()) {
843 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Y);
844 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
845 CCInfo.AllocateReg(Reg);
848 if (Info->hasWorkItemIDZ()) {
849 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Z);
850 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
851 CCInfo.AllocateReg(Reg);
857 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
860 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
861 MachineInstr * MI, MachineBasicBlock * BB) const {
863 switch (MI->getOpcode()) {
865 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
872 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
873 // This currently forces unfolding various combinations of fsub into fma with
874 // free fneg'd operands. As long as we have fast FMA (controlled by
875 // isFMAFasterThanFMulAndFAdd), we should perform these.
877 // When fma is quarter rate, for f64 where add / sub are at best half rate,
878 // most of these combines appear to be cycle neutral but save on instruction
879 // count / code size.
883 EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
885 if (!VT.isVector()) {
888 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
891 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const {
895 // Answering this is somewhat tricky and depends on the specific device which
896 // have different rates for fma or all f64 operations.
898 // v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
899 // regardless of which device (although the number of cycles differs between
900 // devices), so it is always profitable for f64.
902 // v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
903 // only on full rate devices. Normally, we should prefer selecting v_mad_f32
904 // which we can always do even without fused FP ops since it returns the same
905 // result as the separate operations and since it is always full
906 // rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
907 // however does not support denormals, so we do report fma as faster if we have
908 // a fast fma device and require denormals.
910 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
911 VT = VT.getScalarType();
916 switch (VT.getSimpleVT().SimpleTy) {
918 // This is as fast on some subtargets. However, we always have full rate f32
919 // mad available which returns the same result as the separate operations
920 // which we should prefer over fma. We can't use this if we want to support
921 // denormals, so only report this in these cases.
922 return Subtarget->hasFP32Denormals() && Subtarget->hasFastFMAF32();
932 //===----------------------------------------------------------------------===//
933 // Custom DAG Lowering Operations
934 //===----------------------------------------------------------------------===//
936 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
937 switch (Op.getOpcode()) {
938 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
939 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
940 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
942 SDValue Result = LowerLOAD(Op, DAG);
943 assert((!Result.getNode() ||
944 Result.getNode()->getNumValues() == 2) &&
945 "Load should return a value and a chain");
951 return LowerTrig(Op, DAG);
952 case ISD::SELECT: return LowerSELECT(Op, DAG);
953 case ISD::FDIV: return LowerFDIV(Op, DAG);
954 case ISD::STORE: return LowerSTORE(Op, DAG);
955 case ISD::GlobalAddress: {
956 MachineFunction &MF = DAG.getMachineFunction();
957 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
958 return LowerGlobalAddress(MFI, Op, DAG);
960 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
961 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
966 /// \brief Helper function for LowerBRCOND
967 static SDNode *findUser(SDValue Value, unsigned Opcode) {
969 SDNode *Parent = Value.getNode();
970 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
973 if (I.getUse().get() != Value)
976 if (I->getOpcode() == Opcode)
982 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
985 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
986 unsigned FrameIndex = FINode->getIndex();
988 // A FrameIndex node represents a 32-bit offset into scratch memory. If
989 // the high bit of a frame index offset were to be set, this would mean
990 // that it represented an offset of ~2GB * 64 = ~128GB from the start of the
991 // scratch buffer, with 64 being the number of threads per wave.
993 // If we know the machine uses less than 128GB of scratch, then we can
994 // amrk the high bit of the FrameIndex node as known zero,
995 // which is important, because it means in most situations we can
996 // prove that values derived from FrameIndex nodes are non-negative.
997 // This enables us to take advantage of more addressing modes when
998 // accessing scratch buffers, since for scratch reads/writes, the register
999 // offset must always be positive.
1001 SDValue TFI = DAG.getTargetFrameIndex(FrameIndex, MVT::i32);
1002 if (Subtarget->enableHugeScratchBuffer())
1005 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, TFI,
1006 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 31)));
1009 /// This transforms the control flow intrinsics to get the branch destination as
1010 /// last parameter, also switches branch target with BR if the need arise
1011 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
1012 SelectionDAG &DAG) const {
1016 SDNode *Intr = BRCOND.getOperand(1).getNode();
1017 SDValue Target = BRCOND.getOperand(2);
1018 SDNode *BR = nullptr;
1020 if (Intr->getOpcode() == ISD::SETCC) {
1021 // As long as we negate the condition everything is fine
1022 SDNode *SetCC = Intr;
1023 assert(SetCC->getConstantOperandVal(1) == 1);
1024 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
1026 Intr = SetCC->getOperand(0).getNode();
1029 // Get the target from BR if we don't negate the condition
1030 BR = findUser(BRCOND, ISD::BR);
1031 Target = BR->getOperand(1);
1034 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
1036 // Build the result and
1037 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
1039 // operands of the new intrinsic call
1040 SmallVector<SDValue, 4> Ops;
1041 Ops.push_back(BRCOND.getOperand(0));
1042 Ops.append(Intr->op_begin() + 1, Intr->op_end());
1043 Ops.push_back(Target);
1045 // build the new intrinsic call
1046 SDNode *Result = DAG.getNode(
1047 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
1048 DAG.getVTList(Res), Ops).getNode();
1051 // Give the branch instruction our target
1054 BRCOND.getOperand(2)
1056 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
1057 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
1058 BR = NewBR.getNode();
1061 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
1063 // Copy the intrinsic results to registers
1064 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
1065 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
1069 Chain = DAG.getCopyToReg(
1071 CopyToReg->getOperand(1),
1072 SDValue(Result, i - 1),
1075 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
1078 // Remove the old intrinsic from the chain
1079 DAG.ReplaceAllUsesOfValueWith(
1080 SDValue(Intr, Intr->getNumValues() - 1),
1081 Intr->getOperand(0));
1086 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
1088 SelectionDAG &DAG) const {
1089 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
1091 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
1092 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
1095 const GlobalValue *GV = GSD->getGlobal();
1096 MVT PtrVT = getPointerTy(DAG.getDataLayout(), GSD->getAddressSpace());
1098 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
1099 return DAG.getNode(AMDGPUISD::CONST_DATA_PTR, DL, PtrVT, GA);
1102 SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL,
1104 // We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
1105 // so we will end up with redundant moves to m0.
1107 // We can't use S_MOV_B32, because there is no way to specify m0 as the
1108 // destination register.
1110 // We have to use them both. Machine cse will combine all the S_MOV_B32
1111 // instructions and the register coalescer eliminate the extra copies.
1112 SDNode *M0 = DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, V.getValueType(), V);
1113 return DAG.getCopyToReg(Chain, DL, DAG.getRegister(AMDGPU::M0, MVT::i32),
1114 SDValue(M0, 0), SDValue()); // Glue
1115 // A Null SDValue creates
1119 SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
1122 unsigned Offset) const {
1124 SDValue Param = LowerParameter(DAG, MVT::i32, MVT::i32, SL,
1125 DAG.getEntryNode(), Offset, false);
1126 // The local size values will have the hi 16-bits as zero.
1127 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
1128 DAG.getValueType(VT));
1131 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
1132 SelectionDAG &DAG) const {
1133 MachineFunction &MF = DAG.getMachineFunction();
1134 auto MFI = MF.getInfo<SIMachineFunctionInfo>();
1135 const SIRegisterInfo *TRI =
1136 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
1138 EVT VT = Op.getValueType();
1140 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1142 // TODO: Should this propagate fast-math-flags?
1144 switch (IntrinsicID) {
1145 case Intrinsic::amdgcn_dispatch_ptr:
1146 return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass,
1147 TRI->getPreloadedValue(MF, SIRegisterInfo::DISPATCH_PTR), VT);
1149 case Intrinsic::r600_read_ngroups_x:
1150 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1151 SI::KernelInputOffsets::NGROUPS_X, false);
1152 case Intrinsic::r600_read_ngroups_y:
1153 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1154 SI::KernelInputOffsets::NGROUPS_Y, false);
1155 case Intrinsic::r600_read_ngroups_z:
1156 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1157 SI::KernelInputOffsets::NGROUPS_Z, false);
1158 case Intrinsic::r600_read_global_size_x:
1159 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1160 SI::KernelInputOffsets::GLOBAL_SIZE_X, false);
1161 case Intrinsic::r600_read_global_size_y:
1162 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1163 SI::KernelInputOffsets::GLOBAL_SIZE_Y, false);
1164 case Intrinsic::r600_read_global_size_z:
1165 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1166 SI::KernelInputOffsets::GLOBAL_SIZE_Z, false);
1167 case Intrinsic::r600_read_local_size_x:
1168 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1169 SI::KernelInputOffsets::LOCAL_SIZE_X);
1170 case Intrinsic::r600_read_local_size_y:
1171 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1172 SI::KernelInputOffsets::LOCAL_SIZE_Y);
1173 case Intrinsic::r600_read_local_size_z:
1174 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1175 SI::KernelInputOffsets::LOCAL_SIZE_Z);
1176 case Intrinsic::AMDGPU_read_workdim:
1177 // Really only 2 bits.
1178 return lowerImplicitZextParam(DAG, Op, MVT::i8,
1179 getImplicitParameterOffset(MFI, GRID_DIM));
1180 case Intrinsic::r600_read_tgid_x:
1181 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1182 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_X), VT);
1183 case Intrinsic::r600_read_tgid_y:
1184 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1185 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Y), VT);
1186 case Intrinsic::r600_read_tgid_z:
1187 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1188 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Z), VT);
1189 case Intrinsic::r600_read_tidig_x:
1190 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1191 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_X), VT);
1192 case Intrinsic::r600_read_tidig_y:
1193 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1194 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Y), VT);
1195 case Intrinsic::r600_read_tidig_z:
1196 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1197 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Z), VT);
1198 case AMDGPUIntrinsic::SI_load_const: {
1204 MachineMemOperand *MMO = MF.getMachineMemOperand(
1205 MachinePointerInfo(),
1206 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
1207 VT.getStoreSize(), 4);
1208 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
1209 Op->getVTList(), Ops, VT, MMO);
1211 case AMDGPUIntrinsic::SI_sample:
1212 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
1213 case AMDGPUIntrinsic::SI_sampleb:
1214 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
1215 case AMDGPUIntrinsic::SI_sampled:
1216 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
1217 case AMDGPUIntrinsic::SI_samplel:
1218 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
1219 case AMDGPUIntrinsic::SI_vs_load_input:
1220 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
1225 case AMDGPUIntrinsic::AMDGPU_fract:
1226 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
1227 return DAG.getNode(ISD::FSUB, DL, VT, Op.getOperand(1),
1228 DAG.getNode(ISD::FFLOOR, DL, VT, Op.getOperand(1)));
1229 case AMDGPUIntrinsic::SI_fs_constant: {
1230 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1231 SDValue Glue = M0.getValue(1);
1232 return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32,
1233 DAG.getConstant(2, DL, MVT::i32), // P0
1234 Op.getOperand(1), Op.getOperand(2), Glue);
1236 case AMDGPUIntrinsic::SI_packf16:
1237 if (Op.getOperand(1).isUndef() && Op.getOperand(2).isUndef())
1238 return DAG.getUNDEF(MVT::i32);
1240 case AMDGPUIntrinsic::SI_fs_interp: {
1241 SDValue IJ = Op.getOperand(4);
1242 SDValue I = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
1243 DAG.getConstant(0, DL, MVT::i32));
1244 SDValue J = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
1245 DAG.getConstant(1, DL, MVT::i32));
1246 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1247 SDValue Glue = M0.getValue(1);
1248 SDValue P1 = DAG.getNode(AMDGPUISD::INTERP_P1, DL,
1249 DAG.getVTList(MVT::f32, MVT::Glue),
1250 I, Op.getOperand(1), Op.getOperand(2), Glue);
1251 Glue = SDValue(P1.getNode(), 1);
1252 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, P1, J,
1253 Op.getOperand(1), Op.getOperand(2), Glue);
1256 return AMDGPUTargetLowering::LowerOperation(Op, DAG);
1260 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1261 SelectionDAG &DAG) const {
1262 MachineFunction &MF = DAG.getMachineFunction();
1264 SDValue Chain = Op.getOperand(0);
1265 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1267 switch (IntrinsicID) {
1268 case AMDGPUIntrinsic::SI_sendmsg: {
1269 Chain = copyToM0(DAG, Chain, DL, Op.getOperand(3));
1270 SDValue Glue = Chain.getValue(1);
1271 return DAG.getNode(AMDGPUISD::SENDMSG, DL, MVT::Other, Chain,
1272 Op.getOperand(2), Glue);
1274 case AMDGPUIntrinsic::SI_tbuffer_store: {
1292 EVT VT = Op.getOperand(3).getValueType();
1294 MachineMemOperand *MMO = MF.getMachineMemOperand(
1295 MachinePointerInfo(),
1296 MachineMemOperand::MOStore,
1297 VT.getStoreSize(), 4);
1298 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
1299 Op->getVTList(), Ops, VT, MMO);
1306 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1308 LoadSDNode *Load = cast<LoadSDNode>(Op);
1310 if (Op.getValueType().isVector()) {
1311 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
1312 "Custom lowering for non-i32 vectors hasn't been implemented.");
1313 unsigned NumElements = Op.getValueType().getVectorNumElements();
1314 assert(NumElements != 2 && "v2 loads are supported for all address spaces.");
1316 switch (Load->getAddressSpace()) {
1318 case AMDGPUAS::GLOBAL_ADDRESS:
1319 case AMDGPUAS::PRIVATE_ADDRESS:
1320 if (NumElements >= 8)
1321 return SplitVectorLoad(Op, DAG);
1323 // v4 loads are supported for private and global memory.
1324 if (NumElements <= 4)
1327 case AMDGPUAS::LOCAL_ADDRESS:
1328 // If properly aligned, if we split we might be able to use ds_read_b64.
1329 return SplitVectorLoad(Op, DAG);
1333 return AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1336 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
1338 SelectionDAG &DAG) const {
1339 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
1345 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
1346 if (Op.getValueType() != MVT::i64)
1350 SDValue Cond = Op.getOperand(0);
1352 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1353 SDValue One = DAG.getConstant(1, DL, MVT::i32);
1355 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
1356 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
1358 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
1359 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
1361 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
1363 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
1364 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
1366 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
1368 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
1369 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
1372 // Catch division cases where we can use shortcuts with rcp and rsq
1374 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
1376 SDValue LHS = Op.getOperand(0);
1377 SDValue RHS = Op.getOperand(1);
1378 EVT VT = Op.getValueType();
1379 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
1381 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
1382 if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals())) &&
1383 CLHS->isExactlyValue(1.0)) {
1384 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
1385 // the CI documentation has a worst case error of 1 ulp.
1386 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
1387 // use it as long as we aren't trying to use denormals.
1389 // 1.0 / sqrt(x) -> rsq(x)
1391 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
1392 // error seems really high at 2^29 ULP.
1393 if (RHS.getOpcode() == ISD::FSQRT)
1394 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
1396 // 1.0 / x -> rcp(x)
1397 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1402 // Turn into multiply by the reciprocal.
1403 // x / y -> x * (1.0 / y)
1405 Flags.setUnsafeAlgebra(true);
1406 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1407 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip, &Flags);
1413 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
1414 SDValue FastLowered = LowerFastFDIV(Op, DAG);
1415 if (FastLowered.getNode())
1418 // This uses v_rcp_f32 which does not handle denormals. Let this hit a
1419 // selection error for now rather than do something incorrect.
1420 if (Subtarget->hasFP32Denormals())
1424 SDValue LHS = Op.getOperand(0);
1425 SDValue RHS = Op.getOperand(1);
1427 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
1429 const APFloat K0Val(BitsToFloat(0x6f800000));
1430 const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
1432 const APFloat K1Val(BitsToFloat(0x2f800000));
1433 const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
1435 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
1438 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
1440 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
1442 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
1444 // TODO: Should this propagate fast-math-flags?
1446 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
1448 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
1450 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
1452 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
1455 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
1456 if (DAG.getTarget().Options.UnsafeFPMath)
1457 return LowerFastFDIV(Op, DAG);
1460 SDValue X = Op.getOperand(0);
1461 SDValue Y = Op.getOperand(1);
1463 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1465 SDVTList ScaleVT = DAG.getVTList(MVT::f64, MVT::i1);
1467 SDValue DivScale0 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, Y, Y, X);
1469 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0);
1471 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0);
1473 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One);
1475 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp);
1477 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One);
1479 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X);
1481 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1);
1482 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3);
1484 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64,
1485 NegDivScale0, Mul, DivScale1);
1489 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1490 // Workaround a hardware bug on SI where the condition output from div_scale
1493 const SDValue Hi = DAG.getConstant(1, SL, MVT::i32);
1495 // Figure out if the scale to use for div_fmas.
1496 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
1497 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y);
1498 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0);
1499 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1);
1501 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi);
1502 SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi);
1505 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi);
1507 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi);
1509 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ);
1510 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ);
1511 Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen);
1513 Scale = DivScale1.getValue(1);
1516 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64,
1517 Fma4, Fma3, Mul, Scale);
1519 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f64, Fmas, Y, X);
1522 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
1523 EVT VT = Op.getValueType();
1526 return LowerFDIV32(Op, DAG);
1529 return LowerFDIV64(Op, DAG);
1531 llvm_unreachable("Unexpected type for fdiv");
1534 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1536 StoreSDNode *Store = cast<StoreSDNode>(Op);
1537 EVT VT = Store->getMemoryVT();
1539 // These stores are legal.
1540 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
1541 if (VT.isVector() && VT.getVectorNumElements() > 4)
1542 return ScalarizeVectorStore(Op, DAG);
1546 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1550 if (VT.isVector() && VT.getVectorNumElements() >= 8)
1551 return SplitVectorStore(Op, DAG);
1554 return DAG.getTruncStore(Store->getChain(), DL,
1555 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
1556 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
1561 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1563 EVT VT = Op.getValueType();
1564 SDValue Arg = Op.getOperand(0);
1565 // TODO: Should this propagate fast-math-flags?
1566 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
1567 DAG.getNode(ISD::FMUL, DL, VT, Arg,
1568 DAG.getConstantFP(0.5/M_PI, DL,
1571 switch (Op.getOpcode()) {
1573 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
1575 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
1577 llvm_unreachable("Wrong trig opcode");
1581 //===----------------------------------------------------------------------===//
1582 // Custom DAG optimizations
1583 //===----------------------------------------------------------------------===//
1585 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1586 DAGCombinerInfo &DCI) const {
1587 EVT VT = N->getValueType(0);
1588 EVT ScalarVT = VT.getScalarType();
1589 if (ScalarVT != MVT::f32)
1592 SelectionDAG &DAG = DCI.DAG;
1595 SDValue Src = N->getOperand(0);
1596 EVT SrcVT = Src.getValueType();
1598 // TODO: We could try to match extracting the higher bytes, which would be
1599 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1600 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1601 // about in practice.
1602 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1603 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1604 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1605 DCI.AddToWorklist(Cvt.getNode());
1610 // We are primarily trying to catch operations on illegal vector types
1611 // before they are expanded.
1612 // For scalars, we can use the more flexible method of checking masked bits
1613 // after legalization.
1614 if (!DCI.isBeforeLegalize() ||
1615 !SrcVT.isVector() ||
1616 SrcVT.getVectorElementType() != MVT::i8) {
1620 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1622 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1624 unsigned NElts = SrcVT.getVectorNumElements();
1625 if (!SrcVT.isSimple() && NElts != 3)
1628 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1629 // prevent a mess from expanding to v4i32 and repacking.
1630 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1631 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1632 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1633 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1634 LoadSDNode *Load = cast<LoadSDNode>(Src);
1636 unsigned AS = Load->getAddressSpace();
1637 unsigned Align = Load->getAlignment();
1638 Type *Ty = LoadVT.getTypeForEVT(*DAG.getContext());
1639 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
1641 // Don't try to replace the load if we have to expand it due to alignment
1642 // problems. Otherwise we will end up scalarizing the load, and trying to
1643 // repack into the vector for no real reason.
1644 if (Align < ABIAlignment &&
1645 !allowsMisalignedMemoryAccesses(LoadVT, AS, Align, nullptr)) {
1649 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1653 Load->getMemOperand());
1655 // Make sure successors of the original load stay after it by updating
1656 // them to use the new Chain.
1657 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1659 SmallVector<SDValue, 4> Elts;
1660 if (RegVT.isVector())
1661 DAG.ExtractVectorElements(NewLoad, Elts);
1663 Elts.push_back(NewLoad);
1665 SmallVector<SDValue, 4> Ops;
1667 unsigned EltIdx = 0;
1668 for (SDValue Elt : Elts) {
1669 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1670 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1671 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1672 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1673 DCI.AddToWorklist(Cvt.getNode());
1680 assert(Ops.size() == NElts);
1682 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1688 /// \brief Return true if the given offset Size in bytes can be folded into
1689 /// the immediate offsets of a memory instruction for the given address space.
1690 static bool canFoldOffset(unsigned OffsetSize, unsigned AS,
1691 const AMDGPUSubtarget &STI) {
1693 case AMDGPUAS::GLOBAL_ADDRESS: {
1694 // MUBUF instructions a 12-bit offset in bytes.
1695 return isUInt<12>(OffsetSize);
1697 case AMDGPUAS::CONSTANT_ADDRESS: {
1698 // SMRD instructions have an 8-bit offset in dwords on SI and
1699 // a 20-bit offset in bytes on VI.
1700 if (STI.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1701 return isUInt<20>(OffsetSize);
1703 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
1705 case AMDGPUAS::LOCAL_ADDRESS:
1706 case AMDGPUAS::REGION_ADDRESS: {
1707 // The single offset versions have a 16-bit offset in bytes.
1708 return isUInt<16>(OffsetSize);
1710 case AMDGPUAS::PRIVATE_ADDRESS:
1711 // Indirect register addressing does not use any offsets.
1717 // (shl (add x, c1), c2) -> add (shl x, c2), (shl c1, c2)
1719 // This is a variant of
1720 // (mul (add x, c1), c2) -> add (mul x, c2), (mul c1, c2),
1722 // The normal DAG combiner will do this, but only if the add has one use since
1723 // that would increase the number of instructions.
1725 // This prevents us from seeing a constant offset that can be folded into a
1726 // memory instruction's addressing mode. If we know the resulting add offset of
1727 // a pointer can be folded into an addressing offset, we can replace the pointer
1728 // operand with the add of new constant offset. This eliminates one of the uses,
1729 // and may allow the remaining use to also be simplified.
1731 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
1733 DAGCombinerInfo &DCI) const {
1734 SDValue N0 = N->getOperand(0);
1735 SDValue N1 = N->getOperand(1);
1737 if (N0.getOpcode() != ISD::ADD)
1740 const ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N1);
1744 const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1748 // If the resulting offset is too large, we can't fold it into the addressing
1750 APInt Offset = CAdd->getAPIntValue() << CN1->getAPIntValue();
1751 if (!canFoldOffset(Offset.getZExtValue(), AddrSpace, *Subtarget))
1754 SelectionDAG &DAG = DCI.DAG;
1756 EVT VT = N->getValueType(0);
1758 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
1759 SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32);
1761 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset);
1764 SDValue SITargetLowering::performAndCombine(SDNode *N,
1765 DAGCombinerInfo &DCI) const {
1766 if (DCI.isBeforeLegalize())
1769 SelectionDAG &DAG = DCI.DAG;
1771 // (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
1772 // fp_class x, ~(s_nan | q_nan | n_infinity | p_infinity)
1773 SDValue LHS = N->getOperand(0);
1774 SDValue RHS = N->getOperand(1);
1776 if (LHS.getOpcode() == ISD::SETCC &&
1777 RHS.getOpcode() == ISD::SETCC) {
1778 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
1779 ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
1781 SDValue X = LHS.getOperand(0);
1782 SDValue Y = RHS.getOperand(0);
1783 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
1786 if (LCC == ISD::SETO) {
1787 if (X != LHS.getOperand(1))
1790 if (RCC == ISD::SETUNE) {
1791 const ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(RHS.getOperand(1));
1792 if (!C1 || !C1->isInfinity() || C1->isNegative())
1795 const uint32_t Mask = SIInstrFlags::N_NORMAL |
1796 SIInstrFlags::N_SUBNORMAL |
1797 SIInstrFlags::N_ZERO |
1798 SIInstrFlags::P_ZERO |
1799 SIInstrFlags::P_SUBNORMAL |
1800 SIInstrFlags::P_NORMAL;
1802 static_assert(((~(SIInstrFlags::S_NAN |
1803 SIInstrFlags::Q_NAN |
1804 SIInstrFlags::N_INFINITY |
1805 SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask,
1809 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
1810 X, DAG.getConstant(Mask, DL, MVT::i32));
1818 SDValue SITargetLowering::performOrCombine(SDNode *N,
1819 DAGCombinerInfo &DCI) const {
1820 SelectionDAG &DAG = DCI.DAG;
1821 SDValue LHS = N->getOperand(0);
1822 SDValue RHS = N->getOperand(1);
1824 // or (fp_class x, c1), (fp_class x, c2) -> fp_class x, (c1 | c2)
1825 if (LHS.getOpcode() == AMDGPUISD::FP_CLASS &&
1826 RHS.getOpcode() == AMDGPUISD::FP_CLASS) {
1827 SDValue Src = LHS.getOperand(0);
1828 if (Src != RHS.getOperand(0))
1831 const ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
1832 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
1836 // Only 10 bits are used.
1837 static const uint32_t MaxMask = 0x3ff;
1839 uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask;
1841 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
1842 Src, DAG.getConstant(NewMask, DL, MVT::i32));
1848 SDValue SITargetLowering::performClassCombine(SDNode *N,
1849 DAGCombinerInfo &DCI) const {
1850 SelectionDAG &DAG = DCI.DAG;
1851 SDValue Mask = N->getOperand(1);
1853 // fp_class x, 0 -> false
1854 if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
1855 if (CMask->isNullValue())
1856 return DAG.getConstant(0, SDLoc(N), MVT::i1);
1862 static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
1865 return AMDGPUISD::FMAX3;
1867 return AMDGPUISD::SMAX3;
1869 return AMDGPUISD::UMAX3;
1871 return AMDGPUISD::FMIN3;
1873 return AMDGPUISD::SMIN3;
1875 return AMDGPUISD::UMIN3;
1877 llvm_unreachable("Not a min/max opcode");
1881 SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
1882 DAGCombinerInfo &DCI) const {
1883 SelectionDAG &DAG = DCI.DAG;
1885 unsigned Opc = N->getOpcode();
1886 SDValue Op0 = N->getOperand(0);
1887 SDValue Op1 = N->getOperand(1);
1889 // Only do this if the inner op has one use since this will just increases
1890 // register pressure for no benefit.
1892 // max(max(a, b), c)
1893 if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
1895 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
1903 // max(a, max(b, c))
1904 if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
1906 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
1917 SDValue SITargetLowering::performSetCCCombine(SDNode *N,
1918 DAGCombinerInfo &DCI) const {
1919 SelectionDAG &DAG = DCI.DAG;
1922 SDValue LHS = N->getOperand(0);
1923 SDValue RHS = N->getOperand(1);
1924 EVT VT = LHS.getValueType();
1926 if (VT != MVT::f32 && VT != MVT::f64)
1929 // Match isinf pattern
1930 // (fcmp oeq (fabs x), inf) -> (fp_class x, (p_infinity | n_infinity))
1931 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
1932 if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) {
1933 const ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
1937 const APFloat &APF = CRHS->getValueAPF();
1938 if (APF.isInfinity() && !APF.isNegative()) {
1939 unsigned Mask = SIInstrFlags::P_INFINITY | SIInstrFlags::N_INFINITY;
1940 return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1, LHS.getOperand(0),
1941 DAG.getConstant(Mask, SL, MVT::i32));
1948 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1949 DAGCombinerInfo &DCI) const {
1950 SelectionDAG &DAG = DCI.DAG;
1953 switch (N->getOpcode()) {
1955 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1957 return performSetCCCombine(N, DCI);
1958 case ISD::FMAXNUM: // TODO: What about fmax_legacy?
1964 if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG &&
1965 N->getValueType(0) != MVT::f64 &&
1966 getTargetMachine().getOptLevel() > CodeGenOpt::None)
1967 return performMin3Max3Combine(N, DCI);
1971 case AMDGPUISD::CVT_F32_UBYTE0:
1972 case AMDGPUISD::CVT_F32_UBYTE1:
1973 case AMDGPUISD::CVT_F32_UBYTE2:
1974 case AMDGPUISD::CVT_F32_UBYTE3: {
1975 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
1977 SDValue Src = N->getOperand(0);
1978 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
1980 APInt KnownZero, KnownOne;
1981 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1982 !DCI.isBeforeLegalizeOps());
1983 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1984 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1985 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1986 DCI.CommitTargetLoweringOpt(TLO);
1992 case ISD::UINT_TO_FP: {
1993 return performUCharToFloatCombine(N, DCI);
1996 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
1999 EVT VT = N->getValueType(0);
2003 // Only do this if we are not trying to support denormals. v_mad_f32 does
2004 // not support denormals ever.
2005 if (Subtarget->hasFP32Denormals())
2008 SDValue LHS = N->getOperand(0);
2009 SDValue RHS = N->getOperand(1);
2011 // These should really be instruction patterns, but writing patterns with
2012 // source modiifiers is a pain.
2014 // fadd (fadd (a, a), b) -> mad 2.0, a, b
2015 if (LHS.getOpcode() == ISD::FADD) {
2016 SDValue A = LHS.getOperand(0);
2017 if (A == LHS.getOperand(1)) {
2018 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2019 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS);
2023 // fadd (b, fadd (a, a)) -> mad 2.0, a, b
2024 if (RHS.getOpcode() == ISD::FADD) {
2025 SDValue A = RHS.getOperand(0);
2026 if (A == RHS.getOperand(1)) {
2027 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2028 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS);
2035 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2038 EVT VT = N->getValueType(0);
2040 // Try to get the fneg to fold into the source modifier. This undoes generic
2041 // DAG combines and folds them into the mad.
2043 // Only do this if we are not trying to support denormals. v_mad_f32 does
2044 // not support denormals ever.
2045 if (VT == MVT::f32 &&
2046 !Subtarget->hasFP32Denormals()) {
2047 SDValue LHS = N->getOperand(0);
2048 SDValue RHS = N->getOperand(1);
2049 if (LHS.getOpcode() == ISD::FADD) {
2050 // (fsub (fadd a, a), c) -> mad 2.0, a, (fneg c)
2052 SDValue A = LHS.getOperand(0);
2053 if (A == LHS.getOperand(1)) {
2054 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2055 SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS);
2057 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS);
2061 if (RHS.getOpcode() == ISD::FADD) {
2062 // (fsub c, (fadd a, a)) -> mad -2.0, a, c
2064 SDValue A = RHS.getOperand(0);
2065 if (A == RHS.getOperand(1)) {
2066 const SDValue NegTwo = DAG.getConstantFP(-2.0, DL, MVT::f32);
2067 return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS);
2079 case ISD::ATOMIC_LOAD:
2080 case ISD::ATOMIC_STORE:
2081 case ISD::ATOMIC_CMP_SWAP:
2082 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
2083 case ISD::ATOMIC_SWAP:
2084 case ISD::ATOMIC_LOAD_ADD:
2085 case ISD::ATOMIC_LOAD_SUB:
2086 case ISD::ATOMIC_LOAD_AND:
2087 case ISD::ATOMIC_LOAD_OR:
2088 case ISD::ATOMIC_LOAD_XOR:
2089 case ISD::ATOMIC_LOAD_NAND:
2090 case ISD::ATOMIC_LOAD_MIN:
2091 case ISD::ATOMIC_LOAD_MAX:
2092 case ISD::ATOMIC_LOAD_UMIN:
2093 case ISD::ATOMIC_LOAD_UMAX: { // TODO: Target mem intrinsics.
2094 if (DCI.isBeforeLegalize())
2097 MemSDNode *MemNode = cast<MemSDNode>(N);
2098 SDValue Ptr = MemNode->getBasePtr();
2100 // TODO: We could also do this for multiplies.
2101 unsigned AS = MemNode->getAddressSpace();
2102 if (Ptr.getOpcode() == ISD::SHL && AS != AMDGPUAS::PRIVATE_ADDRESS) {
2103 SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), AS, DCI);
2105 SmallVector<SDValue, 8> NewOps(MemNode->op_begin(), MemNode->op_end());
2107 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
2108 return SDValue(DAG.UpdateNodeOperands(MemNode, NewOps), 0);
2114 return performAndCombine(N, DCI);
2116 return performOrCombine(N, DCI);
2117 case AMDGPUISD::FP_CLASS:
2118 return performClassCombine(N, DCI);
2120 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2123 /// \brief Analyze the possible immediate value Op
2125 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
2126 /// and the immediate value if it's a literal immediate
2127 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
2129 const SIInstrInfo *TII =
2130 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2132 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
2133 if (TII->isInlineConstant(Node->getAPIntValue()))
2136 uint64_t Val = Node->getZExtValue();
2137 return isUInt<32>(Val) ? Val : -1;
2140 if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
2141 if (TII->isInlineConstant(Node->getValueAPF().bitcastToAPInt()))
2144 if (Node->getValueType(0) == MVT::f32)
2145 return FloatToBits(Node->getValueAPF().convertToFloat());
2153 /// \brief Helper function for adjustWritemask
2154 static unsigned SubIdx2Lane(unsigned Idx) {
2157 case AMDGPU::sub0: return 0;
2158 case AMDGPU::sub1: return 1;
2159 case AMDGPU::sub2: return 2;
2160 case AMDGPU::sub3: return 3;
2164 /// \brief Adjust the writemask of MIMG instructions
2165 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
2166 SelectionDAG &DAG) const {
2167 SDNode *Users[4] = { };
2169 unsigned OldDmask = Node->getConstantOperandVal(0);
2170 unsigned NewDmask = 0;
2172 // Try to figure out the used register components
2173 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
2176 // Abort if we can't understand the usage
2177 if (!I->isMachineOpcode() ||
2178 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
2181 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
2182 // Note that subregs are packed, i.e. Lane==0 is the first bit set
2183 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
2185 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
2187 // Set which texture component corresponds to the lane.
2189 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
2191 Comp = countTrailingZeros(Dmask);
2192 Dmask &= ~(1 << Comp);
2195 // Abort if we have more than one user per component
2200 NewDmask |= 1 << Comp;
2203 // Abort if there's no change
2204 if (NewDmask == OldDmask)
2207 // Adjust the writemask in the node
2208 std::vector<SDValue> Ops;
2209 Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
2210 Ops.insert(Ops.end(), Node->op_begin() + 1, Node->op_end());
2211 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
2213 // If we only got one lane, replace it with a copy
2214 // (if NewDmask has only one bit set...)
2215 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
2216 SDValue RC = DAG.getTargetConstant(AMDGPU::VGPR_32RegClassID, SDLoc(),
2218 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
2219 SDLoc(), Users[Lane]->getValueType(0),
2220 SDValue(Node, 0), RC);
2221 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
2225 // Update the users of the node with the new indices
2226 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
2228 SDNode *User = Users[i];
2232 SDValue Op = DAG.getTargetConstant(Idx, SDLoc(User), MVT::i32);
2233 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
2237 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
2238 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
2239 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
2244 static bool isFrameIndexOp(SDValue Op) {
2245 if (Op.getOpcode() == ISD::AssertZext)
2246 Op = Op.getOperand(0);
2248 return isa<FrameIndexSDNode>(Op);
2251 /// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
2252 /// with frame index operands.
2253 /// LLVM assumes that inputs are to these instructions are registers.
2254 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
2255 SelectionDAG &DAG) const {
2257 SmallVector<SDValue, 8> Ops;
2258 for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
2259 if (!isFrameIndexOp(Node->getOperand(i))) {
2260 Ops.push_back(Node->getOperand(i));
2265 Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
2266 Node->getOperand(i).getValueType(),
2267 Node->getOperand(i)), 0));
2270 DAG.UpdateNodeOperands(Node, Ops);
2273 /// \brief Fold the instructions after selecting them.
2274 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
2275 SelectionDAG &DAG) const {
2276 const SIInstrInfo *TII =
2277 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2279 if (TII->isMIMG(Node->getMachineOpcode()))
2280 adjustWritemask(Node, DAG);
2282 if (Node->getMachineOpcode() == AMDGPU::INSERT_SUBREG ||
2283 Node->getMachineOpcode() == AMDGPU::REG_SEQUENCE) {
2284 legalizeTargetIndependentNode(Node, DAG);
2290 /// \brief Assign the register class depending on the number of
2291 /// bits set in the writemask
2292 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
2293 SDNode *Node) const {
2294 const SIInstrInfo *TII =
2295 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2297 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2299 if (TII->isVOP3(MI->getOpcode())) {
2300 // Make sure constant bus requirements are respected.
2301 TII->legalizeOperandsVOP3(MRI, MI);
2305 if (TII->isMIMG(*MI)) {
2306 unsigned VReg = MI->getOperand(0).getReg();
2307 unsigned Writemask = MI->getOperand(1).getImm();
2308 unsigned BitsSet = 0;
2309 for (unsigned i = 0; i < 4; ++i)
2310 BitsSet += Writemask & (1 << i) ? 1 : 0;
2312 const TargetRegisterClass *RC;
2315 case 1: RC = &AMDGPU::VGPR_32RegClass; break;
2316 case 2: RC = &AMDGPU::VReg_64RegClass; break;
2317 case 3: RC = &AMDGPU::VReg_96RegClass; break;
2320 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
2321 MI->setDesc(TII->get(NewOpcode));
2322 MRI.setRegClass(VReg, RC);
2326 // Replace unused atomics with the no return version.
2327 int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI->getOpcode());
2328 if (NoRetAtomicOp != -1) {
2329 if (!Node->hasAnyUseOfValue(0)) {
2330 MI->setDesc(TII->get(NoRetAtomicOp));
2331 MI->RemoveOperand(0);
2338 static SDValue buildSMovImm32(SelectionDAG &DAG, SDLoc DL, uint64_t Val) {
2339 SDValue K = DAG.getTargetConstant(Val, DL, MVT::i32);
2340 return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
2343 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
2345 SDValue Ptr) const {
2346 const SIInstrInfo *TII =
2347 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2349 // Build the half of the subregister with the constants before building the
2350 // full 128-bit register. If we are building multiple resource descriptors,
2351 // this will allow CSEing of the 2-component register.
2352 const SDValue Ops0[] = {
2353 DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, DL, MVT::i32),
2354 buildSMovImm32(DAG, DL, 0),
2355 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
2356 buildSMovImm32(DAG, DL, TII->getDefaultRsrcDataFormat() >> 32),
2357 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
2360 SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL,
2361 MVT::v2i32, Ops0), 0);
2363 // Combine the constants and the pointer.
2364 const SDValue Ops1[] = {
2365 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
2367 DAG.getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32),
2369 DAG.getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32)
2372 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
2375 /// \brief Return a resource descriptor with the 'Add TID' bit enabled
2376 /// The TID (Thread ID) is multiplied by the stride value (bits [61:48]
2377 /// of the resource descriptor) to create an offset, which is added to
2378 /// the resource pointer.
2379 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,
2382 uint32_t RsrcDword1,
2383 uint64_t RsrcDword2And3) const {
2384 SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
2385 SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
2387 PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
2388 DAG.getConstant(RsrcDword1, DL, MVT::i32)),
2392 SDValue DataLo = buildSMovImm32(DAG, DL,
2393 RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
2394 SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
2396 const SDValue Ops[] = {
2397 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
2399 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
2401 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32),
2403 DAG.getTargetConstant(AMDGPU::sub2, DL, MVT::i32),
2405 DAG.getTargetConstant(AMDGPU::sub3, DL, MVT::i32)
2408 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
2411 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2412 const TargetRegisterClass *RC,
2413 unsigned Reg, EVT VT) const {
2414 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
2416 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
2417 cast<RegisterSDNode>(VReg)->getReg(), VT);
2420 //===----------------------------------------------------------------------===//
2421 // SI Inline Assembly Support
2422 //===----------------------------------------------------------------------===//
2424 std::pair<unsigned, const TargetRegisterClass *>
2425 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2426 StringRef Constraint,
2429 if (Constraint.size() == 1) {
2430 switch (Constraint[0]) {
2433 switch (VT.getSizeInBits()) {
2435 return std::make_pair(0U, nullptr);
2437 return std::make_pair(0U, &AMDGPU::SGPR_32RegClass);
2439 return std::make_pair(0U, &AMDGPU::SGPR_64RegClass);
2441 return std::make_pair(0U, &AMDGPU::SReg_128RegClass);
2443 return std::make_pair(0U, &AMDGPU::SReg_256RegClass);
2447 switch (VT.getSizeInBits()) {
2449 return std::make_pair(0U, nullptr);
2451 return std::make_pair(0U, &AMDGPU::VGPR_32RegClass);
2453 return std::make_pair(0U, &AMDGPU::VReg_64RegClass);
2455 return std::make_pair(0U, &AMDGPU::VReg_96RegClass);
2457 return std::make_pair(0U, &AMDGPU::VReg_128RegClass);
2459 return std::make_pair(0U, &AMDGPU::VReg_256RegClass);
2461 return std::make_pair(0U, &AMDGPU::VReg_512RegClass);
2466 if (Constraint.size() > 1) {
2467 const TargetRegisterClass *RC = nullptr;
2468 if (Constraint[1] == 'v') {
2469 RC = &AMDGPU::VGPR_32RegClass;
2470 } else if (Constraint[1] == 's') {
2471 RC = &AMDGPU::SGPR_32RegClass;
2476 bool Failed = Constraint.substr(2).getAsInteger(10, Idx);
2477 if (!Failed && Idx < RC->getNumRegs())
2478 return std::make_pair(RC->getRegister(Idx), RC);
2481 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2484 SITargetLowering::ConstraintType
2485 SITargetLowering::getConstraintType(StringRef Constraint) const {
2486 if (Constraint.size() == 1) {
2487 switch (Constraint[0]) {
2491 return C_RegisterClass;
2494 return TargetLowering::getConstraintType(Constraint);