1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUDiagnosticInfoUnsupported.h"
19 #include "AMDGPUFrameLowering.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPURegisterInfo.h"
22 #include "AMDGPUSubtarget.h"
23 #include "R600MachineFunctionInfo.h"
24 #include "SIMachineFunctionInfo.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
34 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
35 CCValAssign::LocInfo LocInfo,
36 ISD::ArgFlagsTy ArgFlags, CCState &State) {
37 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
38 ArgFlags.getOrigAlign());
39 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
44 #include "AMDGPUGenCallingConv.inc"
46 // Find a larger type to do a load / store of a vector with.
47 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
48 unsigned StoreSize = VT.getStoreSizeInBits();
50 return EVT::getIntegerVT(Ctx, StoreSize);
52 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
53 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
56 // Type for a vector that will be loaded to.
57 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
58 unsigned StoreSize = VT.getStoreSizeInBits();
60 return EVT::getIntegerVT(Ctx, 32);
62 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
65 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
66 const AMDGPUSubtarget &STI)
67 : TargetLowering(TM), Subtarget(&STI) {
68 setOperationAction(ISD::Constant, MVT::i32, Legal);
69 setOperationAction(ISD::Constant, MVT::i64, Legal);
70 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
71 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
73 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
74 setOperationAction(ISD::BRIND, MVT::Other, Expand);
76 // This is totally unsupported, just custom lower to produce an error.
77 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
79 // We need to custom lower some of the intrinsics
80 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
82 // Library functions. These default to Expand, but we have instructions
84 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
85 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
86 setOperationAction(ISD::FPOW, MVT::f32, Legal);
87 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
88 setOperationAction(ISD::FABS, MVT::f32, Legal);
89 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
90 setOperationAction(ISD::FRINT, MVT::f32, Legal);
91 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
92 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
93 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
95 setOperationAction(ISD::FROUND, MVT::f32, Custom);
96 setOperationAction(ISD::FROUND, MVT::f64, Custom);
98 setOperationAction(ISD::FREM, MVT::f32, Custom);
99 setOperationAction(ISD::FREM, MVT::f64, Custom);
101 // v_mad_f32 does not support denormals according to some sources.
102 if (!Subtarget->hasFP32Denormals())
103 setOperationAction(ISD::FMAD, MVT::f32, Legal);
105 // Expand to fneg + fadd.
106 setOperationAction(ISD::FSUB, MVT::f64, Expand);
108 // Lower floating point store/load to integer store/load to reduce the number
109 // of patterns in tablegen.
110 setOperationAction(ISD::STORE, MVT::f32, Promote);
111 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
113 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
114 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
116 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
117 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
119 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
120 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
122 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
123 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
125 setOperationAction(ISD::STORE, MVT::f64, Promote);
126 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
128 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
129 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
131 // Custom lowering of vector stores is required for local address space
133 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
135 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
136 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
137 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
139 // XXX: This can be change to Custom, once ExpandVectorStores can
140 // handle 64-bit stores.
141 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
143 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
146 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
147 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
150 setOperationAction(ISD::LOAD, MVT::f32, Promote);
151 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
153 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
154 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
156 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
157 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
159 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
160 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
162 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
163 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
165 setOperationAction(ISD::LOAD, MVT::f64, Promote);
166 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
168 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
169 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
171 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
172 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
173 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
174 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
175 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
176 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
177 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
178 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
179 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
180 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
182 // There are no 64-bit extloads. These should be done as a 32-bit extload and
183 // an extension to 64-bit.
184 for (MVT VT : MVT::integer_valuetypes()) {
185 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
186 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
187 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
190 for (MVT VT : MVT::integer_vector_valuetypes()) {
191 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
192 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
193 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
194 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
195 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
196 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
197 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
198 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
199 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
200 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
201 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
202 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
205 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
207 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
208 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
209 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
210 setOperationAction(ISD::FRINT, MVT::f64, Custom);
211 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
214 if (!Subtarget->hasBFI()) {
215 // fcopysign can be done in a single instruction with BFI.
216 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
217 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
220 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
222 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
223 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
225 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
227 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
228 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
229 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
230 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
232 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
233 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
234 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
235 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
237 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
238 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
240 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
241 for (MVT VT : ScalarIntVTs) {
242 setOperationAction(ISD::SREM, VT, Expand);
243 setOperationAction(ISD::SDIV, VT, Expand);
245 // GPU does not have divrem function for signed or unsigned.
246 setOperationAction(ISD::SDIVREM, VT, Custom);
247 setOperationAction(ISD::UDIVREM, VT, Custom);
249 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
250 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
251 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
253 setOperationAction(ISD::BSWAP, VT, Expand);
254 setOperationAction(ISD::CTTZ, VT, Expand);
255 setOperationAction(ISD::CTLZ, VT, Expand);
258 if (!Subtarget->hasBCNT(32))
259 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
261 if (!Subtarget->hasBCNT(64))
262 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
264 // The hardware supports 32-bit ROTR, but not ROTL.
265 setOperationAction(ISD::ROTL, MVT::i32, Expand);
266 setOperationAction(ISD::ROTL, MVT::i64, Expand);
267 setOperationAction(ISD::ROTR, MVT::i64, Expand);
269 setOperationAction(ISD::MUL, MVT::i64, Expand);
270 setOperationAction(ISD::MULHU, MVT::i64, Expand);
271 setOperationAction(ISD::MULHS, MVT::i64, Expand);
272 setOperationAction(ISD::UDIV, MVT::i32, Expand);
273 setOperationAction(ISD::UREM, MVT::i32, Expand);
274 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
275 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
276 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
277 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
278 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
280 setOperationAction(ISD::SMIN, MVT::i32, Legal);
281 setOperationAction(ISD::UMIN, MVT::i32, Legal);
282 setOperationAction(ISD::SMAX, MVT::i32, Legal);
283 setOperationAction(ISD::UMAX, MVT::i32, Legal);
285 if (!Subtarget->hasFFBH())
286 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
288 if (!Subtarget->hasFFBL())
289 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
291 static const MVT::SimpleValueType VectorIntTypes[] = {
292 MVT::v2i32, MVT::v4i32
295 for (MVT VT : VectorIntTypes) {
296 // Expand the following operations for the current type by default.
297 setOperationAction(ISD::ADD, VT, Expand);
298 setOperationAction(ISD::AND, VT, Expand);
299 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
300 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
301 setOperationAction(ISD::MUL, VT, Expand);
302 setOperationAction(ISD::OR, VT, Expand);
303 setOperationAction(ISD::SHL, VT, Expand);
304 setOperationAction(ISD::SRA, VT, Expand);
305 setOperationAction(ISD::SRL, VT, Expand);
306 setOperationAction(ISD::ROTL, VT, Expand);
307 setOperationAction(ISD::ROTR, VT, Expand);
308 setOperationAction(ISD::SUB, VT, Expand);
309 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
310 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
311 setOperationAction(ISD::SDIV, VT, Expand);
312 setOperationAction(ISD::UDIV, VT, Expand);
313 setOperationAction(ISD::SREM, VT, Expand);
314 setOperationAction(ISD::UREM, VT, Expand);
315 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
316 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
317 setOperationAction(ISD::SDIVREM, VT, Custom);
318 setOperationAction(ISD::UDIVREM, VT, Expand);
319 setOperationAction(ISD::ADDC, VT, Expand);
320 setOperationAction(ISD::SUBC, VT, Expand);
321 setOperationAction(ISD::ADDE, VT, Expand);
322 setOperationAction(ISD::SUBE, VT, Expand);
323 setOperationAction(ISD::SELECT, VT, Expand);
324 setOperationAction(ISD::VSELECT, VT, Expand);
325 setOperationAction(ISD::SELECT_CC, VT, Expand);
326 setOperationAction(ISD::XOR, VT, Expand);
327 setOperationAction(ISD::BSWAP, VT, Expand);
328 setOperationAction(ISD::CTPOP, VT, Expand);
329 setOperationAction(ISD::CTTZ, VT, Expand);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
331 setOperationAction(ISD::CTLZ, VT, Expand);
332 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
333 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
336 static const MVT::SimpleValueType FloatVectorTypes[] = {
337 MVT::v2f32, MVT::v4f32
340 for (MVT VT : FloatVectorTypes) {
341 setOperationAction(ISD::FABS, VT, Expand);
342 setOperationAction(ISD::FMINNUM, VT, Expand);
343 setOperationAction(ISD::FMAXNUM, VT, Expand);
344 setOperationAction(ISD::FADD, VT, Expand);
345 setOperationAction(ISD::FCEIL, VT, Expand);
346 setOperationAction(ISD::FCOS, VT, Expand);
347 setOperationAction(ISD::FDIV, VT, Expand);
348 setOperationAction(ISD::FEXP2, VT, Expand);
349 setOperationAction(ISD::FLOG2, VT, Expand);
350 setOperationAction(ISD::FREM, VT, Expand);
351 setOperationAction(ISD::FPOW, VT, Expand);
352 setOperationAction(ISD::FFLOOR, VT, Expand);
353 setOperationAction(ISD::FTRUNC, VT, Expand);
354 setOperationAction(ISD::FMUL, VT, Expand);
355 setOperationAction(ISD::FMA, VT, Expand);
356 setOperationAction(ISD::FRINT, VT, Expand);
357 setOperationAction(ISD::FNEARBYINT, VT, Expand);
358 setOperationAction(ISD::FSQRT, VT, Expand);
359 setOperationAction(ISD::FSIN, VT, Expand);
360 setOperationAction(ISD::FSUB, VT, Expand);
361 setOperationAction(ISD::FNEG, VT, Expand);
362 setOperationAction(ISD::SELECT, VT, Expand);
363 setOperationAction(ISD::VSELECT, VT, Expand);
364 setOperationAction(ISD::SELECT_CC, VT, Expand);
365 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
366 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
369 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
370 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
372 setTargetDAGCombine(ISD::SHL);
373 setTargetDAGCombine(ISD::MUL);
374 setTargetDAGCombine(ISD::SELECT);
375 setTargetDAGCombine(ISD::SELECT_CC);
376 setTargetDAGCombine(ISD::STORE);
378 setTargetDAGCombine(ISD::FADD);
379 setTargetDAGCombine(ISD::FSUB);
381 setBooleanContents(ZeroOrNegativeOneBooleanContent);
382 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
384 setSchedulingPreference(Sched::RegPressure);
385 setJumpIsExpensive(true);
387 // SI at least has hardware support for floating point exceptions, but no way
388 // of using or handling them is implemented. They are also optional in OpenCL
390 setHasFloatingPointExceptions(false);
392 setSelectIsExpensive(false);
393 PredictableSelectIsExpensive = false;
395 setFsqrtIsCheap(true);
397 // FIXME: Need to really handle these.
398 MaxStoresPerMemcpy = 4096;
399 MaxStoresPerMemmove = 4096;
400 MaxStoresPerMemset = 4096;
403 //===----------------------------------------------------------------------===//
404 // Target Information
405 //===----------------------------------------------------------------------===//
407 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
411 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
415 // The backend supports 32 and 64 bit floating point immediates.
416 // FIXME: Why are we reporting vectors of FP immediates as legal?
417 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
418 EVT ScalarVT = VT.getScalarType();
419 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
422 // We don't want to shrink f64 / f32 constants.
423 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
424 EVT ScalarVT = VT.getScalarType();
425 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
428 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
432 unsigned NewSize = NewVT.getStoreSizeInBits();
434 // If we are reducing to a 32-bit load, this is always better.
438 EVT OldVT = N->getValueType(0);
439 unsigned OldSize = OldVT.getStoreSizeInBits();
441 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
442 // extloads, so doing one requires using a buffer_load. In cases where we
443 // still couldn't use a scalar load, using the wider load shouldn't really
446 // If the old size already had to be an extload, there's no harm in continuing
447 // to reduce the width.
448 return (OldSize < 32);
451 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
453 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
456 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
457 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
459 return ((LScalarSize <= CastScalarSize) ||
460 (CastScalarSize >= 32) ||
464 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
465 // profitable with the expansion for 64-bit since it's generally good to
467 // FIXME: These should really have the size as a parameter.
468 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
472 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
476 //===---------------------------------------------------------------------===//
478 //===---------------------------------------------------------------------===//
480 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
481 assert(VT.isFloatingPoint());
482 return VT == MVT::f32 || VT == MVT::f64;
485 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
486 assert(VT.isFloatingPoint());
487 return VT == MVT::f32 || VT == MVT::f64;
490 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
496 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
497 // There are few operations which truly have vector input operands. Any vector
498 // operation is going to involve operations on each component, and a
499 // build_vector will be a copy per element, so it always makes sense to use a
500 // build_vector input in place of the extracted element to avoid a copy into a
503 // We should probably only do this if all users are extracts only, but this
504 // should be the common case.
508 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
509 // Truncate is just accessing a subregister.
510 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
513 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
514 // Truncate is just accessing a subregister.
515 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
516 (Dest->getPrimitiveSizeInBits() % 32 == 0);
519 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
520 unsigned SrcSize = Src->getScalarSizeInBits();
521 unsigned DestSize = Dest->getScalarSizeInBits();
523 return SrcSize == 32 && DestSize == 64;
526 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
527 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
528 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
529 // this will enable reducing 64-bit operations the 32-bit, which is always
531 return Src == MVT::i32 && Dest == MVT::i64;
534 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
535 return isZExtFree(Val.getValueType(), VT2);
538 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
539 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
540 // limited number of native 64-bit operations. Shrinking an operation to fit
541 // in a single 32-bit register should always be helpful. As currently used,
542 // this is much less general than the name suggests, and is only used in
543 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
544 // not profitable, and may actually be harmful.
545 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
548 //===---------------------------------------------------------------------===//
549 // TargetLowering Callbacks
550 //===---------------------------------------------------------------------===//
552 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
553 const SmallVectorImpl<ISD::InputArg> &Ins) const {
555 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
558 SDValue AMDGPUTargetLowering::LowerReturn(
560 CallingConv::ID CallConv,
562 const SmallVectorImpl<ISD::OutputArg> &Outs,
563 const SmallVectorImpl<SDValue> &OutVals,
564 SDLoc DL, SelectionDAG &DAG) const {
565 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
568 //===---------------------------------------------------------------------===//
569 // Target specific lowering
570 //===---------------------------------------------------------------------===//
572 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
573 SmallVectorImpl<SDValue> &InVals) const {
574 SDValue Callee = CLI.Callee;
575 SelectionDAG &DAG = CLI.DAG;
577 const Function &Fn = *DAG.getMachineFunction().getFunction();
579 StringRef FuncName("<unknown>");
581 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
582 FuncName = G->getSymbol();
583 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
584 FuncName = G->getGlobal()->getName();
586 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
587 DAG.getContext()->diagnose(NoCalls);
591 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
592 SelectionDAG &DAG) const {
593 const Function &Fn = *DAG.getMachineFunction().getFunction();
595 DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "dynamic alloca");
596 DAG.getContext()->diagnose(NoDynamicAlloca);
600 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
601 SelectionDAG &DAG) const {
602 switch (Op.getOpcode()) {
604 Op.getNode()->dump();
605 llvm_unreachable("Custom lowering code for this"
606 "instruction is not implemented yet!");
608 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
609 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
610 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
611 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
612 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
613 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
614 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
615 case ISD::FREM: return LowerFREM(Op, DAG);
616 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
617 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
618 case ISD::FRINT: return LowerFRINT(Op, DAG);
619 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
620 case ISD::FROUND: return LowerFROUND(Op, DAG);
621 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
622 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
623 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
624 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
625 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
626 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
631 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
632 SmallVectorImpl<SDValue> &Results,
633 SelectionDAG &DAG) const {
634 switch (N->getOpcode()) {
635 case ISD::SIGN_EXTEND_INREG:
636 // Different parts of legalization seem to interpret which type of
637 // sign_extend_inreg is the one to check for custom lowering. The extended
638 // from type is what really matters, but some places check for custom
639 // lowering of the result type. This results in trying to use
640 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
641 // nothing here and let the illegal result integer be handled normally.
644 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
648 Results.push_back(SDValue(Node, 0));
649 Results.push_back(SDValue(Node, 1));
650 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
652 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
656 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
657 if (Lowered.getNode())
658 Results.push_back(Lowered);
666 // FIXME: This implements accesses to initialized globals in the constant
667 // address space by copying them to private and accessing that. It does not
668 // properly handle illegal types or vectors. The private vector loads are not
669 // scalarized, and the illegal scalars hit an assertion. This technique will not
670 // work well with large initializers, and this should eventually be
671 // removed. Initialized globals should be placed into a data section that the
672 // runtime will load into a buffer before the kernel is executed. Uses of the
673 // global need to be replaced with a pointer loaded from an implicit kernel
674 // argument into this buffer holding the copy of the data, which will remove the
675 // need for any of this.
676 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
677 const GlobalValue *GV,
678 const SDValue &InitPtr,
680 SelectionDAG &DAG) const {
681 const DataLayout &TD = DAG.getDataLayout();
683 Type *InitTy = Init->getType();
685 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
686 EVT VT = EVT::getEVT(InitTy);
687 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
688 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, DL, VT), InitPtr,
689 MachinePointerInfo(UndefValue::get(PtrTy)), false,
690 false, TD.getPrefTypeAlignment(InitTy));
693 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
694 EVT VT = EVT::getEVT(CFP->getType());
695 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
696 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, DL, VT), InitPtr,
697 MachinePointerInfo(UndefValue::get(PtrTy)), false,
698 false, TD.getPrefTypeAlignment(CFP->getType()));
701 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
702 const StructLayout *SL = TD.getStructLayout(ST);
704 EVT PtrVT = InitPtr.getValueType();
705 SmallVector<SDValue, 8> Chains;
707 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
708 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), DL, PtrVT);
709 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
711 Constant *Elt = Init->getAggregateElement(I);
712 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
715 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
718 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
719 EVT PtrVT = InitPtr.getValueType();
721 unsigned NumElements;
722 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
723 NumElements = AT->getNumElements();
724 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
725 NumElements = VT->getNumElements();
727 llvm_unreachable("Unexpected type");
729 unsigned EltSize = TD.getTypeAllocSize(SeqTy->getElementType());
730 SmallVector<SDValue, 8> Chains;
731 for (unsigned i = 0; i < NumElements; ++i) {
732 SDValue Offset = DAG.getConstant(i * EltSize, DL, PtrVT);
733 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
735 Constant *Elt = Init->getAggregateElement(i);
736 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
739 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
742 if (isa<UndefValue>(Init)) {
743 EVT VT = EVT::getEVT(InitTy);
744 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
745 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
746 MachinePointerInfo(UndefValue::get(PtrTy)), false,
747 false, TD.getPrefTypeAlignment(InitTy));
751 llvm_unreachable("Unhandled constant initializer");
754 static bool hasDefinedInitializer(const GlobalValue *GV) {
755 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
756 if (!GVar || !GVar->hasInitializer())
759 if (isa<UndefValue>(GVar->getInitializer()))
765 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
767 SelectionDAG &DAG) const {
769 const DataLayout &DL = DAG.getDataLayout();
770 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
771 const GlobalValue *GV = G->getGlobal();
773 switch (G->getAddressSpace()) {
774 case AMDGPUAS::LOCAL_ADDRESS: {
775 // XXX: What does the value of G->getOffset() mean?
776 assert(G->getOffset() == 0 &&
777 "Do not know what to do with an non-zero offset");
779 // TODO: We could emit code to handle the initialization somewhere.
780 if (hasDefinedInitializer(GV))
784 if (MFI->LocalMemoryObjects.count(GV) == 0) {
785 uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());
786 Offset = MFI->LDSSize;
787 MFI->LocalMemoryObjects[GV] = Offset;
788 // XXX: Account for alignment?
789 MFI->LDSSize += Size;
791 Offset = MFI->LocalMemoryObjects[GV];
794 return DAG.getConstant(Offset, SDLoc(Op),
795 getPointerTy(DL, AMDGPUAS::LOCAL_ADDRESS));
797 case AMDGPUAS::CONSTANT_ADDRESS: {
798 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
799 Type *EltType = GV->getType()->getElementType();
800 unsigned Size = DL.getTypeAllocSize(EltType);
801 unsigned Alignment = DL.getPrefTypeAlignment(EltType);
803 MVT PrivPtrVT = getPointerTy(DL, AMDGPUAS::PRIVATE_ADDRESS);
804 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
806 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
807 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
809 const GlobalVariable *Var = cast<GlobalVariable>(GV);
810 if (!Var->hasInitializer()) {
811 // This has no use, but bugpoint will hit it.
812 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
815 const Constant *Init = Var->getInitializer();
816 SmallVector<SDNode*, 8> WorkList;
818 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
819 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
820 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
822 WorkList.push_back(*I);
824 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
825 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
826 E = WorkList.end(); I != E; ++I) {
827 SmallVector<SDValue, 8> Ops;
828 Ops.push_back(Chain);
829 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
830 Ops.push_back((*I)->getOperand(i));
832 DAG.UpdateNodeOperands(*I, Ops);
834 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
838 const Function &Fn = *DAG.getMachineFunction().getFunction();
839 DiagnosticInfoUnsupported BadInit(Fn,
840 "initializer for address space");
841 DAG.getContext()->diagnose(BadInit);
845 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
846 SelectionDAG &DAG) const {
847 SmallVector<SDValue, 8> Args;
849 for (const SDUse &U : Op->ops())
850 DAG.ExtractVectorElements(U.get(), Args);
852 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
855 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
856 SelectionDAG &DAG) const {
858 SmallVector<SDValue, 8> Args;
859 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
860 EVT VT = Op.getValueType();
861 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
862 VT.getVectorNumElements());
864 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
867 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
868 SelectionDAG &DAG) const {
870 MachineFunction &MF = DAG.getMachineFunction();
871 const AMDGPUFrameLowering *TFL = Subtarget->getFrameLowering();
873 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
875 unsigned FrameIndex = FIN->getIndex();
876 unsigned IgnoredFrameReg;
878 TFL->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
879 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op),
883 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
884 SelectionDAG &DAG) const {
885 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
887 EVT VT = Op.getValueType();
889 switch (IntrinsicID) {
891 case AMDGPUIntrinsic::AMDGPU_abs:
892 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
893 return LowerIntrinsicIABS(Op, DAG);
894 case AMDGPUIntrinsic::AMDGPU_lrp:
895 return LowerIntrinsicLRP(Op, DAG);
897 case AMDGPUIntrinsic::AMDGPU_clamp:
898 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
899 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
900 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
902 case Intrinsic::AMDGPU_div_scale: {
903 // 3rd parameter required to be a constant.
904 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
906 return DAG.getUNDEF(VT);
908 // Translate to the operands expected by the machine instruction. The
909 // first parameter must be the same as the first instruction.
910 SDValue Numerator = Op.getOperand(1);
911 SDValue Denominator = Op.getOperand(2);
913 // Note this order is opposite of the machine instruction's operations,
914 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
915 // intrinsic has the numerator as the first operand to match a normal
916 // division operation.
918 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
920 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
921 Denominator, Numerator);
924 case Intrinsic::AMDGPU_div_fmas:
925 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
926 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
929 case Intrinsic::AMDGPU_div_fixup:
930 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
931 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
933 case Intrinsic::AMDGPU_trig_preop:
934 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
935 Op.getOperand(1), Op.getOperand(2));
937 case Intrinsic::AMDGPU_rcp:
938 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
940 case Intrinsic::AMDGPU_rsq:
941 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
943 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
944 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
946 case Intrinsic::AMDGPU_rsq_clamped:
947 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
948 Type *Type = VT.getTypeForEVT(*DAG.getContext());
949 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
950 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
952 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
953 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
954 DAG.getConstantFP(Max, DL, VT));
955 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
956 DAG.getConstantFP(Min, DL, VT));
958 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
961 case Intrinsic::AMDGPU_ldexp:
962 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
965 case AMDGPUIntrinsic::AMDGPU_imax:
966 return DAG.getNode(ISD::SMAX, DL, VT, Op.getOperand(1),
968 case AMDGPUIntrinsic::AMDGPU_umax:
969 return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1),
971 case AMDGPUIntrinsic::AMDGPU_imin:
972 return DAG.getNode(ISD::SMIN, DL, VT, Op.getOperand(1),
974 case AMDGPUIntrinsic::AMDGPU_umin:
975 return DAG.getNode(ISD::UMIN, DL, VT, Op.getOperand(1),
978 case AMDGPUIntrinsic::AMDGPU_umul24:
979 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
980 Op.getOperand(1), Op.getOperand(2));
982 case AMDGPUIntrinsic::AMDGPU_imul24:
983 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
984 Op.getOperand(1), Op.getOperand(2));
986 case AMDGPUIntrinsic::AMDGPU_umad24:
987 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
988 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
990 case AMDGPUIntrinsic::AMDGPU_imad24:
991 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
992 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
994 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
995 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
997 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
998 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
1000 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
1001 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
1003 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
1004 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
1006 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
1007 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
1012 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
1013 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
1018 case AMDGPUIntrinsic::AMDGPU_bfi:
1019 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
1024 case AMDGPUIntrinsic::AMDGPU_bfm:
1025 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1029 case AMDGPUIntrinsic::AMDGPU_brev:
1030 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
1032 case Intrinsic::AMDGPU_class:
1033 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1034 Op.getOperand(1), Op.getOperand(2));
1036 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1037 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1039 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1040 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1041 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1042 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1046 ///IABS(a) = SMAX(sub(0, a), a)
1047 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1048 SelectionDAG &DAG) const {
1050 EVT VT = Op.getValueType();
1051 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1054 return DAG.getNode(ISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1057 /// Linear Interpolation
1058 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
1059 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1060 SelectionDAG &DAG) const {
1062 EVT VT = Op.getValueType();
1063 // TODO: Should this propagate fast-math-flags?
1064 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1065 DAG.getConstantFP(1.0f, DL, MVT::f32),
1067 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1069 return DAG.getNode(ISD::FADD, DL, VT,
1070 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1074 /// \brief Generate Min/Max node
1075 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1082 DAGCombinerInfo &DCI) const {
1083 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1086 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1089 SelectionDAG &DAG = DCI.DAG;
1090 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1099 case ISD::SETFALSE2:
1108 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1109 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1115 // Ordered. Assume ordered for undefined.
1117 // Only do this after legalization to avoid interfering with other combines
1118 // which might occur.
1119 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1120 !DCI.isCalledByLegalizer())
1123 // We need to permute the operands to get the correct NaN behavior. The
1124 // selected operand is the second one based on the failing compare with NaN,
1125 // so permute it based on the compare type the hardware uses.
1127 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1128 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1133 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1134 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1140 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1141 !DCI.isCalledByLegalizer())
1145 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1146 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1148 case ISD::SETCC_INVALID:
1149 llvm_unreachable("Invalid setcc condcode!");
1154 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1155 SelectionDAG &DAG) const {
1156 LoadSDNode *Load = cast<LoadSDNode>(Op);
1157 EVT MemVT = Load->getMemoryVT();
1158 EVT MemEltVT = MemVT.getVectorElementType();
1160 EVT LoadVT = Op.getValueType();
1161 EVT EltVT = LoadVT.getVectorElementType();
1162 EVT PtrVT = Load->getBasePtr().getValueType();
1164 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1165 SmallVector<SDValue, 8> Loads;
1166 SmallVector<SDValue, 8> Chains;
1169 unsigned MemEltSize = MemEltVT.getStoreSize();
1170 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1172 for (unsigned i = 0; i < NumElts; ++i) {
1173 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1174 DAG.getConstant(i * MemEltSize, SL, PtrVT));
1177 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1178 Load->getChain(), Ptr,
1179 SrcValue.getWithOffset(i * MemEltSize),
1180 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1181 Load->isInvariant(), Load->getAlignment());
1182 Loads.push_back(NewLoad.getValue(0));
1183 Chains.push_back(NewLoad.getValue(1));
1187 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1188 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1191 return DAG.getMergeValues(Ops, SL);
1194 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1195 SelectionDAG &DAG) const {
1196 EVT VT = Op.getValueType();
1198 // If this is a 2 element vector, we really want to scalarize and not create
1199 // weird 1 element vectors.
1200 if (VT.getVectorNumElements() == 2)
1201 return ScalarizeVectorLoad(Op, DAG);
1203 LoadSDNode *Load = cast<LoadSDNode>(Op);
1204 SDValue BasePtr = Load->getBasePtr();
1205 EVT PtrVT = BasePtr.getValueType();
1206 EVT MemVT = Load->getMemoryVT();
1208 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1211 EVT LoMemVT, HiMemVT;
1214 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1215 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1216 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1218 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1219 Load->getChain(), BasePtr,
1221 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1222 Load->isInvariant(), Load->getAlignment());
1224 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1225 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1229 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1230 Load->getChain(), HiPtr,
1231 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1232 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1233 Load->isInvariant(), Load->getAlignment());
1236 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1237 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1238 LoLoad.getValue(1), HiLoad.getValue(1))
1241 return DAG.getMergeValues(Ops, SL);
1244 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1245 SelectionDAG &DAG) const {
1246 StoreSDNode *Store = cast<StoreSDNode>(Op);
1247 EVT MemVT = Store->getMemoryVT();
1248 unsigned MemBits = MemVT.getSizeInBits();
1250 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1251 // truncating store into an i32 store.
1252 // XXX: We could also handle optimize other vector bitwidths.
1253 if (!MemVT.isVector() || MemBits > 32) {
1258 SDValue Value = Store->getValue();
1259 EVT VT = Value.getValueType();
1260 EVT ElemVT = VT.getVectorElementType();
1261 SDValue Ptr = Store->getBasePtr();
1262 EVT MemEltVT = MemVT.getVectorElementType();
1263 unsigned MemEltBits = MemEltVT.getSizeInBits();
1264 unsigned MemNumElements = MemVT.getVectorNumElements();
1265 unsigned PackedSize = MemVT.getStoreSizeInBits();
1266 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, DL, MVT::i32);
1268 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1270 SDValue PackedValue;
1271 for (unsigned i = 0; i < MemNumElements; ++i) {
1272 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1273 DAG.getConstant(i, DL, MVT::i32));
1274 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1275 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1277 SDValue Shift = DAG.getConstant(MemEltBits * i, DL, MVT::i32);
1278 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1283 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1287 if (PackedSize < 32) {
1288 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1289 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1290 Store->getMemOperand()->getPointerInfo(),
1292 Store->isNonTemporal(), Store->isVolatile(),
1293 Store->getAlignment());
1296 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1297 Store->getMemOperand()->getPointerInfo(),
1298 Store->isVolatile(), Store->isNonTemporal(),
1299 Store->getAlignment());
1302 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1303 SelectionDAG &DAG) const {
1304 StoreSDNode *Store = cast<StoreSDNode>(Op);
1305 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1306 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1307 EVT PtrVT = Store->getBasePtr().getValueType();
1308 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1311 SmallVector<SDValue, 8> Chains;
1313 unsigned EltSize = MemEltVT.getStoreSize();
1314 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1316 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1317 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1319 DAG.getConstant(i, SL, MVT::i32));
1321 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), SL, PtrVT);
1322 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1324 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1325 SrcValue.getWithOffset(i * EltSize),
1326 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1327 Store->getAlignment());
1328 Chains.push_back(NewStore);
1331 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1334 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1335 SelectionDAG &DAG) const {
1336 StoreSDNode *Store = cast<StoreSDNode>(Op);
1337 SDValue Val = Store->getValue();
1338 EVT VT = Val.getValueType();
1340 // If this is a 2 element vector, we really want to scalarize and not create
1341 // weird 1 element vectors.
1342 if (VT.getVectorNumElements() == 2)
1343 return ScalarizeVectorStore(Op, DAG);
1345 EVT MemVT = Store->getMemoryVT();
1346 SDValue Chain = Store->getChain();
1347 SDValue BasePtr = Store->getBasePtr();
1351 EVT LoMemVT, HiMemVT;
1354 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1355 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1356 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1358 EVT PtrVT = BasePtr.getValueType();
1359 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1360 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1363 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1365 = DAG.getTruncStore(Chain, SL, Lo,
1369 Store->isNonTemporal(),
1370 Store->isVolatile(),
1371 Store->getAlignment());
1373 = DAG.getTruncStore(Chain, SL, Hi,
1375 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1377 Store->isNonTemporal(),
1378 Store->isVolatile(),
1379 Store->getAlignment());
1381 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1385 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1387 LoadSDNode *Load = cast<LoadSDNode>(Op);
1388 ISD::LoadExtType ExtType = Load->getExtensionType();
1389 EVT VT = Op.getValueType();
1390 EVT MemVT = Load->getMemoryVT();
1392 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1393 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1394 // FIXME: Copied from PPC
1395 // First, load into 32 bits, then truncate to 1 bit.
1397 SDValue Chain = Load->getChain();
1398 SDValue BasePtr = Load->getBasePtr();
1399 MachineMemOperand *MMO = Load->getMemOperand();
1401 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1402 BasePtr, MVT::i8, MMO);
1405 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1409 return DAG.getMergeValues(Ops, DL);
1412 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1413 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1414 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1417 // <SI && AS=PRIVATE && EXTLOAD && size < 32bit,
1418 // register (2-)byte extract.
1420 // Get Register holding the target.
1421 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1422 DAG.getConstant(2, DL, MVT::i32));
1423 // Load the Register.
1424 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1425 Load->getChain(), Ptr,
1426 DAG.getTargetConstant(0, DL, MVT::i32),
1429 // Get offset within the register.
1430 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1432 DAG.getConstant(0x3, DL, MVT::i32));
1434 // Bit offset of target byte (byteIdx * 8).
1435 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1436 DAG.getConstant(3, DL, MVT::i32));
1438 // Shift to the right.
1439 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1441 // Eliminate the upper bits by setting them to ...
1442 EVT MemEltVT = MemVT.getScalarType();
1445 if (ExtType == ISD::SEXTLOAD) {
1446 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1449 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1453 return DAG.getMergeValues(Ops, DL);
1458 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1462 return DAG.getMergeValues(Ops, DL);
1465 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1467 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1468 if (Result.getNode()) {
1472 StoreSDNode *Store = cast<StoreSDNode>(Op);
1473 SDValue Chain = Store->getChain();
1474 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1475 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1476 Store->getValue().getValueType().isVector()) {
1477 return ScalarizeVectorStore(Op, DAG);
1480 EVT MemVT = Store->getMemoryVT();
1481 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1482 MemVT.bitsLT(MVT::i32)) {
1484 if (Store->getMemoryVT() == MVT::i8) {
1486 } else if (Store->getMemoryVT() == MVT::i16) {
1489 SDValue BasePtr = Store->getBasePtr();
1490 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1491 DAG.getConstant(2, DL, MVT::i32));
1492 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1494 DAG.getTargetConstant(0, DL, MVT::i32));
1496 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1497 DAG.getConstant(0x3, DL, MVT::i32));
1499 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1500 DAG.getConstant(3, DL, MVT::i32));
1502 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1505 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1507 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1508 MaskedValue, ShiftAmt);
1510 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32,
1511 DAG.getConstant(Mask, DL, MVT::i32),
1513 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1514 DAG.getConstant(0xffffffff, DL, MVT::i32));
1515 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1517 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1518 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1520 DAG.getTargetConstant(0, DL, MVT::i32));
1525 // This is a shortcut for integer division because we have fast i32<->f32
1526 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1527 // float is enough to accurately represent up to a 24-bit integer.
1528 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1530 EVT VT = Op.getValueType();
1531 SDValue LHS = Op.getOperand(0);
1532 SDValue RHS = Op.getOperand(1);
1533 MVT IntVT = MVT::i32;
1534 MVT FltVT = MVT::f32;
1536 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1537 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1539 if (VT.isVector()) {
1540 unsigned NElts = VT.getVectorNumElements();
1541 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1542 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1545 unsigned BitSize = VT.getScalarType().getSizeInBits();
1547 SDValue jq = DAG.getConstant(1, DL, IntVT);
1550 // char|short jq = ia ^ ib;
1551 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1553 // jq = jq >> (bitsize - 2)
1554 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1555 DAG.getConstant(BitSize - 2, DL, VT));
1558 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1561 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1564 // int ia = (int)LHS;
1566 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1568 // int ib, (int)RHS;
1570 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1572 // float fa = (float)ia;
1573 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1575 // float fb = (float)ib;
1576 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1578 // TODO: Should this propagate fast-math-flags?
1579 // float fq = native_divide(fa, fb);
1580 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1581 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1584 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1586 // float fqneg = -fq;
1587 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1589 // float fr = mad(fqneg, fb, fa);
1590 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1591 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1593 // int iq = (int)fq;
1594 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1597 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1600 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1602 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1604 // int cv = fr >= fb;
1605 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1607 // jq = (cv ? jq : 0);
1608 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1610 // dst = trunc/extend to legal type
1611 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1614 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1616 // Rem needs compensation, it's easier to recompute it
1617 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1618 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1624 return DAG.getMergeValues(Res, DL);
1627 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1629 SmallVectorImpl<SDValue> &Results) const {
1630 assert(Op.getValueType() == MVT::i64);
1633 EVT VT = Op.getValueType();
1634 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1636 SDValue one = DAG.getConstant(1, DL, HalfVT);
1637 SDValue zero = DAG.getConstant(0, DL, HalfVT);
1640 SDValue LHS = Op.getOperand(0);
1641 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1642 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1644 SDValue RHS = Op.getOperand(1);
1645 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1646 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1648 if (VT == MVT::i64 &&
1649 DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1650 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1652 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1655 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero);
1656 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero);
1657 Results.push_back(DIV);
1658 Results.push_back(REM);
1662 // Get Speculative values
1663 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1664 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1666 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1667 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero);
1669 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1670 SDValue DIV_Lo = zero;
1672 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1674 for (unsigned i = 0; i < halfBitWidth; ++i) {
1675 const unsigned bitPos = halfBitWidth - i - 1;
1676 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1677 // Get value of high bit
1678 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1679 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1680 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1683 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1685 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1687 SDValue BIT = DAG.getConstant(1 << bitPos, DL, HalfVT);
1688 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1690 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1693 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1694 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1697 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1698 Results.push_back(DIV);
1699 Results.push_back(REM);
1702 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1703 SelectionDAG &DAG) const {
1705 EVT VT = Op.getValueType();
1707 if (VT == MVT::i64) {
1708 SmallVector<SDValue, 2> Results;
1709 LowerUDIVREM64(Op, DAG, Results);
1710 return DAG.getMergeValues(Results, DL);
1713 SDValue Num = Op.getOperand(0);
1714 SDValue Den = Op.getOperand(1);
1716 if (VT == MVT::i32) {
1717 if (DAG.MaskedValueIsZero(Num, APInt::getHighBitsSet(32, 8)) &&
1718 DAG.MaskedValueIsZero(Den, APInt::getHighBitsSet(32, 8))) {
1719 // TODO: We technically could do this for i64, but shouldn't that just be
1720 // handled by something generally reducing 64-bit division on 32-bit
1721 // values to 32-bit?
1722 return LowerDIVREM24(Op, DAG, false);
1726 // RCP = URECIP(Den) = 2^32 / Den + e
1727 // e is rounding error.
1728 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1730 // RCP_LO = mul(RCP, Den) */
1731 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1733 // RCP_HI = mulhu (RCP, Den) */
1734 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1736 // NEG_RCP_LO = -RCP_LO
1737 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1740 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1741 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1744 // Calculate the rounding error from the URECIP instruction
1745 // E = mulhu(ABS_RCP_LO, RCP)
1746 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1748 // RCP_A_E = RCP + E
1749 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1751 // RCP_S_E = RCP - E
1752 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1754 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1755 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1758 // Quotient = mulhu(Tmp0, Num)
1759 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1761 // Num_S_Remainder = Quotient * Den
1762 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1764 // Remainder = Num - Num_S_Remainder
1765 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1767 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1768 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1769 DAG.getConstant(-1, DL, VT),
1770 DAG.getConstant(0, DL, VT),
1772 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1773 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1775 DAG.getConstant(-1, DL, VT),
1776 DAG.getConstant(0, DL, VT),
1778 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1779 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1782 // Calculate Division result:
1784 // Quotient_A_One = Quotient + 1
1785 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1786 DAG.getConstant(1, DL, VT));
1788 // Quotient_S_One = Quotient - 1
1789 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1790 DAG.getConstant(1, DL, VT));
1792 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1793 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1794 Quotient, Quotient_A_One, ISD::SETEQ);
1796 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1797 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1798 Quotient_S_One, Div, ISD::SETEQ);
1800 // Calculate Rem result:
1802 // Remainder_S_Den = Remainder - Den
1803 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1805 // Remainder_A_Den = Remainder + Den
1806 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1808 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1809 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1810 Remainder, Remainder_S_Den, ISD::SETEQ);
1812 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1813 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1814 Remainder_A_Den, Rem, ISD::SETEQ);
1819 return DAG.getMergeValues(Ops, DL);
1822 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1823 SelectionDAG &DAG) const {
1825 EVT VT = Op.getValueType();
1827 SDValue LHS = Op.getOperand(0);
1828 SDValue RHS = Op.getOperand(1);
1830 SDValue Zero = DAG.getConstant(0, DL, VT);
1831 SDValue NegOne = DAG.getConstant(-1, DL, VT);
1833 if (VT == MVT::i32 &&
1834 DAG.ComputeNumSignBits(LHS) > 8 &&
1835 DAG.ComputeNumSignBits(RHS) > 8) {
1836 return LowerDIVREM24(Op, DAG, true);
1838 if (VT == MVT::i64 &&
1839 DAG.ComputeNumSignBits(LHS) > 32 &&
1840 DAG.ComputeNumSignBits(RHS) > 32) {
1841 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1844 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1845 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1846 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1849 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1850 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1852 return DAG.getMergeValues(Res, DL);
1855 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1856 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1857 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1858 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1860 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1861 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1863 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1864 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1866 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1867 SDValue Rem = Div.getValue(1);
1869 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1870 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1872 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1873 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1879 return DAG.getMergeValues(Res, DL);
1882 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1883 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1885 EVT VT = Op.getValueType();
1886 SDValue X = Op.getOperand(0);
1887 SDValue Y = Op.getOperand(1);
1889 // TODO: Should this propagate fast-math-flags?
1891 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1892 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1893 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1895 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1898 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1900 SDValue Src = Op.getOperand(0);
1902 // result = trunc(src)
1903 // if (src > 0.0 && src != result)
1906 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1908 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1909 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1912 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1914 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1915 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1916 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1918 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1919 // TODO: Should this propagate fast-math-flags?
1920 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1923 static SDValue extractF64Exponent(SDValue Hi, SDLoc SL, SelectionDAG &DAG) {
1924 const unsigned FractBits = 52;
1925 const unsigned ExpBits = 11;
1927 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1929 DAG.getConstant(FractBits - 32, SL, MVT::i32),
1930 DAG.getConstant(ExpBits, SL, MVT::i32));
1931 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1932 DAG.getConstant(1023, SL, MVT::i32));
1937 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1939 SDValue Src = Op.getOperand(0);
1941 assert(Op.getValueType() == MVT::f64);
1943 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1944 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1946 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1948 // Extract the upper half, since this is where we will find the sign and
1950 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1952 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1954 const unsigned FractBits = 52;
1956 // Extract the sign bit.
1957 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
1958 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1960 // Extend back to to 64-bits.
1961 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1963 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1965 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1966 const SDValue FractMask
1967 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
1969 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1970 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1971 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1974 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
1976 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
1978 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1979 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1981 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1982 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1984 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1987 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1989 SDValue Src = Op.getOperand(0);
1991 assert(Op.getValueType() == MVT::f64);
1993 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1994 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
1995 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1997 // TODO: Should this propagate fast-math-flags?
1999 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2000 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2002 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2004 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
2005 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2008 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2009 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2011 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2014 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2015 // FNEARBYINT and FRINT are the same, except in their handling of FP
2016 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2017 // rint, so just treat them as equivalent.
2018 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2021 // XXX - May require not supporting f32 denormals?
2022 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
2024 SDValue X = Op.getOperand(0);
2026 SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X);
2028 // TODO: Should this propagate fast-math-flags?
2030 SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T);
2032 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);
2034 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f32);
2035 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
2036 const SDValue Half = DAG.getConstantFP(0.5, SL, MVT::f32);
2038 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);
2041 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
2043 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2045 SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero);
2047 return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel);
2050 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2052 SDValue X = Op.getOperand(0);
2054 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2056 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2057 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2058 const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2059 const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2061 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2063 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2065 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2067 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2069 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
2072 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2073 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2074 DAG.getConstant(INT64_C(0x0008000000000000), SL,
2078 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2079 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2080 DAG.getConstant(0, SL, MVT::i64), Tmp0,
2083 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2084 D, DAG.getConstant(0, SL, MVT::i64));
2085 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2087 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2088 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2090 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2091 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2092 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2094 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2096 DAG.getConstantFP(1.0, SL, MVT::f64),
2097 DAG.getConstantFP(0.0, SL, MVT::f64));
2099 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2101 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2102 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2107 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2108 EVT VT = Op.getValueType();
2111 return LowerFROUND32(Op, DAG);
2114 return LowerFROUND64(Op, DAG);
2116 llvm_unreachable("unhandled type");
2119 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2121 SDValue Src = Op.getOperand(0);
2123 // result = trunc(src);
2124 // if (src < 0.0 && src != result)
2127 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2129 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2130 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2133 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2135 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2136 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2137 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2139 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2140 // TODO: Should this propagate fast-math-flags?
2141 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2144 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2145 bool Signed) const {
2147 SDValue Src = Op.getOperand(0);
2149 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2151 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2152 DAG.getConstant(0, SL, MVT::i32));
2153 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2154 DAG.getConstant(1, SL, MVT::i32));
2156 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2159 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2161 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2162 DAG.getConstant(32, SL, MVT::i32));
2163 // TODO: Should this propagate fast-math-flags?
2164 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2167 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2168 SelectionDAG &DAG) const {
2169 SDValue S0 = Op.getOperand(0);
2170 if (S0.getValueType() != MVT::i64)
2173 EVT DestVT = Op.getValueType();
2174 if (DestVT == MVT::f64)
2175 return LowerINT_TO_FP64(Op, DAG, false);
2177 assert(DestVT == MVT::f32);
2181 // f32 uint_to_fp i64
2182 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2183 DAG.getConstant(0, DL, MVT::i32));
2184 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
2185 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2186 DAG.getConstant(1, DL, MVT::i32));
2187 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
2188 // TODO: Should this propagate fast-math-flags?
2189 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
2190 DAG.getConstantFP(4294967296.0f, DL, MVT::f32)); // 2^32
2191 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
2194 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2195 SelectionDAG &DAG) const {
2196 SDValue Src = Op.getOperand(0);
2197 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
2198 return LowerINT_TO_FP64(Op, DAG, true);
2203 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2204 bool Signed) const {
2207 SDValue Src = Op.getOperand(0);
2209 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2211 SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2213 SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2215 // TODO: Should this propagate fast-math-flags?
2216 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2218 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2221 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2223 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2224 MVT::i32, FloorMul);
2225 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2227 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2229 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2232 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2233 SelectionDAG &DAG) const {
2234 SDValue Src = Op.getOperand(0);
2236 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2237 return LowerFP64_TO_INT(Op, DAG, true);
2242 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2243 SelectionDAG &DAG) const {
2244 SDValue Src = Op.getOperand(0);
2246 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2247 return LowerFP64_TO_INT(Op, DAG, false);
2252 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2253 SelectionDAG &DAG) const {
2254 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2255 MVT VT = Op.getSimpleValueType();
2256 MVT ScalarVT = VT.getScalarType();
2261 SDValue Src = Op.getOperand(0);
2264 // TODO: Don't scalarize on Evergreen?
2265 unsigned NElts = VT.getVectorNumElements();
2266 SmallVector<SDValue, 8> Args;
2267 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2269 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2270 for (unsigned I = 0; I < NElts; ++I)
2271 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2273 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2276 //===----------------------------------------------------------------------===//
2277 // Custom DAG optimizations
2278 //===----------------------------------------------------------------------===//
2280 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2281 APInt KnownZero, KnownOne;
2282 EVT VT = Op.getValueType();
2283 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2285 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2288 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2289 EVT VT = Op.getValueType();
2291 // In order for this to be a signed 24-bit value, bit 23, must
2293 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2294 // as unsigned 24-bit values.
2295 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2298 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2300 SelectionDAG &DAG = DCI.DAG;
2301 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2302 EVT VT = Op.getValueType();
2304 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2305 APInt KnownZero, KnownOne;
2306 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2307 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2308 DCI.CommitTargetLoweringOpt(TLO);
2311 template <typename IntTy>
2312 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2313 uint32_t Offset, uint32_t Width, SDLoc DL) {
2314 if (Width + Offset < 32) {
2315 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2316 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2317 return DAG.getConstant(Result, DL, MVT::i32);
2320 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2323 static bool usesAllNormalStores(SDNode *LoadVal) {
2324 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2325 if (!ISD::isNormalStore(*I))
2332 // If we have a copy of an illegal type, replace it with a load / store of an
2333 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2334 // instructions emitted when handling extloads and truncstores. Ideally we could
2335 // recognize the pack / unpack pattern to eliminate it.
2336 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2337 DAGCombinerInfo &DCI) const {
2338 if (!DCI.isBeforeLegalize())
2341 StoreSDNode *SN = cast<StoreSDNode>(N);
2342 SDValue Value = SN->getValue();
2343 EVT VT = Value.getValueType();
2345 if (isTypeLegal(VT) || SN->isVolatile() ||
2346 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2349 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2350 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2353 EVT MemVT = LoadVal->getMemoryVT();
2356 SelectionDAG &DAG = DCI.DAG;
2357 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2359 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2361 LoadVal->getChain(),
2362 LoadVal->getBasePtr(),
2363 LoadVal->getOffset(),
2365 LoadVal->getMemOperand());
2367 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2368 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2370 return DAG.getStore(SN->getChain(), SL, NewLoad,
2371 SN->getBasePtr(), SN->getMemOperand());
2374 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
2375 DAGCombinerInfo &DCI) const {
2376 if (N->getValueType(0) != MVT::i64)
2379 // i64 (shl x, 32) -> (build_pair 0, x)
2381 // Doing this with moves theoretically helps MI optimizations that understand
2382 // copies. 2 v_mov_b32_e32 will have the same code size / cycle count as
2383 // v_lshl_b64. In the SALU case, I think this is slightly worse since it
2384 // doubles the code size and I'm unsure about cycle count.
2385 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2386 if (!RHS || RHS->getZExtValue() != 32)
2389 SDValue LHS = N->getOperand(0);
2392 SelectionDAG &DAG = DCI.DAG;
2394 // Extract low 32-bits.
2395 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
2397 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2398 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, Zero, Lo);
2401 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2402 DAGCombinerInfo &DCI) const {
2403 EVT VT = N->getValueType(0);
2405 if (VT.isVector() || VT.getSizeInBits() > 32)
2408 SelectionDAG &DAG = DCI.DAG;
2411 SDValue N0 = N->getOperand(0);
2412 SDValue N1 = N->getOperand(1);
2415 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2416 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2417 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2418 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2419 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2420 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2421 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2422 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2427 // We need to use sext even for MUL_U24, because MUL_U24 is used
2428 // for signed multiply of 8 and 16-bit types.
2429 return DAG.getSExtOrTrunc(Mul, DL, VT);
2432 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2433 DAGCombinerInfo &DCI) const {
2434 SelectionDAG &DAG = DCI.DAG;
2437 switch(N->getOpcode()) {
2441 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2444 return performShlCombine(N, DCI);
2447 return performMulCombine(N, DCI);
2448 case AMDGPUISD::MUL_I24:
2449 case AMDGPUISD::MUL_U24: {
2450 SDValue N0 = N->getOperand(0);
2451 SDValue N1 = N->getOperand(1);
2452 simplifyI24(N0, DCI);
2453 simplifyI24(N1, DCI);
2457 SDValue Cond = N->getOperand(0);
2458 if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) {
2459 EVT VT = N->getValueType(0);
2460 SDValue LHS = Cond.getOperand(0);
2461 SDValue RHS = Cond.getOperand(1);
2462 SDValue CC = Cond.getOperand(2);
2464 SDValue True = N->getOperand(1);
2465 SDValue False = N->getOperand(2);
2468 return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
2473 case AMDGPUISD::BFE_I32:
2474 case AMDGPUISD::BFE_U32: {
2475 assert(!N->getValueType(0).isVector() &&
2476 "Vector handling of BFE not implemented");
2477 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2481 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2483 return DAG.getConstant(0, DL, MVT::i32);
2485 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2489 SDValue BitsFrom = N->getOperand(0);
2490 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2492 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2494 if (OffsetVal == 0) {
2495 // This is already sign / zero extended, so try to fold away extra BFEs.
2496 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2498 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2499 if (OpSignBits >= SignBits)
2502 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2504 // This is a sign_extend_inreg. Replace it to take advantage of existing
2505 // DAG Combines. If not eliminated, we will match back to BFE during
2508 // TODO: The sext_inreg of extended types ends, although we can could
2509 // handle them in a single BFE.
2510 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2511 DAG.getValueType(SmallVT));
2514 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2517 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2519 return constantFoldBFE<int32_t>(DAG,
2520 CVal->getSExtValue(),
2526 return constantFoldBFE<uint32_t>(DAG,
2527 CVal->getZExtValue(),
2533 if ((OffsetVal + WidthVal) >= 32) {
2534 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
2535 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2536 BitsFrom, ShiftVal);
2539 if (BitsFrom.hasOneUse()) {
2540 APInt Demanded = APInt::getBitsSet(32,
2542 OffsetVal + WidthVal);
2544 APInt KnownZero, KnownOne;
2545 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2546 !DCI.isBeforeLegalizeOps());
2547 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2548 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2549 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2550 KnownZero, KnownOne, TLO)) {
2551 DCI.CommitTargetLoweringOpt(TLO);
2559 return performStoreCombine(N, DCI);
2564 //===----------------------------------------------------------------------===//
2566 //===----------------------------------------------------------------------===//
2568 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2571 const SmallVectorImpl<ISD::InputArg> &Ins,
2572 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2574 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2575 if (Ins[i].ArgVT == Ins[i].VT) {
2576 OrigIns.push_back(Ins[i]);
2581 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2582 // Vector has been split into scalars.
2583 VT = Ins[i].ArgVT.getVectorElementType();
2584 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2585 Ins[i].ArgVT.getVectorElementType() !=
2586 Ins[i].VT.getVectorElementType()) {
2587 // Vector elements have been promoted
2590 // Vector has been spilt into smaller vectors.
2594 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2595 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2596 OrigIns.push_back(Arg);
2600 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2601 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2602 return CFP->isExactlyValue(1.0);
2604 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2605 return C->isAllOnesValue();
2610 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2611 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2612 return CFP->getValueAPF().isZero();
2614 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2615 return C->isNullValue();
2620 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2621 const TargetRegisterClass *RC,
2622 unsigned Reg, EVT VT) const {
2623 MachineFunction &MF = DAG.getMachineFunction();
2624 MachineRegisterInfo &MRI = MF.getRegInfo();
2625 unsigned VirtualRegister;
2626 if (!MRI.isLiveIn(Reg)) {
2627 VirtualRegister = MRI.createVirtualRegister(RC);
2628 MRI.addLiveIn(Reg, VirtualRegister);
2630 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2632 return DAG.getRegister(VirtualRegister, VT);
2635 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
2636 const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const {
2637 uint64_t ArgOffset = MFI->ABIArgOffset;
2642 return ArgOffset + 4;
2644 llvm_unreachable("unexpected implicit parameter type");
2647 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2649 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2650 switch ((AMDGPUISD::NodeType)Opcode) {
2651 case AMDGPUISD::FIRST_NUMBER: break;
2653 NODE_NAME_CASE(CALL);
2654 NODE_NAME_CASE(UMUL);
2655 NODE_NAME_CASE(RET_FLAG);
2656 NODE_NAME_CASE(BRANCH_COND);
2659 NODE_NAME_CASE(DWORDADDR)
2660 NODE_NAME_CASE(FRACT)
2661 NODE_NAME_CASE(CLAMP)
2662 NODE_NAME_CASE(COS_HW)
2663 NODE_NAME_CASE(SIN_HW)
2664 NODE_NAME_CASE(FMAX_LEGACY)
2665 NODE_NAME_CASE(FMIN_LEGACY)
2666 NODE_NAME_CASE(FMAX3)
2667 NODE_NAME_CASE(SMAX3)
2668 NODE_NAME_CASE(UMAX3)
2669 NODE_NAME_CASE(FMIN3)
2670 NODE_NAME_CASE(SMIN3)
2671 NODE_NAME_CASE(UMIN3)
2672 NODE_NAME_CASE(URECIP)
2673 NODE_NAME_CASE(DIV_SCALE)
2674 NODE_NAME_CASE(DIV_FMAS)
2675 NODE_NAME_CASE(DIV_FIXUP)
2676 NODE_NAME_CASE(TRIG_PREOP)
2679 NODE_NAME_CASE(RSQ_LEGACY)
2680 NODE_NAME_CASE(RSQ_CLAMPED)
2681 NODE_NAME_CASE(LDEXP)
2682 NODE_NAME_CASE(FP_CLASS)
2683 NODE_NAME_CASE(DOT4)
2684 NODE_NAME_CASE(CARRY)
2685 NODE_NAME_CASE(BORROW)
2686 NODE_NAME_CASE(BFE_U32)
2687 NODE_NAME_CASE(BFE_I32)
2690 NODE_NAME_CASE(BREV)
2691 NODE_NAME_CASE(MUL_U24)
2692 NODE_NAME_CASE(MUL_I24)
2693 NODE_NAME_CASE(MAD_U24)
2694 NODE_NAME_CASE(MAD_I24)
2695 NODE_NAME_CASE(TEXTURE_FETCH)
2696 NODE_NAME_CASE(EXPORT)
2697 NODE_NAME_CASE(CONST_ADDRESS)
2698 NODE_NAME_CASE(REGISTER_LOAD)
2699 NODE_NAME_CASE(REGISTER_STORE)
2700 NODE_NAME_CASE(LOAD_CONSTANT)
2701 NODE_NAME_CASE(LOAD_INPUT)
2702 NODE_NAME_CASE(SAMPLE)
2703 NODE_NAME_CASE(SAMPLEB)
2704 NODE_NAME_CASE(SAMPLED)
2705 NODE_NAME_CASE(SAMPLEL)
2706 NODE_NAME_CASE(CVT_F32_UBYTE0)
2707 NODE_NAME_CASE(CVT_F32_UBYTE1)
2708 NODE_NAME_CASE(CVT_F32_UBYTE2)
2709 NODE_NAME_CASE(CVT_F32_UBYTE3)
2710 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2711 NODE_NAME_CASE(CONST_DATA_PTR)
2712 case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
2713 NODE_NAME_CASE(SENDMSG)
2714 NODE_NAME_CASE(INTERP_MOV)
2715 NODE_NAME_CASE(INTERP_P1)
2716 NODE_NAME_CASE(INTERP_P2)
2717 NODE_NAME_CASE(STORE_MSKOR)
2718 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2719 case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
2724 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2725 DAGCombinerInfo &DCI,
2726 unsigned &RefinementSteps,
2727 bool &UseOneConstNR) const {
2728 SelectionDAG &DAG = DCI.DAG;
2729 EVT VT = Operand.getValueType();
2731 if (VT == MVT::f32) {
2732 RefinementSteps = 0;
2733 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2736 // TODO: There is also f64 rsq instruction, but the documentation is less
2737 // clear on its precision.
2742 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2743 DAGCombinerInfo &DCI,
2744 unsigned &RefinementSteps) const {
2745 SelectionDAG &DAG = DCI.DAG;
2746 EVT VT = Operand.getValueType();
2748 if (VT == MVT::f32) {
2749 // Reciprocal, < 1 ulp error.
2751 // This reciprocal approximation converges to < 0.5 ulp error with one
2752 // newton rhapson performed with two fused multiple adds (FMAs).
2754 RefinementSteps = 0;
2755 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2758 // TODO: There is also f64 rcp instruction, but the documentation is less
2759 // clear on its precision.
2764 static void computeKnownBitsForMinMax(const SDValue Op0,
2768 const SelectionDAG &DAG,
2770 APInt Op0Zero, Op0One;
2771 APInt Op1Zero, Op1One;
2772 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2773 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2775 KnownZero = Op0Zero & Op1Zero;
2776 KnownOne = Op0One & Op1One;
2779 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2783 const SelectionDAG &DAG,
2784 unsigned Depth) const {
2786 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2790 unsigned Opc = Op.getOpcode();
2795 case ISD::INTRINSIC_WO_CHAIN: {
2796 // FIXME: The intrinsic should just use the node.
2797 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2798 case AMDGPUIntrinsic::AMDGPU_imax:
2799 case AMDGPUIntrinsic::AMDGPU_umax:
2800 case AMDGPUIntrinsic::AMDGPU_imin:
2801 case AMDGPUIntrinsic::AMDGPU_umin:
2802 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2803 KnownZero, KnownOne, DAG, Depth);
2811 case AMDGPUISD::CARRY:
2812 case AMDGPUISD::BORROW: {
2813 KnownZero = APInt::getHighBitsSet(32, 31);
2817 case AMDGPUISD::BFE_I32:
2818 case AMDGPUISD::BFE_U32: {
2819 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2823 unsigned BitWidth = 32;
2824 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2826 if (Opc == AMDGPUISD::BFE_U32)
2827 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2834 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2836 const SelectionDAG &DAG,
2837 unsigned Depth) const {
2838 switch (Op.getOpcode()) {
2839 case AMDGPUISD::BFE_I32: {
2840 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2844 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2845 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2846 if (!Offset || !Offset->isNullValue())
2849 // TODO: Could probably figure something out with non-0 offsets.
2850 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2851 return std::max(SignBits, Op0SignBits);
2854 case AMDGPUISD::BFE_U32: {
2855 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2856 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
2859 case AMDGPUISD::CARRY:
2860 case AMDGPUISD::BORROW: