lib/Target/AArch64/AArch64InstrNEON.td

   1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the AArch64 NEON instruction set.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // NEON-specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17 def Neon_bsl       : SDNode<"AArch64ISD::NEON_BSL", SDTypeProfile<1, 3,
  18                       [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
  19                       SDTCisSameAs<0, 3>]>>;
  20
  21 // (outs Result), (ins Imm, OpCmode)
  22 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
  23
  24 def Neon_movi     : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
  25
  26 def Neon_mvni     : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
  27
  28 // (outs Result), (ins Imm)
  29 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
  30                         [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
  31
  32 // (outs Result), (ins LHS, RHS, CondCode)
  33 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
  34                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  35
  36 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
  37 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
  38                  [SDTCisVec<0>,  SDTCisVec<1>]>>;
  39
  40 // (outs Result), (ins LHS, RHS)
  41 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
  42                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  43
  44 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  45                                      SDTCisVT<2, i32>]>;
  46 def Neon_sqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
  47 def Neon_uqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
  48
  49 def SDTPERMUTE : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  50                                SDTCisSameAs<0, 2>]>;
  51 def Neon_uzp1    : SDNode<"AArch64ISD::NEON_UZP1", SDTPERMUTE>;
  52 def Neon_uzp2    : SDNode<"AArch64ISD::NEON_UZP2", SDTPERMUTE>;
  53 def Neon_zip1    : SDNode<"AArch64ISD::NEON_ZIP1", SDTPERMUTE>;
  54 def Neon_zip2    : SDNode<"AArch64ISD::NEON_ZIP2", SDTPERMUTE>;
  55 def Neon_trn1    : SDNode<"AArch64ISD::NEON_TRN1", SDTPERMUTE>;
  56 def Neon_trn2    : SDNode<"AArch64ISD::NEON_TRN2", SDTPERMUTE>;
  57
  58 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
  59 def Neon_rev64    : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
  60 def Neon_rev32    : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
  61 def Neon_rev16    : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
  62 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
  63                        [SDTCisVec<0>]>>;
  64 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
  65                            [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
  66 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
  67                            [SDTCisVec<0>,  SDTCisSameAs<0, 1>,
  68                            SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
  69
  70 def SDT_assertext : SDTypeProfile<1, 1,
  71   [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
  72 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
  73 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
  74
  75 //===----------------------------------------------------------------------===//
  76 // Multiclasses
  77 //===----------------------------------------------------------------------===//
  78
  79 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size,  bits<5> opcode,
  80                                 string asmop, SDPatternOperator opnode8B,
  81                                 SDPatternOperator opnode16B,
  82                                 bit Commutable = 0> {
  83   let isCommutable = Commutable in {
  84     def _8B :  NeonI_3VSame<0b0, u, size, opcode,
  85                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
  86                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
  87                [(set (v8i8 VPR64:$Rd),
  88                   (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
  89                NoItinerary>;
  90
  91     def _16B : NeonI_3VSame<0b1, u, size, opcode,
  92                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
  93                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
  94                [(set (v16i8 VPR128:$Rd),
  95                   (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
  96                NoItinerary>;
  97   }
  98
  99 }
 100
 101 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
 102                                   string asmop, SDPatternOperator opnode,
 103                                   bit Commutable = 0> {
 104   let isCommutable = Commutable in {
 105     def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
 106               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 107               asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
 108               [(set (v4i16 VPR64:$Rd),
 109                  (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
 110               NoItinerary>;
 111
 112     def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
 113               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 114               asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
 115               [(set (v8i16 VPR128:$Rd),
 116                  (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
 117               NoItinerary>;
 118
 119     def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
 120               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 121               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 122               [(set (v2i32 VPR64:$Rd),
 123                  (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
 124               NoItinerary>;
 125
 126     def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
 127               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 128               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 129               [(set (v4i32 VPR128:$Rd),
 130                  (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
 131               NoItinerary>;
 132   }
 133 }
 134 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
 135                                   string asmop, SDPatternOperator opnode,
 136                                   bit Commutable = 0>
 137    : NeonI_3VSame_HS_sizes<u, opcode,  asmop, opnode, Commutable> {
 138   let isCommutable = Commutable in {
 139     def _8B :  NeonI_3VSame<0b0, u, 0b00, opcode,
 140                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 141                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
 142                [(set (v8i8 VPR64:$Rd),
 143                   (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
 144                NoItinerary>;
 145
 146     def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
 147                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 148                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
 149                [(set (v16i8 VPR128:$Rd),
 150                   (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
 151                NoItinerary>;
 152   }
 153 }
 154
 155 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
 156                                    string asmop, SDPatternOperator opnode,
 157                                    bit Commutable = 0>
 158    : NeonI_3VSame_BHS_sizes<u, opcode,  asmop, opnode, Commutable> {
 159   let isCommutable = Commutable in {
 160     def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
 161               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 162               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 163               [(set (v2i64 VPR128:$Rd),
 164                  (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
 165               NoItinerary>;
 166   }
 167 }
 168
 169 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
 170 // but Result types can be integer or floating point types.
 171 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
 172                                  string asmop, SDPatternOperator opnode2S,
 173                                  SDPatternOperator opnode4S,
 174                                  SDPatternOperator opnode2D,
 175                                  ValueType ResTy2S, ValueType ResTy4S,
 176                                  ValueType ResTy2D, bit Commutable = 0> {
 177   let isCommutable = Commutable in {
 178     def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
 179               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 180               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 181               [(set (ResTy2S VPR64:$Rd),
 182                  (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
 183               NoItinerary>;
 184
 185     def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
 186               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 187               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 188               [(set (ResTy4S VPR128:$Rd),
 189                  (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
 190               NoItinerary>;
 191
 192     def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
 193               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 194               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 195               [(set (ResTy2D VPR128:$Rd),
 196                  (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
 197                NoItinerary>;
 198   }
 199 }
 200
 201 //===----------------------------------------------------------------------===//
 202 // Instruction Definitions
 203 //===----------------------------------------------------------------------===//
 204
 205 // Vector Arithmetic Instructions
 206
 207 // Vector Add (Integer and Floating-Point)
 208
 209 defm ADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
 210 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
 211                                      v2f32, v4f32, v2f64, 1>;
 212
 213 // Vector Sub (Integer and Floating-Point)
 214
 215 defm SUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
 216 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
 217                                      v2f32, v4f32, v2f64, 0>;
 218
 219 // Vector Multiply (Integer and Floating-Point)
 220
 221 defm MULvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
 222 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
 223                                      v2f32, v4f32, v2f64, 1>;
 224
 225 // Vector Multiply (Polynomial)
 226
 227 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
 228                                     int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
 229
 230 // Vector Multiply-accumulate and Multiply-subtract (Integer)
 231
 232 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
 233 // two operands constraints.
 234 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
 235   RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
 236   bits<5> opcode, SDPatternOperator opnode>
 237   : NeonI_3VSame<q, u, size, opcode,
 238     (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
 239     asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
 240     [(set (OpTy VPRC:$Rd),
 241        (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
 242     NoItinerary> {
 243   let Constraints = "$src = $Rd";
 244 }
 245
 246 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 247                        (add node:$Ra, (mul node:$Rn, node:$Rm))>;
 248
 249 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 250                        (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
 251
 252
 253 def MLAvvv_8B:  NeonI_3VSame_Constraint_impl<"mla", ".8b",  VPR64,  v8i8,
 254                                              0b0, 0b0, 0b00, 0b10010, Neon_mla>;
 255 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
 256                                              0b1, 0b0, 0b00, 0b10010, Neon_mla>;
 257 def MLAvvv_4H:  NeonI_3VSame_Constraint_impl<"mla", ".4h",  VPR64,  v4i16,
 258                                              0b0, 0b0, 0b01, 0b10010, Neon_mla>;
 259 def MLAvvv_8H:  NeonI_3VSame_Constraint_impl<"mla", ".8h",  VPR128, v8i16,
 260                                              0b1, 0b0, 0b01, 0b10010, Neon_mla>;
 261 def MLAvvv_2S:  NeonI_3VSame_Constraint_impl<"mla", ".2s",  VPR64,  v2i32,
 262                                              0b0, 0b0, 0b10, 0b10010, Neon_mla>;
 263 def MLAvvv_4S:  NeonI_3VSame_Constraint_impl<"mla", ".4s",  VPR128, v4i32,
 264                                              0b1, 0b0, 0b10, 0b10010, Neon_mla>;
 265
 266 def MLSvvv_8B:  NeonI_3VSame_Constraint_impl<"mls", ".8b",  VPR64,  v8i8,
 267                                              0b0, 0b1, 0b00, 0b10010, Neon_mls>;
 268 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
 269                                              0b1, 0b1, 0b00, 0b10010, Neon_mls>;
 270 def MLSvvv_4H:  NeonI_3VSame_Constraint_impl<"mls", ".4h",  VPR64,  v4i16,
 271                                              0b0, 0b1, 0b01, 0b10010, Neon_mls>;
 272 def MLSvvv_8H:  NeonI_3VSame_Constraint_impl<"mls", ".8h",  VPR128, v8i16,
 273                                              0b1, 0b1, 0b01, 0b10010, Neon_mls>;
 274 def MLSvvv_2S:  NeonI_3VSame_Constraint_impl<"mls", ".2s",  VPR64,  v2i32,
 275                                              0b0, 0b1, 0b10, 0b10010, Neon_mls>;
 276 def MLSvvv_4S:  NeonI_3VSame_Constraint_impl<"mls", ".4s",  VPR128, v4i32,
 277                                              0b1, 0b1, 0b10, 0b10010, Neon_mls>;
 278
 279 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
 280
 281 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 282                         (fadd node:$Ra, (fmul node:$Rn, node:$Rm))>;
 283
 284 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 285                         (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
 286
 287 let Predicates = [HasNEON, UseFusedMAC] in {
 288 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s",  VPR64,  v2f32,
 289                                              0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
 290 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s",  VPR128, v4f32,
 291                                              0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
 292 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d",  VPR128, v2f64,
 293                                              0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
 294
 295 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s",  VPR64,  v2f32,
 296                                               0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
 297 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s",  VPR128, v4f32,
 298                                              0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
 299 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d",  VPR128, v2f64,
 300                                              0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
 301 }
 302
 303 // We're also allowed to match the fma instruction regardless of compile
 304 // options.
 305 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
 306           (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 307 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 308           (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 309 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 310           (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 311
 312 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
 313           (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 314 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 315           (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 316 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 317           (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 318
 319 // Vector Divide (Floating-Point)
 320
 321 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
 322                                      v2f32, v4f32, v2f64, 0>;
 323
 324 // Vector Bitwise Operations
 325
 326 // Vector Bitwise AND
 327
 328 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
 329
 330 // Vector Bitwise Exclusive OR
 331
 332 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
 333
 334 // Vector Bitwise OR
 335
 336 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
 337
 338 // ORR disassembled as MOV if Vn==Vm
 339
 340 // Vector Move - register
 341 // Alias for ORR if Vn=Vm.
 342 // FIXME: This is actually the preferred syntax but TableGen can't deal with
 343 // custom printing of aliases.
 344 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
 345                     (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
 346 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
 347                     (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
 348
 349 // The MOVI instruction takes two immediate operands.  The first is the
 350 // immediate encoding, while the second is the cmode.  A cmode of 14, or
 351 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
 352 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
 353 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
 354
 355 def Neon_not8B  : PatFrag<(ops node:$in),
 356                           (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
 357 def Neon_not16B : PatFrag<(ops node:$in),
 358                           (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
 359
 360 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
 361                          (or node:$Rn, (Neon_not8B node:$Rm))>;
 362
 363 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
 364                           (or node:$Rn, (Neon_not16B node:$Rm))>;
 365
 366 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
 367                          (and node:$Rn, (Neon_not8B node:$Rm))>;
 368
 369 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
 370                           (and node:$Rn, (Neon_not16B node:$Rm))>;
 371
 372
 373 // Vector Bitwise OR NOT - register
 374
 375 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
 376                                    Neon_orn8B, Neon_orn16B, 0>;
 377
 378 // Vector Bitwise Bit Clear (AND NOT) - register
 379
 380 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
 381                                    Neon_bic8B, Neon_bic16B, 0>;
 382
 383 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
 384                                    SDPatternOperator opnode16B,
 385                                    Instruction INST8B,
 386                                    Instruction INST16B> {
 387   def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 388             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 389   def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 390             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 391   def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 392             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 393   def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 394             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 395   def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 396             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 397   def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 398             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 399 }
 400
 401 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
 402 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
 403 defm : Neon_bitwise2V_patterns<or,  or,  ORRvvv_8B, ORRvvv_16B>;
 404 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
 405 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
 406 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
 407
 408 //   Vector Bitwise Select
 409 def BSLvvv_8B  : NeonI_3VSame_Constraint_impl<"bsl", ".8b",  VPR64, v8i8,
 410                                               0b0, 0b1, 0b01, 0b00011, Neon_bsl>;
 411
 412 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
 413                                               0b1, 0b1, 0b01, 0b00011, Neon_bsl>;
 414
 415 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
 416                                    Instruction INST8B,
 417                                    Instruction INST16B> {
 418   // Disassociate type from instruction definition
 419   def : Pat<(v2i32 (opnode VPR64:$src,VPR64:$Rn, VPR64:$Rm)),
 420             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 421   def : Pat<(v4i16 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
 422             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 423   def : Pat<(v1i64 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
 424             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 425   def : Pat<(v4i32 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 426             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 427   def : Pat<(v8i16 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 428             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 429   def : Pat<(v2i64 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 430             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 431
 432   // Allow to match BSL instruction pattern with non-constant operand
 433   def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
 434                     (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 435           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 436   def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
 437                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 438           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 439   def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
 440                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 441           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 442   def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
 443                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 444           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 445   def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
 446                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 447           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 448   def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
 449                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 450           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 451   def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
 452                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 453           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 454   def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
 455                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 456           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 457
 458   // Allow to match llvm.arm.* intrinsics.
 459   def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
 460                     (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
 461             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 462   def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
 463                     (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
 464             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 465   def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
 466                     (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
 467             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 468   def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
 469                     (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
 470             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 471   def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
 472                     (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
 473             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 474   def : Pat<(v1f64 (int_arm_neon_vbsl (v1f64 VPR64:$src),
 475                     (v1f64 VPR64:$Rn), (v1f64 VPR64:$Rm))),
 476             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 477   def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
 478                     (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
 479             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 480   def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
 481                     (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
 482             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 483   def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
 484                     (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
 485             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 486   def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
 487                     (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
 488             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 489   def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
 490                     (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
 491             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 492   def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
 493                     (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
 494             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 495 }
 496
 497 // Additional patterns for bitwise instruction BSL
 498 defm: Neon_bitwise3V_patterns<Neon_bsl, BSLvvv_8B, BSLvvv_16B>;
 499
 500 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
 501                            (Neon_bsl node:$src, node:$Rn, node:$Rm),
 502                            [{ (void)N; return false; }]>;
 503
 504 // Vector Bitwise Insert if True
 505
 506 def BITvvv_8B  : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64,   v8i8,
 507                    0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 508 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
 509                    0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 510
 511 // Vector Bitwise Insert if False
 512
 513 def BIFvvv_8B  : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64,  v8i8,
 514                                 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 515 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
 516                                 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 517
 518 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
 519
 520 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 521                        (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
 522 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 523                        (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
 524
 525 // Vector Absolute Difference and Accumulate (Unsigned)
 526 def UABAvvv_8B :  NeonI_3VSame_Constraint_impl<"uaba", ".8b",  VPR64,  v8i8,
 527                     0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
 528 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
 529                     0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
 530 def UABAvvv_4H :  NeonI_3VSame_Constraint_impl<"uaba", ".4h",  VPR64,  v4i16,
 531                     0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
 532 def UABAvvv_8H :  NeonI_3VSame_Constraint_impl<"uaba", ".8h",  VPR128, v8i16,
 533                     0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
 534 def UABAvvv_2S :  NeonI_3VSame_Constraint_impl<"uaba", ".2s",  VPR64,  v2i32,
 535                     0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
 536 def UABAvvv_4S :  NeonI_3VSame_Constraint_impl<"uaba", ".4s",  VPR128, v4i32,
 537                     0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
 538
 539 // Vector Absolute Difference and Accumulate (Signed)
 540 def SABAvvv_8B :  NeonI_3VSame_Constraint_impl<"saba", ".8b",  VPR64,  v8i8,
 541                     0b0, 0b0, 0b00, 0b01111, Neon_saba>;
 542 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
 543                     0b1, 0b0, 0b00, 0b01111, Neon_saba>;
 544 def SABAvvv_4H :  NeonI_3VSame_Constraint_impl<"saba", ".4h",  VPR64,  v4i16,
 545                     0b0, 0b0, 0b01, 0b01111, Neon_saba>;
 546 def SABAvvv_8H :  NeonI_3VSame_Constraint_impl<"saba", ".8h",  VPR128, v8i16,
 547                     0b1, 0b0, 0b01, 0b01111, Neon_saba>;
 548 def SABAvvv_2S :  NeonI_3VSame_Constraint_impl<"saba", ".2s",  VPR64,  v2i32,
 549                     0b0, 0b0, 0b10, 0b01111, Neon_saba>;
 550 def SABAvvv_4S :  NeonI_3VSame_Constraint_impl<"saba", ".4s",  VPR128, v4i32,
 551                     0b1, 0b0, 0b10, 0b01111, Neon_saba>;
 552
 553
 554 // Vector Absolute Difference (Signed, Unsigned)
 555 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
 556 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
 557
 558 // Vector Absolute Difference (Floating Point)
 559 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
 560                                     int_arm_neon_vabds, int_arm_neon_vabds,
 561                                     int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
 562
 563 // Vector Reciprocal Step (Floating Point)
 564 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
 565                                        int_arm_neon_vrecps, int_arm_neon_vrecps,
 566                                        int_arm_neon_vrecps,
 567                                        v2f32, v4f32, v2f64, 0>;
 568
 569 // Vector Reciprocal Square Root Step (Floating Point)
 570 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
 571                                         int_arm_neon_vrsqrts,
 572                                         int_arm_neon_vrsqrts,
 573                                         int_arm_neon_vrsqrts,
 574                                         v2f32, v4f32, v2f64, 0>;
 575
 576 // Vector Comparisons
 577
 578 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
 579                         (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
 580 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
 581                          (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
 582 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
 583                         (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
 584 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
 585                         (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
 586 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
 587                         (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
 588
 589 // NeonI_compare_aliases class: swaps register operands to implement
 590 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
 591 class NeonI_compare_aliases<string asmop, string asmlane,
 592                             Instruction inst, RegisterOperand VPRC>
 593   : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
 594                     ", $Rm" # asmlane,
 595                   (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
 596
 597 // Vector Comparisons (Integer)
 598
 599 // Vector Compare Mask Equal (Integer)
 600 let isCommutable =1 in {
 601 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
 602 }
 603
 604 // Vector Compare Mask Higher or Same (Unsigned Integer)
 605 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
 606
 607 // Vector Compare Mask Greater Than or Equal (Integer)
 608 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
 609
 610 // Vector Compare Mask Higher (Unsigned Integer)
 611 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
 612
 613 // Vector Compare Mask Greater Than (Integer)
 614 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
 615
 616 // Vector Compare Mask Bitwise Test (Integer)
 617 defm CMTSTvvv:  NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
 618
 619 // Vector Compare Mask Less or Same (Unsigned Integer)
 620 // CMLS is alias for CMHS with operands reversed.
 621 def CMLSvvv_8B  : NeonI_compare_aliases<"cmls", ".8b",  CMHSvvv_8B,  VPR64>;
 622 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
 623 def CMLSvvv_4H  : NeonI_compare_aliases<"cmls", ".4h",  CMHSvvv_4H,  VPR64>;
 624 def CMLSvvv_8H  : NeonI_compare_aliases<"cmls", ".8h",  CMHSvvv_8H,  VPR128>;
 625 def CMLSvvv_2S  : NeonI_compare_aliases<"cmls", ".2s",  CMHSvvv_2S,  VPR64>;
 626 def CMLSvvv_4S  : NeonI_compare_aliases<"cmls", ".4s",  CMHSvvv_4S,  VPR128>;
 627 def CMLSvvv_2D  : NeonI_compare_aliases<"cmls", ".2d",  CMHSvvv_2D,  VPR128>;
 628
 629 // Vector Compare Mask Less Than or Equal (Integer)
 630 // CMLE is alias for CMGE with operands reversed.
 631 def CMLEvvv_8B  : NeonI_compare_aliases<"cmle", ".8b",  CMGEvvv_8B,  VPR64>;
 632 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
 633 def CMLEvvv_4H  : NeonI_compare_aliases<"cmle", ".4h",  CMGEvvv_4H,  VPR64>;
 634 def CMLEvvv_8H  : NeonI_compare_aliases<"cmle", ".8h",  CMGEvvv_8H,  VPR128>;
 635 def CMLEvvv_2S  : NeonI_compare_aliases<"cmle", ".2s",  CMGEvvv_2S,  VPR64>;
 636 def CMLEvvv_4S  : NeonI_compare_aliases<"cmle", ".4s",  CMGEvvv_4S,  VPR128>;
 637 def CMLEvvv_2D  : NeonI_compare_aliases<"cmle", ".2d",  CMGEvvv_2D,  VPR128>;
 638
 639 // Vector Compare Mask Lower (Unsigned Integer)
 640 // CMLO is alias for CMHI with operands reversed.
 641 def CMLOvvv_8B  : NeonI_compare_aliases<"cmlo", ".8b",  CMHIvvv_8B,  VPR64>;
 642 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
 643 def CMLOvvv_4H  : NeonI_compare_aliases<"cmlo", ".4h",  CMHIvvv_4H,  VPR64>;
 644 def CMLOvvv_8H  : NeonI_compare_aliases<"cmlo", ".8h",  CMHIvvv_8H,  VPR128>;
 645 def CMLOvvv_2S  : NeonI_compare_aliases<"cmlo", ".2s",  CMHIvvv_2S,  VPR64>;
 646 def CMLOvvv_4S  : NeonI_compare_aliases<"cmlo", ".4s",  CMHIvvv_4S,  VPR128>;
 647 def CMLOvvv_2D  : NeonI_compare_aliases<"cmlo", ".2d",  CMHIvvv_2D,  VPR128>;
 648
 649 // Vector Compare Mask Less Than (Integer)
 650 // CMLT is alias for CMGT with operands reversed.
 651 def CMLTvvv_8B  : NeonI_compare_aliases<"cmlt", ".8b",  CMGTvvv_8B,  VPR64>;
 652 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
 653 def CMLTvvv_4H  : NeonI_compare_aliases<"cmlt", ".4h",  CMGTvvv_4H,  VPR64>;
 654 def CMLTvvv_8H  : NeonI_compare_aliases<"cmlt", ".8h",  CMGTvvv_8H,  VPR128>;
 655 def CMLTvvv_2S  : NeonI_compare_aliases<"cmlt", ".2s",  CMGTvvv_2S,  VPR64>;
 656 def CMLTvvv_4S  : NeonI_compare_aliases<"cmlt", ".4s",  CMGTvvv_4S,  VPR128>;
 657 def CMLTvvv_2D  : NeonI_compare_aliases<"cmlt", ".2d",  CMGTvvv_2D,  VPR128>;
 658
 659
 660 def neon_uimm0_asmoperand : AsmOperandClass
 661 {
 662   let Name = "UImm0";
 663   let PredicateMethod = "isUImm<0>";
 664   let RenderMethod = "addImmOperands";
 665 }
 666
 667 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
 668   let ParserMatchClass = neon_uimm0_asmoperand;
 669   let PrintMethod = "printNeonUImm0Operand";
 670
 671 }
 672
 673 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
 674 {
 675   def _8B :  NeonI_2VMisc<0b0, u, 0b00, opcode,
 676              (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 677              asmop # "\t$Rd.8b, $Rn.8b, $Imm",
 678              [(set (v8i8 VPR64:$Rd),
 679                 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 680              NoItinerary>;
 681
 682   def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
 683              (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 684              asmop # "\t$Rd.16b, $Rn.16b, $Imm",
 685              [(set (v16i8 VPR128:$Rd),
 686                 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 687              NoItinerary>;
 688
 689   def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
 690             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 691             asmop # "\t$Rd.4h, $Rn.4h, $Imm",
 692             [(set (v4i16 VPR64:$Rd),
 693                (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 694             NoItinerary>;
 695
 696   def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
 697             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 698             asmop # "\t$Rd.8h, $Rn.8h, $Imm",
 699             [(set (v8i16 VPR128:$Rd),
 700                (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 701             NoItinerary>;
 702
 703   def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
 704             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 705             asmop # "\t$Rd.2s, $Rn.2s, $Imm",
 706             [(set (v2i32 VPR64:$Rd),
 707                (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 708             NoItinerary>;
 709
 710   def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
 711             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 712             asmop # "\t$Rd.4s, $Rn.4s, $Imm",
 713             [(set (v4i32 VPR128:$Rd),
 714                (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 715             NoItinerary>;
 716
 717   def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
 718             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 719             asmop # "\t$Rd.2d, $Rn.2d, $Imm",
 720             [(set (v2i64 VPR128:$Rd),
 721                (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 722             NoItinerary>;
 723 }
 724
 725 // Vector Compare Mask Equal to Zero (Integer)
 726 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
 727
 728 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
 729 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
 730
 731 // Vector Compare Mask Greater Than Zero (Signed Integer)
 732 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
 733
 734 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
 735 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
 736
 737 // Vector Compare Mask Less Than Zero (Signed Integer)
 738 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
 739
 740 // Vector Comparisons (Floating Point)
 741
 742 // Vector Compare Mask Equal (Floating Point)
 743 let isCommutable =1 in {
 744 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
 745                                       Neon_cmeq, Neon_cmeq,
 746                                       v2i32, v4i32, v2i64, 0>;
 747 }
 748
 749 // Vector Compare Mask Greater Than Or Equal (Floating Point)
 750 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
 751                                       Neon_cmge, Neon_cmge,
 752                                       v2i32, v4i32, v2i64, 0>;
 753
 754 // Vector Compare Mask Greater Than (Floating Point)
 755 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
 756                                       Neon_cmgt, Neon_cmgt,
 757                                       v2i32, v4i32, v2i64, 0>;
 758
 759 // Vector Compare Mask Less Than Or Equal (Floating Point)
 760 // FCMLE is alias for FCMGE with operands reversed.
 761 def FCMLEvvv_2S  : NeonI_compare_aliases<"fcmle", ".2s",  FCMGEvvv_2S,  VPR64>;
 762 def FCMLEvvv_4S  : NeonI_compare_aliases<"fcmle", ".4s",  FCMGEvvv_4S,  VPR128>;
 763 def FCMLEvvv_2D  : NeonI_compare_aliases<"fcmle", ".2d",  FCMGEvvv_2D,  VPR128>;
 764
 765 // Vector Compare Mask Less Than (Floating Point)
 766 // FCMLT is alias for FCMGT with operands reversed.
 767 def FCMLTvvv_2S  : NeonI_compare_aliases<"fcmlt", ".2s",  FCMGTvvv_2S,  VPR64>;
 768 def FCMLTvvv_4S  : NeonI_compare_aliases<"fcmlt", ".4s",  FCMGTvvv_4S,  VPR128>;
 769 def FCMLTvvv_2D  : NeonI_compare_aliases<"fcmlt", ".2d",  FCMGTvvv_2D,  VPR128>;
 770
 771
 772 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
 773                               string asmop, CondCode CC>
 774 {
 775   def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
 776             (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
 777             asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
 778             [(set (v2i32 VPR64:$Rd),
 779                (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpz32:$FPImm), CC)))],
 780             NoItinerary>;
 781
 782   def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
 783             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 784             asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
 785             [(set (v4i32 VPR128:$Rd),
 786                (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpz32:$FPImm), CC)))],
 787             NoItinerary>;
 788
 789   def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
 790             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 791             asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
 792             [(set (v2i64 VPR128:$Rd),
 793                (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpz32:$FPImm), CC)))],
 794             NoItinerary>;
 795 }
 796
 797 // Vector Compare Mask Equal to Zero (Floating Point)
 798 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
 799
 800 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
 801 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
 802
 803 // Vector Compare Mask Greater Than Zero (Floating Point)
 804 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
 805
 806 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
 807 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
 808
 809 // Vector Compare Mask Less Than Zero (Floating Point)
 810 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
 811
 812 // Vector Absolute Comparisons (Floating Point)
 813
 814 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
 815 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
 816                                       int_arm_neon_vacged, int_arm_neon_vacgeq,
 817                                       int_aarch64_neon_vacgeq,
 818                                       v2i32, v4i32, v2i64, 0>;
 819
 820 // Vector Absolute Compare Mask Greater Than (Floating Point)
 821 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
 822                                       int_arm_neon_vacgtd, int_arm_neon_vacgtq,
 823                                       int_aarch64_neon_vacgtq,
 824                                       v2i32, v4i32, v2i64, 0>;
 825
 826 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
 827 // FACLE is alias for FACGE with operands reversed.
 828 def FACLEvvv_2S  : NeonI_compare_aliases<"facle", ".2s",  FACGEvvv_2S,  VPR64>;
 829 def FACLEvvv_4S  : NeonI_compare_aliases<"facle", ".4s",  FACGEvvv_4S,  VPR128>;
 830 def FACLEvvv_2D  : NeonI_compare_aliases<"facle", ".2d",  FACGEvvv_2D,  VPR128>;
 831
 832 // Vector Absolute Compare Mask Less Than (Floating Point)
 833 // FACLT is alias for FACGT with operands reversed.
 834 def FACLTvvv_2S  : NeonI_compare_aliases<"faclt", ".2s",  FACGTvvv_2S,  VPR64>;
 835 def FACLTvvv_4S  : NeonI_compare_aliases<"faclt", ".4s",  FACGTvvv_4S,  VPR128>;
 836 def FACLTvvv_2D  : NeonI_compare_aliases<"faclt", ".2d",  FACGTvvv_2D,  VPR128>;
 837
 838 // Vector halving add (Integer Signed, Unsigned)
 839 defm SHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
 840                                         int_arm_neon_vhadds, 1>;
 841 defm UHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
 842                                         int_arm_neon_vhaddu, 1>;
 843
 844 // Vector halving sub (Integer Signed, Unsigned)
 845 defm SHSUBvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
 846                                         int_arm_neon_vhsubs, 0>;
 847 defm UHSUBvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
 848                                         int_arm_neon_vhsubu, 0>;
 849
 850 // Vector rouding halving add (Integer Signed, Unsigned)
 851 defm SRHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
 852                                          int_arm_neon_vrhadds, 1>;
 853 defm URHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
 854                                          int_arm_neon_vrhaddu, 1>;
 855
 856 // Vector Saturating add (Integer Signed, Unsigned)
 857 defm SQADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
 858                    int_arm_neon_vqadds, 1>;
 859 defm UQADDvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
 860                    int_arm_neon_vqaddu, 1>;
 861
 862 // Vector Saturating sub (Integer Signed, Unsigned)
 863 defm SQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
 864                    int_arm_neon_vqsubs, 1>;
 865 defm UQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
 866                    int_arm_neon_vqsubu, 1>;
 867
 868 // Vector Shift Left (Signed and Unsigned Integer)
 869 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
 870                  int_arm_neon_vshifts, 1>;
 871 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
 872                  int_arm_neon_vshiftu, 1>;
 873
 874 // Vector Saturating Shift Left (Signed and Unsigned Integer)
 875 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
 876                   int_arm_neon_vqshifts, 1>;
 877 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
 878                   int_arm_neon_vqshiftu, 1>;
 879
 880 // Vector Rouding Shift Left (Signed and Unsigned Integer)
 881 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
 882                   int_arm_neon_vrshifts, 1>;
 883 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
 884                   int_arm_neon_vrshiftu, 1>;
 885
 886 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
 887 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
 888                    int_arm_neon_vqrshifts, 1>;
 889 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
 890                    int_arm_neon_vqrshiftu, 1>;
 891
 892 // Vector Maximum (Signed and Unsigned Integer)
 893 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
 894 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
 895
 896 // Vector Minimum (Signed and Unsigned Integer)
 897 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
 898 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
 899
 900 // Vector Maximum (Floating Point)
 901 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
 902                                      int_arm_neon_vmaxs, int_arm_neon_vmaxs,
 903                                      int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
 904
 905 // Vector Minimum (Floating Point)
 906 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
 907                                      int_arm_neon_vmins, int_arm_neon_vmins,
 908                                      int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
 909
 910 // Vector maxNum (Floating Point) -  prefer a number over a quiet NaN)
 911 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
 912                                        int_aarch64_neon_vmaxnm,
 913                                        int_aarch64_neon_vmaxnm,
 914                                        int_aarch64_neon_vmaxnm,
 915                                        v2f32, v4f32, v2f64, 1>;
 916
 917 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
 918 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
 919                                        int_aarch64_neon_vminnm,
 920                                        int_aarch64_neon_vminnm,
 921                                        int_aarch64_neon_vminnm,
 922                                        v2f32, v4f32, v2f64, 1>;
 923
 924 // Vector Maximum Pairwise (Signed and Unsigned Integer)
 925 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
 926 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
 927
 928 // Vector Minimum Pairwise (Signed and Unsigned Integer)
 929 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
 930 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
 931
 932 // Vector Maximum Pairwise (Floating Point)
 933 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
 934                                      int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
 935                                      int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
 936
 937 // Vector Minimum Pairwise (Floating Point)
 938 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
 939                                      int_arm_neon_vpmins, int_arm_neon_vpmins,
 940                                      int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
 941
 942 // Vector maxNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 943 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
 944                                        int_aarch64_neon_vpmaxnm,
 945                                        int_aarch64_neon_vpmaxnm,
 946                                        int_aarch64_neon_vpmaxnm,
 947                                        v2f32, v4f32, v2f64, 1>;
 948
 949 // Vector minNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 950 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
 951                                        int_aarch64_neon_vpminnm,
 952                                        int_aarch64_neon_vpminnm,
 953                                        int_aarch64_neon_vpminnm,
 954                                        v2f32, v4f32, v2f64, 1>;
 955
 956 // Vector Addition Pairwise (Integer)
 957 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
 958
 959 // Vector Addition Pairwise (Floating Point)
 960 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
 961                                        int_arm_neon_vpadd,
 962                                        int_arm_neon_vpadd,
 963                                        int_arm_neon_vpadd,
 964                                        v2f32, v4f32, v2f64, 1>;
 965
 966 // Vector Saturating Doubling Multiply High
 967 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
 968                     int_arm_neon_vqdmulh, 1>;
 969
 970 // Vector Saturating Rouding Doubling Multiply High
 971 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
 972                      int_arm_neon_vqrdmulh, 1>;
 973
 974 // Vector Multiply Extended (Floating Point)
 975 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
 976                                       int_aarch64_neon_vmulx,
 977                                       int_aarch64_neon_vmulx,
 978                                       int_aarch64_neon_vmulx,
 979                                       v2f32, v4f32, v2f64, 1>;
 980
 981 // Patterns to match llvm.aarch64.* intrinsic for
 982 // ADDP, SMINP, UMINP, SMAXP, UMAXP having i32 as output
 983 class Neon_VectorPair_v2i32_pattern<SDPatternOperator opnode, Instruction INST>
 984   : Pat<(v1i32 (opnode (v2i32 VPR64:$Rn))),
 985         (EXTRACT_SUBREG
 986              (v2i32 (INST (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rn))),
 987              sub_32)>;
 988
 989 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_sminv, SMINPvvv_2S>;
 990 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_uminv, UMINPvvv_2S>;
 991 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_smaxv, SMAXPvvv_2S>;
 992 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_umaxv, UMAXPvvv_2S>;
 993 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_vaddv, ADDP_2S>;
 994
 995 // Vector Immediate Instructions
 996
 997 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
 998 {
 999   def _asmoperand : AsmOperandClass
1000     {
1001       let Name = "NeonMovImmShift" # PREFIX;
1002       let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
1003       let PredicateMethod = "isNeonMovImmShift" # PREFIX;
1004     }
1005 }
1006
1007 // Definition of vector immediates shift operands
1008
1009 // The selectable use-cases extract the shift operation
1010 // information from the OpCmode fields encoded in the immediate.
1011 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
1012   uint64_t OpCmode = N->getZExtValue();
1013   unsigned ShiftImm;
1014   unsigned ShiftOnesIn;
1015   unsigned HasShift =
1016     A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1017   if (!HasShift) return SDValue();
1018   return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
1019 }]>;
1020
1021 // Vector immediates shift operands which accept LSL and MSL
1022 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1023 // or 0, 8 (LSLH) or 8, 16 (MSL).
1024 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1025 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1026 // LSLH restricts shift amount to  0, 8 out of 0, 8, 16, 24
1027 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1028
1029 multiclass neon_mov_imm_shift_operands<string PREFIX,
1030                                        string HALF, string ISHALF, code pred>
1031 {
1032    def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1033     {
1034       let PrintMethod =
1035         "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1036       let DecoderMethod =
1037         "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1038       let ParserMatchClass =
1039         !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1040     }
1041 }
1042
1043 defm neon_mov_imm_LSL  : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1044   unsigned ShiftImm;
1045   unsigned ShiftOnesIn;
1046   unsigned HasShift =
1047     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1048   return (HasShift && !ShiftOnesIn);
1049 }]>;
1050
1051 defm neon_mov_imm_MSL  : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1052   unsigned ShiftImm;
1053   unsigned ShiftOnesIn;
1054   unsigned HasShift =
1055     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1056   return (HasShift && ShiftOnesIn);
1057 }]>;
1058
1059 defm neon_mov_imm_LSLH  : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1060   unsigned ShiftImm;
1061   unsigned ShiftOnesIn;
1062   unsigned HasShift =
1063     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1064   return (HasShift && !ShiftOnesIn);
1065 }]>;
1066
1067 def neon_uimm1_asmoperand : AsmOperandClass
1068 {
1069   let Name = "UImm1";
1070   let PredicateMethod = "isUImm<1>";
1071   let RenderMethod = "addImmOperands";
1072 }
1073
1074 def neon_uimm2_asmoperand : AsmOperandClass
1075 {
1076   let Name = "UImm2";
1077   let PredicateMethod = "isUImm<2>";
1078   let RenderMethod = "addImmOperands";
1079 }
1080
1081 def neon_uimm8_asmoperand : AsmOperandClass
1082 {
1083   let Name = "UImm8";
1084   let PredicateMethod = "isUImm<8>";
1085   let RenderMethod = "addImmOperands";
1086 }
1087
1088 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1089   let ParserMatchClass = neon_uimm8_asmoperand;
1090   let PrintMethod = "printUImmHexOperand";
1091 }
1092
1093 def neon_uimm64_mask_asmoperand : AsmOperandClass
1094 {
1095   let Name = "NeonUImm64Mask";
1096   let PredicateMethod = "isNeonUImm64Mask";
1097   let RenderMethod = "addNeonUImm64MaskOperands";
1098 }
1099
1100 // MCOperand for 64-bit bytemask with each byte having only the
1101 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1102 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1103   let ParserMatchClass = neon_uimm64_mask_asmoperand;
1104   let PrintMethod = "printNeonUImm64MaskOperand";
1105 }
1106
1107 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1108                                    SDPatternOperator opnode>
1109 {
1110     // shift zeros, per word
1111     def _2S  : NeonI_1VModImm<0b0, op,
1112                               (outs VPR64:$Rd),
1113                               (ins neon_uimm8:$Imm,
1114                                 neon_mov_imm_LSL_operand:$Simm),
1115                               !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1116                               [(set (v2i32 VPR64:$Rd),
1117                                  (v2i32 (opnode (timm:$Imm),
1118                                    (neon_mov_imm_LSL_operand:$Simm))))],
1119                               NoItinerary> {
1120        bits<2> Simm;
1121        let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1122      }
1123
1124     def _4S  : NeonI_1VModImm<0b1, op,
1125                               (outs VPR128:$Rd),
1126                               (ins neon_uimm8:$Imm,
1127                                 neon_mov_imm_LSL_operand:$Simm),
1128                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1129                               [(set (v4i32 VPR128:$Rd),
1130                                  (v4i32 (opnode (timm:$Imm),
1131                                    (neon_mov_imm_LSL_operand:$Simm))))],
1132                               NoItinerary> {
1133       bits<2> Simm;
1134       let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1135     }
1136
1137     // shift zeros, per halfword
1138     def _4H  : NeonI_1VModImm<0b0, op,
1139                               (outs VPR64:$Rd),
1140                               (ins neon_uimm8:$Imm,
1141                                 neon_mov_imm_LSLH_operand:$Simm),
1142                               !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1143                               [(set (v4i16 VPR64:$Rd),
1144                                  (v4i16 (opnode (timm:$Imm),
1145                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1146                               NoItinerary> {
1147       bit  Simm;
1148       let cmode = {0b1, 0b0, Simm, 0b0};
1149     }
1150
1151     def _8H  : NeonI_1VModImm<0b1, op,
1152                               (outs VPR128:$Rd),
1153                               (ins neon_uimm8:$Imm,
1154                                 neon_mov_imm_LSLH_operand:$Simm),
1155                               !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1156                               [(set (v8i16 VPR128:$Rd),
1157                                  (v8i16 (opnode (timm:$Imm),
1158                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1159                               NoItinerary> {
1160       bit Simm;
1161       let cmode = {0b1, 0b0, Simm, 0b0};
1162      }
1163 }
1164
1165 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1166                                                    SDPatternOperator opnode,
1167                                                    SDPatternOperator neonopnode>
1168 {
1169   let Constraints = "$src = $Rd" in {
1170     // shift zeros, per word
1171     def _2S  : NeonI_1VModImm<0b0, op,
1172                  (outs VPR64:$Rd),
1173                  (ins VPR64:$src, neon_uimm8:$Imm,
1174                    neon_mov_imm_LSL_operand:$Simm),
1175                  !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1176                  [(set (v2i32 VPR64:$Rd),
1177                     (v2i32 (opnode (v2i32 VPR64:$src),
1178                       (v2i32 (bitconvert (v2i32 (neonopnode timm:$Imm,
1179                         neon_mov_imm_LSL_operand:$Simm)))))))],
1180                  NoItinerary> {
1181       bits<2> Simm;
1182       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1183     }
1184
1185     def _4S  : NeonI_1VModImm<0b1, op,
1186                  (outs VPR128:$Rd),
1187                  (ins VPR128:$src, neon_uimm8:$Imm,
1188                    neon_mov_imm_LSL_operand:$Simm),
1189                  !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1190                  [(set (v4i32 VPR128:$Rd),
1191                     (v4i32 (opnode (v4i32 VPR128:$src),
1192                       (v4i32 (bitconvert (v4i32 (neonopnode timm:$Imm,
1193                         neon_mov_imm_LSL_operand:$Simm)))))))],
1194                  NoItinerary> {
1195       bits<2> Simm;
1196       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1197     }
1198
1199     // shift zeros, per halfword
1200     def _4H  : NeonI_1VModImm<0b0, op,
1201                  (outs VPR64:$Rd),
1202                  (ins VPR64:$src, neon_uimm8:$Imm,
1203                    neon_mov_imm_LSLH_operand:$Simm),
1204                  !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1205                  [(set (v4i16 VPR64:$Rd),
1206                     (v4i16 (opnode (v4i16 VPR64:$src),
1207                        (v4i16 (bitconvert (v4i16 (neonopnode timm:$Imm,
1208                           neon_mov_imm_LSL_operand:$Simm)))))))],
1209                  NoItinerary> {
1210       bit  Simm;
1211       let cmode = {0b1, 0b0, Simm, 0b1};
1212     }
1213
1214     def _8H  : NeonI_1VModImm<0b1, op,
1215                  (outs VPR128:$Rd),
1216                  (ins VPR128:$src, neon_uimm8:$Imm,
1217                    neon_mov_imm_LSLH_operand:$Simm),
1218                  !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1219                  [(set (v8i16 VPR128:$Rd),
1220                     (v8i16 (opnode (v8i16 VPR128:$src),
1221                       (v8i16 (bitconvert (v8i16 (neonopnode timm:$Imm,
1222                         neon_mov_imm_LSL_operand:$Simm)))))))],
1223                  NoItinerary> {
1224       bit Simm;
1225       let cmode = {0b1, 0b0, Simm, 0b1};
1226     }
1227   }
1228 }
1229
1230 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1231                                    SDPatternOperator opnode>
1232 {
1233     // shift ones, per word
1234     def _2S  : NeonI_1VModImm<0b0, op,
1235                              (outs VPR64:$Rd),
1236                              (ins neon_uimm8:$Imm,
1237                                neon_mov_imm_MSL_operand:$Simm),
1238                              !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1239                               [(set (v2i32 VPR64:$Rd),
1240                                  (v2i32 (opnode (timm:$Imm),
1241                                    (neon_mov_imm_MSL_operand:$Simm))))],
1242                              NoItinerary> {
1243        bit Simm;
1244        let cmode = {0b1, 0b1, 0b0, Simm};
1245      }
1246
1247    def _4S  : NeonI_1VModImm<0b1, op,
1248                               (outs VPR128:$Rd),
1249                               (ins neon_uimm8:$Imm,
1250                                 neon_mov_imm_MSL_operand:$Simm),
1251                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1252                               [(set (v4i32 VPR128:$Rd),
1253                                  (v4i32 (opnode (timm:$Imm),
1254                                    (neon_mov_imm_MSL_operand:$Simm))))],
1255                               NoItinerary> {
1256      bit Simm;
1257      let cmode = {0b1, 0b1, 0b0, Simm};
1258    }
1259 }
1260
1261 // Vector Move Immediate Shifted
1262 let isReMaterializable = 1 in {
1263 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1264 }
1265
1266 // Vector Move Inverted Immediate Shifted
1267 let isReMaterializable = 1 in {
1268 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1269 }
1270
1271 // Vector Bitwise Bit Clear (AND NOT) - immediate
1272 let isReMaterializable = 1 in {
1273 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1274                                                          and, Neon_mvni>;
1275 }
1276
1277 // Vector Bitwise OR - immedidate
1278
1279 let isReMaterializable = 1 in {
1280 defm ORRvi_lsl   : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1281                                                            or, Neon_movi>;
1282 }
1283
1284 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1285 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1286 // BIC immediate instructions selection requires additional patterns to
1287 // transform Neon_movi operands into BIC immediate operands
1288
1289 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1290   uint64_t OpCmode = N->getZExtValue();
1291   unsigned ShiftImm;
1292   unsigned ShiftOnesIn;
1293   (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1294   // LSLH restricts shift amount to  0, 8 which are encoded as 0 and 1
1295   // Transform encoded shift amount 0 to 1 and 1 to 0.
1296   return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1297 }]>;
1298
1299 def neon_mov_imm_LSLH_transform_operand
1300   : ImmLeaf<i32, [{
1301     unsigned ShiftImm;
1302     unsigned ShiftOnesIn;
1303     unsigned HasShift =
1304       A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1305     return (HasShift && !ShiftOnesIn); }],
1306   neon_mov_imm_LSLH_transform_XFORM>;
1307
1308 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0x00, LSL 8)
1309 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0x00)
1310 def : Pat<(v4i16 (and VPR64:$src,
1311             (v4i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1312           (BICvi_lsl_4H VPR64:$src, 0,
1313             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1314
1315 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0x00, LSL 8)
1316 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0x00)
1317 def : Pat<(v8i16 (and VPR128:$src,
1318             (v8i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1319           (BICvi_lsl_8H VPR128:$src, 0,
1320             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1321
1322
1323 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1324                                    SDPatternOperator neonopnode,
1325                                    Instruction INST4H,
1326                                    Instruction INST8H> {
1327   def : Pat<(v8i8 (opnode VPR64:$src,
1328                     (bitconvert(v4i16 (neonopnode timm:$Imm,
1329                       neon_mov_imm_LSLH_operand:$Simm))))),
1330             (INST4H VPR64:$src, neon_uimm8:$Imm,
1331               neon_mov_imm_LSLH_operand:$Simm)>;
1332   def : Pat<(v1i64 (opnode VPR64:$src,
1333                   (bitconvert(v4i16 (neonopnode timm:$Imm,
1334                     neon_mov_imm_LSLH_operand:$Simm))))),
1335           (INST4H VPR64:$src, neon_uimm8:$Imm,
1336             neon_mov_imm_LSLH_operand:$Simm)>;
1337
1338   def : Pat<(v16i8 (opnode VPR128:$src,
1339                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1340                      neon_mov_imm_LSLH_operand:$Simm))))),
1341           (INST8H VPR128:$src, neon_uimm8:$Imm,
1342             neon_mov_imm_LSLH_operand:$Simm)>;
1343   def : Pat<(v4i32 (opnode VPR128:$src,
1344                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1345                      neon_mov_imm_LSLH_operand:$Simm))))),
1346           (INST8H VPR128:$src, neon_uimm8:$Imm,
1347             neon_mov_imm_LSLH_operand:$Simm)>;
1348   def : Pat<(v2i64 (opnode VPR128:$src,
1349                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1350                      neon_mov_imm_LSLH_operand:$Simm))))),
1351           (INST8H VPR128:$src, neon_uimm8:$Imm,
1352             neon_mov_imm_LSLH_operand:$Simm)>;
1353 }
1354
1355 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1356 defm : Neon_bitwiseVi_patterns<or, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H>;
1357
1358 // Additional patterns for Vector Bitwise OR - immedidate
1359 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H>;
1360
1361
1362 // Vector Move Immediate Masked
1363 let isReMaterializable = 1 in {
1364 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1365 }
1366
1367 // Vector Move Inverted Immediate Masked
1368 let isReMaterializable = 1 in {
1369 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1370 }
1371
1372 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1373                                 Instruction inst, RegisterOperand VPRC>
1374   : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1375                         (inst VPRC:$Rd, neon_uimm8:$Imm,  0), 0b0>;
1376
1377 // Aliases for Vector Move Immediate Shifted
1378 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1379 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1380 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1381 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1382
1383 // Aliases for Vector Move Inverted Immediate Shifted
1384 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1385 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1386 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1387 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1388
1389 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1390 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1391 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1392 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1393 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1394
1395 // Aliases for Vector Bitwise OR - immedidate
1396 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1397 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1398 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1399 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1400
1401 //  Vector Move Immediate - per byte
1402 let isReMaterializable = 1 in {
1403 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1404                                (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1405                                "movi\t$Rd.8b, $Imm",
1406                                [(set (v8i8 VPR64:$Rd),
1407                                   (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1408                                 NoItinerary> {
1409   let cmode = 0b1110;
1410 }
1411
1412 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1413                                 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1414                                 "movi\t$Rd.16b, $Imm",
1415                                 [(set (v16i8 VPR128:$Rd),
1416                                    (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1417                                  NoItinerary> {
1418   let cmode = 0b1110;
1419 }
1420 }
1421
1422 // Vector Move Immediate - bytemask, per double word
1423 let isReMaterializable = 1 in {
1424 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1425                                (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1426                                "movi\t $Rd.2d, $Imm",
1427                                [(set (v2i64 VPR128:$Rd),
1428                                   (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1429                                NoItinerary> {
1430   let cmode = 0b1110;
1431 }
1432 }
1433
1434 // Vector Move Immediate - bytemask, one doubleword
1435
1436 let isReMaterializable = 1 in {
1437 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1438                            (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1439                            "movi\t $Rd, $Imm",
1440                            [(set (v1i64 FPR64:$Rd),
1441                              (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1442                            NoItinerary> {
1443   let cmode = 0b1110;
1444 }
1445 }
1446
1447 // Vector Floating Point Move Immediate
1448
1449 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1450                       Operand immOpType, bit q, bit op>
1451   : NeonI_1VModImm<q, op,
1452                    (outs VPRC:$Rd), (ins immOpType:$Imm),
1453                    "fmov\t$Rd" # asmlane # ", $Imm",
1454                    [(set (OpTy VPRC:$Rd),
1455                       (OpTy (Neon_fmovi (timm:$Imm))))],
1456                    NoItinerary> {
1457      let cmode = 0b1111;
1458    }
1459
1460 let isReMaterializable = 1 in {
1461 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64,  v2f32, fmov32_operand, 0b0, 0b0>;
1462 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1463 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1464 }
1465
1466 // Vector Shift (Immediate)
1467 // Immediate in [0, 63]
1468 def imm0_63 : Operand<i32> {
1469   let ParserMatchClass = uimm6_asmoperand;
1470 }
1471
1472 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1473 // as follows:
1474 //
1475 //    Offset    Encoding
1476 //     8        immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1477 //     16       immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1478 //     32       immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1479 //     64       immh:immb<6>   = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1480 //
1481 // The shift right immediate amount, in the range 1 to element bits, is computed
1482 // as Offset - UInt(immh:immb).  The shift left immediate amount, in the range 0
1483 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1484
1485 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1486   let Name = "ShrImm" # OFFSET;
1487   let RenderMethod = "addImmOperands";
1488   let DiagnosticType = "ShrImm" # OFFSET;
1489 }
1490
1491 class shr_imm<string OFFSET> : Operand<i32> {
1492   let EncoderMethod = "getShiftRightImm" # OFFSET;
1493   let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1494   let ParserMatchClass =
1495     !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1496 }
1497
1498 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1499 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1500 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1501 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1502
1503 def shr_imm8 : shr_imm<"8">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 8;}]>;
1504 def shr_imm16 : shr_imm<"16">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 16;}]>;
1505 def shr_imm32 : shr_imm<"32">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 32;}]>;
1506 def shr_imm64 : shr_imm<"64">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 64;}]>;
1507
1508 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1509   let Name = "ShlImm" # OFFSET;
1510   let RenderMethod = "addImmOperands";
1511   let DiagnosticType = "ShlImm" # OFFSET;
1512 }
1513
1514 class shl_imm<string OFFSET> : Operand<i32> {
1515   let EncoderMethod = "getShiftLeftImm" # OFFSET;
1516   let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1517   let ParserMatchClass =
1518     !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1519 }
1520
1521 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1522 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1523 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1524 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1525
1526 def shl_imm8 : shl_imm<"8">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 8;}]>;
1527 def shl_imm16 : shl_imm<"16">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 16;}]>;
1528 def shl_imm32 : shl_imm<"32">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 32;}]>;
1529 def shl_imm64 : shl_imm<"64">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 64;}]>;
1530
1531 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1532                RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1533   : NeonI_2VShiftImm<q, u, opcode,
1534                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1535                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1536                      [(set (Ty VPRC:$Rd),
1537                         (Ty (OpNode (Ty VPRC:$Rn),
1538                           (Ty (Neon_vdup (i32 ImmTy:$Imm))))))],
1539                      NoItinerary>;
1540
1541 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1542   // 64-bit vector types.
1543   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8, shl> {
1544     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1545   }
1546
1547   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16, shl> {
1548     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1549   }
1550
1551   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32, shl> {
1552     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1553   }
1554
1555   // 128-bit vector types.
1556   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8, shl> {
1557     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1558   }
1559
1560   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16, shl> {
1561     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1562   }
1563
1564   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32, shl> {
1565     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1566   }
1567
1568   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64, shl> {
1569     let Inst{22} = 0b1;        // immh:immb = 1xxxxxx
1570   }
1571 }
1572
1573 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1574   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1575                      OpNode> {
1576     let Inst{22-19} = 0b0001;
1577   }
1578
1579   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1580                      OpNode> {
1581     let Inst{22-20} = 0b001;
1582   }
1583
1584   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1585                      OpNode> {
1586      let Inst{22-21} = 0b01;
1587   }
1588
1589   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1590                       OpNode> {
1591                       let Inst{22-19} = 0b0001;
1592                     }
1593
1594   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1595                      OpNode> {
1596                      let Inst{22-20} = 0b001;
1597                     }
1598
1599   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1600                      OpNode> {
1601                       let Inst{22-21} = 0b01;
1602                     }
1603
1604   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1605                      OpNode> {
1606                       let Inst{22} = 0b1;
1607                     }
1608 }
1609
1610 // Shift left
1611 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1612
1613 // Shift right
1614 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1615 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1616
1617 def Neon_High16B : PatFrag<(ops node:$in),
1618                            (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1619 def Neon_High8H  : PatFrag<(ops node:$in),
1620                            (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1621 def Neon_High4S  : PatFrag<(ops node:$in),
1622                            (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1623 def Neon_High2D  : PatFrag<(ops node:$in),
1624                            (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1625 def Neon_High4float : PatFrag<(ops node:$in),
1626                                (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1627 def Neon_High2double : PatFrag<(ops node:$in),
1628                                (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1629
1630 def Neon_Low16B : PatFrag<(ops node:$in),
1631                           (v8i8 (extract_subvector (v16i8 node:$in),
1632                                                    (iPTR 0)))>;
1633 def Neon_Low8H : PatFrag<(ops node:$in),
1634                          (v4i16 (extract_subvector (v8i16 node:$in),
1635                                                    (iPTR 0)))>;
1636 def Neon_Low4S : PatFrag<(ops node:$in),
1637                          (v2i32 (extract_subvector (v4i32 node:$in),
1638                                                    (iPTR 0)))>;
1639 def Neon_Low2D : PatFrag<(ops node:$in),
1640                          (v1i64 (extract_subvector (v2i64 node:$in),
1641                                                    (iPTR 0)))>;
1642 def Neon_Low4float : PatFrag<(ops node:$in),
1643                              (v2f32 (extract_subvector (v4f32 node:$in),
1644                                                        (iPTR 0)))>;
1645 def Neon_Low2double : PatFrag<(ops node:$in),
1646                               (v1f64 (extract_subvector (v2f64 node:$in),
1647                                                         (iPTR 0)))>;
1648
1649 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1650                    string SrcT, ValueType DestTy, ValueType SrcTy,
1651                    Operand ImmTy, SDPatternOperator ExtOp>
1652   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1653                      (ins VPR64:$Rn, ImmTy:$Imm),
1654                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1655                      [(set (DestTy VPR128:$Rd),
1656                         (DestTy (shl
1657                           (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1658                             (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1659                      NoItinerary>;
1660
1661 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1662                        string SrcT, ValueType DestTy, ValueType SrcTy,
1663                        int StartIndex, Operand ImmTy,
1664                        SDPatternOperator ExtOp, PatFrag getTop>
1665   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1666                      (ins VPR128:$Rn, ImmTy:$Imm),
1667                      asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1668                      [(set (DestTy VPR128:$Rd),
1669                         (DestTy (shl
1670                           (DestTy (ExtOp
1671                             (SrcTy (getTop VPR128:$Rn)))),
1672                               (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1673                      NoItinerary>;
1674
1675 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1676                          SDNode ExtOp> {
1677   // 64-bit vector types.
1678   def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1679                          shl_imm8, ExtOp> {
1680     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1681   }
1682
1683   def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1684                          shl_imm16, ExtOp> {
1685     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1686   }
1687
1688   def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1689                          shl_imm32, ExtOp> {
1690     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1691   }
1692
1693   // 128-bit vector types
1694   def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1695                               8, shl_imm8, ExtOp, Neon_High16B> {
1696     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1697   }
1698
1699   def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1700                              4, shl_imm16, ExtOp, Neon_High8H> {
1701     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1702   }
1703
1704   def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1705                              2, shl_imm32, ExtOp, Neon_High4S> {
1706     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1707   }
1708
1709   // Use other patterns to match when the immediate is 0.
1710   def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1711             (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1712
1713   def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1714             (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1715
1716   def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1717             (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1718
1719   def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1720             (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1721
1722   def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1723             (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1724
1725   def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1726             (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1727 }
1728
1729 // Shift left long
1730 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1731 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1732
1733 // Rounding/Saturating shift
1734 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1735                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1736                   SDPatternOperator OpNode>
1737   : NeonI_2VShiftImm<q, u, opcode,
1738                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1739                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1740                      [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1741                         (i32 ImmTy:$Imm))))],
1742                      NoItinerary>;
1743
1744 // shift right (vector by immediate)
1745 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1746                            SDPatternOperator OpNode> {
1747   def _8B  : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1748                          OpNode> {
1749     let Inst{22-19} = 0b0001;
1750   }
1751
1752   def _4H  : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1753                          OpNode> {
1754     let Inst{22-20} = 0b001;
1755   }
1756
1757   def _2S  : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1758                          OpNode> {
1759     let Inst{22-21} = 0b01;
1760   }
1761
1762   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1763                          OpNode> {
1764     let Inst{22-19} = 0b0001;
1765   }
1766
1767   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1768                         OpNode> {
1769     let Inst{22-20} = 0b001;
1770   }
1771
1772   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1773                         OpNode> {
1774     let Inst{22-21} = 0b01;
1775   }
1776
1777   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1778                         OpNode> {
1779     let Inst{22} = 0b1;
1780   }
1781 }
1782
1783 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1784                           SDPatternOperator OpNode> {
1785   // 64-bit vector types.
1786   def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1787                         OpNode> {
1788     let Inst{22-19} = 0b0001;
1789   }
1790
1791   def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1792                         OpNode> {
1793     let Inst{22-20} = 0b001;
1794   }
1795
1796   def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1797                         OpNode> {
1798     let Inst{22-21} = 0b01;
1799   }
1800
1801   // 128-bit vector types.
1802   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1803                          OpNode> {
1804     let Inst{22-19} = 0b0001;
1805   }
1806
1807   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1808                         OpNode> {
1809     let Inst{22-20} = 0b001;
1810   }
1811
1812   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1813                         OpNode> {
1814     let Inst{22-21} = 0b01;
1815   }
1816
1817   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1818                         OpNode> {
1819     let Inst{22} = 0b1;
1820   }
1821 }
1822
1823 // Rounding shift right
1824 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1825                                 int_aarch64_neon_vsrshr>;
1826 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1827                                 int_aarch64_neon_vurshr>;
1828
1829 // Saturating shift left unsigned
1830 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1831
1832 // Saturating shift left
1833 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1834 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1835
1836 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1837                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1838                   SDNode OpNode>
1839   : NeonI_2VShiftImm<q, u, opcode,
1840            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1841            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1842            [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1843               (Ty (OpNode (Ty VPRC:$Rn),
1844                 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))))],
1845            NoItinerary> {
1846   let Constraints = "$src = $Rd";
1847 }
1848
1849 // Shift Right accumulate
1850 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1851   def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1852                         OpNode> {
1853     let Inst{22-19} = 0b0001;
1854   }
1855
1856   def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1857                         OpNode> {
1858     let Inst{22-20} = 0b001;
1859   }
1860
1861   def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1862                         OpNode> {
1863     let Inst{22-21} = 0b01;
1864   }
1865
1866   def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1867                          OpNode> {
1868     let Inst{22-19} = 0b0001;
1869   }
1870
1871   def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1872                         OpNode> {
1873     let Inst{22-20} = 0b001;
1874   }
1875
1876   def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1877                         OpNode> {
1878     let Inst{22-21} = 0b01;
1879   }
1880
1881   def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1882                         OpNode> {
1883     let Inst{22} = 0b1;
1884   }
1885 }
1886
1887 // Shift right and accumulate
1888 defm SSRAvvi    : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
1889 defm USRAvvi    : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
1890
1891 // Rounding shift accumulate
1892 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
1893                     RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1894                     SDPatternOperator OpNode>
1895   : NeonI_2VShiftImm<q, u, opcode,
1896                      (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1897                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1898                      [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1899                         (Ty (OpNode (Ty VPRC:$Rn), (i32 ImmTy:$Imm))))))],
1900                      NoItinerary> {
1901   let Constraints = "$src = $Rd";
1902 }
1903
1904 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
1905                              SDPatternOperator OpNode> {
1906   def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1907                           OpNode> {
1908     let Inst{22-19} = 0b0001;
1909   }
1910
1911   def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1912                           OpNode> {
1913     let Inst{22-20} = 0b001;
1914   }
1915
1916   def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1917                           OpNode> {
1918     let Inst{22-21} = 0b01;
1919   }
1920
1921   def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1922                            OpNode> {
1923     let Inst{22-19} = 0b0001;
1924   }
1925
1926   def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1927                           OpNode> {
1928     let Inst{22-20} = 0b001;
1929   }
1930
1931   def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1932                           OpNode> {
1933     let Inst{22-21} = 0b01;
1934   }
1935
1936   def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1937                           OpNode> {
1938     let Inst{22} = 0b1;
1939   }
1940 }
1941
1942 // Rounding shift right and accumulate
1943 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
1944 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
1945
1946 // Shift insert by immediate
1947 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
1948                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1949                   SDPatternOperator OpNode>
1950     : NeonI_2VShiftImm<q, u, opcode,
1951            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1952            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1953            [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
1954              (i32 ImmTy:$Imm))))],
1955            NoItinerary> {
1956   let Constraints = "$src = $Rd";
1957 }
1958
1959 // shift left insert (vector by immediate)
1960 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
1961   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1962                         int_aarch64_neon_vsli> {
1963     let Inst{22-19} = 0b0001;
1964   }
1965
1966   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1967                         int_aarch64_neon_vsli> {
1968     let Inst{22-20} = 0b001;
1969   }
1970
1971   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1972                         int_aarch64_neon_vsli> {
1973     let Inst{22-21} = 0b01;
1974   }
1975
1976     // 128-bit vector types
1977   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1978                          int_aarch64_neon_vsli> {
1979     let Inst{22-19} = 0b0001;
1980   }
1981
1982   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1983                         int_aarch64_neon_vsli> {
1984     let Inst{22-20} = 0b001;
1985   }
1986
1987   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1988                         int_aarch64_neon_vsli> {
1989     let Inst{22-21} = 0b01;
1990   }
1991
1992   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1993                         int_aarch64_neon_vsli> {
1994     let Inst{22} = 0b1;
1995   }
1996 }
1997
1998 // shift right insert (vector by immediate)
1999 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
2000     // 64-bit vector types.
2001   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2002                         int_aarch64_neon_vsri> {
2003     let Inst{22-19} = 0b0001;
2004   }
2005
2006   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2007                         int_aarch64_neon_vsri> {
2008     let Inst{22-20} = 0b001;
2009   }
2010
2011   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2012                         int_aarch64_neon_vsri> {
2013     let Inst{22-21} = 0b01;
2014   }
2015
2016     // 128-bit vector types
2017   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2018                          int_aarch64_neon_vsri> {
2019     let Inst{22-19} = 0b0001;
2020   }
2021
2022   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2023                         int_aarch64_neon_vsri> {
2024     let Inst{22-20} = 0b001;
2025   }
2026
2027   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2028                         int_aarch64_neon_vsri> {
2029     let Inst{22-21} = 0b01;
2030   }
2031
2032   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2033                         int_aarch64_neon_vsri> {
2034     let Inst{22} = 0b1;
2035   }
2036 }
2037
2038 // Shift left and insert
2039 defm SLIvvi   : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2040
2041 // Shift right and insert
2042 defm SRIvvi   : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2043
2044 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2045                     string SrcT, Operand ImmTy>
2046   : NeonI_2VShiftImm<q, u, opcode,
2047                      (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2048                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2049                      [], NoItinerary>;
2050
2051 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2052                        string SrcT, Operand ImmTy>
2053   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2054                      (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2055                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2056                      [], NoItinerary> {
2057   let Constraints = "$src = $Rd";
2058 }
2059
2060 // left long shift by immediate
2061 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2062   def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2063     let Inst{22-19} = 0b0001;
2064   }
2065
2066   def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2067     let Inst{22-20} = 0b001;
2068   }
2069
2070   def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2071     let Inst{22-21} = 0b01;
2072   }
2073
2074   // Shift Narrow High
2075   def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2076                               shr_imm8> {
2077     let Inst{22-19} = 0b0001;
2078   }
2079
2080   def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2081                              shr_imm16> {
2082     let Inst{22-20} = 0b001;
2083   }
2084
2085   def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2086                              shr_imm32> {
2087     let Inst{22-21} = 0b01;
2088   }
2089 }
2090
2091 // Shift right narrow
2092 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2093
2094 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2095 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2096 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2097 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2098 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2099 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2100 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2101 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2102
2103 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2104                               (v2i64 (concat_vectors (v1i64 node:$Rm),
2105                                                      (v1i64 node:$Rn)))>;
2106 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2107                               (v8i16 (concat_vectors (v4i16 node:$Rm),
2108                                                      (v4i16 node:$Rn)))>;
2109 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2110                               (v4i32 (concat_vectors (v2i32 node:$Rm),
2111                                                      (v2i32 node:$Rn)))>;
2112 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2113                               (v4f32 (concat_vectors (v2f32 node:$Rm),
2114                                                      (v2f32 node:$Rn)))>;
2115 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2116                               (v2f64 (concat_vectors (v1f64 node:$Rm),
2117                                                      (v1f64 node:$Rn)))>;
2118
2119 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2120                              (v8i16 (srl (v8i16 node:$lhs),
2121                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2122 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2123                              (v4i32 (srl (v4i32 node:$lhs),
2124                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2125 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2126                              (v2i64 (srl (v2i64 node:$lhs),
2127                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2128 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2129                              (v8i16 (sra (v8i16 node:$lhs),
2130                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2131 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2132                              (v4i32 (sra (v4i32 node:$lhs),
2133                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2134 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2135                              (v2i64 (sra (v2i64 node:$lhs),
2136                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2137
2138 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2139 multiclass Neon_shiftNarrow_patterns<string shr> {
2140   def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2141               (i32 shr_imm8:$Imm)))),
2142             (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2143   def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2144               (i32 shr_imm16:$Imm)))),
2145             (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2146   def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2147               (i32 shr_imm32:$Imm)))),
2148             (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2149
2150   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2151               (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2152                 VPR128:$Rn, (i32 shr_imm8:$Imm))))))),
2153             (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2154                          VPR128:$Rn, imm:$Imm)>;
2155   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2156               (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2157                 VPR128:$Rn, (i32 shr_imm16:$Imm))))))),
2158             (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2159                         VPR128:$Rn, imm:$Imm)>;
2160   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2161               (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2162                 VPR128:$Rn, (i32 shr_imm32:$Imm))))))),
2163             (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2164                         VPR128:$Rn, imm:$Imm)>;
2165 }
2166
2167 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2168   def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm)),
2169             (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2170   def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm)),
2171             (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2172   def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm)),
2173             (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2174
2175   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2176                 (v1i64 (bitconvert (v8i8
2177                     (op (v8i16 VPR128:$Rn), shr_imm8:$Imm))))),
2178             (!cast<Instruction>(prefix # "_16B")
2179                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2180                 VPR128:$Rn, imm:$Imm)>;
2181   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2182                 (v1i64 (bitconvert (v4i16
2183                     (op (v4i32 VPR128:$Rn), shr_imm16:$Imm))))),
2184             (!cast<Instruction>(prefix # "_8H")
2185                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2186                 VPR128:$Rn, imm:$Imm)>;
2187   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2188                 (v1i64 (bitconvert (v2i32
2189                     (op (v2i64 VPR128:$Rn), shr_imm32:$Imm))))),
2190             (!cast<Instruction>(prefix # "_4S")
2191                   (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2192                   VPR128:$Rn, imm:$Imm)>;
2193 }
2194
2195 defm : Neon_shiftNarrow_patterns<"lshr">;
2196 defm : Neon_shiftNarrow_patterns<"ashr">;
2197
2198 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2199 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2200 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2201 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2202 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2203 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2204 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2205
2206 // Convert fix-point and float-pointing
2207 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2208                 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2209                 Operand ImmTy, SDPatternOperator IntOp>
2210   : NeonI_2VShiftImm<q, u, opcode,
2211                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2212                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2213                      [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2214                        (i32 ImmTy:$Imm))))],
2215                      NoItinerary>;
2216
2217 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2218                               SDPatternOperator IntOp> {
2219   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2220                       shr_imm32, IntOp> {
2221     let Inst{22-21} = 0b01;
2222   }
2223
2224   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2225                       shr_imm32, IntOp> {
2226     let Inst{22-21} = 0b01;
2227   }
2228
2229   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2230                       shr_imm64, IntOp> {
2231     let Inst{22} = 0b1;
2232   }
2233 }
2234
2235 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2236                               SDPatternOperator IntOp> {
2237   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2238                       shr_imm32, IntOp> {
2239     let Inst{22-21} = 0b01;
2240   }
2241
2242   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2243                       shr_imm32, IntOp> {
2244     let Inst{22-21} = 0b01;
2245   }
2246
2247   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2248                       shr_imm64, IntOp> {
2249     let Inst{22} = 0b1;
2250   }
2251 }
2252
2253 // Convert fixed-point to floating-point
2254 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2255                                    int_arm_neon_vcvtfxs2fp>;
2256 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2257                                    int_arm_neon_vcvtfxu2fp>;
2258
2259 // Convert floating-point to fixed-point
2260 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2261                                    int_arm_neon_vcvtfp2fxs>;
2262 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2263                                    int_arm_neon_vcvtfp2fxu>;
2264
2265 multiclass Neon_sshll2_0<SDNode ext>
2266 {
2267   def _v8i8  : PatFrag<(ops node:$Rn),
2268                        (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2269   def _v4i16 : PatFrag<(ops node:$Rn),
2270                        (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2271   def _v2i32 : PatFrag<(ops node:$Rn),
2272                        (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2273 }
2274
2275 defm NI_sext_high : Neon_sshll2_0<sext>;
2276 defm NI_zext_high : Neon_sshll2_0<zext>;
2277
2278
2279 //===----------------------------------------------------------------------===//
2280 // Multiclasses for NeonI_Across
2281 //===----------------------------------------------------------------------===//
2282
2283 // Variant 1
2284
2285 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2286                             string asmop, SDPatternOperator opnode>
2287 {
2288     def _1h8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2289                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2290                 asmop # "\t$Rd, $Rn.8b",
2291                 [(set (v1i16 FPR16:$Rd),
2292                     (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2293                 NoItinerary>;
2294
2295     def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2296                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2297                 asmop # "\t$Rd, $Rn.16b",
2298                 [(set (v1i16 FPR16:$Rd),
2299                     (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2300                 NoItinerary>;
2301
2302     def _1s4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2303                 (outs FPR32:$Rd), (ins VPR64:$Rn),
2304                 asmop # "\t$Rd, $Rn.4h",
2305                 [(set (v1i32 FPR32:$Rd),
2306                     (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2307                 NoItinerary>;
2308
2309     def _1s8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2310                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2311                 asmop # "\t$Rd, $Rn.8h",
2312                 [(set (v1i32 FPR32:$Rd),
2313                     (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2314                 NoItinerary>;
2315
2316     // _1d2s doesn't exist!
2317
2318     def _1d4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2319                 (outs FPR64:$Rd), (ins VPR128:$Rn),
2320                 asmop # "\t$Rd, $Rn.4s",
2321                 [(set (v1i64 FPR64:$Rd),
2322                     (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2323                 NoItinerary>;
2324 }
2325
2326 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2327 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2328
2329 // Variant 2
2330
2331 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2332                             string asmop, SDPatternOperator opnode>
2333 {
2334     def _1b8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2335                 (outs FPR8:$Rd), (ins VPR64:$Rn),
2336                 asmop # "\t$Rd, $Rn.8b",
2337                 [(set (v1i8 FPR8:$Rd),
2338                     (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2339                 NoItinerary>;
2340
2341     def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2342                 (outs FPR8:$Rd), (ins VPR128:$Rn),
2343                 asmop # "\t$Rd, $Rn.16b",
2344                 [(set (v1i8 FPR8:$Rd),
2345                     (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2346                 NoItinerary>;
2347
2348     def _1h4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2349                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2350                 asmop # "\t$Rd, $Rn.4h",
2351                 [(set (v1i16 FPR16:$Rd),
2352                     (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2353                 NoItinerary>;
2354
2355     def _1h8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2356                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2357                 asmop # "\t$Rd, $Rn.8h",
2358                 [(set (v1i16 FPR16:$Rd),
2359                     (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2360                 NoItinerary>;
2361
2362     // _1s2s doesn't exist!
2363
2364     def _1s4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2365                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2366                 asmop # "\t$Rd, $Rn.4s",
2367                 [(set (v1i32 FPR32:$Rd),
2368                     (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2369                 NoItinerary>;
2370 }
2371
2372 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2373 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2374
2375 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2376 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2377
2378 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2379
2380 // Variant 3
2381
2382 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2383                             string asmop, SDPatternOperator opnode> {
2384     def _1s4s:  NeonI_2VAcross<0b1, u, size, opcode,
2385                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2386                 asmop # "\t$Rd, $Rn.4s",
2387                 [(set (v1f32 FPR32:$Rd),
2388                     (v1f32 (opnode (v4f32 VPR128:$Rn))))],
2389                 NoItinerary>;
2390 }
2391
2392 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2393                                 int_aarch64_neon_vmaxnmv>;
2394 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2395                                 int_aarch64_neon_vminnmv>;
2396
2397 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2398                               int_aarch64_neon_vmaxv>;
2399 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2400                               int_aarch64_neon_vminv>;
2401
2402 // The followings are for instruction class (Perm)
2403
2404 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2405                     string asmop, RegisterOperand OpVPR, string OpS,
2406                     SDPatternOperator opnode, ValueType Ty>
2407   : NeonI_Perm<q, size, opcode,
2408                (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2409                asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2410                [(set (Ty OpVPR:$Rd),
2411                   (Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
2412                NoItinerary>;
2413
2414 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
2415                           SDPatternOperator opnode> {
2416   def _8b  : NeonI_Permute<0b0, 0b00, opcode, asmop,
2417                            VPR64, "8b", opnode, v8i8>;
2418   def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop,
2419                            VPR128, "16b",opnode, v16i8>;
2420   def _4h  : NeonI_Permute<0b0, 0b01, opcode, asmop,
2421                            VPR64, "4h", opnode, v4i16>;
2422   def _8h  : NeonI_Permute<0b1, 0b01, opcode, asmop,
2423                            VPR128, "8h", opnode, v8i16>;
2424   def _2s  : NeonI_Permute<0b0, 0b10, opcode, asmop,
2425                            VPR64, "2s", opnode, v2i32>;
2426   def _4s  : NeonI_Permute<0b1, 0b10, opcode, asmop,
2427                            VPR128, "4s", opnode, v4i32>;
2428   def _2d  : NeonI_Permute<0b1, 0b11, opcode, asmop,
2429                            VPR128, "2d", opnode, v2i64>;
2430 }
2431
2432 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1", Neon_uzp1>;
2433 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1", Neon_trn1>;
2434 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1", Neon_zip1>;
2435 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2", Neon_uzp2>;
2436 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2", Neon_trn2>;
2437 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2", Neon_zip2>;
2438
2439 multiclass NeonI_Perm_float_pat<string INS, SDPatternOperator opnode> {
2440   def : Pat<(v2f32 (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
2441             (!cast<Instruction>(INS # "_2s") VPR64:$Rn, VPR64:$Rm)>;
2442
2443   def : Pat<(v4f32 (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
2444             (!cast<Instruction>(INS # "_4s") VPR128:$Rn, VPR128:$Rm)>;
2445
2446   def : Pat<(v2f64 (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
2447             (!cast<Instruction>(INS # "_2d") VPR128:$Rn, VPR128:$Rm)>;
2448 }
2449
2450 defm : NeonI_Perm_float_pat<"UZP1vvv", Neon_uzp1>;
2451 defm : NeonI_Perm_float_pat<"UZP2vvv", Neon_uzp2>;
2452 defm : NeonI_Perm_float_pat<"ZIP1vvv", Neon_zip1>;
2453 defm : NeonI_Perm_float_pat<"ZIP2vvv", Neon_zip2>;
2454 defm : NeonI_Perm_float_pat<"TRN1vvv", Neon_trn1>;
2455 defm : NeonI_Perm_float_pat<"TRN2vvv", Neon_trn2>;
2456
2457 // The followings are for instruction class (3V Diff)
2458
2459 // normal long/long2 pattern
2460 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2461                  string asmop, string ResS, string OpS,
2462                  SDPatternOperator opnode, SDPatternOperator ext,
2463                  RegisterOperand OpVPR,
2464                  ValueType ResTy, ValueType OpTy>
2465   : NeonI_3VDiff<q, u, size, opcode,
2466                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2467                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2468                  [(set (ResTy VPR128:$Rd),
2469                     (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2470                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2471                  NoItinerary>;
2472
2473 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2474                         string asmop, SDPatternOperator opnode,
2475                         bit Commutable = 0> {
2476   let isCommutable = Commutable in {
2477     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2478                            opnode, sext, VPR64, v8i16, v8i8>;
2479     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2480                            opnode, sext, VPR64, v4i32, v4i16>;
2481     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2482                            opnode, sext, VPR64, v2i64, v2i32>;
2483   }
2484 }
2485
2486 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2487                          SDPatternOperator opnode, bit Commutable = 0> {
2488   let isCommutable = Commutable in {
2489     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2490                             opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2491     def _4s8h  : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2492                             opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2493     def _2d4s  : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2494                             opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2495   }
2496 }
2497
2498 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2499                         SDPatternOperator opnode, bit Commutable = 0> {
2500   let isCommutable = Commutable in {
2501     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2502                            opnode, zext, VPR64, v8i16, v8i8>;
2503     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2504                            opnode, zext, VPR64, v4i32, v4i16>;
2505     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2506                            opnode, zext, VPR64, v2i64, v2i32>;
2507   }
2508 }
2509
2510 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2511                          SDPatternOperator opnode, bit Commutable = 0> {
2512   let isCommutable = Commutable in {
2513     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2514                             opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2515     def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2516                            opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2517     def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2518                            opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2519   }
2520 }
2521
2522 defm SADDLvvv :  NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2523 defm UADDLvvv :  NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2524
2525 defm SADDL2vvv :  NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2526 defm UADDL2vvv :  NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2527
2528 defm SSUBLvvv :  NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2529 defm USUBLvvv :  NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2530
2531 defm SSUBL2vvv :  NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2532 defm USUBL2vvv :  NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2533
2534 // normal wide/wide2 pattern
2535 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2536                  string asmop, string ResS, string OpS,
2537                  SDPatternOperator opnode, SDPatternOperator ext,
2538                  RegisterOperand OpVPR,
2539                  ValueType ResTy, ValueType OpTy>
2540   : NeonI_3VDiff<q, u, size, opcode,
2541                  (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2542                  asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2543                  [(set (ResTy VPR128:$Rd),
2544                     (ResTy (opnode (ResTy VPR128:$Rn),
2545                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2546                  NoItinerary>;
2547
2548 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2549                         SDPatternOperator opnode> {
2550   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2551                          opnode, sext, VPR64, v8i16, v8i8>;
2552   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2553                          opnode, sext, VPR64, v4i32, v4i16>;
2554   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2555                          opnode, sext, VPR64, v2i64, v2i32>;
2556 }
2557
2558 defm SADDWvvv :  NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2559 defm SSUBWvvv :  NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2560
2561 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2562                          SDPatternOperator opnode> {
2563   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2564                           opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2565   def _4s8h  : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2566                           opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2567   def _2d4s  : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2568                           opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2569 }
2570
2571 defm SADDW2vvv :  NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2572 defm SSUBW2vvv :  NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2573
2574 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2575                         SDPatternOperator opnode> {
2576   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2577                          opnode, zext, VPR64, v8i16, v8i8>;
2578   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2579                          opnode, zext, VPR64, v4i32, v4i16>;
2580   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2581                          opnode, zext, VPR64, v2i64, v2i32>;
2582 }
2583
2584 defm UADDWvvv :  NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2585 defm USUBWvvv :  NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2586
2587 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2588                          SDPatternOperator opnode> {
2589   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2590                           opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2591   def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2592                          opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2593   def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2594                          opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2595 }
2596
2597 defm UADDW2vvv :  NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2598 defm USUBW2vvv :  NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2599
2600 // Get the high half part of the vector element.
2601 multiclass NeonI_get_high {
2602   def _8h : PatFrag<(ops node:$Rn),
2603                     (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2604                                              (v8i16 (Neon_vdup (i32 8)))))))>;
2605   def _4s : PatFrag<(ops node:$Rn),
2606                     (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2607                                               (v4i32 (Neon_vdup (i32 16)))))))>;
2608   def _2d : PatFrag<(ops node:$Rn),
2609                     (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2610                                               (v2i64 (Neon_vdup (i32 32)))))))>;
2611 }
2612
2613 defm NI_get_hi : NeonI_get_high;
2614
2615 // pattern for addhn/subhn with 2 operands
2616 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2617                            string asmop, string ResS, string OpS,
2618                            SDPatternOperator opnode, SDPatternOperator get_hi,
2619                            ValueType ResTy, ValueType OpTy>
2620   : NeonI_3VDiff<q, u, size, opcode,
2621                  (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2622                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2623                  [(set (ResTy VPR64:$Rd),
2624                     (ResTy (get_hi
2625                       (OpTy (opnode (OpTy VPR128:$Rn),
2626                                     (OpTy VPR128:$Rm))))))],
2627                  NoItinerary>;
2628
2629 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2630                                 SDPatternOperator opnode, bit Commutable = 0> {
2631   let isCommutable = Commutable in {
2632     def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2633                                      opnode, NI_get_hi_8h, v8i8, v8i16>;
2634     def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2635                                      opnode, NI_get_hi_4s, v4i16, v4i32>;
2636     def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2637                                      opnode, NI_get_hi_2d, v2i32, v2i64>;
2638   }
2639 }
2640
2641 defm ADDHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2642 defm SUBHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2643
2644 // pattern for operation with 2 operands
2645 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2646                     string asmop, string ResS, string OpS,
2647                     SDPatternOperator opnode,
2648                     RegisterOperand ResVPR, RegisterOperand OpVPR,
2649                     ValueType ResTy, ValueType OpTy>
2650   : NeonI_3VDiff<q, u, size, opcode,
2651                  (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2652                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2653                  [(set (ResTy ResVPR:$Rd),
2654                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2655                  NoItinerary>;
2656
2657 // normal narrow pattern
2658 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2659                           SDPatternOperator opnode, bit Commutable = 0> {
2660   let isCommutable = Commutable in {
2661     def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2662                               opnode, VPR64, VPR128, v8i8, v8i16>;
2663     def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2664                               opnode, VPR64, VPR128, v4i16, v4i32>;
2665     def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2666                               opnode, VPR64, VPR128, v2i32, v2i64>;
2667   }
2668 }
2669
2670 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2671 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2672
2673 // pattern for acle intrinsic with 3 operands
2674 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2675                      string asmop, string ResS, string OpS>
2676   : NeonI_3VDiff<q, u, size, opcode,
2677                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2678                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2679                  [], NoItinerary> {
2680   let Constraints = "$src = $Rd";
2681   let neverHasSideEffects = 1;
2682 }
2683
2684 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2685   def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2686   def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2687   def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2688 }
2689
2690 defm ADDHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2691 defm SUBHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2692
2693 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2694 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2695
2696 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2697 // part.
2698 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2699                         SDPatternOperator coreop>
2700   : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2701                       (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2702                                                         (SrcTy VPR128:$Rm)))))),
2703         (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2704               VPR128:$Rn, VPR128:$Rm)>;
2705
2706 // addhn2 patterns
2707 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8,  v8i16,
2708           BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2709 def : NarrowHighHalfPat<ADDHN2vvv_8h4s,  v4i16, v4i32,
2710           BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2711 def : NarrowHighHalfPat<ADDHN2vvv_4s2d,  v2i32, v2i64,
2712           BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2713
2714 // subhn2 patterns
2715 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8,  v8i16,
2716           BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2717 def : NarrowHighHalfPat<SUBHN2vvv_8h4s,  v4i16, v4i32,
2718           BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2719 def : NarrowHighHalfPat<SUBHN2vvv_4s2d,  v2i32, v2i64,
2720           BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2721
2722 // raddhn2 patterns
2723 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vraddhn>;
2724 def : NarrowHighHalfPat<RADDHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vraddhn>;
2725 def : NarrowHighHalfPat<RADDHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vraddhn>;
2726
2727 // rsubhn2 patterns
2728 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vrsubhn>;
2729 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vrsubhn>;
2730 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vrsubhn>;
2731
2732 // pattern that need to extend result
2733 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2734                      string asmop, string ResS, string OpS,
2735                      SDPatternOperator opnode,
2736                      RegisterOperand OpVPR,
2737                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2738   : NeonI_3VDiff<q, u, size, opcode,
2739                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2740                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2741                  [(set (ResTy VPR128:$Rd),
2742                     (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2743                                                 (OpTy OpVPR:$Rm))))))],
2744                  NoItinerary>;
2745
2746 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2747                            SDPatternOperator opnode, bit Commutable = 0> {
2748   let isCommutable = Commutable in {
2749     def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2750                                opnode, VPR64, v8i16, v8i8, v8i8>;
2751     def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2752                                opnode, VPR64, v4i32, v4i16, v4i16>;
2753     def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2754                                opnode, VPR64, v2i64, v2i32, v2i32>;
2755   }
2756 }
2757
2758 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2759 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2760
2761 multiclass NeonI_Op_High<SDPatternOperator op> {
2762   def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2763                      (op (v8i8 (Neon_High16B node:$Rn)),
2764                          (v8i8 (Neon_High16B node:$Rm)))>;
2765   def _8H  : PatFrag<(ops node:$Rn, node:$Rm),
2766                      (op (v4i16 (Neon_High8H node:$Rn)),
2767                          (v4i16 (Neon_High8H node:$Rm)))>;
2768   def _4S  : PatFrag<(ops node:$Rn, node:$Rm),
2769                      (op (v2i32 (Neon_High4S node:$Rn)),
2770                          (v2i32 (Neon_High4S node:$Rm)))>;
2771 }
2772
2773 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2774 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2775 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2776 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2777 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2778 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2779
2780 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
2781                             bit Commutable = 0> {
2782   let isCommutable = Commutable in {
2783     def _8h8b  : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2784                                 !cast<PatFrag>(opnode # "_16B"),
2785                                 VPR128, v8i16, v16i8, v8i8>;
2786     def _4s4h  : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2787                                 !cast<PatFrag>(opnode # "_8H"),
2788                                 VPR128, v4i32, v8i16, v4i16>;
2789     def _2d2s  : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2790                                 !cast<PatFrag>(opnode # "_4S"),
2791                                 VPR128, v2i64, v4i32, v2i32>;
2792   }
2793 }
2794
2795 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2796 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2797
2798 // For pattern that need two operators being chained.
2799 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2800                      string asmop, string ResS, string OpS,
2801                      SDPatternOperator opnode, SDPatternOperator subop,
2802                      RegisterOperand OpVPR,
2803                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2804   : NeonI_3VDiff<q, u, size, opcode,
2805                  (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2806                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2807                  [(set (ResTy VPR128:$Rd),
2808                     (ResTy (opnode
2809                       (ResTy VPR128:$src),
2810                       (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2811                                                  (OpTy OpVPR:$Rm))))))))],
2812                  NoItinerary> {
2813   let Constraints = "$src = $Rd";
2814 }
2815
2816 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
2817                              SDPatternOperator opnode, SDPatternOperator subop>{
2818   def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2819                              opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2820   def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2821                              opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2822   def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2823                              opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2824 }
2825
2826 defm SABALvvv :  NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2827                                    add, int_arm_neon_vabds>;
2828 defm UABALvvv :  NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2829                                    add, int_arm_neon_vabdu>;
2830
2831 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
2832                               SDPatternOperator opnode, string subop> {
2833   def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2834                              opnode, !cast<PatFrag>(subop # "_16B"),
2835                              VPR128, v8i16, v16i8, v8i8>;
2836   def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2837                              opnode, !cast<PatFrag>(subop # "_8H"),
2838                              VPR128, v4i32, v8i16, v4i16>;
2839   def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2840                              opnode, !cast<PatFrag>(subop # "_4S"),
2841                              VPR128, v2i64, v4i32, v2i32>;
2842 }
2843
2844 defm SABAL2vvv :  NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
2845                                      "NI_sabdl_hi">;
2846 defm UABAL2vvv :  NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
2847                                      "NI_uabdl_hi">;
2848
2849 // Long pattern with 2 operands
2850 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
2851                           SDPatternOperator opnode, bit Commutable = 0> {
2852   let isCommutable = Commutable in {
2853     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2854                               opnode, VPR128, VPR64, v8i16, v8i8>;
2855     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2856                               opnode, VPR128, VPR64, v4i32, v4i16>;
2857     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2858                               opnode, VPR128, VPR64, v2i64, v2i32>;
2859   }
2860 }
2861
2862 defm SMULLvvv :  NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
2863 defm UMULLvvv :  NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
2864
2865 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
2866                            string asmop, string ResS, string OpS,
2867                            SDPatternOperator opnode,
2868                            ValueType ResTy, ValueType OpTy>
2869   : NeonI_3VDiff<q, u, size, opcode,
2870                  (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2871                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2872                  [(set (ResTy VPR128:$Rd),
2873                     (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
2874                  NoItinerary>;
2875
2876 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
2877                                    string opnode, bit Commutable = 0> {
2878   let isCommutable = Commutable in {
2879     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2880                                       !cast<PatFrag>(opnode # "_16B"),
2881                                       v8i16, v16i8>;
2882     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2883                                      !cast<PatFrag>(opnode # "_8H"),
2884                                      v4i32, v8i16>;
2885     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2886                                      !cast<PatFrag>(opnode # "_4S"),
2887                                      v2i64, v4i32>;
2888   }
2889 }
2890
2891 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
2892                                          "NI_smull_hi", 1>;
2893 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
2894                                          "NI_umull_hi", 1>;
2895
2896 // Long pattern with 3 operands
2897 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2898                      string asmop, string ResS, string OpS,
2899                      SDPatternOperator opnode,
2900                      ValueType ResTy, ValueType OpTy>
2901   : NeonI_3VDiff<q, u, size, opcode,
2902                  (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
2903                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2904                  [(set (ResTy VPR128:$Rd),
2905                     (ResTy (opnode
2906                       (ResTy VPR128:$src),
2907                       (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
2908                NoItinerary> {
2909   let Constraints = "$src = $Rd";
2910 }
2911
2912 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
2913                              SDPatternOperator opnode> {
2914   def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2915                              opnode, v8i16, v8i8>;
2916   def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2917                              opnode, v4i32, v4i16>;
2918   def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2919                              opnode, v2i64, v2i32>;
2920 }
2921
2922 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2923                          (add node:$Rd,
2924                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2925
2926 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2927                          (add node:$Rd,
2928                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2929
2930 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2931                          (sub node:$Rd,
2932                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2933
2934 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2935                          (sub node:$Rd,
2936                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2937
2938 defm SMLALvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
2939 defm UMLALvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
2940
2941 defm SMLSLvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
2942 defm UMLSLvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
2943
2944 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
2945                            string asmop, string ResS, string OpS,
2946                            SDPatternOperator subop, SDPatternOperator opnode,
2947                            RegisterOperand OpVPR,
2948                            ValueType ResTy, ValueType OpTy>
2949   : NeonI_3VDiff<q, u, size, opcode,
2950                (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2951                asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2952                [(set (ResTy VPR128:$Rd),
2953                   (ResTy (subop
2954                     (ResTy VPR128:$src),
2955                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
2956                NoItinerary> {
2957   let Constraints = "$src = $Rd";
2958 }
2959
2960 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
2961                                    SDPatternOperator subop, string opnode> {
2962   def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2963                                     subop, !cast<PatFrag>(opnode # "_16B"),
2964                                     VPR128, v8i16, v16i8>;
2965   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2966                                    subop, !cast<PatFrag>(opnode # "_8H"),
2967                                    VPR128, v4i32, v8i16>;
2968   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2969                                    subop, !cast<PatFrag>(opnode # "_4S"),
2970                                    VPR128, v2i64, v4i32>;
2971 }
2972
2973 defm SMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
2974                                           add, "NI_smull_hi">;
2975 defm UMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
2976                                           add, "NI_umull_hi">;
2977
2978 defm SMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
2979                                           sub, "NI_smull_hi">;
2980 defm UMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
2981                                           sub, "NI_umull_hi">;
2982
2983 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
2984                                     SDPatternOperator opnode> {
2985   def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2986                                    opnode, int_arm_neon_vqdmull,
2987                                    VPR64, v4i32, v4i16>;
2988   def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2989                                    opnode, int_arm_neon_vqdmull,
2990                                    VPR64, v2i64, v2i32>;
2991 }
2992
2993 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
2994                                            int_arm_neon_vqadds>;
2995 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
2996                                            int_arm_neon_vqsubs>;
2997
2998 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
2999                          SDPatternOperator opnode, bit Commutable = 0> {
3000   let isCommutable = Commutable in {
3001     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3002                               opnode, VPR128, VPR64, v4i32, v4i16>;
3003     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3004                               opnode, VPR128, VPR64, v2i64, v2i32>;
3005   }
3006 }
3007
3008 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
3009                                 int_arm_neon_vqdmull, 1>;
3010
3011 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
3012                                    string opnode, bit Commutable = 0> {
3013   let isCommutable = Commutable in {
3014     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3015                                      !cast<PatFrag>(opnode # "_8H"),
3016                                      v4i32, v8i16>;
3017     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3018                                      !cast<PatFrag>(opnode # "_4S"),
3019                                      v2i64, v4i32>;
3020   }
3021 }
3022
3023 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3024                                            "NI_qdmull_hi", 1>;
3025
3026 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3027                                      SDPatternOperator opnode> {
3028   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3029                                    opnode, NI_qdmull_hi_8H,
3030                                    VPR128, v4i32, v8i16>;
3031   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3032                                    opnode, NI_qdmull_hi_4S,
3033                                    VPR128, v2i64, v4i32>;
3034 }
3035
3036 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3037                                              int_arm_neon_vqadds>;
3038 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3039                                              int_arm_neon_vqsubs>;
3040
3041 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3042                          SDPatternOperator opnode_8h8b,
3043                          SDPatternOperator opnode_1q1d, bit Commutable = 0> {
3044   let isCommutable = Commutable in {
3045     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3046                               opnode_8h8b, VPR128, VPR64, v8i16, v8i8>;
3047
3048     def _1q1d : NeonI_3VD_2Op<0b0, u, 0b11, opcode, asmop, "1q", "1d",
3049                               opnode_1q1d, VPR128, VPR64, v16i8, v1i64>;
3050   }
3051 }
3052
3053 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp,
3054                               int_aarch64_neon_vmull_p64, 1>;
3055
3056 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3057                                    string opnode, bit Commutable = 0> {
3058   let isCommutable = Commutable in {
3059     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3060                                       !cast<PatFrag>(opnode # "_16B"),
3061                                       v8i16, v16i8>;
3062
3063     def _1q2d :
3064       NeonI_3VDiff<0b1, u, 0b11, opcode,
3065                    (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3066                    asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3067                    [(set (v16i8 VPR128:$Rd),
3068                       (v16i8 (int_aarch64_neon_vmull_p64
3069                         (v1i64 (scalar_to_vector
3070                           (i64 (vector_extract (v2i64 VPR128:$Rn), 1)))),
3071                         (v1i64 (scalar_to_vector
3072                           (i64 (vector_extract (v2i64 VPR128:$Rm), 1)))))))],
3073                    NoItinerary>;
3074   }
3075 }
3076
3077 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3078                                          1>;
3079
3080 // End of implementation for instruction class (3V Diff)
3081
3082 // The followings are vector load/store multiple N-element structure
3083 // (class SIMD lselem).
3084
3085 // ld1:         load multiple 1-element structure to 1/2/3/4 registers.
3086 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3087 //              The structure consists of a sequence of sets of N values.
3088 //              The first element of the structure is placed in the first lane
3089 //              of the first first vector, the second element in the first lane
3090 //              of the second vector, and so on.
3091 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3092 // the three 64-bit vectors list {BA, DC, FE}.
3093 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3094 // 64-bit vectors list {DA, EB, FC}.
3095 // Store instructions store multiple structure to N registers like load.
3096
3097
3098 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3099                     RegisterOperand VecList, string asmop>
3100   : NeonI_LdStMult<q, 1, opcode, size,
3101                  (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3102                  asmop # "\t$Rt, [$Rn]",
3103                  [],
3104                  NoItinerary> {
3105   let mayLoad = 1;
3106   let neverHasSideEffects = 1;
3107 }
3108
3109 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3110   def _8B : NeonI_LDVList<0, opcode, 0b00,
3111                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3112
3113   def _4H : NeonI_LDVList<0, opcode, 0b01,
3114                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3115
3116   def _2S : NeonI_LDVList<0, opcode, 0b10,
3117                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3118
3119   def _16B : NeonI_LDVList<1, opcode, 0b00,
3120                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3121
3122   def _8H : NeonI_LDVList<1, opcode, 0b01,
3123                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3124
3125   def _4S : NeonI_LDVList<1, opcode, 0b10,
3126                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3127
3128   def _2D : NeonI_LDVList<1, opcode, 0b11,
3129                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3130 }
3131
3132 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3133 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3134 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3135
3136 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3137
3138 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3139
3140 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3141
3142 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3143 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3144 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3145
3146 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3147 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3148
3149 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3150 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3151
3152 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3153                     RegisterOperand VecList, string asmop>
3154   : NeonI_LdStMult<q, 0, opcode, size,
3155                  (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3156                  asmop # "\t$Rt, [$Rn]",
3157                  [],
3158                  NoItinerary> {
3159   let mayStore = 1;
3160   let neverHasSideEffects = 1;
3161 }
3162
3163 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3164   def _8B : NeonI_STVList<0, opcode, 0b00,
3165                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3166
3167   def _4H : NeonI_STVList<0, opcode, 0b01,
3168                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3169
3170   def _2S : NeonI_STVList<0, opcode, 0b10,
3171                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3172
3173   def _16B : NeonI_STVList<1, opcode, 0b00,
3174                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3175
3176   def _8H : NeonI_STVList<1, opcode, 0b01,
3177                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3178
3179   def _4S : NeonI_STVList<1, opcode, 0b10,
3180                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3181
3182   def _2D : NeonI_STVList<1, opcode, 0b11,
3183                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3184 }
3185
3186 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3187 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3188 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3189
3190 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3191
3192 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3193
3194 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3195
3196 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3197 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3198 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3199
3200 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3201 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3202
3203 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3204 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3205
3206 def : Pat<(v2f64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3207 def : Pat<(v2i64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3208
3209 def : Pat<(v4f32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3210 def : Pat<(v4i32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3211
3212 def : Pat<(v8i16 (load GPR64xsp:$addr)), (LD1_8H GPR64xsp:$addr)>;
3213 def : Pat<(v16i8 (load GPR64xsp:$addr)), (LD1_16B GPR64xsp:$addr)>;
3214
3215 def : Pat<(v1f64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3216 def : Pat<(v1i64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3217
3218 def : Pat<(v2f32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3219 def : Pat<(v2i32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3220
3221 def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;
3222 def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;
3223
3224 def : Pat<(store (v2i64 VPR128:$value), GPR64xsp:$addr),
3225           (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3226 def : Pat<(store (v2f64 VPR128:$value), GPR64xsp:$addr),
3227           (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3228
3229 def : Pat<(store (v4i32 VPR128:$value), GPR64xsp:$addr),
3230           (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3231 def : Pat<(store (v4f32 VPR128:$value), GPR64xsp:$addr),
3232           (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3233
3234 def : Pat<(store (v8i16 VPR128:$value), GPR64xsp:$addr),
3235           (ST1_8H GPR64xsp:$addr, VPR128:$value)>;
3236 def : Pat<(store (v16i8 VPR128:$value), GPR64xsp:$addr),
3237           (ST1_16B GPR64xsp:$addr, VPR128:$value)>;
3238
3239 def : Pat<(store (v1i64 VPR64:$value), GPR64xsp:$addr),
3240           (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3241 def : Pat<(store (v1f64 VPR64:$value), GPR64xsp:$addr),
3242           (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3243
3244 def : Pat<(store (v2i32 VPR64:$value), GPR64xsp:$addr),
3245           (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3246 def : Pat<(store (v2f32 VPR64:$value), GPR64xsp:$addr),
3247           (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3248
3249 def : Pat<(store (v4i16 VPR64:$value), GPR64xsp:$addr),
3250           (ST1_4H GPR64xsp:$addr, VPR64:$value)>;
3251 def : Pat<(store (v8i8 VPR64:$value), GPR64xsp:$addr),
3252           (ST1_8B GPR64xsp:$addr, VPR64:$value)>;
3253
3254 // End of vector load/store multiple N-element structure(class SIMD lselem)
3255
3256 // The followings are post-index vector load/store multiple N-element
3257 // structure(class SIMD lselem-post)
3258 def exact1_asmoperand : AsmOperandClass {
3259   let Name = "Exact1";
3260   let PredicateMethod = "isExactImm<1>";
3261   let RenderMethod = "addImmOperands";
3262 }
3263 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3264   let ParserMatchClass = exact1_asmoperand;
3265 }
3266
3267 def exact2_asmoperand : AsmOperandClass {
3268   let Name = "Exact2";
3269   let PredicateMethod = "isExactImm<2>";
3270   let RenderMethod = "addImmOperands";
3271 }
3272 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3273   let ParserMatchClass = exact2_asmoperand;
3274 }
3275
3276 def exact3_asmoperand : AsmOperandClass {
3277   let Name = "Exact3";
3278   let PredicateMethod = "isExactImm<3>";
3279   let RenderMethod = "addImmOperands";
3280 }
3281 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3282   let ParserMatchClass = exact3_asmoperand;
3283 }
3284
3285 def exact4_asmoperand : AsmOperandClass {
3286   let Name = "Exact4";
3287   let PredicateMethod = "isExactImm<4>";
3288   let RenderMethod = "addImmOperands";
3289 }
3290 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3291   let ParserMatchClass = exact4_asmoperand;
3292 }
3293
3294 def exact6_asmoperand : AsmOperandClass {
3295   let Name = "Exact6";
3296   let PredicateMethod = "isExactImm<6>";
3297   let RenderMethod = "addImmOperands";
3298 }
3299 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3300   let ParserMatchClass = exact6_asmoperand;
3301 }
3302
3303 def exact8_asmoperand : AsmOperandClass {
3304   let Name = "Exact8";
3305   let PredicateMethod = "isExactImm<8>";
3306   let RenderMethod = "addImmOperands";
3307 }
3308 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3309   let ParserMatchClass = exact8_asmoperand;
3310 }
3311
3312 def exact12_asmoperand : AsmOperandClass {
3313   let Name = "Exact12";
3314   let PredicateMethod = "isExactImm<12>";
3315   let RenderMethod = "addImmOperands";
3316 }
3317 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3318   let ParserMatchClass = exact12_asmoperand;
3319 }
3320
3321 def exact16_asmoperand : AsmOperandClass {
3322   let Name = "Exact16";
3323   let PredicateMethod = "isExactImm<16>";
3324   let RenderMethod = "addImmOperands";
3325 }
3326 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3327   let ParserMatchClass = exact16_asmoperand;
3328 }
3329
3330 def exact24_asmoperand : AsmOperandClass {
3331   let Name = "Exact24";
3332   let PredicateMethod = "isExactImm<24>";
3333   let RenderMethod = "addImmOperands";
3334 }
3335 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3336   let ParserMatchClass = exact24_asmoperand;
3337 }
3338
3339 def exact32_asmoperand : AsmOperandClass {
3340   let Name = "Exact32";
3341   let PredicateMethod = "isExactImm<32>";
3342   let RenderMethod = "addImmOperands";
3343 }
3344 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3345   let ParserMatchClass = exact32_asmoperand;
3346 }
3347
3348 def exact48_asmoperand : AsmOperandClass {
3349   let Name = "Exact48";
3350   let PredicateMethod = "isExactImm<48>";
3351   let RenderMethod = "addImmOperands";
3352 }
3353 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3354   let ParserMatchClass = exact48_asmoperand;
3355 }
3356
3357 def exact64_asmoperand : AsmOperandClass {
3358   let Name = "Exact64";
3359   let PredicateMethod = "isExactImm<64>";
3360   let RenderMethod = "addImmOperands";
3361 }
3362 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3363   let ParserMatchClass = exact64_asmoperand;
3364 }
3365
3366 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3367                            RegisterOperand VecList, Operand ImmTy,
3368                            string asmop> {
3369   let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3370       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3371     def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3372                      (outs VecList:$Rt, GPR64xsp:$wb),
3373                      (ins GPR64xsp:$Rn, ImmTy:$amt),
3374                      asmop # "\t$Rt, [$Rn], $amt",
3375                      [],
3376                      NoItinerary> {
3377       let Rm = 0b11111;
3378     }
3379
3380     def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3381                         (outs VecList:$Rt, GPR64xsp:$wb),
3382                         (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3383                         asmop # "\t$Rt, [$Rn], $Rm",
3384                         [],
3385                         NoItinerary>;
3386   }
3387 }
3388
3389 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3390     Operand ImmTy2, string asmop> {
3391   defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3392                               !cast<RegisterOperand>(List # "8B_operand"),
3393                               ImmTy, asmop>;
3394
3395   defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3396                               !cast<RegisterOperand>(List # "4H_operand"),
3397                               ImmTy, asmop>;
3398
3399   defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3400                               !cast<RegisterOperand>(List # "2S_operand"),
3401                               ImmTy, asmop>;
3402
3403   defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3404                                !cast<RegisterOperand>(List # "16B_operand"),
3405                                ImmTy2, asmop>;
3406
3407   defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3408                               !cast<RegisterOperand>(List # "8H_operand"),
3409                               ImmTy2, asmop>;
3410
3411   defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3412                               !cast<RegisterOperand>(List # "4S_operand"),
3413                               ImmTy2, asmop>;
3414
3415   defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3416                               !cast<RegisterOperand>(List # "2D_operand"),
3417                               ImmTy2, asmop>;
3418 }
3419
3420 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3421 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3422 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3423                                  "ld1">;
3424
3425 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3426
3427 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3428                              "ld3">;
3429
3430 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3431
3432 // Post-index load multiple 1-element structures from N consecutive registers
3433 // (N = 2,3,4)
3434 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3435                                "ld1">;
3436 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3437                                    uimm_exact16, "ld1">;
3438
3439 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3440                                "ld1">;
3441 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3442                                    uimm_exact24, "ld1">;
3443
3444 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3445                                 "ld1">;
3446 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3447                                    uimm_exact32, "ld1">;
3448
3449 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3450                             RegisterOperand VecList, Operand ImmTy,
3451                             string asmop> {
3452   let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3453       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3454     def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3455                      (outs GPR64xsp:$wb),
3456                      (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3457                      asmop # "\t$Rt, [$Rn], $amt",
3458                      [],
3459                      NoItinerary> {
3460       let Rm = 0b11111;
3461     }
3462
3463     def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3464                       (outs GPR64xsp:$wb),
3465                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3466                       asmop # "\t$Rt, [$Rn], $Rm",
3467                       [],
3468                       NoItinerary>;
3469   }
3470 }
3471
3472 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3473                            Operand ImmTy2, string asmop> {
3474   defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3475                  !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3476
3477   defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3478                               !cast<RegisterOperand>(List # "4H_operand"),
3479                               ImmTy, asmop>;
3480
3481   defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3482                               !cast<RegisterOperand>(List # "2S_operand"),
3483                               ImmTy, asmop>;
3484
3485   defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3486                                !cast<RegisterOperand>(List # "16B_operand"),
3487                                ImmTy2, asmop>;
3488
3489   defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3490                               !cast<RegisterOperand>(List # "8H_operand"),
3491                               ImmTy2, asmop>;
3492
3493   defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3494                               !cast<RegisterOperand>(List # "4S_operand"),
3495                               ImmTy2, asmop>;
3496
3497   defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3498                               !cast<RegisterOperand>(List # "2D_operand"),
3499                               ImmTy2, asmop>;
3500 }
3501
3502 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3503 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3504 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3505                                  "st1">;
3506
3507 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3508
3509 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3510                              "st3">;
3511
3512 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3513
3514 // Post-index load multiple 1-element structures from N consecutive registers
3515 // (N = 2,3,4)
3516 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3517                                "st1">;
3518 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3519                                    uimm_exact16, "st1">;
3520
3521 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3522                                "st1">;
3523 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3524                                    uimm_exact24, "st1">;
3525
3526 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3527                                "st1">;
3528 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3529                                    uimm_exact32, "st1">;
3530
3531 // End of post-index vector load/store multiple N-element structure
3532 // (class SIMD lselem-post)
3533
3534 // The followings are vector load/store single N-element structure
3535 // (class SIMD lsone).
3536 def neon_uimm0_bare : Operand<i64>,
3537                         ImmLeaf<i64, [{return Imm == 0;}]> {
3538   let ParserMatchClass = neon_uimm0_asmoperand;
3539   let PrintMethod = "printUImmBareOperand";
3540 }
3541
3542 def neon_uimm1_bare : Operand<i64>,
3543                         ImmLeaf<i64, [{return Imm < 2;}]> {
3544   let ParserMatchClass = neon_uimm1_asmoperand;
3545   let PrintMethod = "printUImmBareOperand";
3546 }
3547
3548 def neon_uimm2_bare : Operand<i64>,
3549                         ImmLeaf<i64, [{return Imm < 4;}]> {
3550   let ParserMatchClass = neon_uimm2_asmoperand;
3551   let PrintMethod = "printUImmBareOperand";
3552 }
3553
3554 def neon_uimm3_bare : Operand<i64>,
3555                         ImmLeaf<i64, [{return Imm < 8;}]> {
3556   let ParserMatchClass = uimm3_asmoperand;
3557   let PrintMethod = "printUImmBareOperand";
3558 }
3559
3560 def neon_uimm4_bare : Operand<i64>,
3561                         ImmLeaf<i64, [{return Imm < 16;}]> {
3562   let ParserMatchClass = uimm4_asmoperand;
3563   let PrintMethod = "printUImmBareOperand";
3564 }
3565
3566 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3567                     RegisterOperand VecList, string asmop>
3568     : NeonI_LdOne_Dup<q, r, opcode, size,
3569                       (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3570                       asmop # "\t$Rt, [$Rn]",
3571                       [],
3572                       NoItinerary> {
3573   let mayLoad = 1;
3574   let neverHasSideEffects = 1;
3575 }
3576
3577 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3578   def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3579                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3580
3581   def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3582                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3583
3584   def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3585                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3586
3587   def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3588                           !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3589
3590   def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3591                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3592
3593   def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3594                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3595
3596   def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3597                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3598
3599   def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3600                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3601 }
3602
3603 // Load single 1-element structure to all lanes of 1 register
3604 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3605
3606 // Load single N-element structure to all lanes of N consecutive
3607 // registers (N = 2,3,4)
3608 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3609 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3610 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3611
3612
3613 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3614                     Instruction INST>
3615     : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3616           (VTy (INST GPR64xsp:$Rn))>;
3617
3618 // Match all LD1R instructions
3619 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3620
3621 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3622
3623 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3624
3625 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3626
3627 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3628 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3629
3630 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3631 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3632
3633 def : LD1R_pattern<v1i64, i64, load, LD1R_1D>;
3634 def : LD1R_pattern<v1f64, f64, load, LD1R_1D>;
3635
3636 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3637 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3638
3639
3640 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3641                                 RegisterClass RegList> {
3642   defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3643   defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3644   defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3645   defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3646 }
3647
3648 // Special vector list operand of 128-bit vectors with bare layout.
3649 // i.e. only show ".b", ".h", ".s", ".d"
3650 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3651 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3652 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3653 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3654
3655 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3656                      Operand ImmOp, string asmop>
3657     : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3658                          (outs VList:$Rt),
3659                          (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3660                          asmop # "\t$Rt[$lane], [$Rn]",
3661                          [],
3662                          NoItinerary> {
3663   let mayLoad = 1;
3664   let neverHasSideEffects = 1;
3665   let hasExtraDefRegAllocReq = 1;
3666   let Constraints = "$src = $Rt";
3667 }
3668
3669 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3670   def _B : NeonI_LDN_Lane<r, 0b00, op0,
3671                           !cast<RegisterOperand>(List # "B_operand"),
3672                           neon_uimm4_bare, asmop> {
3673     let Inst{12-10} = lane{2-0};
3674     let Inst{30} = lane{3};
3675   }
3676
3677   def _H : NeonI_LDN_Lane<r, 0b01, op0,
3678                           !cast<RegisterOperand>(List # "H_operand"),
3679                           neon_uimm3_bare, asmop> {
3680     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3681     let Inst{30} = lane{2};
3682   }
3683
3684   def _S : NeonI_LDN_Lane<r, 0b10, op0,
3685                           !cast<RegisterOperand>(List # "S_operand"),
3686                           neon_uimm2_bare, asmop> {
3687     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3688     let Inst{30} = lane{1};
3689   }
3690
3691   def _D : NeonI_LDN_Lane<r, 0b10, op0,
3692                           !cast<RegisterOperand>(List # "D_operand"),
3693                           neon_uimm1_bare, asmop> {
3694     let Inst{12-10} = 0b001;
3695     let Inst{30} = lane{0};
3696   }
3697 }
3698
3699 // Load single 1-element structure to one lane of 1 register.
3700 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3701
3702 // Load single N-element structure to one lane of N consecutive registers
3703 // (N = 2,3,4)
3704 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3705 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3706 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3707
3708 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3709                           Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3710                           Instruction INST> {
3711   def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3712                      (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3713             (VTy (EXTRACT_SUBREG
3714                      (INST GPR64xsp:$Rn,
3715                            (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3716                            ImmOp:$lane),
3717                      sub_64))>;
3718
3719   def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3720                       (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3721             (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3722 }
3723
3724 // Match all LD1LN instructions
3725 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3726                       extloadi8, LD1LN_B>;
3727
3728 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3729                       extloadi16, LD1LN_H>;
3730
3731 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3732                       load, LD1LN_S>;
3733 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3734                       load, LD1LN_S>;
3735
3736 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3737                       load, LD1LN_D>;
3738 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3739                       load, LD1LN_D>;
3740
3741 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3742                      Operand ImmOp, string asmop>
3743     : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3744                          (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3745                          asmop # "\t$Rt[$lane], [$Rn]",
3746                          [],
3747                          NoItinerary> {
3748   let mayStore = 1;
3749   let neverHasSideEffects = 1;
3750   let hasExtraDefRegAllocReq = 1;
3751 }
3752
3753 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3754   def _B : NeonI_STN_Lane<r, 0b00, op0,
3755                           !cast<RegisterOperand>(List # "B_operand"),
3756                           neon_uimm4_bare, asmop> {
3757     let Inst{12-10} = lane{2-0};
3758     let Inst{30} = lane{3};
3759   }
3760
3761   def _H : NeonI_STN_Lane<r, 0b01, op0,
3762                           !cast<RegisterOperand>(List # "H_operand"),
3763                           neon_uimm3_bare, asmop> {
3764     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3765     let Inst{30} = lane{2};
3766   }
3767
3768   def _S : NeonI_STN_Lane<r, 0b10, op0,
3769                           !cast<RegisterOperand>(List # "S_operand"),
3770                            neon_uimm2_bare, asmop> {
3771     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3772     let Inst{30} = lane{1};
3773   }
3774
3775   def _D : NeonI_STN_Lane<r, 0b10, op0,
3776                           !cast<RegisterOperand>(List # "D_operand"),
3777                           neon_uimm1_bare, asmop>{
3778     let Inst{12-10} = 0b001;
3779     let Inst{30} = lane{0};
3780   }
3781 }
3782
3783 // Store single 1-element structure from one lane of 1 register.
3784 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3785
3786 // Store single N-element structure from one lane of N consecutive registers
3787 // (N = 2,3,4)
3788 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3789 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3790 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3791
3792 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3793                           Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3794                           Instruction INST> {
3795   def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3796                      GPR64xsp:$Rn),
3797             (INST GPR64xsp:$Rn,
3798                   (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
3799                   ImmOp:$lane)>;
3800
3801   def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
3802                      GPR64xsp:$Rn),
3803             (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
3804 }
3805
3806 // Match all ST1LN instructions
3807 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3808                       truncstorei8, ST1LN_B>;
3809
3810 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3811                       truncstorei16, ST1LN_H>;
3812
3813 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3814                       store, ST1LN_S>;
3815 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3816                       store, ST1LN_S>;
3817
3818 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3819                       store, ST1LN_D>;
3820 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3821                       store, ST1LN_D>;
3822
3823 // End of vector load/store single N-element structure (class SIMD lsone).
3824
3825
3826 // The following are post-index load/store single N-element instructions
3827 // (class SIMD lsone-post)
3828
3829 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3830                             RegisterOperand VecList, Operand ImmTy,
3831                             string asmop> {
3832   let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
3833   DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3834     def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3835                       (outs VecList:$Rt, GPR64xsp:$wb),
3836                       (ins GPR64xsp:$Rn, ImmTy:$amt),
3837                       asmop # "\t$Rt, [$Rn], $amt",
3838                       [],
3839                       NoItinerary> {
3840                         let Rm = 0b11111;
3841                       }
3842
3843     def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3844                       (outs VecList:$Rt, GPR64xsp:$wb),
3845                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3846                       asmop # "\t$Rt, [$Rn], $Rm",
3847                       [],
3848                       NoItinerary>;
3849   }
3850 }
3851
3852 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
3853                          Operand uimm_b, Operand uimm_h,
3854                          Operand uimm_s, Operand uimm_d> {
3855   defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
3856                               !cast<RegisterOperand>(List # "8B_operand"),
3857                               uimm_b, asmop>;
3858
3859   defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
3860                               !cast<RegisterOperand>(List # "4H_operand"),
3861                               uimm_h, asmop>;
3862
3863   defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
3864                               !cast<RegisterOperand>(List # "2S_operand"),
3865                               uimm_s, asmop>;
3866
3867   defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
3868                               !cast<RegisterOperand>(List # "1D_operand"),
3869                               uimm_d, asmop>;
3870
3871   defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
3872                                !cast<RegisterOperand>(List # "16B_operand"),
3873                                uimm_b, asmop>;
3874
3875   defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
3876                               !cast<RegisterOperand>(List # "8H_operand"),
3877                               uimm_h, asmop>;
3878
3879   defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
3880                               !cast<RegisterOperand>(List # "4S_operand"),
3881                               uimm_s, asmop>;
3882
3883   defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
3884                               !cast<RegisterOperand>(List # "2D_operand"),
3885                               uimm_d, asmop>;
3886 }
3887
3888 // Post-index load single 1-element structure to all lanes of 1 register
3889 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
3890                              uimm_exact2, uimm_exact4, uimm_exact8>;
3891
3892 // Post-index load single N-element structure to all lanes of N consecutive
3893 // registers (N = 2,3,4)
3894 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
3895                              uimm_exact4, uimm_exact8, uimm_exact16>;
3896 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
3897                              uimm_exact6, uimm_exact12, uimm_exact24>;
3898 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
3899                              uimm_exact8, uimm_exact16, uimm_exact32>;
3900
3901 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
3902     Constraints = "$Rn = $wb, $Rt = $src",
3903     DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3904   class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3905                                 Operand ImmTy, Operand ImmOp, string asmop>
3906       : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3907                                 (outs VList:$Rt, GPR64xsp:$wb),
3908                                 (ins GPR64xsp:$Rn, ImmTy:$amt,
3909                                     VList:$src, ImmOp:$lane),
3910                                 asmop # "\t$Rt[$lane], [$Rn], $amt",
3911                                 [],
3912                                 NoItinerary> {
3913     let Rm = 0b11111;
3914   }
3915
3916   class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3917                                  Operand ImmTy, Operand ImmOp, string asmop>
3918       : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3919                                 (outs VList:$Rt, GPR64xsp:$wb),
3920                                 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
3921                                     VList:$src, ImmOp:$lane),
3922                                 asmop # "\t$Rt[$lane], [$Rn], $Rm",
3923                                 [],
3924                                 NoItinerary>;
3925 }
3926
3927 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
3928                            Operand uimm_b, Operand uimm_h,
3929                            Operand uimm_s, Operand uimm_d> {
3930   def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
3931                                !cast<RegisterOperand>(List # "B_operand"),
3932                                uimm_b, neon_uimm4_bare, asmop> {
3933     let Inst{12-10} = lane{2-0};
3934     let Inst{30} = lane{3};
3935   }
3936
3937   def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
3938                                    !cast<RegisterOperand>(List # "B_operand"),
3939                                    uimm_b, neon_uimm4_bare, asmop> {
3940     let Inst{12-10} = lane{2-0};
3941     let Inst{30} = lane{3};
3942   }
3943
3944   def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
3945                                !cast<RegisterOperand>(List # "H_operand"),
3946                                uimm_h, neon_uimm3_bare, asmop> {
3947     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3948     let Inst{30} = lane{2};
3949   }
3950
3951   def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
3952                                    !cast<RegisterOperand>(List # "H_operand"),
3953                                    uimm_h, neon_uimm3_bare, asmop> {
3954     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3955     let Inst{30} = lane{2};
3956   }
3957
3958   def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3959                                !cast<RegisterOperand>(List # "S_operand"),
3960                                uimm_s, neon_uimm2_bare, asmop> {
3961     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3962     let Inst{30} = lane{1};
3963   }
3964
3965   def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
3966                                    !cast<RegisterOperand>(List # "S_operand"),
3967                                    uimm_s, neon_uimm2_bare, asmop> {
3968     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3969     let Inst{30} = lane{1};
3970   }
3971
3972   def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3973                                !cast<RegisterOperand>(List # "D_operand"),
3974                                uimm_d, neon_uimm1_bare, asmop> {
3975     let Inst{12-10} = 0b001;
3976     let Inst{30} = lane{0};
3977   }
3978
3979   def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
3980                                    !cast<RegisterOperand>(List # "D_operand"),
3981                                    uimm_d, neon_uimm1_bare, asmop> {
3982     let Inst{12-10} = 0b001;
3983     let Inst{30} = lane{0};
3984   }
3985 }
3986
3987 // Post-index load single 1-element structure to one lane of 1 register.
3988 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
3989                                 uimm_exact2, uimm_exact4, uimm_exact8>;
3990
3991 // Post-index load single N-element structure to one lane of N consecutive
3992 // registers
3993 // (N = 2,3,4)
3994 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
3995                                 uimm_exact4, uimm_exact8, uimm_exact16>;
3996 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
3997                                 uimm_exact6, uimm_exact12, uimm_exact24>;
3998 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
3999                                 uimm_exact8, uimm_exact16, uimm_exact32>;
4000
4001 let mayStore = 1, neverHasSideEffects = 1,
4002     hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
4003     DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4004   class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4005                       Operand ImmTy, Operand ImmOp, string asmop>
4006       : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4007                                 (outs GPR64xsp:$wb),
4008                                 (ins GPR64xsp:$Rn, ImmTy:$amt,
4009                                     VList:$Rt, ImmOp:$lane),
4010                                 asmop # "\t$Rt[$lane], [$Rn], $amt",
4011                                 [],
4012                                 NoItinerary> {
4013     let Rm = 0b11111;
4014   }
4015
4016   class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4017                        Operand ImmTy, Operand ImmOp, string asmop>
4018       : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4019                                 (outs GPR64xsp:$wb),
4020                                 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
4021                                     ImmOp:$lane),
4022                                 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4023                                 [],
4024                                 NoItinerary>;
4025 }
4026
4027 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4028                            Operand uimm_b, Operand uimm_h,
4029                            Operand uimm_s, Operand uimm_d> {
4030   def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4031                                !cast<RegisterOperand>(List # "B_operand"),
4032                                uimm_b, neon_uimm4_bare, asmop> {
4033     let Inst{12-10} = lane{2-0};
4034     let Inst{30} = lane{3};
4035   }
4036
4037   def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4038                                    !cast<RegisterOperand>(List # "B_operand"),
4039                                    uimm_b, neon_uimm4_bare, asmop> {
4040     let Inst{12-10} = lane{2-0};
4041     let Inst{30} = lane{3};
4042   }
4043
4044   def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4045                                !cast<RegisterOperand>(List # "H_operand"),
4046                                uimm_h, neon_uimm3_bare, asmop> {
4047     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4048     let Inst{30} = lane{2};
4049   }
4050
4051   def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4052                                    !cast<RegisterOperand>(List # "H_operand"),
4053                                    uimm_h, neon_uimm3_bare, asmop> {
4054     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4055     let Inst{30} = lane{2};
4056   }
4057
4058   def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4059                                !cast<RegisterOperand>(List # "S_operand"),
4060                                uimm_s, neon_uimm2_bare, asmop> {
4061     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4062     let Inst{30} = lane{1};
4063   }
4064
4065   def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4066                                    !cast<RegisterOperand>(List # "S_operand"),
4067                                    uimm_s, neon_uimm2_bare, asmop> {
4068     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4069     let Inst{30} = lane{1};
4070   }
4071
4072   def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4073                                !cast<RegisterOperand>(List # "D_operand"),
4074                                uimm_d, neon_uimm1_bare, asmop> {
4075     let Inst{12-10} = 0b001;
4076     let Inst{30} = lane{0};
4077   }
4078
4079   def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4080                                    !cast<RegisterOperand>(List # "D_operand"),
4081                                    uimm_d, neon_uimm1_bare, asmop> {
4082     let Inst{12-10} = 0b001;
4083     let Inst{30} = lane{0};
4084   }
4085 }
4086
4087 // Post-index store single 1-element structure from one lane of 1 register.
4088 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4089                                 uimm_exact2, uimm_exact4, uimm_exact8>;
4090
4091 // Post-index store single N-element structure from one lane of N consecutive
4092 // registers (N = 2,3,4)
4093 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4094                                 uimm_exact4, uimm_exact8, uimm_exact16>;
4095 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4096                                 uimm_exact6, uimm_exact12, uimm_exact24>;
4097 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4098                                 uimm_exact8, uimm_exact16, uimm_exact32>;
4099
4100 // End of post-index load/store single N-element instructions
4101 // (class SIMD lsone-post)
4102
4103 // Neon Scalar instructions implementation
4104 // Scalar Three Same
4105
4106 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4107                              RegisterClass FPRC>
4108   : NeonI_Scalar3Same<u, size, opcode,
4109                       (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4110                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4111                       [],
4112                       NoItinerary>;
4113
4114 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4115   : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4116
4117 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4118                                       bit Commutable = 0> {
4119   let isCommutable = Commutable in {
4120     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4121     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4122   }
4123 }
4124
4125 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4126                                       string asmop, bit Commutable = 0> {
4127   let isCommutable = Commutable in {
4128     def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4129     def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4130   }
4131 }
4132
4133 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4134                                         string asmop, bit Commutable = 0> {
4135   let isCommutable = Commutable in {
4136     def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4137     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4138     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4139     def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4140   }
4141 }
4142
4143 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4144                                             Instruction INSTD> {
4145   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4146             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4147 }
4148
4149 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4150                                                Instruction INSTB,
4151                                                Instruction INSTH,
4152                                                Instruction INSTS,
4153                                                Instruction INSTD>
4154   : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4155   def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4156            (INSTB FPR8:$Rn, FPR8:$Rm)>;
4157
4158   def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4159            (INSTH FPR16:$Rn, FPR16:$Rm)>;
4160
4161   def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4162            (INSTS FPR32:$Rn, FPR32:$Rm)>;
4163 }
4164
4165 class Neon_Scalar3Same_cmp_D_size_patterns<SDPatternOperator opnode,
4166                                            Instruction INSTD>
4167   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4168         (INSTD FPR64:$Rn, FPR64:$Rm)>;
4169
4170 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4171                                              Instruction INSTH,
4172                                              Instruction INSTS> {
4173   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4174             (INSTH FPR16:$Rn, FPR16:$Rm)>;
4175   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4176             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4177 }
4178
4179 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4180                                              Instruction INSTS,
4181                                              Instruction INSTD> {
4182   def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
4183             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4184   def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4185             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4186 }
4187
4188 multiclass Neon_Scalar3Same_cmp_SD_size_patterns<SDPatternOperator opnode,
4189                                                  Instruction INSTS,
4190                                                  Instruction INSTD> {
4191   def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
4192             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4193   def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4194             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4195 }
4196
4197 class Neon_Scalar3Same_cmp_V1_D_size_patterns<CondCode CC,
4198                                               Instruction INSTD>
4199   : Pat<(v1i64 (Neon_cmp (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm), CC)),
4200         (INSTD FPR64:$Rn, FPR64:$Rm)>;
4201
4202 // Scalar Three Different
4203
4204 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4205                              RegisterClass FPRCD, RegisterClass FPRCS>
4206   : NeonI_Scalar3Diff<u, size, opcode,
4207                       (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4208                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4209                       [],
4210                       NoItinerary>;
4211
4212 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4213   def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4214   def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4215 }
4216
4217 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4218   let Constraints = "$Src = $Rd" in {
4219     def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4220                        (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4221                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4222                        [],
4223                        NoItinerary>;
4224     def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4225                        (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4226                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4227                        [],
4228                        NoItinerary>;
4229   }
4230 }
4231
4232 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4233                                              Instruction INSTH,
4234                                              Instruction INSTS> {
4235   def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4236             (INSTH FPR16:$Rn, FPR16:$Rm)>;
4237   def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4238             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4239 }
4240
4241 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4242                                              Instruction INSTH,
4243                                              Instruction INSTS> {
4244   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4245             (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4246   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4247             (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4248 }
4249
4250 // Scalar Two Registers Miscellaneous
4251
4252 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4253                              RegisterClass FPRCD, RegisterClass FPRCS>
4254   : NeonI_Scalar2SameMisc<u, size, opcode,
4255                           (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4256                           !strconcat(asmop, "\t$Rd, $Rn"),
4257                           [],
4258                           NoItinerary>;
4259
4260 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4261                                          string asmop> {
4262   def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4263                                       FPR32>;
4264   def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4265                                       FPR64>;
4266 }
4267
4268 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4269   def dd : NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4270 }
4271
4272 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4273   : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4274   def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4275   def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4276   def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4277 }
4278
4279 class NeonI_Scalar2SameMisc_fcvtxn_D_size<bit u, bits<5> opcode, string asmop>
4280   : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR32, FPR64>;
4281
4282 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4283                                                  string asmop> {
4284   def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4285   def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4286   def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4287 }
4288
4289 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4290                                        string asmop, RegisterClass FPRC>
4291   : NeonI_Scalar2SameMisc<u, size, opcode,
4292                           (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4293                           !strconcat(asmop, "\t$Rd, $Rn"),
4294                           [],
4295                           NoItinerary>;
4296
4297 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4298                                                  string asmop> {
4299
4300   let Constraints = "$Src = $Rd" in {
4301     def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4302     def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4303     def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4304     def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4305   }
4306 }
4307
4308 class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<SDPatternOperator opnode,
4309                                                   Instruction INSTD>
4310   : Pat<(f32 (opnode (f64 FPR64:$Rn))),
4311         (INSTD FPR64:$Rn)>;
4312
4313 multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns<SDPatternOperator opnode,
4314                                                       Instruction INSTS,
4315                                                       Instruction INSTD> {
4316   def : Pat<(v1i32 (opnode (f32 FPR32:$Rn))),
4317             (INSTS FPR32:$Rn)>;
4318   def : Pat<(v1i64 (opnode (f64 FPR64:$Rn))),
4319             (INSTD FPR64:$Rn)>;
4320 }
4321
4322 class Neon_Scalar2SameMisc_vcvt_D_size_patterns<SDPatternOperator opnode,
4323                                                 Instruction INSTD>
4324   : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
4325             (INSTD FPR64:$Rn)>;
4326
4327 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator opnode,
4328                                                      Instruction INSTS,
4329                                                      Instruction INSTD> {
4330   def : Pat<(f32 (opnode (v1i32 FPR32:$Rn))),
4331             (INSTS FPR32:$Rn)>;
4332   def : Pat<(f64 (opnode (v1i64 FPR64:$Rn))),
4333             (INSTD FPR64:$Rn)>;
4334 }
4335
4336 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4337                                                  Instruction INSTS,
4338                                                  Instruction INSTD> {
4339   def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn))),
4340             (INSTS FPR32:$Rn)>;
4341   def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4342             (INSTD FPR64:$Rn)>;
4343 }
4344
4345 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4346   : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4347                           (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4348                           !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4349                           [],
4350                           NoItinerary>;
4351
4352 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4353                                               string asmop> {
4354   def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4355                            (outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
4356                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4357                            [],
4358                            NoItinerary>;
4359   def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4360                            (outs FPR64:$Rd), (ins FPR64:$Rn, fpz32:$FPImm),
4361                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4362                            [],
4363                            NoItinerary>;
4364 }
4365
4366 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4367                                                 Instruction INSTD>
4368   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4369                        (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4370         (INSTD FPR64:$Rn, 0)>;
4371
4372 class Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<CondCode CC,
4373                                                    Instruction INSTD>
4374   : Pat<(v1i64 (Neon_cmpz (v1i64 FPR64:$Rn),
4375                           (i32 neon_uimm0:$Imm), CC)),
4376         (INSTD FPR64:$Rn, neon_uimm0:$Imm)>;
4377
4378 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4379                                                       Instruction INSTS,
4380                                                       Instruction INSTD> {
4381   def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn),
4382                            (v1f32 (scalar_to_vector (f32 fpz32:$FPImm))))),
4383             (INSTS FPR32:$Rn, fpz32:$FPImm)>;
4384   def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn),
4385                            (v1f32 (scalar_to_vector (f32 fpz32:$FPImm))))),
4386             (INSTD FPR64:$Rn, fpz32:$FPImm)>;
4387 }
4388
4389 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4390                                                 Instruction INSTD> {
4391   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4392             (INSTD FPR64:$Rn)>;
4393 }
4394
4395 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4396                                                    Instruction INSTB,
4397                                                    Instruction INSTH,
4398                                                    Instruction INSTS,
4399                                                    Instruction INSTD>
4400   : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4401   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4402             (INSTB FPR8:$Rn)>;
4403   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4404             (INSTH FPR16:$Rn)>;
4405   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4406             (INSTS FPR32:$Rn)>;
4407 }
4408
4409 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4410                                                        SDPatternOperator opnode,
4411                                                        Instruction INSTH,
4412                                                        Instruction INSTS,
4413                                                        Instruction INSTD> {
4414   def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4415             (INSTH FPR16:$Rn)>;
4416   def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4417             (INSTS FPR32:$Rn)>;
4418   def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4419             (INSTD FPR64:$Rn)>;
4420
4421 }
4422
4423 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4424                                                        SDPatternOperator opnode,
4425                                                        Instruction INSTB,
4426                                                        Instruction INSTH,
4427                                                        Instruction INSTS,
4428                                                        Instruction INSTD> {
4429   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4430             (INSTB FPR8:$Src, FPR8:$Rn)>;
4431   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4432             (INSTH FPR16:$Src, FPR16:$Rn)>;
4433   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4434             (INSTS FPR32:$Src, FPR32:$Rn)>;
4435   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4436             (INSTD FPR64:$Src, FPR64:$Rn)>;
4437 }
4438
4439 // Scalar Shift By Immediate
4440
4441 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4442                                 RegisterClass FPRC, Operand ImmTy>
4443   : NeonI_ScalarShiftImm<u, opcode,
4444                          (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4445                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4446                          [], NoItinerary>;
4447
4448 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4449                                             string asmop> {
4450   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4451     bits<6> Imm;
4452     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4453     let Inst{21-16} = Imm;
4454   }
4455 }
4456
4457 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4458                                                string asmop>
4459   : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4460   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4461     bits<3> Imm;
4462     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4463     let Inst{18-16} = Imm;
4464   }
4465   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4466     bits<4> Imm;
4467     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4468     let Inst{19-16} = Imm;
4469   }
4470   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4471     bits<5> Imm;
4472     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4473     let Inst{20-16} = Imm;
4474   }
4475 }
4476
4477 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4478                                             string asmop> {
4479   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4480     bits<6> Imm;
4481     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4482     let Inst{21-16} = Imm;
4483   }
4484 }
4485
4486 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4487                                               string asmop>
4488   : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4489   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4490     bits<3> Imm;
4491     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4492     let Inst{18-16} = Imm;
4493   }
4494   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4495     bits<4> Imm;
4496     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4497     let Inst{19-16} = Imm;
4498   }
4499   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4500     bits<5> Imm;
4501     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4502     let Inst{20-16} = Imm;
4503   }
4504 }
4505
4506 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4507   : NeonI_ScalarShiftImm<u, opcode,
4508                          (outs FPR64:$Rd),
4509                          (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4510                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4511                          [], NoItinerary> {
4512     bits<6> Imm;
4513     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4514     let Inst{21-16} = Imm;
4515     let Constraints = "$Src = $Rd";
4516 }
4517
4518 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4519   : NeonI_ScalarShiftImm<u, opcode,
4520                          (outs FPR64:$Rd),
4521                          (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4522                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4523                          [], NoItinerary> {
4524     bits<6> Imm;
4525     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4526     let Inst{21-16} = Imm;
4527     let Constraints = "$Src = $Rd";
4528 }
4529
4530 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4531                                        RegisterClass FPRCD, RegisterClass FPRCS,
4532                                        Operand ImmTy>
4533   : NeonI_ScalarShiftImm<u, opcode,
4534                          (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4535                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4536                          [], NoItinerary>;
4537
4538 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4539                                                 string asmop> {
4540   def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4541                                              shr_imm8> {
4542     bits<3> Imm;
4543     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4544     let Inst{18-16} = Imm;
4545   }
4546   def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4547                                              shr_imm16> {
4548     bits<4> Imm;
4549     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4550     let Inst{19-16} = Imm;
4551   }
4552   def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4553                                              shr_imm32> {
4554     bits<5> Imm;
4555     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4556     let Inst{20-16} = Imm;
4557   }
4558 }
4559
4560 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4561   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4562     bits<5> Imm;
4563     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4564     let Inst{20-16} = Imm;
4565   }
4566   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4567     bits<6> Imm;
4568     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4569     let Inst{21-16} = Imm;
4570   }
4571 }
4572
4573 multiclass Neon_ScalarShiftRImm_D_size_patterns<SDPatternOperator opnode,
4574                                                Instruction INSTD> {
4575   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4576                 (INSTD FPR64:$Rn, imm:$Imm)>;
4577 }
4578
4579 multiclass Neon_ScalarShiftLImm_D_size_patterns<SDPatternOperator opnode,
4580                                                Instruction INSTD> {
4581   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shl_imm64:$Imm))),
4582                 (INSTD FPR64:$Rn, imm:$Imm)>;
4583 }
4584
4585 class Neon_ScalarShiftImm_arm_D_size_patterns<SDPatternOperator opnode,
4586                                               Instruction INSTD>
4587   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4588             (v1i64 (Neon_vdup (i32 shr_imm64:$Imm))))),
4589         (INSTD FPR64:$Rn, imm:$Imm)>;
4590
4591 multiclass Neon_ScalarShiftLImm_BHSD_size_patterns<SDPatternOperator opnode,
4592                                                    Instruction INSTB,
4593                                                    Instruction INSTH,
4594                                                    Instruction INSTS,
4595                                                    Instruction INSTD>
4596   : Neon_ScalarShiftLImm_D_size_patterns<opnode, INSTD> {
4597   def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 shl_imm8:$Imm))),
4598                 (INSTB FPR8:$Rn, imm:$Imm)>;
4599   def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 shl_imm16:$Imm))),
4600                 (INSTH FPR16:$Rn, imm:$Imm)>;
4601   def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 shl_imm32:$Imm))),
4602                 (INSTS FPR32:$Rn, imm:$Imm)>;
4603 }
4604
4605 class Neon_ScalarShiftLImm_accum_D_size_patterns<SDPatternOperator opnode,
4606                                                 Instruction INSTD>
4607   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4608             (i32 shl_imm64:$Imm))),
4609         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4610
4611 class Neon_ScalarShiftRImm_accum_D_size_patterns<SDPatternOperator opnode,
4612                                                 Instruction INSTD>
4613   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4614             (i32 shr_imm64:$Imm))),
4615         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4616
4617 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4618                                                        SDPatternOperator opnode,
4619                                                        Instruction INSTH,
4620                                                        Instruction INSTS,
4621                                                        Instruction INSTD> {
4622   def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 shr_imm16:$Imm))),
4623                 (INSTH FPR16:$Rn, imm:$Imm)>;
4624   def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4625                 (INSTS FPR32:$Rn, imm:$Imm)>;
4626   def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4627                 (INSTD FPR64:$Rn, imm:$Imm)>;
4628 }
4629
4630 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator opnode,
4631                                                       Instruction INSTS,
4632                                                       Instruction INSTD> {
4633   def ssi : Pat<(f32 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4634                 (INSTS FPR32:$Rn, imm:$Imm)>;
4635   def ddi : Pat<(f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4636                 (INSTD FPR64:$Rn, imm:$Imm)>;
4637 }
4638
4639 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator opnode,
4640                                                       Instruction INSTS,
4641                                                       Instruction INSTD> {
4642   def ssi : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4643                 (INSTS FPR32:$Rn, imm:$Imm)>;
4644   def ddi : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4645                 (INSTD FPR64:$Rn, imm:$Imm)>;
4646 }
4647
4648 // Scalar Signed Shift Right (Immediate)
4649 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4650 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4651 // Pattern to match llvm.arm.* intrinsic.
4652 def : Neon_ScalarShiftImm_arm_D_size_patterns<sra, SSHRddi>;
4653
4654 // Scalar Unsigned Shift Right (Immediate)
4655 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4656 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4657 // Pattern to match llvm.arm.* intrinsic.
4658 def : Neon_ScalarShiftImm_arm_D_size_patterns<srl, USHRddi>;
4659
4660 // Scalar Signed Rounding Shift Right (Immediate)
4661 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4662 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4663
4664 // Scalar Unigned Rounding Shift Right (Immediate)
4665 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4666 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4667
4668 // Scalar Signed Shift Right and Accumulate (Immediate)
4669 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4670 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4671           <int_aarch64_neon_vsrads_n, SSRA>;
4672
4673 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4674 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4675 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4676           <int_aarch64_neon_vsradu_n, USRA>;
4677
4678 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4679 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4680 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4681           <int_aarch64_neon_vrsrads_n, SRSRA>;
4682
4683 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4684 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4685 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4686           <int_aarch64_neon_vrsradu_n, URSRA>;
4687
4688 // Scalar Shift Left (Immediate)
4689 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4690 defm : Neon_ScalarShiftLImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4691 // Pattern to match llvm.arm.* intrinsic.
4692 def : Neon_ScalarShiftImm_arm_D_size_patterns<shl, SHLddi>;
4693
4694 // Signed Saturating Shift Left (Immediate)
4695 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4696 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4697                                                SQSHLbbi, SQSHLhhi,
4698                                                SQSHLssi, SQSHLddi>;
4699 // Pattern to match llvm.arm.* intrinsic.
4700 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4701
4702 // Unsigned Saturating Shift Left (Immediate)
4703 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4704 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4705                                                UQSHLbbi, UQSHLhhi,
4706                                                UQSHLssi, UQSHLddi>;
4707 // Pattern to match llvm.arm.* intrinsic.
4708 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4709
4710 // Signed Saturating Shift Left Unsigned (Immediate)
4711 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4712 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4713                                                SQSHLUbbi, SQSHLUhhi,
4714                                                SQSHLUssi, SQSHLUddi>;
4715
4716 // Shift Right And Insert (Immediate)
4717 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4718 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4719           <int_aarch64_neon_vsri, SRI>;
4720
4721 // Shift Left And Insert (Immediate)
4722 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4723 def : Neon_ScalarShiftLImm_accum_D_size_patterns
4724           <int_aarch64_neon_vsli, SLI>;
4725
4726 // Signed Saturating Shift Right Narrow (Immediate)
4727 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4728 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4729                                                     SQSHRNbhi, SQSHRNhsi,
4730                                                     SQSHRNsdi>;
4731
4732 // Unsigned Saturating Shift Right Narrow (Immediate)
4733 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4734 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4735                                                     UQSHRNbhi, UQSHRNhsi,
4736                                                     UQSHRNsdi>;
4737
4738 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4739 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4740 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4741                                                     SQRSHRNbhi, SQRSHRNhsi,
4742                                                     SQRSHRNsdi>;
4743
4744 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4745 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4746 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4747                                                     UQRSHRNbhi, UQRSHRNhsi,
4748                                                     UQRSHRNsdi>;
4749
4750 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4751 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4752 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4753                                                     SQSHRUNbhi, SQSHRUNhsi,
4754                                                     SQSHRUNsdi>;
4755
4756 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4757 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4758 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4759                                                     SQRSHRUNbhi, SQRSHRUNhsi,
4760                                                     SQRSHRUNsdi>;
4761
4762 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4763 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4764 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxs2fp_n,
4765                                                   SCVTF_Nssi, SCVTF_Nddi>;
4766
4767 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4768 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4769 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxu2fp_n,
4770                                                   UCVTF_Nssi, UCVTF_Nddi>;
4771
4772 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4773 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4774 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxs_n,
4775                                                   FCVTZS_Nssi, FCVTZS_Nddi>;
4776
4777 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4778 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4779 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxu_n,
4780                                                   FCVTZU_Nssi, FCVTZU_Nddi>;
4781
4782 // Patterns For Convert Instructions Between v1f64 and v1i64
4783 class Neon_ScalarShiftImm_cvtf_v1f64_pattern<SDPatternOperator opnode,
4784                                              Instruction INST>
4785     : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4786           (INST FPR64:$Rn, imm:$Imm)>;
4787
4788 class Neon_ScalarShiftImm_fcvt_v1f64_pattern<SDPatternOperator opnode,
4789                                              Instruction INST>
4790     : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4791           (INST FPR64:$Rn, imm:$Imm)>;
4792
4793 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxs2fp,
4794                                              SCVTF_Nddi>;
4795
4796 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxu2fp,
4797                                              UCVTF_Nddi>;
4798
4799 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxs,
4800                                              FCVTZS_Nddi>;
4801
4802 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxu,
4803                                              FCVTZU_Nddi>;
4804
4805 // Scalar Integer Add
4806 let isCommutable = 1 in {
4807 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4808 }
4809
4810 // Scalar Integer Sub
4811 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4812
4813 // Pattern for Scalar Integer Add and Sub with D register only
4814 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4815 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4816
4817 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
4818 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
4819 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
4820 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
4821 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
4822
4823 // Scalar Integer Saturating Add (Signed, Unsigned)
4824 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
4825 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
4826
4827 // Scalar Integer Saturating Sub (Signed, Unsigned)
4828 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
4829 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
4830
4831
4832 // Patterns to match llvm.aarch64.* intrinsic for
4833 // Scalar Integer Saturating Add, Sub  (Signed, Unsigned)
4834 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
4835                                            SQADDhhh, SQADDsss, SQADDddd>;
4836 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
4837                                            UQADDhhh, UQADDsss, UQADDddd>;
4838 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
4839                                            SQSUBhhh, SQSUBsss, SQSUBddd>;
4840 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
4841                                            UQSUBhhh, UQSUBsss, UQSUBddd>;
4842
4843 // Scalar Integer Saturating Doubling Multiply Half High
4844 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
4845
4846 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4847 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
4848
4849 // Patterns to match llvm.arm.* intrinsic for
4850 // Scalar Integer Saturating Doubling Multiply Half High and
4851 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4852 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
4853                                                                SQDMULHsss>;
4854 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
4855                                                                 SQRDMULHsss>;
4856
4857 // Scalar Floating-point Multiply Extended
4858 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
4859
4860 // Scalar Floating-point Reciprocal Step
4861 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
4862
4863 // Scalar Floating-point Reciprocal Square Root Step
4864 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
4865
4866 // Patterns to match llvm.arm.* intrinsic for
4867 // Scalar Floating-point Reciprocal Step and
4868 // Scalar Floating-point Reciprocal Square Root Step
4869 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrecps, FRECPSsss,
4870                                                               FRECPSddd>;
4871 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrsqrts, FRSQRTSsss,
4872                                                                FRSQRTSddd>;
4873
4874 def : Pat<(v1f64 (fsqrt (v1f64 FPR64:$Rn))), (FSQRTdd FPR64:$Rn)>;
4875
4876 // Patterns to match llvm.aarch64.* intrinsic for
4877 // Scalar Floating-point Multiply Extended,
4878 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
4879                                                   Instruction INSTS,
4880                                                   Instruction INSTD> {
4881   def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4882             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4883   def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4884             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4885 }
4886
4887 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
4888                                               FMULXsss,FMULXddd>;
4889
4890 // Scalar Integer Shift Left (Signed, Unsigned)
4891 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
4892 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
4893
4894 // Patterns to match llvm.arm.* intrinsic for
4895 // Scalar Integer Shift Left (Signed, Unsigned)
4896 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
4897 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
4898
4899 // Patterns to match llvm.aarch64.* intrinsic for
4900 // Scalar Integer Shift Left (Signed, Unsigned)
4901 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
4902 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
4903
4904 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
4905 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
4906 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
4907
4908 // Patterns to match llvm.aarch64.* intrinsic for
4909 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
4910 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
4911                                            SQSHLhhh, SQSHLsss, SQSHLddd>;
4912 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
4913                                            UQSHLhhh, UQSHLsss, UQSHLddd>;
4914
4915 // Patterns to match llvm.arm.* intrinsic for
4916 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
4917 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
4918 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
4919
4920 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4921 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
4922 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
4923
4924 // Patterns to match llvm.aarch64.* intrinsic for
4925 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4926 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
4927 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
4928
4929 // Patterns to match llvm.arm.* intrinsic for
4930 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4931 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
4932 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
4933
4934 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4935 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
4936 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
4937
4938 // Patterns to match llvm.aarch64.* intrinsic for
4939 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4940 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
4941                                            SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
4942 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
4943                                            UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
4944
4945 // Patterns to match llvm.arm.* intrinsic for
4946 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4947 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
4948 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
4949
4950 // Signed Saturating Doubling Multiply-Add Long
4951 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
4952 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
4953                                             SQDMLALshh, SQDMLALdss>;
4954
4955 // Signed Saturating Doubling Multiply-Subtract Long
4956 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
4957 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
4958                                             SQDMLSLshh, SQDMLSLdss>;
4959
4960 // Signed Saturating Doubling Multiply Long
4961 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
4962 defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
4963                                          SQDMULLshh, SQDMULLdss>;
4964
4965 // Scalar Signed Integer Convert To Floating-point
4966 defm SCVTF  : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
4967 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fps,
4968                                                  SCVTFss, SCVTFdd>;
4969
4970 // Scalar Unsigned Integer Convert To Floating-point
4971 defm UCVTF  : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
4972 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fpu,
4973                                                  UCVTFss, UCVTFdd>;
4974
4975 // Scalar Floating-point Converts
4976 def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">;
4977 def : Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<int_aarch64_neon_fcvtxn,
4978                                                   FCVTXN>;
4979
4980 defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">;
4981 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtns,
4982                                                   FCVTNSss, FCVTNSdd>;
4983 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtns, FCVTNSdd>;
4984
4985 defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">;
4986 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtnu,
4987                                                   FCVTNUss, FCVTNUdd>;
4988 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtnu, FCVTNUdd>;
4989
4990 defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">;
4991 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtms,
4992                                                   FCVTMSss, FCVTMSdd>;
4993 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtms, FCVTMSdd>;
4994
4995 defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">;
4996 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtmu,
4997                                                   FCVTMUss, FCVTMUdd>;
4998 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtmu, FCVTMUdd>;
4999
5000 defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">;
5001 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtas,
5002                                                   FCVTASss, FCVTASdd>;
5003 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtas, FCVTASdd>;
5004
5005 defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">;
5006 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtau,
5007                                                   FCVTAUss, FCVTAUdd>;
5008 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtau, FCVTAUdd>;
5009
5010 defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">;
5011 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtps,
5012                                                   FCVTPSss, FCVTPSdd>;
5013 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtps, FCVTPSdd>;
5014
5015 defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">;
5016 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtpu,
5017                                                   FCVTPUss, FCVTPUdd>;
5018 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtpu, FCVTPUdd>;
5019
5020 defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">;
5021 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzs,
5022                                                   FCVTZSss, FCVTZSdd>;
5023 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzs,
5024                                                 FCVTZSdd>;
5025
5026 defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">;
5027 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzu,
5028                                                   FCVTZUss, FCVTZUdd>;
5029 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzu,
5030                                                 FCVTZUdd>;
5031
5032 // Patterns For Convert Instructions Between v1f64 and v1i64
5033 class Neon_Scalar2SameMisc_cvtf_v1f64_pattern<SDPatternOperator opnode,
5034                                               Instruction INST>
5035     : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5036
5037 class Neon_Scalar2SameMisc_fcvt_v1f64_pattern<SDPatternOperator opnode,
5038                                               Instruction INST>
5039     : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5040
5041 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<sint_to_fp, SCVTFdd>;
5042 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<uint_to_fp, UCVTFdd>;
5043
5044 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_sint, FCVTZSdd>;
5045 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_uint, FCVTZUdd>;
5046
5047 // Scalar Floating-point Reciprocal Estimate
5048 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
5049 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrecpe,
5050                                              FRECPEss, FRECPEdd>;
5051
5052 // Scalar Floating-point Reciprocal Exponent
5053 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
5054 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
5055                                              FRECPXss, FRECPXdd>;
5056
5057 // Scalar Floating-point Reciprocal Square Root Estimate
5058 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
5059 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrsqrte,
5060                                              FRSQRTEss, FRSQRTEdd>;
5061
5062 // Scalar Floating-point Round
5063 class Neon_ScalarFloatRound_pattern<SDPatternOperator opnode, Instruction INST>
5064     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5065
5066 def : Neon_ScalarFloatRound_pattern<fceil, FRINTPdd>;
5067 def : Neon_ScalarFloatRound_pattern<ffloor, FRINTMdd>;
5068 def : Neon_ScalarFloatRound_pattern<ftrunc, FRINTZdd>;
5069 def : Neon_ScalarFloatRound_pattern<frint, FRINTXdd>;
5070 def : Neon_ScalarFloatRound_pattern<fnearbyint, FRINTIdd>;
5071 def : Neon_ScalarFloatRound_pattern<frnd, FRINTAdd>;
5072 def : Neon_ScalarFloatRound_pattern<int_aarch64_neon_frintn, FRINTNdd>;
5073
5074 // Scalar Integer Compare
5075
5076 // Scalar Compare Bitwise Equal
5077 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
5078 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
5079
5080 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
5081                                               Instruction INSTD,
5082                                               CondCode CC>
5083   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
5084         (INSTD FPR64:$Rn, FPR64:$Rm)>;
5085
5086 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
5087
5088 // Scalar Compare Signed Greather Than Or Equal
5089 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
5090 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
5091 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGEddd, SETGE>;
5092
5093 // Scalar Compare Unsigned Higher Or Same
5094 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
5095 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
5096 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHSddd, SETUGE>;
5097
5098 // Scalar Compare Unsigned Higher
5099 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
5100 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
5101 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHIddd, SETUGT>;
5102
5103 // Scalar Compare Signed Greater Than
5104 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
5105 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
5106 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGTddd, SETGT>;
5107
5108 // Scalar Compare Bitwise Test Bits
5109 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
5110 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
5111 def : Neon_Scalar3Same_cmp_D_size_patterns<Neon_tst, CMTSTddd>;
5112
5113 // Scalar Compare Bitwise Equal To Zero
5114 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5115 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5116                                                 CMEQddi>;
5117 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETEQ, CMEQddi>;
5118
5119 // Scalar Compare Signed Greather Than Or Equal To Zero
5120 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5121 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5122                                                 CMGEddi>;
5123 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGE, CMGEddi>;
5124
5125 // Scalar Compare Signed Greater Than Zero
5126 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5127 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5128                                                 CMGTddi>;
5129 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGT, CMGTddi>;
5130
5131 // Scalar Compare Signed Less Than Or Equal To Zero
5132 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5133 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5134                                                 CMLEddi>;
5135 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLE, CMLEddi>;
5136
5137 // Scalar Compare Less Than Zero
5138 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5139 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5140                                                 CMLTddi>;
5141 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLT, CMLTddi>;
5142
5143 // Scalar Floating-point Compare
5144
5145 // Scalar Floating-point Compare Mask Equal
5146 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5147 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vceq,
5148                                              FCMEQsss, FCMEQddd>;
5149 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETEQ, FCMEQddd>;
5150
5151 // Scalar Floating-point Compare Mask Equal To Zero
5152 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5153 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vceq,
5154                                                   FCMEQZssi, FCMEQZddi>;
5155 def : Pat<(v1i64 (Neon_cmpz (v1f64 FPR64:$Rn), (f32 fpz32:$FPImm), SETEQ)),
5156           (FCMEQZddi FPR64:$Rn, fpz32:$FPImm)>;
5157
5158 // Scalar Floating-point Compare Mask Greater Than Or Equal
5159 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5160 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcge,
5161                                              FCMGEsss, FCMGEddd>;
5162 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGE, FCMGEddd>;
5163
5164 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5165 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5166 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcge,
5167                                                   FCMGEZssi, FCMGEZddi>;
5168
5169 // Scalar Floating-point Compare Mask Greather Than
5170 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5171 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcgt,
5172                                              FCMGTsss, FCMGTddd>;
5173 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGT, FCMGTddd>;
5174
5175 // Scalar Floating-point Compare Mask Greather Than Zero
5176 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5177 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcgt,
5178                                                   FCMGTZssi, FCMGTZddi>;
5179
5180 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5181 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5182 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vclez,
5183                                                   FCMLEZssi, FCMLEZddi>;
5184
5185 // Scalar Floating-point Compare Mask Less Than Zero
5186 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5187 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcltz,
5188                                                   FCMLTZssi, FCMLTZddi>;
5189
5190 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5191 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5192 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcage,
5193                                              FACGEsss, FACGEddd>;
5194
5195 // Scalar Floating-point Absolute Compare Mask Greater Than
5196 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5197 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcagt,
5198                                              FACGTsss, FACGTddd>;
5199
5200 // Scakar Floating-point Absolute Difference
5201 defm FABD: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11010, "fabd">;
5202 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vabd,
5203                                          FABDsss, FABDddd>;
5204
5205 // Scalar Absolute Value
5206 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5207 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5208
5209 // Scalar Signed Saturating Absolute Value
5210 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5211 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5212                                                SQABSbb, SQABShh, SQABSss, SQABSdd>;
5213
5214 // Scalar Negate
5215 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5216 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5217
5218 // Scalar Signed Saturating Negate
5219 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5220 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5221                                                SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5222
5223 // Scalar Signed Saturating Accumulated of Unsigned Value
5224 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5225 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5226                                                      SUQADDbb, SUQADDhh,
5227                                                      SUQADDss, SUQADDdd>;
5228
5229 // Scalar Unsigned Saturating Accumulated of Signed Value
5230 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5231 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5232                                                      USQADDbb, USQADDhh,
5233                                                      USQADDss, USQADDdd>;
5234
5235 def : Pat<(v1i64 (int_aarch64_neon_suqadd (v1i64 FPR64:$Src),
5236                                           (v1i64 FPR64:$Rn))),
5237           (SUQADDdd FPR64:$Src, FPR64:$Rn)>;
5238
5239 def : Pat<(v1i64 (int_aarch64_neon_usqadd (v1i64 FPR64:$Src),
5240                                           (v1i64 FPR64:$Rn))),
5241           (USQADDdd FPR64:$Src, FPR64:$Rn)>;
5242
5243 def : Pat<(v1i64 (int_arm_neon_vabs (v1i64 FPR64:$Rn))),
5244           (ABSdd FPR64:$Rn)>;
5245
5246 def : Pat<(v1i64 (int_arm_neon_vqabs (v1i64 FPR64:$Rn))),
5247           (SQABSdd FPR64:$Rn)>;
5248
5249 def : Pat<(v1i64 (int_arm_neon_vqneg (v1i64 FPR64:$Rn))),
5250           (SQNEGdd FPR64:$Rn)>;
5251
5252 def : Pat<(v1i64 (sub (v1i64 (bitconvert (v8i8 Neon_AllZero))),
5253                       (v1i64 FPR64:$Rn))),
5254           (NEGdd FPR64:$Rn)>;
5255
5256 // Scalar Signed Saturating Extract Unsigned Narrow
5257 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5258 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5259                                                      SQXTUNbh, SQXTUNhs,
5260                                                      SQXTUNsd>;
5261
5262 // Scalar Signed Saturating Extract Narrow
5263 defm SQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5264 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5265                                                      SQXTNbh, SQXTNhs,
5266                                                      SQXTNsd>;
5267
5268 // Scalar Unsigned Saturating Extract Narrow
5269 defm UQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5270 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5271                                                      UQXTNbh, UQXTNhs,
5272                                                      UQXTNsd>;
5273
5274 // Scalar Reduce Pairwise
5275
5276 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5277                                      string asmop, bit Commutable = 0> {
5278   let isCommutable = Commutable in {
5279     def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5280                                 (outs FPR64:$Rd), (ins VPR128:$Rn),
5281                                 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5282                                 [],
5283                                 NoItinerary>;
5284   }
5285 }
5286
5287 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5288                                      string asmop, bit Commutable = 0>
5289   : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5290   let isCommutable = Commutable in {
5291     def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5292                                 (outs FPR32:$Rd), (ins VPR64:$Rn),
5293                                 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5294                                 [],
5295                                 NoItinerary>;
5296   }
5297 }
5298
5299 // Scalar Reduce Addition Pairwise (Integer) with
5300 // Pattern to match llvm.arm.* intrinsic
5301 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5302
5303 // Pattern to match llvm.aarch64.* intrinsic for
5304 // Scalar Reduce Addition Pairwise (Integer)
5305 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5306           (ADDPvv_D_2D VPR128:$Rn)>;
5307 def : Pat<(v1i64 (int_aarch64_neon_vaddv (v2i64 VPR128:$Rn))),
5308           (ADDPvv_D_2D VPR128:$Rn)>;
5309
5310 // Scalar Reduce Addition Pairwise (Floating Point)
5311 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5312
5313 // Scalar Reduce Maximum Pairwise (Floating Point)
5314 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5315
5316 // Scalar Reduce Minimum Pairwise (Floating Point)
5317 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5318
5319 // Scalar Reduce maxNum Pairwise (Floating Point)
5320 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5321
5322 // Scalar Reduce minNum Pairwise (Floating Point)
5323 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5324
5325 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnode,
5326                                             Instruction INSTS,
5327                                             Instruction INSTD> {
5328   def : Pat<(f32 (opnode (v2f32 VPR64:$Rn))),
5329             (INSTS VPR64:$Rn)>;
5330   def : Pat<(f64 (opnode (v2f64 VPR128:$Rn))),
5331             (INSTD VPR128:$Rn)>;
5332 }
5333
5334 // Patterns to match llvm.aarch64.* intrinsic for
5335 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5336 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5337                                         FADDPvv_S_2S, FADDPvv_D_2D>;
5338
5339 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5340                                         FMAXPvv_S_2S, FMAXPvv_D_2D>;
5341
5342 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5343                                         FMINPvv_S_2S, FMINPvv_D_2D>;
5344
5345 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5346                                         FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5347
5348 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5349                                         FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5350
5351 def : Pat<(f32 (int_aarch64_neon_vpfadd (v4f32 VPR128:$Rn))),
5352           (FADDPvv_S_2S (v2f32
5353                (EXTRACT_SUBREG
5354                    (v4f32 (FADDP_4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rn))),
5355                    sub_64)))>;
5356
5357 // Scalar by element Arithmetic
5358
5359 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5360                                     string rmlane, bit u, bit szhi, bit szlo,
5361                                     RegisterClass ResFPR, RegisterClass OpFPR,
5362                                     RegisterOperand OpVPR, Operand OpImm>
5363   : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5364                              (outs ResFPR:$Rd),
5365                              (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5366                              asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5367                              [],
5368                              NoItinerary> {
5369   bits<3> Imm;
5370   bits<5> MRm;
5371 }
5372
5373 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5374                                                     string rmlane,
5375                                                     bit u, bit szhi, bit szlo,
5376                                                     RegisterClass ResFPR,
5377                                                     RegisterClass OpFPR,
5378                                                     RegisterOperand OpVPR,
5379                                                     Operand OpImm>
5380   : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5381                              (outs ResFPR:$Rd),
5382                              (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5383                              asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5384                              [],
5385                              NoItinerary> {
5386   let Constraints = "$src = $Rd";
5387   bits<3> Imm;
5388   bits<5> MRm;
5389 }
5390
5391 // Scalar Floating Point  multiply (scalar, by element)
5392 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5393   0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5394   let Inst{11} = Imm{1}; // h
5395   let Inst{21} = Imm{0}; // l
5396   let Inst{20-16} = MRm;
5397 }
5398 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5399   0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5400   let Inst{11} = Imm{0}; // h
5401   let Inst{21} = 0b0;    // l
5402   let Inst{20-16} = MRm;
5403 }
5404
5405 // Scalar Floating Point  multiply extended (scalar, by element)
5406 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5407   0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5408   let Inst{11} = Imm{1}; // h
5409   let Inst{21} = Imm{0}; // l
5410   let Inst{20-16} = MRm;
5411 }
5412 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5413   0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5414   let Inst{11} = Imm{0}; // h
5415   let Inst{21} = 0b0;    // l
5416   let Inst{20-16} = MRm;
5417 }
5418
5419 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5420   SDPatternOperator opnode,
5421   Instruction INST,
5422   ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5423   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5424
5425   def  : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5426                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5427              (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5428
5429   def  : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5430                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5431              (ResTy (INST (ResTy FPRC:$Rn),
5432                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5433                OpNImm:$Imm))>;
5434
5435   // swapped operands
5436   def  : Pat<(ResTy (opnode
5437                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5438                (ResTy FPRC:$Rn))),
5439              (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5440
5441   def  : Pat<(ResTy (opnode
5442                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5443                (ResTy FPRC:$Rn))),
5444              (ResTy (INST (ResTy FPRC:$Rn),
5445                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5446                OpNImm:$Imm))>;
5447 }
5448
5449 // Patterns for Scalar Floating Point  multiply (scalar, by element)
5450 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5451   f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5452 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5453   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5454
5455 // Patterns for Scalar Floating Point  multiply extended (scalar, by element)
5456 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5457   FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5458   v2f32, v4f32, neon_uimm1_bare>;
5459 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5460   FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5461   v1f64, v2f64, neon_uimm0_bare>;
5462
5463
5464 // Scalar Floating Point fused multiply-add (scalar, by element)
5465 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5466   0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5467   let Inst{11} = Imm{1}; // h
5468   let Inst{21} = Imm{0}; // l
5469   let Inst{20-16} = MRm;
5470 }
5471 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5472   0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5473   let Inst{11} = Imm{0}; // h
5474   let Inst{21} = 0b0;    // l
5475   let Inst{20-16} = MRm;
5476 }
5477
5478 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5479 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5480   0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5481   let Inst{11} = Imm{1}; // h
5482   let Inst{21} = Imm{0}; // l
5483   let Inst{20-16} = MRm;
5484 }
5485 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5486   0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5487   let Inst{11} = Imm{0}; // h
5488   let Inst{21} = 0b0;    // l
5489   let Inst{20-16} = MRm;
5490 }
5491 // We are allowed to match the fma instruction regardless of compile options.
5492 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5493   Instruction FMLAI, Instruction FMLSI,
5494   ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5495   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5496   // fmla
5497   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5498                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5499                (ResTy FPRC:$Ra))),
5500              (ResTy (FMLAI (ResTy FPRC:$Ra),
5501                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5502
5503   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5504                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5505                (ResTy FPRC:$Ra))),
5506              (ResTy (FMLAI (ResTy FPRC:$Ra),
5507                (ResTy FPRC:$Rn),
5508                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5509                OpNImm:$Imm))>;
5510
5511   // swapped fmla operands
5512   def  : Pat<(ResTy (fma
5513                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5514                (ResTy FPRC:$Rn),
5515                (ResTy FPRC:$Ra))),
5516              (ResTy (FMLAI (ResTy FPRC:$Ra),
5517                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5518
5519   def  : Pat<(ResTy (fma
5520                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5521                (ResTy FPRC:$Rn),
5522                (ResTy FPRC:$Ra))),
5523              (ResTy (FMLAI (ResTy FPRC:$Ra),
5524                (ResTy FPRC:$Rn),
5525                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5526                OpNImm:$Imm))>;
5527
5528   // fmls
5529   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5530                (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5531                (ResTy FPRC:$Ra))),
5532              (ResTy (FMLSI (ResTy FPRC:$Ra),
5533                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5534
5535   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5536                (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5537                (ResTy FPRC:$Ra))),
5538              (ResTy (FMLSI (ResTy FPRC:$Ra),
5539                (ResTy FPRC:$Rn),
5540                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5541                OpNImm:$Imm))>;
5542
5543   // swapped fmls operands
5544   def  : Pat<(ResTy (fma
5545                (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5546                (ResTy FPRC:$Rn),
5547                (ResTy FPRC:$Ra))),
5548              (ResTy (FMLSI (ResTy FPRC:$Ra),
5549                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5550
5551   def  : Pat<(ResTy (fma
5552                (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5553                (ResTy FPRC:$Rn),
5554                (ResTy FPRC:$Ra))),
5555              (ResTy (FMLSI (ResTy FPRC:$Ra),
5556                (ResTy FPRC:$Rn),
5557                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5558                OpNImm:$Imm))>;
5559 }
5560
5561 // Scalar Floating Point fused multiply-add and
5562 // multiply-subtract (scalar, by element)
5563 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5564   f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5565 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5566   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5567 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5568   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5569
5570 // Scalar Signed saturating doubling multiply long (scalar, by element)
5571 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5572   0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5573   let Inst{11} = 0b0; // h
5574   let Inst{21} = Imm{1}; // l
5575   let Inst{20} = Imm{0}; // m
5576   let Inst{19-16} = MRm{3-0};
5577 }
5578 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5579   0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5580   let Inst{11} = Imm{2}; // h
5581   let Inst{21} = Imm{1}; // l
5582   let Inst{20} = Imm{0}; // m
5583   let Inst{19-16} = MRm{3-0};
5584 }
5585 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5586   0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5587   let Inst{11} = 0b0;    // h
5588   let Inst{21} = Imm{0}; // l
5589   let Inst{20-16} = MRm;
5590 }
5591 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5592   0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5593   let Inst{11} = Imm{1};    // h
5594   let Inst{21} = Imm{0};    // l
5595   let Inst{20-16} = MRm;
5596 }
5597
5598 multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
5599   SDPatternOperator opnode,
5600   Instruction INST,
5601   ValueType ResTy, RegisterClass FPRC,
5602   ValueType OpVTy, ValueType OpTy,
5603   ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5604
5605   def  : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
5606                (OpVTy (scalar_to_vector
5607                  (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
5608              (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5609
5610   //swapped operands
5611   def  : Pat<(ResTy (opnode
5612                (OpVTy (scalar_to_vector
5613                  (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
5614                  (OpVTy FPRC:$Rn))),
5615              (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5616 }
5617
5618
5619 // Patterns for Scalar Signed saturating doubling
5620 // multiply long (scalar, by element)
5621 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5622   SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
5623   i32, VPR64Lo, neon_uimm2_bare>;
5624 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5625   SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
5626   i32, VPR128Lo, neon_uimm3_bare>;
5627 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5628   SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
5629   i32, VPR64Lo, neon_uimm1_bare>;
5630 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5631   SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
5632   i32, VPR128Lo, neon_uimm2_bare>;
5633
5634 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5635 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5636   0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5637   let Inst{11} = 0b0; // h
5638   let Inst{21} = Imm{1}; // l
5639   let Inst{20} = Imm{0}; // m
5640   let Inst{19-16} = MRm{3-0};
5641 }
5642 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5643   0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5644   let Inst{11} = Imm{2}; // h
5645   let Inst{21} = Imm{1}; // l
5646   let Inst{20} = Imm{0}; // m
5647   let Inst{19-16} = MRm{3-0};
5648 }
5649 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5650   0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5651   let Inst{11} = 0b0;    // h
5652   let Inst{21} = Imm{0}; // l
5653   let Inst{20-16} = MRm;
5654 }
5655 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5656   0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5657   let Inst{11} = Imm{1};    // h
5658   let Inst{21} = Imm{0};    // l
5659   let Inst{20-16} = MRm;
5660 }
5661
5662 // Scalar Signed saturating doubling
5663 // multiply-subtract long (scalar, by element)
5664 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5665   0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5666   let Inst{11} = 0b0; // h
5667   let Inst{21} = Imm{1}; // l
5668   let Inst{20} = Imm{0}; // m
5669   let Inst{19-16} = MRm{3-0};
5670 }
5671 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5672   0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5673   let Inst{11} = Imm{2}; // h
5674   let Inst{21} = Imm{1}; // l
5675   let Inst{20} = Imm{0}; // m
5676   let Inst{19-16} = MRm{3-0};
5677 }
5678 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5679   0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5680   let Inst{11} = 0b0;    // h
5681   let Inst{21} = Imm{0}; // l
5682   let Inst{20-16} = MRm;
5683 }
5684 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5685   0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5686   let Inst{11} = Imm{1};    // h
5687   let Inst{21} = Imm{0};    // l
5688   let Inst{20-16} = MRm;
5689 }
5690
5691 multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
5692   SDPatternOperator opnode,
5693   SDPatternOperator coreopnode,
5694   Instruction INST,
5695   ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
5696   ValueType OpTy,
5697   ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5698
5699   def  : Pat<(ResTy (opnode
5700                (ResTy ResFPRC:$Ra),
5701                (ResTy (coreopnode (OpTy FPRC:$Rn),
5702                  (OpTy (scalar_to_vector
5703                    (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
5704              (ResTy (INST (ResTy ResFPRC:$Ra),
5705                (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5706
5707   // swapped operands
5708   def  : Pat<(ResTy (opnode
5709                (ResTy ResFPRC:$Ra),
5710                (ResTy (coreopnode
5711                  (OpTy (scalar_to_vector
5712                    (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
5713                  (OpTy FPRC:$Rn))))),
5714              (ResTy (INST (ResTy ResFPRC:$Ra),
5715                (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5716 }
5717
5718 // Patterns for Scalar Signed saturating
5719 // doubling multiply-add long (scalar, by element)
5720 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5721   int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5722   i32, VPR64Lo, neon_uimm2_bare>;
5723 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5724   int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5725   i32, VPR128Lo, neon_uimm3_bare>;
5726 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5727   int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5728   i32, VPR64Lo, neon_uimm1_bare>;
5729 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5730   int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5731   i32, VPR128Lo, neon_uimm2_bare>;
5732
5733 // Patterns for Scalar Signed saturating
5734 // doubling multiply-sub long (scalar, by element)
5735 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5736   int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5737   i32, VPR64Lo, neon_uimm2_bare>;
5738 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5739   int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5740   i32, VPR128Lo, neon_uimm3_bare>;
5741 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5742   int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5743   i32, VPR64Lo, neon_uimm1_bare>;
5744 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5745   int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5746   i32, VPR128Lo, neon_uimm2_bare>;
5747
5748 // Scalar general arithmetic operation
5749 class Neon_Scalar_GeneralMath2D_pattern<SDPatternOperator opnode,
5750                                         Instruction INST>
5751     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5752
5753 class Neon_Scalar_GeneralMath3D_pattern<SDPatternOperator opnode,
5754                                         Instruction INST>
5755     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5756           (INST FPR64:$Rn, FPR64:$Rm)>;
5757
5758 class Neon_Scalar_GeneralMath4D_pattern<SDPatternOperator opnode,
5759                                         Instruction INST>
5760     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm),
5761               (v1f64 FPR64:$Ra))),
5762           (INST FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
5763
5764 def : Neon_Scalar_GeneralMath3D_pattern<fadd, FADDddd>;
5765 def : Neon_Scalar_GeneralMath3D_pattern<fmul, FMULddd>;
5766 def : Neon_Scalar_GeneralMath3D_pattern<fsub, FSUBddd>;
5767 def : Neon_Scalar_GeneralMath3D_pattern<fdiv, FDIVddd>;
5768 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vabds, FABDddd>;
5769 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmaxs, FMAXddd>;
5770 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmins, FMINddd>;
5771 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vmaxnm, FMAXNMddd>;
5772 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vminnm, FMINNMddd>;
5773
5774 def : Neon_Scalar_GeneralMath2D_pattern<fabs, FABSdd>;
5775 def : Neon_Scalar_GeneralMath2D_pattern<fneg, FNEGdd>;
5776
5777 def : Neon_Scalar_GeneralMath4D_pattern<fma, FMADDdddd>;
5778 def : Neon_Scalar_GeneralMath4D_pattern<fmsub, FMSUBdddd>;
5779
5780 // Scalar Signed saturating doubling multiply returning
5781 // high half (scalar, by element)
5782 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5783   0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5784   let Inst{11} = 0b0; // h
5785   let Inst{21} = Imm{1}; // l
5786   let Inst{20} = Imm{0}; // m
5787   let Inst{19-16} = MRm{3-0};
5788 }
5789 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5790   0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5791   let Inst{11} = Imm{2}; // h
5792   let Inst{21} = Imm{1}; // l
5793   let Inst{20} = Imm{0}; // m
5794   let Inst{19-16} = MRm{3-0};
5795 }
5796 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5797   0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5798   let Inst{11} = 0b0;    // h
5799   let Inst{21} = Imm{0}; // l
5800   let Inst{20-16} = MRm;
5801 }
5802 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5803   0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5804   let Inst{11} = Imm{1};    // h
5805   let Inst{21} = Imm{0};    // l
5806   let Inst{20-16} = MRm;
5807 }
5808
5809 // Patterns for Scalar Signed saturating doubling multiply returning
5810 // high half (scalar, by element)
5811 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5812   SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
5813   i32, VPR64Lo, neon_uimm2_bare>;
5814 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5815   SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
5816   i32, VPR128Lo, neon_uimm3_bare>;
5817 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5818   SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
5819   i32, VPR64Lo, neon_uimm1_bare>;
5820 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5821   SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
5822   i32, VPR128Lo, neon_uimm2_bare>;
5823
5824 // Scalar Signed saturating rounding doubling multiply
5825 // returning high half (scalar, by element)
5826 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5827   0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5828   let Inst{11} = 0b0; // h
5829   let Inst{21} = Imm{1}; // l
5830   let Inst{20} = Imm{0}; // m
5831   let Inst{19-16} = MRm{3-0};
5832 }
5833 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5834   0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5835   let Inst{11} = Imm{2}; // h
5836   let Inst{21} = Imm{1}; // l
5837   let Inst{20} = Imm{0}; // m
5838   let Inst{19-16} = MRm{3-0};
5839 }
5840 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5841   0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5842   let Inst{11} = 0b0;    // h
5843   let Inst{21} = Imm{0}; // l
5844   let Inst{20-16} = MRm;
5845 }
5846 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5847   0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5848   let Inst{11} = Imm{1};    // h
5849   let Inst{21} = Imm{0};    // l
5850   let Inst{20-16} = MRm;
5851 }
5852
5853 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5854   SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
5855   VPR64Lo, neon_uimm2_bare>;
5856 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5857   SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
5858   VPR128Lo, neon_uimm3_bare>;
5859 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5860   SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
5861   VPR64Lo, neon_uimm1_bare>;
5862 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5863   SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
5864   VPR128Lo, neon_uimm2_bare>;
5865
5866 // Scalar Copy - DUP element to scalar
5867 class NeonI_Scalar_DUP<string asmop, string asmlane,
5868                        RegisterClass ResRC, RegisterOperand VPRC,
5869                        Operand OpImm>
5870   : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
5871                      asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
5872                      [],
5873                      NoItinerary> {
5874   bits<4> Imm;
5875 }
5876
5877 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
5878   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5879 }
5880 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
5881   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5882 }
5883 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
5884   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5885 }
5886 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
5887   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5888 }
5889
5890 multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy,
5891   ValueType OpTy, Operand OpImm,
5892   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5893   def : Pat<(ResTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5894             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5895
5896   def : Pat<(ResTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5897             (ResTy (DUPI
5898               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5899                 OpNImm:$Imm))>;
5900 }
5901
5902 // Patterns for vector extract of FP data using scalar DUP instructions
5903 defm : NeonI_Scalar_DUP_Elt_pattern<DUPsv_S, f32,
5904   v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5905 defm : NeonI_Scalar_DUP_Elt_pattern<DUPdv_D, f64,
5906   v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5907
5908 multiclass NeonI_Scalar_DUP_Ext_Vec_pattern<Instruction DUPI,
5909   ValueType ResTy, ValueType OpTy,Operand OpLImm,
5910   ValueType NOpTy, ValueType ExTy, Operand OpNImm> {
5911
5912   def : Pat<(ResTy (extract_subvector (OpTy VPR128:$Rn), OpLImm:$Imm)),
5913             (ResTy (DUPI VPR128:$Rn, OpLImm:$Imm))>;
5914
5915   def : Pat<(ResTy (extract_subvector (NOpTy VPR64:$Rn), OpNImm:$Imm)),
5916             (ResTy (DUPI
5917               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5918                 OpNImm:$Imm))>;
5919 }
5920
5921 // Patterns for extract subvectors of v1ix data using scalar DUP instructions.
5922 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPbv_B, v1i8, v16i8, neon_uimm4_bare,
5923                                         v8i8, v16i8, neon_uimm3_bare>;
5924 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPhv_H, v1i16, v8i16, neon_uimm3_bare,
5925                                         v4i16, v8i16, neon_uimm2_bare>;
5926 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPsv_S, v1i32, v4i32, neon_uimm2_bare,
5927                                         v2i32, v4i32, neon_uimm1_bare>;
5928
5929 multiclass NeonI_Scalar_DUP_Copy_pattern1<Instruction DUPI, ValueType ResTy,
5930                                           ValueType OpTy, ValueType ElemTy,
5931                                           Operand OpImm, ValueType OpNTy,
5932                                           ValueType ExTy, Operand OpNImm> {
5933
5934   def : Pat<(ResTy (vector_insert (ResTy undef),
5935               (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5936               (neon_uimm0_bare:$Imm))),
5937             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5938
5939   def : Pat<(ResTy (vector_insert (ResTy undef),
5940               (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5941               (OpNImm:$Imm))),
5942             (ResTy (DUPI
5943               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5944               OpNImm:$Imm))>;
5945 }
5946
5947 multiclass NeonI_Scalar_DUP_Copy_pattern2<Instruction DUPI, ValueType ResTy,
5948                                           ValueType OpTy, ValueType ElemTy,
5949                                           Operand OpImm, ValueType OpNTy,
5950                                           ValueType ExTy, Operand OpNImm> {
5951
5952   def : Pat<(ResTy (scalar_to_vector
5953               (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)))),
5954             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5955
5956   def : Pat<(ResTy (scalar_to_vector
5957               (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)))),
5958             (ResTy (DUPI
5959               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5960               OpNImm:$Imm))>;
5961 }
5962
5963 // Patterns for vector copy to v1ix and v1fx vectors using scalar DUP
5964 // instructions.
5965 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
5966   v1i64, v2i64, i64, neon_uimm1_bare,
5967   v1i64, v2i64, neon_uimm0_bare>;
5968 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
5969   v1i32, v4i32, i32, neon_uimm2_bare,
5970   v2i32, v4i32, neon_uimm1_bare>;
5971 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPhv_H,
5972   v1i16, v8i16, i32, neon_uimm3_bare,
5973   v4i16, v8i16, neon_uimm2_bare>;
5974 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPbv_B,
5975   v1i8, v16i8, i32, neon_uimm4_bare,
5976   v8i8, v16i8, neon_uimm3_bare>;
5977 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
5978   v1f64, v2f64, f64, neon_uimm1_bare,
5979   v1f64, v2f64, neon_uimm0_bare>;
5980 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
5981   v1f32, v4f32, f32, neon_uimm2_bare,
5982   v2f32, v4f32, neon_uimm1_bare>;
5983 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
5984   v1i64, v2i64, i64, neon_uimm1_bare,
5985   v1i64, v2i64, neon_uimm0_bare>;
5986 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
5987   v1i32, v4i32, i32, neon_uimm2_bare,
5988   v2i32, v4i32, neon_uimm1_bare>;
5989 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPhv_H,
5990   v1i16, v8i16, i32, neon_uimm3_bare,
5991   v4i16, v8i16, neon_uimm2_bare>;
5992 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPbv_B,
5993   v1i8, v16i8, i32, neon_uimm4_bare,
5994   v8i8, v16i8, neon_uimm3_bare>;
5995 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
5996   v1f64, v2f64, f64, neon_uimm1_bare,
5997   v1f64, v2f64, neon_uimm0_bare>;
5998 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
5999   v1f32, v4f32, f32, neon_uimm2_bare,
6000   v2f32, v4f32, neon_uimm1_bare>;
6001
6002 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
6003                                   Instruction DUPI, Operand OpImm,
6004                                   RegisterClass ResRC> {
6005   def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn" # asmlane # "[$Imm]"),
6006           (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
6007 }
6008
6009 // Aliases for Scalar copy - DUP element (scalar)
6010 // FIXME: This is actually the preferred syntax but TableGen can't deal with
6011 // custom printing of aliases.
6012 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
6013 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
6014 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
6015 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
6016
6017 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh, ValueType ResTy,
6018                       ValueType OpTy> {
6019   def : Pat<(ResTy (GetLow VPR128:$Rn)),
6020             (ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>;
6021   def : Pat<(ResTy (GetHigh VPR128:$Rn)),
6022             (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
6023 }
6024
6025 defm : NeonI_SDUP<Neon_Low16B, Neon_High16B, v8i8, v16i8>;
6026 defm : NeonI_SDUP<Neon_Low8H, Neon_High8H, v4i16, v8i16>;
6027 defm : NeonI_SDUP<Neon_Low4S, Neon_High4S, v2i32, v4i32>;
6028 defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>;
6029 defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>;
6030 defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>;
6031
6032 //===----------------------------------------------------------------------===//
6033 // Non-Instruction Patterns
6034 //===----------------------------------------------------------------------===//
6035
6036 // 64-bit vector bitcasts...
6037
6038 def : Pat<(v1i64 (bitconvert (v8i8  VPR64:$src))), (v1i64 VPR64:$src)>;
6039 def : Pat<(v2f32 (bitconvert (v8i8  VPR64:$src))), (v2f32 VPR64:$src)>;
6040 def : Pat<(v2i32 (bitconvert (v8i8  VPR64:$src))), (v2i32 VPR64:$src)>;
6041 def : Pat<(v4i16 (bitconvert (v8i8  VPR64:$src))), (v4i16 VPR64:$src)>;
6042
6043 def : Pat<(v1i64 (bitconvert (v4i16  VPR64:$src))), (v1i64 VPR64:$src)>;
6044 def : Pat<(v2i32 (bitconvert (v4i16  VPR64:$src))), (v2i32 VPR64:$src)>;
6045 def : Pat<(v2f32 (bitconvert (v4i16  VPR64:$src))), (v2f32 VPR64:$src)>;
6046 def : Pat<(v8i8  (bitconvert (v4i16  VPR64:$src))), (v8i8 VPR64:$src)>;
6047
6048 def : Pat<(v1i64 (bitconvert (v2i32  VPR64:$src))), (v1i64 VPR64:$src)>;
6049 def : Pat<(v2f32 (bitconvert (v2i32  VPR64:$src))), (v2f32 VPR64:$src)>;
6050 def : Pat<(v4i16 (bitconvert (v2i32  VPR64:$src))), (v4i16 VPR64:$src)>;
6051 def : Pat<(v8i8  (bitconvert (v2i32  VPR64:$src))), (v8i8 VPR64:$src)>;
6052
6053 def : Pat<(v1i64 (bitconvert (v2f32  VPR64:$src))), (v1i64 VPR64:$src)>;
6054 def : Pat<(v2i32 (bitconvert (v2f32  VPR64:$src))), (v2i32 VPR64:$src)>;
6055 def : Pat<(v4i16 (bitconvert (v2f32  VPR64:$src))), (v4i16 VPR64:$src)>;
6056 def : Pat<(v8i8  (bitconvert (v2f32  VPR64:$src))), (v8i8 VPR64:$src)>;
6057
6058 def : Pat<(v2f32 (bitconvert (v1i64  VPR64:$src))), (v2f32 VPR64:$src)>;
6059 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
6060 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
6061 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
6062
6063 // ..and 128-bit vector bitcasts...
6064
6065 def : Pat<(v2f64 (bitconvert (v16i8  VPR128:$src))), (v2f64 VPR128:$src)>;
6066 def : Pat<(v2i64 (bitconvert (v16i8  VPR128:$src))), (v2i64 VPR128:$src)>;
6067 def : Pat<(v4f32 (bitconvert (v16i8  VPR128:$src))), (v4f32 VPR128:$src)>;
6068 def : Pat<(v4i32 (bitconvert (v16i8  VPR128:$src))), (v4i32 VPR128:$src)>;
6069 def : Pat<(v8i16 (bitconvert (v16i8  VPR128:$src))), (v8i16 VPR128:$src)>;
6070
6071 def : Pat<(v2f64 (bitconvert (v8i16  VPR128:$src))), (v2f64 VPR128:$src)>;
6072 def : Pat<(v2i64 (bitconvert (v8i16  VPR128:$src))), (v2i64 VPR128:$src)>;
6073 def : Pat<(v4i32 (bitconvert (v8i16  VPR128:$src))), (v4i32 VPR128:$src)>;
6074 def : Pat<(v4f32 (bitconvert (v8i16  VPR128:$src))), (v4f32 VPR128:$src)>;
6075 def : Pat<(v16i8 (bitconvert (v8i16  VPR128:$src))), (v16i8 VPR128:$src)>;
6076
6077 def : Pat<(v2f64 (bitconvert (v4i32  VPR128:$src))), (v2f64 VPR128:$src)>;
6078 def : Pat<(v2i64 (bitconvert (v4i32  VPR128:$src))), (v2i64 VPR128:$src)>;
6079 def : Pat<(v4f32 (bitconvert (v4i32  VPR128:$src))), (v4f32 VPR128:$src)>;
6080 def : Pat<(v8i16 (bitconvert (v4i32  VPR128:$src))), (v8i16 VPR128:$src)>;
6081 def : Pat<(v16i8 (bitconvert (v4i32  VPR128:$src))), (v16i8 VPR128:$src)>;
6082
6083 def : Pat<(v2f64 (bitconvert (v4f32  VPR128:$src))), (v2f64 VPR128:$src)>;
6084 def : Pat<(v2i64 (bitconvert (v4f32  VPR128:$src))), (v2i64 VPR128:$src)>;
6085 def : Pat<(v4i32 (bitconvert (v4f32  VPR128:$src))), (v4i32 VPR128:$src)>;
6086 def : Pat<(v8i16 (bitconvert (v4f32  VPR128:$src))), (v8i16 VPR128:$src)>;
6087 def : Pat<(v16i8 (bitconvert (v4f32  VPR128:$src))), (v16i8 VPR128:$src)>;
6088
6089 def : Pat<(v2f64 (bitconvert (v2i64  VPR128:$src))), (v2f64 VPR128:$src)>;
6090 def : Pat<(v4f32 (bitconvert (v2i64  VPR128:$src))), (v4f32 VPR128:$src)>;
6091 def : Pat<(v4i32 (bitconvert (v2i64  VPR128:$src))), (v4i32 VPR128:$src)>;
6092 def : Pat<(v8i16 (bitconvert (v2i64  VPR128:$src))), (v8i16 VPR128:$src)>;
6093 def : Pat<(v16i8 (bitconvert (v2i64  VPR128:$src))), (v16i8 VPR128:$src)>;
6094
6095 def : Pat<(v2i64 (bitconvert (v2f64  VPR128:$src))), (v2i64 VPR128:$src)>;
6096 def : Pat<(v4f32 (bitconvert (v2f64  VPR128:$src))), (v4f32 VPR128:$src)>;
6097 def : Pat<(v4i32 (bitconvert (v2f64  VPR128:$src))), (v4i32 VPR128:$src)>;
6098 def : Pat<(v8i16 (bitconvert (v2f64  VPR128:$src))), (v8i16 VPR128:$src)>;
6099 def : Pat<(v16i8 (bitconvert (v2f64  VPR128:$src))), (v16i8 VPR128:$src)>;
6100
6101 // ...and scalar bitcasts...
6102 def : Pat<(f16 (bitconvert (v1i16  FPR16:$src))), (f16 FPR16:$src)>;
6103 def : Pat<(f32 (bitconvert (v1i32  FPR32:$src))), (f32 FPR32:$src)>;
6104 def : Pat<(f64 (bitconvert (v1i64  FPR64:$src))), (f64 FPR64:$src)>;
6105 def : Pat<(f32 (bitconvert (v1f32  FPR32:$src))), (f32 FPR32:$src)>;
6106 def : Pat<(f64 (bitconvert (v1f64  FPR64:$src))), (f64 FPR64:$src)>;
6107
6108 def : Pat<(i64 (bitconvert (v1i64  FPR64:$src))), (FMOVxd $src)>;
6109 def : Pat<(i64 (bitconvert (v1f64  FPR64:$src))), (FMOVxd $src)>;
6110 def : Pat<(i64 (bitconvert (v2i32  FPR64:$src))), (FMOVxd $src)>;
6111 def : Pat<(i64 (bitconvert (v2f32  FPR64:$src))), (FMOVxd $src)>;
6112 def : Pat<(i64 (bitconvert (v4i16  FPR64:$src))), (FMOVxd $src)>;
6113 def : Pat<(i64 (bitconvert (v8i8  FPR64:$src))), (FMOVxd $src)>;
6114
6115 def : Pat<(i32 (bitconvert (v1i32  FPR32:$src))), (FMOVws $src)>;
6116
6117 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
6118 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
6119 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
6120
6121 def : Pat<(f64   (bitconvert (v8i8  VPR64:$src))), (f64 VPR64:$src)>;
6122 def : Pat<(f64   (bitconvert (v4i16  VPR64:$src))), (f64 VPR64:$src)>;
6123 def : Pat<(f64   (bitconvert (v2i32  VPR64:$src))), (f64 VPR64:$src)>;
6124 def : Pat<(f64   (bitconvert (v2f32  VPR64:$src))), (f64 VPR64:$src)>;
6125 def : Pat<(f64   (bitconvert (v1i64  VPR64:$src))), (f64 VPR64:$src)>;
6126
6127 def : Pat<(f128  (bitconvert (v16i8  VPR128:$src))), (f128 VPR128:$src)>;
6128 def : Pat<(f128  (bitconvert (v8i16  VPR128:$src))), (f128 VPR128:$src)>;
6129 def : Pat<(f128  (bitconvert (v4i32  VPR128:$src))), (f128 VPR128:$src)>;
6130 def : Pat<(f128  (bitconvert (v2i64  VPR128:$src))), (f128 VPR128:$src)>;
6131 def : Pat<(f128  (bitconvert (v4f32  VPR128:$src))), (f128 VPR128:$src)>;
6132 def : Pat<(f128  (bitconvert (v2f64  VPR128:$src))), (f128 VPR128:$src)>;
6133
6134 def : Pat<(v1i16 (bitconvert (f16  FPR16:$src))), (v1i16 FPR16:$src)>;
6135 def : Pat<(v1i32 (bitconvert (f32  FPR32:$src))), (v1i32 FPR32:$src)>;
6136 def : Pat<(v1i64 (bitconvert (f64  FPR64:$src))), (v1i64 FPR64:$src)>;
6137 def : Pat<(v1f32 (bitconvert (f32  FPR32:$src))), (v1f32 FPR32:$src)>;
6138 def : Pat<(v1f64 (bitconvert (f64  FPR64:$src))), (v1f64 FPR64:$src)>;
6139
6140 def : Pat<(v1i64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6141 def : Pat<(v1f64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6142 def : Pat<(v2i32 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6143 def : Pat<(v2f32 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6144 def : Pat<(v4i16 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6145 def : Pat<(v8i8 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6146
6147 def : Pat<(v1i32 (bitconvert (i32  GPR32:$src))), (FMOVsw $src)>;
6148
6149 def : Pat<(v8i8   (bitconvert (f64   FPR64:$src))), (v8i8 FPR64:$src)>;
6150 def : Pat<(v4i16  (bitconvert (f64   FPR64:$src))), (v4i16 FPR64:$src)>;
6151 def : Pat<(v2i32  (bitconvert (f64   FPR64:$src))), (v2i32 FPR64:$src)>;
6152 def : Pat<(v2f32  (bitconvert (f64   FPR64:$src))), (v2f32 FPR64:$src)>;
6153 def : Pat<(v1i64  (bitconvert (f64   FPR64:$src))), (v1i64 FPR64:$src)>;
6154
6155 def : Pat<(v16i8  (bitconvert (f128   FPR128:$src))), (v16i8 FPR128:$src)>;
6156 def : Pat<(v8i16  (bitconvert (f128   FPR128:$src))), (v8i16 FPR128:$src)>;
6157 def : Pat<(v4i32  (bitconvert (f128   FPR128:$src))), (v4i32 FPR128:$src)>;
6158 def : Pat<(v2i64  (bitconvert (f128   FPR128:$src))), (v2i64 FPR128:$src)>;
6159 def : Pat<(v4f32  (bitconvert (f128   FPR128:$src))), (v4f32 FPR128:$src)>;
6160 def : Pat<(v2f64  (bitconvert (f128   FPR128:$src))), (v2f64 FPR128:$src)>;
6161
6162 // Scalar Three Same
6163
6164 def neon_uimm3 : Operand<i64>,
6165                    ImmLeaf<i64, [{return Imm < 8;}]> {
6166   let ParserMatchClass = uimm3_asmoperand;
6167   let PrintMethod = "printUImmHexOperand";
6168 }
6169
6170 def neon_uimm4 : Operand<i64>,
6171                    ImmLeaf<i64, [{return Imm < 16;}]> {
6172   let ParserMatchClass = uimm4_asmoperand;
6173   let PrintMethod = "printUImmHexOperand";
6174 }
6175
6176 // Bitwise Extract
6177 class NeonI_Extract<bit q, bits<2> op2, string asmop,
6178                     string OpS, RegisterOperand OpVPR, Operand OpImm>
6179   : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
6180                      (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
6181                      asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
6182                      ", $Rm." # OpS # ", $Index",
6183                      [],
6184                      NoItinerary>{
6185   bits<4> Index;
6186 }
6187
6188 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
6189                                VPR64, neon_uimm3> {
6190   let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
6191 }
6192
6193 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
6194                                VPR128, neon_uimm4> {
6195   let Inst{14-11} = Index;
6196 }
6197
6198 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
6199                  Operand OpImm>
6200   : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
6201                                  (i64 OpImm:$Imm))),
6202               (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
6203
6204 def : NI_Extract<v8i8,  VPR64,  EXTvvvi_8b,  neon_uimm3>;
6205 def : NI_Extract<v4i16, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6206 def : NI_Extract<v2i32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6207 def : NI_Extract<v1i64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6208 def : NI_Extract<v2f32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6209 def : NI_Extract<v1f64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6210 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
6211 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
6212 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
6213 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
6214 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
6215 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
6216
6217 // Table lookup
6218 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
6219              string asmop, string OpS, RegisterOperand OpVPR,
6220              RegisterOperand VecList>
6221   : NeonI_TBL<q, op2, len, op,
6222               (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
6223               asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6224               [],
6225               NoItinerary>;
6226
6227 // The vectors in look up table are always 16b
6228 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
6229   def _8b  : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
6230                     !cast<RegisterOperand>(List # "16B_operand")>;
6231
6232   def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
6233                     !cast<RegisterOperand>(List # "16B_operand")>;
6234 }
6235
6236 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
6237 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
6238 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
6239 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
6240
6241 // Table lookup extention
6242 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
6243              string asmop, string OpS, RegisterOperand OpVPR,
6244              RegisterOperand VecList>
6245   : NeonI_TBL<q, op2, len, op,
6246               (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
6247               asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6248               [],
6249               NoItinerary> {
6250   let Constraints = "$src = $Rd";
6251 }
6252
6253 // The vectors in look up table are always 16b
6254 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
6255   def _8b  : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
6256                     !cast<RegisterOperand>(List # "16B_operand")>;
6257
6258   def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6259                     !cast<RegisterOperand>(List # "16B_operand")>;
6260 }
6261
6262 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6263 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6264 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6265 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6266
6267 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6268                      RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6269   : NeonI_copy<0b1, 0b0, 0b0011,
6270                (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6271                asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6272                [(set (ResTy VPR128:$Rd),
6273                  (ResTy (vector_insert
6274                    (ResTy VPR128:$src),
6275                    (OpTy OpGPR:$Rn),
6276                    (OpImm:$Imm))))],
6277                NoItinerary> {
6278   bits<4> Imm;
6279   let Constraints = "$src = $Rd";
6280 }
6281
6282 //Insert element (vector, from main)
6283 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6284                            neon_uimm4_bare> {
6285   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6286 }
6287 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6288                            neon_uimm3_bare> {
6289   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6290 }
6291 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6292                            neon_uimm2_bare> {
6293   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6294 }
6295 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6296                            neon_uimm1_bare> {
6297   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6298 }
6299
6300 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6301                     (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6302 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6303                     (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6304 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6305                     (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6306 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6307                     (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6308
6309 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6310                              RegisterClass OpGPR, ValueType OpTy,
6311                              Operand OpImm, Instruction INS>
6312   : Pat<(ResTy (vector_insert
6313               (ResTy VPR64:$src),
6314               (OpTy OpGPR:$Rn),
6315               (OpImm:$Imm))),
6316         (ResTy (EXTRACT_SUBREG
6317           (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6318             OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6319
6320 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6321                                           neon_uimm3_bare, INSbw>;
6322 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6323                                           neon_uimm2_bare, INShw>;
6324 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6325                                           neon_uimm1_bare, INSsw>;
6326 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6327                                           neon_uimm0_bare, INSdx>;
6328
6329 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6330   : NeonI_insert<0b1, 0b1,
6331                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6332                  ResImm:$Immd, ResImm:$Immn),
6333                  asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6334                  [],
6335                  NoItinerary> {
6336   let Constraints = "$src = $Rd";
6337   bits<4> Immd;
6338   bits<4> Immn;
6339 }
6340
6341 //Insert element (vector, from element)
6342 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6343   let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6344   let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6345 }
6346 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6347   let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6348   let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6349   // bit 11 is unspecified, but should be set to zero.
6350 }
6351 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6352   let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6353   let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6354   // bits 11-12 are unspecified, but should be set to zero.
6355 }
6356 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6357   let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6358   let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6359   // bits 11-13 are unspecified, but should be set to zero.
6360 }
6361
6362 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6363                     (INSELb VPR128:$Rd, VPR128:$Rn,
6364                       neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6365 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6366                     (INSELh VPR128:$Rd, VPR128:$Rn,
6367                       neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6368 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6369                     (INSELs VPR128:$Rd, VPR128:$Rn,
6370                       neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6371 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6372                     (INSELd VPR128:$Rd, VPR128:$Rn,
6373                       neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
6374
6375 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
6376                                 ValueType MidTy, Operand StImm, Operand NaImm,
6377                                 Instruction INS> {
6378 def : Pat<(ResTy (vector_insert
6379             (ResTy VPR128:$src),
6380             (MidTy (vector_extract
6381               (ResTy VPR128:$Rn),
6382               (StImm:$Immn))),
6383             (StImm:$Immd))),
6384           (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
6385               StImm:$Immd, StImm:$Immn)>;
6386
6387 def : Pat <(ResTy (vector_insert
6388              (ResTy VPR128:$src),
6389              (MidTy (vector_extract
6390                (NaTy VPR64:$Rn),
6391                (NaImm:$Immn))),
6392              (StImm:$Immd))),
6393            (INS (ResTy VPR128:$src),
6394              (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6395              StImm:$Immd, NaImm:$Immn)>;
6396
6397 def : Pat <(NaTy (vector_insert
6398              (NaTy VPR64:$src),
6399              (MidTy (vector_extract
6400                (ResTy VPR128:$Rn),
6401                (StImm:$Immn))),
6402              (NaImm:$Immd))),
6403            (NaTy (EXTRACT_SUBREG
6404              (ResTy (INS
6405                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6406                (ResTy VPR128:$Rn),
6407                NaImm:$Immd, StImm:$Immn)),
6408              sub_64))>;
6409
6410 def : Pat <(NaTy (vector_insert
6411              (NaTy VPR64:$src),
6412              (MidTy (vector_extract
6413                (NaTy VPR64:$Rn),
6414                (NaImm:$Immn))),
6415              (NaImm:$Immd))),
6416            (NaTy (EXTRACT_SUBREG
6417              (ResTy (INS
6418                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6419                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6420                NaImm:$Immd, NaImm:$Immn)),
6421              sub_64))>;
6422 }
6423
6424 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
6425                             neon_uimm1_bare, INSELs>;
6426 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
6427                             neon_uimm0_bare, INSELd>;
6428 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6429                             neon_uimm3_bare, INSELb>;
6430 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6431                             neon_uimm2_bare, INSELh>;
6432 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6433                             neon_uimm1_bare, INSELs>;
6434 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
6435                             neon_uimm0_bare, INSELd>;
6436
6437 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
6438                                       ValueType MidTy,
6439                                       RegisterClass OpFPR, Operand ResImm,
6440                                       SubRegIndex SubIndex, Instruction INS> {
6441 def : Pat <(ResTy (vector_insert
6442              (ResTy VPR128:$src),
6443              (MidTy OpFPR:$Rn),
6444              (ResImm:$Imm))),
6445            (INS (ResTy VPR128:$src),
6446              (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
6447              ResImm:$Imm,
6448              (i64 0))>;
6449
6450 def : Pat <(NaTy (vector_insert
6451              (NaTy VPR64:$src),
6452              (MidTy OpFPR:$Rn),
6453              (ResImm:$Imm))),
6454            (NaTy (EXTRACT_SUBREG
6455              (ResTy (INS
6456                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6457                (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
6458                ResImm:$Imm,
6459                (i64 0))),
6460              sub_64))>;
6461 }
6462
6463 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
6464                                   sub_32, INSELs>;
6465 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
6466                                   sub_64, INSELd>;
6467
6468 class NeonI_SMOV<string asmop, string Res, bit Q,
6469                  ValueType OpTy, ValueType eleTy,
6470                  Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
6471   : NeonI_copy<Q, 0b0, 0b0101,
6472                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6473                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6474                [(set (ResTy ResGPR:$Rd),
6475                  (ResTy (sext_inreg
6476                    (ResTy (vector_extract
6477                      (OpTy VPR128:$Rn), (OpImm:$Imm))),
6478                    eleTy)))],
6479                NoItinerary> {
6480   bits<4> Imm;
6481 }
6482
6483 //Signed integer move (main, from element)
6484 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
6485                         GPR32, i32> {
6486   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6487 }
6488 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
6489                         GPR32, i32> {
6490   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6491 }
6492 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
6493                         GPR64, i64> {
6494   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6495 }
6496 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
6497                         GPR64, i64> {
6498   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6499 }
6500 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
6501                         GPR64, i64> {
6502   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6503 }
6504
6505 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
6506                                ValueType eleTy, Operand StImm,  Operand NaImm,
6507                                Instruction SMOVI> {
6508   def : Pat<(i64 (sext_inreg
6509               (i64 (anyext
6510                 (i32 (vector_extract
6511                   (StTy VPR128:$Rn), (StImm:$Imm))))),
6512               eleTy)),
6513             (SMOVI VPR128:$Rn, StImm:$Imm)>;
6514
6515   def : Pat<(i64 (sext
6516               (i32 (vector_extract
6517                 (StTy VPR128:$Rn), (StImm:$Imm))))),
6518             (SMOVI VPR128:$Rn, StImm:$Imm)>;
6519
6520   def : Pat<(i64 (sext_inreg
6521               (i64 (vector_extract
6522                 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6523               eleTy)),
6524             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6525               NaImm:$Imm)>;
6526
6527   def : Pat<(i64 (sext_inreg
6528               (i64 (anyext
6529                 (i32 (vector_extract
6530                   (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6531               eleTy)),
6532             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6533               NaImm:$Imm)>;
6534
6535   def : Pat<(i64 (sext
6536               (i32 (vector_extract
6537                 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6538             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6539               NaImm:$Imm)>;
6540 }
6541
6542 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6543                           neon_uimm3_bare, SMOVxb>;
6544 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6545                           neon_uimm2_bare, SMOVxh>;
6546 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6547                           neon_uimm1_bare, SMOVxs>;
6548
6549 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
6550                           ValueType eleTy, Operand StImm,  Operand NaImm,
6551                           Instruction SMOVI>
6552   : Pat<(i32 (sext_inreg
6553           (i32 (vector_extract
6554             (NaTy VPR64:$Rn), (NaImm:$Imm))),
6555           eleTy)),
6556         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6557           NaImm:$Imm)>;
6558
6559 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6560                          neon_uimm3_bare, SMOVwb>;
6561 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6562                          neon_uimm2_bare, SMOVwh>;
6563
6564 class NeonI_UMOV<string asmop, string Res, bit Q,
6565                  ValueType OpTy, Operand OpImm,
6566                  RegisterClass ResGPR, ValueType ResTy>
6567   : NeonI_copy<Q, 0b0, 0b0111,
6568                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6569                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6570                [(set (ResTy ResGPR:$Rd),
6571                   (ResTy (vector_extract
6572                     (OpTy VPR128:$Rn), (OpImm:$Imm))))],
6573                NoItinerary> {
6574   bits<4> Imm;
6575 }
6576
6577 //Unsigned integer move (main, from element)
6578 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
6579                          GPR32, i32> {
6580   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6581 }
6582 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
6583                          GPR32, i32> {
6584   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6585 }
6586 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
6587                          GPR32, i32> {
6588   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6589 }
6590 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
6591                          GPR64, i64> {
6592   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6593 }
6594
6595 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
6596                     (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
6597 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
6598                     (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
6599
6600 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
6601                          Operand StImm,  Operand NaImm,
6602                          Instruction SMOVI>
6603   : Pat<(ResTy (vector_extract
6604           (NaTy VPR64:$Rn), NaImm:$Imm)),
6605         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6606           NaImm:$Imm)>;
6607
6608 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6609                         neon_uimm3_bare, UMOVwb>;
6610 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6611                         neon_uimm2_bare, UMOVwh>;
6612 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6613                         neon_uimm1_bare, UMOVws>;
6614
6615 def : Pat<(i32 (and
6616             (i32 (vector_extract
6617               (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
6618             255)),
6619           (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
6620
6621 def : Pat<(i32 (and
6622             (i32 (vector_extract
6623               (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
6624             65535)),
6625           (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
6626
6627 def : Pat<(i64 (zext
6628             (i32 (vector_extract
6629               (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
6630           (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
6631
6632 def : Pat<(i32 (and
6633             (i32 (vector_extract
6634               (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
6635             255)),
6636           (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6637             neon_uimm3_bare:$Imm)>;
6638
6639 def : Pat<(i32 (and
6640             (i32 (vector_extract
6641               (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
6642             65535)),
6643           (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6644             neon_uimm2_bare:$Imm)>;
6645
6646 def : Pat<(i64 (zext
6647             (i32 (vector_extract
6648               (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
6649           (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6650             neon_uimm0_bare:$Imm)>;
6651
6652 // Additional copy patterns for scalar types
6653 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
6654           (UMOVwb (v16i8
6655             (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
6656
6657 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
6658           (UMOVwh (v8i16
6659             (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
6660
6661 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
6662           (FMOVws FPR32:$Rn)>;
6663
6664 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
6665           (FMOVxd FPR64:$Rn)>;
6666
6667 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
6668           (f64 FPR64:$Rn)>;
6669
6670 def : Pat<(f32 (vector_extract (v1f32 FPR32:$Rn), (i64 0))),
6671           (f32 FPR32:$Rn)>;
6672
6673 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
6674           (v1i8 (EXTRACT_SUBREG (v16i8
6675             (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6676             sub_8))>;
6677
6678 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
6679           (v1i16 (EXTRACT_SUBREG (v8i16
6680             (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6681             sub_16))>;
6682
6683 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
6684           (FMOVsw $src)>;
6685
6686 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
6687           (FMOVdx $src)>;
6688
6689 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))),
6690           (v1f32 FPR32:$Rn)>;
6691 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
6692           (v1f64 FPR64:$Rn)>;
6693
6694 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
6695           (FMOVdd $src)>;
6696
6697 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
6698           (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
6699                          (f64 FPR64:$src), sub_64)>;
6700
6701 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane,  string rnlane,
6702                     RegisterOperand ResVPR, Operand OpImm>
6703   : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
6704                (ins VPR128:$Rn, OpImm:$Imm),
6705                asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
6706                [],
6707                NoItinerary> {
6708   bits<4> Imm;
6709 }
6710
6711 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
6712                               neon_uimm4_bare> {
6713   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6714 }
6715
6716 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
6717                               neon_uimm3_bare> {
6718   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6719 }
6720
6721 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
6722                               neon_uimm2_bare> {
6723   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6724 }
6725
6726 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
6727                               neon_uimm1_bare> {
6728   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6729 }
6730
6731 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
6732                               neon_uimm4_bare> {
6733   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6734 }
6735
6736 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
6737                               neon_uimm3_bare> {
6738   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6739 }
6740
6741 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
6742                               neon_uimm2_bare> {
6743   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6744 }
6745
6746 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
6747                                        ValueType OpTy,ValueType NaTy,
6748                                        ValueType ExTy, Operand OpLImm,
6749                                        Operand OpNImm> {
6750 def  : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
6751         (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
6752
6753 def : Pat<(ResTy (Neon_vduplane
6754             (NaTy VPR64:$Rn), OpNImm:$Imm)),
6755           (ResTy (DUPELT
6756             (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
6757 }
6758 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
6759                              neon_uimm4_bare, neon_uimm3_bare>;
6760 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
6761                              neon_uimm4_bare, neon_uimm3_bare>;
6762 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
6763                              neon_uimm3_bare, neon_uimm2_bare>;
6764 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
6765                              neon_uimm3_bare, neon_uimm2_bare>;
6766 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
6767                              neon_uimm2_bare, neon_uimm1_bare>;
6768 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
6769                              neon_uimm2_bare, neon_uimm1_bare>;
6770 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
6771                              neon_uimm1_bare, neon_uimm0_bare>;
6772 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
6773                              neon_uimm2_bare, neon_uimm1_bare>;
6774 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
6775                              neon_uimm2_bare, neon_uimm1_bare>;
6776 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
6777                              neon_uimm1_bare, neon_uimm0_bare>;
6778
6779 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
6780           (v2f32 (DUPELT2s
6781             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6782             (i64 0)))>;
6783 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
6784           (v4f32 (DUPELT4s
6785             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6786             (i64 0)))>;
6787 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
6788           (v2f64 (DUPELT2d
6789             (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
6790             (i64 0)))>;
6791
6792 class NeonI_DUP<bit Q, string asmop, string rdlane,
6793                 RegisterOperand ResVPR, ValueType ResTy,
6794                 RegisterClass OpGPR, ValueType OpTy>
6795   : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
6796                asmop # "\t$Rd" # rdlane # ", $Rn",
6797                [(set (ResTy ResVPR:$Rd),
6798                  (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
6799                NoItinerary>;
6800
6801 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
6802   let Inst{20-16} = 0b00001;
6803   // bits 17-20 are unspecified, but should be set to zero.
6804 }
6805
6806 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
6807   let Inst{20-16} = 0b00010;
6808   // bits 18-20 are unspecified, but should be set to zero.
6809 }
6810
6811 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
6812   let Inst{20-16} = 0b00100;
6813   // bits 19-20 are unspecified, but should be set to zero.
6814 }
6815
6816 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
6817   let Inst{20-16} = 0b01000;
6818   // bit 20 is unspecified, but should be set to zero.
6819 }
6820
6821 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
6822   let Inst{20-16} = 0b00001;
6823   // bits 17-20 are unspecified, but should be set to zero.
6824 }
6825
6826 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
6827   let Inst{20-16} = 0b00010;
6828   // bits 18-20 are unspecified, but should be set to zero.
6829 }
6830
6831 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
6832   let Inst{20-16} = 0b00100;
6833   // bits 19-20 are unspecified, but should be set to zero.
6834 }
6835
6836 // patterns for CONCAT_VECTORS
6837 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
6838 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
6839           (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
6840 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
6841           (INSELd
6842             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6843             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
6844             (i64 1),
6845             (i64 0))>;
6846 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
6847           (DUPELT2d
6848             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6849             (i64 0))> ;
6850 }
6851
6852 defm : Concat_Vector_Pattern<v16i8, v8i8>;
6853 defm : Concat_Vector_Pattern<v8i16, v4i16>;
6854 defm : Concat_Vector_Pattern<v4i32, v2i32>;
6855 defm : Concat_Vector_Pattern<v2i64, v1i64>;
6856 defm : Concat_Vector_Pattern<v4f32, v2f32>;
6857 defm : Concat_Vector_Pattern<v2f64, v1f64>;
6858
6859 //patterns for EXTRACT_SUBVECTOR
6860 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
6861           (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6862 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
6863           (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6864 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
6865           (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6866 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
6867           (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6868 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
6869           (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6870 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
6871           (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6872
6873 // The followings are for instruction class (3V Elem)
6874
6875 // Variant 1
6876
6877 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
6878              string asmop, string ResS, string OpS, string EleOpS,
6879              Operand OpImm, RegisterOperand ResVPR,
6880              RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6881   : NeonI_2VElem<q, u, size, opcode,
6882                  (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
6883                                          EleOpVPR:$Re, OpImm:$Index),
6884                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6885                  ", $Re." # EleOpS # "[$Index]",
6886                  [],
6887                  NoItinerary> {
6888   bits<3> Index;
6889   bits<5> Re;
6890
6891   let Constraints = "$src = $Rd";
6892 }
6893
6894 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
6895   // vector register class for element is always 128-bit to cover the max index
6896   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6897                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
6898     let Inst{11} = {Index{1}};
6899     let Inst{21} = {Index{0}};
6900     let Inst{20-16} = Re;
6901   }
6902
6903   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6904                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
6905     let Inst{11} = {Index{1}};
6906     let Inst{21} = {Index{0}};
6907     let Inst{20-16} = Re;
6908   }
6909
6910   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6911   def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6912                      neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6913     let Inst{11} = {Index{2}};
6914     let Inst{21} = {Index{1}};
6915     let Inst{20} = {Index{0}};
6916     let Inst{19-16} = Re{3-0};
6917   }
6918
6919   def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
6920                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6921     let Inst{11} = {Index{2}};
6922     let Inst{21} = {Index{1}};
6923     let Inst{20} = {Index{0}};
6924     let Inst{19-16} = Re{3-0};
6925   }
6926 }
6927
6928 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
6929 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
6930
6931 // Pattern for lane in 128-bit vector
6932 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6933                    RegisterOperand ResVPR, RegisterOperand OpVPR,
6934                    RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6935                    ValueType EleOpTy>
6936   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6937           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6938         (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6939
6940 // Pattern for lane in 64-bit vector
6941 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6942                   RegisterOperand ResVPR, RegisterOperand OpVPR,
6943                   RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6944                   ValueType EleOpTy>
6945   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6946           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6947         (INST ResVPR:$src, OpVPR:$Rn,
6948           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6949
6950 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
6951 {
6952   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6953                      op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32>;
6954
6955   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6956                      op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32>;
6957
6958   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
6959                      op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
6960
6961   def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
6962                      op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
6963
6964   // Index can only be half of the max value for lane in 64-bit vector
6965
6966   def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6967                     op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32>;
6968
6969   def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
6970                     op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
6971 }
6972
6973 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
6974 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
6975
6976 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
6977                  string asmop, string ResS, string OpS, string EleOpS,
6978                  Operand OpImm, RegisterOperand ResVPR,
6979                  RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6980   : NeonI_2VElem<q, u, size, opcode,
6981                  (outs ResVPR:$Rd), (ins OpVPR:$Rn,
6982                                          EleOpVPR:$Re, OpImm:$Index),
6983                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6984                  ", $Re." # EleOpS # "[$Index]",
6985                  [],
6986                  NoItinerary> {
6987   bits<3> Index;
6988   bits<5> Re;
6989 }
6990
6991 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
6992   // vector register class for element is always 128-bit to cover the max index
6993   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6994                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
6995     let Inst{11} = {Index{1}};
6996     let Inst{21} = {Index{0}};
6997     let Inst{20-16} = Re;
6998   }
6999
7000   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7001                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7002     let Inst{11} = {Index{1}};
7003     let Inst{21} = {Index{0}};
7004     let Inst{20-16} = Re;
7005   }
7006
7007   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7008   def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
7009                          neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
7010     let Inst{11} = {Index{2}};
7011     let Inst{21} = {Index{1}};
7012     let Inst{20} = {Index{0}};
7013     let Inst{19-16} = Re{3-0};
7014   }
7015
7016   def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7017                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7018     let Inst{11} = {Index{2}};
7019     let Inst{21} = {Index{1}};
7020     let Inst{20} = {Index{0}};
7021     let Inst{19-16} = Re{3-0};
7022   }
7023 }
7024
7025 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
7026 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
7027 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
7028
7029 // Pattern for lane in 128-bit vector
7030 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7031                        RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7032                        ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7033   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7034           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7035         (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7036
7037 // Pattern for lane in 64-bit vector
7038 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7039                       RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7040                       ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7041   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7042           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7043         (INST OpVPR:$Rn,
7044           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7045
7046 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
7047   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7048                          op, VPR64, VPR128, v2i32, v2i32, v4i32>;
7049
7050   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7051                          op, VPR128, VPR128, v4i32, v4i32, v4i32>;
7052
7053   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7054                          op, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7055
7056   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7057                          op, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7058
7059   // Index can only be half of the max value for lane in 64-bit vector
7060
7061   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7062                         op, VPR64, VPR64, v2i32, v2i32, v2i32>;
7063
7064   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7065                         op, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7066 }
7067
7068 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
7069 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
7070 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
7071
7072 // Variant 2
7073
7074 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
7075   // vector register class for element is always 128-bit to cover the max index
7076   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7077                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
7078     let Inst{11} = {Index{1}};
7079     let Inst{21} = {Index{0}};
7080     let Inst{20-16} = Re;
7081   }
7082
7083   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7084                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7085     let Inst{11} = {Index{1}};
7086     let Inst{21} = {Index{0}};
7087     let Inst{20-16} = Re;
7088   }
7089
7090   // _1d2d doesn't exist!
7091
7092   def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7093                          neon_uimm1_bare, VPR128, VPR128, VPR128> {
7094     let Inst{11} = {Index{0}};
7095     let Inst{21} = 0b0;
7096     let Inst{20-16} = Re;
7097   }
7098 }
7099
7100 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
7101 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
7102
7103 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
7104                          RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7105                          ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
7106                          SDPatternOperator coreop>
7107   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7108           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
7109         (INST OpVPR:$Rn,
7110           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
7111
7112 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
7113   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7114                          op, VPR64, VPR128, v2f32, v2f32, v4f32>;
7115
7116   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7117                          op, VPR128, VPR128, v4f32, v4f32, v4f32>;
7118
7119   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7120                          op, VPR128, VPR128, v2f64, v2f64, v2f64>;
7121
7122   // Index can only be half of the max value for lane in 64-bit vector
7123
7124   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7125                         op, VPR64, VPR64, v2f32, v2f32, v2f32>;
7126
7127   def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7128                            op, VPR128, VPR64, v2f64, v2f64, v1f64,
7129                            BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7130 }
7131
7132 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
7133 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
7134
7135 def : Pat<(v2f32 (fmul (v2f32 (Neon_vdup (f32 FPR32:$Re))),
7136                        (v2f32 VPR64:$Rn))),
7137           (FMULve_2s4s VPR64:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7138
7139 def : Pat<(v4f32 (fmul (v4f32 (Neon_vdup (f32 FPR32:$Re))),
7140                        (v4f32 VPR128:$Rn))),
7141           (FMULve_4s4s VPR128:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7142
7143 def : Pat<(v2f64 (fmul (v2f64 (Neon_vdup (f64 FPR64:$Re))),
7144                        (v2f64 VPR128:$Rn))),
7145           (FMULve_2d2d VPR128:$Rn, (SUBREG_TO_REG (i64 0), $Re, sub_64), 0)>;
7146
7147 // The followings are patterns using fma
7148 // -ffp-contract=fast generates fma
7149
7150 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
7151   // vector register class for element is always 128-bit to cover the max index
7152   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7153                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
7154     let Inst{11} = {Index{1}};
7155     let Inst{21} = {Index{0}};
7156     let Inst{20-16} = Re;
7157   }
7158
7159   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7160                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
7161     let Inst{11} = {Index{1}};
7162     let Inst{21} = {Index{0}};
7163     let Inst{20-16} = Re;
7164   }
7165
7166   // _1d2d doesn't exist!
7167
7168   def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7169                      neon_uimm1_bare, VPR128, VPR128, VPR128> {
7170     let Inst{11} = {Index{0}};
7171     let Inst{21} = 0b0;
7172     let Inst{20-16} = Re;
7173   }
7174 }
7175
7176 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
7177 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
7178
7179 // Pattern for lane in 128-bit vector
7180 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7181                        RegisterOperand ResVPR, RegisterOperand OpVPR,
7182                        ValueType ResTy, ValueType OpTy,
7183                        SDPatternOperator coreop>
7184   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7185                    (ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
7186         (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
7187
7188 // Pattern for lane 0
7189 class NI_2VEfma_lane0<Instruction INST, SDPatternOperator op,
7190                       RegisterOperand ResVPR, ValueType ResTy>
7191   : Pat<(ResTy (op (ResTy ResVPR:$Rn),
7192                    (ResTy (Neon_vdup (f32 FPR32:$Re))),
7193                    (ResTy ResVPR:$src))),
7194         (INST ResVPR:$src, ResVPR:$Rn,
7195               (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7196
7197 // Pattern for lane in 64-bit vector
7198 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7199                       RegisterOperand ResVPR, RegisterOperand OpVPR,
7200                       ValueType ResTy, ValueType OpTy,
7201                       SDPatternOperator coreop>
7202   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7203                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7204         (INST ResVPR:$src, ResVPR:$Rn,
7205           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
7206
7207 // Pattern for lane in 64-bit vector
7208 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
7209                            SDPatternOperator op,
7210                            RegisterOperand ResVPR, RegisterOperand OpVPR,
7211                            ValueType ResTy, ValueType OpTy,
7212                            SDPatternOperator coreop>
7213   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
7214                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7215         (INST ResVPR:$src, ResVPR:$Rn,
7216           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
7217
7218
7219 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
7220   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7221                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7222                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7223
7224   def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_2s4s"),
7225                         op, VPR64, v2f32>;
7226
7227   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7228                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7229                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7230
7231   def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_4s4s"),
7232                         op, VPR128, v4f32>;
7233
7234   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7235                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7236                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7237
7238   // Index can only be half of the max value for lane in 64-bit vector
7239
7240   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7241                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7242                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7243
7244   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7245                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7246                              BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7247 }
7248
7249 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
7250
7251 // Pattern for lane 0
7252 class NI_2VEfms_lane0<Instruction INST, SDPatternOperator op,
7253                       RegisterOperand ResVPR, ValueType ResTy>
7254   : Pat<(ResTy (op (ResTy (fneg ResVPR:$Rn)),
7255                    (ResTy (Neon_vdup (f32 FPR32:$Re))),
7256                    (ResTy ResVPR:$src))),
7257         (INST ResVPR:$src, ResVPR:$Rn,
7258               (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7259
7260 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
7261 {
7262   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7263                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7264                          BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7265
7266   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7267                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7268                          BinOpFrag<(Neon_vduplane
7269                                      (fneg node:$LHS), node:$RHS)>>;
7270
7271   def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_2s4s"),
7272                         op, VPR64, v2f32>;
7273
7274   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7275                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7276                          BinOpFrag<(fneg (Neon_vduplane
7277                                      node:$LHS, node:$RHS))>>;
7278
7279   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7280                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7281                          BinOpFrag<(Neon_vduplane
7282                                      (fneg node:$LHS), node:$RHS)>>;
7283
7284   def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_4s4s"),
7285                         op, VPR128, v4f32>;
7286
7287   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7288                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7289                          BinOpFrag<(fneg (Neon_vduplane
7290                                      node:$LHS, node:$RHS))>>;
7291
7292   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7293                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7294                          BinOpFrag<(Neon_vduplane
7295                                      (fneg node:$LHS), node:$RHS)>>;
7296
7297   // Index can only be half of the max value for lane in 64-bit vector
7298
7299   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7300                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7301                         BinOpFrag<(fneg (Neon_vduplane
7302                                     node:$LHS, node:$RHS))>>;
7303
7304   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7305                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7306                         BinOpFrag<(Neon_vduplane
7307                                     (fneg node:$LHS), node:$RHS)>>;
7308
7309   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7310                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7311                         BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7312
7313   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7314                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7315                         BinOpFrag<(Neon_vduplane (fneg node:$LHS), node:$RHS)>>;
7316
7317   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7318                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7319                              BinOpFrag<(fneg (Neon_combine_2d
7320                                          node:$LHS, node:$RHS))>>;
7321
7322   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7323                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7324                              BinOpFrag<(Neon_combine_2d
7325                                          (fneg node:$LHS), (fneg node:$RHS))>>;
7326 }
7327
7328 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
7329
7330 // Variant 3: Long type
7331 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
7332 //      SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
7333
7334 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
7335   // vector register class for element is always 128-bit to cover the max index
7336   def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7337                      neon_uimm2_bare, VPR128, VPR64, VPR128> {
7338     let Inst{11} = {Index{1}};
7339     let Inst{21} = {Index{0}};
7340     let Inst{20-16} = Re;
7341   }
7342
7343   def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7344                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
7345     let Inst{11} = {Index{1}};
7346     let Inst{21} = {Index{0}};
7347     let Inst{20-16} = Re;
7348   }
7349
7350   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7351   def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7352                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7353     let Inst{11} = {Index{2}};
7354     let Inst{21} = {Index{1}};
7355     let Inst{20} = {Index{0}};
7356     let Inst{19-16} = Re{3-0};
7357   }
7358
7359   def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7360                      neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7361     let Inst{11} = {Index{2}};
7362     let Inst{21} = {Index{1}};
7363     let Inst{20} = {Index{0}};
7364     let Inst{19-16} = Re{3-0};
7365   }
7366 }
7367
7368 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
7369 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
7370 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
7371 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
7372 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
7373 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
7374
7375 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
7376   // vector register class for element is always 128-bit to cover the max index
7377   def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7378                          neon_uimm2_bare, VPR128, VPR64, VPR128> {
7379     let Inst{11} = {Index{1}};
7380     let Inst{21} = {Index{0}};
7381     let Inst{20-16} = Re;
7382   }
7383
7384   def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7385                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7386     let Inst{11} = {Index{1}};
7387     let Inst{21} = {Index{0}};
7388     let Inst{20-16} = Re;
7389   }
7390
7391   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7392   def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7393                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7394     let Inst{11} = {Index{2}};
7395     let Inst{21} = {Index{1}};
7396     let Inst{20} = {Index{0}};
7397     let Inst{19-16} = Re{3-0};
7398   }
7399
7400   def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7401                          neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7402     let Inst{11} = {Index{2}};
7403     let Inst{21} = {Index{1}};
7404     let Inst{20} = {Index{0}};
7405     let Inst{19-16} = Re{3-0};
7406   }
7407 }
7408
7409 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
7410 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
7411 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
7412
7413 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7414           (FMOVdd $src)>;
7415 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$src))),
7416           (FMOVss $src)>;
7417
7418 // Pattern for lane in 128-bit vector
7419 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7420                      RegisterOperand EleOpVPR, ValueType ResTy,
7421                      ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7422                      SDPatternOperator hiop>
7423   : Pat<(ResTy (op (ResTy VPR128:$src),
7424           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7425           (HalfOpTy (Neon_vduplane
7426                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7427         (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7428
7429 // Pattern for lane in 64-bit vector
7430 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7431                     RegisterOperand EleOpVPR, ValueType ResTy,
7432                     ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7433                     SDPatternOperator hiop>
7434   : Pat<(ResTy (op (ResTy VPR128:$src),
7435           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7436           (HalfOpTy (Neon_vduplane
7437                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7438         (INST VPR128:$src, VPR128:$Rn,
7439           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7440
7441 class NI_2VEL2_lane0<Instruction INST, SDPatternOperator op,
7442                      ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7443                      SDPatternOperator hiop, Instruction DupInst>
7444   : Pat<(ResTy (op (ResTy VPR128:$src),
7445           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7446           (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7447         (INST VPR128:$src, VPR128:$Rn, (DupInst $Re), 0)>;
7448
7449 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
7450   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7451                      op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7452
7453   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7454                      op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32>;
7455
7456   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7457                        op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7458
7459   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7460                        op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7461
7462   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7463                        op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7464
7465   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7466                        op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7467
7468   // Index can only be half of the max value for lane in 64-bit vector
7469
7470   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7471                     op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7472
7473   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7474                     op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32>;
7475
7476   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7477                       op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7478
7479   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7480                       op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7481 }
7482
7483 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
7484 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
7485 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
7486 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
7487
7488 // Pattern for lane in 128-bit vector
7489 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7490                          RegisterOperand EleOpVPR, ValueType ResTy,
7491                          ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7492                          SDPatternOperator hiop>
7493   : Pat<(ResTy (op
7494           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7495           (HalfOpTy (Neon_vduplane
7496                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7497         (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7498
7499 // Pattern for lane in 64-bit vector
7500 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7501                         RegisterOperand EleOpVPR, ValueType ResTy,
7502                         ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7503                         SDPatternOperator hiop>
7504   : Pat<(ResTy (op
7505           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7506           (HalfOpTy (Neon_vduplane
7507                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7508         (INST VPR128:$Rn,
7509           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7510
7511 // Pattern for fixed lane 0
7512 class NI_2VEL2_mul_lane0<Instruction INST, SDPatternOperator op,
7513                          ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7514                          SDPatternOperator hiop, Instruction DupInst>
7515   : Pat<(ResTy (op
7516           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7517           (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7518         (INST VPR128:$Rn, (DupInst $Re), 0)>;
7519
7520 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
7521   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7522                          op, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7523
7524   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7525                          op, VPR64, VPR128, v2i64, v2i32, v4i32>;
7526
7527   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7528                          op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7529
7530   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7531                            op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7532
7533   def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_4s8h"),
7534                            op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7535
7536   def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_2d4s"),
7537                            op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7538
7539   // Index can only be half of the max value for lane in 64-bit vector
7540
7541   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7542                         op, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7543
7544   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7545                         op, VPR64, VPR64, v2i64, v2i32, v2i32>;
7546
7547   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7548                           op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7549
7550   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7551                           op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7552 }
7553
7554 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
7555 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
7556 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
7557
7558 multiclass NI_qdma<SDPatternOperator op> {
7559   def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7560                     (op node:$Ra,
7561                       (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7562
7563   def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7564                     (op node:$Ra,
7565                       (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7566 }
7567
7568 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
7569 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
7570
7571 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
7572   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7573                      !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
7574                      v4i32, v4i16, v8i16>;
7575
7576   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7577                      !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
7578                      v2i64, v2i32, v4i32>;
7579
7580   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7581                        !cast<PatFrag>(op # "_4s"), VPR128Lo,
7582                        v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7583
7584   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7585                        !cast<PatFrag>(op # "_2d"), VPR128,
7586                        v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7587
7588   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7589                        !cast<PatFrag>(op # "_4s"),
7590                        v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7591
7592   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7593                        !cast<PatFrag>(op # "_2d"),
7594                        v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7595
7596   // Index can only be half of the max value for lane in 64-bit vector
7597
7598   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7599                     !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
7600                     v4i32, v4i16, v4i16>;
7601
7602   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7603                     !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
7604                     v2i64, v2i32, v2i32>;
7605
7606   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7607                       !cast<PatFrag>(op # "_4s"), VPR64Lo,
7608                       v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7609
7610   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7611                       !cast<PatFrag>(op # "_2d"), VPR64,
7612                       v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7613 }
7614
7615 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
7616 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
7617
7618 // End of implementation for instruction class (3V Elem)
7619
7620 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7621                 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7622                 SDPatternOperator Neon_Rev>
7623   : NeonI_2VMisc<Q, U, size, opcode,
7624                (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7625                asmop # "\t$Rd." # Res # ", $Rn." # Res,
7626                [(set (ResTy ResVPR:$Rd),
7627                   (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7628                NoItinerary> ;
7629
7630 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7631                           v16i8, Neon_rev64>;
7632 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7633                          v8i16, Neon_rev64>;
7634 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7635                          v4i32, Neon_rev64>;
7636 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7637                          v8i8, Neon_rev64>;
7638 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7639                          v4i16, Neon_rev64>;
7640 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7641                          v2i32, Neon_rev64>;
7642
7643 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7644 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7645
7646 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7647                           v16i8, Neon_rev32>;
7648 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7649                           v8i16, Neon_rev32>;
7650 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7651                          v8i8, Neon_rev32>;
7652 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7653                          v4i16, Neon_rev32>;
7654
7655 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7656                           v16i8, Neon_rev16>;
7657 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7658                          v8i8, Neon_rev16>;
7659
7660 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7661                              SDPatternOperator Neon_Padd> {
7662   def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7663                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7664                            asmop # "\t$Rd.8h, $Rn.16b",
7665                            [(set (v8i16 VPR128:$Rd),
7666                               (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7667                            NoItinerary>;
7668
7669   def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7670                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7671                           asmop # "\t$Rd.4h, $Rn.8b",
7672                           [(set (v4i16 VPR64:$Rd),
7673                              (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7674                           NoItinerary>;
7675
7676   def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7677                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7678                            asmop # "\t$Rd.4s, $Rn.8h",
7679                            [(set (v4i32 VPR128:$Rd),
7680                               (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7681                            NoItinerary>;
7682
7683   def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7684                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7685                           asmop # "\t$Rd.2s, $Rn.4h",
7686                           [(set (v2i32 VPR64:$Rd),
7687                              (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7688                           NoItinerary>;
7689
7690   def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7691                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7692                            asmop # "\t$Rd.2d, $Rn.4s",
7693                            [(set (v2i64 VPR128:$Rd),
7694                               (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7695                            NoItinerary>;
7696
7697   def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7698                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7699                           asmop # "\t$Rd.1d, $Rn.2s",
7700                           [(set (v1i64 VPR64:$Rd),
7701                              (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7702                           NoItinerary>;
7703 }
7704
7705 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7706                                 int_arm_neon_vpaddls>;
7707 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7708                                 int_arm_neon_vpaddlu>;
7709
7710 def : Pat<(v1i64 (int_aarch64_neon_saddlv (v2i32 VPR64:$Rn))),
7711           (SADDLP2s1d $Rn)>;
7712 def : Pat<(v1i64 (int_aarch64_neon_uaddlv (v2i32 VPR64:$Rn))),
7713           (UADDLP2s1d $Rn)>;
7714
7715 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7716                              SDPatternOperator Neon_Padd> {
7717   let Constraints = "$src = $Rd" in {
7718     def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7719                              (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7720                              asmop # "\t$Rd.8h, $Rn.16b",
7721                              [(set (v8i16 VPR128:$Rd),
7722                                 (v8i16 (Neon_Padd
7723                                   (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7724                              NoItinerary>;
7725
7726     def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7727                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7728                             asmop # "\t$Rd.4h, $Rn.8b",
7729                             [(set (v4i16 VPR64:$Rd),
7730                                (v4i16 (Neon_Padd
7731                                  (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7732                             NoItinerary>;
7733
7734     def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7735                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7736                             asmop # "\t$Rd.4s, $Rn.8h",
7737                             [(set (v4i32 VPR128:$Rd),
7738                                (v4i32 (Neon_Padd
7739                                  (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7740                             NoItinerary>;
7741
7742     def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7743                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7744                             asmop # "\t$Rd.2s, $Rn.4h",
7745                             [(set (v2i32 VPR64:$Rd),
7746                                (v2i32 (Neon_Padd
7747                                  (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7748                             NoItinerary>;
7749
7750     def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7751                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7752                             asmop # "\t$Rd.2d, $Rn.4s",
7753                             [(set (v2i64 VPR128:$Rd),
7754                                (v2i64 (Neon_Padd
7755                                  (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7756                             NoItinerary>;
7757
7758     def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7759                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7760                             asmop # "\t$Rd.1d, $Rn.2s",
7761                             [(set (v1i64 VPR64:$Rd),
7762                                (v1i64 (Neon_Padd
7763                                  (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7764                             NoItinerary>;
7765   }
7766 }
7767
7768 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7769                                    int_arm_neon_vpadals>;
7770 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
7771                                    int_arm_neon_vpadalu>;
7772
7773 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
7774   def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7775                          (outs VPR128:$Rd), (ins VPR128:$Rn),
7776                          asmop # "\t$Rd.16b, $Rn.16b",
7777                          [], NoItinerary>;
7778
7779   def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7780                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7781                         asmop # "\t$Rd.8h, $Rn.8h",
7782                         [], NoItinerary>;
7783
7784   def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7785                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7786                         asmop # "\t$Rd.4s, $Rn.4s",
7787                         [], NoItinerary>;
7788
7789   def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7790                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7791                         asmop # "\t$Rd.2d, $Rn.2d",
7792                         [], NoItinerary>;
7793
7794   def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7795                          (outs VPR64:$Rd), (ins VPR64:$Rn),
7796                          asmop # "\t$Rd.8b, $Rn.8b",
7797                          [], NoItinerary>;
7798
7799   def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7800                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7801                         asmop # "\t$Rd.4h, $Rn.4h",
7802                         [], NoItinerary>;
7803
7804   def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7805                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7806                         asmop # "\t$Rd.2s, $Rn.2s",
7807                         [], NoItinerary>;
7808 }
7809
7810 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
7811 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
7812 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
7813 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
7814
7815 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
7816                                           SDPatternOperator Neon_Op> {
7817   def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
7818             (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
7819
7820   def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
7821             (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
7822
7823   def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
7824             (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
7825
7826   def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
7827             (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
7828
7829   def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
7830             (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
7831
7832   def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
7833             (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
7834
7835   def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
7836             (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
7837 }
7838
7839 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
7840 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
7841 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
7842
7843 def : Pat<(v16i8 (sub
7844             (v16i8 Neon_AllZero),
7845             (v16i8 VPR128:$Rn))),
7846           (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
7847 def : Pat<(v8i8 (sub
7848             (v8i8 Neon_AllZero),
7849             (v8i8 VPR64:$Rn))),
7850           (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
7851 def : Pat<(v8i16 (sub
7852             (v8i16 (bitconvert (v16i8 Neon_AllZero))),
7853             (v8i16 VPR128:$Rn))),
7854           (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
7855 def : Pat<(v4i16 (sub
7856             (v4i16 (bitconvert (v8i8 Neon_AllZero))),
7857             (v4i16 VPR64:$Rn))),
7858           (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
7859 def : Pat<(v4i32 (sub
7860             (v4i32 (bitconvert (v16i8 Neon_AllZero))),
7861             (v4i32 VPR128:$Rn))),
7862           (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
7863 def : Pat<(v2i32 (sub
7864             (v2i32 (bitconvert (v8i8 Neon_AllZero))),
7865             (v2i32 VPR64:$Rn))),
7866           (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
7867 def : Pat<(v2i64 (sub
7868             (v2i64 (bitconvert (v16i8 Neon_AllZero))),
7869             (v2i64 VPR128:$Rn))),
7870           (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
7871
7872 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
7873   let Constraints = "$src = $Rd" in {
7874     def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7875                            (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7876                            asmop # "\t$Rd.16b, $Rn.16b",
7877                            [], NoItinerary>;
7878
7879     def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7880                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7881                           asmop # "\t$Rd.8h, $Rn.8h",
7882                           [], NoItinerary>;
7883
7884     def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7885                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7886                           asmop # "\t$Rd.4s, $Rn.4s",
7887                           [], NoItinerary>;
7888
7889     def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7890                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7891                           asmop # "\t$Rd.2d, $Rn.2d",
7892                           [], NoItinerary>;
7893
7894     def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7895                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7896                           asmop # "\t$Rd.8b, $Rn.8b",
7897                           [], NoItinerary>;
7898
7899     def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7900                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7901                           asmop # "\t$Rd.4h, $Rn.4h",
7902                           [], NoItinerary>;
7903
7904     def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7905                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7906                           asmop # "\t$Rd.2s, $Rn.2s",
7907                           [], NoItinerary>;
7908   }
7909 }
7910
7911 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
7912 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
7913
7914 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
7915                                            SDPatternOperator Neon_Op> {
7916   def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
7917             (v16i8 (!cast<Instruction>(Prefix # 16b)
7918               (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
7919
7920   def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
7921             (v8i16 (!cast<Instruction>(Prefix # 8h)
7922               (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
7923
7924   def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
7925             (v4i32 (!cast<Instruction>(Prefix # 4s)
7926               (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
7927
7928   def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
7929             (v2i64 (!cast<Instruction>(Prefix # 2d)
7930               (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
7931
7932   def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
7933             (v8i8 (!cast<Instruction>(Prefix # 8b)
7934               (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
7935
7936   def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
7937             (v4i16 (!cast<Instruction>(Prefix # 4h)
7938               (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
7939
7940   def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
7941             (v2i32 (!cast<Instruction>(Prefix # 2s)
7942               (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
7943 }
7944
7945 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
7946 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
7947
7948 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
7949                           SDPatternOperator Neon_Op> {
7950   def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
7951                          (outs VPR128:$Rd), (ins VPR128:$Rn),
7952                          asmop # "\t$Rd.16b, $Rn.16b",
7953                          [(set (v16i8 VPR128:$Rd),
7954                             (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
7955                          NoItinerary>;
7956
7957   def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
7958                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7959                         asmop # "\t$Rd.8h, $Rn.8h",
7960                         [(set (v8i16 VPR128:$Rd),
7961                            (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
7962                         NoItinerary>;
7963
7964   def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
7965                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7966                         asmop # "\t$Rd.4s, $Rn.4s",
7967                         [(set (v4i32 VPR128:$Rd),
7968                            (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
7969                         NoItinerary>;
7970
7971   def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
7972                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7973                         asmop # "\t$Rd.8b, $Rn.8b",
7974                         [(set (v8i8 VPR64:$Rd),
7975                            (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
7976                         NoItinerary>;
7977
7978   def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
7979                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7980                         asmop # "\t$Rd.4h, $Rn.4h",
7981                         [(set (v4i16 VPR64:$Rd),
7982                            (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
7983                         NoItinerary>;
7984
7985   def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
7986                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7987                         asmop # "\t$Rd.2s, $Rn.2s",
7988                         [(set (v2i32 VPR64:$Rd),
7989                            (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
7990                         NoItinerary>;
7991 }
7992
7993 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
7994 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
7995
7996 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
7997                               bits<5> Opcode> {
7998   def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
7999                          (outs VPR128:$Rd), (ins VPR128:$Rn),
8000                          asmop # "\t$Rd.16b, $Rn.16b",
8001                          [], NoItinerary>;
8002
8003   def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
8004                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8005                         asmop # "\t$Rd.8b, $Rn.8b",
8006                         [], NoItinerary>;
8007 }
8008
8009 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
8010 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
8011 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
8012
8013 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
8014                     (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
8015 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
8016                     (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
8017
8018 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
8019           (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
8020 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
8021           (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
8022
8023 def : Pat<(v16i8 (xor
8024             (v16i8 VPR128:$Rn),
8025             (v16i8 Neon_AllOne))),
8026           (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
8027 def : Pat<(v8i8 (xor
8028             (v8i8 VPR64:$Rn),
8029             (v8i8 Neon_AllOne))),
8030           (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
8031 def : Pat<(v8i16 (xor
8032             (v8i16 VPR128:$Rn),
8033             (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
8034           (NOT16b VPR128:$Rn)>;
8035 def : Pat<(v4i16 (xor
8036             (v4i16 VPR64:$Rn),
8037             (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
8038           (NOT8b VPR64:$Rn)>;
8039 def : Pat<(v4i32 (xor
8040             (v4i32 VPR128:$Rn),
8041             (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
8042           (NOT16b VPR128:$Rn)>;
8043 def : Pat<(v2i32 (xor
8044             (v2i32 VPR64:$Rn),
8045             (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
8046           (NOT8b VPR64:$Rn)>;
8047 def : Pat<(v2i64 (xor
8048             (v2i64 VPR128:$Rn),
8049             (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
8050           (NOT16b VPR128:$Rn)>;
8051
8052 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
8053           (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
8054 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
8055           (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
8056
8057 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
8058                                 SDPatternOperator Neon_Op> {
8059   def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8060                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8061                         asmop # "\t$Rd.4s, $Rn.4s",
8062                         [(set (v4f32 VPR128:$Rd),
8063                            (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
8064                         NoItinerary>;
8065
8066   def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8067                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8068                         asmop # "\t$Rd.2d, $Rn.2d",
8069                         [(set (v2f64 VPR128:$Rd),
8070                            (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
8071                         NoItinerary>;
8072
8073   def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8074                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8075                         asmop # "\t$Rd.2s, $Rn.2s",
8076                         [(set (v2f32 VPR64:$Rd),
8077                            (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
8078                         NoItinerary>;
8079 }
8080
8081 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
8082 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
8083
8084 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
8085   def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8086                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8087                           asmop # "\t$Rd.8b, $Rn.8h",
8088                           [], NoItinerary>;
8089
8090   def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8091                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8092                           asmop # "\t$Rd.4h, $Rn.4s",
8093                           [], NoItinerary>;
8094
8095   def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8096                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8097                           asmop # "\t$Rd.2s, $Rn.2d",
8098                           [], NoItinerary>;
8099
8100   let Constraints = "$Rd = $src" in {
8101     def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8102                              (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8103                              asmop # "2\t$Rd.16b, $Rn.8h",
8104                              [], NoItinerary>;
8105
8106     def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8107                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8108                             asmop # "2\t$Rd.8h, $Rn.4s",
8109                             [], NoItinerary>;
8110
8111     def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8112                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8113                             asmop # "2\t$Rd.4s, $Rn.2d",
8114                             [], NoItinerary>;
8115   }
8116 }
8117
8118 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
8119 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
8120 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
8121 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
8122
8123 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
8124                                         SDPatternOperator Neon_Op> {
8125   def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
8126             (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
8127
8128   def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
8129             (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
8130
8131   def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
8132             (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
8133
8134   def : Pat<(v16i8 (concat_vectors
8135               (v8i8 VPR64:$src),
8136               (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
8137             (!cast<Instruction>(Prefix # 8h16b)
8138               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8139               VPR128:$Rn)>;
8140
8141   def : Pat<(v8i16 (concat_vectors
8142               (v4i16 VPR64:$src),
8143               (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
8144             (!cast<Instruction>(Prefix # 4s8h)
8145               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8146               VPR128:$Rn)>;
8147
8148   def : Pat<(v4i32 (concat_vectors
8149               (v2i32 VPR64:$src),
8150               (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
8151             (!cast<Instruction>(Prefix # 2d4s)
8152               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8153               VPR128:$Rn)>;
8154 }
8155
8156 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
8157 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
8158 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
8159 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
8160
8161 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
8162   let DecoderMethod = "DecodeSHLLInstruction" in {
8163     def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8164                             (outs VPR128:$Rd),
8165                             (ins VPR64:$Rn, uimm_exact8:$Imm),
8166                             asmop # "\t$Rd.8h, $Rn.8b, $Imm",
8167                             [], NoItinerary>;
8168
8169     def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8170                             (outs VPR128:$Rd),
8171                             (ins VPR64:$Rn, uimm_exact16:$Imm),
8172                             asmop # "\t$Rd.4s, $Rn.4h, $Imm",
8173                             [], NoItinerary>;
8174
8175     def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
8176                             (outs VPR128:$Rd),
8177                             (ins VPR64:$Rn, uimm_exact32:$Imm),
8178                             asmop # "\t$Rd.2d, $Rn.2s, $Imm",
8179                             [], NoItinerary>;
8180
8181     def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8182                             (outs VPR128:$Rd),
8183                             (ins VPR128:$Rn, uimm_exact8:$Imm),
8184                             asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
8185                             [], NoItinerary>;
8186
8187     def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8188                             (outs VPR128:$Rd),
8189                             (ins VPR128:$Rn, uimm_exact16:$Imm),
8190                             asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
8191                             [], NoItinerary>;
8192
8193     def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
8194                             (outs VPR128:$Rd),
8195                             (ins VPR128:$Rn, uimm_exact32:$Imm),
8196                             asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
8197                             [], NoItinerary>;
8198   }
8199 }
8200
8201 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
8202
8203 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
8204                           SDPatternOperator ExtOp, Operand Neon_Imm,
8205                           string suffix>
8206   : Pat<(DesTy (shl
8207           (DesTy (ExtOp (OpTy VPR64:$Rn))),
8208             (DesTy (Neon_vdup
8209               (i32 Neon_Imm:$Imm))))),
8210         (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
8211
8212 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
8213                                SDPatternOperator ExtOp, Operand Neon_Imm,
8214                                string suffix, PatFrag GetHigh>
8215   : Pat<(DesTy (shl
8216           (DesTy (ExtOp
8217             (OpTy (GetHigh VPR128:$Rn)))),
8218               (DesTy (Neon_vdup
8219                 (i32 Neon_Imm:$Imm))))),
8220         (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
8221
8222 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
8223 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
8224 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
8225 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
8226 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
8227 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
8228 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
8229                                Neon_High16B>;
8230 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
8231                                Neon_High16B>;
8232 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
8233                                Neon_High8H>;
8234 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
8235                                Neon_High8H>;
8236 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
8237                                Neon_High4S>;
8238 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
8239                                Neon_High4S>;
8240
8241 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
8242   def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8243                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8244                           asmop # "\t$Rd.4h, $Rn.4s",
8245                           [], NoItinerary>;
8246
8247   def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8248                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8249                           asmop # "\t$Rd.2s, $Rn.2d",
8250                           [], NoItinerary>;
8251
8252   let Constraints = "$src = $Rd" in {
8253     def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8254                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8255                             asmop # "2\t$Rd.8h, $Rn.4s",
8256                             [], NoItinerary>;
8257
8258     def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8259                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8260                             asmop # "2\t$Rd.4s, $Rn.2d",
8261                             [], NoItinerary>;
8262   }
8263 }
8264
8265 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8266
8267 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8268                                        SDPatternOperator f32_to_f16_Op,
8269                                        SDPatternOperator f64_to_f32_Op> {
8270
8271   def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8272               (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8273
8274   def : Pat<(v8i16 (concat_vectors
8275                 (v4i16 VPR64:$src),
8276                 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8277                   (!cast<Instruction>(prefix # "4s8h")
8278                     (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8279                     (v4f32 VPR128:$Rn))>;
8280
8281   def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8282             (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8283
8284   def : Pat<(v4f32 (concat_vectors
8285               (v2f32 VPR64:$src),
8286               (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8287                 (!cast<Instruction>(prefix # "2d4s")
8288                   (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8289                   (v2f64 VPR128:$Rn))>;
8290 }
8291
8292 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8293
8294 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8295                                  bits<5> opcode> {
8296   def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8297                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8298                           asmop # "\t$Rd.2s, $Rn.2d",
8299                           [], NoItinerary>;
8300
8301   def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8302                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8303                           asmop # "2\t$Rd.4s, $Rn.2d",
8304                           [], NoItinerary> {
8305     let Constraints = "$src = $Rd";
8306   }
8307
8308   def : Pat<(v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))),
8309             (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8310
8311   def : Pat<(v4f32 (concat_vectors
8312               (v2f32 VPR64:$src),
8313               (v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))))),
8314             (!cast<Instruction>(prefix # "2d4s")
8315                (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8316                VPR128:$Rn)>;
8317 }
8318
8319 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8320
8321 def Neon_High4Float : PatFrag<(ops node:$in),
8322                               (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8323
8324 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8325   def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8326                           (outs VPR128:$Rd), (ins VPR64:$Rn),
8327                           asmop # "\t$Rd.4s, $Rn.4h",
8328                           [], NoItinerary>;
8329
8330   def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8331                           (outs VPR128:$Rd), (ins VPR64:$Rn),
8332                           asmop # "\t$Rd.2d, $Rn.2s",
8333                           [], NoItinerary>;
8334
8335   def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8336                           (outs VPR128:$Rd), (ins VPR128:$Rn),
8337                           asmop # "2\t$Rd.4s, $Rn.8h",
8338                           [], NoItinerary>;
8339
8340   def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8341                           (outs VPR128:$Rd), (ins VPR128:$Rn),
8342                           asmop # "2\t$Rd.2d, $Rn.4s",
8343                           [], NoItinerary>;
8344 }
8345
8346 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8347
8348 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8349   def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8350             (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8351
8352   def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8353               (v4i16 (Neon_High8H
8354                 (v8i16 VPR128:$Rn))))),
8355             (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8356
8357   def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8358             (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8359
8360   def : Pat<(v2f64 (fextend
8361               (v2f32 (Neon_High4Float
8362                 (v4f32 VPR128:$Rn))))),
8363             (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8364 }
8365
8366 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8367
8368 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8369                                 ValueType ResTy4s, ValueType OpTy4s,
8370                                 ValueType ResTy2d, ValueType OpTy2d,
8371                                 ValueType ResTy2s, ValueType OpTy2s,
8372                                 SDPatternOperator Neon_Op> {
8373
8374   def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8375                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8376                         asmop # "\t$Rd.4s, $Rn.4s",
8377                         [(set (ResTy4s VPR128:$Rd),
8378                            (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8379                         NoItinerary>;
8380
8381   def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8382                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8383                         asmop # "\t$Rd.2d, $Rn.2d",
8384                         [(set (ResTy2d VPR128:$Rd),
8385                            (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8386                         NoItinerary>;
8387
8388   def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8389                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8390                         asmop # "\t$Rd.2s, $Rn.2s",
8391                         [(set (ResTy2s VPR64:$Rd),
8392                            (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8393                         NoItinerary>;
8394 }
8395
8396 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8397                                   bits<5> opcode, SDPatternOperator Neon_Op> {
8398   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8399                                 v2f64, v2i32, v2f32, Neon_Op>;
8400 }
8401
8402 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8403                                      int_arm_neon_vcvtns>;
8404 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8405                                      int_arm_neon_vcvtnu>;
8406 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8407                                      int_arm_neon_vcvtps>;
8408 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8409                                      int_arm_neon_vcvtpu>;
8410 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8411                                      int_arm_neon_vcvtms>;
8412 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8413                                      int_arm_neon_vcvtmu>;
8414 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8415 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8416 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8417                                      int_arm_neon_vcvtas>;
8418 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8419                                      int_arm_neon_vcvtau>;
8420
8421 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8422                                   bits<5> opcode, SDPatternOperator Neon_Op> {
8423   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8424                                 v2i64, v2f32, v2i32, Neon_Op>;
8425 }
8426
8427 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8428 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8429
8430 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8431                                  bits<5> opcode, SDPatternOperator Neon_Op> {
8432   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8433                                 v2f64, v2f32, v2f32, Neon_Op>;
8434 }
8435
8436 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8437                                      int_aarch64_neon_frintn>;
8438 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8439 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8440 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8441 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8442 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8443 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8444 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8445                                     int_arm_neon_vrecpe>;
8446 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8447                                      int_arm_neon_vrsqrte>;
8448 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111, fsqrt>;
8449
8450 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8451                                bits<5> opcode, SDPatternOperator Neon_Op> {
8452   def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8453                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8454                         asmop # "\t$Rd.4s, $Rn.4s",
8455                         [(set (v4i32 VPR128:$Rd),
8456                            (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8457                         NoItinerary>;
8458
8459   def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8460                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8461                         asmop # "\t$Rd.2s, $Rn.2s",
8462                         [(set (v2i32 VPR64:$Rd),
8463                            (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8464                         NoItinerary>;
8465 }
8466
8467 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8468                                   int_arm_neon_vrecpe>;
8469 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8470                                    int_arm_neon_vrsqrte>;
8471
8472 // Crypto Class
8473 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8474                          string asmop, SDPatternOperator opnode>
8475   : NeonI_Crypto_AES<size, opcode,
8476                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8477                      asmop # "\t$Rd.16b, $Rn.16b",
8478                      [(set (v16i8 VPR128:$Rd),
8479                         (v16i8 (opnode (v16i8 VPR128:$src),
8480                                        (v16i8 VPR128:$Rn))))],
8481                      NoItinerary>{
8482   let Constraints = "$src = $Rd";
8483   let Predicates = [HasNEON, HasCrypto];
8484 }
8485
8486 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8487 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8488
8489 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8490                       string asmop, SDPatternOperator opnode>
8491   : NeonI_Crypto_AES<size, opcode,
8492                      (outs VPR128:$Rd), (ins VPR128:$Rn),
8493                      asmop # "\t$Rd.16b, $Rn.16b",
8494                      [(set (v16i8 VPR128:$Rd),
8495                         (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8496                      NoItinerary>;
8497
8498 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8499 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8500
8501 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8502                          string asmop, SDPatternOperator opnode>
8503   : NeonI_Crypto_SHA<size, opcode,
8504                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8505                      asmop # "\t$Rd.4s, $Rn.4s",
8506                      [(set (v4i32 VPR128:$Rd),
8507                         (v4i32 (opnode (v4i32 VPR128:$src),
8508                                        (v4i32 VPR128:$Rn))))],
8509                      NoItinerary> {
8510   let Constraints = "$src = $Rd";
8511   let Predicates = [HasNEON, HasCrypto];
8512 }
8513
8514 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8515                                  int_arm_neon_sha1su1>;
8516 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8517                                    int_arm_neon_sha256su0>;
8518
8519 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8520                          string asmop, SDPatternOperator opnode>
8521   : NeonI_Crypto_SHA<size, opcode,
8522                      (outs FPR32:$Rd), (ins FPR32:$Rn),
8523                      asmop # "\t$Rd, $Rn",
8524                      [(set (v1i32 FPR32:$Rd),
8525                         (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8526                      NoItinerary> {
8527   let Predicates = [HasNEON, HasCrypto];
8528 }
8529
8530 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8531
8532 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8533                            SDPatternOperator opnode>
8534   : NeonI_Crypto_3VSHA<size, opcode,
8535                        (outs VPR128:$Rd),
8536                        (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8537                        asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8538                        [(set (v4i32 VPR128:$Rd),
8539                           (v4i32 (opnode (v4i32 VPR128:$src),
8540                                          (v4i32 VPR128:$Rn),
8541                                          (v4i32 VPR128:$Rm))))],
8542                        NoItinerary> {
8543   let Constraints = "$src = $Rd";
8544   let Predicates = [HasNEON, HasCrypto];
8545 }
8546
8547 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8548                                    int_arm_neon_sha1su0>;
8549 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8550                                      int_arm_neon_sha256su1>;
8551
8552 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8553                            SDPatternOperator opnode>
8554   : NeonI_Crypto_3VSHA<size, opcode,
8555                        (outs FPR128:$Rd),
8556                        (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8557                        asmop # "\t$Rd, $Rn, $Rm.4s",
8558                        [(set (v4i32 FPR128:$Rd),
8559                           (v4i32 (opnode (v4i32 FPR128:$src),
8560                                          (v4i32 FPR128:$Rn),
8561                                          (v4i32 VPR128:$Rm))))],
8562                        NoItinerary> {
8563   let Constraints = "$src = $Rd";
8564   let Predicates = [HasNEON, HasCrypto];
8565 }
8566
8567 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8568                                    int_arm_neon_sha256h>;
8569 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8570                                     int_arm_neon_sha256h2>;
8571
8572 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8573                            SDPatternOperator opnode>
8574   : NeonI_Crypto_3VSHA<size, opcode,
8575                        (outs FPR128:$Rd),
8576                        (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8577                        asmop # "\t$Rd, $Rn, $Rm.4s",
8578                        [(set (v4i32 FPR128:$Rd),
8579                           (v4i32 (opnode (v4i32 FPR128:$src),
8580                                          (v1i32 FPR32:$Rn),
8581                                          (v4i32 VPR128:$Rm))))],
8582                        NoItinerary> {
8583   let Constraints = "$src = $Rd";
8584   let Predicates = [HasNEON, HasCrypto];
8585 }
8586
8587 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8588 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8589 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
8590
8591 //
8592 // Patterns for handling half-precision values
8593 //
8594
8595 // Convert f16 value coming in as i16 value to f32
8596 def : Pat<(f32 (f16_to_f32 (i32 (and (i32 GPR32:$Rn), 65535)))),
8597           (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8598 def : Pat<(f32 (f16_to_f32 (i32 (assertzext GPR32:$Rn)))),
8599           (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8600
8601 def : Pat<(f32 (f16_to_f32 (i32 (assertzext (i32 (
8602             f32_to_f16 (f32 FPR32:$Rn))))))),
8603           (f32 FPR32:$Rn)>;
8604
8605 // Patterns for vector extract of half-precision FP value in i16 storage type
8606 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8607             (v4i16 VPR64:$Rn), neon_uimm2_bare:$Imm)), 65535)))),
8608           (FCVTsh (f16 (DUPhv_H
8609             (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8610             neon_uimm2_bare:$Imm)))>;
8611
8612 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8613             (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)), 65535)))),
8614           (FCVTsh (f16 (DUPhv_H (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)))>;
8615
8616 // Patterns for vector insert of half-precision FP value 0 in i16 storage type
8617 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8618             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8619             (neon_uimm3_bare:$Imm))),
8620           (v8i16 (INSELh (v8i16 VPR128:$Rn),
8621             (v8i16 (SUBREG_TO_REG (i64 0),
8622               (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8623               sub_16)),
8624             neon_uimm3_bare:$Imm, 0))>;
8625
8626 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8627             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8628             (neon_uimm2_bare:$Imm))),
8629           (v4i16 (EXTRACT_SUBREG
8630             (v8i16 (INSELh
8631               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8632               (v8i16 (SUBREG_TO_REG (i64 0),
8633                 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8634                 sub_16)),
8635               neon_uimm2_bare:$Imm, 0)),
8636             sub_64))>;
8637
8638 // Patterns for vector insert of half-precision FP value in i16 storage type
8639 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8640             (i32 (assertsext (i32 (fp_to_sint
8641               (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8642             (neon_uimm3_bare:$Imm))),
8643           (v8i16 (INSELh (v8i16 VPR128:$Rn),
8644             (v8i16 (SUBREG_TO_REG (i64 0),
8645               (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8646               sub_16)),
8647             neon_uimm3_bare:$Imm, 0))>;
8648
8649 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8650             (i32 (assertsext (i32 (fp_to_sint
8651               (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8652             (neon_uimm2_bare:$Imm))),
8653           (v4i16 (EXTRACT_SUBREG
8654             (v8i16 (INSELh
8655               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8656               (v8i16 (SUBREG_TO_REG (i64 0),
8657                 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8658                 sub_16)),
8659               neon_uimm2_bare:$Imm, 0)),
8660             sub_64))>;
8661
8662 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8663             (i32 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8664               (neon_uimm3_bare:$Imm1))),
8665           (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8666             neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8667
8668 // Patterns for vector copy of half-precision FP value in i16 storage type
8669 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8670             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8671               (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8672               65535)))))))),
8673             (neon_uimm3_bare:$Imm1))),
8674           (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8675             neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8676
8677 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8678             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8679               (vector_extract (v4i16 VPR64:$src), neon_uimm3_bare:$Imm2)),
8680               65535)))))))),
8681             (neon_uimm3_bare:$Imm1))),
8682           (v4i16 (EXTRACT_SUBREG
8683             (v8i16 (INSELh
8684               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8685               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
8686               neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2)),
8687             sub_64))>;
8688
8689