[AArch64] Refactor the NEON signed/unsigned floating-point convert to fixed-point

LLVM AArch64 intrinsics to use f32/f64, rather than their vector equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196964 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/IR/IntrinsicsAArch64.td b/include/llvm/IR/IntrinsicsAArch64.td
index 14ae8a9b795f0dac925cde840e4ae3be80a70cef..ddbbc7a2e7ddcfb6bf7427d0e8417ff9721afb3b 100644 (file)
--- a/include/llvm/IR/IntrinsicsAArch64.td
+++ b/include/llvm/IR/IntrinsicsAArch64.td
@@ -358,11 +358,11 @@ def int_aarch64_neon_vcvtfxu2fp_n :
 
 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
 def int_aarch64_neon_vcvtfp2fxs_n :
-  Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i32_ty], [IntrNoMem]>;
+  Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 
 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
 def int_aarch64_neon_vcvtfp2fxu_n :
-  Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i32_ty], [IntrNoMem]>;
+  Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 
 class Neon_SHA_Intrinsic
   : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v1i32_ty, llvm_v4i32_ty],

diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td
index 82264da6b621e9d6bd19b54ab6f22a73041bff95..a07bec015d2bc0d4f85f7141a80328500d9c3c5d 100644 (file)
--- a/lib/Target/AArch64/AArch64InstrNEON.td
+++ b/lib/Target/AArch64/AArch64InstrNEON.td
@@ -4639,9 +4639,9 @@ multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator opnode,
 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator opnode,
                                                       Instruction INSTS,
                                                       Instruction INSTD> {
-  def ssi : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
+  def ssi : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
                 (INSTS FPR32:$Rn, imm:$Imm)>;
-  def ddi : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
+  def ddi : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
                 (INSTD FPR64:$Rn, imm:$Imm)>;
 }
 

diff --git a/test/CodeGen/AArch64/neon-scalar-cvt.ll b/test/CodeGen/AArch64/neon-scalar-cvt.ll
index ef91c2e4a88051cb0bbe7ffcbcc8dd11588a5b78..3a19bed9f6716b0bc40a2683562f5ebe53674480 100644 (file)
--- a/test/CodeGen/AArch64/neon-scalar-cvt.ll
+++ b/test/CodeGen/AArch64/neon-scalar-cvt.ll
@@ -92,46 +92,42 @@ define i32 @test_vcvts_n_s32_f32(float %a) {
 ; CHECK: test_vcvts_n_s32_f32
 ; CHECK: fcvtzs {{s[0-9]+}}, {{s[0-9]+}}, #1
 entry:
-  %fcvtzs = insertelement <1 x float> undef, float %a, i32 0
-  %fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.v1f32(<1 x float> %fcvtzs, i32 1)
+  %fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.f32(float %a, i32 1)
   %0 = extractelement <1 x i32> %fcvtzs1, i32 0
   ret i32 %0
 }
 
-declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.v1f32(<1 x float>, i32)
+declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.f32(float, i32)
 
 define i64 @test_vcvtd_n_s64_f64(double %a) {
 ; CHECK: test_vcvtd_n_s64_f64
 ; CHECK: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}, #1
 entry:
-  %fcvtzs = insertelement <1 x double> undef, double %a, i32 0
-  %fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.v1f64(<1 x double> %fcvtzs, i32 1)
+  %fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.f64(double %a, i32 1)
   %0 = extractelement <1 x i64> %fcvtzs1, i32 0
   ret i64 %0
 }
 
-declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.v1f64(<1 x double>, i32)
+declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.f64(double, i32)
 
 define i32 @test_vcvts_n_u32_f32(float %a) {
 ; CHECK: test_vcvts_n_u32_f32
 ; CHECK: fcvtzu {{s[0-9]+}}, {{s[0-9]+}}, #32
 entry:
-  %fcvtzu = insertelement <1 x float> undef, float %a, i32 0
-  %fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.v1f32(<1 x float> %fcvtzu, i32 32)
+  %fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.f32(float %a, i32 32)
   %0 = extractelement <1 x i32> %fcvtzu1, i32 0
   ret i32 %0
 }
 
-declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.v1f32(<1 x float>, i32)
+declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.f32(float, i32)
 
 define i64 @test_vcvtd_n_u64_f64(double %a) {
 ; CHECK: test_vcvtd_n_u64_f64
 ; CHECK: fcvtzu {{d[0-9]+}}, {{d[0-9]+}}, #64
 entry:
-  %fcvtzu = insertelement <1 x double> undef, double %a, i32 0
-  %fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.v1f64(<1 x double> %fcvtzu, i32 64)
+  %fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.f64(double %a, i32 64)
   %0 = extractelement <1 x i64> %fcvtzu1, i32 0
   ret i64 %0
 }
 
-declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.v1f64(<1 x double>, i32)
+declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.f64(double, i32)