1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLoweringBase class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineJumpTableInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/MC/MCAsmInfo.h"
26 #include "llvm/MC/MCExpr.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Target/TargetLoweringObjectFile.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
36 /// InitLibcallNames - Set default libcall names.
38 static void InitLibcallNames(const char **Names, const TargetMachine &TM) {
39 Names[RTLIB::SHL_I16] = "__ashlhi3";
40 Names[RTLIB::SHL_I32] = "__ashlsi3";
41 Names[RTLIB::SHL_I64] = "__ashldi3";
42 Names[RTLIB::SHL_I128] = "__ashlti3";
43 Names[RTLIB::SRL_I16] = "__lshrhi3";
44 Names[RTLIB::SRL_I32] = "__lshrsi3";
45 Names[RTLIB::SRL_I64] = "__lshrdi3";
46 Names[RTLIB::SRL_I128] = "__lshrti3";
47 Names[RTLIB::SRA_I16] = "__ashrhi3";
48 Names[RTLIB::SRA_I32] = "__ashrsi3";
49 Names[RTLIB::SRA_I64] = "__ashrdi3";
50 Names[RTLIB::SRA_I128] = "__ashrti3";
51 Names[RTLIB::MUL_I8] = "__mulqi3";
52 Names[RTLIB::MUL_I16] = "__mulhi3";
53 Names[RTLIB::MUL_I32] = "__mulsi3";
54 Names[RTLIB::MUL_I64] = "__muldi3";
55 Names[RTLIB::MUL_I128] = "__multi3";
56 Names[RTLIB::MULO_I32] = "__mulosi4";
57 Names[RTLIB::MULO_I64] = "__mulodi4";
58 Names[RTLIB::MULO_I128] = "__muloti4";
59 Names[RTLIB::SDIV_I8] = "__divqi3";
60 Names[RTLIB::SDIV_I16] = "__divhi3";
61 Names[RTLIB::SDIV_I32] = "__divsi3";
62 Names[RTLIB::SDIV_I64] = "__divdi3";
63 Names[RTLIB::SDIV_I128] = "__divti3";
64 Names[RTLIB::UDIV_I8] = "__udivqi3";
65 Names[RTLIB::UDIV_I16] = "__udivhi3";
66 Names[RTLIB::UDIV_I32] = "__udivsi3";
67 Names[RTLIB::UDIV_I64] = "__udivdi3";
68 Names[RTLIB::UDIV_I128] = "__udivti3";
69 Names[RTLIB::SREM_I8] = "__modqi3";
70 Names[RTLIB::SREM_I16] = "__modhi3";
71 Names[RTLIB::SREM_I32] = "__modsi3";
72 Names[RTLIB::SREM_I64] = "__moddi3";
73 Names[RTLIB::SREM_I128] = "__modti3";
74 Names[RTLIB::UREM_I8] = "__umodqi3";
75 Names[RTLIB::UREM_I16] = "__umodhi3";
76 Names[RTLIB::UREM_I32] = "__umodsi3";
77 Names[RTLIB::UREM_I64] = "__umoddi3";
78 Names[RTLIB::UREM_I128] = "__umodti3";
80 // These are generally not available.
81 Names[RTLIB::SDIVREM_I8] = 0;
82 Names[RTLIB::SDIVREM_I16] = 0;
83 Names[RTLIB::SDIVREM_I32] = 0;
84 Names[RTLIB::SDIVREM_I64] = 0;
85 Names[RTLIB::SDIVREM_I128] = 0;
86 Names[RTLIB::UDIVREM_I8] = 0;
87 Names[RTLIB::UDIVREM_I16] = 0;
88 Names[RTLIB::UDIVREM_I32] = 0;
89 Names[RTLIB::UDIVREM_I64] = 0;
90 Names[RTLIB::UDIVREM_I128] = 0;
92 Names[RTLIB::NEG_I32] = "__negsi2";
93 Names[RTLIB::NEG_I64] = "__negdi2";
94 Names[RTLIB::ADD_F32] = "__addsf3";
95 Names[RTLIB::ADD_F64] = "__adddf3";
96 Names[RTLIB::ADD_F80] = "__addxf3";
97 Names[RTLIB::ADD_F128] = "__addtf3";
98 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
99 Names[RTLIB::SUB_F32] = "__subsf3";
100 Names[RTLIB::SUB_F64] = "__subdf3";
101 Names[RTLIB::SUB_F80] = "__subxf3";
102 Names[RTLIB::SUB_F128] = "__subtf3";
103 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
104 Names[RTLIB::MUL_F32] = "__mulsf3";
105 Names[RTLIB::MUL_F64] = "__muldf3";
106 Names[RTLIB::MUL_F80] = "__mulxf3";
107 Names[RTLIB::MUL_F128] = "__multf3";
108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
109 Names[RTLIB::DIV_F32] = "__divsf3";
110 Names[RTLIB::DIV_F64] = "__divdf3";
111 Names[RTLIB::DIV_F80] = "__divxf3";
112 Names[RTLIB::DIV_F128] = "__divtf3";
113 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
114 Names[RTLIB::REM_F32] = "fmodf";
115 Names[RTLIB::REM_F64] = "fmod";
116 Names[RTLIB::REM_F80] = "fmodl";
117 Names[RTLIB::REM_F128] = "fmodl";
118 Names[RTLIB::REM_PPCF128] = "fmodl";
119 Names[RTLIB::FMA_F32] = "fmaf";
120 Names[RTLIB::FMA_F64] = "fma";
121 Names[RTLIB::FMA_F80] = "fmal";
122 Names[RTLIB::FMA_F128] = "fmal";
123 Names[RTLIB::FMA_PPCF128] = "fmal";
124 Names[RTLIB::POWI_F32] = "__powisf2";
125 Names[RTLIB::POWI_F64] = "__powidf2";
126 Names[RTLIB::POWI_F80] = "__powixf2";
127 Names[RTLIB::POWI_F128] = "__powitf2";
128 Names[RTLIB::POWI_PPCF128] = "__powitf2";
129 Names[RTLIB::SQRT_F32] = "sqrtf";
130 Names[RTLIB::SQRT_F64] = "sqrt";
131 Names[RTLIB::SQRT_F80] = "sqrtl";
132 Names[RTLIB::SQRT_F128] = "sqrtl";
133 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
134 Names[RTLIB::LOG_F32] = "logf";
135 Names[RTLIB::LOG_F64] = "log";
136 Names[RTLIB::LOG_F80] = "logl";
137 Names[RTLIB::LOG_F128] = "logl";
138 Names[RTLIB::LOG_PPCF128] = "logl";
139 Names[RTLIB::LOG2_F32] = "log2f";
140 Names[RTLIB::LOG2_F64] = "log2";
141 Names[RTLIB::LOG2_F80] = "log2l";
142 Names[RTLIB::LOG2_F128] = "log2l";
143 Names[RTLIB::LOG2_PPCF128] = "log2l";
144 Names[RTLIB::LOG10_F32] = "log10f";
145 Names[RTLIB::LOG10_F64] = "log10";
146 Names[RTLIB::LOG10_F80] = "log10l";
147 Names[RTLIB::LOG10_F128] = "log10l";
148 Names[RTLIB::LOG10_PPCF128] = "log10l";
149 Names[RTLIB::EXP_F32] = "expf";
150 Names[RTLIB::EXP_F64] = "exp";
151 Names[RTLIB::EXP_F80] = "expl";
152 Names[RTLIB::EXP_F128] = "expl";
153 Names[RTLIB::EXP_PPCF128] = "expl";
154 Names[RTLIB::EXP2_F32] = "exp2f";
155 Names[RTLIB::EXP2_F64] = "exp2";
156 Names[RTLIB::EXP2_F80] = "exp2l";
157 Names[RTLIB::EXP2_F128] = "exp2l";
158 Names[RTLIB::EXP2_PPCF128] = "exp2l";
159 Names[RTLIB::SIN_F32] = "sinf";
160 Names[RTLIB::SIN_F64] = "sin";
161 Names[RTLIB::SIN_F80] = "sinl";
162 Names[RTLIB::SIN_F128] = "sinl";
163 Names[RTLIB::SIN_PPCF128] = "sinl";
164 Names[RTLIB::COS_F32] = "cosf";
165 Names[RTLIB::COS_F64] = "cos";
166 Names[RTLIB::COS_F80] = "cosl";
167 Names[RTLIB::COS_F128] = "cosl";
168 Names[RTLIB::COS_PPCF128] = "cosl";
169 Names[RTLIB::POW_F32] = "powf";
170 Names[RTLIB::POW_F64] = "pow";
171 Names[RTLIB::POW_F80] = "powl";
172 Names[RTLIB::POW_F128] = "powl";
173 Names[RTLIB::POW_PPCF128] = "powl";
174 Names[RTLIB::CEIL_F32] = "ceilf";
175 Names[RTLIB::CEIL_F64] = "ceil";
176 Names[RTLIB::CEIL_F80] = "ceill";
177 Names[RTLIB::CEIL_F128] = "ceill";
178 Names[RTLIB::CEIL_PPCF128] = "ceill";
179 Names[RTLIB::TRUNC_F32] = "truncf";
180 Names[RTLIB::TRUNC_F64] = "trunc";
181 Names[RTLIB::TRUNC_F80] = "truncl";
182 Names[RTLIB::TRUNC_F128] = "truncl";
183 Names[RTLIB::TRUNC_PPCF128] = "truncl";
184 Names[RTLIB::RINT_F32] = "rintf";
185 Names[RTLIB::RINT_F64] = "rint";
186 Names[RTLIB::RINT_F80] = "rintl";
187 Names[RTLIB::RINT_F128] = "rintl";
188 Names[RTLIB::RINT_PPCF128] = "rintl";
189 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
190 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
191 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
192 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
193 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
194 Names[RTLIB::ROUND_F32] = "roundf";
195 Names[RTLIB::ROUND_F64] = "round";
196 Names[RTLIB::ROUND_F80] = "roundl";
197 Names[RTLIB::ROUND_F128] = "roundl";
198 Names[RTLIB::ROUND_PPCF128] = "roundl";
199 Names[RTLIB::FLOOR_F32] = "floorf";
200 Names[RTLIB::FLOOR_F64] = "floor";
201 Names[RTLIB::FLOOR_F80] = "floorl";
202 Names[RTLIB::FLOOR_F128] = "floorl";
203 Names[RTLIB::FLOOR_PPCF128] = "floorl";
204 Names[RTLIB::COPYSIGN_F32] = "copysignf";
205 Names[RTLIB::COPYSIGN_F64] = "copysign";
206 Names[RTLIB::COPYSIGN_F80] = "copysignl";
207 Names[RTLIB::COPYSIGN_F128] = "copysignl";
208 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
209 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
210 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
211 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
212 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
213 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
214 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
215 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
216 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
217 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
218 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
219 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
220 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
221 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
222 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
223 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
224 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
225 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
226 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
227 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
228 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
229 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
230 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
231 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
232 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
233 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
234 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
235 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
236 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
237 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
238 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
239 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
240 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
241 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
242 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
243 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
244 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
245 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
246 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
247 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
248 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
249 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
250 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
251 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
252 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
253 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
254 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
255 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
256 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
257 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
258 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
259 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
260 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
261 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
262 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
263 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
264 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
265 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
266 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
267 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
268 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
269 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
270 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
271 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
272 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
273 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
274 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
275 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
276 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
277 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
278 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
279 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
280 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
281 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
282 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
283 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
284 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
285 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
286 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
287 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
288 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
289 Names[RTLIB::OEQ_F32] = "__eqsf2";
290 Names[RTLIB::OEQ_F64] = "__eqdf2";
291 Names[RTLIB::OEQ_F128] = "__eqtf2";
292 Names[RTLIB::UNE_F32] = "__nesf2";
293 Names[RTLIB::UNE_F64] = "__nedf2";
294 Names[RTLIB::UNE_F128] = "__netf2";
295 Names[RTLIB::OGE_F32] = "__gesf2";
296 Names[RTLIB::OGE_F64] = "__gedf2";
297 Names[RTLIB::OGE_F128] = "__getf2";
298 Names[RTLIB::OLT_F32] = "__ltsf2";
299 Names[RTLIB::OLT_F64] = "__ltdf2";
300 Names[RTLIB::OLT_F128] = "__lttf2";
301 Names[RTLIB::OLE_F32] = "__lesf2";
302 Names[RTLIB::OLE_F64] = "__ledf2";
303 Names[RTLIB::OLE_F128] = "__letf2";
304 Names[RTLIB::OGT_F32] = "__gtsf2";
305 Names[RTLIB::OGT_F64] = "__gtdf2";
306 Names[RTLIB::OGT_F128] = "__gttf2";
307 Names[RTLIB::UO_F32] = "__unordsf2";
308 Names[RTLIB::UO_F64] = "__unorddf2";
309 Names[RTLIB::UO_F128] = "__unordtf2";
310 Names[RTLIB::O_F32] = "__unordsf2";
311 Names[RTLIB::O_F64] = "__unorddf2";
312 Names[RTLIB::O_F128] = "__unordtf2";
313 Names[RTLIB::MEMCPY] = "memcpy";
314 Names[RTLIB::MEMMOVE] = "memmove";
315 Names[RTLIB::MEMSET] = "memset";
316 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
317 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
318 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
319 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
320 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
321 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
322 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
323 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
324 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
325 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
326 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
327 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
328 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
329 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
330 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
331 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
332 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
333 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
334 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
335 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
336 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
337 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
338 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
339 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
340 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
341 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
342 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
343 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
344 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
345 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
346 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
347 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
348 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
350 if (Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU) {
351 Names[RTLIB::SINCOS_F32] = "sincosf";
352 Names[RTLIB::SINCOS_F64] = "sincos";
353 Names[RTLIB::SINCOS_F80] = "sincosl";
354 Names[RTLIB::SINCOS_F128] = "sincosl";
355 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
357 // These are generally not available.
358 Names[RTLIB::SINCOS_F32] = 0;
359 Names[RTLIB::SINCOS_F64] = 0;
360 Names[RTLIB::SINCOS_F80] = 0;
361 Names[RTLIB::SINCOS_F128] = 0;
362 Names[RTLIB::SINCOS_PPCF128] = 0;
365 if (Triple(TM.getTargetTriple()).getOS() != Triple::OpenBSD) {
366 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
368 // These are generally not available.
369 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = 0;
373 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
375 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
376 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
377 CCs[i] = CallingConv::C;
381 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
382 /// UNKNOWN_LIBCALL if there is none.
383 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
384 if (OpVT == MVT::f32) {
385 if (RetVT == MVT::f64)
386 return FPEXT_F32_F64;
387 if (RetVT == MVT::f128)
388 return FPEXT_F32_F128;
389 } else if (OpVT == MVT::f64) {
390 if (RetVT == MVT::f128)
391 return FPEXT_F64_F128;
394 return UNKNOWN_LIBCALL;
397 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
398 /// UNKNOWN_LIBCALL if there is none.
399 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
400 if (RetVT == MVT::f32) {
401 if (OpVT == MVT::f64)
402 return FPROUND_F64_F32;
403 if (OpVT == MVT::f80)
404 return FPROUND_F80_F32;
405 if (OpVT == MVT::f128)
406 return FPROUND_F128_F32;
407 if (OpVT == MVT::ppcf128)
408 return FPROUND_PPCF128_F32;
409 } else if (RetVT == MVT::f64) {
410 if (OpVT == MVT::f80)
411 return FPROUND_F80_F64;
412 if (OpVT == MVT::f128)
413 return FPROUND_F128_F64;
414 if (OpVT == MVT::ppcf128)
415 return FPROUND_PPCF128_F64;
418 return UNKNOWN_LIBCALL;
421 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
422 /// UNKNOWN_LIBCALL if there is none.
423 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
424 if (OpVT == MVT::f32) {
425 if (RetVT == MVT::i8)
426 return FPTOSINT_F32_I8;
427 if (RetVT == MVT::i16)
428 return FPTOSINT_F32_I16;
429 if (RetVT == MVT::i32)
430 return FPTOSINT_F32_I32;
431 if (RetVT == MVT::i64)
432 return FPTOSINT_F32_I64;
433 if (RetVT == MVT::i128)
434 return FPTOSINT_F32_I128;
435 } else if (OpVT == MVT::f64) {
436 if (RetVT == MVT::i8)
437 return FPTOSINT_F64_I8;
438 if (RetVT == MVT::i16)
439 return FPTOSINT_F64_I16;
440 if (RetVT == MVT::i32)
441 return FPTOSINT_F64_I32;
442 if (RetVT == MVT::i64)
443 return FPTOSINT_F64_I64;
444 if (RetVT == MVT::i128)
445 return FPTOSINT_F64_I128;
446 } else if (OpVT == MVT::f80) {
447 if (RetVT == MVT::i32)
448 return FPTOSINT_F80_I32;
449 if (RetVT == MVT::i64)
450 return FPTOSINT_F80_I64;
451 if (RetVT == MVT::i128)
452 return FPTOSINT_F80_I128;
453 } else if (OpVT == MVT::f128) {
454 if (RetVT == MVT::i32)
455 return FPTOSINT_F128_I32;
456 if (RetVT == MVT::i64)
457 return FPTOSINT_F128_I64;
458 if (RetVT == MVT::i128)
459 return FPTOSINT_F128_I128;
460 } else if (OpVT == MVT::ppcf128) {
461 if (RetVT == MVT::i32)
462 return FPTOSINT_PPCF128_I32;
463 if (RetVT == MVT::i64)
464 return FPTOSINT_PPCF128_I64;
465 if (RetVT == MVT::i128)
466 return FPTOSINT_PPCF128_I128;
468 return UNKNOWN_LIBCALL;
471 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
472 /// UNKNOWN_LIBCALL if there is none.
473 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
474 if (OpVT == MVT::f32) {
475 if (RetVT == MVT::i8)
476 return FPTOUINT_F32_I8;
477 if (RetVT == MVT::i16)
478 return FPTOUINT_F32_I16;
479 if (RetVT == MVT::i32)
480 return FPTOUINT_F32_I32;
481 if (RetVT == MVT::i64)
482 return FPTOUINT_F32_I64;
483 if (RetVT == MVT::i128)
484 return FPTOUINT_F32_I128;
485 } else if (OpVT == MVT::f64) {
486 if (RetVT == MVT::i8)
487 return FPTOUINT_F64_I8;
488 if (RetVT == MVT::i16)
489 return FPTOUINT_F64_I16;
490 if (RetVT == MVT::i32)
491 return FPTOUINT_F64_I32;
492 if (RetVT == MVT::i64)
493 return FPTOUINT_F64_I64;
494 if (RetVT == MVT::i128)
495 return FPTOUINT_F64_I128;
496 } else if (OpVT == MVT::f80) {
497 if (RetVT == MVT::i32)
498 return FPTOUINT_F80_I32;
499 if (RetVT == MVT::i64)
500 return FPTOUINT_F80_I64;
501 if (RetVT == MVT::i128)
502 return FPTOUINT_F80_I128;
503 } else if (OpVT == MVT::f128) {
504 if (RetVT == MVT::i32)
505 return FPTOUINT_F128_I32;
506 if (RetVT == MVT::i64)
507 return FPTOUINT_F128_I64;
508 if (RetVT == MVT::i128)
509 return FPTOUINT_F128_I128;
510 } else if (OpVT == MVT::ppcf128) {
511 if (RetVT == MVT::i32)
512 return FPTOUINT_PPCF128_I32;
513 if (RetVT == MVT::i64)
514 return FPTOUINT_PPCF128_I64;
515 if (RetVT == MVT::i128)
516 return FPTOUINT_PPCF128_I128;
518 return UNKNOWN_LIBCALL;
521 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
522 /// UNKNOWN_LIBCALL if there is none.
523 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
524 if (OpVT == MVT::i32) {
525 if (RetVT == MVT::f32)
526 return SINTTOFP_I32_F32;
527 if (RetVT == MVT::f64)
528 return SINTTOFP_I32_F64;
529 if (RetVT == MVT::f80)
530 return SINTTOFP_I32_F80;
531 if (RetVT == MVT::f128)
532 return SINTTOFP_I32_F128;
533 if (RetVT == MVT::ppcf128)
534 return SINTTOFP_I32_PPCF128;
535 } else if (OpVT == MVT::i64) {
536 if (RetVT == MVT::f32)
537 return SINTTOFP_I64_F32;
538 if (RetVT == MVT::f64)
539 return SINTTOFP_I64_F64;
540 if (RetVT == MVT::f80)
541 return SINTTOFP_I64_F80;
542 if (RetVT == MVT::f128)
543 return SINTTOFP_I64_F128;
544 if (RetVT == MVT::ppcf128)
545 return SINTTOFP_I64_PPCF128;
546 } else if (OpVT == MVT::i128) {
547 if (RetVT == MVT::f32)
548 return SINTTOFP_I128_F32;
549 if (RetVT == MVT::f64)
550 return SINTTOFP_I128_F64;
551 if (RetVT == MVT::f80)
552 return SINTTOFP_I128_F80;
553 if (RetVT == MVT::f128)
554 return SINTTOFP_I128_F128;
555 if (RetVT == MVT::ppcf128)
556 return SINTTOFP_I128_PPCF128;
558 return UNKNOWN_LIBCALL;
561 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
562 /// UNKNOWN_LIBCALL if there is none.
563 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
564 if (OpVT == MVT::i32) {
565 if (RetVT == MVT::f32)
566 return UINTTOFP_I32_F32;
567 if (RetVT == MVT::f64)
568 return UINTTOFP_I32_F64;
569 if (RetVT == MVT::f80)
570 return UINTTOFP_I32_F80;
571 if (RetVT == MVT::f128)
572 return UINTTOFP_I32_F128;
573 if (RetVT == MVT::ppcf128)
574 return UINTTOFP_I32_PPCF128;
575 } else if (OpVT == MVT::i64) {
576 if (RetVT == MVT::f32)
577 return UINTTOFP_I64_F32;
578 if (RetVT == MVT::f64)
579 return UINTTOFP_I64_F64;
580 if (RetVT == MVT::f80)
581 return UINTTOFP_I64_F80;
582 if (RetVT == MVT::f128)
583 return UINTTOFP_I64_F128;
584 if (RetVT == MVT::ppcf128)
585 return UINTTOFP_I64_PPCF128;
586 } else if (OpVT == MVT::i128) {
587 if (RetVT == MVT::f32)
588 return UINTTOFP_I128_F32;
589 if (RetVT == MVT::f64)
590 return UINTTOFP_I128_F64;
591 if (RetVT == MVT::f80)
592 return UINTTOFP_I128_F80;
593 if (RetVT == MVT::f128)
594 return UINTTOFP_I128_F128;
595 if (RetVT == MVT::ppcf128)
596 return UINTTOFP_I128_PPCF128;
598 return UNKNOWN_LIBCALL;
601 /// InitCmpLibcallCCs - Set default comparison libcall CC.
603 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
604 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
605 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
606 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
607 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
608 CCs[RTLIB::UNE_F32] = ISD::SETNE;
609 CCs[RTLIB::UNE_F64] = ISD::SETNE;
610 CCs[RTLIB::UNE_F128] = ISD::SETNE;
611 CCs[RTLIB::OGE_F32] = ISD::SETGE;
612 CCs[RTLIB::OGE_F64] = ISD::SETGE;
613 CCs[RTLIB::OGE_F128] = ISD::SETGE;
614 CCs[RTLIB::OLT_F32] = ISD::SETLT;
615 CCs[RTLIB::OLT_F64] = ISD::SETLT;
616 CCs[RTLIB::OLT_F128] = ISD::SETLT;
617 CCs[RTLIB::OLE_F32] = ISD::SETLE;
618 CCs[RTLIB::OLE_F64] = ISD::SETLE;
619 CCs[RTLIB::OLE_F128] = ISD::SETLE;
620 CCs[RTLIB::OGT_F32] = ISD::SETGT;
621 CCs[RTLIB::OGT_F64] = ISD::SETGT;
622 CCs[RTLIB::OGT_F128] = ISD::SETGT;
623 CCs[RTLIB::UO_F32] = ISD::SETNE;
624 CCs[RTLIB::UO_F64] = ISD::SETNE;
625 CCs[RTLIB::UO_F128] = ISD::SETNE;
626 CCs[RTLIB::O_F32] = ISD::SETEQ;
627 CCs[RTLIB::O_F64] = ISD::SETEQ;
628 CCs[RTLIB::O_F128] = ISD::SETEQ;
631 /// NOTE: The constructor takes ownership of TLOF.
632 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
633 const TargetLoweringObjectFile *tlof)
634 : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) {
637 // Perform these initializations only once.
638 IsLittleEndian = TD->isLittleEndian();
639 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize(0));
640 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
641 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
642 = MaxStoresPerMemmoveOptSize = 4;
643 UseUnderscoreSetJmp = false;
644 UseUnderscoreLongJmp = false;
645 SelectIsExpensive = false;
646 IntDivIsCheap = false;
647 Pow2DivIsCheap = false;
648 JumpIsExpensive = false;
649 PredictableSelectIsExpensive = false;
650 StackPointerRegisterToSaveRestore = 0;
651 ExceptionPointerRegister = 0;
652 ExceptionSelectorRegister = 0;
653 BooleanContents = UndefinedBooleanContent;
654 BooleanVectorContents = UndefinedBooleanContent;
655 SchedPreferenceInfo = Sched::ILP;
657 JumpBufAlignment = 0;
658 MinFunctionAlignment = 0;
659 PrefFunctionAlignment = 0;
660 PrefLoopAlignment = 0;
661 MinStackArgumentAlignment = 1;
662 InsertFencesForAtomic = false;
663 SupportJumpTables = true;
664 MinimumJumpTableEntries = 4;
666 InitLibcallNames(LibcallRoutineNames, TM);
667 InitCmpLibcallCCs(CmpLibcallCCs);
668 InitLibcallCallingConvs(LibcallCallingConvs);
671 TargetLoweringBase::~TargetLoweringBase() {
675 void TargetLoweringBase::initActions() {
676 // All operations default to being supported.
677 memset(OpActions, 0, sizeof(OpActions));
678 memset(LoadExtActions, 0, sizeof(LoadExtActions));
679 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
680 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
681 memset(CondCodeActions, 0, sizeof(CondCodeActions));
682 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
683 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
685 // Set default actions for various operations.
686 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
687 // Default all indexed load / store to expand.
688 for (unsigned IM = (unsigned)ISD::PRE_INC;
689 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
690 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
691 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
694 // These operations default to expand.
695 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
698 // These library functions default to expand.
699 setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand);
701 // These operations default to expand for vector types.
702 if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
703 VT <= MVT::LAST_VECTOR_VALUETYPE)
704 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
707 // Most targets ignore the @llvm.prefetch intrinsic.
708 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
710 // ConstantFP nodes default to expand. Targets can either change this to
711 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
712 // to optimize expansions for certain constants.
713 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
714 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
715 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
716 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
717 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
719 // These library functions default to expand.
720 setOperationAction(ISD::FLOG , MVT::f16, Expand);
721 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
722 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
723 setOperationAction(ISD::FEXP , MVT::f16, Expand);
724 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
725 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
726 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
727 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
728 setOperationAction(ISD::FRINT, MVT::f16, Expand);
729 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
730 setOperationAction(ISD::FLOG , MVT::f32, Expand);
731 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
732 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
733 setOperationAction(ISD::FEXP , MVT::f32, Expand);
734 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
735 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
736 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
737 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
738 setOperationAction(ISD::FRINT, MVT::f32, Expand);
739 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
740 setOperationAction(ISD::FLOG , MVT::f64, Expand);
741 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
742 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
743 setOperationAction(ISD::FEXP , MVT::f64, Expand);
744 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
745 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
746 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
747 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
748 setOperationAction(ISD::FRINT, MVT::f64, Expand);
749 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
750 setOperationAction(ISD::FLOG , MVT::f128, Expand);
751 setOperationAction(ISD::FLOG2, MVT::f128, Expand);
752 setOperationAction(ISD::FLOG10, MVT::f128, Expand);
753 setOperationAction(ISD::FEXP , MVT::f128, Expand);
754 setOperationAction(ISD::FEXP2, MVT::f128, Expand);
755 setOperationAction(ISD::FFLOOR, MVT::f128, Expand);
756 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand);
757 setOperationAction(ISD::FCEIL, MVT::f128, Expand);
758 setOperationAction(ISD::FRINT, MVT::f128, Expand);
759 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
761 // Default ISD::TRAP to expand (which turns it into abort).
762 setOperationAction(ISD::TRAP, MVT::Other, Expand);
764 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
765 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
767 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
770 MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const {
771 return MVT::getIntegerVT(8*TD->getPointerSize(0));
774 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const {
775 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
776 if (LHSTy.isVector())
778 return getScalarShiftAmountTy(LHSTy);
781 /// canOpTrap - Returns true if the operation can trap for the value type.
782 /// VT must be a legal type.
783 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
784 assert(isTypeLegal(VT));
799 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
800 unsigned &NumIntermediates,
802 TargetLoweringBase *TLI) {
803 // Figure out the right, legal destination reg to copy into.
804 unsigned NumElts = VT.getVectorNumElements();
805 MVT EltTy = VT.getVectorElementType();
807 unsigned NumVectorRegs = 1;
809 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
810 // could break down into LHS/RHS like LegalizeDAG does.
811 if (!isPowerOf2_32(NumElts)) {
812 NumVectorRegs = NumElts;
816 // Divide the input until we get to a supported size. This will always
817 // end with a scalar if the target doesn't support vectors.
818 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
823 NumIntermediates = NumVectorRegs;
825 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
826 if (!TLI->isTypeLegal(NewVT))
828 IntermediateVT = NewVT;
830 unsigned NewVTSize = NewVT.getSizeInBits();
832 // Convert sizes such as i33 to i64.
833 if (!isPowerOf2_32(NewVTSize))
834 NewVTSize = NextPowerOf2(NewVTSize);
836 MVT DestVT = TLI->getRegisterType(NewVT);
838 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
839 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
841 // Otherwise, promotion or legal types use the same number of registers as
842 // the vector decimated to the appropriate level.
843 return NumVectorRegs;
846 /// isLegalRC - Return true if the value types that can be represented by the
847 /// specified register class are all legal.
848 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
849 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
857 /// findRepresentativeClass - Return the largest legal super-reg register class
858 /// of the register class for the specified type and its associated "cost".
859 std::pair<const TargetRegisterClass*, uint8_t>
860 TargetLoweringBase::findRepresentativeClass(MVT VT) const {
861 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
862 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
864 return std::make_pair(RC, 0);
866 // Compute the set of all super-register classes.
867 BitVector SuperRegRC(TRI->getNumRegClasses());
868 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
869 SuperRegRC.setBitsInMask(RCI.getMask());
871 // Find the first legal register class with the largest spill size.
872 const TargetRegisterClass *BestRC = RC;
873 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
874 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
875 // We want the largest possible spill size.
876 if (SuperRC->getSize() <= BestRC->getSize())
878 if (!isLegalRC(SuperRC))
882 return std::make_pair(BestRC, 1);
885 /// computeRegisterProperties - Once all of the register classes are added,
886 /// this allows us to compute derived properties we expose.
887 void TargetLoweringBase::computeRegisterProperties() {
888 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
889 "Too many value types for ValueTypeActions to hold!");
891 // Everything defaults to needing one register.
892 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
893 NumRegistersForVT[i] = 1;
894 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
896 // ...except isVoid, which doesn't need any registers.
897 NumRegistersForVT[MVT::isVoid] = 0;
899 // Find the largest integer register class.
900 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
901 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
902 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
904 // Every integer value type larger than this largest register takes twice as
905 // many registers to represent as the previous ValueType.
906 for (unsigned ExpandedReg = LargestIntReg + 1;
907 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
908 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
909 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
910 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
911 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
915 // Inspect all of the ValueType's smaller than the largest integer
916 // register to see which ones need promotion.
917 unsigned LegalIntReg = LargestIntReg;
918 for (unsigned IntReg = LargestIntReg - 1;
919 IntReg >= (unsigned)MVT::i1; --IntReg) {
920 MVT IVT = (MVT::SimpleValueType)IntReg;
921 if (isTypeLegal(IVT)) {
922 LegalIntReg = IntReg;
924 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
925 (const MVT::SimpleValueType)LegalIntReg;
926 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
930 // ppcf128 type is really two f64's.
931 if (!isTypeLegal(MVT::ppcf128)) {
932 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
933 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
934 TransformToType[MVT::ppcf128] = MVT::f64;
935 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
938 // Decide how to handle f128. If the target does not have native f128 support,
939 // expand it to i128 and we will be generating soft float library calls.
940 if (!isTypeLegal(MVT::f128)) {
941 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
942 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
943 TransformToType[MVT::f128] = MVT::i128;
944 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
947 // Decide how to handle f64. If the target does not have native f64 support,
948 // expand it to i64 and we will be generating soft float library calls.
949 if (!isTypeLegal(MVT::f64)) {
950 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
951 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
952 TransformToType[MVT::f64] = MVT::i64;
953 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
956 // Decide how to handle f32. If the target does not have native support for
957 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
958 if (!isTypeLegal(MVT::f32)) {
959 if (isTypeLegal(MVT::f64)) {
960 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
961 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
962 TransformToType[MVT::f32] = MVT::f64;
963 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
965 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
966 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
967 TransformToType[MVT::f32] = MVT::i32;
968 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
972 // Loop over all of the vector value types to see which need transformations.
973 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
974 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
975 MVT VT = (MVT::SimpleValueType)i;
976 if (isTypeLegal(VT)) continue;
978 // Determine if there is a legal wider type. If so, we should promote to
979 // that wider vector type.
980 MVT EltVT = VT.getVectorElementType();
981 unsigned NElts = VT.getVectorNumElements();
982 if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) {
983 bool IsLegalWiderType = false;
984 // First try to promote the elements of integer vectors. If no legal
985 // promotion was found, fallback to the widen-vector method.
986 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
987 MVT SVT = (MVT::SimpleValueType)nVT;
988 // Promote vectors of integers to vectors with the same number
989 // of elements, with a wider element type.
990 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
991 && SVT.getVectorNumElements() == NElts &&
992 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
993 TransformToType[i] = SVT;
994 RegisterTypeForVT[i] = SVT;
995 NumRegistersForVT[i] = 1;
996 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
997 IsLegalWiderType = true;
1002 if (IsLegalWiderType) continue;
1004 // Try to widen the vector.
1005 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1006 MVT SVT = (MVT::SimpleValueType)nVT;
1007 if (SVT.getVectorElementType() == EltVT &&
1008 SVT.getVectorNumElements() > NElts &&
1010 TransformToType[i] = SVT;
1011 RegisterTypeForVT[i] = SVT;
1012 NumRegistersForVT[i] = 1;
1013 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1014 IsLegalWiderType = true;
1018 if (IsLegalWiderType) continue;
1023 unsigned NumIntermediates;
1024 NumRegistersForVT[i] =
1025 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
1027 RegisterTypeForVT[i] = RegisterVT;
1029 MVT NVT = VT.getPow2VectorType();
1031 // Type is already a power of 2. The default action is to split.
1032 TransformToType[i] = MVT::Other;
1033 unsigned NumElts = VT.getVectorNumElements();
1034 ValueTypeActions.setTypeAction(VT,
1035 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
1037 TransformToType[i] = NVT;
1038 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1042 // Determine the 'representative' register class for each value type.
1043 // An representative register class is the largest (meaning one which is
1044 // not a sub-register class / subreg register class) legal register class for
1045 // a group of value types. For example, on i386, i8, i16, and i32
1046 // representative would be GR32; while on x86_64 it's GR64.
1047 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1048 const TargetRegisterClass* RRC;
1050 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
1051 RepRegClassForVT[i] = RRC;
1052 RepRegClassCostForVT[i] = Cost;
1056 EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const {
1057 assert(!VT.isVector() && "No default SetCC type for vectors!");
1058 return getPointerTy(0).SimpleTy;
1061 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1062 return MVT::i32; // return the default value
1065 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1066 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1067 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1068 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1070 /// This method returns the number of registers needed, and the VT for each
1071 /// register. It also returns the VT and quantity of the intermediate values
1072 /// before they are promoted/expanded.
1074 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1075 EVT &IntermediateVT,
1076 unsigned &NumIntermediates,
1077 MVT &RegisterVT) const {
1078 unsigned NumElts = VT.getVectorNumElements();
1080 // If there is a wider vector type with the same element type as this one,
1081 // or a promoted vector type that has the same number of elements which
1082 // are wider, then we should convert to that legal vector type.
1083 // This handles things like <2 x float> -> <4 x float> and
1084 // <4 x i1> -> <4 x i32>.
1085 LegalizeTypeAction TA = getTypeAction(Context, VT);
1086 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1087 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1088 if (isTypeLegal(RegisterEVT)) {
1089 IntermediateVT = RegisterEVT;
1090 RegisterVT = RegisterEVT.getSimpleVT();
1091 NumIntermediates = 1;
1096 // Figure out the right, legal destination reg to copy into.
1097 EVT EltTy = VT.getVectorElementType();
1099 unsigned NumVectorRegs = 1;
1101 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1102 // could break down into LHS/RHS like LegalizeDAG does.
1103 if (!isPowerOf2_32(NumElts)) {
1104 NumVectorRegs = NumElts;
1108 // Divide the input until we get to a supported size. This will always
1109 // end with a scalar if the target doesn't support vectors.
1110 while (NumElts > 1 && !isTypeLegal(
1111 EVT::getVectorVT(Context, EltTy, NumElts))) {
1113 NumVectorRegs <<= 1;
1116 NumIntermediates = NumVectorRegs;
1118 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1119 if (!isTypeLegal(NewVT))
1121 IntermediateVT = NewVT;
1123 MVT DestVT = getRegisterType(Context, NewVT);
1124 RegisterVT = DestVT;
1125 unsigned NewVTSize = NewVT.getSizeInBits();
1127 // Convert sizes such as i33 to i64.
1128 if (!isPowerOf2_32(NewVTSize))
1129 NewVTSize = NextPowerOf2(NewVTSize);
1131 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1132 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1134 // Otherwise, promotion or legal types use the same number of registers as
1135 // the vector decimated to the appropriate level.
1136 return NumVectorRegs;
1139 /// Get the EVTs and ArgFlags collections that represent the legalized return
1140 /// type of the given function. This does not require a DAG or a return value,
1141 /// and is suitable for use before any DAGs for the function are constructed.
1142 /// TODO: Move this out of TargetLowering.cpp.
1143 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr,
1144 SmallVectorImpl<ISD::OutputArg> &Outs,
1145 const TargetLowering &TLI) {
1146 SmallVector<EVT, 4> ValueVTs;
1147 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1148 unsigned NumValues = ValueVTs.size();
1149 if (NumValues == 0) return;
1151 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1152 EVT VT = ValueVTs[j];
1153 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1155 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1156 ExtendKind = ISD::SIGN_EXTEND;
1157 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1158 ExtendKind = ISD::ZERO_EXTEND;
1160 // FIXME: C calling convention requires the return type to be promoted to
1161 // at least 32-bit. But this is not necessary for non-C calling
1162 // conventions. The frontend should mark functions whose return values
1163 // require promoting with signext or zeroext attributes.
1164 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1165 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1166 if (VT.bitsLT(MinVT))
1170 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1171 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1173 // 'inreg' on function refers to return value
1174 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1175 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1178 // Propagate extension type if any
1179 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1181 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1184 for (unsigned i = 0; i < NumParts; ++i)
1185 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true, 0, 0));
1189 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1190 /// function arguments in the caller parameter area. This is the actual
1191 /// alignment, not its logarithm.
1192 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const {
1193 return TD->getCallFrameTypeAlignment(Ty);
1196 //===----------------------------------------------------------------------===//
1197 // TargetTransformInfo Helpers
1198 //===----------------------------------------------------------------------===//
1200 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1201 enum InstructionOpcodes {
1202 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1203 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1204 #include "llvm/IR/Instruction.def"
1206 switch (static_cast<InstructionOpcodes>(Opcode)) {
1209 case Switch: return 0;
1210 case IndirectBr: return 0;
1211 case Invoke: return 0;
1212 case Resume: return 0;
1213 case Unreachable: return 0;
1214 case Add: return ISD::ADD;
1215 case FAdd: return ISD::FADD;
1216 case Sub: return ISD::SUB;
1217 case FSub: return ISD::FSUB;
1218 case Mul: return ISD::MUL;
1219 case FMul: return ISD::FMUL;
1220 case UDiv: return ISD::UDIV;
1221 case SDiv: return ISD::UDIV;
1222 case FDiv: return ISD::FDIV;
1223 case URem: return ISD::UREM;
1224 case SRem: return ISD::SREM;
1225 case FRem: return ISD::FREM;
1226 case Shl: return ISD::SHL;
1227 case LShr: return ISD::SRL;
1228 case AShr: return ISD::SRA;
1229 case And: return ISD::AND;
1230 case Or: return ISD::OR;
1231 case Xor: return ISD::XOR;
1232 case Alloca: return 0;
1233 case Load: return ISD::LOAD;
1234 case Store: return ISD::STORE;
1235 case GetElementPtr: return 0;
1236 case Fence: return 0;
1237 case AtomicCmpXchg: return 0;
1238 case AtomicRMW: return 0;
1239 case Trunc: return ISD::TRUNCATE;
1240 case ZExt: return ISD::ZERO_EXTEND;
1241 case SExt: return ISD::SIGN_EXTEND;
1242 case FPToUI: return ISD::FP_TO_UINT;
1243 case FPToSI: return ISD::FP_TO_SINT;
1244 case UIToFP: return ISD::UINT_TO_FP;
1245 case SIToFP: return ISD::SINT_TO_FP;
1246 case FPTrunc: return ISD::FP_ROUND;
1247 case FPExt: return ISD::FP_EXTEND;
1248 case PtrToInt: return ISD::BITCAST;
1249 case IntToPtr: return ISD::BITCAST;
1250 case BitCast: return ISD::BITCAST;
1251 case ICmp: return ISD::SETCC;
1252 case FCmp: return ISD::SETCC;
1254 case Call: return 0;
1255 case Select: return ISD::SELECT;
1256 case UserOp1: return 0;
1257 case UserOp2: return 0;
1258 case VAArg: return 0;
1259 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1260 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1261 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1262 case ExtractValue: return ISD::MERGE_VALUES;
1263 case InsertValue: return ISD::MERGE_VALUES;
1264 case LandingPad: return 0;
1267 llvm_unreachable("Unknown instruction type encountered!");
1270 std::pair<unsigned, MVT>
1271 TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const {
1272 LLVMContext &C = Ty->getContext();
1273 EVT MTy = getValueType(Ty);
1276 // We keep legalizing the type until we find a legal kind. We assume that
1277 // the only operation that costs anything is the split. After splitting
1278 // we need to handle two types.
1280 LegalizeKind LK = getTypeConversion(C, MTy);
1282 if (LK.first == TypeLegal)
1283 return std::make_pair(Cost, MTy.getSimpleVT());
1285 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1288 // Keep legalizing the type.
1293 //===----------------------------------------------------------------------===//
1294 // Loop Strength Reduction hooks
1295 //===----------------------------------------------------------------------===//
1297 /// isLegalAddressingMode - Return true if the addressing mode represented
1298 /// by AM is legal for this target, for a load/store of the specified type.
1299 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM,
1301 // The default implementation of this implements a conservative RISCy, r+r and
1304 // Allows a sign-extended 16-bit immediate field.
1305 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1308 // No global is ever allowed as a base.
1312 // Only support r+r,
1314 case 0: // "r+i" or just "i", depending on HasBaseReg.
1317 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1319 // Otherwise we have r+r or r+i.
1322 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1324 // Allow 2*r as r+r.