1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/CodeGen/ScheduleDAG.h"
17 #include "llvm/CallingConv.h"
18 #include "llvm/Constants.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/InlineAsm.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineDebugInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/CodeGen/SSARegMap.h"
34 #include "llvm/Target/MRegisterInfo.h"
35 #include "llvm/Target/TargetData.h"
36 #include "llvm/Target/TargetFrameInfo.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetLowering.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/Debug.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
62 // Scheduling heuristics
63 enum SchedHeuristics {
64 defaultScheduling, // Let the target specify its preference.
65 noScheduling, // No scheduling, emit breadth first sequence.
66 simpleScheduling, // Two pass, min. critical path, max. utilization.
67 simpleNoItinScheduling, // Same as above exact using generic latency.
68 listSchedulingBURR, // Bottom-up reg reduction list scheduling.
69 listSchedulingTDRR, // Top-down reg reduction list scheduling.
70 listSchedulingTD // Top-down list scheduler.
74 cl::opt<SchedHeuristics>
77 cl::desc("Choose scheduling style"),
78 cl::init(defaultScheduling),
80 clEnumValN(defaultScheduling, "default",
81 "Target preferred scheduling style"),
82 clEnumValN(noScheduling, "none",
83 "No scheduling: breadth first sequencing"),
84 clEnumValN(simpleScheduling, "simple",
85 "Simple two pass scheduling: minimize critical path "
86 "and maximize processor utilization"),
87 clEnumValN(simpleNoItinScheduling, "simple-noitin",
88 "Simple two pass scheduling: Same as simple "
89 "except using generic latency"),
90 clEnumValN(listSchedulingBURR, "list-burr",
91 "Bottom-up register reduction list scheduling"),
92 clEnumValN(listSchedulingTDRR, "list-tdrr",
93 "Top-down register reduction list scheduling"),
94 clEnumValN(listSchedulingTD, "list-td",
95 "Top-down list scheduler"),
100 /// RegsForValue - This struct represents the physical registers that a
101 /// particular value is assigned and the type information about the value.
102 /// This is needed because values can be promoted into larger registers and
103 /// expanded into multiple smaller registers than the value.
104 struct RegsForValue {
105 /// Regs - This list hold the register (for legal and promoted values)
106 /// or register set (for expanded values) that the value should be assigned
108 std::vector<unsigned> Regs;
110 /// RegVT - The value type of each register.
112 MVT::ValueType RegVT;
114 /// ValueVT - The value type of the LLVM value, which may be promoted from
115 /// RegVT or made from merging the two expanded parts.
116 MVT::ValueType ValueVT;
118 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
120 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
121 : RegVT(regvt), ValueVT(valuevt) {
124 RegsForValue(const std::vector<unsigned> ®s,
125 MVT::ValueType regvt, MVT::ValueType valuevt)
126 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
129 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
130 /// this value and returns the result as a ValueVT value. This uses
131 /// Chain/Flag as the input and updates them for the output Chain/Flag.
132 SDOperand getCopyFromRegs(SelectionDAG &DAG,
133 SDOperand &Chain, SDOperand &Flag) const;
135 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
136 /// specified value into the registers specified by this object. This uses
137 /// Chain/Flag as the input and updates them for the output Chain/Flag.
138 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
139 SDOperand &Chain, SDOperand &Flag) const;
141 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
142 /// operand list. This adds the code marker and includes the number of
143 /// values added into it.
144 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
145 std::vector<SDOperand> &Ops) const;
150 //===--------------------------------------------------------------------===//
151 /// FunctionLoweringInfo - This contains information that is global to a
152 /// function that is used when lowering a region of the function.
153 class FunctionLoweringInfo {
160 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
162 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
163 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
165 /// ValueMap - Since we emit code for the function a basic block at a time,
166 /// we must remember which virtual registers hold the values for
167 /// cross-basic-block values.
168 std::map<const Value*, unsigned> ValueMap;
170 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
171 /// the entry block. This allows the allocas to be efficiently referenced
172 /// anywhere in the function.
173 std::map<const AllocaInst*, int> StaticAllocaMap;
175 unsigned MakeReg(MVT::ValueType VT) {
176 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
179 unsigned CreateRegForValue(const Value *V);
181 unsigned InitializeRegForValue(const Value *V) {
182 unsigned &R = ValueMap[V];
183 assert(R == 0 && "Already initialized this value register!");
184 return R = CreateRegForValue(V);
189 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
190 /// PHI nodes or outside of the basic block that defines it, or used by a
191 /// switch instruction, which may expand to multiple basic blocks.
192 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
193 if (isa<PHINode>(I)) return true;
194 BasicBlock *BB = I->getParent();
195 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
196 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
197 isa<SwitchInst>(*UI))
202 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
203 /// entry block, return true. This includes arguments used by switches, since
204 /// the switch may expand into multiple basic blocks.
205 static bool isOnlyUsedInEntryBlock(Argument *A) {
206 BasicBlock *Entry = A->getParent()->begin();
207 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
208 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
209 return false; // Use not in entry block.
213 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
214 Function &fn, MachineFunction &mf)
215 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
217 // Create a vreg for each argument register that is not dead and is used
218 // outside of the entry block for the function.
219 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
221 if (!isOnlyUsedInEntryBlock(AI))
222 InitializeRegForValue(AI);
224 // Initialize the mapping of values to registers. This is only set up for
225 // instruction values that are used outside of the block that defines
227 Function::iterator BB = Fn.begin(), EB = Fn.end();
228 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
229 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
230 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
231 const Type *Ty = AI->getAllocatedType();
232 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
234 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
237 // If the alignment of the value is smaller than the size of the value,
238 // and if the size of the value is particularly small (<= 8 bytes),
239 // round up to the size of the value for potentially better performance.
241 // FIXME: This could be made better with a preferred alignment hook in
242 // TargetData. It serves primarily to 8-byte align doubles for X86.
243 if (Align < TySize && TySize <= 8) Align = TySize;
244 TySize *= CUI->getValue(); // Get total allocated size.
245 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
246 StaticAllocaMap[AI] =
247 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
250 for (; BB != EB; ++BB)
251 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
252 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
253 if (!isa<AllocaInst>(I) ||
254 !StaticAllocaMap.count(cast<AllocaInst>(I)))
255 InitializeRegForValue(I);
257 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
258 // also creates the initial PHI MachineInstrs, though none of the input
259 // operands are populated.
260 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
261 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
263 MF.getBasicBlockList().push_back(MBB);
265 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
268 for (BasicBlock::iterator I = BB->begin();
269 (PN = dyn_cast<PHINode>(I)); ++I)
270 if (!PN->use_empty()) {
271 MVT::ValueType VT = TLI.getValueType(PN->getType());
272 unsigned NumElements;
273 if (VT != MVT::Vector)
274 NumElements = TLI.getNumElements(VT);
276 MVT::ValueType VT1,VT2;
278 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
281 unsigned PHIReg = ValueMap[PN];
282 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
283 for (unsigned i = 0; i != NumElements; ++i)
284 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
289 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
290 /// the correctly promoted or expanded types. Assign these registers
291 /// consecutive vreg numbers and return the first assigned number.
292 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
293 MVT::ValueType VT = TLI.getValueType(V->getType());
295 // The number of multiples of registers that we need, to, e.g., split up
296 // a <2 x int64> -> 4 x i32 registers.
297 unsigned NumVectorRegs = 1;
299 // If this is a packed type, figure out what type it will decompose into
300 // and how many of the elements it will use.
301 if (VT == MVT::Vector) {
302 const PackedType *PTy = cast<PackedType>(V->getType());
303 unsigned NumElts = PTy->getNumElements();
304 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
306 // Divide the input until we get to a supported size. This will always
307 // end with a scalar if the target doesn't support vectors.
308 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
315 VT = getVectorType(EltTy, NumElts);
318 // The common case is that we will only create one register for this
319 // value. If we have that case, create and return the virtual register.
320 unsigned NV = TLI.getNumElements(VT);
322 // If we are promoting this value, pick the next largest supported type.
323 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
324 unsigned Reg = MakeReg(PromotedType);
325 // If this is a vector of supported or promoted types (e.g. 4 x i16),
326 // create all of the registers.
327 for (unsigned i = 1; i != NumVectorRegs; ++i)
328 MakeReg(PromotedType);
332 // If this value is represented with multiple target registers, make sure
333 // to create enough consecutive registers of the right (smaller) type.
334 unsigned NT = VT-1; // Find the type to use.
335 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
338 unsigned R = MakeReg((MVT::ValueType)NT);
339 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
340 MakeReg((MVT::ValueType)NT);
344 //===----------------------------------------------------------------------===//
345 /// SelectionDAGLowering - This is the common target-independent lowering
346 /// implementation that is parameterized by a TargetLowering object.
347 /// Also, targets can overload any lowering method.
350 class SelectionDAGLowering {
351 MachineBasicBlock *CurMBB;
353 std::map<const Value*, SDOperand> NodeMap;
355 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
356 /// them up and then emit token factor nodes when possible. This allows us to
357 /// get simple disambiguation between loads without worrying about alias
359 std::vector<SDOperand> PendingLoads;
361 /// Case - A pair of values to record the Value for a switch case, and the
362 /// case's target basic block.
363 typedef std::pair<Constant*, MachineBasicBlock*> Case;
364 typedef std::vector<Case>::iterator CaseItr;
365 typedef std::pair<CaseItr, CaseItr> CaseRange;
367 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
368 /// of conditional branches.
370 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
371 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
373 /// CaseBB - The MBB in which to emit the compare and branch
374 MachineBasicBlock *CaseBB;
375 /// LT, GE - If nonzero, we know the current case value must be less-than or
376 /// greater-than-or-equal-to these Constants.
379 /// Range - A pair of iterators representing the range of case values to be
380 /// processed at this point in the binary search tree.
384 /// The comparison function for sorting Case values.
386 bool operator () (const Case& C1, const Case& C2) {
387 if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first))
388 return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue();
390 const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first);
391 return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue();
396 // TLI - This is information that describes the available target features we
397 // need for lowering. This indicates when operations are unavailable,
398 // implemented with a libcall, etc.
401 const TargetData *TD;
403 /// SwitchCases - Vector of CaseBlock structures used to communicate
404 /// SwitchInst code generation information.
405 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
406 SelectionDAGISel::JumpTable JT;
408 /// FuncInfo - Information about the function as a whole.
410 FunctionLoweringInfo &FuncInfo;
412 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
413 FunctionLoweringInfo &funcinfo)
414 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
415 JT(0,0,0,0), FuncInfo(funcinfo) {
418 /// getRoot - Return the current virtual root of the Selection DAG.
420 SDOperand getRoot() {
421 if (PendingLoads.empty())
422 return DAG.getRoot();
424 if (PendingLoads.size() == 1) {
425 SDOperand Root = PendingLoads[0];
427 PendingLoads.clear();
431 // Otherwise, we have to make a token factor node.
432 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
433 PendingLoads.clear();
438 void visit(Instruction &I) { visit(I.getOpcode(), I); }
440 void visit(unsigned Opcode, User &I) {
442 default: assert(0 && "Unknown instruction type encountered!");
444 // Build the switch statement using the Instruction.def file.
445 #define HANDLE_INST(NUM, OPCODE, CLASS) \
446 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
447 #include "llvm/Instruction.def"
451 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
453 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
454 SDOperand SrcValue, SDOperand Root,
457 SDOperand getIntPtrConstant(uint64_t Val) {
458 return DAG.getConstant(Val, TLI.getPointerTy());
461 SDOperand getValue(const Value *V);
463 const SDOperand &setValue(const Value *V, SDOperand NewN) {
464 SDOperand &N = NodeMap[V];
465 assert(N.Val == 0 && "Already set a value for this node!");
469 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
471 bool OutReg, bool InReg,
472 std::set<unsigned> &OutputRegs,
473 std::set<unsigned> &InputRegs);
475 // Terminator instructions.
476 void visitRet(ReturnInst &I);
477 void visitBr(BranchInst &I);
478 void visitSwitch(SwitchInst &I);
479 void visitUnreachable(UnreachableInst &I) { /* noop */ }
481 // Helper for visitSwitch
482 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
483 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
485 // These all get lowered before this pass.
486 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
487 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
489 void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
490 void visitShift(User &I, unsigned Opcode);
491 void visitAdd(User &I) {
492 visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
494 void visitSub(User &I);
495 void visitMul(User &I) {
496 visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
498 void visitDiv(User &I) {
499 const Type *Ty = I.getType();
501 Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
502 Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
504 void visitRem(User &I) {
505 const Type *Ty = I.getType();
506 visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
508 void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
509 void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
510 void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
511 void visitShl(User &I) { visitShift(I, ISD::SHL); }
512 void visitShr(User &I) {
513 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
516 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc,
517 ISD::CondCode FPOpc);
518 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ,
520 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE,
522 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE,
524 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE,
526 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT,
528 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT,
531 void visitExtractElement(User &I);
532 void visitInsertElement(User &I);
533 void visitShuffleVector(User &I);
535 void visitGetElementPtr(User &I);
536 void visitCast(User &I);
537 void visitSelect(User &I);
539 void visitMalloc(MallocInst &I);
540 void visitFree(FreeInst &I);
541 void visitAlloca(AllocaInst &I);
542 void visitLoad(LoadInst &I);
543 void visitStore(StoreInst &I);
544 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
545 void visitCall(CallInst &I);
546 void visitInlineAsm(CallInst &I);
547 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
548 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
550 void visitVAStart(CallInst &I);
551 void visitVAArg(VAArgInst &I);
552 void visitVAEnd(CallInst &I);
553 void visitVACopy(CallInst &I);
554 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
556 void visitMemIntrinsic(CallInst &I, unsigned Op);
558 void visitUserOp1(Instruction &I) {
559 assert(0 && "UserOp1 should not exist at instruction selection time!");
562 void visitUserOp2(Instruction &I) {
563 assert(0 && "UserOp2 should not exist at instruction selection time!");
567 } // end namespace llvm
569 SDOperand SelectionDAGLowering::getValue(const Value *V) {
570 SDOperand &N = NodeMap[V];
573 const Type *VTy = V->getType();
574 MVT::ValueType VT = TLI.getValueType(VTy);
575 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
576 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
577 visit(CE->getOpcode(), *CE);
578 assert(N.Val && "visit didn't populate the ValueMap!");
580 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
581 return N = DAG.getGlobalAddress(GV, VT);
582 } else if (isa<ConstantPointerNull>(C)) {
583 return N = DAG.getConstant(0, TLI.getPointerTy());
584 } else if (isa<UndefValue>(C)) {
585 if (!isa<PackedType>(VTy))
586 return N = DAG.getNode(ISD::UNDEF, VT);
588 // Create a VBUILD_VECTOR of undef nodes.
589 const PackedType *PTy = cast<PackedType>(VTy);
590 unsigned NumElements = PTy->getNumElements();
591 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
593 std::vector<SDOperand> Ops;
594 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
596 // Create a VConstant node with generic Vector type.
597 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
598 Ops.push_back(DAG.getValueType(PVT));
599 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
600 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
601 return N = DAG.getConstantFP(CFP->getValue(), VT);
602 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
603 unsigned NumElements = PTy->getNumElements();
604 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
606 // Now that we know the number and type of the elements, push a
607 // Constant or ConstantFP node onto the ops list for each element of
608 // the packed constant.
609 std::vector<SDOperand> Ops;
610 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
611 for (unsigned i = 0; i != NumElements; ++i)
612 Ops.push_back(getValue(CP->getOperand(i)));
614 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
616 if (MVT::isFloatingPoint(PVT))
617 Op = DAG.getConstantFP(0, PVT);
619 Op = DAG.getConstant(0, PVT);
620 Ops.assign(NumElements, Op);
623 // Create a VBUILD_VECTOR node with generic Vector type.
624 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
625 Ops.push_back(DAG.getValueType(PVT));
626 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
628 // Canonicalize all constant ints to be unsigned.
629 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
633 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
634 std::map<const AllocaInst*, int>::iterator SI =
635 FuncInfo.StaticAllocaMap.find(AI);
636 if (SI != FuncInfo.StaticAllocaMap.end())
637 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
640 std::map<const Value*, unsigned>::const_iterator VMI =
641 FuncInfo.ValueMap.find(V);
642 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
644 unsigned InReg = VMI->second;
646 // If this type is not legal, make it so now.
647 if (VT != MVT::Vector) {
648 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
650 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
652 // Source must be expanded. This input value is actually coming from the
653 // register pair VMI->second and VMI->second+1.
654 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
655 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
656 } else if (DestVT > VT) { // Promotion case
657 if (MVT::isFloatingPoint(VT))
658 N = DAG.getNode(ISD::FP_ROUND, VT, N);
660 N = DAG.getNode(ISD::TRUNCATE, VT, N);
663 // Otherwise, if this is a vector, make it available as a generic vector
665 MVT::ValueType PTyElementVT, PTyLegalElementVT;
666 const PackedType *PTy = cast<PackedType>(VTy);
667 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
670 // Build a VBUILD_VECTOR with the input registers.
671 std::vector<SDOperand> Ops;
672 if (PTyElementVT == PTyLegalElementVT) {
673 // If the value types are legal, just VBUILD the CopyFromReg nodes.
674 for (unsigned i = 0; i != NE; ++i)
675 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
677 } else if (PTyElementVT < PTyLegalElementVT) {
678 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
679 for (unsigned i = 0; i != NE; ++i) {
680 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
682 if (MVT::isFloatingPoint(PTyElementVT))
683 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
685 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
689 // If the register was expanded, use BUILD_PAIR.
690 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
691 for (unsigned i = 0; i != NE/2; ++i) {
692 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
694 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
696 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
700 Ops.push_back(DAG.getConstant(NE, MVT::i32));
701 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
702 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
704 // Finally, use a VBIT_CONVERT to make this available as the appropriate
706 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
707 DAG.getConstant(PTy->getNumElements(),
709 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
716 void SelectionDAGLowering::visitRet(ReturnInst &I) {
717 if (I.getNumOperands() == 0) {
718 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
721 std::vector<SDOperand> NewValues;
722 NewValues.push_back(getRoot());
723 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
724 SDOperand RetOp = getValue(I.getOperand(i));
725 bool isSigned = I.getOperand(i)->getType()->isSigned();
727 // If this is an integer return value, we need to promote it ourselves to
728 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
730 // FIXME: C calling convention requires the return type to be promoted to
731 // at least 32-bit. But this is not necessary for non-C calling conventions.
732 if (MVT::isInteger(RetOp.getValueType()) &&
733 RetOp.getValueType() < MVT::i64) {
734 MVT::ValueType TmpVT;
735 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
736 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
741 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
743 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
745 NewValues.push_back(RetOp);
746 NewValues.push_back(DAG.getConstant(isSigned, MVT::i32));
748 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, NewValues));
751 void SelectionDAGLowering::visitBr(BranchInst &I) {
752 // Update machine-CFG edges.
753 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
754 CurMBB->addSuccessor(Succ0MBB);
756 // Figure out which block is immediately after the current one.
757 MachineBasicBlock *NextBlock = 0;
758 MachineFunction::iterator BBI = CurMBB;
759 if (++BBI != CurMBB->getParent()->end())
762 if (I.isUnconditional()) {
763 // If this is not a fall-through branch, emit the branch.
764 if (Succ0MBB != NextBlock)
765 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
766 DAG.getBasicBlock(Succ0MBB)));
768 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
769 CurMBB->addSuccessor(Succ1MBB);
771 SDOperand Cond = getValue(I.getCondition());
772 if (Succ1MBB == NextBlock) {
773 // If the condition is false, fall through. This means we should branch
774 // if the condition is true to Succ #0.
775 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
776 Cond, DAG.getBasicBlock(Succ0MBB)));
777 } else if (Succ0MBB == NextBlock) {
778 // If the condition is true, fall through. This means we should branch if
779 // the condition is false to Succ #1. Invert the condition first.
780 SDOperand True = DAG.getConstant(1, Cond.getValueType());
781 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
782 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
783 Cond, DAG.getBasicBlock(Succ1MBB)));
785 std::vector<SDOperand> Ops;
786 Ops.push_back(getRoot());
787 // If the false case is the current basic block, then this is a self
788 // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
789 // adds an extra instruction in the loop. Instead, invert the
790 // condition and emit "Loop: ... br!cond Loop; br Out.
791 if (CurMBB == Succ1MBB) {
792 std::swap(Succ0MBB, Succ1MBB);
793 SDOperand True = DAG.getConstant(1, Cond.getValueType());
794 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
796 SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
797 DAG.getBasicBlock(Succ0MBB));
798 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
799 DAG.getBasicBlock(Succ1MBB)));
804 /// visitSwitchCase - Emits the necessary code to represent a single node in
805 /// the binary search tree resulting from lowering a switch instruction.
806 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
807 SDOperand SwitchOp = getValue(CB.SwitchV);
808 SDOperand CaseOp = getValue(CB.CaseC);
809 SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC);
811 // Set NextBlock to be the MBB immediately after the current one, if any.
812 // This is used to avoid emitting unnecessary branches to the next block.
813 MachineBasicBlock *NextBlock = 0;
814 MachineFunction::iterator BBI = CurMBB;
815 if (++BBI != CurMBB->getParent()->end())
818 // If the lhs block is the next block, invert the condition so that we can
819 // fall through to the lhs instead of the rhs block.
820 if (CB.LHSBB == NextBlock) {
821 std::swap(CB.LHSBB, CB.RHSBB);
822 SDOperand True = DAG.getConstant(1, Cond.getValueType());
823 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
825 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
826 DAG.getBasicBlock(CB.LHSBB));
827 if (CB.RHSBB == NextBlock)
830 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
831 DAG.getBasicBlock(CB.RHSBB)));
832 // Update successor info
833 CurMBB->addSuccessor(CB.LHSBB);
834 CurMBB->addSuccessor(CB.RHSBB);
837 /// visitSwitchCase - Emits the necessary code to represent a single node in
838 /// the binary search tree resulting from lowering a switch instruction.
839 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
840 // FIXME: Need to emit different code for PIC vs. Non-PIC, specifically,
841 // we need to add the address of the jump table to the value loaded, since
842 // the entries in the jump table will be differences rather than absolute
845 // Emit the code for the jump table
846 MVT::ValueType PTy = TLI.getPointerTy();
847 unsigned PTyBytes = MVT::getSizeInBits(PTy)/8;
848 SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
849 SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy,
850 DAG.getConstant(PTyBytes, PTy));
851 SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, DAG.getJumpTable(JT.JTI,PTy));
852 SDOperand LD = DAG.getLoad(PTy, Copy.getValue(1), ADD, DAG.getSrcValue(0));
853 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD));
856 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
857 // Figure out which block is immediately after the current one.
858 MachineBasicBlock *NextBlock = 0;
859 MachineFunction::iterator BBI = CurMBB;
860 if (++BBI != CurMBB->getParent()->end())
863 // If there is only the default destination, branch to it if it is not the
864 // next basic block. Otherwise, just fall through.
865 if (I.getNumOperands() == 2) {
866 // Update machine-CFG edges.
867 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()];
868 // If this is not a fall-through branch, emit the branch.
869 if (DefaultMBB != NextBlock)
870 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
871 DAG.getBasicBlock(DefaultMBB)));
875 // If there are any non-default case statements, create a vector of Cases
876 // representing each one, and sort the vector so that we can efficiently
877 // create a binary search tree from them.
878 std::vector<Case> Cases;
879 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
880 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
881 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
883 std::sort(Cases.begin(), Cases.end(), CaseCmp());
885 // Get the Value to be switched on and default basic blocks, which will be
886 // inserted into CaseBlock records, representing basic blocks in the binary
888 Value *SV = I.getOperand(0);
889 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
891 // Get the MachineFunction which holds the current MBB. This is used during
892 // emission of jump tables, and when inserting any additional MBBs necessary
893 // to represent the switch.
894 MachineFunction *CurMF = CurMBB->getParent();
895 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
896 Reloc::Model Relocs = TLI.getTargetMachine().getRelocationModel();
898 // If the switch has more than 5 blocks, and at least 31.25% dense, and the
899 // target supports indirect branches, then emit a jump table rather than
900 // lowering the switch to a binary tree of conditional branches.
901 // FIXME: Make this work with PIC code
902 if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) &&
903 (Relocs == Reloc::Static || Relocs == Reloc::DynamicNoPIC) &&
905 uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue();
906 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getRawValue();
907 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
909 if (Density >= 0.3125) {
910 // Create a new basic block to hold the code for loading the address
911 // of the jump table, and jumping to it. Update successor information;
912 // we will either branch to the default case for the switch, or the jump
914 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
915 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
916 CurMBB->addSuccessor(Default);
917 CurMBB->addSuccessor(JumpTableBB);
919 // Subtract the lowest switch case value from the value being switched on
920 // and conditional branch to default mbb if the result is greater than the
921 // difference between smallest and largest cases.
922 SDOperand SwitchOp = getValue(SV);
923 MVT::ValueType VT = SwitchOp.getValueType();
924 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
925 DAG.getConstant(First, VT));
927 // The SDNode we just created, which holds the value being switched on
928 // minus the the smallest case value, needs to be copied to a virtual
929 // register so it can be used as an index into the jump table in a
930 // subsequent basic block. This value may be smaller or larger than the
931 // target's pointer type, and therefore require extension or truncating.
932 if (VT > TLI.getPointerTy())
933 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
935 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
936 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
937 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
939 // Emit the range check for the jump table, and branch to the default
940 // block for the switch statement if the value being switched on exceeds
941 // the largest case in the switch.
942 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
943 DAG.getConstant(Last-First,VT), ISD::SETUGT);
944 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
945 DAG.getBasicBlock(Default)));
947 // Build a vector of destination BBs, corresponding to each target
948 // of the jump table. If the value of the jump table slot corresponds to
949 // a case statement, push the case's BB onto the vector, otherwise, push
951 std::set<MachineBasicBlock*> UniqueBBs;
952 std::vector<MachineBasicBlock*> DestBBs;
953 uint64_t TEI = First;
954 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) {
955 if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) {
956 DestBBs.push_back(ii->second);
957 UniqueBBs.insert(ii->second);
960 DestBBs.push_back(Default);
961 UniqueBBs.insert(Default);
965 // Update successor info
966 for (std::set<MachineBasicBlock*>::iterator ii = UniqueBBs.begin(),
967 ee = UniqueBBs.end(); ii != ee; ++ii)
968 JumpTableBB->addSuccessor(*ii);
970 // Create a jump table index for this jump table, or return an existing
972 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
974 // Set the jump table information so that we can codegen it as a second
976 JT.Reg = JumpTableReg;
978 JT.MBB = JumpTableBB;
979 JT.Default = Default;
984 // Push the initial CaseRec onto the worklist
985 std::vector<CaseRec> CaseVec;
986 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
988 while (!CaseVec.empty()) {
989 // Grab a record representing a case range to process off the worklist
990 CaseRec CR = CaseVec.back();
993 // Size is the number of Cases represented by this range. If Size is 1,
994 // then we are processing a leaf of the binary search tree. Otherwise,
995 // we need to pick a pivot, and push left and right ranges onto the
997 unsigned Size = CR.Range.second - CR.Range.first;
1000 // Create a CaseBlock record representing a conditional branch to
1001 // the Case's target mbb if the value being switched on SV is equal
1002 // to C. Otherwise, branch to default.
1003 Constant *C = CR.Range.first->first;
1004 MachineBasicBlock *Target = CR.Range.first->second;
1005 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1007 // If the MBB representing the leaf node is the current MBB, then just
1008 // call visitSwitchCase to emit the code into the current block.
1009 // Otherwise, push the CaseBlock onto the vector to be later processed
1010 // by SDISel, and insert the node's MBB before the next MBB.
1011 if (CR.CaseBB == CurMBB)
1012 visitSwitchCase(CB);
1014 SwitchCases.push_back(CB);
1015 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1018 // split case range at pivot
1019 CaseItr Pivot = CR.Range.first + (Size / 2);
1020 CaseRange LHSR(CR.Range.first, Pivot);
1021 CaseRange RHSR(Pivot, CR.Range.second);
1022 Constant *C = Pivot->first;
1023 MachineBasicBlock *RHSBB = 0, *LHSBB = 0;
1024 // We know that we branch to the LHS if the Value being switched on is
1025 // less than the Pivot value, C. We use this to optimize our binary
1026 // tree a bit, by recognizing that if SV is greater than or equal to the
1027 // LHS's Case Value, and that Case Value is exactly one less than the
1028 // Pivot's Value, then we can branch directly to the LHS's Target,
1029 // rather than creating a leaf node for it.
1030 if ((LHSR.second - LHSR.first) == 1 &&
1031 LHSR.first->first == CR.GE &&
1032 cast<ConstantIntegral>(C)->getRawValue() ==
1033 (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) {
1034 LHSBB = LHSR.first->second;
1036 LHSBB = new MachineBasicBlock(LLVMBB);
1037 CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR));
1039 // Similar to the optimization above, if the Value being switched on is
1040 // known to be less than the Constant CR.LT, and the current Case Value
1041 // is CR.LT - 1, then we can branch directly to the target block for
1042 // the current Case Value, rather than emitting a RHS leaf node for it.
1043 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1044 cast<ConstantIntegral>(RHSR.first->first)->getRawValue() ==
1045 (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) {
1046 RHSBB = RHSR.first->second;
1048 RHSBB = new MachineBasicBlock(LLVMBB);
1049 CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR));
1051 // Create a CaseBlock record representing a conditional branch to
1052 // the LHS node if the value being switched on SV is less than C.
1053 // Otherwise, branch to LHS.
1054 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
1055 SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB);
1056 if (CR.CaseBB == CurMBB)
1057 visitSwitchCase(CB);
1059 SwitchCases.push_back(CB);
1060 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1066 void SelectionDAGLowering::visitSub(User &I) {
1067 // -0.0 - X --> fneg
1068 if (I.getType()->isFloatingPoint()) {
1069 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1070 if (CFP->isExactlyValue(-0.0)) {
1071 SDOperand Op2 = getValue(I.getOperand(1));
1072 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1076 visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
1079 void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
1081 const Type *Ty = I.getType();
1082 SDOperand Op1 = getValue(I.getOperand(0));
1083 SDOperand Op2 = getValue(I.getOperand(1));
1085 if (Ty->isIntegral()) {
1086 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
1087 } else if (Ty->isFloatingPoint()) {
1088 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
1090 const PackedType *PTy = cast<PackedType>(Ty);
1091 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1092 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1093 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1097 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1098 SDOperand Op1 = getValue(I.getOperand(0));
1099 SDOperand Op2 = getValue(I.getOperand(1));
1101 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1103 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1106 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
1107 ISD::CondCode UnsignedOpcode,
1108 ISD::CondCode FPOpcode) {
1109 SDOperand Op1 = getValue(I.getOperand(0));
1110 SDOperand Op2 = getValue(I.getOperand(1));
1111 ISD::CondCode Opcode = SignedOpcode;
1112 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint())
1114 else if (I.getOperand(0)->getType()->isUnsigned())
1115 Opcode = UnsignedOpcode;
1116 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1119 void SelectionDAGLowering::visitSelect(User &I) {
1120 SDOperand Cond = getValue(I.getOperand(0));
1121 SDOperand TrueVal = getValue(I.getOperand(1));
1122 SDOperand FalseVal = getValue(I.getOperand(2));
1123 if (!isa<PackedType>(I.getType())) {
1124 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1125 TrueVal, FalseVal));
1127 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1128 *(TrueVal.Val->op_end()-2),
1129 *(TrueVal.Val->op_end()-1)));
1133 void SelectionDAGLowering::visitCast(User &I) {
1134 SDOperand N = getValue(I.getOperand(0));
1135 MVT::ValueType SrcVT = N.getValueType();
1136 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1138 if (DestVT == MVT::Vector) {
1139 // This is a cast to a vector from something else. This is always a bit
1140 // convert. Get information about the input vector.
1141 const PackedType *DestTy = cast<PackedType>(I.getType());
1142 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1143 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1144 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1145 DAG.getValueType(EltVT)));
1146 } else if (SrcVT == DestVT) {
1147 setValue(&I, N); // noop cast.
1148 } else if (DestVT == MVT::i1) {
1149 // Cast to bool is a comparison against zero, not truncation to zero.
1150 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
1151 DAG.getConstantFP(0.0, N.getValueType());
1152 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
1153 } else if (isInteger(SrcVT)) {
1154 if (isInteger(DestVT)) { // Int -> Int cast
1155 if (DestVT < SrcVT) // Truncating cast?
1156 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1157 else if (I.getOperand(0)->getType()->isSigned())
1158 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1160 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1161 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast
1162 if (I.getOperand(0)->getType()->isSigned())
1163 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1165 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1167 assert(0 && "Unknown cast!");
1169 } else if (isFloatingPoint(SrcVT)) {
1170 if (isFloatingPoint(DestVT)) { // FP -> FP cast
1171 if (DestVT < SrcVT) // Rounding cast?
1172 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1174 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1175 } else if (isInteger(DestVT)) { // FP -> Int cast.
1176 if (I.getType()->isSigned())
1177 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1179 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1181 assert(0 && "Unknown cast!");
1184 assert(SrcVT == MVT::Vector && "Unknown cast!");
1185 assert(DestVT != MVT::Vector && "Casts to vector already handled!");
1186 // This is a cast from a vector to something else. This is always a bit
1187 // convert. Get information about the input vector.
1188 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1192 void SelectionDAGLowering::visitInsertElement(User &I) {
1193 SDOperand InVec = getValue(I.getOperand(0));
1194 SDOperand InVal = getValue(I.getOperand(1));
1195 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1196 getValue(I.getOperand(2)));
1198 SDOperand Num = *(InVec.Val->op_end()-2);
1199 SDOperand Typ = *(InVec.Val->op_end()-1);
1200 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1201 InVec, InVal, InIdx, Num, Typ));
1204 void SelectionDAGLowering::visitExtractElement(User &I) {
1205 SDOperand InVec = getValue(I.getOperand(0));
1206 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1207 getValue(I.getOperand(1)));
1208 SDOperand Typ = *(InVec.Val->op_end()-1);
1209 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1210 TLI.getValueType(I.getType()), InVec, InIdx));
1213 void SelectionDAGLowering::visitShuffleVector(User &I) {
1214 SDOperand V1 = getValue(I.getOperand(0));
1215 SDOperand V2 = getValue(I.getOperand(1));
1216 SDOperand Mask = getValue(I.getOperand(2));
1218 SDOperand Num = *(V1.Val->op_end()-2);
1219 SDOperand Typ = *(V2.Val->op_end()-1);
1220 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1221 V1, V2, Mask, Num, Typ));
1225 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1226 SDOperand N = getValue(I.getOperand(0));
1227 const Type *Ty = I.getOperand(0)->getType();
1229 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1232 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1233 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
1236 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
1237 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1238 getIntPtrConstant(Offset));
1240 Ty = StTy->getElementType(Field);
1242 Ty = cast<SequentialType>(Ty)->getElementType();
1244 // If this is a constant subscript, handle it quickly.
1245 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1246 if (CI->getRawValue() == 0) continue;
1249 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
1250 Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
1252 Offs = TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
1253 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1257 // N = N + Idx * ElementSize;
1258 uint64_t ElementSize = TD->getTypeSize(Ty);
1259 SDOperand IdxN = getValue(Idx);
1261 // If the index is smaller or larger than intptr_t, truncate or extend
1263 if (IdxN.getValueType() < N.getValueType()) {
1264 if (Idx->getType()->isSigned())
1265 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1267 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
1268 } else if (IdxN.getValueType() > N.getValueType())
1269 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1271 // If this is a multiply by a power of two, turn it into a shl
1272 // immediately. This is a very common case.
1273 if (isPowerOf2_64(ElementSize)) {
1274 unsigned Amt = Log2_64(ElementSize);
1275 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1276 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1277 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1281 SDOperand Scale = getIntPtrConstant(ElementSize);
1282 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1283 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1289 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1290 // If this is a fixed sized alloca in the entry block of the function,
1291 // allocate it statically on the stack.
1292 if (FuncInfo.StaticAllocaMap.count(&I))
1293 return; // getValue will auto-populate this.
1295 const Type *Ty = I.getAllocatedType();
1296 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1297 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
1300 SDOperand AllocSize = getValue(I.getArraySize());
1301 MVT::ValueType IntPtr = TLI.getPointerTy();
1302 if (IntPtr < AllocSize.getValueType())
1303 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1304 else if (IntPtr > AllocSize.getValueType())
1305 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1307 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1308 getIntPtrConstant(TySize));
1310 // Handle alignment. If the requested alignment is less than or equal to the
1311 // stack alignment, ignore it and round the size of the allocation up to the
1312 // stack alignment size. If the size is greater than the stack alignment, we
1313 // note this in the DYNAMIC_STACKALLOC node.
1314 unsigned StackAlign =
1315 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1316 if (Align <= StackAlign) {
1318 // Add SA-1 to the size.
1319 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1320 getIntPtrConstant(StackAlign-1));
1321 // Mask out the low bits for alignment purposes.
1322 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1323 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1326 std::vector<MVT::ValueType> VTs;
1327 VTs.push_back(AllocSize.getValueType());
1328 VTs.push_back(MVT::Other);
1329 std::vector<SDOperand> Ops;
1330 Ops.push_back(getRoot());
1331 Ops.push_back(AllocSize);
1332 Ops.push_back(getIntPtrConstant(Align));
1333 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
1334 DAG.setRoot(setValue(&I, DSA).getValue(1));
1336 // Inform the Frame Information that we have just allocated a variable-sized
1338 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1341 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1342 SDOperand Ptr = getValue(I.getOperand(0));
1348 // Do not serialize non-volatile loads against each other.
1349 Root = DAG.getRoot();
1352 setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)),
1353 Root, I.isVolatile()));
1356 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1357 SDOperand SrcValue, SDOperand Root,
1360 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1361 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1362 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue);
1364 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue);
1368 DAG.setRoot(L.getValue(1));
1370 PendingLoads.push_back(L.getValue(1));
1376 void SelectionDAGLowering::visitStore(StoreInst &I) {
1377 Value *SrcV = I.getOperand(0);
1378 SDOperand Src = getValue(SrcV);
1379 SDOperand Ptr = getValue(I.getOperand(1));
1380 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
1381 DAG.getSrcValue(I.getOperand(1))));
1384 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1385 /// access memory and has no other side effects at all.
1386 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1387 #define GET_NO_MEMORY_INTRINSICS
1388 #include "llvm/Intrinsics.gen"
1389 #undef GET_NO_MEMORY_INTRINSICS
1393 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1394 // have any side-effects or if it only reads memory.
1395 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1396 #define GET_SIDE_EFFECT_INFO
1397 #include "llvm/Intrinsics.gen"
1398 #undef GET_SIDE_EFFECT_INFO
1402 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1404 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1405 unsigned Intrinsic) {
1406 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1407 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1409 // Build the operand list.
1410 std::vector<SDOperand> Ops;
1411 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1413 // We don't need to serialize loads against other loads.
1414 Ops.push_back(DAG.getRoot());
1416 Ops.push_back(getRoot());
1420 // Add the intrinsic ID as an integer operand.
1421 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1423 // Add all operands of the call to the operand list.
1424 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1425 SDOperand Op = getValue(I.getOperand(i));
1427 // If this is a vector type, force it to the right packed type.
1428 if (Op.getValueType() == MVT::Vector) {
1429 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1430 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1432 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1433 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1434 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1437 assert(TLI.isTypeLegal(Op.getValueType()) &&
1438 "Intrinsic uses a non-legal type?");
1442 std::vector<MVT::ValueType> VTs;
1443 if (I.getType() != Type::VoidTy) {
1444 MVT::ValueType VT = TLI.getValueType(I.getType());
1445 if (VT == MVT::Vector) {
1446 const PackedType *DestTy = cast<PackedType>(I.getType());
1447 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1449 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1450 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1453 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1457 VTs.push_back(MVT::Other);
1462 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, Ops);
1463 else if (I.getType() != Type::VoidTy)
1464 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, Ops);
1466 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
1469 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1471 PendingLoads.push_back(Chain);
1475 if (I.getType() != Type::VoidTy) {
1476 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1477 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1478 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1479 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1480 DAG.getValueType(EVT));
1482 setValue(&I, Result);
1486 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1487 /// we want to emit this as a call to a named external function, return the name
1488 /// otherwise lower it and return null.
1490 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1491 switch (Intrinsic) {
1493 // By default, turn this into a target intrinsic node.
1494 visitTargetIntrinsic(I, Intrinsic);
1496 case Intrinsic::vastart: visitVAStart(I); return 0;
1497 case Intrinsic::vaend: visitVAEnd(I); return 0;
1498 case Intrinsic::vacopy: visitVACopy(I); return 0;
1499 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1500 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1501 case Intrinsic::setjmp:
1502 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1504 case Intrinsic::longjmp:
1505 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1507 case Intrinsic::memcpy_i32:
1508 case Intrinsic::memcpy_i64:
1509 visitMemIntrinsic(I, ISD::MEMCPY);
1511 case Intrinsic::memset_i32:
1512 case Intrinsic::memset_i64:
1513 visitMemIntrinsic(I, ISD::MEMSET);
1515 case Intrinsic::memmove_i32:
1516 case Intrinsic::memmove_i64:
1517 visitMemIntrinsic(I, ISD::MEMMOVE);
1520 case Intrinsic::dbg_stoppoint: {
1521 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1522 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1523 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
1524 std::vector<SDOperand> Ops;
1526 Ops.push_back(getRoot());
1527 Ops.push_back(getValue(SPI.getLineValue()));
1528 Ops.push_back(getValue(SPI.getColumnValue()));
1530 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
1531 assert(DD && "Not a debug information descriptor");
1532 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1534 Ops.push_back(DAG.getString(CompileUnit->getFileName()));
1535 Ops.push_back(DAG.getString(CompileUnit->getDirectory()));
1537 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops));
1542 case Intrinsic::dbg_region_start: {
1543 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1544 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1545 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
1546 std::vector<SDOperand> Ops;
1548 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
1550 Ops.push_back(getRoot());
1551 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1553 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1558 case Intrinsic::dbg_region_end: {
1559 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1560 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
1561 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
1562 std::vector<SDOperand> Ops;
1564 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
1566 Ops.push_back(getRoot());
1567 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1569 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1574 case Intrinsic::dbg_func_start: {
1575 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1576 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
1577 if (DebugInfo && FSI.getSubprogram() &&
1578 DebugInfo->Verify(FSI.getSubprogram())) {
1579 std::vector<SDOperand> Ops;
1581 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
1583 Ops.push_back(getRoot());
1584 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1586 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1591 case Intrinsic::dbg_declare: {
1592 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1593 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
1594 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
1595 std::vector<SDOperand> Ops;
1597 SDOperand AddressOp = getValue(DI.getAddress());
1598 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) {
1599 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
1606 case Intrinsic::isunordered_f32:
1607 case Intrinsic::isunordered_f64:
1608 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
1609 getValue(I.getOperand(2)), ISD::SETUO));
1612 case Intrinsic::sqrt_f32:
1613 case Intrinsic::sqrt_f64:
1614 setValue(&I, DAG.getNode(ISD::FSQRT,
1615 getValue(I.getOperand(1)).getValueType(),
1616 getValue(I.getOperand(1))));
1618 case Intrinsic::pcmarker: {
1619 SDOperand Tmp = getValue(I.getOperand(1));
1620 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
1623 case Intrinsic::readcyclecounter: {
1624 std::vector<MVT::ValueType> VTs;
1625 VTs.push_back(MVT::i64);
1626 VTs.push_back(MVT::Other);
1627 std::vector<SDOperand> Ops;
1628 Ops.push_back(getRoot());
1629 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops);
1631 DAG.setRoot(Tmp.getValue(1));
1634 case Intrinsic::bswap_i16:
1635 case Intrinsic::bswap_i32:
1636 case Intrinsic::bswap_i64:
1637 setValue(&I, DAG.getNode(ISD::BSWAP,
1638 getValue(I.getOperand(1)).getValueType(),
1639 getValue(I.getOperand(1))));
1641 case Intrinsic::cttz_i8:
1642 case Intrinsic::cttz_i16:
1643 case Intrinsic::cttz_i32:
1644 case Intrinsic::cttz_i64:
1645 setValue(&I, DAG.getNode(ISD::CTTZ,
1646 getValue(I.getOperand(1)).getValueType(),
1647 getValue(I.getOperand(1))));
1649 case Intrinsic::ctlz_i8:
1650 case Intrinsic::ctlz_i16:
1651 case Intrinsic::ctlz_i32:
1652 case Intrinsic::ctlz_i64:
1653 setValue(&I, DAG.getNode(ISD::CTLZ,
1654 getValue(I.getOperand(1)).getValueType(),
1655 getValue(I.getOperand(1))));
1657 case Intrinsic::ctpop_i8:
1658 case Intrinsic::ctpop_i16:
1659 case Intrinsic::ctpop_i32:
1660 case Intrinsic::ctpop_i64:
1661 setValue(&I, DAG.getNode(ISD::CTPOP,
1662 getValue(I.getOperand(1)).getValueType(),
1663 getValue(I.getOperand(1))));
1665 case Intrinsic::stacksave: {
1666 std::vector<MVT::ValueType> VTs;
1667 VTs.push_back(TLI.getPointerTy());
1668 VTs.push_back(MVT::Other);
1669 std::vector<SDOperand> Ops;
1670 Ops.push_back(getRoot());
1671 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, Ops);
1673 DAG.setRoot(Tmp.getValue(1));
1676 case Intrinsic::stackrestore: {
1677 SDOperand Tmp = getValue(I.getOperand(1));
1678 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
1681 case Intrinsic::prefetch:
1682 // FIXME: Currently discarding prefetches.
1688 void SelectionDAGLowering::visitCall(CallInst &I) {
1689 const char *RenameFn = 0;
1690 if (Function *F = I.getCalledFunction()) {
1691 if (F->isExternal())
1692 if (unsigned IID = F->getIntrinsicID()) {
1693 RenameFn = visitIntrinsicCall(I, IID);
1696 } else { // Not an LLVM intrinsic.
1697 const std::string &Name = F->getName();
1698 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
1699 if (I.getNumOperands() == 3 && // Basic sanity checks.
1700 I.getOperand(1)->getType()->isFloatingPoint() &&
1701 I.getType() == I.getOperand(1)->getType() &&
1702 I.getType() == I.getOperand(2)->getType()) {
1703 SDOperand LHS = getValue(I.getOperand(1));
1704 SDOperand RHS = getValue(I.getOperand(2));
1705 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
1709 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
1710 if (I.getNumOperands() == 2 && // Basic sanity checks.
1711 I.getOperand(1)->getType()->isFloatingPoint() &&
1712 I.getType() == I.getOperand(1)->getType()) {
1713 SDOperand Tmp = getValue(I.getOperand(1));
1714 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
1717 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
1718 if (I.getNumOperands() == 2 && // Basic sanity checks.
1719 I.getOperand(1)->getType()->isFloatingPoint() &&
1720 I.getType() == I.getOperand(1)->getType()) {
1721 SDOperand Tmp = getValue(I.getOperand(1));
1722 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
1725 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
1726 if (I.getNumOperands() == 2 && // Basic sanity checks.
1727 I.getOperand(1)->getType()->isFloatingPoint() &&
1728 I.getType() == I.getOperand(1)->getType()) {
1729 SDOperand Tmp = getValue(I.getOperand(1));
1730 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
1735 } else if (isa<InlineAsm>(I.getOperand(0))) {
1742 Callee = getValue(I.getOperand(0));
1744 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
1745 std::vector<std::pair<SDOperand, const Type*> > Args;
1746 Args.reserve(I.getNumOperands());
1747 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1748 Value *Arg = I.getOperand(i);
1749 SDOperand ArgNode = getValue(Arg);
1750 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
1753 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
1754 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1756 std::pair<SDOperand,SDOperand> Result =
1757 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
1758 I.isTailCall(), Callee, Args, DAG);
1759 if (I.getType() != Type::VoidTy)
1760 setValue(&I, Result.first);
1761 DAG.setRoot(Result.second);
1764 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
1765 SDOperand &Chain, SDOperand &Flag)const{
1766 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
1767 Chain = Val.getValue(1);
1768 Flag = Val.getValue(2);
1770 // If the result was expanded, copy from the top part.
1771 if (Regs.size() > 1) {
1772 assert(Regs.size() == 2 &&
1773 "Cannot expand to more than 2 elts yet!");
1774 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
1775 Chain = Val.getValue(1);
1776 Flag = Val.getValue(2);
1777 if (DAG.getTargetLoweringInfo().isLittleEndian())
1778 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
1780 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
1783 // Otherwise, if the return value was promoted or extended, truncate it to the
1784 // appropriate type.
1785 if (RegVT == ValueVT)
1788 if (MVT::isInteger(RegVT)) {
1789 if (ValueVT < RegVT)
1790 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1792 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
1794 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
1798 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
1799 /// specified value into the registers specified by this object. This uses
1800 /// Chain/Flag as the input and updates them for the output Chain/Flag.
1801 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
1802 SDOperand &Chain, SDOperand &Flag) const {
1803 if (Regs.size() == 1) {
1804 // If there is a single register and the types differ, this must be
1806 if (RegVT != ValueVT) {
1807 if (MVT::isInteger(RegVT))
1808 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
1810 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
1812 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
1813 Flag = Chain.getValue(1);
1815 std::vector<unsigned> R(Regs);
1816 if (!DAG.getTargetLoweringInfo().isLittleEndian())
1817 std::reverse(R.begin(), R.end());
1819 for (unsigned i = 0, e = R.size(); i != e; ++i) {
1820 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
1821 DAG.getConstant(i, MVT::i32));
1822 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
1823 Flag = Chain.getValue(1);
1828 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
1829 /// operand list. This adds the code marker and includes the number of
1830 /// values added into it.
1831 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
1832 std::vector<SDOperand> &Ops) const {
1833 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
1834 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1835 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
1838 /// isAllocatableRegister - If the specified register is safe to allocate,
1839 /// i.e. it isn't a stack pointer or some other special register, return the
1840 /// register class for the register. Otherwise, return null.
1841 static const TargetRegisterClass *
1842 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
1843 const TargetLowering &TLI, const MRegisterInfo *MRI) {
1844 MVT::ValueType FoundVT = MVT::Other;
1845 const TargetRegisterClass *FoundRC = 0;
1846 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
1847 E = MRI->regclass_end(); RCI != E; ++RCI) {
1848 MVT::ValueType ThisVT = MVT::Other;
1850 const TargetRegisterClass *RC = *RCI;
1851 // If none of the the value types for this register class are valid, we
1852 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1853 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1855 if (TLI.isTypeLegal(*I)) {
1856 // If we have already found this register in a different register class,
1857 // choose the one with the largest VT specified. For example, on
1858 // PowerPC, we favor f64 register classes over f32.
1859 if (FoundVT == MVT::Other ||
1860 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
1867 if (ThisVT == MVT::Other) continue;
1869 // NOTE: This isn't ideal. In particular, this might allocate the
1870 // frame pointer in functions that need it (due to them not being taken
1871 // out of allocation, because a variable sized allocation hasn't been seen
1872 // yet). This is a slight code pessimization, but should still work.
1873 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
1874 E = RC->allocation_order_end(MF); I != E; ++I)
1876 // We found a matching register class. Keep looking at others in case
1877 // we find one with larger registers that this physreg is also in.
1886 RegsForValue SelectionDAGLowering::
1887 GetRegistersForValue(const std::string &ConstrCode,
1888 MVT::ValueType VT, bool isOutReg, bool isInReg,
1889 std::set<unsigned> &OutputRegs,
1890 std::set<unsigned> &InputRegs) {
1891 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
1892 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
1893 std::vector<unsigned> Regs;
1895 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
1896 MVT::ValueType RegVT;
1897 MVT::ValueType ValueVT = VT;
1899 if (PhysReg.first) {
1900 if (VT == MVT::Other)
1901 ValueVT = *PhysReg.second->vt_begin();
1903 // Get the actual register value type. This is important, because the user
1904 // may have asked for (e.g.) the AX register in i32 type. We need to
1905 // remember that AX is actually i16 to get the right extension.
1906 RegVT = *PhysReg.second->vt_begin();
1908 // This is a explicit reference to a physical register.
1909 Regs.push_back(PhysReg.first);
1911 // If this is an expanded reference, add the rest of the regs to Regs.
1913 TargetRegisterClass::iterator I = PhysReg.second->begin();
1914 TargetRegisterClass::iterator E = PhysReg.second->end();
1915 for (; *I != PhysReg.first; ++I)
1916 assert(I != E && "Didn't find reg!");
1918 // Already added the first reg.
1920 for (; NumRegs; --NumRegs, ++I) {
1921 assert(I != E && "Ran out of registers to allocate!");
1925 return RegsForValue(Regs, RegVT, ValueVT);
1928 // This is a reference to a register class. Allocate NumRegs consecutive,
1929 // available, registers from the class.
1930 std::vector<unsigned> RegClassRegs =
1931 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
1933 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
1934 MachineFunction &MF = *CurMBB->getParent();
1935 unsigned NumAllocated = 0;
1936 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
1937 unsigned Reg = RegClassRegs[i];
1938 // See if this register is available.
1939 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
1940 (isInReg && InputRegs.count(Reg))) { // Already used.
1941 // Make sure we find consecutive registers.
1946 // Check to see if this register is allocatable (i.e. don't give out the
1948 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
1950 // Make sure we find consecutive registers.
1955 // Okay, this register is good, we can use it.
1958 // If we allocated enough consecutive
1959 if (NumAllocated == NumRegs) {
1960 unsigned RegStart = (i-NumAllocated)+1;
1961 unsigned RegEnd = i+1;
1962 // Mark all of the allocated registers used.
1963 for (unsigned i = RegStart; i != RegEnd; ++i) {
1964 unsigned Reg = RegClassRegs[i];
1965 Regs.push_back(Reg);
1966 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
1967 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
1970 return RegsForValue(Regs, *RC->vt_begin(), VT);
1974 // Otherwise, we couldn't allocate enough registers for this.
1975 return RegsForValue();
1979 /// visitInlineAsm - Handle a call to an InlineAsm object.
1981 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
1982 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
1984 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
1987 // Note, we treat inline asms both with and without side-effects as the same.
1988 // If an inline asm doesn't have side effects and doesn't access memory, we
1989 // could not choose to not chain it.
1990 bool hasSideEffects = IA->hasSideEffects();
1992 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
1993 std::vector<MVT::ValueType> ConstraintVTs;
1995 /// AsmNodeOperands - A list of pairs. The first element is a register, the
1996 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
1997 /// if it is a def of that register.
1998 std::vector<SDOperand> AsmNodeOperands;
1999 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
2000 AsmNodeOperands.push_back(AsmStr);
2002 SDOperand Chain = getRoot();
2005 // We fully assign registers here at isel time. This is not optimal, but
2006 // should work. For register classes that correspond to LLVM classes, we
2007 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
2008 // over the constraints, collecting fixed registers that we know we can't use.
2009 std::set<unsigned> OutputRegs, InputRegs;
2011 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2012 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2013 std::string &ConstraintCode = Constraints[i].Codes[0];
2015 MVT::ValueType OpVT;
2017 // Compute the value type for each operand and add it to ConstraintVTs.
2018 switch (Constraints[i].Type) {
2019 case InlineAsm::isOutput:
2020 if (!Constraints[i].isIndirectOutput) {
2021 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2022 OpVT = TLI.getValueType(I.getType());
2024 const Type *OpTy = I.getOperand(OpNum)->getType();
2025 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2026 OpNum++; // Consumes a call operand.
2029 case InlineAsm::isInput:
2030 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2031 OpNum++; // Consumes a call operand.
2033 case InlineAsm::isClobber:
2038 ConstraintVTs.push_back(OpVT);
2040 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2041 continue; // Not assigned a fixed reg.
2043 // Build a list of regs that this operand uses. This always has a single
2044 // element for promoted/expanded operands.
2045 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2047 OutputRegs, InputRegs);
2049 switch (Constraints[i].Type) {
2050 case InlineAsm::isOutput:
2051 // We can't assign any other output to this register.
2052 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2053 // If this is an early-clobber output, it cannot be assigned to the same
2054 // value as the input reg.
2055 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2056 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2058 case InlineAsm::isInput:
2059 // We can't assign any other input to this register.
2060 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2062 case InlineAsm::isClobber:
2063 // Clobbered regs cannot be used as inputs or outputs.
2064 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2065 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2070 // Loop over all of the inputs, copying the operand values into the
2071 // appropriate registers and processing the output regs.
2072 RegsForValue RetValRegs;
2073 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2076 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2077 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2078 std::string &ConstraintCode = Constraints[i].Codes[0];
2080 switch (Constraints[i].Type) {
2081 case InlineAsm::isOutput: {
2082 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2083 if (ConstraintCode.size() == 1) // not a physreg name.
2084 CTy = TLI.getConstraintType(ConstraintCode[0]);
2086 if (CTy == TargetLowering::C_Memory) {
2088 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2090 // Check that the operand (the address to store to) isn't a float.
2091 if (!MVT::isInteger(InOperandVal.getValueType()))
2092 assert(0 && "MATCH FAIL!");
2094 if (!Constraints[i].isIndirectOutput)
2095 assert(0 && "MATCH FAIL!");
2097 OpNum++; // Consumes a call operand.
2099 // Extend/truncate to the right pointer type if needed.
2100 MVT::ValueType PtrType = TLI.getPointerTy();
2101 if (InOperandVal.getValueType() < PtrType)
2102 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2103 else if (InOperandVal.getValueType() > PtrType)
2104 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2106 // Add information to the INLINEASM node to know about this output.
2107 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2108 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2109 AsmNodeOperands.push_back(InOperandVal);
2113 // Otherwise, this is a register output.
2114 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2116 // If this is an early-clobber output, or if there is an input
2117 // constraint that matches this, we need to reserve the input register
2118 // so no other inputs allocate to it.
2119 bool UsesInputRegister = false;
2120 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2121 UsesInputRegister = true;
2123 // Copy the output from the appropriate register. Find a register that
2126 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2127 true, UsesInputRegister,
2128 OutputRegs, InputRegs);
2129 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
2131 if (!Constraints[i].isIndirectOutput) {
2132 assert(RetValRegs.Regs.empty() &&
2133 "Cannot have multiple output constraints yet!");
2134 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2137 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2138 I.getOperand(OpNum)));
2139 OpNum++; // Consumes a call operand.
2142 // Add information to the INLINEASM node to know that this register is
2144 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2147 case InlineAsm::isInput: {
2148 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2149 OpNum++; // Consumes a call operand.
2151 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2152 // If this is required to match an output register we have already set,
2153 // just use its register.
2154 unsigned OperandNo = atoi(ConstraintCode.c_str());
2156 // Scan until we find the definition we already emitted of this operand.
2157 // When we find it, create a RegsForValue operand.
2158 unsigned CurOp = 2; // The first operand.
2159 for (; OperandNo; --OperandNo) {
2160 // Advance to the next operand.
2162 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2163 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2164 "Skipped past definitions?");
2165 CurOp += (NumOps>>3)+1;
2169 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2170 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2171 "Skipped past definitions?");
2173 // Add NumOps>>3 registers to MatchedRegs.
2174 RegsForValue MatchedRegs;
2175 MatchedRegs.ValueVT = InOperandVal.getValueType();
2176 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2177 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2178 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2179 MatchedRegs.Regs.push_back(Reg);
2182 // Use the produced MatchedRegs object to
2183 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
2184 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2188 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2189 if (ConstraintCode.size() == 1) // not a physreg name.
2190 CTy = TLI.getConstraintType(ConstraintCode[0]);
2192 if (CTy == TargetLowering::C_Other) {
2193 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
2194 assert(0 && "MATCH FAIL!");
2196 // Add information to the INLINEASM node to know about this input.
2197 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2198 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2199 AsmNodeOperands.push_back(InOperandVal);
2201 } else if (CTy == TargetLowering::C_Memory) {
2204 // Check that the operand isn't a float.
2205 if (!MVT::isInteger(InOperandVal.getValueType()))
2206 assert(0 && "MATCH FAIL!");
2208 // Extend/truncate to the right pointer type if needed.
2209 MVT::ValueType PtrType = TLI.getPointerTy();
2210 if (InOperandVal.getValueType() < PtrType)
2211 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2212 else if (InOperandVal.getValueType() > PtrType)
2213 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2215 // Add information to the INLINEASM node to know about this input.
2216 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2217 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2218 AsmNodeOperands.push_back(InOperandVal);
2222 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2224 // Copy the input into the appropriate registers.
2225 RegsForValue InRegs =
2226 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2227 false, true, OutputRegs, InputRegs);
2228 // FIXME: should be match fail.
2229 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2231 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
2233 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2236 case InlineAsm::isClobber: {
2237 RegsForValue ClobberedRegs =
2238 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2239 OutputRegs, InputRegs);
2240 // Add the clobbered value to the operand list, so that the register
2241 // allocator is aware that the physreg got clobbered.
2242 if (!ClobberedRegs.Regs.empty())
2243 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2249 // Finish up input operands.
2250 AsmNodeOperands[0] = Chain;
2251 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2253 std::vector<MVT::ValueType> VTs;
2254 VTs.push_back(MVT::Other);
2255 VTs.push_back(MVT::Flag);
2256 Chain = DAG.getNode(ISD::INLINEASM, VTs, AsmNodeOperands);
2257 Flag = Chain.getValue(1);
2259 // If this asm returns a register value, copy the result from that register
2260 // and set it as the value of the call.
2261 if (!RetValRegs.Regs.empty())
2262 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2264 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2266 // Process indirect outputs, first output all of the flagged copies out of
2268 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2269 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2270 Value *Ptr = IndirectStoresToEmit[i].second;
2271 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2272 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2275 // Emit the non-flagged stores from the physregs.
2276 std::vector<SDOperand> OutChains;
2277 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2278 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
2279 StoresToEmit[i].first,
2280 getValue(StoresToEmit[i].second),
2281 DAG.getSrcValue(StoresToEmit[i].second)));
2282 if (!OutChains.empty())
2283 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
2288 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2289 SDOperand Src = getValue(I.getOperand(0));
2291 MVT::ValueType IntPtr = TLI.getPointerTy();
2293 if (IntPtr < Src.getValueType())
2294 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2295 else if (IntPtr > Src.getValueType())
2296 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2298 // Scale the source by the type size.
2299 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
2300 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2301 Src, getIntPtrConstant(ElementSize));
2303 std::vector<std::pair<SDOperand, const Type*> > Args;
2304 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType()));
2306 std::pair<SDOperand,SDOperand> Result =
2307 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
2308 DAG.getExternalSymbol("malloc", IntPtr),
2310 setValue(&I, Result.first); // Pointers always fit in registers
2311 DAG.setRoot(Result.second);
2314 void SelectionDAGLowering::visitFree(FreeInst &I) {
2315 std::vector<std::pair<SDOperand, const Type*> > Args;
2316 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
2317 TLI.getTargetData()->getIntPtrType()));
2318 MVT::ValueType IntPtr = TLI.getPointerTy();
2319 std::pair<SDOperand,SDOperand> Result =
2320 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
2321 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2322 DAG.setRoot(Result.second);
2325 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2326 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2327 // instructions are special in various ways, which require special support to
2328 // insert. The specified MachineInstr is created but not inserted into any
2329 // basic blocks, and the scheduler passes ownership of it to this method.
2330 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2331 MachineBasicBlock *MBB) {
2332 std::cerr << "If a target marks an instruction with "
2333 "'usesCustomDAGSchedInserter', it must implement "
2334 "TargetLowering::InsertAtEndOfBasicBlock!\n";
2339 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2340 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2341 getValue(I.getOperand(1)),
2342 DAG.getSrcValue(I.getOperand(1))));
2345 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2346 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2347 getValue(I.getOperand(0)),
2348 DAG.getSrcValue(I.getOperand(0)));
2350 DAG.setRoot(V.getValue(1));
2353 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2354 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2355 getValue(I.getOperand(1)),
2356 DAG.getSrcValue(I.getOperand(1))));
2359 void SelectionDAGLowering::visitVACopy(CallInst &I) {
2360 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2361 getValue(I.getOperand(1)),
2362 getValue(I.getOperand(2)),
2363 DAG.getSrcValue(I.getOperand(1)),
2364 DAG.getSrcValue(I.getOperand(2))));
2367 /// TargetLowering::LowerArguments - This is the default LowerArguments
2368 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
2369 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
2370 /// integrated into SDISel.
2371 std::vector<SDOperand>
2372 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2373 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2374 std::vector<SDOperand> Ops;
2375 Ops.push_back(DAG.getRoot());
2376 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2377 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2379 // Add one result value for each formal argument.
2380 std::vector<MVT::ValueType> RetVals;
2381 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2382 MVT::ValueType VT = getValueType(I->getType());
2384 switch (getTypeAction(VT)) {
2385 default: assert(0 && "Unknown type action!");
2387 RetVals.push_back(VT);
2390 RetVals.push_back(getTypeToTransformTo(VT));
2393 if (VT != MVT::Vector) {
2394 // If this is a large integer, it needs to be broken up into small
2395 // integers. Figure out what the destination type is and how many small
2396 // integers it turns into.
2397 MVT::ValueType NVT = getTypeToTransformTo(VT);
2398 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2399 for (unsigned i = 0; i != NumVals; ++i)
2400 RetVals.push_back(NVT);
2402 // Otherwise, this is a vector type. We only support legal vectors
2404 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2405 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2407 // Figure out if there is a Packed type corresponding to this Vector
2408 // type. If so, convert to the packed type.
2409 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2410 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2411 RetVals.push_back(TVT);
2413 assert(0 && "Don't support illegal by-val vector arguments yet!");
2420 RetVals.push_back(MVT::Other);
2423 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals, Ops).Val;
2425 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
2427 // Set up the return result vector.
2430 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2431 MVT::ValueType VT = getValueType(I->getType());
2433 switch (getTypeAction(VT)) {
2434 default: assert(0 && "Unknown type action!");
2436 Ops.push_back(SDOperand(Result, i++));
2439 SDOperand Op(Result, i++);
2440 if (MVT::isInteger(VT)) {
2441 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
2443 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
2444 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2446 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2447 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2453 if (VT != MVT::Vector) {
2454 // If this is a large integer, it needs to be reassembled from small
2455 // integers. Figure out what the source elt type is and how many small
2457 MVT::ValueType NVT = getTypeToTransformTo(VT);
2458 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2460 SDOperand Lo = SDOperand(Result, i++);
2461 SDOperand Hi = SDOperand(Result, i++);
2463 if (!isLittleEndian())
2466 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
2468 // Value scalarized into many values. Unimp for now.
2469 assert(0 && "Cannot expand i64 -> i16 yet!");
2472 // Otherwise, this is a vector type. We only support legal vectors
2474 const PackedType *PTy = cast<PackedType>(I->getType());
2475 unsigned NumElems = PTy->getNumElements();
2476 const Type *EltTy = PTy->getElementType();
2478 // Figure out if there is a Packed type corresponding to this Vector
2479 // type. If so, convert to the packed type.
2480 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2481 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2482 SDOperand N = SDOperand(Result, i++);
2483 // Handle copies from generic vectors to registers.
2484 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
2485 DAG.getConstant(NumElems, MVT::i32),
2486 DAG.getValueType(getValueType(EltTy)));
2489 assert(0 && "Don't support illegal by-val vector arguments yet!");
2500 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
2501 /// implementation, which just inserts an ISD::CALL node, which is later custom
2502 /// lowered by the target to something concrete. FIXME: When all targets are
2503 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
2504 std::pair<SDOperand, SDOperand>
2505 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
2506 unsigned CallingConv, bool isTailCall,
2508 ArgListTy &Args, SelectionDAG &DAG) {
2509 std::vector<SDOperand> Ops;
2510 Ops.push_back(Chain); // Op#0 - Chain
2511 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
2512 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
2513 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
2514 Ops.push_back(Callee);
2516 // Handle all of the outgoing arguments.
2517 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
2518 MVT::ValueType VT = getValueType(Args[i].second);
2519 SDOperand Op = Args[i].first;
2520 bool isSigned = Args[i].second->isSigned();
2521 switch (getTypeAction(VT)) {
2522 default: assert(0 && "Unknown type action!");
2525 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2528 if (MVT::isInteger(VT)) {
2529 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2530 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
2532 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2533 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
2536 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2539 if (VT != MVT::Vector) {
2540 // If this is a large integer, it needs to be broken down into small
2541 // integers. Figure out what the source elt type is and how many small
2543 MVT::ValueType NVT = getTypeToTransformTo(VT);
2544 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2546 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2547 DAG.getConstant(0, getPointerTy()));
2548 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2549 DAG.getConstant(1, getPointerTy()));
2550 if (!isLittleEndian())
2554 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2556 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2558 // Value scalarized into many values. Unimp for now.
2559 assert(0 && "Cannot expand i64 -> i16 yet!");
2562 // Otherwise, this is a vector type. We only support legal vectors
2564 const PackedType *PTy = cast<PackedType>(Args[i].second);
2565 unsigned NumElems = PTy->getNumElements();
2566 const Type *EltTy = PTy->getElementType();
2568 // Figure out if there is a Packed type corresponding to this Vector
2569 // type. If so, convert to the packed type.
2570 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2571 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2572 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
2573 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
2575 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2577 assert(0 && "Don't support illegal by-val vector call args yet!");
2585 // Figure out the result value types.
2586 std::vector<MVT::ValueType> RetTys;
2588 if (RetTy != Type::VoidTy) {
2589 MVT::ValueType VT = getValueType(RetTy);
2590 switch (getTypeAction(VT)) {
2591 default: assert(0 && "Unknown type action!");
2593 RetTys.push_back(VT);
2596 RetTys.push_back(getTypeToTransformTo(VT));
2599 if (VT != MVT::Vector) {
2600 // If this is a large integer, it needs to be reassembled from small
2601 // integers. Figure out what the source elt type is and how many small
2603 MVT::ValueType NVT = getTypeToTransformTo(VT);
2604 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2605 for (unsigned i = 0; i != NumVals; ++i)
2606 RetTys.push_back(NVT);
2608 // Otherwise, this is a vector type. We only support legal vectors
2610 const PackedType *PTy = cast<PackedType>(RetTy);
2611 unsigned NumElems = PTy->getNumElements();
2612 const Type *EltTy = PTy->getElementType();
2614 // Figure out if there is a Packed type corresponding to this Vector
2615 // type. If so, convert to the packed type.
2616 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2617 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2618 RetTys.push_back(TVT);
2620 assert(0 && "Don't support illegal by-val vector call results yet!");
2627 RetTys.push_back(MVT::Other); // Always has a chain.
2629 // Finally, create the CALL node.
2630 SDOperand Res = DAG.getNode(ISD::CALL, RetTys, Ops);
2632 // This returns a pair of operands. The first element is the
2633 // return value for the function (if RetTy is not VoidTy). The second
2634 // element is the outgoing token chain.
2636 if (RetTys.size() != 1) {
2637 MVT::ValueType VT = getValueType(RetTy);
2638 if (RetTys.size() == 2) {
2641 // If this value was promoted, truncate it down.
2642 if (ResVal.getValueType() != VT) {
2643 if (VT == MVT::Vector) {
2644 // Insert a VBITCONVERT to convert from the packed result type to the
2645 // MVT::Vector type.
2646 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
2647 const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
2649 // Figure out if there is a Packed type corresponding to this Vector
2650 // type. If so, convert to the packed type.
2651 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2652 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2653 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
2654 // "N x PTyElementVT" MVT::Vector type.
2655 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
2656 DAG.getConstant(NumElems, MVT::i32),
2657 DAG.getValueType(getValueType(EltTy)));
2661 } else if (MVT::isInteger(VT)) {
2662 unsigned AssertOp = RetTy->isSigned() ?
2663 ISD::AssertSext : ISD::AssertZext;
2664 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
2665 DAG.getValueType(VT));
2666 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
2668 assert(MVT::isFloatingPoint(VT));
2669 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
2672 } else if (RetTys.size() == 3) {
2673 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
2674 Res.getValue(0), Res.getValue(1));
2677 assert(0 && "Case not handled yet!");
2681 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
2686 // It is always conservatively correct for llvm.returnaddress and
2687 // llvm.frameaddress to return 0.
2689 // FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
2690 // expanded to 0 if the target wants.
2691 std::pair<SDOperand, SDOperand>
2692 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
2693 unsigned Depth, SelectionDAG &DAG) {
2694 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
2697 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2698 assert(0 && "LowerOperation not implemented for this target!");
2703 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
2704 SelectionDAG &DAG) {
2705 assert(0 && "CustomPromoteOperation not implemented for this target!");
2710 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
2711 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
2712 std::pair<SDOperand,SDOperand> Result =
2713 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
2714 setValue(&I, Result.first);
2715 DAG.setRoot(Result.second);
2718 /// getMemsetValue - Vectorized representation of the memset value
2720 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
2721 SelectionDAG &DAG) {
2722 MVT::ValueType CurVT = VT;
2723 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2724 uint64_t Val = C->getValue() & 255;
2726 while (CurVT != MVT::i8) {
2727 Val = (Val << Shift) | Val;
2729 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2731 return DAG.getConstant(Val, VT);
2733 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
2735 while (CurVT != MVT::i8) {
2737 DAG.getNode(ISD::OR, VT,
2738 DAG.getNode(ISD::SHL, VT, Value,
2739 DAG.getConstant(Shift, MVT::i8)), Value);
2741 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2748 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2749 /// used when a memcpy is turned into a memset when the source is a constant
2751 static SDOperand getMemsetStringVal(MVT::ValueType VT,
2752 SelectionDAG &DAG, TargetLowering &TLI,
2753 std::string &Str, unsigned Offset) {
2754 MVT::ValueType CurVT = VT;
2756 unsigned MSB = getSizeInBits(VT) / 8;
2757 if (TLI.isLittleEndian())
2758 Offset = Offset + MSB - 1;
2759 for (unsigned i = 0; i != MSB; ++i) {
2760 Val = (Val << 8) | Str[Offset];
2761 Offset += TLI.isLittleEndian() ? -1 : 1;
2763 return DAG.getConstant(Val, VT);
2766 /// getMemBasePlusOffset - Returns base and offset node for the
2767 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
2768 SelectionDAG &DAG, TargetLowering &TLI) {
2769 MVT::ValueType VT = Base.getValueType();
2770 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
2773 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
2774 /// to replace the memset / memcpy is below the threshold. It also returns the
2775 /// types of the sequence of memory ops to perform memset / memcpy.
2776 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
2777 unsigned Limit, uint64_t Size,
2778 unsigned Align, TargetLowering &TLI) {
2781 if (TLI.allowsUnalignedMemoryAccesses()) {
2784 switch (Align & 7) {
2800 MVT::ValueType LVT = MVT::i64;
2801 while (!TLI.isTypeLegal(LVT))
2802 LVT = (MVT::ValueType)((unsigned)LVT - 1);
2803 assert(MVT::isInteger(LVT));
2808 unsigned NumMemOps = 0;
2810 unsigned VTSize = getSizeInBits(VT) / 8;
2811 while (VTSize > Size) {
2812 VT = (MVT::ValueType)((unsigned)VT - 1);
2815 assert(MVT::isInteger(VT));
2817 if (++NumMemOps > Limit)
2819 MemOps.push_back(VT);
2826 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
2827 SDOperand Op1 = getValue(I.getOperand(1));
2828 SDOperand Op2 = getValue(I.getOperand(2));
2829 SDOperand Op3 = getValue(I.getOperand(3));
2830 SDOperand Op4 = getValue(I.getOperand(4));
2831 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
2832 if (Align == 0) Align = 1;
2834 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
2835 std::vector<MVT::ValueType> MemOps;
2837 // Expand memset / memcpy to a series of load / store ops
2838 // if the size operand falls below a certain threshold.
2839 std::vector<SDOperand> OutChains;
2841 default: break; // Do nothing for now.
2843 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
2844 Size->getValue(), Align, TLI)) {
2845 unsigned NumMemOps = MemOps.size();
2846 unsigned Offset = 0;
2847 for (unsigned i = 0; i < NumMemOps; i++) {
2848 MVT::ValueType VT = MemOps[i];
2849 unsigned VTSize = getSizeInBits(VT) / 8;
2850 SDOperand Value = getMemsetValue(Op2, VT, DAG);
2851 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(),
2853 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
2854 DAG.getSrcValue(I.getOperand(1), Offset));
2855 OutChains.push_back(Store);
2862 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
2863 Size->getValue(), Align, TLI)) {
2864 unsigned NumMemOps = MemOps.size();
2865 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
2866 GlobalAddressSDNode *G = NULL;
2868 bool CopyFromStr = false;
2870 if (Op2.getOpcode() == ISD::GlobalAddress)
2871 G = cast<GlobalAddressSDNode>(Op2);
2872 else if (Op2.getOpcode() == ISD::ADD &&
2873 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
2874 Op2.getOperand(1).getOpcode() == ISD::Constant) {
2875 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
2876 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
2879 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
2881 Str = GV->getStringValue(false);
2889 for (unsigned i = 0; i < NumMemOps; i++) {
2890 MVT::ValueType VT = MemOps[i];
2891 unsigned VTSize = getSizeInBits(VT) / 8;
2892 SDOperand Value, Chain, Store;
2895 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
2898 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2899 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2900 DAG.getSrcValue(I.getOperand(1), DstOff));
2902 Value = DAG.getLoad(VT, getRoot(),
2903 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
2904 DAG.getSrcValue(I.getOperand(2), SrcOff));
2905 Chain = Value.getValue(1);
2907 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2908 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2909 DAG.getSrcValue(I.getOperand(1), DstOff));
2911 OutChains.push_back(Store);
2920 if (!OutChains.empty()) {
2921 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
2926 std::vector<SDOperand> Ops;
2927 Ops.push_back(getRoot());
2932 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
2935 //===----------------------------------------------------------------------===//
2936 // SelectionDAGISel code
2937 //===----------------------------------------------------------------------===//
2939 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
2940 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
2943 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
2944 // FIXME: we only modify the CFG to split critical edges. This
2945 // updates dom and loop info.
2949 /// OptimizeNoopCopyExpression - We have determined that the specified cast
2950 /// instruction is a noop copy (e.g. it's casting from one pointer type to
2951 /// another, int->uint, or int->sbyte on PPC.
2953 /// Return true if any changes are made.
2954 static bool OptimizeNoopCopyExpression(CastInst *CI) {
2955 BasicBlock *DefBB = CI->getParent();
2957 /// InsertedCasts - Only insert a cast in each block once.
2958 std::map<BasicBlock*, CastInst*> InsertedCasts;
2960 bool MadeChange = false;
2961 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
2963 Use &TheUse = UI.getUse();
2964 Instruction *User = cast<Instruction>(*UI);
2966 // Figure out which BB this cast is used in. For PHI's this is the
2967 // appropriate predecessor block.
2968 BasicBlock *UserBB = User->getParent();
2969 if (PHINode *PN = dyn_cast<PHINode>(User)) {
2970 unsigned OpVal = UI.getOperandNo()/2;
2971 UserBB = PN->getIncomingBlock(OpVal);
2974 // Preincrement use iterator so we don't invalidate it.
2977 // If this user is in the same block as the cast, don't change the cast.
2978 if (UserBB == DefBB) continue;
2980 // If we have already inserted a cast into this block, use it.
2981 CastInst *&InsertedCast = InsertedCasts[UserBB];
2983 if (!InsertedCast) {
2984 BasicBlock::iterator InsertPt = UserBB->begin();
2985 while (isa<PHINode>(InsertPt)) ++InsertPt;
2988 new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
2992 // Replace a use of the cast with a use of the new casat.
2993 TheUse = InsertedCast;
2996 // If we removed all uses, nuke the cast.
2997 if (CI->use_empty())
2998 CI->eraseFromParent();
3003 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
3004 /// casting to the type of GEPI.
3005 static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
3006 Instruction *GEPI, Value *Ptr,
3008 if (V) return V; // Already computed.
3010 BasicBlock::iterator InsertPt;
3011 if (BB == GEPI->getParent()) {
3012 // If insert into the GEP's block, insert right after the GEP.
3016 // Otherwise, insert at the top of BB, after any PHI nodes
3017 InsertPt = BB->begin();
3018 while (isa<PHINode>(InsertPt)) ++InsertPt;
3021 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3022 // BB so that there is only one value live across basic blocks (the cast
3024 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3025 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3026 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3028 // Add the offset, cast it to the right type.
3029 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
3030 return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
3033 /// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3034 /// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
3035 /// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3036 /// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
3037 /// sink PtrOffset into user blocks where doing so will likely allow us to fold
3038 /// the constant add into a load or store instruction. Additionally, if a user
3039 /// is a pointer-pointer cast, we look through it to find its users.
3040 static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3041 Constant *PtrOffset, BasicBlock *DefBB,
3042 GetElementPtrInst *GEPI,
3043 std::map<BasicBlock*,Instruction*> &InsertedExprs) {
3044 while (!RepPtr->use_empty()) {
3045 Instruction *User = cast<Instruction>(RepPtr->use_back());
3047 // If the user is a Pointer-Pointer cast, recurse.
3048 if (isa<CastInst>(User) && isa<PointerType>(User->getType())) {
3049 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3051 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
3052 // could invalidate an iterator.
3053 User->setOperand(0, UndefValue::get(RepPtr->getType()));
3057 // If this is a load of the pointer, or a store through the pointer, emit
3058 // the increment into the load/store block.
3059 Instruction *NewVal;
3060 if (isa<LoadInst>(User) ||
3061 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3062 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3063 User->getParent(), GEPI,
3066 // If this use is not foldable into the addressing mode, use a version
3067 // emitted in the GEP block.
3068 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3072 if (GEPI->getType() != RepPtr->getType()) {
3073 BasicBlock::iterator IP = NewVal;
3075 NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP);
3077 User->replaceUsesOfWith(RepPtr, NewVal);
3082 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3083 /// selection, we want to be a bit careful about some things. In particular, if
3084 /// we have a GEP instruction that is used in a different block than it is
3085 /// defined, the addressing expression of the GEP cannot be folded into loads or
3086 /// stores that use it. In this case, decompose the GEP and move constant
3087 /// indices into blocks that use it.
3088 static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
3089 const TargetData *TD) {
3090 // If this GEP is only used inside the block it is defined in, there is no
3091 // need to rewrite it.
3092 bool isUsedOutsideDefBB = false;
3093 BasicBlock *DefBB = GEPI->getParent();
3094 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3096 if (cast<Instruction>(*UI)->getParent() != DefBB) {
3097 isUsedOutsideDefBB = true;
3101 if (!isUsedOutsideDefBB) return false;
3103 // If this GEP has no non-zero constant indices, there is nothing we can do,
3105 bool hasConstantIndex = false;
3106 bool hasVariableIndex = false;
3107 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3108 E = GEPI->op_end(); OI != E; ++OI) {
3109 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
3110 if (CI->getRawValue()) {
3111 hasConstantIndex = true;
3115 hasVariableIndex = true;
3119 // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3120 if (!hasConstantIndex && !hasVariableIndex) {
3121 Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(),
3122 GEPI->getName(), GEPI);
3123 GEPI->replaceAllUsesWith(NC);
3124 GEPI->eraseFromParent();
3128 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
3129 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3132 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
3133 // constant offset (which we now know is non-zero) and deal with it later.
3134 uint64_t ConstantOffset = 0;
3135 const Type *UIntPtrTy = TD->getIntPtrType();
3136 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3137 const Type *Ty = GEPI->getOperand(0)->getType();
3139 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3140 E = GEPI->op_end(); OI != E; ++OI) {
3142 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3143 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
3145 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
3146 Ty = StTy->getElementType(Field);
3148 Ty = cast<SequentialType>(Ty)->getElementType();
3150 // Handle constant subscripts.
3151 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3152 if (CI->getRawValue() == 0) continue;
3154 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
3155 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
3157 ConstantOffset+=TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
3161 // Ptr = Ptr + Idx * ElementSize;
3163 // Cast Idx to UIntPtrTy if needed.
3164 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
3166 uint64_t ElementSize = TD->getTypeSize(Ty);
3167 // Mask off bits that should not be set.
3168 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3169 Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize);
3171 // Multiply by the element size and add to the base.
3172 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3173 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3177 // Make sure that the offset fits in uintptr_t.
3178 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3179 Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset);
3181 // Okay, we have now emitted all of the variable index parts to the BB that
3182 // the GEP is defined in. Loop over all of the using instructions, inserting
3183 // an "add Ptr, ConstantOffset" into each block that uses it and update the
3184 // instruction to use the newly computed value, making GEPI dead. When the
3185 // user is a load or store instruction address, we emit the add into the user
3186 // block, otherwise we use a canonical version right next to the gep (these
3187 // won't be foldable as addresses, so we might as well share the computation).
3189 std::map<BasicBlock*,Instruction*> InsertedExprs;
3190 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3192 // Finally, the GEP is dead, remove it.
3193 GEPI->eraseFromParent();
3198 bool SelectionDAGISel::runOnFunction(Function &Fn) {
3199 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3200 RegMap = MF.getSSARegMap();
3201 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
3203 // First, split all critical edges for PHI nodes with incoming values that are
3204 // constants, this way the load of the constant into a vreg will not be placed
3205 // into MBBs that are used some other way.
3207 // In this pass we also look for GEP and cast instructions that are used
3208 // across basic blocks and rewrite them to improve basic-block-at-a-time
3212 bool MadeChange = true;
3213 while (MadeChange) {
3215 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
3217 BasicBlock::iterator BBI;
3218 for (BBI = BB->begin(); (PN = dyn_cast<PHINode>(BBI)); ++BBI)
3219 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
3220 if (isa<Constant>(PN->getIncomingValue(i)))
3221 SplitCriticalEdge(PN->getIncomingBlock(i), BB);
3223 for (BasicBlock::iterator E = BB->end(); BBI != E; ) {
3224 Instruction *I = BBI++;
3225 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
3226 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
3227 } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
3228 // If this is a noop copy, sink it into user blocks to reduce the number
3229 // of virtual registers that must be created and coallesced.
3230 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
3231 MVT::ValueType DstVT = TLI.getValueType(CI->getType());
3233 // This is an fp<->int conversion?
3234 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
3237 // If this is an extension, it will be a zero or sign extension, which
3239 if (SrcVT < DstVT) continue;
3241 // If these values will be promoted, find out what they will be promoted
3242 // to. This helps us consider truncates on PPC as noop copies when they
3244 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
3245 SrcVT = TLI.getTypeToTransformTo(SrcVT);
3246 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
3247 DstVT = TLI.getTypeToTransformTo(DstVT);
3249 // If, after promotion, these are the same types, this is a noop copy.
3251 MadeChange |= OptimizeNoopCopyExpression(CI);
3257 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
3259 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
3260 SelectBasicBlock(I, MF, FuncInfo);
3266 SDOperand SelectionDAGISel::
3267 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
3268 SDOperand Op = SDL.getValue(V);
3269 assert((Op.getOpcode() != ISD::CopyFromReg ||
3270 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
3271 "Copy from a reg to the same reg!");
3273 // If this type is not legal, we must make sure to not create an invalid
3275 MVT::ValueType SrcVT = Op.getValueType();
3276 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
3277 SelectionDAG &DAG = SDL.DAG;
3278 if (SrcVT == DestVT) {
3279 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3280 } else if (SrcVT == MVT::Vector) {
3281 // Handle copies from generic vectors to registers.
3282 MVT::ValueType PTyElementVT, PTyLegalElementVT;
3283 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
3284 PTyElementVT, PTyLegalElementVT);
3286 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
3287 // MVT::Vector type.
3288 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
3289 DAG.getConstant(NE, MVT::i32),
3290 DAG.getValueType(PTyElementVT));
3292 // Loop over all of the elements of the resultant vector,
3293 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
3294 // copying them into output registers.
3295 std::vector<SDOperand> OutChains;
3296 SDOperand Root = SDL.getRoot();
3297 for (unsigned i = 0; i != NE; ++i) {
3298 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
3299 Op, DAG.getConstant(i, MVT::i32));
3300 if (PTyElementVT == PTyLegalElementVT) {
3301 // Elements are legal.
3302 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3303 } else if (PTyLegalElementVT > PTyElementVT) {
3304 // Elements are promoted.
3305 if (MVT::isFloatingPoint(PTyLegalElementVT))
3306 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
3308 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
3309 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3311 // Elements are expanded.
3312 // The src value is expanded into multiple registers.
3313 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3314 Elt, DAG.getConstant(0, MVT::i32));
3315 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3316 Elt, DAG.getConstant(1, MVT::i32));
3317 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
3318 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
3321 return DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
3322 } else if (SrcVT < DestVT) {
3323 // The src value is promoted to the register.
3324 if (MVT::isFloatingPoint(SrcVT))
3325 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
3327 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
3328 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3330 // The src value is expanded into multiple registers.
3331 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3332 Op, DAG.getConstant(0, MVT::i32));
3333 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3334 Op, DAG.getConstant(1, MVT::i32));
3335 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
3336 return DAG.getCopyToReg(Op, Reg+1, Hi);
3340 void SelectionDAGISel::
3341 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
3342 std::vector<SDOperand> &UnorderedChains) {
3343 // If this is the entry block, emit arguments.
3344 Function &F = *BB->getParent();
3345 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
3346 SDOperand OldRoot = SDL.DAG.getRoot();
3347 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
3350 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
3352 if (!AI->use_empty()) {
3353 SDL.setValue(AI, Args[a]);
3355 // If this argument is live outside of the entry block, insert a copy from
3356 // whereever we got it to the vreg that other BB's will reference it as.
3357 if (FuncInfo.ValueMap.count(AI)) {
3359 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
3360 UnorderedChains.push_back(Copy);
3364 // Finally, if the target has anything special to do, allow it to do so.
3365 // FIXME: this should insert code into the DAG!
3366 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
3369 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3370 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
3371 FunctionLoweringInfo &FuncInfo) {
3372 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
3374 std::vector<SDOperand> UnorderedChains;
3376 // Lower any arguments needed in this block if this is the entry block.
3377 if (LLVMBB == &LLVMBB->getParent()->front())
3378 LowerArguments(LLVMBB, SDL, UnorderedChains);
3380 BB = FuncInfo.MBBMap[LLVMBB];
3381 SDL.setCurrentBasicBlock(BB);
3383 // Lower all of the non-terminator instructions.
3384 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3388 // Ensure that all instructions which are used outside of their defining
3389 // blocks are available as virtual registers.
3390 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
3391 if (!I->use_empty() && !isa<PHINode>(I)) {
3392 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
3393 if (VMI != FuncInfo.ValueMap.end())
3394 UnorderedChains.push_back(
3395 CopyValueToVirtualRegister(SDL, I, VMI->second));
3398 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
3399 // ensure constants are generated when needed. Remember the virtual registers
3400 // that need to be added to the Machine PHI nodes as input. We cannot just
3401 // directly add them, because expansion might result in multiple MBB's for one
3402 // BB. As such, the start of the BB might correspond to a different MBB than
3406 // Emit constants only once even if used by multiple PHI nodes.
3407 std::map<Constant*, unsigned> ConstantsOut;
3409 // Check successor nodes PHI nodes that expect a constant to be available from
3411 TerminatorInst *TI = LLVMBB->getTerminator();
3412 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
3413 BasicBlock *SuccBB = TI->getSuccessor(succ);
3414 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
3417 // At this point we know that there is a 1-1 correspondence between LLVM PHI
3418 // nodes and Machine PHI nodes, but the incoming operands have not been
3420 for (BasicBlock::iterator I = SuccBB->begin();
3421 (PN = dyn_cast<PHINode>(I)); ++I)
3422 if (!PN->use_empty()) {
3424 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
3425 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
3426 unsigned &RegOut = ConstantsOut[C];
3428 RegOut = FuncInfo.CreateRegForValue(C);
3429 UnorderedChains.push_back(
3430 CopyValueToVirtualRegister(SDL, C, RegOut));
3434 Reg = FuncInfo.ValueMap[PHIOp];
3436 assert(isa<AllocaInst>(PHIOp) &&
3437 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
3438 "Didn't codegen value into a register!??");
3439 Reg = FuncInfo.CreateRegForValue(PHIOp);
3440 UnorderedChains.push_back(
3441 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
3445 // Remember that this register needs to added to the machine PHI node as
3446 // the input for this MBB.
3447 MVT::ValueType VT = TLI.getValueType(PN->getType());
3448 unsigned NumElements;
3449 if (VT != MVT::Vector)
3450 NumElements = TLI.getNumElements(VT);
3452 MVT::ValueType VT1,VT2;
3454 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
3457 for (unsigned i = 0, e = NumElements; i != e; ++i)
3458 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
3461 ConstantsOut.clear();
3463 // Turn all of the unordered chains into one factored node.
3464 if (!UnorderedChains.empty()) {
3465 SDOperand Root = SDL.getRoot();
3466 if (Root.getOpcode() != ISD::EntryToken) {
3467 unsigned i = 0, e = UnorderedChains.size();
3468 for (; i != e; ++i) {
3469 assert(UnorderedChains[i].Val->getNumOperands() > 1);
3470 if (UnorderedChains[i].Val->getOperand(0) == Root)
3471 break; // Don't add the root if we already indirectly depend on it.
3475 UnorderedChains.push_back(Root);
3477 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
3480 // Lower the terminator after the copies are emitted.
3481 SDL.visit(*LLVMBB->getTerminator());
3483 // Copy over any CaseBlock records that may now exist due to SwitchInst
3484 // lowering, as well as any jump table information.
3485 SwitchCases.clear();
3486 SwitchCases = SDL.SwitchCases;
3489 // Make sure the root of the DAG is up-to-date.
3490 DAG.setRoot(SDL.getRoot());
3493 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
3494 // Run the DAG combiner in pre-legalize mode.
3497 DEBUG(std::cerr << "Lowered selection DAG:\n");
3500 // Second step, hack on the DAG until it only uses operations and types that
3501 // the target supports.
3504 DEBUG(std::cerr << "Legalized selection DAG:\n");
3507 // Run the DAG combiner in post-legalize mode.
3510 if (ViewISelDAGs) DAG.viewGraph();
3512 // Third, instruction select all of the operations to machine code, adding the
3513 // code to the MachineBasicBlock.
3514 InstructionSelectBasicBlock(DAG);
3516 DEBUG(std::cerr << "Selected machine code:\n");
3520 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
3521 FunctionLoweringInfo &FuncInfo) {
3522 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
3524 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3527 // First step, lower LLVM code to some DAG. This DAG may use operations and
3528 // types that are not supported by the target.
3529 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
3531 // Second step, emit the lowered DAG as machine code.
3532 CodeGenAndEmitDAG(DAG);
3535 // Next, now that we know what the last MBB the LLVM BB expanded is, update
3536 // PHI nodes in successors.
3537 if (SwitchCases.empty() && JT.Reg == 0) {
3538 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3539 MachineInstr *PHI = PHINodesToUpdate[i].first;
3540 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3541 "This is not a machine PHI node that we are updating!");
3542 PHI->addRegOperand(PHINodesToUpdate[i].second);
3543 PHI->addMachineBasicBlockOperand(BB);
3548 // If the JumpTable record is filled in, then we need to emit a jump table.
3549 // Updating the PHI nodes is tricky in this case, since we need to determine
3550 // whether the PHI is a successor of the range check MBB or the jump table MBB
3552 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
3553 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3555 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3556 MachineBasicBlock *RangeBB = BB;
3557 // Set the current basic block to the mbb we wish to insert the code into
3559 SDL.setCurrentBasicBlock(BB);
3561 SDL.visitJumpTable(JT);
3562 SDAG.setRoot(SDL.getRoot());
3563 CodeGenAndEmitDAG(SDAG);
3565 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3566 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3567 MachineBasicBlock *PHIBB = PHI->getParent();
3568 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3569 "This is not a machine PHI node that we are updating!");
3570 if (PHIBB == JT.Default) {
3571 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3572 PHI->addMachineBasicBlockOperand(RangeBB);
3574 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
3575 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3576 PHI->addMachineBasicBlockOperand(BB);
3582 // If we generated any switch lowering information, build and codegen any
3583 // additional DAGs necessary.
3584 for(unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
3585 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3587 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3588 // Set the current basic block to the mbb we wish to insert the code into
3589 BB = SwitchCases[i].ThisBB;
3590 SDL.setCurrentBasicBlock(BB);
3592 SDL.visitSwitchCase(SwitchCases[i]);
3593 SDAG.setRoot(SDL.getRoot());
3594 CodeGenAndEmitDAG(SDAG);
3595 // Iterate over the phi nodes, if there is a phi node in a successor of this
3596 // block (for instance, the default block), then add a pair of operands to
3597 // the phi node for this block, as if we were coming from the original
3598 // BB before switch expansion.
3599 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3600 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3601 MachineBasicBlock *PHIBB = PHI->getParent();
3602 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3603 "This is not a machine PHI node that we are updating!");
3604 if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
3605 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3606 PHI->addMachineBasicBlockOperand(BB);
3612 //===----------------------------------------------------------------------===//
3613 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
3614 /// target node in the graph.
3615 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
3616 if (ViewSchedDAGs) DAG.viewGraph();
3617 ScheduleDAG *SL = NULL;
3619 switch (ISHeuristic) {
3620 default: assert(0 && "Unrecognized scheduling heuristic");
3621 case defaultScheduling:
3622 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
3623 SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
3625 assert(TLI.getSchedulingPreference() ==
3626 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
3627 SL = createBURRListDAGScheduler(DAG, BB);
3631 SL = createBFS_DAGScheduler(DAG, BB);
3633 case simpleScheduling:
3634 SL = createSimpleDAGScheduler(false, DAG, BB);
3636 case simpleNoItinScheduling:
3637 SL = createSimpleDAGScheduler(true, DAG, BB);
3639 case listSchedulingBURR:
3640 SL = createBURRListDAGScheduler(DAG, BB);
3642 case listSchedulingTDRR:
3643 SL = createTDRRListDAGScheduler(DAG, BB);
3645 case listSchedulingTD:
3646 SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
3653 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
3654 return new HazardRecognizer();
3657 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
3658 /// by tblgen. Others should not call it.
3659 void SelectionDAGISel::
3660 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
3661 std::vector<SDOperand> InOps;
3662 std::swap(InOps, Ops);
3664 Ops.push_back(InOps[0]); // input chain.
3665 Ops.push_back(InOps[1]); // input asm string.
3667 unsigned i = 2, e = InOps.size();
3668 if (InOps[e-1].getValueType() == MVT::Flag)
3669 --e; // Don't process a flag operand if it is here.
3672 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
3673 if ((Flags & 7) != 4 /*MEM*/) {
3674 // Just skip over this operand, copying the operands verbatim.
3675 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
3676 i += (Flags >> 3) + 1;
3678 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
3679 // Otherwise, this is a memory operand. Ask the target to select it.
3680 std::vector<SDOperand> SelOps;
3681 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
3682 std::cerr << "Could not match memory address. Inline asm failure!\n";
3686 // Add this to the output node.
3687 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
3688 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
3693 // Add the flag input back if present.
3694 if (e != InOps.size())
3695 Ops.push_back(InOps.back());