1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/Analysis/AliasAnalysis.h"
16 #include "llvm/CodeGen/SelectionDAGISel.h"
17 #include "llvm/CodeGen/ScheduleDAG.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/GlobalVariable.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineDebugInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/SSARegMap.h"
36 #include "llvm/Target/MRegisterInfo.h"
37 #include "llvm/Target/TargetData.h"
38 #include "llvm/Target/TargetFrameInfo.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/Compiler.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
63 //===---------------------------------------------------------------------===//
65 /// RegisterScheduler class - Track the registration of instruction schedulers.
67 //===---------------------------------------------------------------------===//
68 MachinePassRegistry RegisterScheduler::Registry;
70 //===---------------------------------------------------------------------===//
72 /// ISHeuristic command line option for instruction schedulers.
74 //===---------------------------------------------------------------------===//
76 cl::opt<RegisterScheduler::FunctionPassCtor, false,
77 RegisterPassParser<RegisterScheduler> >
79 cl::init(&createDefaultScheduler),
80 cl::desc("Instruction schedulers available:"));
82 static RegisterScheduler
83 defaultListDAGScheduler("default", " Best scheduler for the target",
84 createDefaultScheduler);
88 /// RegsForValue - This struct represents the physical registers that a
89 /// particular value is assigned and the type information about the value.
90 /// This is needed because values can be promoted into larger registers and
91 /// expanded into multiple smaller registers than the value.
92 struct VISIBILITY_HIDDEN RegsForValue {
93 /// Regs - This list hold the register (for legal and promoted values)
94 /// or register set (for expanded values) that the value should be assigned
96 std::vector<unsigned> Regs;
98 /// RegVT - The value type of each register.
100 MVT::ValueType RegVT;
102 /// ValueVT - The value type of the LLVM value, which may be promoted from
103 /// RegVT or made from merging the two expanded parts.
104 MVT::ValueType ValueVT;
106 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
108 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
109 : RegVT(regvt), ValueVT(valuevt) {
112 RegsForValue(const std::vector<unsigned> ®s,
113 MVT::ValueType regvt, MVT::ValueType valuevt)
114 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
117 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
118 /// this value and returns the result as a ValueVT value. This uses
119 /// Chain/Flag as the input and updates them for the output Chain/Flag.
120 SDOperand getCopyFromRegs(SelectionDAG &DAG,
121 SDOperand &Chain, SDOperand &Flag) const;
123 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
124 /// specified value into the registers specified by this object. This uses
125 /// Chain/Flag as the input and updates them for the output Chain/Flag.
126 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
127 SDOperand &Chain, SDOperand &Flag,
128 MVT::ValueType PtrVT) const;
130 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
131 /// operand list. This adds the code marker and includes the number of
132 /// values added into it.
133 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
134 std::vector<SDOperand> &Ops) const;
139 //===--------------------------------------------------------------------===//
140 /// createDefaultScheduler - This creates an instruction scheduler appropriate
142 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
144 MachineBasicBlock *BB) {
145 TargetLowering &TLI = IS->getTargetLowering();
147 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
148 return createTDListDAGScheduler(IS, DAG, BB);
150 assert(TLI.getSchedulingPreference() ==
151 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
152 return createBURRListDAGScheduler(IS, DAG, BB);
157 //===--------------------------------------------------------------------===//
158 /// FunctionLoweringInfo - This contains information that is global to a
159 /// function that is used when lowering a region of the function.
160 class FunctionLoweringInfo {
167 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
169 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
170 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
172 /// ValueMap - Since we emit code for the function a basic block at a time,
173 /// we must remember which virtual registers hold the values for
174 /// cross-basic-block values.
175 std::map<const Value*, unsigned> ValueMap;
177 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
178 /// the entry block. This allows the allocas to be efficiently referenced
179 /// anywhere in the function.
180 std::map<const AllocaInst*, int> StaticAllocaMap;
182 unsigned MakeReg(MVT::ValueType VT) {
183 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
186 /// isExportedInst - Return true if the specified value is an instruction
187 /// exported from its block.
188 bool isExportedInst(const Value *V) {
189 return ValueMap.count(V);
192 unsigned CreateRegForValue(const Value *V);
194 unsigned InitializeRegForValue(const Value *V) {
195 unsigned &R = ValueMap[V];
196 assert(R == 0 && "Already initialized this value register!");
197 return R = CreateRegForValue(V);
202 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
203 /// PHI nodes or outside of the basic block that defines it, or used by a
204 /// switch instruction, which may expand to multiple basic blocks.
205 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
206 if (isa<PHINode>(I)) return true;
207 BasicBlock *BB = I->getParent();
208 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
209 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
210 // FIXME: Remove switchinst special case.
211 isa<SwitchInst>(*UI))
216 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
217 /// entry block, return true. This includes arguments used by switches, since
218 /// the switch may expand into multiple basic blocks.
219 static bool isOnlyUsedInEntryBlock(Argument *A) {
220 BasicBlock *Entry = A->getParent()->begin();
221 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
222 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
223 return false; // Use not in entry block.
227 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
228 Function &fn, MachineFunction &mf)
229 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
231 // Create a vreg for each argument register that is not dead and is used
232 // outside of the entry block for the function.
233 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
235 if (!isOnlyUsedInEntryBlock(AI))
236 InitializeRegForValue(AI);
238 // Initialize the mapping of values to registers. This is only set up for
239 // instruction values that are used outside of the block that defines
241 Function::iterator BB = Fn.begin(), EB = Fn.end();
242 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
243 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
244 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
245 const Type *Ty = AI->getAllocatedType();
246 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
248 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
251 // If the alignment of the value is smaller than the size of the
252 // value, and if the size of the value is particularly small
253 // (<= 8 bytes), round up to the size of the value for potentially
254 // better performance.
256 // FIXME: This could be made better with a preferred alignment hook in
257 // TargetData. It serves primarily to 8-byte align doubles for X86.
258 if (Align < TySize && TySize <= 8) Align = TySize;
259 TySize *= CUI->getZExtValue(); // Get total allocated size.
260 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
261 StaticAllocaMap[AI] =
262 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
265 for (; BB != EB; ++BB)
266 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
267 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
268 if (!isa<AllocaInst>(I) ||
269 !StaticAllocaMap.count(cast<AllocaInst>(I)))
270 InitializeRegForValue(I);
272 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
273 // also creates the initial PHI MachineInstrs, though none of the input
274 // operands are populated.
275 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
276 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
278 MF.getBasicBlockList().push_back(MBB);
280 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
283 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
284 if (PN->use_empty()) continue;
286 MVT::ValueType VT = TLI.getValueType(PN->getType());
287 unsigned NumElements;
288 if (VT != MVT::Vector)
289 NumElements = TLI.getNumElements(VT);
291 MVT::ValueType VT1,VT2;
293 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
296 unsigned PHIReg = ValueMap[PN];
297 assert(PHIReg && "PHI node does not have an assigned virtual register!");
298 for (unsigned i = 0; i != NumElements; ++i)
299 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
304 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
305 /// the correctly promoted or expanded types. Assign these registers
306 /// consecutive vreg numbers and return the first assigned number.
307 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
308 MVT::ValueType VT = TLI.getValueType(V->getType());
310 // The number of multiples of registers that we need, to, e.g., split up
311 // a <2 x int64> -> 4 x i32 registers.
312 unsigned NumVectorRegs = 1;
314 // If this is a packed type, figure out what type it will decompose into
315 // and how many of the elements it will use.
316 if (VT == MVT::Vector) {
317 const PackedType *PTy = cast<PackedType>(V->getType());
318 unsigned NumElts = PTy->getNumElements();
319 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
321 // Divide the input until we get to a supported size. This will always
322 // end with a scalar if the target doesn't support vectors.
323 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
330 VT = getVectorType(EltTy, NumElts);
333 // The common case is that we will only create one register for this
334 // value. If we have that case, create and return the virtual register.
335 unsigned NV = TLI.getNumElements(VT);
337 // If we are promoting this value, pick the next largest supported type.
338 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
339 unsigned Reg = MakeReg(PromotedType);
340 // If this is a vector of supported or promoted types (e.g. 4 x i16),
341 // create all of the registers.
342 for (unsigned i = 1; i != NumVectorRegs; ++i)
343 MakeReg(PromotedType);
347 // If this value is represented with multiple target registers, make sure
348 // to create enough consecutive registers of the right (smaller) type.
349 unsigned NT = VT-1; // Find the type to use.
350 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
353 unsigned R = MakeReg((MVT::ValueType)NT);
354 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
355 MakeReg((MVT::ValueType)NT);
359 //===----------------------------------------------------------------------===//
360 /// SelectionDAGLowering - This is the common target-independent lowering
361 /// implementation that is parameterized by a TargetLowering object.
362 /// Also, targets can overload any lowering method.
365 class SelectionDAGLowering {
366 MachineBasicBlock *CurMBB;
368 std::map<const Value*, SDOperand> NodeMap;
370 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
371 /// them up and then emit token factor nodes when possible. This allows us to
372 /// get simple disambiguation between loads without worrying about alias
374 std::vector<SDOperand> PendingLoads;
376 /// Case - A pair of values to record the Value for a switch case, and the
377 /// case's target basic block.
378 typedef std::pair<Constant*, MachineBasicBlock*> Case;
379 typedef std::vector<Case>::iterator CaseItr;
380 typedef std::pair<CaseItr, CaseItr> CaseRange;
382 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
383 /// of conditional branches.
385 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
386 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
388 /// CaseBB - The MBB in which to emit the compare and branch
389 MachineBasicBlock *CaseBB;
390 /// LT, GE - If nonzero, we know the current case value must be less-than or
391 /// greater-than-or-equal-to these Constants.
394 /// Range - A pair of iterators representing the range of case values to be
395 /// processed at this point in the binary search tree.
399 /// The comparison function for sorting Case values.
401 bool operator () (const Case& C1, const Case& C2) {
402 if (const ConstantInt* I1 = dyn_cast<const ConstantInt>(C1.first))
403 if (I1->getType()->isUnsigned())
404 return I1->getZExtValue() <
405 cast<const ConstantInt>(C2.first)->getZExtValue();
407 return cast<const ConstantInt>(C1.first)->getSExtValue() <
408 cast<const ConstantInt>(C2.first)->getSExtValue();
413 // TLI - This is information that describes the available target features we
414 // need for lowering. This indicates when operations are unavailable,
415 // implemented with a libcall, etc.
418 const TargetData *TD;
420 /// SwitchCases - Vector of CaseBlock structures used to communicate
421 /// SwitchInst code generation information.
422 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
423 SelectionDAGISel::JumpTable JT;
425 /// FuncInfo - Information about the function as a whole.
427 FunctionLoweringInfo &FuncInfo;
429 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
430 FunctionLoweringInfo &funcinfo)
431 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
432 JT(0,0,0,0), FuncInfo(funcinfo) {
435 /// getRoot - Return the current virtual root of the Selection DAG.
437 SDOperand getRoot() {
438 if (PendingLoads.empty())
439 return DAG.getRoot();
441 if (PendingLoads.size() == 1) {
442 SDOperand Root = PendingLoads[0];
444 PendingLoads.clear();
448 // Otherwise, we have to make a token factor node.
449 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
450 &PendingLoads[0], PendingLoads.size());
451 PendingLoads.clear();
456 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
458 void visit(Instruction &I) { visit(I.getOpcode(), I); }
460 void visit(unsigned Opcode, User &I) {
462 default: assert(0 && "Unknown instruction type encountered!");
464 // Build the switch statement using the Instruction.def file.
465 #define HANDLE_INST(NUM, OPCODE, CLASS) \
466 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
467 #include "llvm/Instruction.def"
471 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
473 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
474 const Value *SV, SDOperand Root,
477 SDOperand getIntPtrConstant(uint64_t Val) {
478 return DAG.getConstant(Val, TLI.getPointerTy());
481 SDOperand getValue(const Value *V);
483 const SDOperand &setValue(const Value *V, SDOperand NewN) {
484 SDOperand &N = NodeMap[V];
485 assert(N.Val == 0 && "Already set a value for this node!");
489 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
491 bool OutReg, bool InReg,
492 std::set<unsigned> &OutputRegs,
493 std::set<unsigned> &InputRegs);
495 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
496 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
498 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
499 void ExportFromCurrentBlock(Value *V);
501 // Terminator instructions.
502 void visitRet(ReturnInst &I);
503 void visitBr(BranchInst &I);
504 void visitSwitch(SwitchInst &I);
505 void visitUnreachable(UnreachableInst &I) { /* noop */ }
507 // Helper for visitSwitch
508 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
509 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
511 // These all get lowered before this pass.
512 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
513 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
515 void visitIntBinary(User &I, unsigned IntOp, unsigned VecOp);
516 void visitFPBinary(User &I, unsigned FPOp, unsigned VecOp);
517 void visitShift(User &I, unsigned Opcode);
518 void visitAdd(User &I) {
519 if (I.getType()->isFloatingPoint())
520 visitFPBinary(I, ISD::FADD, ISD::VADD);
522 visitIntBinary(I, ISD::ADD, ISD::VADD);
524 void visitSub(User &I);
525 void visitMul(User &I) {
526 if (I.getType()->isFloatingPoint())
527 visitFPBinary(I, ISD::FMUL, ISD::VMUL);
529 visitIntBinary(I, ISD::MUL, ISD::VMUL);
531 void visitUDiv(User &I) { visitIntBinary(I, ISD::UDIV, ISD::VUDIV); }
532 void visitSDiv(User &I) { visitIntBinary(I, ISD::SDIV, ISD::VSDIV); }
533 void visitFDiv(User &I) { visitFPBinary(I, ISD::FDIV, ISD::VSDIV); }
534 void visitRem(User &I) {
535 const Type *Ty = I.getType();
536 if (Ty->isFloatingPoint())
537 visitFPBinary(I, ISD::FREM, 0);
539 visitIntBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, 0);
541 void visitAnd(User &I) { visitIntBinary(I, ISD::AND, ISD::VAND); }
542 void visitOr (User &I) { visitIntBinary(I, ISD::OR, ISD::VOR); }
543 void visitXor(User &I) { visitIntBinary(I, ISD::XOR, ISD::VXOR); }
544 void visitShl(User &I) { visitShift(I, ISD::SHL); }
545 void visitShr(User &I) {
546 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
549 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc,
550 ISD::CondCode FPOpc);
551 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ,
553 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE,
555 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE,
557 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE,
559 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT,
561 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT,
564 void visitExtractElement(User &I);
565 void visitInsertElement(User &I);
566 void visitShuffleVector(User &I);
568 void visitGetElementPtr(User &I);
569 void visitCast(User &I);
570 void visitSelect(User &I);
572 void visitMalloc(MallocInst &I);
573 void visitFree(FreeInst &I);
574 void visitAlloca(AllocaInst &I);
575 void visitLoad(LoadInst &I);
576 void visitStore(StoreInst &I);
577 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
578 void visitCall(CallInst &I);
579 void visitInlineAsm(CallInst &I);
580 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
581 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
583 void visitVAStart(CallInst &I);
584 void visitVAArg(VAArgInst &I);
585 void visitVAEnd(CallInst &I);
586 void visitVACopy(CallInst &I);
587 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
589 void visitMemIntrinsic(CallInst &I, unsigned Op);
591 void visitUserOp1(Instruction &I) {
592 assert(0 && "UserOp1 should not exist at instruction selection time!");
595 void visitUserOp2(Instruction &I) {
596 assert(0 && "UserOp2 should not exist at instruction selection time!");
600 } // end namespace llvm
602 SDOperand SelectionDAGLowering::getValue(const Value *V) {
603 SDOperand &N = NodeMap[V];
606 const Type *VTy = V->getType();
607 MVT::ValueType VT = TLI.getValueType(VTy);
608 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
609 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
610 visit(CE->getOpcode(), *CE);
611 assert(N.Val && "visit didn't populate the ValueMap!");
613 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
614 return N = DAG.getGlobalAddress(GV, VT);
615 } else if (isa<ConstantPointerNull>(C)) {
616 return N = DAG.getConstant(0, TLI.getPointerTy());
617 } else if (isa<UndefValue>(C)) {
618 if (!isa<PackedType>(VTy))
619 return N = DAG.getNode(ISD::UNDEF, VT);
621 // Create a VBUILD_VECTOR of undef nodes.
622 const PackedType *PTy = cast<PackedType>(VTy);
623 unsigned NumElements = PTy->getNumElements();
624 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
626 SmallVector<SDOperand, 8> Ops;
627 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
629 // Create a VConstant node with generic Vector type.
630 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
631 Ops.push_back(DAG.getValueType(PVT));
632 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
633 &Ops[0], Ops.size());
634 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
635 return N = DAG.getConstantFP(CFP->getValue(), VT);
636 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
637 unsigned NumElements = PTy->getNumElements();
638 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
640 // Now that we know the number and type of the elements, push a
641 // Constant or ConstantFP node onto the ops list for each element of
642 // the packed constant.
643 SmallVector<SDOperand, 8> Ops;
644 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
645 for (unsigned i = 0; i != NumElements; ++i)
646 Ops.push_back(getValue(CP->getOperand(i)));
648 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
650 if (MVT::isFloatingPoint(PVT))
651 Op = DAG.getConstantFP(0, PVT);
653 Op = DAG.getConstant(0, PVT);
654 Ops.assign(NumElements, Op);
657 // Create a VBUILD_VECTOR node with generic Vector type.
658 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
659 Ops.push_back(DAG.getValueType(PVT));
660 return N = DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector,&Ops[0],Ops.size());
662 // Canonicalize all constant ints to be unsigned.
663 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getZExtValue(),VT);
667 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
668 std::map<const AllocaInst*, int>::iterator SI =
669 FuncInfo.StaticAllocaMap.find(AI);
670 if (SI != FuncInfo.StaticAllocaMap.end())
671 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
674 std::map<const Value*, unsigned>::const_iterator VMI =
675 FuncInfo.ValueMap.find(V);
676 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
678 unsigned InReg = VMI->second;
680 // If this type is not legal, make it so now.
681 if (VT != MVT::Vector) {
682 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
684 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
686 // Source must be expanded. This input value is actually coming from the
687 // register pair VMI->second and VMI->second+1.
688 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
689 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
690 } else if (DestVT > VT) { // Promotion case
691 if (MVT::isFloatingPoint(VT))
692 N = DAG.getNode(ISD::FP_ROUND, VT, N);
694 N = DAG.getNode(ISD::TRUNCATE, VT, N);
697 // Otherwise, if this is a vector, make it available as a generic vector
699 MVT::ValueType PTyElementVT, PTyLegalElementVT;
700 const PackedType *PTy = cast<PackedType>(VTy);
701 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
704 // Build a VBUILD_VECTOR with the input registers.
705 SmallVector<SDOperand, 8> Ops;
706 if (PTyElementVT == PTyLegalElementVT) {
707 // If the value types are legal, just VBUILD the CopyFromReg nodes.
708 for (unsigned i = 0; i != NE; ++i)
709 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
711 } else if (PTyElementVT < PTyLegalElementVT) {
712 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
713 for (unsigned i = 0; i != NE; ++i) {
714 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
716 if (MVT::isFloatingPoint(PTyElementVT))
717 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
719 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
723 // If the register was expanded, use BUILD_PAIR.
724 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
725 for (unsigned i = 0; i != NE/2; ++i) {
726 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
728 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
730 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
734 Ops.push_back(DAG.getConstant(NE, MVT::i32));
735 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
736 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
738 // Finally, use a VBIT_CONVERT to make this available as the appropriate
740 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
741 DAG.getConstant(PTy->getNumElements(),
743 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
750 void SelectionDAGLowering::visitRet(ReturnInst &I) {
751 if (I.getNumOperands() == 0) {
752 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
755 SmallVector<SDOperand, 8> NewValues;
756 NewValues.push_back(getRoot());
757 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
758 SDOperand RetOp = getValue(I.getOperand(i));
759 bool isSigned = I.getOperand(i)->getType()->isSigned();
761 // If this is an integer return value, we need to promote it ourselves to
762 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
764 // FIXME: C calling convention requires the return type to be promoted to
765 // at least 32-bit. But this is not necessary for non-C calling conventions.
766 if (MVT::isInteger(RetOp.getValueType()) &&
767 RetOp.getValueType() < MVT::i64) {
768 MVT::ValueType TmpVT;
769 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
770 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
775 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
777 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
779 NewValues.push_back(RetOp);
780 NewValues.push_back(DAG.getConstant(isSigned, MVT::i32));
782 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
783 &NewValues[0], NewValues.size()));
786 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
787 /// the current basic block, add it to ValueMap now so that we'll get a
789 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
790 // No need to export constants.
791 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
794 if (FuncInfo.isExportedInst(V)) return;
796 unsigned Reg = FuncInfo.InitializeRegForValue(V);
797 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
800 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
801 const BasicBlock *FromBB) {
802 // The operands of the setcc have to be in this block. We don't know
803 // how to export them from some other block.
804 if (Instruction *VI = dyn_cast<Instruction>(V)) {
805 // Can export from current BB.
806 if (VI->getParent() == FromBB)
809 // Is already exported, noop.
810 return FuncInfo.isExportedInst(V);
813 // If this is an argument, we can export it if the BB is the entry block or
814 // if it is already exported.
815 if (isa<Argument>(V)) {
816 if (FromBB == &FromBB->getParent()->getEntryBlock())
819 // Otherwise, can only export this if it is already exported.
820 return FuncInfo.isExportedInst(V);
823 // Otherwise, constants can always be exported.
827 /// FindMergedConditions - If Cond is an expression like
828 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
829 MachineBasicBlock *TBB,
830 MachineBasicBlock *FBB,
831 MachineBasicBlock *CurBB,
833 // If this node is not part of the or/and tree, emit it as a branch.
834 BinaryOperator *BOp = dyn_cast<BinaryOperator>(Cond);
836 if (!BOp || (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
837 BOp->getParent() != CurBB->getBasicBlock()) {
838 const BasicBlock *BB = CurBB->getBasicBlock();
840 // If the leaf of the tree is a setcond inst, merge the condition into the
842 if (BOp && isa<SetCondInst>(BOp) &&
843 // The operands of the setcc have to be in this block. We don't know
844 // how to export them from some other block.
845 isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
846 isExportableFromCurrentBlock(BOp->getOperand(1), BB)) {
847 ExportFromCurrentBlock(BOp->getOperand(0));
848 ExportFromCurrentBlock(BOp->getOperand(1));
850 ISD::CondCode SignCond, UnsCond, FPCond, Condition;
851 switch (BOp->getOpcode()) {
852 default: assert(0 && "Unknown setcc opcode!");
853 case Instruction::SetEQ:
854 SignCond = ISD::SETEQ;
855 UnsCond = ISD::SETEQ;
856 FPCond = ISD::SETOEQ;
858 case Instruction::SetNE:
859 SignCond = ISD::SETNE;
860 UnsCond = ISD::SETNE;
861 FPCond = ISD::SETUNE;
863 case Instruction::SetLE:
864 SignCond = ISD::SETLE;
865 UnsCond = ISD::SETULE;
866 FPCond = ISD::SETOLE;
868 case Instruction::SetGE:
869 SignCond = ISD::SETGE;
870 UnsCond = ISD::SETUGE;
871 FPCond = ISD::SETOGE;
873 case Instruction::SetLT:
874 SignCond = ISD::SETLT;
875 UnsCond = ISD::SETULT;
876 FPCond = ISD::SETOLT;
878 case Instruction::SetGT:
879 SignCond = ISD::SETGT;
880 UnsCond = ISD::SETUGT;
881 FPCond = ISD::SETOGT;
885 const Type *OpType = BOp->getOperand(0)->getType();
886 if (const PackedType *PTy = dyn_cast<PackedType>(OpType))
887 OpType = PTy->getElementType();
889 if (!FiniteOnlyFPMath() && OpType->isFloatingPoint())
891 else if (OpType->isUnsigned())
894 Condition = SignCond;
896 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
897 BOp->getOperand(1), TBB, FBB, CurBB);
898 SwitchCases.push_back(CB);
902 // Create a CaseBlock record representing this branch.
903 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantBool::getTrue(),
905 SwitchCases.push_back(CB);
906 ExportFromCurrentBlock(Cond);
911 // Create TmpBB after CurBB.
912 MachineFunction::iterator BBI = CurBB;
913 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
914 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
916 if (Opc == Instruction::Or) {
925 // Emit the LHS condition.
926 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
928 // Emit the RHS condition into TmpBB.
929 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
931 assert(Opc == Instruction::And && "Unknown merge op!");
939 // This requires creation of TmpBB after CurBB.
941 // Emit the LHS condition.
942 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
944 // Emit the RHS condition into TmpBB.
945 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
949 void SelectionDAGLowering::visitBr(BranchInst &I) {
950 // Update machine-CFG edges.
951 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
953 // Figure out which block is immediately after the current one.
954 MachineBasicBlock *NextBlock = 0;
955 MachineFunction::iterator BBI = CurMBB;
956 if (++BBI != CurMBB->getParent()->end())
959 if (I.isUnconditional()) {
960 // If this is not a fall-through branch, emit the branch.
961 if (Succ0MBB != NextBlock)
962 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
963 DAG.getBasicBlock(Succ0MBB)));
965 // Update machine-CFG edges.
966 CurMBB->addSuccessor(Succ0MBB);
971 // If this condition is one of the special cases we handle, do special stuff
973 Value *CondVal = I.getCondition();
974 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
976 // If this is a series of conditions that are or'd or and'd together, emit
977 // this as a sequence of branches instead of setcc's with and/or operations.
978 // For example, instead of something like:
991 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
992 if (BOp->hasOneUse() &&
993 (BOp->getOpcode() == Instruction::And ||
994 BOp->getOpcode() == Instruction::Or)) {
995 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
996 visitSwitchCase(SwitchCases[0]);
997 SwitchCases.erase(SwitchCases.begin());
1002 // Create a CaseBlock record representing this branch.
1003 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantBool::getTrue(),
1004 Succ0MBB, Succ1MBB, CurMBB);
1005 // Use visitSwitchCase to actually insert the fast branch sequence for this
1007 visitSwitchCase(CB);
1010 /// visitSwitchCase - Emits the necessary code to represent a single node in
1011 /// the binary search tree resulting from lowering a switch instruction.
1012 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1014 SDOperand CondLHS = getValue(CB.CmpLHS);
1016 // Build the setcc now, fold "(X == true)" to X and "(X == false)" to !X to
1017 // handle common cases produced by branch lowering.
1018 if (CB.CmpRHS == ConstantBool::getTrue() && CB.CC == ISD::SETEQ)
1020 else if (CB.CmpRHS == ConstantBool::getFalse() && CB.CC == ISD::SETEQ) {
1021 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1022 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1024 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1026 // Set NextBlock to be the MBB immediately after the current one, if any.
1027 // This is used to avoid emitting unnecessary branches to the next block.
1028 MachineBasicBlock *NextBlock = 0;
1029 MachineFunction::iterator BBI = CurMBB;
1030 if (++BBI != CurMBB->getParent()->end())
1033 // If the lhs block is the next block, invert the condition so that we can
1034 // fall through to the lhs instead of the rhs block.
1035 if (CB.TrueBB == NextBlock) {
1036 std::swap(CB.TrueBB, CB.FalseBB);
1037 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1038 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1040 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1041 DAG.getBasicBlock(CB.TrueBB));
1042 if (CB.FalseBB == NextBlock)
1043 DAG.setRoot(BrCond);
1045 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1046 DAG.getBasicBlock(CB.FalseBB)));
1047 // Update successor info
1048 CurMBB->addSuccessor(CB.TrueBB);
1049 CurMBB->addSuccessor(CB.FalseBB);
1052 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1053 // Emit the code for the jump table
1054 MVT::ValueType PTy = TLI.getPointerTy();
1055 assert((PTy == MVT::i32 || PTy == MVT::i64) &&
1056 "Jump table entries are 32-bit values");
1057 bool isPIC = TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_;
1058 // PIC jump table entries are 32-bit values.
1059 unsigned EntrySize = isPIC ? 4 : MVT::getSizeInBits(PTy)/8;
1060 SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1061 SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy,
1062 DAG.getConstant(EntrySize, PTy));
1063 SDOperand TAB = DAG.getJumpTable(JT.JTI,PTy);
1064 SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, TAB);
1065 SDOperand LD = DAG.getLoad(isPIC ? MVT::i32 : PTy, Copy.getValue(1), ADD,
1068 // For Pic, the sequence is:
1069 // BRIND(load(Jumptable + index) + RelocBase)
1070 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1072 if (TLI.usesGlobalOffsetTable())
1073 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1076 ADD = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1077 ADD = DAG.getNode(ISD::ADD, PTy, ADD, Reloc);
1078 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), ADD));
1080 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD));
1084 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
1085 // Figure out which block is immediately after the current one.
1086 MachineBasicBlock *NextBlock = 0;
1087 MachineFunction::iterator BBI = CurMBB;
1089 if (++BBI != CurMBB->getParent()->end())
1092 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
1094 // If there is only the default destination, branch to it if it is not the
1095 // next basic block. Otherwise, just fall through.
1096 if (I.getNumOperands() == 2) {
1097 // Update machine-CFG edges.
1099 // If this is not a fall-through branch, emit the branch.
1100 if (Default != NextBlock)
1101 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1102 DAG.getBasicBlock(Default)));
1104 CurMBB->addSuccessor(Default);
1108 // If there are any non-default case statements, create a vector of Cases
1109 // representing each one, and sort the vector so that we can efficiently
1110 // create a binary search tree from them.
1111 std::vector<Case> Cases;
1113 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
1114 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
1115 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
1118 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1120 // Get the Value to be switched on and default basic blocks, which will be
1121 // inserted into CaseBlock records, representing basic blocks in the binary
1123 Value *SV = I.getOperand(0);
1125 // Get the MachineFunction which holds the current MBB. This is used during
1126 // emission of jump tables, and when inserting any additional MBBs necessary
1127 // to represent the switch.
1128 MachineFunction *CurMF = CurMBB->getParent();
1129 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
1131 // If the switch has few cases (two or less) emit a series of specific
1133 if (Cases.size() < 3) {
1134 // TODO: If any two of the cases has the same destination, and if one value
1135 // is the same as the other, but has one bit unset that the other has set,
1136 // use bit manipulation to do two compares at once. For example:
1137 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1139 // Rearrange the case blocks so that the last one falls through if possible.
1140 if (NextBlock && Default != NextBlock && Cases.back().second != NextBlock) {
1141 // The last case block won't fall through into 'NextBlock' if we emit the
1142 // branches in this order. See if rearranging a case value would help.
1143 for (unsigned i = 0, e = Cases.size()-1; i != e; ++i) {
1144 if (Cases[i].second == NextBlock) {
1145 std::swap(Cases[i], Cases.back());
1151 // Create a CaseBlock record representing a conditional branch to
1152 // the Case's target mbb if the value being switched on SV is equal
1154 MachineBasicBlock *CurBlock = CurMBB;
1155 for (unsigned i = 0, e = Cases.size(); i != e; ++i) {
1156 MachineBasicBlock *FallThrough;
1158 FallThrough = new MachineBasicBlock(CurMBB->getBasicBlock());
1159 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1161 // If the last case doesn't match, go to the default block.
1162 FallThrough = Default;
1165 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, Cases[i].first,
1166 Cases[i].second, FallThrough, CurBlock);
1168 // If emitting the first comparison, just call visitSwitchCase to emit the
1169 // code into the current block. Otherwise, push the CaseBlock onto the
1170 // vector to be later processed by SDISel, and insert the node's MBB
1171 // before the next MBB.
1172 if (CurBlock == CurMBB)
1173 visitSwitchCase(CB);
1175 SwitchCases.push_back(CB);
1177 CurBlock = FallThrough;
1182 // If the switch has more than 5 blocks, and at least 31.25% dense, and the
1183 // target supports indirect branches, then emit a jump table rather than
1184 // lowering the switch to a binary tree of conditional branches.
1185 if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) &&
1187 uint64_t First =cast<ConstantIntegral>(Cases.front().first)->getZExtValue();
1188 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getZExtValue();
1189 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
1191 if (Density >= 0.3125) {
1192 // Create a new basic block to hold the code for loading the address
1193 // of the jump table, and jumping to it. Update successor information;
1194 // we will either branch to the default case for the switch, or the jump
1196 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1197 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1198 CurMBB->addSuccessor(Default);
1199 CurMBB->addSuccessor(JumpTableBB);
1201 // Subtract the lowest switch case value from the value being switched on
1202 // and conditional branch to default mbb if the result is greater than the
1203 // difference between smallest and largest cases.
1204 SDOperand SwitchOp = getValue(SV);
1205 MVT::ValueType VT = SwitchOp.getValueType();
1206 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1207 DAG.getConstant(First, VT));
1209 // The SDNode we just created, which holds the value being switched on
1210 // minus the the smallest case value, needs to be copied to a virtual
1211 // register so it can be used as an index into the jump table in a
1212 // subsequent basic block. This value may be smaller or larger than the
1213 // target's pointer type, and therefore require extension or truncating.
1214 if (VT > TLI.getPointerTy())
1215 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1217 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1219 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1220 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1222 // Emit the range check for the jump table, and branch to the default
1223 // block for the switch statement if the value being switched on exceeds
1224 // the largest case in the switch.
1225 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1226 DAG.getConstant(Last-First,VT), ISD::SETUGT);
1227 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1228 DAG.getBasicBlock(Default)));
1230 // Build a vector of destination BBs, corresponding to each target
1231 // of the jump table. If the value of the jump table slot corresponds to
1232 // a case statement, push the case's BB onto the vector, otherwise, push
1234 std::vector<MachineBasicBlock*> DestBBs;
1235 uint64_t TEI = First;
1236 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI)
1237 if (cast<ConstantIntegral>(ii->first)->getZExtValue() == TEI) {
1238 DestBBs.push_back(ii->second);
1241 DestBBs.push_back(Default);
1244 // Update successor info. Add one edge to each unique successor.
1245 // Vector bool would be better, but vector<bool> is really slow.
1246 std::vector<unsigned char> SuccsHandled;
1247 SuccsHandled.resize(CurMBB->getParent()->getNumBlockIDs());
1249 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1250 E = DestBBs.end(); I != E; ++I) {
1251 if (!SuccsHandled[(*I)->getNumber()]) {
1252 SuccsHandled[(*I)->getNumber()] = true;
1253 JumpTableBB->addSuccessor(*I);
1257 // Create a jump table index for this jump table, or return an existing
1259 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1261 // Set the jump table information so that we can codegen it as a second
1262 // MachineBasicBlock
1263 JT.Reg = JumpTableReg;
1265 JT.MBB = JumpTableBB;
1266 JT.Default = Default;
1271 // Push the initial CaseRec onto the worklist
1272 std::vector<CaseRec> CaseVec;
1273 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1275 while (!CaseVec.empty()) {
1276 // Grab a record representing a case range to process off the worklist
1277 CaseRec CR = CaseVec.back();
1280 // Size is the number of Cases represented by this range. If Size is 1,
1281 // then we are processing a leaf of the binary search tree. Otherwise,
1282 // we need to pick a pivot, and push left and right ranges onto the
1284 unsigned Size = CR.Range.second - CR.Range.first;
1287 // Create a CaseBlock record representing a conditional branch to
1288 // the Case's target mbb if the value being switched on SV is equal
1289 // to C. Otherwise, branch to default.
1290 Constant *C = CR.Range.first->first;
1291 MachineBasicBlock *Target = CR.Range.first->second;
1292 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1295 // If the MBB representing the leaf node is the current MBB, then just
1296 // call visitSwitchCase to emit the code into the current block.
1297 // Otherwise, push the CaseBlock onto the vector to be later processed
1298 // by SDISel, and insert the node's MBB before the next MBB.
1299 if (CR.CaseBB == CurMBB)
1300 visitSwitchCase(CB);
1302 SwitchCases.push_back(CB);
1304 // split case range at pivot
1305 CaseItr Pivot = CR.Range.first + (Size / 2);
1306 CaseRange LHSR(CR.Range.first, Pivot);
1307 CaseRange RHSR(Pivot, CR.Range.second);
1308 Constant *C = Pivot->first;
1309 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1311 // We know that we branch to the LHS if the Value being switched on is
1312 // less than the Pivot value, C. We use this to optimize our binary
1313 // tree a bit, by recognizing that if SV is greater than or equal to the
1314 // LHS's Case Value, and that Case Value is exactly one less than the
1315 // Pivot's Value, then we can branch directly to the LHS's Target,
1316 // rather than creating a leaf node for it.
1317 if ((LHSR.second - LHSR.first) == 1 &&
1318 LHSR.first->first == CR.GE &&
1319 cast<ConstantIntegral>(C)->getZExtValue() ==
1320 (cast<ConstantIntegral>(CR.GE)->getZExtValue() + 1ULL)) {
1321 TrueBB = LHSR.first->second;
1323 TrueBB = new MachineBasicBlock(LLVMBB);
1324 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1325 CaseVec.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1328 // Similar to the optimization above, if the Value being switched on is
1329 // known to be less than the Constant CR.LT, and the current Case Value
1330 // is CR.LT - 1, then we can branch directly to the target block for
1331 // the current Case Value, rather than emitting a RHS leaf node for it.
1332 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1333 cast<ConstantIntegral>(RHSR.first->first)->getZExtValue() ==
1334 (cast<ConstantIntegral>(CR.LT)->getZExtValue() - 1ULL)) {
1335 FalseBB = RHSR.first->second;
1337 FalseBB = new MachineBasicBlock(LLVMBB);
1338 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1339 CaseVec.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1342 // Create a CaseBlock record representing a conditional branch to
1343 // the LHS node if the value being switched on SV is less than C.
1344 // Otherwise, branch to LHS.
1345 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
1346 SelectionDAGISel::CaseBlock CB(CC, SV, C, TrueBB, FalseBB, CR.CaseBB);
1348 if (CR.CaseBB == CurMBB)
1349 visitSwitchCase(CB);
1351 SwitchCases.push_back(CB);
1356 void SelectionDAGLowering::visitSub(User &I) {
1357 // -0.0 - X --> fneg
1358 if (I.getType()->isFloatingPoint()) {
1359 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1360 if (CFP->isExactlyValue(-0.0)) {
1361 SDOperand Op2 = getValue(I.getOperand(1));
1362 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1365 visitFPBinary(I, ISD::FSUB, ISD::VSUB);
1367 visitIntBinary(I, ISD::SUB, ISD::VSUB);
1371 SelectionDAGLowering::visitIntBinary(User &I, unsigned IntOp, unsigned VecOp) {
1372 const Type *Ty = I.getType();
1373 SDOperand Op1 = getValue(I.getOperand(0));
1374 SDOperand Op2 = getValue(I.getOperand(1));
1376 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1377 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1378 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1379 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1381 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
1386 SelectionDAGLowering::visitFPBinary(User &I, unsigned FPOp, unsigned VecOp) {
1387 const Type *Ty = I.getType();
1388 SDOperand Op1 = getValue(I.getOperand(0));
1389 SDOperand Op2 = getValue(I.getOperand(1));
1391 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1392 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1393 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1394 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1396 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
1400 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1401 SDOperand Op1 = getValue(I.getOperand(0));
1402 SDOperand Op2 = getValue(I.getOperand(1));
1404 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1406 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1409 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
1410 ISD::CondCode UnsignedOpcode,
1411 ISD::CondCode FPOpcode) {
1412 SDOperand Op1 = getValue(I.getOperand(0));
1413 SDOperand Op2 = getValue(I.getOperand(1));
1414 ISD::CondCode Opcode = SignedOpcode;
1415 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint())
1417 else if (I.getOperand(0)->getType()->isUnsigned())
1418 Opcode = UnsignedOpcode;
1419 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1422 void SelectionDAGLowering::visitSelect(User &I) {
1423 SDOperand Cond = getValue(I.getOperand(0));
1424 SDOperand TrueVal = getValue(I.getOperand(1));
1425 SDOperand FalseVal = getValue(I.getOperand(2));
1426 if (!isa<PackedType>(I.getType())) {
1427 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1428 TrueVal, FalseVal));
1430 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1431 *(TrueVal.Val->op_end()-2),
1432 *(TrueVal.Val->op_end()-1)));
1436 void SelectionDAGLowering::visitCast(User &I) {
1437 SDOperand N = getValue(I.getOperand(0));
1438 MVT::ValueType SrcVT = N.getValueType();
1439 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1441 if (DestVT == MVT::Vector) {
1442 // This is a cast to a vector from something else. This is always a bit
1443 // convert. Get information about the input vector.
1444 const PackedType *DestTy = cast<PackedType>(I.getType());
1445 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1446 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1447 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1448 DAG.getValueType(EltVT)));
1449 } else if (SrcVT == DestVT) {
1450 setValue(&I, N); // noop cast.
1451 } else if (DestVT == MVT::i1) {
1452 // Cast to bool is a comparison against zero, not truncation to zero.
1453 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
1454 DAG.getConstantFP(0.0, N.getValueType());
1455 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
1456 } else if (isInteger(SrcVT)) {
1457 if (isInteger(DestVT)) { // Int -> Int cast
1458 if (DestVT < SrcVT) // Truncating cast?
1459 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1460 else if (I.getOperand(0)->getType()->isSigned())
1461 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1463 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1464 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast
1465 if (I.getOperand(0)->getType()->isSigned())
1466 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1468 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1470 assert(0 && "Unknown cast!");
1472 } else if (isFloatingPoint(SrcVT)) {
1473 if (isFloatingPoint(DestVT)) { // FP -> FP cast
1474 if (DestVT < SrcVT) // Rounding cast?
1475 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1477 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1478 } else if (isInteger(DestVT)) { // FP -> Int cast.
1479 if (I.getType()->isSigned())
1480 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1482 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1484 assert(0 && "Unknown cast!");
1487 assert(SrcVT == MVT::Vector && "Unknown cast!");
1488 assert(DestVT != MVT::Vector && "Casts to vector already handled!");
1489 // This is a cast from a vector to something else. This is always a bit
1490 // convert. Get information about the input vector.
1491 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1495 void SelectionDAGLowering::visitInsertElement(User &I) {
1496 SDOperand InVec = getValue(I.getOperand(0));
1497 SDOperand InVal = getValue(I.getOperand(1));
1498 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1499 getValue(I.getOperand(2)));
1501 SDOperand Num = *(InVec.Val->op_end()-2);
1502 SDOperand Typ = *(InVec.Val->op_end()-1);
1503 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1504 InVec, InVal, InIdx, Num, Typ));
1507 void SelectionDAGLowering::visitExtractElement(User &I) {
1508 SDOperand InVec = getValue(I.getOperand(0));
1509 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1510 getValue(I.getOperand(1)));
1511 SDOperand Typ = *(InVec.Val->op_end()-1);
1512 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1513 TLI.getValueType(I.getType()), InVec, InIdx));
1516 void SelectionDAGLowering::visitShuffleVector(User &I) {
1517 SDOperand V1 = getValue(I.getOperand(0));
1518 SDOperand V2 = getValue(I.getOperand(1));
1519 SDOperand Mask = getValue(I.getOperand(2));
1521 SDOperand Num = *(V1.Val->op_end()-2);
1522 SDOperand Typ = *(V2.Val->op_end()-1);
1523 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1524 V1, V2, Mask, Num, Typ));
1528 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1529 SDOperand N = getValue(I.getOperand(0));
1530 const Type *Ty = I.getOperand(0)->getType();
1532 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1535 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1536 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
1539 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
1540 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1541 getIntPtrConstant(Offset));
1543 Ty = StTy->getElementType(Field);
1545 Ty = cast<SequentialType>(Ty)->getElementType();
1547 // If this is a constant subscript, handle it quickly.
1548 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1549 if (CI->getZExtValue() == 0) continue;
1551 if (CI->getType()->isSigned())
1553 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
1556 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getZExtValue();
1557 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1561 // N = N + Idx * ElementSize;
1562 uint64_t ElementSize = TD->getTypeSize(Ty);
1563 SDOperand IdxN = getValue(Idx);
1565 // If the index is smaller or larger than intptr_t, truncate or extend
1567 if (IdxN.getValueType() < N.getValueType()) {
1568 if (Idx->getType()->isSigned())
1569 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1571 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
1572 } else if (IdxN.getValueType() > N.getValueType())
1573 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1575 // If this is a multiply by a power of two, turn it into a shl
1576 // immediately. This is a very common case.
1577 if (isPowerOf2_64(ElementSize)) {
1578 unsigned Amt = Log2_64(ElementSize);
1579 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1580 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1581 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1585 SDOperand Scale = getIntPtrConstant(ElementSize);
1586 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1587 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1593 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1594 // If this is a fixed sized alloca in the entry block of the function,
1595 // allocate it statically on the stack.
1596 if (FuncInfo.StaticAllocaMap.count(&I))
1597 return; // getValue will auto-populate this.
1599 const Type *Ty = I.getAllocatedType();
1600 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1601 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
1604 SDOperand AllocSize = getValue(I.getArraySize());
1605 MVT::ValueType IntPtr = TLI.getPointerTy();
1606 if (IntPtr < AllocSize.getValueType())
1607 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1608 else if (IntPtr > AllocSize.getValueType())
1609 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1611 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1612 getIntPtrConstant(TySize));
1614 // Handle alignment. If the requested alignment is less than or equal to the
1615 // stack alignment, ignore it and round the size of the allocation up to the
1616 // stack alignment size. If the size is greater than the stack alignment, we
1617 // note this in the DYNAMIC_STACKALLOC node.
1618 unsigned StackAlign =
1619 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1620 if (Align <= StackAlign) {
1622 // Add SA-1 to the size.
1623 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1624 getIntPtrConstant(StackAlign-1));
1625 // Mask out the low bits for alignment purposes.
1626 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1627 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1630 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
1631 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
1633 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
1634 DAG.setRoot(setValue(&I, DSA).getValue(1));
1636 // Inform the Frame Information that we have just allocated a variable-sized
1638 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1641 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1642 SDOperand Ptr = getValue(I.getOperand(0));
1648 // Do not serialize non-volatile loads against each other.
1649 Root = DAG.getRoot();
1652 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
1653 Root, I.isVolatile()));
1656 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1657 const Value *SV, SDOperand Root,
1660 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1661 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1662 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr,
1663 DAG.getSrcValue(SV));
1665 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, isVolatile);
1669 DAG.setRoot(L.getValue(1));
1671 PendingLoads.push_back(L.getValue(1));
1677 void SelectionDAGLowering::visitStore(StoreInst &I) {
1678 Value *SrcV = I.getOperand(0);
1679 SDOperand Src = getValue(SrcV);
1680 SDOperand Ptr = getValue(I.getOperand(1));
1681 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1),
1685 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1686 /// access memory and has no other side effects at all.
1687 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1688 #define GET_NO_MEMORY_INTRINSICS
1689 #include "llvm/Intrinsics.gen"
1690 #undef GET_NO_MEMORY_INTRINSICS
1694 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1695 // have any side-effects or if it only reads memory.
1696 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1697 #define GET_SIDE_EFFECT_INFO
1698 #include "llvm/Intrinsics.gen"
1699 #undef GET_SIDE_EFFECT_INFO
1703 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1705 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1706 unsigned Intrinsic) {
1707 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1708 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1710 // Build the operand list.
1711 SmallVector<SDOperand, 8> Ops;
1712 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1714 // We don't need to serialize loads against other loads.
1715 Ops.push_back(DAG.getRoot());
1717 Ops.push_back(getRoot());
1721 // Add the intrinsic ID as an integer operand.
1722 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1724 // Add all operands of the call to the operand list.
1725 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1726 SDOperand Op = getValue(I.getOperand(i));
1728 // If this is a vector type, force it to the right packed type.
1729 if (Op.getValueType() == MVT::Vector) {
1730 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1731 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1733 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1734 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1735 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1738 assert(TLI.isTypeLegal(Op.getValueType()) &&
1739 "Intrinsic uses a non-legal type?");
1743 std::vector<MVT::ValueType> VTs;
1744 if (I.getType() != Type::VoidTy) {
1745 MVT::ValueType VT = TLI.getValueType(I.getType());
1746 if (VT == MVT::Vector) {
1747 const PackedType *DestTy = cast<PackedType>(I.getType());
1748 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1750 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1751 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1754 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1758 VTs.push_back(MVT::Other);
1760 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
1765 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
1766 &Ops[0], Ops.size());
1767 else if (I.getType() != Type::VoidTy)
1768 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
1769 &Ops[0], Ops.size());
1771 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
1772 &Ops[0], Ops.size());
1775 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1777 PendingLoads.push_back(Chain);
1781 if (I.getType() != Type::VoidTy) {
1782 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1783 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1784 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1785 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1786 DAG.getValueType(EVT));
1788 setValue(&I, Result);
1792 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1793 /// we want to emit this as a call to a named external function, return the name
1794 /// otherwise lower it and return null.
1796 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1797 switch (Intrinsic) {
1799 // By default, turn this into a target intrinsic node.
1800 visitTargetIntrinsic(I, Intrinsic);
1802 case Intrinsic::vastart: visitVAStart(I); return 0;
1803 case Intrinsic::vaend: visitVAEnd(I); return 0;
1804 case Intrinsic::vacopy: visitVACopy(I); return 0;
1805 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1806 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1807 case Intrinsic::setjmp:
1808 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1810 case Intrinsic::longjmp:
1811 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1813 case Intrinsic::memcpy_i32:
1814 case Intrinsic::memcpy_i64:
1815 visitMemIntrinsic(I, ISD::MEMCPY);
1817 case Intrinsic::memset_i32:
1818 case Intrinsic::memset_i64:
1819 visitMemIntrinsic(I, ISD::MEMSET);
1821 case Intrinsic::memmove_i32:
1822 case Intrinsic::memmove_i64:
1823 visitMemIntrinsic(I, ISD::MEMMOVE);
1826 case Intrinsic::dbg_stoppoint: {
1827 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1828 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1829 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
1833 Ops[1] = getValue(SPI.getLineValue());
1834 Ops[2] = getValue(SPI.getColumnValue());
1836 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
1837 assert(DD && "Not a debug information descriptor");
1838 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1840 Ops[3] = DAG.getString(CompileUnit->getFileName());
1841 Ops[4] = DAG.getString(CompileUnit->getDirectory());
1843 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
1848 case Intrinsic::dbg_region_start: {
1849 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1850 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1851 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
1852 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
1853 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
1854 DAG.getConstant(LabelID, MVT::i32)));
1859 case Intrinsic::dbg_region_end: {
1860 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1861 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
1862 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
1863 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
1864 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
1865 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
1870 case Intrinsic::dbg_func_start: {
1871 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1872 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
1873 if (DebugInfo && FSI.getSubprogram() &&
1874 DebugInfo->Verify(FSI.getSubprogram())) {
1875 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
1876 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
1877 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
1882 case Intrinsic::dbg_declare: {
1883 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1884 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
1885 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
1886 SDOperand AddressOp = getValue(DI.getAddress());
1887 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
1888 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
1894 case Intrinsic::isunordered_f32:
1895 case Intrinsic::isunordered_f64:
1896 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
1897 getValue(I.getOperand(2)), ISD::SETUO));
1900 case Intrinsic::sqrt_f32:
1901 case Intrinsic::sqrt_f64:
1902 setValue(&I, DAG.getNode(ISD::FSQRT,
1903 getValue(I.getOperand(1)).getValueType(),
1904 getValue(I.getOperand(1))));
1906 case Intrinsic::powi_f32:
1907 case Intrinsic::powi_f64:
1908 setValue(&I, DAG.getNode(ISD::FPOWI,
1909 getValue(I.getOperand(1)).getValueType(),
1910 getValue(I.getOperand(1)),
1911 getValue(I.getOperand(2))));
1913 case Intrinsic::pcmarker: {
1914 SDOperand Tmp = getValue(I.getOperand(1));
1915 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
1918 case Intrinsic::readcyclecounter: {
1919 SDOperand Op = getRoot();
1920 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
1921 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
1924 DAG.setRoot(Tmp.getValue(1));
1927 case Intrinsic::bswap_i16:
1928 case Intrinsic::bswap_i32:
1929 case Intrinsic::bswap_i64:
1930 setValue(&I, DAG.getNode(ISD::BSWAP,
1931 getValue(I.getOperand(1)).getValueType(),
1932 getValue(I.getOperand(1))));
1934 case Intrinsic::cttz_i8:
1935 case Intrinsic::cttz_i16:
1936 case Intrinsic::cttz_i32:
1937 case Intrinsic::cttz_i64:
1938 setValue(&I, DAG.getNode(ISD::CTTZ,
1939 getValue(I.getOperand(1)).getValueType(),
1940 getValue(I.getOperand(1))));
1942 case Intrinsic::ctlz_i8:
1943 case Intrinsic::ctlz_i16:
1944 case Intrinsic::ctlz_i32:
1945 case Intrinsic::ctlz_i64:
1946 setValue(&I, DAG.getNode(ISD::CTLZ,
1947 getValue(I.getOperand(1)).getValueType(),
1948 getValue(I.getOperand(1))));
1950 case Intrinsic::ctpop_i8:
1951 case Intrinsic::ctpop_i16:
1952 case Intrinsic::ctpop_i32:
1953 case Intrinsic::ctpop_i64:
1954 setValue(&I, DAG.getNode(ISD::CTPOP,
1955 getValue(I.getOperand(1)).getValueType(),
1956 getValue(I.getOperand(1))));
1958 case Intrinsic::stacksave: {
1959 SDOperand Op = getRoot();
1960 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
1961 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
1963 DAG.setRoot(Tmp.getValue(1));
1966 case Intrinsic::stackrestore: {
1967 SDOperand Tmp = getValue(I.getOperand(1));
1968 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
1971 case Intrinsic::prefetch:
1972 // FIXME: Currently discarding prefetches.
1978 void SelectionDAGLowering::visitCall(CallInst &I) {
1979 const char *RenameFn = 0;
1980 if (Function *F = I.getCalledFunction()) {
1981 if (F->isExternal())
1982 if (unsigned IID = F->getIntrinsicID()) {
1983 RenameFn = visitIntrinsicCall(I, IID);
1986 } else { // Not an LLVM intrinsic.
1987 const std::string &Name = F->getName();
1988 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
1989 if (I.getNumOperands() == 3 && // Basic sanity checks.
1990 I.getOperand(1)->getType()->isFloatingPoint() &&
1991 I.getType() == I.getOperand(1)->getType() &&
1992 I.getType() == I.getOperand(2)->getType()) {
1993 SDOperand LHS = getValue(I.getOperand(1));
1994 SDOperand RHS = getValue(I.getOperand(2));
1995 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
1999 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
2000 if (I.getNumOperands() == 2 && // Basic sanity checks.
2001 I.getOperand(1)->getType()->isFloatingPoint() &&
2002 I.getType() == I.getOperand(1)->getType()) {
2003 SDOperand Tmp = getValue(I.getOperand(1));
2004 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
2007 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
2008 if (I.getNumOperands() == 2 && // Basic sanity checks.
2009 I.getOperand(1)->getType()->isFloatingPoint() &&
2010 I.getType() == I.getOperand(1)->getType()) {
2011 SDOperand Tmp = getValue(I.getOperand(1));
2012 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
2015 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
2016 if (I.getNumOperands() == 2 && // Basic sanity checks.
2017 I.getOperand(1)->getType()->isFloatingPoint() &&
2018 I.getType() == I.getOperand(1)->getType()) {
2019 SDOperand Tmp = getValue(I.getOperand(1));
2020 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
2025 } else if (isa<InlineAsm>(I.getOperand(0))) {
2032 Callee = getValue(I.getOperand(0));
2034 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
2035 std::vector<std::pair<SDOperand, const Type*> > Args;
2036 Args.reserve(I.getNumOperands());
2037 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2038 Value *Arg = I.getOperand(i);
2039 SDOperand ArgNode = getValue(Arg);
2040 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
2043 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
2044 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2046 std::pair<SDOperand,SDOperand> Result =
2047 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
2048 I.isTailCall(), Callee, Args, DAG);
2049 if (I.getType() != Type::VoidTy)
2050 setValue(&I, Result.first);
2051 DAG.setRoot(Result.second);
2054 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
2055 SDOperand &Chain, SDOperand &Flag)const{
2056 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
2057 Chain = Val.getValue(1);
2058 Flag = Val.getValue(2);
2060 // If the result was expanded, copy from the top part.
2061 if (Regs.size() > 1) {
2062 assert(Regs.size() == 2 &&
2063 "Cannot expand to more than 2 elts yet!");
2064 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
2065 Chain = Hi.getValue(1);
2066 Flag = Hi.getValue(2);
2067 if (DAG.getTargetLoweringInfo().isLittleEndian())
2068 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
2070 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
2073 // Otherwise, if the return value was promoted or extended, truncate it to the
2074 // appropriate type.
2075 if (RegVT == ValueVT)
2078 if (MVT::isInteger(RegVT)) {
2079 if (ValueVT < RegVT)
2080 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
2082 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
2084 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
2088 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
2089 /// specified value into the registers specified by this object. This uses
2090 /// Chain/Flag as the input and updates them for the output Chain/Flag.
2091 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
2092 SDOperand &Chain, SDOperand &Flag,
2093 MVT::ValueType PtrVT) const {
2094 if (Regs.size() == 1) {
2095 // If there is a single register and the types differ, this must be
2097 if (RegVT != ValueVT) {
2098 if (MVT::isInteger(RegVT)) {
2099 if (RegVT < ValueVT)
2100 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
2102 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
2104 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
2106 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
2107 Flag = Chain.getValue(1);
2109 std::vector<unsigned> R(Regs);
2110 if (!DAG.getTargetLoweringInfo().isLittleEndian())
2111 std::reverse(R.begin(), R.end());
2113 for (unsigned i = 0, e = R.size(); i != e; ++i) {
2114 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
2115 DAG.getConstant(i, PtrVT));
2116 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
2117 Flag = Chain.getValue(1);
2122 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
2123 /// operand list. This adds the code marker and includes the number of
2124 /// values added into it.
2125 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
2126 std::vector<SDOperand> &Ops) const {
2127 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
2128 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
2129 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
2132 /// isAllocatableRegister - If the specified register is safe to allocate,
2133 /// i.e. it isn't a stack pointer or some other special register, return the
2134 /// register class for the register. Otherwise, return null.
2135 static const TargetRegisterClass *
2136 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
2137 const TargetLowering &TLI, const MRegisterInfo *MRI) {
2138 MVT::ValueType FoundVT = MVT::Other;
2139 const TargetRegisterClass *FoundRC = 0;
2140 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
2141 E = MRI->regclass_end(); RCI != E; ++RCI) {
2142 MVT::ValueType ThisVT = MVT::Other;
2144 const TargetRegisterClass *RC = *RCI;
2145 // If none of the the value types for this register class are valid, we
2146 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2147 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2149 if (TLI.isTypeLegal(*I)) {
2150 // If we have already found this register in a different register class,
2151 // choose the one with the largest VT specified. For example, on
2152 // PowerPC, we favor f64 register classes over f32.
2153 if (FoundVT == MVT::Other ||
2154 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
2161 if (ThisVT == MVT::Other) continue;
2163 // NOTE: This isn't ideal. In particular, this might allocate the
2164 // frame pointer in functions that need it (due to them not being taken
2165 // out of allocation, because a variable sized allocation hasn't been seen
2166 // yet). This is a slight code pessimization, but should still work.
2167 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
2168 E = RC->allocation_order_end(MF); I != E; ++I)
2170 // We found a matching register class. Keep looking at others in case
2171 // we find one with larger registers that this physreg is also in.
2180 RegsForValue SelectionDAGLowering::
2181 GetRegistersForValue(const std::string &ConstrCode,
2182 MVT::ValueType VT, bool isOutReg, bool isInReg,
2183 std::set<unsigned> &OutputRegs,
2184 std::set<unsigned> &InputRegs) {
2185 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
2186 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
2187 std::vector<unsigned> Regs;
2189 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
2190 MVT::ValueType RegVT;
2191 MVT::ValueType ValueVT = VT;
2193 if (PhysReg.first) {
2194 if (VT == MVT::Other)
2195 ValueVT = *PhysReg.second->vt_begin();
2197 // Get the actual register value type. This is important, because the user
2198 // may have asked for (e.g.) the AX register in i32 type. We need to
2199 // remember that AX is actually i16 to get the right extension.
2200 RegVT = *PhysReg.second->vt_begin();
2202 // This is a explicit reference to a physical register.
2203 Regs.push_back(PhysReg.first);
2205 // If this is an expanded reference, add the rest of the regs to Regs.
2207 TargetRegisterClass::iterator I = PhysReg.second->begin();
2208 TargetRegisterClass::iterator E = PhysReg.second->end();
2209 for (; *I != PhysReg.first; ++I)
2210 assert(I != E && "Didn't find reg!");
2212 // Already added the first reg.
2214 for (; NumRegs; --NumRegs, ++I) {
2215 assert(I != E && "Ran out of registers to allocate!");
2219 return RegsForValue(Regs, RegVT, ValueVT);
2222 // This is a reference to a register class. Allocate NumRegs consecutive,
2223 // available, registers from the class.
2224 std::vector<unsigned> RegClassRegs =
2225 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
2227 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
2228 MachineFunction &MF = *CurMBB->getParent();
2229 unsigned NumAllocated = 0;
2230 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
2231 unsigned Reg = RegClassRegs[i];
2232 // See if this register is available.
2233 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
2234 (isInReg && InputRegs.count(Reg))) { // Already used.
2235 // Make sure we find consecutive registers.
2240 // Check to see if this register is allocatable (i.e. don't give out the
2242 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
2244 // Make sure we find consecutive registers.
2249 // Okay, this register is good, we can use it.
2252 // If we allocated enough consecutive
2253 if (NumAllocated == NumRegs) {
2254 unsigned RegStart = (i-NumAllocated)+1;
2255 unsigned RegEnd = i+1;
2256 // Mark all of the allocated registers used.
2257 for (unsigned i = RegStart; i != RegEnd; ++i) {
2258 unsigned Reg = RegClassRegs[i];
2259 Regs.push_back(Reg);
2260 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
2261 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
2264 return RegsForValue(Regs, *RC->vt_begin(), VT);
2268 // Otherwise, we couldn't allocate enough registers for this.
2269 return RegsForValue();
2273 /// visitInlineAsm - Handle a call to an InlineAsm object.
2275 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
2276 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
2278 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
2281 // Note, we treat inline asms both with and without side-effects as the same.
2282 // If an inline asm doesn't have side effects and doesn't access memory, we
2283 // could not choose to not chain it.
2284 bool hasSideEffects = IA->hasSideEffects();
2286 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
2287 std::vector<MVT::ValueType> ConstraintVTs;
2289 /// AsmNodeOperands - A list of pairs. The first element is a register, the
2290 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
2291 /// if it is a def of that register.
2292 std::vector<SDOperand> AsmNodeOperands;
2293 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
2294 AsmNodeOperands.push_back(AsmStr);
2296 SDOperand Chain = getRoot();
2299 // We fully assign registers here at isel time. This is not optimal, but
2300 // should work. For register classes that correspond to LLVM classes, we
2301 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
2302 // over the constraints, collecting fixed registers that we know we can't use.
2303 std::set<unsigned> OutputRegs, InputRegs;
2305 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2306 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2307 std::string &ConstraintCode = Constraints[i].Codes[0];
2309 MVT::ValueType OpVT;
2311 // Compute the value type for each operand and add it to ConstraintVTs.
2312 switch (Constraints[i].Type) {
2313 case InlineAsm::isOutput:
2314 if (!Constraints[i].isIndirectOutput) {
2315 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2316 OpVT = TLI.getValueType(I.getType());
2318 const Type *OpTy = I.getOperand(OpNum)->getType();
2319 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2320 OpNum++; // Consumes a call operand.
2323 case InlineAsm::isInput:
2324 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2325 OpNum++; // Consumes a call operand.
2327 case InlineAsm::isClobber:
2332 ConstraintVTs.push_back(OpVT);
2334 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2335 continue; // Not assigned a fixed reg.
2337 // Build a list of regs that this operand uses. This always has a single
2338 // element for promoted/expanded operands.
2339 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2341 OutputRegs, InputRegs);
2343 switch (Constraints[i].Type) {
2344 case InlineAsm::isOutput:
2345 // We can't assign any other output to this register.
2346 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2347 // If this is an early-clobber output, it cannot be assigned to the same
2348 // value as the input reg.
2349 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2350 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2352 case InlineAsm::isInput:
2353 // We can't assign any other input to this register.
2354 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2356 case InlineAsm::isClobber:
2357 // Clobbered regs cannot be used as inputs or outputs.
2358 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2359 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2364 // Loop over all of the inputs, copying the operand values into the
2365 // appropriate registers and processing the output regs.
2366 RegsForValue RetValRegs;
2367 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2370 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2371 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2372 std::string &ConstraintCode = Constraints[i].Codes[0];
2374 switch (Constraints[i].Type) {
2375 case InlineAsm::isOutput: {
2376 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2377 if (ConstraintCode.size() == 1) // not a physreg name.
2378 CTy = TLI.getConstraintType(ConstraintCode[0]);
2380 if (CTy == TargetLowering::C_Memory) {
2382 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2384 // Check that the operand (the address to store to) isn't a float.
2385 if (!MVT::isInteger(InOperandVal.getValueType()))
2386 assert(0 && "MATCH FAIL!");
2388 if (!Constraints[i].isIndirectOutput)
2389 assert(0 && "MATCH FAIL!");
2391 OpNum++; // Consumes a call operand.
2393 // Extend/truncate to the right pointer type if needed.
2394 MVT::ValueType PtrType = TLI.getPointerTy();
2395 if (InOperandVal.getValueType() < PtrType)
2396 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2397 else if (InOperandVal.getValueType() > PtrType)
2398 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2400 // Add information to the INLINEASM node to know about this output.
2401 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2402 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2403 AsmNodeOperands.push_back(InOperandVal);
2407 // Otherwise, this is a register output.
2408 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2410 // If this is an early-clobber output, or if there is an input
2411 // constraint that matches this, we need to reserve the input register
2412 // so no other inputs allocate to it.
2413 bool UsesInputRegister = false;
2414 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2415 UsesInputRegister = true;
2417 // Copy the output from the appropriate register. Find a register that
2420 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2421 true, UsesInputRegister,
2422 OutputRegs, InputRegs);
2423 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
2425 if (!Constraints[i].isIndirectOutput) {
2426 assert(RetValRegs.Regs.empty() &&
2427 "Cannot have multiple output constraints yet!");
2428 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2431 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2432 I.getOperand(OpNum)));
2433 OpNum++; // Consumes a call operand.
2436 // Add information to the INLINEASM node to know that this register is
2438 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2441 case InlineAsm::isInput: {
2442 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2443 OpNum++; // Consumes a call operand.
2445 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2446 // If this is required to match an output register we have already set,
2447 // just use its register.
2448 unsigned OperandNo = atoi(ConstraintCode.c_str());
2450 // Scan until we find the definition we already emitted of this operand.
2451 // When we find it, create a RegsForValue operand.
2452 unsigned CurOp = 2; // The first operand.
2453 for (; OperandNo; --OperandNo) {
2454 // Advance to the next operand.
2456 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2457 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
2458 (NumOps & 7) == 4 /*MEM*/) &&
2459 "Skipped past definitions?");
2460 CurOp += (NumOps>>3)+1;
2464 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2465 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2466 "Skipped past definitions?");
2468 // Add NumOps>>3 registers to MatchedRegs.
2469 RegsForValue MatchedRegs;
2470 MatchedRegs.ValueVT = InOperandVal.getValueType();
2471 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2472 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2473 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2474 MatchedRegs.Regs.push_back(Reg);
2477 // Use the produced MatchedRegs object to
2478 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag,
2479 TLI.getPointerTy());
2480 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2484 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2485 if (ConstraintCode.size() == 1) // not a physreg name.
2486 CTy = TLI.getConstraintType(ConstraintCode[0]);
2488 if (CTy == TargetLowering::C_Other) {
2489 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
2490 assert(0 && "MATCH FAIL!");
2492 // Add information to the INLINEASM node to know about this input.
2493 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2494 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2495 AsmNodeOperands.push_back(InOperandVal);
2497 } else if (CTy == TargetLowering::C_Memory) {
2500 // Check that the operand isn't a float.
2501 if (!MVT::isInteger(InOperandVal.getValueType()))
2502 assert(0 && "MATCH FAIL!");
2504 // Extend/truncate to the right pointer type if needed.
2505 MVT::ValueType PtrType = TLI.getPointerTy();
2506 if (InOperandVal.getValueType() < PtrType)
2507 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2508 else if (InOperandVal.getValueType() > PtrType)
2509 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2511 // Add information to the INLINEASM node to know about this input.
2512 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2513 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2514 AsmNodeOperands.push_back(InOperandVal);
2518 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2520 // Copy the input into the appropriate registers.
2521 RegsForValue InRegs =
2522 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2523 false, true, OutputRegs, InputRegs);
2524 // FIXME: should be match fail.
2525 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2527 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy());
2529 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2532 case InlineAsm::isClobber: {
2533 RegsForValue ClobberedRegs =
2534 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2535 OutputRegs, InputRegs);
2536 // Add the clobbered value to the operand list, so that the register
2537 // allocator is aware that the physreg got clobbered.
2538 if (!ClobberedRegs.Regs.empty())
2539 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2545 // Finish up input operands.
2546 AsmNodeOperands[0] = Chain;
2547 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2549 Chain = DAG.getNode(ISD::INLINEASM,
2550 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
2551 &AsmNodeOperands[0], AsmNodeOperands.size());
2552 Flag = Chain.getValue(1);
2554 // If this asm returns a register value, copy the result from that register
2555 // and set it as the value of the call.
2556 if (!RetValRegs.Regs.empty())
2557 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2559 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2561 // Process indirect outputs, first output all of the flagged copies out of
2563 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2564 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2565 Value *Ptr = IndirectStoresToEmit[i].second;
2566 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2567 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2570 // Emit the non-flagged stores from the physregs.
2571 SmallVector<SDOperand, 8> OutChains;
2572 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2573 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
2574 getValue(StoresToEmit[i].second),
2575 StoresToEmit[i].second, 0));
2576 if (!OutChains.empty())
2577 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2578 &OutChains[0], OutChains.size());
2583 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2584 SDOperand Src = getValue(I.getOperand(0));
2586 MVT::ValueType IntPtr = TLI.getPointerTy();
2588 if (IntPtr < Src.getValueType())
2589 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2590 else if (IntPtr > Src.getValueType())
2591 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2593 // Scale the source by the type size.
2594 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
2595 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2596 Src, getIntPtrConstant(ElementSize));
2598 std::vector<std::pair<SDOperand, const Type*> > Args;
2599 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType()));
2601 std::pair<SDOperand,SDOperand> Result =
2602 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
2603 DAG.getExternalSymbol("malloc", IntPtr),
2605 setValue(&I, Result.first); // Pointers always fit in registers
2606 DAG.setRoot(Result.second);
2609 void SelectionDAGLowering::visitFree(FreeInst &I) {
2610 std::vector<std::pair<SDOperand, const Type*> > Args;
2611 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
2612 TLI.getTargetData()->getIntPtrType()));
2613 MVT::ValueType IntPtr = TLI.getPointerTy();
2614 std::pair<SDOperand,SDOperand> Result =
2615 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
2616 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2617 DAG.setRoot(Result.second);
2620 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2621 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2622 // instructions are special in various ways, which require special support to
2623 // insert. The specified MachineInstr is created but not inserted into any
2624 // basic blocks, and the scheduler passes ownership of it to this method.
2625 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2626 MachineBasicBlock *MBB) {
2627 std::cerr << "If a target marks an instruction with "
2628 "'usesCustomDAGSchedInserter', it must implement "
2629 "TargetLowering::InsertAtEndOfBasicBlock!\n";
2634 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2635 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2636 getValue(I.getOperand(1)),
2637 DAG.getSrcValue(I.getOperand(1))));
2640 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2641 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2642 getValue(I.getOperand(0)),
2643 DAG.getSrcValue(I.getOperand(0)));
2645 DAG.setRoot(V.getValue(1));
2648 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2649 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2650 getValue(I.getOperand(1)),
2651 DAG.getSrcValue(I.getOperand(1))));
2654 void SelectionDAGLowering::visitVACopy(CallInst &I) {
2655 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2656 getValue(I.getOperand(1)),
2657 getValue(I.getOperand(2)),
2658 DAG.getSrcValue(I.getOperand(1)),
2659 DAG.getSrcValue(I.getOperand(2))));
2662 /// TargetLowering::LowerArguments - This is the default LowerArguments
2663 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
2664 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
2665 /// integrated into SDISel.
2666 std::vector<SDOperand>
2667 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2668 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2669 std::vector<SDOperand> Ops;
2670 Ops.push_back(DAG.getRoot());
2671 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2672 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2674 // Add one result value for each formal argument.
2675 std::vector<MVT::ValueType> RetVals;
2676 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2677 MVT::ValueType VT = getValueType(I->getType());
2679 switch (getTypeAction(VT)) {
2680 default: assert(0 && "Unknown type action!");
2682 RetVals.push_back(VT);
2685 RetVals.push_back(getTypeToTransformTo(VT));
2688 if (VT != MVT::Vector) {
2689 // If this is a large integer, it needs to be broken up into small
2690 // integers. Figure out what the destination type is and how many small
2691 // integers it turns into.
2692 MVT::ValueType NVT = getTypeToTransformTo(VT);
2693 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2694 for (unsigned i = 0; i != NumVals; ++i)
2695 RetVals.push_back(NVT);
2697 // Otherwise, this is a vector type. We only support legal vectors
2699 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2700 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2702 // Figure out if there is a Packed type corresponding to this Vector
2703 // type. If so, convert to the packed type.
2704 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2705 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2706 RetVals.push_back(TVT);
2708 assert(0 && "Don't support illegal by-val vector arguments yet!");
2715 RetVals.push_back(MVT::Other);
2718 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
2719 DAG.getNodeValueTypes(RetVals), RetVals.size(),
2720 &Ops[0], Ops.size()).Val;
2722 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
2724 // Set up the return result vector.
2727 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2728 MVT::ValueType VT = getValueType(I->getType());
2730 switch (getTypeAction(VT)) {
2731 default: assert(0 && "Unknown type action!");
2733 Ops.push_back(SDOperand(Result, i++));
2736 SDOperand Op(Result, i++);
2737 if (MVT::isInteger(VT)) {
2738 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
2740 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
2741 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2743 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2744 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2750 if (VT != MVT::Vector) {
2751 // If this is a large integer, it needs to be reassembled from small
2752 // integers. Figure out what the source elt type is and how many small
2754 MVT::ValueType NVT = getTypeToTransformTo(VT);
2755 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2757 SDOperand Lo = SDOperand(Result, i++);
2758 SDOperand Hi = SDOperand(Result, i++);
2760 if (!isLittleEndian())
2763 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
2765 // Value scalarized into many values. Unimp for now.
2766 assert(0 && "Cannot expand i64 -> i16 yet!");
2769 // Otherwise, this is a vector type. We only support legal vectors
2771 const PackedType *PTy = cast<PackedType>(I->getType());
2772 unsigned NumElems = PTy->getNumElements();
2773 const Type *EltTy = PTy->getElementType();
2775 // Figure out if there is a Packed type corresponding to this Vector
2776 // type. If so, convert to the packed type.
2777 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2778 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2779 SDOperand N = SDOperand(Result, i++);
2780 // Handle copies from generic vectors to registers.
2781 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
2782 DAG.getConstant(NumElems, MVT::i32),
2783 DAG.getValueType(getValueType(EltTy)));
2786 assert(0 && "Don't support illegal by-val vector arguments yet!");
2797 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
2798 /// implementation, which just inserts an ISD::CALL node, which is later custom
2799 /// lowered by the target to something concrete. FIXME: When all targets are
2800 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
2801 std::pair<SDOperand, SDOperand>
2802 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
2803 unsigned CallingConv, bool isTailCall,
2805 ArgListTy &Args, SelectionDAG &DAG) {
2806 SmallVector<SDOperand, 32> Ops;
2807 Ops.push_back(Chain); // Op#0 - Chain
2808 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
2809 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
2810 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
2811 Ops.push_back(Callee);
2813 // Handle all of the outgoing arguments.
2814 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
2815 MVT::ValueType VT = getValueType(Args[i].second);
2816 SDOperand Op = Args[i].first;
2817 bool isSigned = Args[i].second->isSigned();
2818 switch (getTypeAction(VT)) {
2819 default: assert(0 && "Unknown type action!");
2822 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2825 if (MVT::isInteger(VT)) {
2826 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2827 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
2829 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2830 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
2833 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2836 if (VT != MVT::Vector) {
2837 // If this is a large integer, it needs to be broken down into small
2838 // integers. Figure out what the source elt type is and how many small
2840 MVT::ValueType NVT = getTypeToTransformTo(VT);
2841 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2843 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2844 DAG.getConstant(0, getPointerTy()));
2845 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2846 DAG.getConstant(1, getPointerTy()));
2847 if (!isLittleEndian())
2851 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2853 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2855 // Value scalarized into many values. Unimp for now.
2856 assert(0 && "Cannot expand i64 -> i16 yet!");
2859 // Otherwise, this is a vector type. We only support legal vectors
2861 const PackedType *PTy = cast<PackedType>(Args[i].second);
2862 unsigned NumElems = PTy->getNumElements();
2863 const Type *EltTy = PTy->getElementType();
2865 // Figure out if there is a Packed type corresponding to this Vector
2866 // type. If so, convert to the packed type.
2867 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2868 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2869 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
2870 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
2872 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2874 assert(0 && "Don't support illegal by-val vector call args yet!");
2882 // Figure out the result value types.
2883 SmallVector<MVT::ValueType, 4> RetTys;
2885 if (RetTy != Type::VoidTy) {
2886 MVT::ValueType VT = getValueType(RetTy);
2887 switch (getTypeAction(VT)) {
2888 default: assert(0 && "Unknown type action!");
2890 RetTys.push_back(VT);
2893 RetTys.push_back(getTypeToTransformTo(VT));
2896 if (VT != MVT::Vector) {
2897 // If this is a large integer, it needs to be reassembled from small
2898 // integers. Figure out what the source elt type is and how many small
2900 MVT::ValueType NVT = getTypeToTransformTo(VT);
2901 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2902 for (unsigned i = 0; i != NumVals; ++i)
2903 RetTys.push_back(NVT);
2905 // Otherwise, this is a vector type. We only support legal vectors
2907 const PackedType *PTy = cast<PackedType>(RetTy);
2908 unsigned NumElems = PTy->getNumElements();
2909 const Type *EltTy = PTy->getElementType();
2911 // Figure out if there is a Packed type corresponding to this Vector
2912 // type. If so, convert to the packed type.
2913 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2914 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2915 RetTys.push_back(TVT);
2917 assert(0 && "Don't support illegal by-val vector call results yet!");
2924 RetTys.push_back(MVT::Other); // Always has a chain.
2926 // Finally, create the CALL node.
2927 SDOperand Res = DAG.getNode(ISD::CALL,
2928 DAG.getVTList(&RetTys[0], RetTys.size()),
2929 &Ops[0], Ops.size());
2931 // This returns a pair of operands. The first element is the
2932 // return value for the function (if RetTy is not VoidTy). The second
2933 // element is the outgoing token chain.
2935 if (RetTys.size() != 1) {
2936 MVT::ValueType VT = getValueType(RetTy);
2937 if (RetTys.size() == 2) {
2940 // If this value was promoted, truncate it down.
2941 if (ResVal.getValueType() != VT) {
2942 if (VT == MVT::Vector) {
2943 // Insert a VBITCONVERT to convert from the packed result type to the
2944 // MVT::Vector type.
2945 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
2946 const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
2948 // Figure out if there is a Packed type corresponding to this Vector
2949 // type. If so, convert to the packed type.
2950 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2951 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2952 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
2953 // "N x PTyElementVT" MVT::Vector type.
2954 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
2955 DAG.getConstant(NumElems, MVT::i32),
2956 DAG.getValueType(getValueType(EltTy)));
2960 } else if (MVT::isInteger(VT)) {
2961 unsigned AssertOp = RetTy->isSigned() ?
2962 ISD::AssertSext : ISD::AssertZext;
2963 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
2964 DAG.getValueType(VT));
2965 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
2967 assert(MVT::isFloatingPoint(VT));
2968 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
2971 } else if (RetTys.size() == 3) {
2972 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
2973 Res.getValue(0), Res.getValue(1));
2976 assert(0 && "Case not handled yet!");
2980 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
2985 // It is always conservatively correct for llvm.returnaddress and
2986 // llvm.frameaddress to return 0.
2988 // FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
2989 // expanded to 0 if the target wants.
2990 std::pair<SDOperand, SDOperand>
2991 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
2992 unsigned Depth, SelectionDAG &DAG) {
2993 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
2996 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2997 assert(0 && "LowerOperation not implemented for this target!");
3002 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
3003 SelectionDAG &DAG) {
3004 assert(0 && "CustomPromoteOperation not implemented for this target!");
3009 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
3010 unsigned Depth = (unsigned)cast<ConstantInt>(I.getOperand(1))->getZExtValue();
3011 std::pair<SDOperand,SDOperand> Result =
3012 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
3013 setValue(&I, Result.first);
3014 DAG.setRoot(Result.second);
3017 /// getMemsetValue - Vectorized representation of the memset value
3019 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
3020 SelectionDAG &DAG) {
3021 MVT::ValueType CurVT = VT;
3022 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
3023 uint64_t Val = C->getValue() & 255;
3025 while (CurVT != MVT::i8) {
3026 Val = (Val << Shift) | Val;
3028 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
3030 return DAG.getConstant(Val, VT);
3032 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
3034 while (CurVT != MVT::i8) {
3036 DAG.getNode(ISD::OR, VT,
3037 DAG.getNode(ISD::SHL, VT, Value,
3038 DAG.getConstant(Shift, MVT::i8)), Value);
3040 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
3047 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
3048 /// used when a memcpy is turned into a memset when the source is a constant
3050 static SDOperand getMemsetStringVal(MVT::ValueType VT,
3051 SelectionDAG &DAG, TargetLowering &TLI,
3052 std::string &Str, unsigned Offset) {
3053 MVT::ValueType CurVT = VT;
3055 unsigned MSB = getSizeInBits(VT) / 8;
3056 if (TLI.isLittleEndian())
3057 Offset = Offset + MSB - 1;
3058 for (unsigned i = 0; i != MSB; ++i) {
3059 Val = (Val << 8) | Str[Offset];
3060 Offset += TLI.isLittleEndian() ? -1 : 1;
3062 return DAG.getConstant(Val, VT);
3065 /// getMemBasePlusOffset - Returns base and offset node for the
3066 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
3067 SelectionDAG &DAG, TargetLowering &TLI) {
3068 MVT::ValueType VT = Base.getValueType();
3069 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
3072 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
3073 /// to replace the memset / memcpy is below the threshold. It also returns the
3074 /// types of the sequence of memory ops to perform memset / memcpy.
3075 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
3076 unsigned Limit, uint64_t Size,
3077 unsigned Align, TargetLowering &TLI) {
3080 if (TLI.allowsUnalignedMemoryAccesses()) {
3083 switch (Align & 7) {
3099 MVT::ValueType LVT = MVT::i64;
3100 while (!TLI.isTypeLegal(LVT))
3101 LVT = (MVT::ValueType)((unsigned)LVT - 1);
3102 assert(MVT::isInteger(LVT));
3107 unsigned NumMemOps = 0;
3109 unsigned VTSize = getSizeInBits(VT) / 8;
3110 while (VTSize > Size) {
3111 VT = (MVT::ValueType)((unsigned)VT - 1);
3114 assert(MVT::isInteger(VT));
3116 if (++NumMemOps > Limit)
3118 MemOps.push_back(VT);
3125 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
3126 SDOperand Op1 = getValue(I.getOperand(1));
3127 SDOperand Op2 = getValue(I.getOperand(2));
3128 SDOperand Op3 = getValue(I.getOperand(3));
3129 SDOperand Op4 = getValue(I.getOperand(4));
3130 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
3131 if (Align == 0) Align = 1;
3133 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
3134 std::vector<MVT::ValueType> MemOps;
3136 // Expand memset / memcpy to a series of load / store ops
3137 // if the size operand falls below a certain threshold.
3138 SmallVector<SDOperand, 8> OutChains;
3140 default: break; // Do nothing for now.
3142 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
3143 Size->getValue(), Align, TLI)) {
3144 unsigned NumMemOps = MemOps.size();
3145 unsigned Offset = 0;
3146 for (unsigned i = 0; i < NumMemOps; i++) {
3147 MVT::ValueType VT = MemOps[i];
3148 unsigned VTSize = getSizeInBits(VT) / 8;
3149 SDOperand Value = getMemsetValue(Op2, VT, DAG);
3150 SDOperand Store = DAG.getStore(getRoot(), Value,
3151 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
3152 I.getOperand(1), Offset);
3153 OutChains.push_back(Store);
3160 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
3161 Size->getValue(), Align, TLI)) {
3162 unsigned NumMemOps = MemOps.size();
3163 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
3164 GlobalAddressSDNode *G = NULL;
3166 bool CopyFromStr = false;
3168 if (Op2.getOpcode() == ISD::GlobalAddress)
3169 G = cast<GlobalAddressSDNode>(Op2);
3170 else if (Op2.getOpcode() == ISD::ADD &&
3171 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
3172 Op2.getOperand(1).getOpcode() == ISD::Constant) {
3173 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
3174 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
3177 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
3179 Str = GV->getStringValue(false);
3187 for (unsigned i = 0; i < NumMemOps; i++) {
3188 MVT::ValueType VT = MemOps[i];
3189 unsigned VTSize = getSizeInBits(VT) / 8;
3190 SDOperand Value, Chain, Store;
3193 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
3196 DAG.getStore(Chain, Value,
3197 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
3198 I.getOperand(1), DstOff);
3200 Value = DAG.getLoad(VT, getRoot(),
3201 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
3202 I.getOperand(2), SrcOff);
3203 Chain = Value.getValue(1);
3205 DAG.getStore(Chain, Value,
3206 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
3207 I.getOperand(1), DstOff);
3209 OutChains.push_back(Store);
3218 if (!OutChains.empty()) {
3219 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
3220 &OutChains[0], OutChains.size()));
3225 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
3228 //===----------------------------------------------------------------------===//
3229 // SelectionDAGISel code
3230 //===----------------------------------------------------------------------===//
3232 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
3233 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
3236 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
3237 // FIXME: we only modify the CFG to split critical edges. This
3238 // updates dom and loop info.
3239 AU.addRequired<AliasAnalysis>();
3243 /// OptimizeNoopCopyExpression - We have determined that the specified cast
3244 /// instruction is a noop copy (e.g. it's casting from one pointer type to
3245 /// another, int->uint, or int->sbyte on PPC.
3247 /// Return true if any changes are made.
3248 static bool OptimizeNoopCopyExpression(CastInst *CI) {
3249 BasicBlock *DefBB = CI->getParent();
3251 /// InsertedCasts - Only insert a cast in each block once.
3252 std::map<BasicBlock*, CastInst*> InsertedCasts;
3254 bool MadeChange = false;
3255 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
3257 Use &TheUse = UI.getUse();
3258 Instruction *User = cast<Instruction>(*UI);
3260 // Figure out which BB this cast is used in. For PHI's this is the
3261 // appropriate predecessor block.
3262 BasicBlock *UserBB = User->getParent();
3263 if (PHINode *PN = dyn_cast<PHINode>(User)) {
3264 unsigned OpVal = UI.getOperandNo()/2;
3265 UserBB = PN->getIncomingBlock(OpVal);
3268 // Preincrement use iterator so we don't invalidate it.
3271 // If this user is in the same block as the cast, don't change the cast.
3272 if (UserBB == DefBB) continue;
3274 // If we have already inserted a cast into this block, use it.
3275 CastInst *&InsertedCast = InsertedCasts[UserBB];
3277 if (!InsertedCast) {
3278 BasicBlock::iterator InsertPt = UserBB->begin();
3279 while (isa<PHINode>(InsertPt)) ++InsertPt;
3282 new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3286 // Replace a use of the cast with a use of the new casat.
3287 TheUse = InsertedCast;
3290 // If we removed all uses, nuke the cast.
3291 if (CI->use_empty())
3292 CI->eraseFromParent();
3297 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
3298 /// casting to the type of GEPI.
3299 static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
3300 Instruction *GEPI, Value *Ptr,
3302 if (V) return V; // Already computed.
3304 BasicBlock::iterator InsertPt;
3305 if (BB == GEPI->getParent()) {
3306 // If insert into the GEP's block, insert right after the GEP.
3310 // Otherwise, insert at the top of BB, after any PHI nodes
3311 InsertPt = BB->begin();
3312 while (isa<PHINode>(InsertPt)) ++InsertPt;
3315 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3316 // BB so that there is only one value live across basic blocks (the cast
3318 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3319 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3320 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3322 // Add the offset, cast it to the right type.
3323 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
3324 return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
3327 /// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3328 /// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
3329 /// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3330 /// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
3331 /// sink PtrOffset into user blocks where doing so will likely allow us to fold
3332 /// the constant add into a load or store instruction. Additionally, if a user
3333 /// is a pointer-pointer cast, we look through it to find its users.
3334 static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3335 Constant *PtrOffset, BasicBlock *DefBB,
3336 GetElementPtrInst *GEPI,
3337 std::map<BasicBlock*,Instruction*> &InsertedExprs) {
3338 while (!RepPtr->use_empty()) {
3339 Instruction *User = cast<Instruction>(RepPtr->use_back());
3341 // If the user is a Pointer-Pointer cast, recurse.
3342 if (isa<CastInst>(User) && isa<PointerType>(User->getType())) {
3343 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3345 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
3346 // could invalidate an iterator.
3347 User->setOperand(0, UndefValue::get(RepPtr->getType()));
3351 // If this is a load of the pointer, or a store through the pointer, emit
3352 // the increment into the load/store block.
3353 Instruction *NewVal;
3354 if (isa<LoadInst>(User) ||
3355 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3356 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3357 User->getParent(), GEPI,
3360 // If this use is not foldable into the addressing mode, use a version
3361 // emitted in the GEP block.
3362 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3366 if (GEPI->getType() != RepPtr->getType()) {
3367 BasicBlock::iterator IP = NewVal;
3369 NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP);
3371 User->replaceUsesOfWith(RepPtr, NewVal);
3376 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3377 /// selection, we want to be a bit careful about some things. In particular, if
3378 /// we have a GEP instruction that is used in a different block than it is
3379 /// defined, the addressing expression of the GEP cannot be folded into loads or
3380 /// stores that use it. In this case, decompose the GEP and move constant
3381 /// indices into blocks that use it.
3382 static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
3383 const TargetData *TD) {
3384 // If this GEP is only used inside the block it is defined in, there is no
3385 // need to rewrite it.
3386 bool isUsedOutsideDefBB = false;
3387 BasicBlock *DefBB = GEPI->getParent();
3388 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3390 if (cast<Instruction>(*UI)->getParent() != DefBB) {
3391 isUsedOutsideDefBB = true;
3395 if (!isUsedOutsideDefBB) return false;
3397 // If this GEP has no non-zero constant indices, there is nothing we can do,
3399 bool hasConstantIndex = false;
3400 bool hasVariableIndex = false;
3401 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3402 E = GEPI->op_end(); OI != E; ++OI) {
3403 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
3404 if (CI->getZExtValue()) {
3405 hasConstantIndex = true;
3409 hasVariableIndex = true;
3413 // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3414 if (!hasConstantIndex && !hasVariableIndex) {
3415 Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(),
3416 GEPI->getName(), GEPI);
3417 GEPI->replaceAllUsesWith(NC);
3418 GEPI->eraseFromParent();
3422 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
3423 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3426 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
3427 // constant offset (which we now know is non-zero) and deal with it later.
3428 uint64_t ConstantOffset = 0;
3429 const Type *UIntPtrTy = TD->getIntPtrType();
3430 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3431 const Type *Ty = GEPI->getOperand(0)->getType();
3433 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3434 E = GEPI->op_end(); OI != E; ++OI) {
3436 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3437 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
3439 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
3440 Ty = StTy->getElementType(Field);
3442 Ty = cast<SequentialType>(Ty)->getElementType();
3444 // Handle constant subscripts.
3445 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3446 if (CI->getZExtValue() == 0) continue;
3447 if (CI->getType()->isSigned())
3448 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CI->getSExtValue();
3450 ConstantOffset += TD->getTypeSize(Ty)*CI->getZExtValue();
3454 // Ptr = Ptr + Idx * ElementSize;
3456 // Cast Idx to UIntPtrTy if needed.
3457 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
3459 uint64_t ElementSize = TD->getTypeSize(Ty);
3460 // Mask off bits that should not be set.
3461 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3462 Constant *SizeCst = ConstantInt::get(UIntPtrTy, ElementSize);
3464 // Multiply by the element size and add to the base.
3465 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3466 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3470 // Make sure that the offset fits in uintptr_t.
3471 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3472 Constant *PtrOffset = ConstantInt::get(UIntPtrTy, ConstantOffset);
3474 // Okay, we have now emitted all of the variable index parts to the BB that
3475 // the GEP is defined in. Loop over all of the using instructions, inserting
3476 // an "add Ptr, ConstantOffset" into each block that uses it and update the
3477 // instruction to use the newly computed value, making GEPI dead. When the
3478 // user is a load or store instruction address, we emit the add into the user
3479 // block, otherwise we use a canonical version right next to the gep (these
3480 // won't be foldable as addresses, so we might as well share the computation).
3482 std::map<BasicBlock*,Instruction*> InsertedExprs;
3483 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3485 // Finally, the GEP is dead, remove it.
3486 GEPI->eraseFromParent();
3492 /// SplitEdgeNicely - Split the critical edge from TI to it's specified
3493 /// successor if it will improve codegen. We only do this if the successor has
3494 /// phi nodes (otherwise critical edges are ok). If there is already another
3495 /// predecessor of the succ that is empty (and thus has no phi nodes), use it
3496 /// instead of introducing a new block.
3497 static void SplitEdgeNicely(TerminatorInst *TI, unsigned SuccNum, Pass *P) {
3498 BasicBlock *TIBB = TI->getParent();
3499 BasicBlock *Dest = TI->getSuccessor(SuccNum);
3500 assert(isa<PHINode>(Dest->begin()) &&
3501 "This should only be called if Dest has a PHI!");
3503 /// TIPHIValues - This array is lazily computed to determine the values of
3504 /// PHIs in Dest that TI would provide.
3505 std::vector<Value*> TIPHIValues;
3507 // Check to see if Dest has any blocks that can be used as a split edge for
3509 for (pred_iterator PI = pred_begin(Dest), E = pred_end(Dest); PI != E; ++PI) {
3510 BasicBlock *Pred = *PI;
3511 // To be usable, the pred has to end with an uncond branch to the dest.
3512 BranchInst *PredBr = dyn_cast<BranchInst>(Pred->getTerminator());
3513 if (!PredBr || !PredBr->isUnconditional() ||
3514 // Must be empty other than the branch.
3515 &Pred->front() != PredBr)
3518 // Finally, since we know that Dest has phi nodes in it, we have to make
3519 // sure that jumping to Pred will have the same affect as going to Dest in
3520 // terms of PHI values.
3523 bool FoundMatch = true;
3524 for (BasicBlock::iterator I = Dest->begin();
3525 (PN = dyn_cast<PHINode>(I)); ++I, ++PHINo) {
3526 if (PHINo == TIPHIValues.size())
3527 TIPHIValues.push_back(PN->getIncomingValueForBlock(TIBB));
3529 // If the PHI entry doesn't work, we can't use this pred.
3530 if (TIPHIValues[PHINo] != PN->getIncomingValueForBlock(Pred)) {
3536 // If we found a workable predecessor, change TI to branch to Succ.
3538 Dest->removePredecessor(TIBB);
3539 TI->setSuccessor(SuccNum, Pred);
3544 SplitCriticalEdge(TI, SuccNum, P, true);
3548 bool SelectionDAGISel::runOnFunction(Function &Fn) {
3549 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3550 RegMap = MF.getSSARegMap();
3551 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
3553 // First, split all critical edges.
3555 // In this pass we also look for GEP and cast instructions that are used
3556 // across basic blocks and rewrite them to improve basic-block-at-a-time
3559 bool MadeChange = true;
3560 while (MadeChange) {
3562 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
3563 // Split all critical edges where the dest block has a PHI.
3564 TerminatorInst *BBTI = BB->getTerminator();
3565 if (BBTI->getNumSuccessors() > 1) {
3566 for (unsigned i = 0, e = BBTI->getNumSuccessors(); i != e; ++i)
3567 if (isa<PHINode>(BBTI->getSuccessor(i)->begin()) &&
3568 isCriticalEdge(BBTI, i, true))
3569 SplitEdgeNicely(BBTI, i, this);
3573 for (BasicBlock::iterator BBI = BB->begin(), E = BB->end(); BBI != E; ) {
3574 Instruction *I = BBI++;
3575 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
3576 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
3577 } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
3578 // If the source of the cast is a constant, then this should have
3579 // already been constant folded. The only reason NOT to constant fold
3580 // it is if something (e.g. LSR) was careful to place the constant
3581 // evaluation in a block other than then one that uses it (e.g. to hoist
3582 // the address of globals out of a loop). If this is the case, we don't
3583 // want to forward-subst the cast.
3584 if (isa<Constant>(CI->getOperand(0)))
3587 // If this is a noop copy, sink it into user blocks to reduce the number
3588 // of virtual registers that must be created and coallesced.
3589 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
3590 MVT::ValueType DstVT = TLI.getValueType(CI->getType());
3592 // This is an fp<->int conversion?
3593 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
3596 // If this is an extension, it will be a zero or sign extension, which
3598 if (SrcVT < DstVT) continue;
3600 // If these values will be promoted, find out what they will be promoted
3601 // to. This helps us consider truncates on PPC as noop copies when they
3603 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
3604 SrcVT = TLI.getTypeToTransformTo(SrcVT);
3605 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
3606 DstVT = TLI.getTypeToTransformTo(DstVT);
3608 // If, after promotion, these are the same types, this is a noop copy.
3610 MadeChange |= OptimizeNoopCopyExpression(CI);
3616 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
3618 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
3619 SelectBasicBlock(I, MF, FuncInfo);
3624 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
3626 SDOperand Op = getValue(V);
3627 assert((Op.getOpcode() != ISD::CopyFromReg ||
3628 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
3629 "Copy from a reg to the same reg!");
3631 // If this type is not legal, we must make sure to not create an invalid
3633 MVT::ValueType SrcVT = Op.getValueType();
3634 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
3635 if (SrcVT == DestVT) {
3636 return DAG.getCopyToReg(getRoot(), Reg, Op);
3637 } else if (SrcVT == MVT::Vector) {
3638 // Handle copies from generic vectors to registers.
3639 MVT::ValueType PTyElementVT, PTyLegalElementVT;
3640 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
3641 PTyElementVT, PTyLegalElementVT);
3643 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
3644 // MVT::Vector type.
3645 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
3646 DAG.getConstant(NE, MVT::i32),
3647 DAG.getValueType(PTyElementVT));
3649 // Loop over all of the elements of the resultant vector,
3650 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
3651 // copying them into output registers.
3652 SmallVector<SDOperand, 8> OutChains;
3653 SDOperand Root = getRoot();
3654 for (unsigned i = 0; i != NE; ++i) {
3655 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
3656 Op, DAG.getConstant(i, TLI.getPointerTy()));
3657 if (PTyElementVT == PTyLegalElementVT) {
3658 // Elements are legal.
3659 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3660 } else if (PTyLegalElementVT > PTyElementVT) {
3661 // Elements are promoted.
3662 if (MVT::isFloatingPoint(PTyLegalElementVT))
3663 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
3665 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
3666 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3668 // Elements are expanded.
3669 // The src value is expanded into multiple registers.
3670 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3671 Elt, DAG.getConstant(0, TLI.getPointerTy()));
3672 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3673 Elt, DAG.getConstant(1, TLI.getPointerTy()));
3674 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
3675 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
3678 return DAG.getNode(ISD::TokenFactor, MVT::Other,
3679 &OutChains[0], OutChains.size());
3680 } else if (SrcVT < DestVT) {
3681 // The src value is promoted to the register.
3682 if (MVT::isFloatingPoint(SrcVT))
3683 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
3685 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
3686 return DAG.getCopyToReg(getRoot(), Reg, Op);
3688 // The src value is expanded into multiple registers.
3689 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3690 Op, DAG.getConstant(0, TLI.getPointerTy()));
3691 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3692 Op, DAG.getConstant(1, TLI.getPointerTy()));
3693 Op = DAG.getCopyToReg(getRoot(), Reg, Lo);
3694 return DAG.getCopyToReg(Op, Reg+1, Hi);
3698 void SelectionDAGISel::
3699 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
3700 std::vector<SDOperand> &UnorderedChains) {
3701 // If this is the entry block, emit arguments.
3702 Function &F = *BB->getParent();
3703 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
3704 SDOperand OldRoot = SDL.DAG.getRoot();
3705 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
3708 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
3710 if (!AI->use_empty()) {
3711 SDL.setValue(AI, Args[a]);
3713 // If this argument is live outside of the entry block, insert a copy from
3714 // whereever we got it to the vreg that other BB's will reference it as.
3715 if (FuncInfo.ValueMap.count(AI)) {
3717 SDL.CopyValueToVirtualRegister(AI, FuncInfo.ValueMap[AI]);
3718 UnorderedChains.push_back(Copy);
3722 // Finally, if the target has anything special to do, allow it to do so.
3723 // FIXME: this should insert code into the DAG!
3724 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
3727 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3728 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
3729 FunctionLoweringInfo &FuncInfo) {
3730 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
3732 std::vector<SDOperand> UnorderedChains;
3734 // Lower any arguments needed in this block if this is the entry block.
3735 if (LLVMBB == &LLVMBB->getParent()->front())
3736 LowerArguments(LLVMBB, SDL, UnorderedChains);
3738 BB = FuncInfo.MBBMap[LLVMBB];
3739 SDL.setCurrentBasicBlock(BB);
3741 // Lower all of the non-terminator instructions.
3742 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3746 // Ensure that all instructions which are used outside of their defining
3747 // blocks are available as virtual registers.
3748 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
3749 if (!I->use_empty() && !isa<PHINode>(I)) {
3750 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
3751 if (VMI != FuncInfo.ValueMap.end())
3752 UnorderedChains.push_back(
3753 SDL.CopyValueToVirtualRegister(I, VMI->second));
3756 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
3757 // ensure constants are generated when needed. Remember the virtual registers
3758 // that need to be added to the Machine PHI nodes as input. We cannot just
3759 // directly add them, because expansion might result in multiple MBB's for one
3760 // BB. As such, the start of the BB might correspond to a different MBB than
3763 TerminatorInst *TI = LLVMBB->getTerminator();
3765 // Emit constants only once even if used by multiple PHI nodes.
3766 std::map<Constant*, unsigned> ConstantsOut;
3768 // Vector bool would be better, but vector<bool> is really slow.
3769 std::vector<unsigned char> SuccsHandled;
3770 if (TI->getNumSuccessors())
3771 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
3773 // Check successor nodes PHI nodes that expect a constant to be available from
3775 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
3776 BasicBlock *SuccBB = TI->getSuccessor(succ);
3777 if (!isa<PHINode>(SuccBB->begin())) continue;
3778 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
3780 // If this terminator has multiple identical successors (common for
3781 // switches), only handle each succ once.
3782 unsigned SuccMBBNo = SuccMBB->getNumber();
3783 if (SuccsHandled[SuccMBBNo]) continue;
3784 SuccsHandled[SuccMBBNo] = true;
3786 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
3789 // At this point we know that there is a 1-1 correspondence between LLVM PHI
3790 // nodes and Machine PHI nodes, but the incoming operands have not been
3792 for (BasicBlock::iterator I = SuccBB->begin();
3793 (PN = dyn_cast<PHINode>(I)); ++I) {
3794 // Ignore dead phi's.
3795 if (PN->use_empty()) continue;
3798 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
3799 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
3800 unsigned &RegOut = ConstantsOut[C];
3802 RegOut = FuncInfo.CreateRegForValue(C);
3803 UnorderedChains.push_back(
3804 SDL.CopyValueToVirtualRegister(C, RegOut));
3808 Reg = FuncInfo.ValueMap[PHIOp];
3810 assert(isa<AllocaInst>(PHIOp) &&
3811 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
3812 "Didn't codegen value into a register!??");
3813 Reg = FuncInfo.CreateRegForValue(PHIOp);
3814 UnorderedChains.push_back(
3815 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
3819 // Remember that this register needs to added to the machine PHI node as
3820 // the input for this MBB.
3821 MVT::ValueType VT = TLI.getValueType(PN->getType());
3822 unsigned NumElements;
3823 if (VT != MVT::Vector)
3824 NumElements = TLI.getNumElements(VT);
3826 MVT::ValueType VT1,VT2;
3828 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
3831 for (unsigned i = 0, e = NumElements; i != e; ++i)
3832 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
3835 ConstantsOut.clear();
3837 // Turn all of the unordered chains into one factored node.
3838 if (!UnorderedChains.empty()) {
3839 SDOperand Root = SDL.getRoot();
3840 if (Root.getOpcode() != ISD::EntryToken) {
3841 unsigned i = 0, e = UnorderedChains.size();
3842 for (; i != e; ++i) {
3843 assert(UnorderedChains[i].Val->getNumOperands() > 1);
3844 if (UnorderedChains[i].Val->getOperand(0) == Root)
3845 break; // Don't add the root if we already indirectly depend on it.
3849 UnorderedChains.push_back(Root);
3851 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
3852 &UnorderedChains[0], UnorderedChains.size()));
3855 // Lower the terminator after the copies are emitted.
3856 SDL.visit(*LLVMBB->getTerminator());
3858 // Copy over any CaseBlock records that may now exist due to SwitchInst
3859 // lowering, as well as any jump table information.
3860 SwitchCases.clear();
3861 SwitchCases = SDL.SwitchCases;
3864 // Make sure the root of the DAG is up-to-date.
3865 DAG.setRoot(SDL.getRoot());
3868 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
3869 // Get alias analysis for load/store combining.
3870 AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
3872 // Run the DAG combiner in pre-legalize mode.
3873 DAG.Combine(false, AA);
3875 DEBUG(std::cerr << "Lowered selection DAG:\n");
3878 // Second step, hack on the DAG until it only uses operations and types that
3879 // the target supports.
3882 DEBUG(std::cerr << "Legalized selection DAG:\n");
3885 // Run the DAG combiner in post-legalize mode.
3886 DAG.Combine(true, AA);
3888 if (ViewISelDAGs) DAG.viewGraph();
3890 // Third, instruction select all of the operations to machine code, adding the
3891 // code to the MachineBasicBlock.
3892 InstructionSelectBasicBlock(DAG);
3894 DEBUG(std::cerr << "Selected machine code:\n");
3898 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
3899 FunctionLoweringInfo &FuncInfo) {
3900 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
3902 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3905 // First step, lower LLVM code to some DAG. This DAG may use operations and
3906 // types that are not supported by the target.
3907 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
3909 // Second step, emit the lowered DAG as machine code.
3910 CodeGenAndEmitDAG(DAG);
3913 // Next, now that we know what the last MBB the LLVM BB expanded is, update
3914 // PHI nodes in successors.
3915 if (SwitchCases.empty() && JT.Reg == 0) {
3916 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3917 MachineInstr *PHI = PHINodesToUpdate[i].first;
3918 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3919 "This is not a machine PHI node that we are updating!");
3920 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
3921 PHI->addMachineBasicBlockOperand(BB);
3926 // If the JumpTable record is filled in, then we need to emit a jump table.
3927 // Updating the PHI nodes is tricky in this case, since we need to determine
3928 // whether the PHI is a successor of the range check MBB or the jump table MBB
3930 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
3931 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3933 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3934 MachineBasicBlock *RangeBB = BB;
3935 // Set the current basic block to the mbb we wish to insert the code into
3937 SDL.setCurrentBasicBlock(BB);
3939 SDL.visitJumpTable(JT);
3940 SDAG.setRoot(SDL.getRoot());
3941 CodeGenAndEmitDAG(SDAG);
3943 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3944 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3945 MachineBasicBlock *PHIBB = PHI->getParent();
3946 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3947 "This is not a machine PHI node that we are updating!");
3948 if (PHIBB == JT.Default) {
3949 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
3950 PHI->addMachineBasicBlockOperand(RangeBB);
3952 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
3953 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
3954 PHI->addMachineBasicBlockOperand(BB);
3960 // If the switch block involved a branch to one of the actual successors, we
3961 // need to update PHI nodes in that block.
3962 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3963 MachineInstr *PHI = PHINodesToUpdate[i].first;
3964 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3965 "This is not a machine PHI node that we are updating!");
3966 if (BB->isSuccessor(PHI->getParent())) {
3967 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
3968 PHI->addMachineBasicBlockOperand(BB);
3972 // If we generated any switch lowering information, build and codegen any
3973 // additional DAGs necessary.
3974 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
3975 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3977 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3979 // Set the current basic block to the mbb we wish to insert the code into
3980 BB = SwitchCases[i].ThisBB;
3981 SDL.setCurrentBasicBlock(BB);
3984 SDL.visitSwitchCase(SwitchCases[i]);
3985 SDAG.setRoot(SDL.getRoot());
3986 CodeGenAndEmitDAG(SDAG);
3988 // Handle any PHI nodes in successors of this chunk, as if we were coming
3989 // from the original BB before switch expansion. Note that PHI nodes can
3990 // occur multiple times in PHINodesToUpdate. We have to be very careful to
3991 // handle them the right number of times.
3992 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
3993 for (MachineBasicBlock::iterator Phi = BB->begin();
3994 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
3995 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
3996 for (unsigned pn = 0; ; ++pn) {
3997 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
3998 if (PHINodesToUpdate[pn].first == Phi) {
3999 Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
4000 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
4006 // Don't process RHS if same block as LHS.
4007 if (BB == SwitchCases[i].FalseBB)
4008 SwitchCases[i].FalseBB = 0;
4010 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4011 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4012 SwitchCases[i].FalseBB = 0;
4014 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
4019 //===----------------------------------------------------------------------===//
4020 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4021 /// target node in the graph.
4022 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4023 if (ViewSchedDAGs) DAG.viewGraph();
4025 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
4029 RegisterScheduler::setDefault(Ctor);
4032 ScheduleDAG *SL = Ctor(this, &DAG, BB);
4038 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
4039 return new HazardRecognizer();
4042 //===----------------------------------------------------------------------===//
4043 // Helper functions used by the generated instruction selector.
4044 //===----------------------------------------------------------------------===//
4045 // Calls to these methods are generated by tblgen.
4047 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
4048 /// the dag combiner simplified the 255, we still want to match. RHS is the
4049 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
4050 /// specified in the .td file (e.g. 255).
4051 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
4052 int64_t DesiredMaskS) {
4053 uint64_t ActualMask = RHS->getValue();
4054 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4056 // If the actual mask exactly matches, success!
4057 if (ActualMask == DesiredMask)
4060 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4061 if (ActualMask & ~DesiredMask)
4064 // Otherwise, the DAG Combiner may have proven that the value coming in is
4065 // either already zero or is not demanded. Check for known zero input bits.
4066 uint64_t NeededMask = DesiredMask & ~ActualMask;
4067 if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask))
4070 // TODO: check to see if missing bits are just not demanded.
4072 // Otherwise, this pattern doesn't match.
4076 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
4077 /// the dag combiner simplified the 255, we still want to match. RHS is the
4078 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
4079 /// specified in the .td file (e.g. 255).
4080 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
4081 int64_t DesiredMaskS) {
4082 uint64_t ActualMask = RHS->getValue();
4083 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4085 // If the actual mask exactly matches, success!
4086 if (ActualMask == DesiredMask)
4089 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4090 if (ActualMask & ~DesiredMask)
4093 // Otherwise, the DAG Combiner may have proven that the value coming in is
4094 // either already zero or is not demanded. Check for known zero input bits.
4095 uint64_t NeededMask = DesiredMask & ~ActualMask;
4097 uint64_t KnownZero, KnownOne;
4098 getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
4100 // If all the missing bits in the or are already known to be set, match!
4101 if ((NeededMask & KnownOne) == NeededMask)
4104 // TODO: check to see if missing bits are just not demanded.
4106 // Otherwise, this pattern doesn't match.
4111 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
4112 /// by tblgen. Others should not call it.
4113 void SelectionDAGISel::
4114 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
4115 std::vector<SDOperand> InOps;
4116 std::swap(InOps, Ops);
4118 Ops.push_back(InOps[0]); // input chain.
4119 Ops.push_back(InOps[1]); // input asm string.
4121 unsigned i = 2, e = InOps.size();
4122 if (InOps[e-1].getValueType() == MVT::Flag)
4123 --e; // Don't process a flag operand if it is here.
4126 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
4127 if ((Flags & 7) != 4 /*MEM*/) {
4128 // Just skip over this operand, copying the operands verbatim.
4129 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
4130 i += (Flags >> 3) + 1;
4132 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
4133 // Otherwise, this is a memory operand. Ask the target to select it.
4134 std::vector<SDOperand> SelOps;
4135 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
4136 std::cerr << "Could not match memory address. Inline asm failure!\n";
4140 // Add this to the output node.
4141 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
4142 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
4147 // Add the flag input back if present.
4148 if (e != InOps.size())
4149 Ops.push_back(InOps.back());