1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/MRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/Compiler.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
60 cl::desc("Pop up a window to show SUnit dags after they are processed"));
62 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
65 //===---------------------------------------------------------------------===//
67 /// RegisterScheduler class - Track the registration of instruction schedulers.
69 //===---------------------------------------------------------------------===//
70 MachinePassRegistry RegisterScheduler::Registry;
72 //===---------------------------------------------------------------------===//
74 /// ISHeuristic command line option for instruction schedulers.
76 //===---------------------------------------------------------------------===//
78 cl::opt<RegisterScheduler::FunctionPassCtor, false,
79 RegisterPassParser<RegisterScheduler> >
80 ISHeuristic("pre-RA-sched",
81 cl::init(&createDefaultScheduler),
82 cl::desc("Instruction schedulers available (before register"
85 static RegisterScheduler
86 defaultListDAGScheduler("default", " Best scheduler for the target",
87 createDefaultScheduler);
90 namespace { struct AsmOperandInfo; }
93 /// RegsForValue - This struct represents the physical registers that a
94 /// particular value is assigned and the type information about the value.
95 /// This is needed because values can be promoted into larger registers and
96 /// expanded into multiple smaller registers than the value.
97 struct VISIBILITY_HIDDEN RegsForValue {
98 /// Regs - This list holds the register (for legal and promoted values)
99 /// or register set (for expanded values) that the value should be assigned
101 std::vector<unsigned> Regs;
103 /// RegVT - The value type of each register.
105 MVT::ValueType RegVT;
107 /// ValueVT - The value type of the LLVM value, which may be promoted from
108 /// RegVT or made from merging the two expanded parts.
109 MVT::ValueType ValueVT;
111 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
113 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
114 : RegVT(regvt), ValueVT(valuevt) {
117 RegsForValue(const std::vector<unsigned> ®s,
118 MVT::ValueType regvt, MVT::ValueType valuevt)
119 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
122 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
123 /// this value and returns the result as a ValueVT value. This uses
124 /// Chain/Flag as the input and updates them for the output Chain/Flag.
125 /// If the Flag pointer is NULL, no flag is used.
126 SDOperand getCopyFromRegs(SelectionDAG &DAG,
127 SDOperand &Chain, SDOperand *Flag) const;
129 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
130 /// specified value into the registers specified by this object. This uses
131 /// Chain/Flag as the input and updates them for the output Chain/Flag.
132 /// If the Flag pointer is NULL, no flag is used.
133 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
134 SDOperand &Chain, SDOperand *Flag) const;
136 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
137 /// operand list. This adds the code marker and includes the number of
138 /// values added into it.
139 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
140 std::vector<SDOperand> &Ops) const;
145 //===--------------------------------------------------------------------===//
146 /// createDefaultScheduler - This creates an instruction scheduler appropriate
148 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
150 MachineBasicBlock *BB) {
151 TargetLowering &TLI = IS->getTargetLowering();
153 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
154 return createTDListDAGScheduler(IS, DAG, BB);
156 assert(TLI.getSchedulingPreference() ==
157 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
158 return createBURRListDAGScheduler(IS, DAG, BB);
163 //===--------------------------------------------------------------------===//
164 /// FunctionLoweringInfo - This contains information that is global to a
165 /// function that is used when lowering a region of the function.
166 class FunctionLoweringInfo {
171 MachineRegisterInfo &RegInfo;
173 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
175 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
176 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
178 /// ValueMap - Since we emit code for the function a basic block at a time,
179 /// we must remember which virtual registers hold the values for
180 /// cross-basic-block values.
181 DenseMap<const Value*, unsigned> ValueMap;
183 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
184 /// the entry block. This allows the allocas to be efficiently referenced
185 /// anywhere in the function.
186 std::map<const AllocaInst*, int> StaticAllocaMap;
189 SmallSet<Instruction*, 8> CatchInfoLost;
190 SmallSet<Instruction*, 8> CatchInfoFound;
193 unsigned MakeReg(MVT::ValueType VT) {
194 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
197 /// isExportedInst - Return true if the specified value is an instruction
198 /// exported from its block.
199 bool isExportedInst(const Value *V) {
200 return ValueMap.count(V);
203 unsigned CreateRegForValue(const Value *V);
205 unsigned InitializeRegForValue(const Value *V) {
206 unsigned &R = ValueMap[V];
207 assert(R == 0 && "Already initialized this value register!");
208 return R = CreateRegForValue(V);
213 /// isSelector - Return true if this instruction is a call to the
214 /// eh.selector intrinsic.
215 static bool isSelector(Instruction *I) {
216 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
217 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
218 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
222 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
223 /// PHI nodes or outside of the basic block that defines it, or used by a
224 /// switch instruction, which may expand to multiple basic blocks.
225 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
226 if (isa<PHINode>(I)) return true;
227 BasicBlock *BB = I->getParent();
228 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
229 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
230 // FIXME: Remove switchinst special case.
231 isa<SwitchInst>(*UI))
236 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
237 /// entry block, return true. This includes arguments used by switches, since
238 /// the switch may expand into multiple basic blocks.
239 static bool isOnlyUsedInEntryBlock(Argument *A) {
240 BasicBlock *Entry = A->getParent()->begin();
241 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
242 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
243 return false; // Use not in entry block.
247 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
248 Function &fn, MachineFunction &mf)
249 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
251 // Create a vreg for each argument register that is not dead and is used
252 // outside of the entry block for the function.
253 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
255 if (!isOnlyUsedInEntryBlock(AI))
256 InitializeRegForValue(AI);
258 // Initialize the mapping of values to registers. This is only set up for
259 // instruction values that are used outside of the block that defines
261 Function::iterator BB = Fn.begin(), EB = Fn.end();
262 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
263 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
264 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
265 const Type *Ty = AI->getAllocatedType();
266 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
268 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
271 TySize *= CUI->getZExtValue(); // Get total allocated size.
272 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
273 StaticAllocaMap[AI] =
274 MF.getFrameInfo()->CreateStackObject(TySize, Align);
277 for (; BB != EB; ++BB)
278 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
279 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
280 if (!isa<AllocaInst>(I) ||
281 !StaticAllocaMap.count(cast<AllocaInst>(I)))
282 InitializeRegForValue(I);
284 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
285 // also creates the initial PHI MachineInstrs, though none of the input
286 // operands are populated.
287 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
288 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
290 MF.getBasicBlockList().push_back(MBB);
292 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
295 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
296 if (PN->use_empty()) continue;
298 MVT::ValueType VT = TLI.getValueType(PN->getType());
299 unsigned NumRegisters = TLI.getNumRegisters(VT);
300 unsigned PHIReg = ValueMap[PN];
301 assert(PHIReg && "PHI node does not have an assigned virtual register!");
302 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
303 for (unsigned i = 0; i != NumRegisters; ++i)
304 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
309 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
310 /// the correctly promoted or expanded types. Assign these registers
311 /// consecutive vreg numbers and return the first assigned number.
312 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
313 MVT::ValueType VT = TLI.getValueType(V->getType());
315 unsigned NumRegisters = TLI.getNumRegisters(VT);
316 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
318 unsigned R = MakeReg(RegisterVT);
319 for (unsigned i = 1; i != NumRegisters; ++i)
325 //===----------------------------------------------------------------------===//
326 /// SelectionDAGLowering - This is the common target-independent lowering
327 /// implementation that is parameterized by a TargetLowering object.
328 /// Also, targets can overload any lowering method.
331 class SelectionDAGLowering {
332 MachineBasicBlock *CurMBB;
334 DenseMap<const Value*, SDOperand> NodeMap;
336 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
337 /// them up and then emit token factor nodes when possible. This allows us to
338 /// get simple disambiguation between loads without worrying about alias
340 std::vector<SDOperand> PendingLoads;
342 /// Case - A struct to record the Value for a switch case, and the
343 /// case's target basic block.
347 MachineBasicBlock* BB;
349 Case() : Low(0), High(0), BB(0) { }
350 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
351 Low(low), High(high), BB(bb) { }
352 uint64_t size() const {
353 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
354 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
355 return (rHigh - rLow + 1ULL);
361 MachineBasicBlock* BB;
364 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
365 Mask(mask), BB(bb), Bits(bits) { }
368 typedef std::vector<Case> CaseVector;
369 typedef std::vector<CaseBits> CaseBitsVector;
370 typedef CaseVector::iterator CaseItr;
371 typedef std::pair<CaseItr, CaseItr> CaseRange;
373 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
374 /// of conditional branches.
376 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
377 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
379 /// CaseBB - The MBB in which to emit the compare and branch
380 MachineBasicBlock *CaseBB;
381 /// LT, GE - If nonzero, we know the current case value must be less-than or
382 /// greater-than-or-equal-to these Constants.
385 /// Range - A pair of iterators representing the range of case values to be
386 /// processed at this point in the binary search tree.
390 typedef std::vector<CaseRec> CaseRecVector;
392 /// The comparison function for sorting the switch case values in the vector.
393 /// WARNING: Case ranges should be disjoint!
395 bool operator () (const Case& C1, const Case& C2) {
396 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
397 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
398 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
399 return CI1->getValue().slt(CI2->getValue());
404 bool operator () (const CaseBits& C1, const CaseBits& C2) {
405 return C1.Bits > C2.Bits;
409 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
412 // TLI - This is information that describes the available target features we
413 // need for lowering. This indicates when operations are unavailable,
414 // implemented with a libcall, etc.
417 const TargetData *TD;
420 /// SwitchCases - Vector of CaseBlock structures used to communicate
421 /// SwitchInst code generation information.
422 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
423 /// JTCases - Vector of JumpTable structures used to communicate
424 /// SwitchInst code generation information.
425 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
426 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
428 /// FuncInfo - Information about the function as a whole.
430 FunctionLoweringInfo &FuncInfo;
432 /// GCI - Garbage collection metadata for the function.
433 CollectorMetadata *GCI;
435 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
437 FunctionLoweringInfo &funcinfo,
438 CollectorMetadata *gci)
439 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
440 FuncInfo(funcinfo), GCI(gci) {
443 /// getRoot - Return the current virtual root of the Selection DAG.
445 SDOperand getRoot() {
446 if (PendingLoads.empty())
447 return DAG.getRoot();
449 if (PendingLoads.size() == 1) {
450 SDOperand Root = PendingLoads[0];
452 PendingLoads.clear();
456 // Otherwise, we have to make a token factor node.
457 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
458 &PendingLoads[0], PendingLoads.size());
459 PendingLoads.clear();
464 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
466 void visit(Instruction &I) { visit(I.getOpcode(), I); }
468 void visit(unsigned Opcode, User &I) {
469 // Note: this doesn't use InstVisitor, because it has to work with
470 // ConstantExpr's in addition to instructions.
472 default: assert(0 && "Unknown instruction type encountered!");
474 // Build the switch statement using the Instruction.def file.
475 #define HANDLE_INST(NUM, OPCODE, CLASS) \
476 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
477 #include "llvm/Instruction.def"
481 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
483 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
484 const Value *SV, SDOperand Root,
485 bool isVolatile, unsigned Alignment);
487 SDOperand getValue(const Value *V);
489 void setValue(const Value *V, SDOperand NewN) {
490 SDOperand &N = NodeMap[V];
491 assert(N.Val == 0 && "Already set a value for this node!");
495 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
496 std::set<unsigned> &OutputRegs,
497 std::set<unsigned> &InputRegs);
499 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
500 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
502 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
503 void ExportFromCurrentBlock(Value *V);
504 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
505 MachineBasicBlock *LandingPad = NULL);
507 // Terminator instructions.
508 void visitRet(ReturnInst &I);
509 void visitBr(BranchInst &I);
510 void visitSwitch(SwitchInst &I);
511 void visitUnreachable(UnreachableInst &I) { /* noop */ }
513 // Helpers for visitSwitch
514 bool handleSmallSwitchRange(CaseRec& CR,
515 CaseRecVector& WorkList,
517 MachineBasicBlock* Default);
518 bool handleJTSwitchCase(CaseRec& CR,
519 CaseRecVector& WorkList,
521 MachineBasicBlock* Default);
522 bool handleBTSplitSwitchCase(CaseRec& CR,
523 CaseRecVector& WorkList,
525 MachineBasicBlock* Default);
526 bool handleBitTestsSwitchCase(CaseRec& CR,
527 CaseRecVector& WorkList,
529 MachineBasicBlock* Default);
530 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
531 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
532 void visitBitTestCase(MachineBasicBlock* NextMBB,
534 SelectionDAGISel::BitTestCase &B);
535 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
536 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
537 SelectionDAGISel::JumpTableHeader &JTH);
539 // These all get lowered before this pass.
540 void visitInvoke(InvokeInst &I);
541 void visitUnwind(UnwindInst &I);
543 void visitBinary(User &I, unsigned OpCode);
544 void visitShift(User &I, unsigned Opcode);
545 void visitAdd(User &I) {
546 if (I.getType()->isFPOrFPVector())
547 visitBinary(I, ISD::FADD);
549 visitBinary(I, ISD::ADD);
551 void visitSub(User &I);
552 void visitMul(User &I) {
553 if (I.getType()->isFPOrFPVector())
554 visitBinary(I, ISD::FMUL);
556 visitBinary(I, ISD::MUL);
558 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
559 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
560 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
561 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
562 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
563 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
564 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
565 void visitOr (User &I) { visitBinary(I, ISD::OR); }
566 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
567 void visitShl (User &I) { visitShift(I, ISD::SHL); }
568 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
569 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
570 void visitICmp(User &I);
571 void visitFCmp(User &I);
572 // Visit the conversion instructions
573 void visitTrunc(User &I);
574 void visitZExt(User &I);
575 void visitSExt(User &I);
576 void visitFPTrunc(User &I);
577 void visitFPExt(User &I);
578 void visitFPToUI(User &I);
579 void visitFPToSI(User &I);
580 void visitUIToFP(User &I);
581 void visitSIToFP(User &I);
582 void visitPtrToInt(User &I);
583 void visitIntToPtr(User &I);
584 void visitBitCast(User &I);
586 void visitExtractElement(User &I);
587 void visitInsertElement(User &I);
588 void visitShuffleVector(User &I);
590 void visitGetElementPtr(User &I);
591 void visitSelect(User &I);
593 void visitMalloc(MallocInst &I);
594 void visitFree(FreeInst &I);
595 void visitAlloca(AllocaInst &I);
596 void visitLoad(LoadInst &I);
597 void visitStore(StoreInst &I);
598 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
599 void visitCall(CallInst &I);
600 void visitInlineAsm(CallSite CS);
601 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
602 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
604 void visitVAStart(CallInst &I);
605 void visitVAArg(VAArgInst &I);
606 void visitVAEnd(CallInst &I);
607 void visitVACopy(CallInst &I);
609 void visitMemIntrinsic(CallInst &I, unsigned Op);
611 void visitUserOp1(Instruction &I) {
612 assert(0 && "UserOp1 should not exist at instruction selection time!");
615 void visitUserOp2(Instruction &I) {
616 assert(0 && "UserOp2 should not exist at instruction selection time!");
620 } // end namespace llvm
623 /// getCopyFromParts - Create a value that contains the
624 /// specified legal parts combined into the value they represent.
625 static SDOperand getCopyFromParts(SelectionDAG &DAG,
626 const SDOperand *Parts,
628 MVT::ValueType PartVT,
629 MVT::ValueType ValueVT,
630 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
631 if (!MVT::isVector(ValueVT) || NumParts == 1) {
632 SDOperand Val = Parts[0];
634 // If the value was expanded, copy from the top part.
636 assert(NumParts == 2 &&
637 "Cannot expand to more than 2 elts yet!");
638 SDOperand Hi = Parts[1];
639 if (!DAG.getTargetLoweringInfo().isLittleEndian())
641 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
644 // Otherwise, if the value was promoted or extended, truncate it to the
646 if (PartVT == ValueVT)
649 if (MVT::isVector(PartVT)) {
650 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
651 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
654 if (MVT::isVector(ValueVT)) {
655 assert(NumParts == 1 &&
656 MVT::getVectorElementType(ValueVT) == PartVT &&
657 MVT::getVectorNumElements(ValueVT) == 1 &&
658 "Only trivial scalar-to-vector conversions should get here!");
659 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
662 if (MVT::isInteger(PartVT) &&
663 MVT::isInteger(ValueVT)) {
664 if (ValueVT < PartVT) {
665 // For a truncate, see if we have any information to
666 // indicate whether the truncated bits will always be
667 // zero or sign-extension.
668 if (AssertOp != ISD::DELETED_NODE)
669 Val = DAG.getNode(AssertOp, PartVT, Val,
670 DAG.getValueType(ValueVT));
671 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
673 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
677 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT))
678 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, DAG.getIntPtrConstant(0));
680 if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
681 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
683 assert(0 && "Unknown mismatch!");
686 // Handle a multi-element vector.
687 MVT::ValueType IntermediateVT, RegisterVT;
688 unsigned NumIntermediates;
690 DAG.getTargetLoweringInfo()
691 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
694 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
695 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
696 assert(RegisterVT == Parts[0].getValueType() &&
697 "Part type doesn't match part!");
699 // Assemble the parts into intermediate operands.
700 SmallVector<SDOperand, 8> Ops(NumIntermediates);
701 if (NumIntermediates == NumParts) {
702 // If the register was not expanded, truncate or copy the value,
704 for (unsigned i = 0; i != NumParts; ++i)
705 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
706 PartVT, IntermediateVT);
707 } else if (NumParts > 0) {
708 // If the intermediate type was expanded, build the intermediate operands
710 assert(NumParts % NumIntermediates == 0 &&
711 "Must expand into a divisible number of parts!");
712 unsigned Factor = NumParts / NumIntermediates;
713 for (unsigned i = 0; i != NumIntermediates; ++i)
714 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
715 PartVT, IntermediateVT);
718 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
720 return DAG.getNode(MVT::isVector(IntermediateVT) ?
721 ISD::CONCAT_VECTORS :
723 ValueVT, &Ops[0], NumIntermediates);
726 /// getCopyToParts - Create a series of nodes that contain the
727 /// specified value split into legal parts.
728 static void getCopyToParts(SelectionDAG &DAG,
732 MVT::ValueType PartVT) {
733 TargetLowering &TLI = DAG.getTargetLoweringInfo();
734 MVT::ValueType PtrVT = TLI.getPointerTy();
735 MVT::ValueType ValueVT = Val.getValueType();
737 if (!MVT::isVector(ValueVT) || NumParts == 1) {
738 // If the value was expanded, copy from the parts.
740 for (unsigned i = 0; i != NumParts; ++i)
741 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
742 DAG.getConstant(i, PtrVT));
743 if (!DAG.getTargetLoweringInfo().isLittleEndian())
744 std::reverse(Parts, Parts + NumParts);
748 // If there is a single part and the types differ, this must be
750 if (PartVT != ValueVT) {
751 if (MVT::isVector(PartVT)) {
752 assert(MVT::isVector(ValueVT) &&
753 "Not a vector-vector cast?");
754 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
755 } else if (MVT::isVector(ValueVT)) {
756 assert(NumParts == 1 &&
757 MVT::getVectorElementType(ValueVT) == PartVT &&
758 MVT::getVectorNumElements(ValueVT) == 1 &&
759 "Only trivial vector-to-scalar conversions should get here!");
760 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
761 DAG.getConstant(0, PtrVT));
762 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
763 if (PartVT < ValueVT)
764 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
766 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val);
767 } else if (MVT::isFloatingPoint(PartVT) &&
768 MVT::isFloatingPoint(ValueVT)) {
769 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
770 } else if (MVT::getSizeInBits(PartVT) ==
771 MVT::getSizeInBits(ValueVT)) {
772 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
774 assert(0 && "Unknown mismatch!");
781 // Handle a multi-element vector.
782 MVT::ValueType IntermediateVT, RegisterVT;
783 unsigned NumIntermediates;
785 DAG.getTargetLoweringInfo()
786 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
788 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
790 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
791 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
793 // Split the vector into intermediate operands.
794 SmallVector<SDOperand, 8> Ops(NumIntermediates);
795 for (unsigned i = 0; i != NumIntermediates; ++i)
796 if (MVT::isVector(IntermediateVT))
797 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
799 DAG.getConstant(i * (NumElements / NumIntermediates),
802 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
804 DAG.getConstant(i, PtrVT));
806 // Split the intermediate operands into legal parts.
807 if (NumParts == NumIntermediates) {
808 // If the register was not expanded, promote or copy the value,
810 for (unsigned i = 0; i != NumParts; ++i)
811 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
812 } else if (NumParts > 0) {
813 // If the intermediate type was expanded, split each the value into
815 assert(NumParts % NumIntermediates == 0 &&
816 "Must expand into a divisible number of parts!");
817 unsigned Factor = NumParts / NumIntermediates;
818 for (unsigned i = 0; i != NumIntermediates; ++i)
819 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
824 SDOperand SelectionDAGLowering::getValue(const Value *V) {
825 SDOperand &N = NodeMap[V];
828 const Type *VTy = V->getType();
829 MVT::ValueType VT = TLI.getValueType(VTy);
830 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
831 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
832 visit(CE->getOpcode(), *CE);
833 SDOperand N1 = NodeMap[V];
834 assert(N1.Val && "visit didn't populate the ValueMap!");
836 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
837 return N = DAG.getGlobalAddress(GV, VT);
838 } else if (isa<ConstantPointerNull>(C)) {
839 return N = DAG.getConstant(0, TLI.getPointerTy());
840 } else if (isa<UndefValue>(C)) {
841 if (!isa<VectorType>(VTy))
842 return N = DAG.getNode(ISD::UNDEF, VT);
844 // Create a BUILD_VECTOR of undef nodes.
845 const VectorType *PTy = cast<VectorType>(VTy);
846 unsigned NumElements = PTy->getNumElements();
847 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
849 SmallVector<SDOperand, 8> Ops;
850 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
852 // Create a VConstant node with generic Vector type.
853 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
854 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
855 &Ops[0], Ops.size());
856 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
857 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
858 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
859 unsigned NumElements = PTy->getNumElements();
860 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
862 // Now that we know the number and type of the elements, push a
863 // Constant or ConstantFP node onto the ops list for each element of
864 // the vector constant.
865 SmallVector<SDOperand, 8> Ops;
866 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
867 for (unsigned i = 0; i != NumElements; ++i)
868 Ops.push_back(getValue(CP->getOperand(i)));
870 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
872 if (MVT::isFloatingPoint(PVT))
873 Op = DAG.getConstantFP(0, PVT);
875 Op = DAG.getConstant(0, PVT);
876 Ops.assign(NumElements, Op);
879 // Create a BUILD_VECTOR node.
880 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
881 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
884 // Canonicalize all constant ints to be unsigned.
885 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
889 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
890 std::map<const AllocaInst*, int>::iterator SI =
891 FuncInfo.StaticAllocaMap.find(AI);
892 if (SI != FuncInfo.StaticAllocaMap.end())
893 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
896 unsigned InReg = FuncInfo.ValueMap[V];
897 assert(InReg && "Value not in map!");
899 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
900 unsigned NumRegs = TLI.getNumRegisters(VT);
902 std::vector<unsigned> Regs(NumRegs);
903 for (unsigned i = 0; i != NumRegs; ++i)
906 RegsForValue RFV(Regs, RegisterVT, VT);
907 SDOperand Chain = DAG.getEntryNode();
909 return RFV.getCopyFromRegs(DAG, Chain, NULL);
913 void SelectionDAGLowering::visitRet(ReturnInst &I) {
914 if (I.getNumOperands() == 0) {
915 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
918 SmallVector<SDOperand, 8> NewValues;
919 NewValues.push_back(getRoot());
920 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
921 SDOperand RetOp = getValue(I.getOperand(i));
923 // If this is an integer return value, we need to promote it ourselves to
924 // the full width of a register, since getCopyToParts and Legalize will use
925 // ANY_EXTEND rather than sign/zero.
926 // FIXME: C calling convention requires the return type to be promoted to
927 // at least 32-bit. But this is not necessary for non-C calling conventions.
928 if (MVT::isInteger(RetOp.getValueType()) &&
929 RetOp.getValueType() < MVT::i64) {
930 MVT::ValueType TmpVT;
931 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
932 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
935 const Function *F = I.getParent()->getParent();
936 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
937 if (F->paramHasAttr(0, ParamAttr::SExt))
938 ExtendKind = ISD::SIGN_EXTEND;
939 if (F->paramHasAttr(0, ParamAttr::ZExt))
940 ExtendKind = ISD::ZERO_EXTEND;
941 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
942 NewValues.push_back(RetOp);
943 NewValues.push_back(DAG.getConstant(false, MVT::i32));
945 MVT::ValueType VT = RetOp.getValueType();
946 unsigned NumParts = TLI.getNumRegisters(VT);
947 MVT::ValueType PartVT = TLI.getRegisterType(VT);
948 SmallVector<SDOperand, 4> Parts(NumParts);
949 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT);
950 for (unsigned i = 0; i < NumParts; ++i) {
951 NewValues.push_back(Parts[i]);
952 NewValues.push_back(DAG.getConstant(false, MVT::i32));
956 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
957 &NewValues[0], NewValues.size()));
960 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
961 /// the current basic block, add it to ValueMap now so that we'll get a
963 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
964 // No need to export constants.
965 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
968 if (FuncInfo.isExportedInst(V)) return;
970 unsigned Reg = FuncInfo.InitializeRegForValue(V);
971 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
974 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
975 const BasicBlock *FromBB) {
976 // The operands of the setcc have to be in this block. We don't know
977 // how to export them from some other block.
978 if (Instruction *VI = dyn_cast<Instruction>(V)) {
979 // Can export from current BB.
980 if (VI->getParent() == FromBB)
983 // Is already exported, noop.
984 return FuncInfo.isExportedInst(V);
987 // If this is an argument, we can export it if the BB is the entry block or
988 // if it is already exported.
989 if (isa<Argument>(V)) {
990 if (FromBB == &FromBB->getParent()->getEntryBlock())
993 // Otherwise, can only export this if it is already exported.
994 return FuncInfo.isExportedInst(V);
997 // Otherwise, constants can always be exported.
1001 static bool InBlock(const Value *V, const BasicBlock *BB) {
1002 if (const Instruction *I = dyn_cast<Instruction>(V))
1003 return I->getParent() == BB;
1007 /// FindMergedConditions - If Cond is an expression like
1008 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1009 MachineBasicBlock *TBB,
1010 MachineBasicBlock *FBB,
1011 MachineBasicBlock *CurBB,
1013 // If this node is not part of the or/and tree, emit it as a branch.
1014 Instruction *BOp = dyn_cast<Instruction>(Cond);
1016 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1017 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1018 BOp->getParent() != CurBB->getBasicBlock() ||
1019 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1020 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1021 const BasicBlock *BB = CurBB->getBasicBlock();
1023 // If the leaf of the tree is a comparison, merge the condition into
1025 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1026 // The operands of the cmp have to be in this block. We don't know
1027 // how to export them from some other block. If this is the first block
1028 // of the sequence, no exporting is needed.
1030 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1031 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1032 BOp = cast<Instruction>(Cond);
1033 ISD::CondCode Condition;
1034 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1035 switch (IC->getPredicate()) {
1036 default: assert(0 && "Unknown icmp predicate opcode!");
1037 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1038 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1039 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1040 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1041 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1042 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1043 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1044 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1045 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1046 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1048 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1049 ISD::CondCode FPC, FOC;
1050 switch (FC->getPredicate()) {
1051 default: assert(0 && "Unknown fcmp predicate opcode!");
1052 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1053 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1054 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1055 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1056 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1057 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1058 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1059 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1060 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1061 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1062 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1063 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1064 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1065 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1066 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1067 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1069 if (FiniteOnlyFPMath())
1074 Condition = ISD::SETEQ; // silence warning.
1075 assert(0 && "Unknown compare instruction");
1078 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1079 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1080 SwitchCases.push_back(CB);
1084 // Create a CaseBlock record representing this branch.
1085 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1086 NULL, TBB, FBB, CurBB);
1087 SwitchCases.push_back(CB);
1092 // Create TmpBB after CurBB.
1093 MachineFunction::iterator BBI = CurBB;
1094 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1095 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1097 if (Opc == Instruction::Or) {
1098 // Codegen X | Y as:
1106 // Emit the LHS condition.
1107 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1109 // Emit the RHS condition into TmpBB.
1110 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1112 assert(Opc == Instruction::And && "Unknown merge op!");
1113 // Codegen X & Y as:
1120 // This requires creation of TmpBB after CurBB.
1122 // Emit the LHS condition.
1123 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1125 // Emit the RHS condition into TmpBB.
1126 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1130 /// If the set of cases should be emitted as a series of branches, return true.
1131 /// If we should emit this as a bunch of and/or'd together conditions, return
1134 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1135 if (Cases.size() != 2) return true;
1137 // If this is two comparisons of the same values or'd or and'd together, they
1138 // will get folded into a single comparison, so don't emit two blocks.
1139 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1140 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1141 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1142 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1149 void SelectionDAGLowering::visitBr(BranchInst &I) {
1150 // Update machine-CFG edges.
1151 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1153 // Figure out which block is immediately after the current one.
1154 MachineBasicBlock *NextBlock = 0;
1155 MachineFunction::iterator BBI = CurMBB;
1156 if (++BBI != CurMBB->getParent()->end())
1159 if (I.isUnconditional()) {
1160 // If this is not a fall-through branch, emit the branch.
1161 if (Succ0MBB != NextBlock)
1162 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1163 DAG.getBasicBlock(Succ0MBB)));
1165 // Update machine-CFG edges.
1166 CurMBB->addSuccessor(Succ0MBB);
1170 // If this condition is one of the special cases we handle, do special stuff
1172 Value *CondVal = I.getCondition();
1173 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1175 // If this is a series of conditions that are or'd or and'd together, emit
1176 // this as a sequence of branches instead of setcc's with and/or operations.
1177 // For example, instead of something like:
1190 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1191 if (BOp->hasOneUse() &&
1192 (BOp->getOpcode() == Instruction::And ||
1193 BOp->getOpcode() == Instruction::Or)) {
1194 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1195 // If the compares in later blocks need to use values not currently
1196 // exported from this block, export them now. This block should always
1197 // be the first entry.
1198 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1200 // Allow some cases to be rejected.
1201 if (ShouldEmitAsBranches(SwitchCases)) {
1202 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1203 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1204 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1207 // Emit the branch for this block.
1208 visitSwitchCase(SwitchCases[0]);
1209 SwitchCases.erase(SwitchCases.begin());
1213 // Okay, we decided not to do this, remove any inserted MBB's and clear
1215 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1216 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1218 SwitchCases.clear();
1222 // Create a CaseBlock record representing this branch.
1223 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1224 NULL, Succ0MBB, Succ1MBB, CurMBB);
1225 // Use visitSwitchCase to actually insert the fast branch sequence for this
1227 visitSwitchCase(CB);
1230 /// visitSwitchCase - Emits the necessary code to represent a single node in
1231 /// the binary search tree resulting from lowering a switch instruction.
1232 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1234 SDOperand CondLHS = getValue(CB.CmpLHS);
1236 // Build the setcc now.
1237 if (CB.CmpMHS == NULL) {
1238 // Fold "(X == true)" to X and "(X == false)" to !X to
1239 // handle common cases produced by branch lowering.
1240 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1242 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1243 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1244 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1246 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1248 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1250 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1251 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1253 SDOperand CmpOp = getValue(CB.CmpMHS);
1254 MVT::ValueType VT = CmpOp.getValueType();
1256 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1257 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1259 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1260 Cond = DAG.getSetCC(MVT::i1, SUB,
1261 DAG.getConstant(High-Low, VT), ISD::SETULE);
1266 // Set NextBlock to be the MBB immediately after the current one, if any.
1267 // This is used to avoid emitting unnecessary branches to the next block.
1268 MachineBasicBlock *NextBlock = 0;
1269 MachineFunction::iterator BBI = CurMBB;
1270 if (++BBI != CurMBB->getParent()->end())
1273 // If the lhs block is the next block, invert the condition so that we can
1274 // fall through to the lhs instead of the rhs block.
1275 if (CB.TrueBB == NextBlock) {
1276 std::swap(CB.TrueBB, CB.FalseBB);
1277 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1278 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1280 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1281 DAG.getBasicBlock(CB.TrueBB));
1282 if (CB.FalseBB == NextBlock)
1283 DAG.setRoot(BrCond);
1285 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1286 DAG.getBasicBlock(CB.FalseBB)));
1287 // Update successor info
1288 CurMBB->addSuccessor(CB.TrueBB);
1289 CurMBB->addSuccessor(CB.FalseBB);
1292 /// visitJumpTable - Emit JumpTable node in the current MBB
1293 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1294 // Emit the code for the jump table
1295 assert(JT.Reg != -1U && "Should lower JT Header first!");
1296 MVT::ValueType PTy = TLI.getPointerTy();
1297 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1298 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1299 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1304 /// visitJumpTableHeader - This function emits necessary code to produce index
1305 /// in the JumpTable from switch case.
1306 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1307 SelectionDAGISel::JumpTableHeader &JTH) {
1308 // Subtract the lowest switch case value from the value being switched on
1309 // and conditional branch to default mbb if the result is greater than the
1310 // difference between smallest and largest cases.
1311 SDOperand SwitchOp = getValue(JTH.SValue);
1312 MVT::ValueType VT = SwitchOp.getValueType();
1313 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1314 DAG.getConstant(JTH.First, VT));
1316 // The SDNode we just created, which holds the value being switched on
1317 // minus the the smallest case value, needs to be copied to a virtual
1318 // register so it can be used as an index into the jump table in a
1319 // subsequent basic block. This value may be smaller or larger than the
1320 // target's pointer type, and therefore require extension or truncating.
1321 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1322 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1324 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1326 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1327 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1328 JT.Reg = JumpTableReg;
1330 // Emit the range check for the jump table, and branch to the default
1331 // block for the switch statement if the value being switched on exceeds
1332 // the largest case in the switch.
1333 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1334 DAG.getConstant(JTH.Last-JTH.First,VT),
1337 // Set NextBlock to be the MBB immediately after the current one, if any.
1338 // This is used to avoid emitting unnecessary branches to the next block.
1339 MachineBasicBlock *NextBlock = 0;
1340 MachineFunction::iterator BBI = CurMBB;
1341 if (++BBI != CurMBB->getParent()->end())
1344 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1345 DAG.getBasicBlock(JT.Default));
1347 if (JT.MBB == NextBlock)
1348 DAG.setRoot(BrCond);
1350 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1351 DAG.getBasicBlock(JT.MBB)));
1356 /// visitBitTestHeader - This function emits necessary code to produce value
1357 /// suitable for "bit tests"
1358 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1359 // Subtract the minimum value
1360 SDOperand SwitchOp = getValue(B.SValue);
1361 MVT::ValueType VT = SwitchOp.getValueType();
1362 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1363 DAG.getConstant(B.First, VT));
1366 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1367 DAG.getConstant(B.Range, VT),
1371 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1372 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1374 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1376 // Make desired shift
1377 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1378 DAG.getConstant(1, TLI.getPointerTy()),
1381 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1382 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1385 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1386 DAG.getBasicBlock(B.Default));
1388 // Set NextBlock to be the MBB immediately after the current one, if any.
1389 // This is used to avoid emitting unnecessary branches to the next block.
1390 MachineBasicBlock *NextBlock = 0;
1391 MachineFunction::iterator BBI = CurMBB;
1392 if (++BBI != CurMBB->getParent()->end())
1395 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1396 if (MBB == NextBlock)
1397 DAG.setRoot(BrRange);
1399 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1400 DAG.getBasicBlock(MBB)));
1402 CurMBB->addSuccessor(B.Default);
1403 CurMBB->addSuccessor(MBB);
1408 /// visitBitTestCase - this function produces one "bit test"
1409 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1411 SelectionDAGISel::BitTestCase &B) {
1412 // Emit bit tests and jumps
1413 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1415 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1417 DAG.getConstant(B.Mask,
1418 TLI.getPointerTy()));
1419 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1420 DAG.getConstant(0, TLI.getPointerTy()),
1422 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1423 AndCmp, DAG.getBasicBlock(B.TargetBB));
1425 // Set NextBlock to be the MBB immediately after the current one, if any.
1426 // This is used to avoid emitting unnecessary branches to the next block.
1427 MachineBasicBlock *NextBlock = 0;
1428 MachineFunction::iterator BBI = CurMBB;
1429 if (++BBI != CurMBB->getParent()->end())
1432 if (NextMBB == NextBlock)
1435 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1436 DAG.getBasicBlock(NextMBB)));
1438 CurMBB->addSuccessor(B.TargetBB);
1439 CurMBB->addSuccessor(NextMBB);
1444 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1445 // Retrieve successors.
1446 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1447 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1449 if (isa<InlineAsm>(I.getCalledValue()))
1452 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1454 // If the value of the invoke is used outside of its defining block, make it
1455 // available as a virtual register.
1456 if (!I.use_empty()) {
1457 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1458 if (VMI != FuncInfo.ValueMap.end())
1459 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
1462 // Drop into normal successor.
1463 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1464 DAG.getBasicBlock(Return)));
1466 // Update successor info
1467 CurMBB->addSuccessor(Return);
1468 CurMBB->addSuccessor(LandingPad);
1471 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1474 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1475 /// small case ranges).
1476 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1477 CaseRecVector& WorkList,
1479 MachineBasicBlock* Default) {
1480 Case& BackCase = *(CR.Range.second-1);
1482 // Size is the number of Cases represented by this range.
1483 unsigned Size = CR.Range.second - CR.Range.first;
1487 // Get the MachineFunction which holds the current MBB. This is used when
1488 // inserting any additional MBBs necessary to represent the switch.
1489 MachineFunction *CurMF = CurMBB->getParent();
1491 // Figure out which block is immediately after the current one.
1492 MachineBasicBlock *NextBlock = 0;
1493 MachineFunction::iterator BBI = CR.CaseBB;
1495 if (++BBI != CurMBB->getParent()->end())
1498 // TODO: If any two of the cases has the same destination, and if one value
1499 // is the same as the other, but has one bit unset that the other has set,
1500 // use bit manipulation to do two compares at once. For example:
1501 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1503 // Rearrange the case blocks so that the last one falls through if possible.
1504 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1505 // The last case block won't fall through into 'NextBlock' if we emit the
1506 // branches in this order. See if rearranging a case value would help.
1507 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1508 if (I->BB == NextBlock) {
1509 std::swap(*I, BackCase);
1515 // Create a CaseBlock record representing a conditional branch to
1516 // the Case's target mbb if the value being switched on SV is equal
1518 MachineBasicBlock *CurBlock = CR.CaseBB;
1519 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1520 MachineBasicBlock *FallThrough;
1522 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1523 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1525 // If the last case doesn't match, go to the default block.
1526 FallThrough = Default;
1529 Value *RHS, *LHS, *MHS;
1531 if (I->High == I->Low) {
1532 // This is just small small case range :) containing exactly 1 case
1534 LHS = SV; RHS = I->High; MHS = NULL;
1537 LHS = I->Low; MHS = SV; RHS = I->High;
1539 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1540 I->BB, FallThrough, CurBlock);
1542 // If emitting the first comparison, just call visitSwitchCase to emit the
1543 // code into the current block. Otherwise, push the CaseBlock onto the
1544 // vector to be later processed by SDISel, and insert the node's MBB
1545 // before the next MBB.
1546 if (CurBlock == CurMBB)
1547 visitSwitchCase(CB);
1549 SwitchCases.push_back(CB);
1551 CurBlock = FallThrough;
1557 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1558 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1559 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1562 /// handleJTSwitchCase - Emit jumptable for current switch case range
1563 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1564 CaseRecVector& WorkList,
1566 MachineBasicBlock* Default) {
1567 Case& FrontCase = *CR.Range.first;
1568 Case& BackCase = *(CR.Range.second-1);
1570 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1571 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1574 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1578 if (!areJTsAllowed(TLI) || TSize <= 3)
1581 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1585 DOUT << "Lowering jump table\n"
1586 << "First entry: " << First << ". Last entry: " << Last << "\n"
1587 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1589 // Get the MachineFunction which holds the current MBB. This is used when
1590 // inserting any additional MBBs necessary to represent the switch.
1591 MachineFunction *CurMF = CurMBB->getParent();
1593 // Figure out which block is immediately after the current one.
1594 MachineBasicBlock *NextBlock = 0;
1595 MachineFunction::iterator BBI = CR.CaseBB;
1597 if (++BBI != CurMBB->getParent()->end())
1600 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1602 // Create a new basic block to hold the code for loading the address
1603 // of the jump table, and jumping to it. Update successor information;
1604 // we will either branch to the default case for the switch, or the jump
1606 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1607 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1608 CR.CaseBB->addSuccessor(Default);
1609 CR.CaseBB->addSuccessor(JumpTableBB);
1611 // Build a vector of destination BBs, corresponding to each target
1612 // of the jump table. If the value of the jump table slot corresponds to
1613 // a case statement, push the case's BB onto the vector, otherwise, push
1615 std::vector<MachineBasicBlock*> DestBBs;
1616 int64_t TEI = First;
1617 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1618 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1619 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1621 if ((Low <= TEI) && (TEI <= High)) {
1622 DestBBs.push_back(I->BB);
1626 DestBBs.push_back(Default);
1630 // Update successor info. Add one edge to each unique successor.
1631 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1632 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1633 E = DestBBs.end(); I != E; ++I) {
1634 if (!SuccsHandled[(*I)->getNumber()]) {
1635 SuccsHandled[(*I)->getNumber()] = true;
1636 JumpTableBB->addSuccessor(*I);
1640 // Create a jump table index for this jump table, or return an existing
1642 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1644 // Set the jump table information so that we can codegen it as a second
1645 // MachineBasicBlock
1646 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1647 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1648 (CR.CaseBB == CurMBB));
1649 if (CR.CaseBB == CurMBB)
1650 visitJumpTableHeader(JT, JTH);
1652 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1657 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1659 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1660 CaseRecVector& WorkList,
1662 MachineBasicBlock* Default) {
1663 // Get the MachineFunction which holds the current MBB. This is used when
1664 // inserting any additional MBBs necessary to represent the switch.
1665 MachineFunction *CurMF = CurMBB->getParent();
1667 // Figure out which block is immediately after the current one.
1668 MachineBasicBlock *NextBlock = 0;
1669 MachineFunction::iterator BBI = CR.CaseBB;
1671 if (++BBI != CurMBB->getParent()->end())
1674 Case& FrontCase = *CR.Range.first;
1675 Case& BackCase = *(CR.Range.second-1);
1676 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1678 // Size is the number of Cases represented by this range.
1679 unsigned Size = CR.Range.second - CR.Range.first;
1681 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1682 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1684 CaseItr Pivot = CR.Range.first + Size/2;
1686 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1687 // (heuristically) allow us to emit JumpTable's later.
1689 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1693 uint64_t LSize = FrontCase.size();
1694 uint64_t RSize = TSize-LSize;
1695 DOUT << "Selecting best pivot: \n"
1696 << "First: " << First << ", Last: " << Last <<"\n"
1697 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1698 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1700 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1701 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1702 assert((RBegin-LEnd>=1) && "Invalid case distance");
1703 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1704 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1705 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1706 // Should always split in some non-trivial place
1708 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1709 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1710 << "Metric: " << Metric << "\n";
1711 if (FMetric < Metric) {
1714 DOUT << "Current metric set to: " << FMetric << "\n";
1720 if (areJTsAllowed(TLI)) {
1721 // If our case is dense we *really* should handle it earlier!
1722 assert((FMetric > 0) && "Should handle dense range earlier!");
1724 Pivot = CR.Range.first + Size/2;
1727 CaseRange LHSR(CR.Range.first, Pivot);
1728 CaseRange RHSR(Pivot, CR.Range.second);
1729 Constant *C = Pivot->Low;
1730 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1732 // We know that we branch to the LHS if the Value being switched on is
1733 // less than the Pivot value, C. We use this to optimize our binary
1734 // tree a bit, by recognizing that if SV is greater than or equal to the
1735 // LHS's Case Value, and that Case Value is exactly one less than the
1736 // Pivot's Value, then we can branch directly to the LHS's Target,
1737 // rather than creating a leaf node for it.
1738 if ((LHSR.second - LHSR.first) == 1 &&
1739 LHSR.first->High == CR.GE &&
1740 cast<ConstantInt>(C)->getSExtValue() ==
1741 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1742 TrueBB = LHSR.first->BB;
1744 TrueBB = new MachineBasicBlock(LLVMBB);
1745 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1746 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1749 // Similar to the optimization above, if the Value being switched on is
1750 // known to be less than the Constant CR.LT, and the current Case Value
1751 // is CR.LT - 1, then we can branch directly to the target block for
1752 // the current Case Value, rather than emitting a RHS leaf node for it.
1753 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1754 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1755 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1756 FalseBB = RHSR.first->BB;
1758 FalseBB = new MachineBasicBlock(LLVMBB);
1759 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1760 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1763 // Create a CaseBlock record representing a conditional branch to
1764 // the LHS node if the value being switched on SV is less than C.
1765 // Otherwise, branch to LHS.
1766 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1767 TrueBB, FalseBB, CR.CaseBB);
1769 if (CR.CaseBB == CurMBB)
1770 visitSwitchCase(CB);
1772 SwitchCases.push_back(CB);
1777 /// handleBitTestsSwitchCase - if current case range has few destination and
1778 /// range span less, than machine word bitwidth, encode case range into series
1779 /// of masks and emit bit tests with these masks.
1780 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1781 CaseRecVector& WorkList,
1783 MachineBasicBlock* Default){
1784 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
1786 Case& FrontCase = *CR.Range.first;
1787 Case& BackCase = *(CR.Range.second-1);
1789 // Get the MachineFunction which holds the current MBB. This is used when
1790 // inserting any additional MBBs necessary to represent the switch.
1791 MachineFunction *CurMF = CurMBB->getParent();
1793 unsigned numCmps = 0;
1794 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1796 // Single case counts one, case range - two.
1797 if (I->Low == I->High)
1803 // Count unique destinations
1804 SmallSet<MachineBasicBlock*, 4> Dests;
1805 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1806 Dests.insert(I->BB);
1807 if (Dests.size() > 3)
1808 // Don't bother the code below, if there are too much unique destinations
1811 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1812 << "Total number of comparisons: " << numCmps << "\n";
1814 // Compute span of values.
1815 Constant* minValue = FrontCase.Low;
1816 Constant* maxValue = BackCase.High;
1817 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1818 cast<ConstantInt>(minValue)->getSExtValue();
1819 DOUT << "Compare range: " << range << "\n"
1820 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1821 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1823 if (range>=IntPtrBits ||
1824 (!(Dests.size() == 1 && numCmps >= 3) &&
1825 !(Dests.size() == 2 && numCmps >= 5) &&
1826 !(Dests.size() >= 3 && numCmps >= 6)))
1829 DOUT << "Emitting bit tests\n";
1830 int64_t lowBound = 0;
1832 // Optimize the case where all the case values fit in a
1833 // word without having to subtract minValue. In this case,
1834 // we can optimize away the subtraction.
1835 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1836 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1837 range = cast<ConstantInt>(maxValue)->getSExtValue();
1839 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1842 CaseBitsVector CasesBits;
1843 unsigned i, count = 0;
1845 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1846 MachineBasicBlock* Dest = I->BB;
1847 for (i = 0; i < count; ++i)
1848 if (Dest == CasesBits[i].BB)
1852 assert((count < 3) && "Too much destinations to test!");
1853 CasesBits.push_back(CaseBits(0, Dest, 0));
1857 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1858 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1860 for (uint64_t j = lo; j <= hi; j++) {
1861 CasesBits[i].Mask |= 1ULL << j;
1862 CasesBits[i].Bits++;
1866 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1868 SelectionDAGISel::BitTestInfo BTC;
1870 // Figure out which block is immediately after the current one.
1871 MachineFunction::iterator BBI = CR.CaseBB;
1874 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1877 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1878 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1879 << ", BB: " << CasesBits[i].BB << "\n";
1881 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1882 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1883 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1888 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
1889 -1U, (CR.CaseBB == CurMBB),
1890 CR.CaseBB, Default, BTC);
1892 if (CR.CaseBB == CurMBB)
1893 visitBitTestHeader(BTB);
1895 BitTestCases.push_back(BTB);
1901 // Clusterify - Transform simple list of Cases into list of CaseRange's
1902 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1903 const SwitchInst& SI) {
1904 unsigned numCmps = 0;
1906 // Start with "simple" cases
1907 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1908 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1909 Cases.push_back(Case(SI.getSuccessorValue(i),
1910 SI.getSuccessorValue(i),
1913 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1915 // Merge case into clusters
1916 if (Cases.size()>=2)
1917 // Must recompute end() each iteration because it may be
1918 // invalidated by erase if we hold on to it
1919 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
1920 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1921 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1922 MachineBasicBlock* nextBB = J->BB;
1923 MachineBasicBlock* currentBB = I->BB;
1925 // If the two neighboring cases go to the same destination, merge them
1926 // into a single case.
1927 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1935 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1936 if (I->Low != I->High)
1937 // A range counts double, since it requires two compares.
1944 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
1945 // Figure out which block is immediately after the current one.
1946 MachineBasicBlock *NextBlock = 0;
1947 MachineFunction::iterator BBI = CurMBB;
1949 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1951 // If there is only the default destination, branch to it if it is not the
1952 // next basic block. Otherwise, just fall through.
1953 if (SI.getNumOperands() == 2) {
1954 // Update machine-CFG edges.
1956 // If this is not a fall-through branch, emit the branch.
1957 if (Default != NextBlock)
1958 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1959 DAG.getBasicBlock(Default)));
1961 CurMBB->addSuccessor(Default);
1965 // If there are any non-default case statements, create a vector of Cases
1966 // representing each one, and sort the vector so that we can efficiently
1967 // create a binary search tree from them.
1969 unsigned numCmps = Clusterify(Cases, SI);
1970 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
1971 << ". Total compares: " << numCmps << "\n";
1973 // Get the Value to be switched on and default basic blocks, which will be
1974 // inserted into CaseBlock records, representing basic blocks in the binary
1976 Value *SV = SI.getOperand(0);
1978 // Push the initial CaseRec onto the worklist
1979 CaseRecVector WorkList;
1980 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1982 while (!WorkList.empty()) {
1983 // Grab a record representing a case range to process off the worklist
1984 CaseRec CR = WorkList.back();
1985 WorkList.pop_back();
1987 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
1990 // If the range has few cases (two or less) emit a series of specific
1992 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
1995 // If the switch has more than 5 blocks, and at least 40% dense, and the
1996 // target supports indirect branches, then emit a jump table rather than
1997 // lowering the switch to a binary tree of conditional branches.
1998 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2001 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2002 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2003 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2008 void SelectionDAGLowering::visitSub(User &I) {
2009 // -0.0 - X --> fneg
2010 const Type *Ty = I.getType();
2011 if (isa<VectorType>(Ty)) {
2012 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2013 const VectorType *DestTy = cast<VectorType>(I.getType());
2014 const Type *ElTy = DestTy->getElementType();
2015 if (ElTy->isFloatingPoint()) {
2016 unsigned VL = DestTy->getNumElements();
2017 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2018 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2020 SDOperand Op2 = getValue(I.getOperand(1));
2021 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2027 if (Ty->isFloatingPoint()) {
2028 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2029 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2030 SDOperand Op2 = getValue(I.getOperand(1));
2031 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2036 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2039 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2040 SDOperand Op1 = getValue(I.getOperand(0));
2041 SDOperand Op2 = getValue(I.getOperand(1));
2043 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2046 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2047 SDOperand Op1 = getValue(I.getOperand(0));
2048 SDOperand Op2 = getValue(I.getOperand(1));
2050 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2051 MVT::getSizeInBits(Op2.getValueType()))
2052 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2053 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2054 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2056 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2059 void SelectionDAGLowering::visitICmp(User &I) {
2060 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2061 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2062 predicate = IC->getPredicate();
2063 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2064 predicate = ICmpInst::Predicate(IC->getPredicate());
2065 SDOperand Op1 = getValue(I.getOperand(0));
2066 SDOperand Op2 = getValue(I.getOperand(1));
2067 ISD::CondCode Opcode;
2068 switch (predicate) {
2069 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2070 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2071 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2072 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2073 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2074 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2075 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2076 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2077 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2078 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2080 assert(!"Invalid ICmp predicate value");
2081 Opcode = ISD::SETEQ;
2084 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2087 void SelectionDAGLowering::visitFCmp(User &I) {
2088 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2089 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2090 predicate = FC->getPredicate();
2091 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2092 predicate = FCmpInst::Predicate(FC->getPredicate());
2093 SDOperand Op1 = getValue(I.getOperand(0));
2094 SDOperand Op2 = getValue(I.getOperand(1));
2095 ISD::CondCode Condition, FOC, FPC;
2096 switch (predicate) {
2097 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2098 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2099 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2100 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2101 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2102 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2103 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2104 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2105 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2106 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2107 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2108 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2109 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2110 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2111 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2112 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2114 assert(!"Invalid FCmp predicate value");
2115 FOC = FPC = ISD::SETFALSE;
2118 if (FiniteOnlyFPMath())
2122 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2125 void SelectionDAGLowering::visitSelect(User &I) {
2126 SDOperand Cond = getValue(I.getOperand(0));
2127 SDOperand TrueVal = getValue(I.getOperand(1));
2128 SDOperand FalseVal = getValue(I.getOperand(2));
2129 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2130 TrueVal, FalseVal));
2134 void SelectionDAGLowering::visitTrunc(User &I) {
2135 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2136 SDOperand N = getValue(I.getOperand(0));
2137 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2138 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2141 void SelectionDAGLowering::visitZExt(User &I) {
2142 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2143 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2144 SDOperand N = getValue(I.getOperand(0));
2145 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2146 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2149 void SelectionDAGLowering::visitSExt(User &I) {
2150 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2151 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2152 SDOperand N = getValue(I.getOperand(0));
2153 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2154 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2157 void SelectionDAGLowering::visitFPTrunc(User &I) {
2158 // FPTrunc is never a no-op cast, no need to check
2159 SDOperand N = getValue(I.getOperand(0));
2160 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2161 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2164 void SelectionDAGLowering::visitFPExt(User &I){
2165 // FPTrunc is never a no-op cast, no need to check
2166 SDOperand N = getValue(I.getOperand(0));
2167 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2168 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2171 void SelectionDAGLowering::visitFPToUI(User &I) {
2172 // FPToUI is never a no-op cast, no need to check
2173 SDOperand N = getValue(I.getOperand(0));
2174 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2175 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2178 void SelectionDAGLowering::visitFPToSI(User &I) {
2179 // FPToSI is never a no-op cast, no need to check
2180 SDOperand N = getValue(I.getOperand(0));
2181 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2182 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2185 void SelectionDAGLowering::visitUIToFP(User &I) {
2186 // UIToFP is never a no-op cast, no need to check
2187 SDOperand N = getValue(I.getOperand(0));
2188 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2189 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2192 void SelectionDAGLowering::visitSIToFP(User &I){
2193 // UIToFP is never a no-op cast, no need to check
2194 SDOperand N = getValue(I.getOperand(0));
2195 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2196 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2199 void SelectionDAGLowering::visitPtrToInt(User &I) {
2200 // What to do depends on the size of the integer and the size of the pointer.
2201 // We can either truncate, zero extend, or no-op, accordingly.
2202 SDOperand N = getValue(I.getOperand(0));
2203 MVT::ValueType SrcVT = N.getValueType();
2204 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2206 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2207 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2209 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2210 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2211 setValue(&I, Result);
2214 void SelectionDAGLowering::visitIntToPtr(User &I) {
2215 // What to do depends on the size of the integer and the size of the pointer.
2216 // We can either truncate, zero extend, or no-op, accordingly.
2217 SDOperand N = getValue(I.getOperand(0));
2218 MVT::ValueType SrcVT = N.getValueType();
2219 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2220 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2221 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2223 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2224 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2227 void SelectionDAGLowering::visitBitCast(User &I) {
2228 SDOperand N = getValue(I.getOperand(0));
2229 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2231 // BitCast assures us that source and destination are the same size so this
2232 // is either a BIT_CONVERT or a no-op.
2233 if (DestVT != N.getValueType())
2234 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2236 setValue(&I, N); // noop cast.
2239 void SelectionDAGLowering::visitInsertElement(User &I) {
2240 SDOperand InVec = getValue(I.getOperand(0));
2241 SDOperand InVal = getValue(I.getOperand(1));
2242 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2243 getValue(I.getOperand(2)));
2245 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2246 TLI.getValueType(I.getType()),
2247 InVec, InVal, InIdx));
2250 void SelectionDAGLowering::visitExtractElement(User &I) {
2251 SDOperand InVec = getValue(I.getOperand(0));
2252 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2253 getValue(I.getOperand(1)));
2254 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2255 TLI.getValueType(I.getType()), InVec, InIdx));
2258 void SelectionDAGLowering::visitShuffleVector(User &I) {
2259 SDOperand V1 = getValue(I.getOperand(0));
2260 SDOperand V2 = getValue(I.getOperand(1));
2261 SDOperand Mask = getValue(I.getOperand(2));
2263 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2264 TLI.getValueType(I.getType()),
2269 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2270 SDOperand N = getValue(I.getOperand(0));
2271 const Type *Ty = I.getOperand(0)->getType();
2273 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2276 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2277 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2280 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2281 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2282 DAG.getIntPtrConstant(Offset));
2284 Ty = StTy->getElementType(Field);
2286 Ty = cast<SequentialType>(Ty)->getElementType();
2288 // If this is a constant subscript, handle it quickly.
2289 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2290 if (CI->getZExtValue() == 0) continue;
2292 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2293 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2294 DAG.getIntPtrConstant(Offs));
2298 // N = N + Idx * ElementSize;
2299 uint64_t ElementSize = TD->getABITypeSize(Ty);
2300 SDOperand IdxN = getValue(Idx);
2302 // If the index is smaller or larger than intptr_t, truncate or extend
2304 if (IdxN.getValueType() < N.getValueType()) {
2305 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2306 } else if (IdxN.getValueType() > N.getValueType())
2307 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2309 // If this is a multiply by a power of two, turn it into a shl
2310 // immediately. This is a very common case.
2311 if (isPowerOf2_64(ElementSize)) {
2312 unsigned Amt = Log2_64(ElementSize);
2313 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2314 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2315 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2319 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2320 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2321 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2327 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2328 // If this is a fixed sized alloca in the entry block of the function,
2329 // allocate it statically on the stack.
2330 if (FuncInfo.StaticAllocaMap.count(&I))
2331 return; // getValue will auto-populate this.
2333 const Type *Ty = I.getAllocatedType();
2334 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2336 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2339 SDOperand AllocSize = getValue(I.getArraySize());
2340 MVT::ValueType IntPtr = TLI.getPointerTy();
2341 if (IntPtr < AllocSize.getValueType())
2342 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2343 else if (IntPtr > AllocSize.getValueType())
2344 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2346 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2347 DAG.getIntPtrConstant(TySize));
2349 // Handle alignment. If the requested alignment is less than or equal to
2350 // the stack alignment, ignore it. If the size is greater than or equal to
2351 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2352 unsigned StackAlign =
2353 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2354 if (Align <= StackAlign)
2357 // Round the size of the allocation up to the stack alignment size
2358 // by add SA-1 to the size.
2359 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2360 DAG.getIntPtrConstant(StackAlign-1));
2361 // Mask out the low bits for alignment purposes.
2362 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2363 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2365 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2366 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2368 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2370 DAG.setRoot(DSA.getValue(1));
2372 // Inform the Frame Information that we have just allocated a variable-sized
2374 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2377 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2378 SDOperand Ptr = getValue(I.getOperand(0));
2384 // Do not serialize non-volatile loads against each other.
2385 Root = DAG.getRoot();
2388 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2389 Root, I.isVolatile(), I.getAlignment()));
2392 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2393 const Value *SV, SDOperand Root,
2395 unsigned Alignment) {
2397 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2398 isVolatile, Alignment);
2401 DAG.setRoot(L.getValue(1));
2403 PendingLoads.push_back(L.getValue(1));
2409 void SelectionDAGLowering::visitStore(StoreInst &I) {
2410 Value *SrcV = I.getOperand(0);
2411 SDOperand Src = getValue(SrcV);
2412 SDOperand Ptr = getValue(I.getOperand(1));
2413 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2414 I.isVolatile(), I.getAlignment()));
2417 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2419 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2420 unsigned Intrinsic) {
2421 bool HasChain = !I.doesNotAccessMemory();
2422 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2424 // Build the operand list.
2425 SmallVector<SDOperand, 8> Ops;
2426 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2428 // We don't need to serialize loads against other loads.
2429 Ops.push_back(DAG.getRoot());
2431 Ops.push_back(getRoot());
2435 // Add the intrinsic ID as an integer operand.
2436 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2438 // Add all operands of the call to the operand list.
2439 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2440 SDOperand Op = getValue(I.getOperand(i));
2441 assert(TLI.isTypeLegal(Op.getValueType()) &&
2442 "Intrinsic uses a non-legal type?");
2446 std::vector<MVT::ValueType> VTs;
2447 if (I.getType() != Type::VoidTy) {
2448 MVT::ValueType VT = TLI.getValueType(I.getType());
2449 if (MVT::isVector(VT)) {
2450 const VectorType *DestTy = cast<VectorType>(I.getType());
2451 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2453 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2454 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2457 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2461 VTs.push_back(MVT::Other);
2463 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2468 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2469 &Ops[0], Ops.size());
2470 else if (I.getType() != Type::VoidTy)
2471 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2472 &Ops[0], Ops.size());
2474 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2475 &Ops[0], Ops.size());
2478 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2480 PendingLoads.push_back(Chain);
2484 if (I.getType() != Type::VoidTy) {
2485 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2486 MVT::ValueType VT = TLI.getValueType(PTy);
2487 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2489 setValue(&I, Result);
2493 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2494 static GlobalVariable *ExtractTypeInfo (Value *V) {
2495 V = IntrinsicInst::StripPointerCasts(V);
2496 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2497 assert (GV || isa<ConstantPointerNull>(V) &&
2498 "TypeInfo must be a global variable or NULL");
2502 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2503 /// call, and add them to the specified machine basic block.
2504 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2505 MachineBasicBlock *MBB) {
2506 // Inform the MachineModuleInfo of the personality for this landing pad.
2507 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2508 assert(CE->getOpcode() == Instruction::BitCast &&
2509 isa<Function>(CE->getOperand(0)) &&
2510 "Personality should be a function");
2511 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2513 // Gather all the type infos for this landing pad and pass them along to
2514 // MachineModuleInfo.
2515 std::vector<GlobalVariable *> TyInfo;
2516 unsigned N = I.getNumOperands();
2518 for (unsigned i = N - 1; i > 2; --i) {
2519 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2520 unsigned FilterLength = CI->getZExtValue();
2521 unsigned FirstCatch = i + FilterLength + !FilterLength;
2522 assert (FirstCatch <= N && "Invalid filter length");
2524 if (FirstCatch < N) {
2525 TyInfo.reserve(N - FirstCatch);
2526 for (unsigned j = FirstCatch; j < N; ++j)
2527 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2528 MMI->addCatchTypeInfo(MBB, TyInfo);
2532 if (!FilterLength) {
2534 MMI->addCleanup(MBB);
2537 TyInfo.reserve(FilterLength - 1);
2538 for (unsigned j = i + 1; j < FirstCatch; ++j)
2539 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2540 MMI->addFilterTypeInfo(MBB, TyInfo);
2549 TyInfo.reserve(N - 3);
2550 for (unsigned j = 3; j < N; ++j)
2551 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2552 MMI->addCatchTypeInfo(MBB, TyInfo);
2556 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2557 /// we want to emit this as a call to a named external function, return the name
2558 /// otherwise lower it and return null.
2560 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2561 switch (Intrinsic) {
2563 // By default, turn this into a target intrinsic node.
2564 visitTargetIntrinsic(I, Intrinsic);
2566 case Intrinsic::vastart: visitVAStart(I); return 0;
2567 case Intrinsic::vaend: visitVAEnd(I); return 0;
2568 case Intrinsic::vacopy: visitVACopy(I); return 0;
2569 case Intrinsic::returnaddress:
2570 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2571 getValue(I.getOperand(1))));
2573 case Intrinsic::frameaddress:
2574 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2575 getValue(I.getOperand(1))));
2577 case Intrinsic::setjmp:
2578 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2580 case Intrinsic::longjmp:
2581 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2583 case Intrinsic::memcpy_i32:
2584 case Intrinsic::memcpy_i64:
2585 visitMemIntrinsic(I, ISD::MEMCPY);
2587 case Intrinsic::memset_i32:
2588 case Intrinsic::memset_i64:
2589 visitMemIntrinsic(I, ISD::MEMSET);
2591 case Intrinsic::memmove_i32:
2592 case Intrinsic::memmove_i64:
2593 visitMemIntrinsic(I, ISD::MEMMOVE);
2596 case Intrinsic::dbg_stoppoint: {
2597 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2598 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2599 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2603 Ops[1] = getValue(SPI.getLineValue());
2604 Ops[2] = getValue(SPI.getColumnValue());
2606 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2607 assert(DD && "Not a debug information descriptor");
2608 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2610 Ops[3] = DAG.getString(CompileUnit->getFileName());
2611 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2613 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2618 case Intrinsic::dbg_region_start: {
2619 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2620 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2621 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2622 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2623 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2624 DAG.getConstant(LabelID, MVT::i32),
2625 DAG.getConstant(0, MVT::i32)));
2630 case Intrinsic::dbg_region_end: {
2631 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2632 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2633 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2634 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2635 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2636 DAG.getConstant(LabelID, MVT::i32),
2637 DAG.getConstant(0, MVT::i32)));
2642 case Intrinsic::dbg_func_start: {
2643 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2645 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2646 Value *SP = FSI.getSubprogram();
2647 if (SP && MMI->Verify(SP)) {
2648 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
2649 // what (most?) gdb expects.
2650 DebugInfoDesc *DD = MMI->getDescFor(SP);
2651 assert(DD && "Not a debug information descriptor");
2652 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
2653 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
2654 unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(),
2655 CompileUnit->getFileName());
2656 // Record the source line but does create a label. It will be emitted
2657 // at asm emission time.
2658 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
2663 case Intrinsic::dbg_declare: {
2664 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2665 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2666 Value *Variable = DI.getVariable();
2667 if (MMI && Variable && MMI->Verify(Variable))
2668 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
2669 getValue(DI.getAddress()), getValue(Variable)));
2673 case Intrinsic::eh_exception: {
2674 if (ExceptionHandling) {
2675 if (!CurMBB->isLandingPad()) {
2676 // FIXME: Mark exception register as live in. Hack for PR1508.
2677 unsigned Reg = TLI.getExceptionAddressRegister();
2678 if (Reg) CurMBB->addLiveIn(Reg);
2680 // Insert the EXCEPTIONADDR instruction.
2681 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2683 Ops[0] = DAG.getRoot();
2684 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2686 DAG.setRoot(Op.getValue(1));
2688 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2693 case Intrinsic::eh_selector_i32:
2694 case Intrinsic::eh_selector_i64: {
2695 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2696 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
2697 MVT::i32 : MVT::i64);
2699 if (ExceptionHandling && MMI) {
2700 if (CurMBB->isLandingPad())
2701 addCatchInfo(I, MMI, CurMBB);
2704 FuncInfo.CatchInfoLost.insert(&I);
2706 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2707 unsigned Reg = TLI.getExceptionSelectorRegister();
2708 if (Reg) CurMBB->addLiveIn(Reg);
2711 // Insert the EHSELECTION instruction.
2712 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
2714 Ops[0] = getValue(I.getOperand(1));
2716 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2718 DAG.setRoot(Op.getValue(1));
2720 setValue(&I, DAG.getConstant(0, VT));
2726 case Intrinsic::eh_typeid_for_i32:
2727 case Intrinsic::eh_typeid_for_i64: {
2728 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2729 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
2730 MVT::i32 : MVT::i64);
2733 // Find the type id for the given typeinfo.
2734 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2736 unsigned TypeID = MMI->getTypeIDFor(GV);
2737 setValue(&I, DAG.getConstant(TypeID, VT));
2739 // Return something different to eh_selector.
2740 setValue(&I, DAG.getConstant(1, VT));
2746 case Intrinsic::eh_return: {
2747 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2749 if (MMI && ExceptionHandling) {
2750 MMI->setCallsEHReturn(true);
2751 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2754 getValue(I.getOperand(1)),
2755 getValue(I.getOperand(2))));
2757 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2763 case Intrinsic::eh_unwind_init: {
2764 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2765 MMI->setCallsUnwindInit(true);
2771 case Intrinsic::eh_dwarf_cfa: {
2772 if (ExceptionHandling) {
2773 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2775 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
2776 CfaArg = DAG.getNode(ISD::TRUNCATE,
2777 TLI.getPointerTy(), getValue(I.getOperand(1)));
2779 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
2780 TLI.getPointerTy(), getValue(I.getOperand(1)));
2782 SDOperand Offset = DAG.getNode(ISD::ADD,
2784 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2785 TLI.getPointerTy()),
2787 setValue(&I, DAG.getNode(ISD::ADD,
2789 DAG.getNode(ISD::FRAMEADDR,
2792 TLI.getPointerTy())),
2795 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2801 case Intrinsic::sqrt:
2802 setValue(&I, DAG.getNode(ISD::FSQRT,
2803 getValue(I.getOperand(1)).getValueType(),
2804 getValue(I.getOperand(1))));
2806 case Intrinsic::powi:
2807 setValue(&I, DAG.getNode(ISD::FPOWI,
2808 getValue(I.getOperand(1)).getValueType(),
2809 getValue(I.getOperand(1)),
2810 getValue(I.getOperand(2))));
2812 case Intrinsic::sin:
2813 setValue(&I, DAG.getNode(ISD::FSIN,
2814 getValue(I.getOperand(1)).getValueType(),
2815 getValue(I.getOperand(1))));
2817 case Intrinsic::cos:
2818 setValue(&I, DAG.getNode(ISD::FCOS,
2819 getValue(I.getOperand(1)).getValueType(),
2820 getValue(I.getOperand(1))));
2822 case Intrinsic::pow:
2823 setValue(&I, DAG.getNode(ISD::FPOW,
2824 getValue(I.getOperand(1)).getValueType(),
2825 getValue(I.getOperand(1)),
2826 getValue(I.getOperand(2))));
2828 case Intrinsic::pcmarker: {
2829 SDOperand Tmp = getValue(I.getOperand(1));
2830 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2833 case Intrinsic::readcyclecounter: {
2834 SDOperand Op = getRoot();
2835 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2836 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2839 DAG.setRoot(Tmp.getValue(1));
2842 case Intrinsic::part_select: {
2843 // Currently not implemented: just abort
2844 assert(0 && "part_select intrinsic not implemented");
2847 case Intrinsic::part_set: {
2848 // Currently not implemented: just abort
2849 assert(0 && "part_set intrinsic not implemented");
2852 case Intrinsic::bswap:
2853 setValue(&I, DAG.getNode(ISD::BSWAP,
2854 getValue(I.getOperand(1)).getValueType(),
2855 getValue(I.getOperand(1))));
2857 case Intrinsic::cttz: {
2858 SDOperand Arg = getValue(I.getOperand(1));
2859 MVT::ValueType Ty = Arg.getValueType();
2860 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
2861 setValue(&I, result);
2864 case Intrinsic::ctlz: {
2865 SDOperand Arg = getValue(I.getOperand(1));
2866 MVT::ValueType Ty = Arg.getValueType();
2867 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
2868 setValue(&I, result);
2871 case Intrinsic::ctpop: {
2872 SDOperand Arg = getValue(I.getOperand(1));
2873 MVT::ValueType Ty = Arg.getValueType();
2874 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
2875 setValue(&I, result);
2878 case Intrinsic::stacksave: {
2879 SDOperand Op = getRoot();
2880 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2881 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2883 DAG.setRoot(Tmp.getValue(1));
2886 case Intrinsic::stackrestore: {
2887 SDOperand Tmp = getValue(I.getOperand(1));
2888 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2891 case Intrinsic::prefetch:
2892 // FIXME: Currently discarding prefetches.
2895 case Intrinsic::var_annotation:
2896 // Discard annotate attributes
2899 case Intrinsic::init_trampoline: {
2901 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
2905 Ops[1] = getValue(I.getOperand(1));
2906 Ops[2] = getValue(I.getOperand(2));
2907 Ops[3] = getValue(I.getOperand(3));
2908 Ops[4] = DAG.getSrcValue(I.getOperand(1));
2909 Ops[5] = DAG.getSrcValue(F);
2911 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
2912 DAG.getNodeValueTypes(TLI.getPointerTy(),
2917 DAG.setRoot(Tmp.getValue(1));
2921 case Intrinsic::gcroot:
2923 Value *Alloca = I.getOperand(1);
2924 Constant *TypeMap = cast<Constant>(I.getOperand(2));
2926 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
2927 GCI->addStackRoot(FI->getIndex(), TypeMap);
2931 case Intrinsic::gcread:
2932 case Intrinsic::gcwrite:
2933 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
2936 case Intrinsic::flt_rounds: {
2937 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
2941 case Intrinsic::trap: {
2942 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
2949 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
2951 MachineBasicBlock *LandingPad) {
2952 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2953 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2954 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2955 unsigned BeginLabel = 0, EndLabel = 0;
2957 TargetLowering::ArgListTy Args;
2958 TargetLowering::ArgListEntry Entry;
2959 Args.reserve(CS.arg_size());
2960 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2962 SDOperand ArgNode = getValue(*i);
2963 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
2965 unsigned attrInd = i - CS.arg_begin() + 1;
2966 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
2967 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
2968 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
2969 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
2970 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
2971 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
2972 Args.push_back(Entry);
2975 bool MarkTryRange = LandingPad ||
2976 // C++ requires special handling of 'nounwind' calls.
2977 (CS.doesNotThrow());
2979 if (MarkTryRange && ExceptionHandling && MMI) {
2980 // Insert a label before the invoke call to mark the try range. This can be
2981 // used to detect deletion of the invoke via the MachineModuleInfo.
2982 BeginLabel = MMI->NextLabelID();
2983 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2984 DAG.getConstant(BeginLabel, MVT::i32),
2985 DAG.getConstant(1, MVT::i32)));
2988 std::pair<SDOperand,SDOperand> Result =
2989 TLI.LowerCallTo(getRoot(), CS.getType(),
2990 CS.paramHasAttr(0, ParamAttr::SExt),
2991 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
2993 if (CS.getType() != Type::VoidTy)
2994 setValue(CS.getInstruction(), Result.first);
2995 DAG.setRoot(Result.second);
2997 if (MarkTryRange && ExceptionHandling && MMI) {
2998 // Insert a label at the end of the invoke call to mark the try range. This
2999 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3000 EndLabel = MMI->NextLabelID();
3001 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3002 DAG.getConstant(EndLabel, MVT::i32),
3003 DAG.getConstant(1, MVT::i32)));
3005 // Inform MachineModuleInfo of range.
3006 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3011 void SelectionDAGLowering::visitCall(CallInst &I) {
3012 const char *RenameFn = 0;
3013 if (Function *F = I.getCalledFunction()) {
3014 if (F->isDeclaration()) {
3015 if (unsigned IID = F->getIntrinsicID()) {
3016 RenameFn = visitIntrinsicCall(I, IID);
3022 // Check for well-known libc/libm calls. If the function is internal, it
3023 // can't be a library call.
3024 unsigned NameLen = F->getNameLen();
3025 if (!F->hasInternalLinkage() && NameLen) {
3026 const char *NameStr = F->getNameStart();
3027 if (NameStr[0] == 'c' &&
3028 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3029 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3030 if (I.getNumOperands() == 3 && // Basic sanity checks.
3031 I.getOperand(1)->getType()->isFloatingPoint() &&
3032 I.getType() == I.getOperand(1)->getType() &&
3033 I.getType() == I.getOperand(2)->getType()) {
3034 SDOperand LHS = getValue(I.getOperand(1));
3035 SDOperand RHS = getValue(I.getOperand(2));
3036 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3040 } else if (NameStr[0] == 'f' &&
3041 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3042 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3043 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3044 if (I.getNumOperands() == 2 && // Basic sanity checks.
3045 I.getOperand(1)->getType()->isFloatingPoint() &&
3046 I.getType() == I.getOperand(1)->getType()) {
3047 SDOperand Tmp = getValue(I.getOperand(1));
3048 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3051 } else if (NameStr[0] == 's' &&
3052 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3053 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3054 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3055 if (I.getNumOperands() == 2 && // Basic sanity checks.
3056 I.getOperand(1)->getType()->isFloatingPoint() &&
3057 I.getType() == I.getOperand(1)->getType()) {
3058 SDOperand Tmp = getValue(I.getOperand(1));
3059 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3062 } else if (NameStr[0] == 'c' &&
3063 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3064 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3065 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3066 if (I.getNumOperands() == 2 && // Basic sanity checks.
3067 I.getOperand(1)->getType()->isFloatingPoint() &&
3068 I.getType() == I.getOperand(1)->getType()) {
3069 SDOperand Tmp = getValue(I.getOperand(1));
3070 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3075 } else if (isa<InlineAsm>(I.getOperand(0))) {
3082 Callee = getValue(I.getOperand(0));
3084 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3086 LowerCallTo(&I, Callee, I.isTailCall());
3090 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3091 /// this value and returns the result as a ValueVT value. This uses
3092 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3093 /// If the Flag pointer is NULL, no flag is used.
3094 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3095 SDOperand &Chain, SDOperand *Flag)const{
3096 // Copy the legal parts from the registers.
3097 unsigned NumParts = Regs.size();
3098 SmallVector<SDOperand, 8> Parts(NumParts);
3099 for (unsigned i = 0; i != NumParts; ++i) {
3100 SDOperand Part = Flag ?
3101 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3102 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3103 Chain = Part.getValue(1);
3105 *Flag = Part.getValue(2);
3109 // Assemble the legal parts into the final value.
3110 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3113 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3114 /// specified value into the registers specified by this object. This uses
3115 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3116 /// If the Flag pointer is NULL, no flag is used.
3117 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3118 SDOperand &Chain, SDOperand *Flag) const {
3119 // Get the list of the values's legal parts.
3120 unsigned NumParts = Regs.size();
3121 SmallVector<SDOperand, 8> Parts(NumParts);
3122 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3124 // Copy the parts into the registers.
3125 for (unsigned i = 0; i != NumParts; ++i) {
3126 SDOperand Part = Flag ?
3127 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3128 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3129 Chain = Part.getValue(0);
3131 *Flag = Part.getValue(1);
3135 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3136 /// operand list. This adds the code marker and includes the number of
3137 /// values added into it.
3138 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3139 std::vector<SDOperand> &Ops) const {
3140 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3141 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3142 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3143 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3146 /// isAllocatableRegister - If the specified register is safe to allocate,
3147 /// i.e. it isn't a stack pointer or some other special register, return the
3148 /// register class for the register. Otherwise, return null.
3149 static const TargetRegisterClass *
3150 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3151 const TargetLowering &TLI, const MRegisterInfo *MRI) {
3152 MVT::ValueType FoundVT = MVT::Other;
3153 const TargetRegisterClass *FoundRC = 0;
3154 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
3155 E = MRI->regclass_end(); RCI != E; ++RCI) {
3156 MVT::ValueType ThisVT = MVT::Other;
3158 const TargetRegisterClass *RC = *RCI;
3159 // If none of the the value types for this register class are valid, we
3160 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3161 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3163 if (TLI.isTypeLegal(*I)) {
3164 // If we have already found this register in a different register class,
3165 // choose the one with the largest VT specified. For example, on
3166 // PowerPC, we favor f64 register classes over f32.
3167 if (FoundVT == MVT::Other ||
3168 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3175 if (ThisVT == MVT::Other) continue;
3177 // NOTE: This isn't ideal. In particular, this might allocate the
3178 // frame pointer in functions that need it (due to them not being taken
3179 // out of allocation, because a variable sized allocation hasn't been seen
3180 // yet). This is a slight code pessimization, but should still work.
3181 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3182 E = RC->allocation_order_end(MF); I != E; ++I)
3184 // We found a matching register class. Keep looking at others in case
3185 // we find one with larger registers that this physreg is also in.
3196 /// AsmOperandInfo - This contains information for each constraint that we are
3198 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3199 /// ConstraintCode - This contains the actual string for the code, like "m".
3200 std::string ConstraintCode;
3202 /// ConstraintType - Information about the constraint code, e.g. Register,
3203 /// RegisterClass, Memory, Other, Unknown.
3204 TargetLowering::ConstraintType ConstraintType;
3206 /// CallOperand/CallOperandval - If this is the result output operand or a
3207 /// clobber, this is null, otherwise it is the incoming operand to the
3208 /// CallInst. This gets modified as the asm is processed.
3209 SDOperand CallOperand;
3210 Value *CallOperandVal;
3212 /// ConstraintVT - The ValueType for the operand value.
3213 MVT::ValueType ConstraintVT;
3215 /// AssignedRegs - If this is a register or register class operand, this
3216 /// contains the set of register corresponding to the operand.
3217 RegsForValue AssignedRegs;
3219 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3220 : InlineAsm::ConstraintInfo(info),
3221 ConstraintType(TargetLowering::C_Unknown),
3222 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
3225 void ComputeConstraintToUse(const TargetLowering &TLI);
3227 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3228 /// busy in OutputRegs/InputRegs.
3229 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3230 std::set<unsigned> &OutputRegs,
3231 std::set<unsigned> &InputRegs) const {
3233 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3235 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3238 } // end anon namespace.
3240 /// getConstraintGenerality - Return an integer indicating how general CT is.
3241 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3243 default: assert(0 && "Unknown constraint type!");
3244 case TargetLowering::C_Other:
3245 case TargetLowering::C_Unknown:
3247 case TargetLowering::C_Register:
3249 case TargetLowering::C_RegisterClass:
3251 case TargetLowering::C_Memory:
3256 void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
3257 assert(!Codes.empty() && "Must have at least one constraint");
3259 std::string *Current = &Codes[0];
3260 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
3261 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common.
3262 ConstraintCode = *Current;
3263 ConstraintType = CurType;
3265 unsigned CurGenerality = getConstraintGenerality(CurType);
3267 // If we have multiple constraints, try to pick the most general one ahead
3268 // of time. This isn't a wonderful solution, but handles common cases.
3269 for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
3270 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
3271 unsigned ThisGenerality = getConstraintGenerality(ThisType);
3272 if (ThisGenerality > CurGenerality) {
3273 // This constraint letter is more general than the previous one,
3276 Current = &Codes[j];
3277 CurGenerality = ThisGenerality;
3281 ConstraintCode = *Current;
3282 ConstraintType = CurType;
3285 if (ConstraintCode == "X") {
3286 if (isa<BasicBlock>(CallOperandVal) || isa<ConstantInt>(CallOperandVal))
3288 // This matches anything. Labels and constants we handle elsewhere
3289 // ('X' is the only thing that matches labels). Otherwise, try to
3290 // resolve it to something we know about by looking at the actual
3293 TLI.lowerXConstraint(ConstraintVT, s);
3296 ConstraintType = TLI.getConstraintType(ConstraintCode);
3302 void SelectionDAGLowering::
3303 GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
3304 std::set<unsigned> &OutputRegs,
3305 std::set<unsigned> &InputRegs) {
3306 // Compute whether this value requires an input register, an output register,
3308 bool isOutReg = false;
3309 bool isInReg = false;
3310 switch (OpInfo.Type) {
3311 case InlineAsm::isOutput:
3314 // If this is an early-clobber output, or if there is an input
3315 // constraint that matches this, we need to reserve the input register
3316 // so no other inputs allocate to it.
3317 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3319 case InlineAsm::isInput:
3323 case InlineAsm::isClobber:
3330 MachineFunction &MF = DAG.getMachineFunction();
3331 std::vector<unsigned> Regs;
3333 // If this is a constraint for a single physreg, or a constraint for a
3334 // register class, find it.
3335 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3336 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3337 OpInfo.ConstraintVT);
3339 unsigned NumRegs = 1;
3340 if (OpInfo.ConstraintVT != MVT::Other)
3341 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3342 MVT::ValueType RegVT;
3343 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3346 // If this is a constraint for a specific physical register, like {r17},
3348 if (PhysReg.first) {
3349 if (OpInfo.ConstraintVT == MVT::Other)
3350 ValueVT = *PhysReg.second->vt_begin();
3352 // Get the actual register value type. This is important, because the user
3353 // may have asked for (e.g.) the AX register in i32 type. We need to
3354 // remember that AX is actually i16 to get the right extension.
3355 RegVT = *PhysReg.second->vt_begin();
3357 // This is a explicit reference to a physical register.
3358 Regs.push_back(PhysReg.first);
3360 // If this is an expanded reference, add the rest of the regs to Regs.
3362 TargetRegisterClass::iterator I = PhysReg.second->begin();
3363 TargetRegisterClass::iterator E = PhysReg.second->end();
3364 for (; *I != PhysReg.first; ++I)
3365 assert(I != E && "Didn't find reg!");
3367 // Already added the first reg.
3369 for (; NumRegs; --NumRegs, ++I) {
3370 assert(I != E && "Ran out of registers to allocate!");
3374 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3375 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3379 // Otherwise, if this was a reference to an LLVM register class, create vregs
3380 // for this reference.
3381 std::vector<unsigned> RegClassRegs;
3382 const TargetRegisterClass *RC = PhysReg.second;
3384 // If this is an early clobber or tied register, our regalloc doesn't know
3385 // how to maintain the constraint. If it isn't, go ahead and create vreg
3386 // and let the regalloc do the right thing.
3387 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3388 // If there is some other early clobber and this is an input register,
3389 // then we are forced to pre-allocate the input reg so it doesn't
3390 // conflict with the earlyclobber.
3391 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3392 RegVT = *PhysReg.second->vt_begin();
3394 if (OpInfo.ConstraintVT == MVT::Other)
3397 // Create the appropriate number of virtual registers.
3398 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3399 for (; NumRegs; --NumRegs)
3400 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
3402 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3403 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3407 // Otherwise, we can't allocate it. Let the code below figure out how to
3408 // maintain these constraints.
3409 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3412 // This is a reference to a register class that doesn't directly correspond
3413 // to an LLVM register class. Allocate NumRegs consecutive, available,
3414 // registers from the class.
3415 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3416 OpInfo.ConstraintVT);
3419 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
3420 unsigned NumAllocated = 0;
3421 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3422 unsigned Reg = RegClassRegs[i];
3423 // See if this register is available.
3424 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3425 (isInReg && InputRegs.count(Reg))) { // Already used.
3426 // Make sure we find consecutive registers.
3431 // Check to see if this register is allocatable (i.e. don't give out the
3434 RC = isAllocatableRegister(Reg, MF, TLI, MRI);
3435 if (!RC) { // Couldn't allocate this register.
3436 // Reset NumAllocated to make sure we return consecutive registers.
3442 // Okay, this register is good, we can use it.
3445 // If we allocated enough consecutive registers, succeed.
3446 if (NumAllocated == NumRegs) {
3447 unsigned RegStart = (i-NumAllocated)+1;
3448 unsigned RegEnd = i+1;
3449 // Mark all of the allocated registers used.
3450 for (unsigned i = RegStart; i != RegEnd; ++i)
3451 Regs.push_back(RegClassRegs[i]);
3453 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3454 OpInfo.ConstraintVT);
3455 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3460 // Otherwise, we couldn't allocate enough registers for this.
3465 /// visitInlineAsm - Handle a call to an InlineAsm object.
3467 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
3468 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3470 /// ConstraintOperands - Information about all of the constraints.
3471 std::vector<AsmOperandInfo> ConstraintOperands;
3473 SDOperand Chain = getRoot();
3476 std::set<unsigned> OutputRegs, InputRegs;
3478 // Do a prepass over the constraints, canonicalizing them, and building up the
3479 // ConstraintOperands list.
3480 std::vector<InlineAsm::ConstraintInfo>
3481 ConstraintInfos = IA->ParseConstraints();
3483 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3484 // constraint. If so, we can't let the register allocator allocate any input
3485 // registers, because it will not know to avoid the earlyclobbered output reg.
3486 bool SawEarlyClobber = false;
3488 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3489 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3490 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3491 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3493 MVT::ValueType OpVT = MVT::Other;
3495 // Compute the value type for each operand.
3496 switch (OpInfo.Type) {
3497 case InlineAsm::isOutput:
3498 if (!OpInfo.isIndirect) {
3499 // The return value of the call is this value. As such, there is no
3500 // corresponding argument.
3501 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3502 OpVT = TLI.getValueType(CS.getType());
3504 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3507 case InlineAsm::isInput:
3508 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3510 case InlineAsm::isClobber:
3515 // If this is an input or an indirect output, process the call argument.
3516 // BasicBlocks are labels, currently appearing only in asm's.
3517 if (OpInfo.CallOperandVal) {
3518 if (isa<BasicBlock>(OpInfo.CallOperandVal))
3519 OpInfo.CallOperand =
3520 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(
3521 OpInfo.CallOperandVal)]);
3523 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3524 const Type *OpTy = OpInfo.CallOperandVal->getType();
3525 // If this is an indirect operand, the operand is a pointer to the
3527 if (OpInfo.isIndirect)
3528 OpTy = cast<PointerType>(OpTy)->getElementType();
3530 // If OpTy is not a first-class value, it may be a struct/union that we
3531 // can tile with integers.
3532 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3533 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3541 OpTy = IntegerType::get(BitSize);
3546 OpVT = TLI.getValueType(OpTy, true);
3550 OpInfo.ConstraintVT = OpVT;
3552 // Compute the constraint code and ConstraintType to use.
3553 OpInfo.ComputeConstraintToUse(TLI);
3555 // Keep track of whether we see an earlyclobber.
3556 SawEarlyClobber |= OpInfo.isEarlyClobber;
3558 // If this is a memory input, and if the operand is not indirect, do what we
3559 // need to to provide an address for the memory input.
3560 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3561 !OpInfo.isIndirect) {
3562 assert(OpInfo.Type == InlineAsm::isInput &&
3563 "Can only indirectify direct input operands!");
3565 // Memory operands really want the address of the value. If we don't have
3566 // an indirect input, put it in the constpool if we can, otherwise spill
3567 // it to a stack slot.
3569 // If the operand is a float, integer, or vector constant, spill to a
3570 // constant pool entry to get its address.
3571 Value *OpVal = OpInfo.CallOperandVal;
3572 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3573 isa<ConstantVector>(OpVal)) {
3574 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3575 TLI.getPointerTy());
3577 // Otherwise, create a stack slot and emit a store to it before the
3579 const Type *Ty = OpVal->getType();
3580 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3581 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3582 MachineFunction &MF = DAG.getMachineFunction();
3583 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3584 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3585 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3586 OpInfo.CallOperand = StackSlot;
3589 // There is no longer a Value* corresponding to this operand.
3590 OpInfo.CallOperandVal = 0;
3591 // It is now an indirect operand.
3592 OpInfo.isIndirect = true;
3595 // If this constraint is for a specific register, allocate it before
3597 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3598 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3600 ConstraintInfos.clear();
3603 // Second pass - Loop over all of the operands, assigning virtual or physregs
3604 // to registerclass operands.
3605 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3606 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3608 // C_Register operands have already been allocated, Other/Memory don't need
3610 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3611 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3614 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3615 std::vector<SDOperand> AsmNodeOperands;
3616 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3617 AsmNodeOperands.push_back(
3618 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3621 // Loop over all of the inputs, copying the operand values into the
3622 // appropriate registers and processing the output regs.
3623 RegsForValue RetValRegs;
3625 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3626 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3628 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3629 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3631 switch (OpInfo.Type) {
3632 case InlineAsm::isOutput: {
3633 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3634 OpInfo.ConstraintType != TargetLowering::C_Register) {
3635 // Memory output, or 'other' output (e.g. 'X' constraint).
3636 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3638 // Add information to the INLINEASM node to know about this output.
3639 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3640 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3641 TLI.getPointerTy()));
3642 AsmNodeOperands.push_back(OpInfo.CallOperand);
3646 // Otherwise, this is a register or register class output.
3648 // Copy the output from the appropriate register. Find a register that
3650 if (OpInfo.AssignedRegs.Regs.empty()) {
3651 cerr << "Couldn't allocate output reg for contraint '"
3652 << OpInfo.ConstraintCode << "'!\n";
3656 if (!OpInfo.isIndirect) {
3657 // This is the result value of the call.
3658 assert(RetValRegs.Regs.empty() &&
3659 "Cannot have multiple output constraints yet!");
3660 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3661 RetValRegs = OpInfo.AssignedRegs;
3663 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3664 OpInfo.CallOperandVal));
3667 // Add information to the INLINEASM node to know that this register is
3669 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3673 case InlineAsm::isInput: {
3674 SDOperand InOperandVal = OpInfo.CallOperand;
3676 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3677 // If this is required to match an output register we have already set,
3678 // just use its register.
3679 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3681 // Scan until we find the definition we already emitted of this operand.
3682 // When we find it, create a RegsForValue operand.
3683 unsigned CurOp = 2; // The first operand.
3684 for (; OperandNo; --OperandNo) {
3685 // Advance to the next operand.
3687 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3688 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3689 (NumOps & 7) == 4 /*MEM*/) &&
3690 "Skipped past definitions?");
3691 CurOp += (NumOps>>3)+1;
3695 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3696 if ((NumOps & 7) == 2 /*REGDEF*/) {
3697 // Add NumOps>>3 registers to MatchedRegs.
3698 RegsForValue MatchedRegs;
3699 MatchedRegs.ValueVT = InOperandVal.getValueType();
3700 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3701 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3703 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3704 MatchedRegs.Regs.push_back(Reg);
3707 // Use the produced MatchedRegs object to
3708 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3709 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3712 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3713 assert(0 && "matching constraints for memory operands unimp");
3717 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3718 assert(!OpInfo.isIndirect &&
3719 "Don't know how to handle indirect other inputs yet!");
3721 std::vector<SDOperand> Ops;
3722 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
3725 cerr << "Invalid operand for inline asm constraint '"
3726 << OpInfo.ConstraintCode << "'!\n";
3730 // Add information to the INLINEASM node to know about this input.
3731 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
3732 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3733 TLI.getPointerTy()));
3734 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
3736 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3737 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
3738 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3739 "Memory operands expect pointer values");
3741 // Add information to the INLINEASM node to know about this input.
3742 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3743 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3744 TLI.getPointerTy()));
3745 AsmNodeOperands.push_back(InOperandVal);
3749 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3750 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3751 "Unknown constraint type!");
3752 assert(!OpInfo.isIndirect &&
3753 "Don't know how to handle indirect register inputs yet!");
3755 // Copy the input into the appropriate registers.
3756 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3757 "Couldn't allocate input reg!");
3759 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3761 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3765 case InlineAsm::isClobber: {
3766 // Add the clobbered value to the operand list, so that the register
3767 // allocator is aware that the physreg got clobbered.
3768 if (!OpInfo.AssignedRegs.Regs.empty())
3769 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3776 // Finish up input operands.
3777 AsmNodeOperands[0] = Chain;
3778 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3780 Chain = DAG.getNode(ISD::INLINEASM,
3781 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3782 &AsmNodeOperands[0], AsmNodeOperands.size());
3783 Flag = Chain.getValue(1);
3785 // If this asm returns a register value, copy the result from that register
3786 // and set it as the value of the call.
3787 if (!RetValRegs.Regs.empty()) {
3788 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
3790 // If the result of the inline asm is a vector, it may have the wrong
3791 // width/num elts. Make sure to convert it to the right type with
3793 if (MVT::isVector(Val.getValueType())) {
3794 const VectorType *VTy = cast<VectorType>(CS.getType());
3795 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
3797 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
3800 setValue(CS.getInstruction(), Val);
3803 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3805 // Process indirect outputs, first output all of the flagged copies out of
3807 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
3808 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
3809 Value *Ptr = IndirectStoresToEmit[i].second;
3810 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
3811 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
3814 // Emit the non-flagged stores from the physregs.
3815 SmallVector<SDOperand, 8> OutChains;
3816 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
3817 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
3818 getValue(StoresToEmit[i].second),
3819 StoresToEmit[i].second, 0));
3820 if (!OutChains.empty())
3821 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3822 &OutChains[0], OutChains.size());
3827 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
3828 SDOperand Src = getValue(I.getOperand(0));
3830 MVT::ValueType IntPtr = TLI.getPointerTy();
3832 if (IntPtr < Src.getValueType())
3833 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
3834 else if (IntPtr > Src.getValueType())
3835 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
3837 // Scale the source by the type size.
3838 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
3839 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
3840 Src, DAG.getIntPtrConstant(ElementSize));
3842 TargetLowering::ArgListTy Args;
3843 TargetLowering::ArgListEntry Entry;
3845 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3846 Args.push_back(Entry);
3848 std::pair<SDOperand,SDOperand> Result =
3849 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
3850 DAG.getExternalSymbol("malloc", IntPtr),
3852 setValue(&I, Result.first); // Pointers always fit in registers
3853 DAG.setRoot(Result.second);
3856 void SelectionDAGLowering::visitFree(FreeInst &I) {
3857 TargetLowering::ArgListTy Args;
3858 TargetLowering::ArgListEntry Entry;
3859 Entry.Node = getValue(I.getOperand(0));
3860 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3861 Args.push_back(Entry);
3862 MVT::ValueType IntPtr = TLI.getPointerTy();
3863 std::pair<SDOperand,SDOperand> Result =
3864 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
3865 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
3866 DAG.setRoot(Result.second);
3869 // EmitInstrWithCustomInserter - This method should be implemented by targets
3870 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
3871 // instructions are special in various ways, which require special support to
3872 // insert. The specified MachineInstr is created but not inserted into any
3873 // basic blocks, and the scheduler passes ownership of it to this method.
3874 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3875 MachineBasicBlock *MBB) {
3876 cerr << "If a target marks an instruction with "
3877 << "'usesCustomDAGSchedInserter', it must implement "
3878 << "TargetLowering::EmitInstrWithCustomInserter!\n";
3883 void SelectionDAGLowering::visitVAStart(CallInst &I) {
3884 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
3885 getValue(I.getOperand(1)),
3886 DAG.getSrcValue(I.getOperand(1))));
3889 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
3890 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
3891 getValue(I.getOperand(0)),
3892 DAG.getSrcValue(I.getOperand(0)));
3894 DAG.setRoot(V.getValue(1));
3897 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
3898 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
3899 getValue(I.getOperand(1)),
3900 DAG.getSrcValue(I.getOperand(1))));
3903 void SelectionDAGLowering::visitVACopy(CallInst &I) {
3904 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
3905 getValue(I.getOperand(1)),
3906 getValue(I.getOperand(2)),
3907 DAG.getSrcValue(I.getOperand(1)),
3908 DAG.getSrcValue(I.getOperand(2))));
3911 /// TargetLowering::LowerArguments - This is the default LowerArguments
3912 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
3913 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
3914 /// integrated into SDISel.
3915 std::vector<SDOperand>
3916 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
3917 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
3918 std::vector<SDOperand> Ops;
3919 Ops.push_back(DAG.getRoot());
3920 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
3921 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
3923 // Add one result value for each formal argument.
3924 std::vector<MVT::ValueType> RetVals;
3926 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
3928 MVT::ValueType VT = getValueType(I->getType());
3929 unsigned Flags = ISD::ParamFlags::NoFlagSet;
3930 unsigned OriginalAlignment =
3931 getTargetData()->getABITypeAlignment(I->getType());
3933 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
3934 // that is zero extended!
3935 if (F.paramHasAttr(j, ParamAttr::ZExt))
3936 Flags &= ~(ISD::ParamFlags::SExt);
3937 if (F.paramHasAttr(j, ParamAttr::SExt))
3938 Flags |= ISD::ParamFlags::SExt;
3939 if (F.paramHasAttr(j, ParamAttr::InReg))
3940 Flags |= ISD::ParamFlags::InReg;
3941 if (F.paramHasAttr(j, ParamAttr::StructRet))
3942 Flags |= ISD::ParamFlags::StructReturn;
3943 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
3944 Flags |= ISD::ParamFlags::ByVal;
3945 const PointerType *Ty = cast<PointerType>(I->getType());
3946 const Type *ElementTy = Ty->getElementType();
3947 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy));
3948 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
3949 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs);
3950 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs);
3952 if (F.paramHasAttr(j, ParamAttr::Nest))
3953 Flags |= ISD::ParamFlags::Nest;
3954 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
3956 switch (getTypeAction(VT)) {
3957 default: assert(0 && "Unknown type action!");
3959 RetVals.push_back(VT);
3960 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3963 RetVals.push_back(getTypeToTransformTo(VT));
3964 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3967 // If this is an illegal type, it needs to be broken up to fit into
3969 MVT::ValueType RegisterVT = getRegisterType(VT);
3970 unsigned NumRegs = getNumRegisters(VT);
3971 for (unsigned i = 0; i != NumRegs; ++i) {
3972 RetVals.push_back(RegisterVT);
3973 // if it isn't first piece, alignment must be 1
3975 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
3976 (1 << ISD::ParamFlags::OrigAlignmentOffs);
3977 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3984 RetVals.push_back(MVT::Other);
3987 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
3988 DAG.getNodeValueTypes(RetVals), RetVals.size(),
3989 &Ops[0], Ops.size()).Val;
3990 unsigned NumArgRegs = Result->getNumValues() - 1;
3991 DAG.setRoot(SDOperand(Result, NumArgRegs));
3993 // Set up the return result vector.
3997 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
3999 MVT::ValueType VT = getValueType(I->getType());
4001 switch (getTypeAction(VT)) {
4002 default: assert(0 && "Unknown type action!");
4004 Ops.push_back(SDOperand(Result, i++));
4007 SDOperand Op(Result, i++);
4008 if (MVT::isInteger(VT)) {
4009 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4010 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
4011 DAG.getValueType(VT));
4012 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4013 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
4014 DAG.getValueType(VT));
4015 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
4017 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
4018 Op = DAG.getNode(ISD::FP_ROUND, VT, Op, DAG.getIntPtrConstant(1));
4024 MVT::ValueType PartVT = getRegisterType(VT);
4025 unsigned NumParts = getNumRegisters(VT);
4026 SmallVector<SDOperand, 4> Parts(NumParts);
4027 for (unsigned j = 0; j != NumParts; ++j)
4028 Parts[j] = SDOperand(Result, i++);
4029 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT));
4034 assert(i == NumArgRegs && "Argument register count mismatch!");
4039 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4040 /// implementation, which just inserts an ISD::CALL node, which is later custom
4041 /// lowered by the target to something concrete. FIXME: When all targets are
4042 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4043 std::pair<SDOperand, SDOperand>
4044 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4045 bool RetTyIsSigned, bool isVarArg,
4046 unsigned CallingConv, bool isTailCall,
4048 ArgListTy &Args, SelectionDAG &DAG) {
4049 SmallVector<SDOperand, 32> Ops;
4050 Ops.push_back(Chain); // Op#0 - Chain
4051 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4052 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4053 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4054 Ops.push_back(Callee);
4056 // Handle all of the outgoing arguments.
4057 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4058 MVT::ValueType VT = getValueType(Args[i].Ty);
4059 SDOperand Op = Args[i].Node;
4060 unsigned Flags = ISD::ParamFlags::NoFlagSet;
4061 unsigned OriginalAlignment =
4062 getTargetData()->getABITypeAlignment(Args[i].Ty);
4065 Flags |= ISD::ParamFlags::SExt;
4067 Flags |= ISD::ParamFlags::ZExt;
4068 if (Args[i].isInReg)
4069 Flags |= ISD::ParamFlags::InReg;
4071 Flags |= ISD::ParamFlags::StructReturn;
4072 if (Args[i].isByVal) {
4073 Flags |= ISD::ParamFlags::ByVal;
4074 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4075 const Type *ElementTy = Ty->getElementType();
4076 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy));
4077 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4078 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs);
4079 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs);
4082 Flags |= ISD::ParamFlags::Nest;
4083 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
4085 switch (getTypeAction(VT)) {
4086 default: assert(0 && "Unknown type action!");
4089 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
4092 if (MVT::isInteger(VT)) {
4095 ExtOp = ISD::SIGN_EXTEND;
4096 else if (Args[i].isZExt)
4097 ExtOp = ISD::ZERO_EXTEND;
4099 ExtOp = ISD::ANY_EXTEND;
4100 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
4102 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
4103 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
4106 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
4109 MVT::ValueType PartVT = getRegisterType(VT);
4110 unsigned NumParts = getNumRegisters(VT);
4111 SmallVector<SDOperand, 4> Parts(NumParts);
4112 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT);
4113 for (unsigned i = 0; i != NumParts; ++i) {
4114 // if it isn't first piece, alignment must be 1
4115 unsigned MyFlags = Flags;
4117 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
4118 (1 << ISD::ParamFlags::OrigAlignmentOffs);
4120 Ops.push_back(Parts[i]);
4121 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
4128 // Figure out the result value types.
4129 MVT::ValueType VT = getValueType(RetTy);
4130 MVT::ValueType RegisterVT = getRegisterType(VT);
4131 unsigned NumRegs = getNumRegisters(VT);
4132 SmallVector<MVT::ValueType, 4> RetTys(NumRegs);
4133 for (unsigned i = 0; i != NumRegs; ++i)
4134 RetTys[i] = RegisterVT;
4136 RetTys.push_back(MVT::Other); // Always has a chain.
4138 // Create the CALL node.
4139 SDOperand Res = DAG.getNode(ISD::CALL,
4140 DAG.getVTList(&RetTys[0], NumRegs + 1),
4141 &Ops[0], Ops.size());
4142 Chain = Res.getValue(NumRegs);
4144 // Gather up the call result into a single value.
4145 if (RetTy != Type::VoidTy) {
4146 ISD::NodeType AssertOp = ISD::AssertSext;
4148 AssertOp = ISD::AssertZext;
4149 SmallVector<SDOperand, 4> Results(NumRegs);
4150 for (unsigned i = 0; i != NumRegs; ++i)
4151 Results[i] = Res.getValue(i);
4152 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
4155 return std::make_pair(Res, Chain);
4158 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4159 assert(0 && "LowerOperation not implemented for this target!");
4164 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4165 SelectionDAG &DAG) {
4166 assert(0 && "CustomPromoteOperation not implemented for this target!");
4171 /// getMemsetValue - Vectorized representation of the memset value
4173 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4174 SelectionDAG &DAG) {
4175 MVT::ValueType CurVT = VT;
4176 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4177 uint64_t Val = C->getValue() & 255;
4179 while (CurVT != MVT::i8) {
4180 Val = (Val << Shift) | Val;
4182 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4184 return DAG.getConstant(Val, VT);
4186 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4188 while (CurVT != MVT::i8) {
4190 DAG.getNode(ISD::OR, VT,
4191 DAG.getNode(ISD::SHL, VT, Value,
4192 DAG.getConstant(Shift, MVT::i8)), Value);
4194 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4201 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4202 /// used when a memcpy is turned into a memset when the source is a constant
4204 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4205 SelectionDAG &DAG, TargetLowering &TLI,
4206 std::string &Str, unsigned Offset) {
4208 unsigned MSB = MVT::getSizeInBits(VT) / 8;
4209 if (TLI.isLittleEndian())
4210 Offset = Offset + MSB - 1;
4211 for (unsigned i = 0; i != MSB; ++i) {
4212 Val = (Val << 8) | (unsigned char)Str[Offset];
4213 Offset += TLI.isLittleEndian() ? -1 : 1;
4215 return DAG.getConstant(Val, VT);
4218 /// getMemBasePlusOffset - Returns base and offset node for the
4219 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4220 SelectionDAG &DAG, TargetLowering &TLI) {
4221 MVT::ValueType VT = Base.getValueType();
4222 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4225 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4226 /// to replace the memset / memcpy is below the threshold. It also returns the
4227 /// types of the sequence of memory ops to perform memset / memcpy.
4228 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4229 unsigned Limit, uint64_t Size,
4230 unsigned Align, TargetLowering &TLI) {
4233 if (TLI.allowsUnalignedMemoryAccesses()) {
4236 switch (Align & 7) {
4252 MVT::ValueType LVT = MVT::i64;
4253 while (!TLI.isTypeLegal(LVT))
4254 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4255 assert(MVT::isInteger(LVT));
4260 unsigned NumMemOps = 0;
4262 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4263 while (VTSize > Size) {
4264 VT = (MVT::ValueType)((unsigned)VT - 1);
4267 assert(MVT::isInteger(VT));
4269 if (++NumMemOps > Limit)
4271 MemOps.push_back(VT);
4278 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4279 SDOperand Op1 = getValue(I.getOperand(1));
4280 SDOperand Op2 = getValue(I.getOperand(2));
4281 SDOperand Op3 = getValue(I.getOperand(3));
4282 SDOperand Op4 = getValue(I.getOperand(4));
4283 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4284 if (Align == 0) Align = 1;
4286 // If the source and destination are known to not be aliases, we can
4287 // lower memmove as memcpy.
4288 if (Op == ISD::MEMMOVE) {
4289 uint64_t Size = -1ULL;
4290 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4291 Size = C->getValue();
4292 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4293 AliasAnalysis::NoAlias)
4297 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4298 std::vector<MVT::ValueType> MemOps;
4300 // Expand memset / memcpy to a series of load / store ops
4301 // if the size operand falls below a certain threshold.
4302 SmallVector<SDOperand, 8> OutChains;
4304 default: break; // Do nothing for now.
4306 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4307 Size->getValue(), Align, TLI)) {
4308 unsigned NumMemOps = MemOps.size();
4309 unsigned Offset = 0;
4310 for (unsigned i = 0; i < NumMemOps; i++) {
4311 MVT::ValueType VT = MemOps[i];
4312 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4313 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4314 SDOperand Store = DAG.getStore(getRoot(), Value,
4315 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4316 I.getOperand(1), Offset);
4317 OutChains.push_back(Store);
4324 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4325 Size->getValue(), Align, TLI)) {
4326 unsigned NumMemOps = MemOps.size();
4327 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4328 GlobalAddressSDNode *G = NULL;
4330 bool CopyFromStr = false;
4332 if (Op2.getOpcode() == ISD::GlobalAddress)
4333 G = cast<GlobalAddressSDNode>(Op2);
4334 else if (Op2.getOpcode() == ISD::ADD &&
4335 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4336 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4337 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4338 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4341 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4342 if (GV && GV->isConstant()) {
4343 Str = GV->getStringValue(false);
4351 for (unsigned i = 0; i < NumMemOps; i++) {
4352 MVT::ValueType VT = MemOps[i];
4353 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4354 SDOperand Value, Chain, Store;
4357 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4360 DAG.getStore(Chain, Value,
4361 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4362 I.getOperand(1), DstOff);
4364 Value = DAG.getLoad(VT, getRoot(),
4365 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4366 I.getOperand(2), SrcOff, false, Align);
4367 Chain = Value.getValue(1);
4369 DAG.getStore(Chain, Value,
4370 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4371 I.getOperand(1), DstOff, false, Align);
4373 OutChains.push_back(Store);
4382 if (!OutChains.empty()) {
4383 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4384 &OutChains[0], OutChains.size()));
4389 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1);
4393 assert(0 && "Unknown Op");
4395 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4398 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4401 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4407 //===----------------------------------------------------------------------===//
4408 // SelectionDAGISel code
4409 //===----------------------------------------------------------------------===//
4411 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4412 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4415 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4416 AU.addRequired<AliasAnalysis>();
4417 AU.addRequired<CollectorModuleMetadata>();
4418 AU.setPreservesAll();
4423 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4424 // Get alias analysis for load/store combining.
4425 AA = &getAnalysis<AliasAnalysis>();
4427 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4428 if (MF.getFunction()->hasCollector())
4429 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4432 RegInfo = &MF.getRegInfo();
4433 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4435 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4437 if (ExceptionHandling)
4438 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4439 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4440 // Mark landing pad.
4441 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4443 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4444 SelectBasicBlock(I, MF, FuncInfo);
4446 // Add function live-ins to entry block live-in set.
4447 BasicBlock *EntryBB = &Fn.getEntryBlock();
4448 BB = FuncInfo.MBBMap[EntryBB];
4449 if (!RegInfo->livein_empty())
4450 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4451 E = RegInfo->livein_end(); I != E; ++I)
4452 BB->addLiveIn(I->first);
4455 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4456 "Not all catch info was assigned to a landing pad!");
4462 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4464 SDOperand Op = getValue(V);
4465 assert((Op.getOpcode() != ISD::CopyFromReg ||
4466 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4467 "Copy from a reg to the same reg!");
4469 MVT::ValueType SrcVT = Op.getValueType();
4470 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4471 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4472 SmallVector<SDOperand, 8> Regs(NumRegs);
4473 SmallVector<SDOperand, 8> Chains(NumRegs);
4475 // Copy the value by legal parts into sequential virtual registers.
4476 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4477 for (unsigned i = 0; i != NumRegs; ++i)
4478 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
4479 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4482 void SelectionDAGISel::
4483 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
4484 std::vector<SDOperand> &UnorderedChains) {
4485 // If this is the entry block, emit arguments.
4486 Function &F = *LLVMBB->getParent();
4487 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4488 SDOperand OldRoot = SDL.DAG.getRoot();
4489 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4492 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4494 if (!AI->use_empty()) {
4495 SDL.setValue(AI, Args[a]);
4497 // If this argument is live outside of the entry block, insert a copy from
4498 // whereever we got it to the vreg that other BB's will reference it as.
4499 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4500 if (VMI != FuncInfo.ValueMap.end()) {
4501 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
4502 UnorderedChains.push_back(Copy);
4506 // Finally, if the target has anything special to do, allow it to do so.
4507 // FIXME: this should insert code into the DAG!
4508 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4511 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4512 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4513 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4514 if (isSelector(I)) {
4515 // Apply the catch info to DestBB.
4516 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4518 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4519 FLI.CatchInfoFound.insert(I);
4524 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4525 /// DAG and fixes their tailcall attribute operand.
4526 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4527 TargetLowering& TLI) {
4528 SDNode * Ret = NULL;
4529 SDOperand Terminator = DAG.getRoot();
4532 if (Terminator.getOpcode() == ISD::RET) {
4533 Ret = Terminator.Val;
4536 // Fix tail call attribute of CALL nodes.
4537 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4538 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4539 if (BI->getOpcode() == ISD::CALL) {
4540 SDOperand OpRet(Ret, 0);
4541 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4542 bool isMarkedTailCall =
4543 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4544 // If CALL node has tail call attribute set to true and the call is not
4545 // eligible (no RET or the target rejects) the attribute is fixed to
4546 // false. The TargetLowering::IsEligibleForTailCallOptimization function
4547 // must correctly identify tail call optimizable calls.
4548 if (isMarkedTailCall &&
4550 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) {
4551 SmallVector<SDOperand, 32> Ops;
4553 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4554 E=OpCall.Val->op_end(); I!=E; I++, idx++) {
4558 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4560 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4566 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4567 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4568 FunctionLoweringInfo &FuncInfo) {
4569 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
4571 std::vector<SDOperand> UnorderedChains;
4573 // Lower any arguments needed in this block if this is the entry block.
4574 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4575 LowerArguments(LLVMBB, SDL, UnorderedChains);
4577 BB = FuncInfo.MBBMap[LLVMBB];
4578 SDL.setCurrentBasicBlock(BB);
4580 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4582 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4583 // Add a label to mark the beginning of the landing pad. Deletion of the
4584 // landing pad can thus be detected via the MachineModuleInfo.
4585 unsigned LabelID = MMI->addLandingPad(BB);
4586 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4587 DAG.getConstant(LabelID, MVT::i32),
4588 DAG.getConstant(1, MVT::i32)));
4590 // Mark exception register as live in.
4591 unsigned Reg = TLI.getExceptionAddressRegister();
4592 if (Reg) BB->addLiveIn(Reg);
4594 // Mark exception selector register as live in.
4595 Reg = TLI.getExceptionSelectorRegister();
4596 if (Reg) BB->addLiveIn(Reg);
4598 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4599 // function and list of typeids logically belong to the invoke (or, if you
4600 // like, the basic block containing the invoke), and need to be associated
4601 // with it in the dwarf exception handling tables. Currently however the
4602 // information is provided by an intrinsic (eh.selector) that can be moved
4603 // to unexpected places by the optimizers: if the unwind edge is critical,
4604 // then breaking it can result in the intrinsics being in the successor of
4605 // the landing pad, not the landing pad itself. This results in exceptions
4606 // not being caught because no typeids are associated with the invoke.
4607 // This may not be the only way things can go wrong, but it is the only way
4608 // we try to work around for the moment.
4609 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4611 if (Br && Br->isUnconditional()) { // Critical edge?
4612 BasicBlock::iterator I, E;
4613 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4618 // No catch info found - try to extract some from the successor.
4619 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4623 // Lower all of the non-terminator instructions.
4624 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4628 // Ensure that all instructions which are used outside of their defining
4629 // blocks are available as virtual registers. Invoke is handled elsewhere.
4630 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4631 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4632 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4633 if (VMI != FuncInfo.ValueMap.end())
4634 UnorderedChains.push_back(
4635 SDL.CopyValueToVirtualRegister(I, VMI->second));
4638 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4639 // ensure constants are generated when needed. Remember the virtual registers
4640 // that need to be added to the Machine PHI nodes as input. We cannot just
4641 // directly add them, because expansion might result in multiple MBB's for one
4642 // BB. As such, the start of the BB might correspond to a different MBB than
4645 TerminatorInst *TI = LLVMBB->getTerminator();
4647 // Emit constants only once even if used by multiple PHI nodes.
4648 std::map<Constant*, unsigned> ConstantsOut;
4650 // Vector bool would be better, but vector<bool> is really slow.
4651 std::vector<unsigned char> SuccsHandled;
4652 if (TI->getNumSuccessors())
4653 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4655 // Check successor nodes' PHI nodes that expect a constant to be available
4657 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4658 BasicBlock *SuccBB = TI->getSuccessor(succ);
4659 if (!isa<PHINode>(SuccBB->begin())) continue;
4660 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4662 // If this terminator has multiple identical successors (common for
4663 // switches), only handle each succ once.
4664 unsigned SuccMBBNo = SuccMBB->getNumber();
4665 if (SuccsHandled[SuccMBBNo]) continue;
4666 SuccsHandled[SuccMBBNo] = true;
4668 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4671 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4672 // nodes and Machine PHI nodes, but the incoming operands have not been
4674 for (BasicBlock::iterator I = SuccBB->begin();
4675 (PN = dyn_cast<PHINode>(I)); ++I) {
4676 // Ignore dead phi's.
4677 if (PN->use_empty()) continue;
4680 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4682 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4683 unsigned &RegOut = ConstantsOut[C];
4685 RegOut = FuncInfo.CreateRegForValue(C);
4686 UnorderedChains.push_back(
4687 SDL.CopyValueToVirtualRegister(C, RegOut));
4691 Reg = FuncInfo.ValueMap[PHIOp];
4693 assert(isa<AllocaInst>(PHIOp) &&
4694 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4695 "Didn't codegen value into a register!??");
4696 Reg = FuncInfo.CreateRegForValue(PHIOp);
4697 UnorderedChains.push_back(
4698 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4702 // Remember that this register needs to added to the machine PHI node as
4703 // the input for this MBB.
4704 MVT::ValueType VT = TLI.getValueType(PN->getType());
4705 unsigned NumRegisters = TLI.getNumRegisters(VT);
4706 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4707 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4710 ConstantsOut.clear();
4712 // Turn all of the unordered chains into one factored node.
4713 if (!UnorderedChains.empty()) {
4714 SDOperand Root = SDL.getRoot();
4715 if (Root.getOpcode() != ISD::EntryToken) {
4716 unsigned i = 0, e = UnorderedChains.size();
4717 for (; i != e; ++i) {
4718 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4719 if (UnorderedChains[i].Val->getOperand(0) == Root)
4720 break; // Don't add the root if we already indirectly depend on it.
4724 UnorderedChains.push_back(Root);
4726 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4727 &UnorderedChains[0], UnorderedChains.size()));
4730 // Lower the terminator after the copies are emitted.
4731 SDL.visit(*LLVMBB->getTerminator());
4733 // Copy over any CaseBlock records that may now exist due to SwitchInst
4734 // lowering, as well as any jump table information.
4735 SwitchCases.clear();
4736 SwitchCases = SDL.SwitchCases;
4738 JTCases = SDL.JTCases;
4739 BitTestCases.clear();
4740 BitTestCases = SDL.BitTestCases;
4742 // Make sure the root of the DAG is up-to-date.
4743 DAG.setRoot(SDL.getRoot());
4745 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4746 // with correct tailcall attribute so that the target can rely on the tailcall
4747 // attribute indicating whether the call is really eligible for tail call
4749 CheckDAGForTailCallsAndFixThem(DAG, TLI);
4752 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4753 DOUT << "Lowered selection DAG:\n";
4756 // Run the DAG combiner in pre-legalize mode.
4757 DAG.Combine(false, *AA);
4759 DOUT << "Optimized lowered selection DAG:\n";
4762 // Second step, hack on the DAG until it only uses operations and types that
4763 // the target supports.
4764 #if 0 // Enable this some day.
4765 DAG.LegalizeTypes();
4766 // Someday even later, enable a dag combine pass here.
4770 DOUT << "Legalized selection DAG:\n";
4773 // Run the DAG combiner in post-legalize mode.
4774 DAG.Combine(true, *AA);
4776 DOUT << "Optimized legalized selection DAG:\n";
4779 if (ViewISelDAGs) DAG.viewGraph();
4781 // Third, instruction select all of the operations to machine code, adding the
4782 // code to the MachineBasicBlock.
4783 InstructionSelectBasicBlock(DAG);
4785 DOUT << "Selected machine code:\n";
4789 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4790 FunctionLoweringInfo &FuncInfo) {
4791 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4793 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4796 // First step, lower LLVM code to some DAG. This DAG may use operations and
4797 // types that are not supported by the target.
4798 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4800 // Second step, emit the lowered DAG as machine code.
4801 CodeGenAndEmitDAG(DAG);
4804 DOUT << "Total amount of phi nodes to update: "
4805 << PHINodesToUpdate.size() << "\n";
4806 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4807 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4808 << ", " << PHINodesToUpdate[i].second << ")\n";);
4810 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4811 // PHI nodes in successors.
4812 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4813 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4814 MachineInstr *PHI = PHINodesToUpdate[i].first;
4815 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4816 "This is not a machine PHI node that we are updating!");
4817 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4819 PHI->addOperand(MachineOperand::CreateMBB(BB));
4824 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4825 // Lower header first, if it wasn't already lowered
4826 if (!BitTestCases[i].Emitted) {
4827 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4829 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
4830 // Set the current basic block to the mbb we wish to insert the code into
4831 BB = BitTestCases[i].Parent;
4832 HSDL.setCurrentBasicBlock(BB);
4834 HSDL.visitBitTestHeader(BitTestCases[i]);
4835 HSDAG.setRoot(HSDL.getRoot());
4836 CodeGenAndEmitDAG(HSDAG);
4839 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4840 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4842 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
4843 // Set the current basic block to the mbb we wish to insert the code into
4844 BB = BitTestCases[i].Cases[j].ThisBB;
4845 BSDL.setCurrentBasicBlock(BB);
4848 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4849 BitTestCases[i].Reg,
4850 BitTestCases[i].Cases[j]);
4852 BSDL.visitBitTestCase(BitTestCases[i].Default,
4853 BitTestCases[i].Reg,
4854 BitTestCases[i].Cases[j]);
4857 BSDAG.setRoot(BSDL.getRoot());
4858 CodeGenAndEmitDAG(BSDAG);
4862 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4863 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4864 MachineBasicBlock *PHIBB = PHI->getParent();
4865 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4866 "This is not a machine PHI node that we are updating!");
4867 // This is "default" BB. We have two jumps to it. From "header" BB and
4868 // from last "case" BB.
4869 if (PHIBB == BitTestCases[i].Default) {
4870 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4872 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
4873 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4875 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
4878 // One of "cases" BB.
4879 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4880 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
4881 if (cBB->succ_end() !=
4882 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
4883 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4885 PHI->addOperand(MachineOperand::CreateMBB(cBB));
4891 // If the JumpTable record is filled in, then we need to emit a jump table.
4892 // Updating the PHI nodes is tricky in this case, since we need to determine
4893 // whether the PHI is a successor of the range check MBB or the jump table MBB
4894 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
4895 // Lower header first, if it wasn't already lowered
4896 if (!JTCases[i].first.Emitted) {
4897 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4899 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
4900 // Set the current basic block to the mbb we wish to insert the code into
4901 BB = JTCases[i].first.HeaderBB;
4902 HSDL.setCurrentBasicBlock(BB);
4904 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
4905 HSDAG.setRoot(HSDL.getRoot());
4906 CodeGenAndEmitDAG(HSDAG);
4909 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4911 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
4912 // Set the current basic block to the mbb we wish to insert the code into
4913 BB = JTCases[i].second.MBB;
4914 JSDL.setCurrentBasicBlock(BB);
4916 JSDL.visitJumpTable(JTCases[i].second);
4917 JSDAG.setRoot(JSDL.getRoot());
4918 CodeGenAndEmitDAG(JSDAG);
4921 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4922 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4923 MachineBasicBlock *PHIBB = PHI->getParent();
4924 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4925 "This is not a machine PHI node that we are updating!");
4926 // "default" BB. We can go there only from header BB.
4927 if (PHIBB == JTCases[i].second.Default) {
4928 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4930 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
4932 // JT BB. Just iterate over successors here
4933 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
4934 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4936 PHI->addOperand(MachineOperand::CreateMBB(BB));
4941 // If the switch block involved a branch to one of the actual successors, we
4942 // need to update PHI nodes in that block.
4943 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4944 MachineInstr *PHI = PHINodesToUpdate[i].first;
4945 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4946 "This is not a machine PHI node that we are updating!");
4947 if (BB->isSuccessor(PHI->getParent())) {
4948 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4950 PHI->addOperand(MachineOperand::CreateMBB(BB));
4954 // If we generated any switch lowering information, build and codegen any
4955 // additional DAGs necessary.
4956 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
4957 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4959 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
4961 // Set the current basic block to the mbb we wish to insert the code into
4962 BB = SwitchCases[i].ThisBB;
4963 SDL.setCurrentBasicBlock(BB);
4966 SDL.visitSwitchCase(SwitchCases[i]);
4967 SDAG.setRoot(SDL.getRoot());
4968 CodeGenAndEmitDAG(SDAG);
4970 // Handle any PHI nodes in successors of this chunk, as if we were coming
4971 // from the original BB before switch expansion. Note that PHI nodes can
4972 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4973 // handle them the right number of times.
4974 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
4975 for (MachineBasicBlock::iterator Phi = BB->begin();
4976 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4977 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4978 for (unsigned pn = 0; ; ++pn) {
4979 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4980 if (PHINodesToUpdate[pn].first == Phi) {
4981 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
4983 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
4989 // Don't process RHS if same block as LHS.
4990 if (BB == SwitchCases[i].FalseBB)
4991 SwitchCases[i].FalseBB = 0;
4993 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4994 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4995 SwitchCases[i].FalseBB = 0;
4997 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5002 //===----------------------------------------------------------------------===//
5003 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
5004 /// target node in the graph.
5005 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
5006 if (ViewSchedDAGs) DAG.viewGraph();
5008 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5012 RegisterScheduler::setDefault(Ctor);
5015 ScheduleDAG *SL = Ctor(this, &DAG, BB);
5018 if (ViewSUnitDAGs) SL->viewGraph();
5024 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5025 return new HazardRecognizer();
5028 //===----------------------------------------------------------------------===//
5029 // Helper functions used by the generated instruction selector.
5030 //===----------------------------------------------------------------------===//
5031 // Calls to these methods are generated by tblgen.
5033 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5034 /// the dag combiner simplified the 255, we still want to match. RHS is the
5035 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5036 /// specified in the .td file (e.g. 255).
5037 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5038 int64_t DesiredMaskS) const {
5039 uint64_t ActualMask = RHS->getValue();
5040 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5042 // If the actual mask exactly matches, success!
5043 if (ActualMask == DesiredMask)
5046 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5047 if (ActualMask & ~DesiredMask)
5050 // Otherwise, the DAG Combiner may have proven that the value coming in is
5051 // either already zero or is not demanded. Check for known zero input bits.
5052 uint64_t NeededMask = DesiredMask & ~ActualMask;
5053 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5056 // TODO: check to see if missing bits are just not demanded.
5058 // Otherwise, this pattern doesn't match.
5062 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5063 /// the dag combiner simplified the 255, we still want to match. RHS is the
5064 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5065 /// specified in the .td file (e.g. 255).
5066 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5067 int64_t DesiredMaskS) const {
5068 uint64_t ActualMask = RHS->getValue();
5069 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5071 // If the actual mask exactly matches, success!
5072 if (ActualMask == DesiredMask)
5075 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5076 if (ActualMask & ~DesiredMask)
5079 // Otherwise, the DAG Combiner may have proven that the value coming in is
5080 // either already zero or is not demanded. Check for known zero input bits.
5081 uint64_t NeededMask = DesiredMask & ~ActualMask;
5083 uint64_t KnownZero, KnownOne;
5084 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5086 // If all the missing bits in the or are already known to be set, match!
5087 if ((NeededMask & KnownOne) == NeededMask)
5090 // TODO: check to see if missing bits are just not demanded.
5092 // Otherwise, this pattern doesn't match.
5097 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5098 /// by tblgen. Others should not call it.
5099 void SelectionDAGISel::
5100 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5101 std::vector<SDOperand> InOps;
5102 std::swap(InOps, Ops);
5104 Ops.push_back(InOps[0]); // input chain.
5105 Ops.push_back(InOps[1]); // input asm string.
5107 unsigned i = 2, e = InOps.size();
5108 if (InOps[e-1].getValueType() == MVT::Flag)
5109 --e; // Don't process a flag operand if it is here.
5112 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5113 if ((Flags & 7) != 4 /*MEM*/) {
5114 // Just skip over this operand, copying the operands verbatim.
5115 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5116 i += (Flags >> 3) + 1;
5118 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5119 // Otherwise, this is a memory operand. Ask the target to select it.
5120 std::vector<SDOperand> SelOps;
5121 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5122 cerr << "Could not match memory address. Inline asm failure!\n";
5126 // Add this to the output node.
5127 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5128 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5130 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5135 // Add the flag input back if present.
5136 if (e != InOps.size())
5137 Ops.push_back(InOps.back());
5140 char SelectionDAGISel::ID = 0;