1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/CodeGen/ScheduleDAG.h"
17 #include "llvm/CallingConv.h"
18 #include "llvm/Constants.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/InlineAsm.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineDebugInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/CodeGen/SSARegMap.h"
34 #include "llvm/Target/MRegisterInfo.h"
35 #include "llvm/Target/TargetData.h"
36 #include "llvm/Target/TargetFrameInfo.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetLowering.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/Debug.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
62 // Scheduling heuristics
63 enum SchedHeuristics {
64 defaultScheduling, // Let the target specify its preference.
65 noScheduling, // No scheduling, emit breadth first sequence.
66 simpleScheduling, // Two pass, min. critical path, max. utilization.
67 simpleNoItinScheduling, // Same as above exact using generic latency.
68 listSchedulingBURR, // Bottom-up reg reduction list scheduling.
69 listSchedulingTDRR, // Top-down reg reduction list scheduling.
70 listSchedulingTD // Top-down list scheduler.
74 cl::opt<SchedHeuristics>
77 cl::desc("Choose scheduling style"),
78 cl::init(defaultScheduling),
80 clEnumValN(defaultScheduling, "default",
81 "Target preferred scheduling style"),
82 clEnumValN(noScheduling, "none",
83 "No scheduling: breadth first sequencing"),
84 clEnumValN(simpleScheduling, "simple",
85 "Simple two pass scheduling: minimize critical path "
86 "and maximize processor utilization"),
87 clEnumValN(simpleNoItinScheduling, "simple-noitin",
88 "Simple two pass scheduling: Same as simple "
89 "except using generic latency"),
90 clEnumValN(listSchedulingBURR, "list-burr",
91 "Bottom-up register reduction list scheduling"),
92 clEnumValN(listSchedulingTDRR, "list-tdrr",
93 "Top-down register reduction list scheduling"),
94 clEnumValN(listSchedulingTD, "list-td",
95 "Top-down list scheduler"),
100 /// RegsForValue - This struct represents the physical registers that a
101 /// particular value is assigned and the type information about the value.
102 /// This is needed because values can be promoted into larger registers and
103 /// expanded into multiple smaller registers than the value.
104 struct RegsForValue {
105 /// Regs - This list hold the register (for legal and promoted values)
106 /// or register set (for expanded values) that the value should be assigned
108 std::vector<unsigned> Regs;
110 /// RegVT - The value type of each register.
112 MVT::ValueType RegVT;
114 /// ValueVT - The value type of the LLVM value, which may be promoted from
115 /// RegVT or made from merging the two expanded parts.
116 MVT::ValueType ValueVT;
118 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
120 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
121 : RegVT(regvt), ValueVT(valuevt) {
124 RegsForValue(const std::vector<unsigned> ®s,
125 MVT::ValueType regvt, MVT::ValueType valuevt)
126 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
129 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
130 /// this value and returns the result as a ValueVT value. This uses
131 /// Chain/Flag as the input and updates them for the output Chain/Flag.
132 SDOperand getCopyFromRegs(SelectionDAG &DAG,
133 SDOperand &Chain, SDOperand &Flag) const;
135 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
136 /// specified value into the registers specified by this object. This uses
137 /// Chain/Flag as the input and updates them for the output Chain/Flag.
138 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
139 SDOperand &Chain, SDOperand &Flag) const;
141 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
142 /// operand list. This adds the code marker and includes the number of
143 /// values added into it.
144 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
145 std::vector<SDOperand> &Ops) const;
150 //===--------------------------------------------------------------------===//
151 /// FunctionLoweringInfo - This contains information that is global to a
152 /// function that is used when lowering a region of the function.
153 class FunctionLoweringInfo {
160 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
162 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
163 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
165 /// ValueMap - Since we emit code for the function a basic block at a time,
166 /// we must remember which virtual registers hold the values for
167 /// cross-basic-block values.
168 std::map<const Value*, unsigned> ValueMap;
170 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
171 /// the entry block. This allows the allocas to be efficiently referenced
172 /// anywhere in the function.
173 std::map<const AllocaInst*, int> StaticAllocaMap;
175 unsigned MakeReg(MVT::ValueType VT) {
176 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
179 unsigned CreateRegForValue(const Value *V);
181 unsigned InitializeRegForValue(const Value *V) {
182 unsigned &R = ValueMap[V];
183 assert(R == 0 && "Already initialized this value register!");
184 return R = CreateRegForValue(V);
189 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
190 /// PHI nodes or outside of the basic block that defines it, or used by a
191 /// switch instruction, which may expand to multiple basic blocks.
192 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
193 if (isa<PHINode>(I)) return true;
194 BasicBlock *BB = I->getParent();
195 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
196 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
197 isa<SwitchInst>(*UI))
202 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
203 /// entry block, return true. This includes arguments used by switches, since
204 /// the switch may expand into multiple basic blocks.
205 static bool isOnlyUsedInEntryBlock(Argument *A) {
206 BasicBlock *Entry = A->getParent()->begin();
207 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
208 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
209 return false; // Use not in entry block.
213 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
214 Function &fn, MachineFunction &mf)
215 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
217 // Create a vreg for each argument register that is not dead and is used
218 // outside of the entry block for the function.
219 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
221 if (!isOnlyUsedInEntryBlock(AI))
222 InitializeRegForValue(AI);
224 // Initialize the mapping of values to registers. This is only set up for
225 // instruction values that are used outside of the block that defines
227 Function::iterator BB = Fn.begin(), EB = Fn.end();
228 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
229 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
230 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
231 const Type *Ty = AI->getAllocatedType();
232 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
234 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
237 // If the alignment of the value is smaller than the size of the value,
238 // and if the size of the value is particularly small (<= 8 bytes),
239 // round up to the size of the value for potentially better performance.
241 // FIXME: This could be made better with a preferred alignment hook in
242 // TargetData. It serves primarily to 8-byte align doubles for X86.
243 if (Align < TySize && TySize <= 8) Align = TySize;
244 TySize *= CUI->getValue(); // Get total allocated size.
245 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
246 StaticAllocaMap[AI] =
247 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
250 for (; BB != EB; ++BB)
251 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
252 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
253 if (!isa<AllocaInst>(I) ||
254 !StaticAllocaMap.count(cast<AllocaInst>(I)))
255 InitializeRegForValue(I);
257 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
258 // also creates the initial PHI MachineInstrs, though none of the input
259 // operands are populated.
260 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
261 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
263 MF.getBasicBlockList().push_back(MBB);
265 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
268 for (BasicBlock::iterator I = BB->begin();
269 (PN = dyn_cast<PHINode>(I)); ++I)
270 if (!PN->use_empty()) {
271 MVT::ValueType VT = TLI.getValueType(PN->getType());
272 unsigned NumElements;
273 if (VT != MVT::Vector)
274 NumElements = TLI.getNumElements(VT);
276 MVT::ValueType VT1,VT2;
278 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
281 unsigned PHIReg = ValueMap[PN];
282 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
283 for (unsigned i = 0; i != NumElements; ++i)
284 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
289 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
290 /// the correctly promoted or expanded types. Assign these registers
291 /// consecutive vreg numbers and return the first assigned number.
292 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
293 MVT::ValueType VT = TLI.getValueType(V->getType());
295 // The number of multiples of registers that we need, to, e.g., split up
296 // a <2 x int64> -> 4 x i32 registers.
297 unsigned NumVectorRegs = 1;
299 // If this is a packed type, figure out what type it will decompose into
300 // and how many of the elements it will use.
301 if (VT == MVT::Vector) {
302 const PackedType *PTy = cast<PackedType>(V->getType());
303 unsigned NumElts = PTy->getNumElements();
304 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
306 // Divide the input until we get to a supported size. This will always
307 // end with a scalar if the target doesn't support vectors.
308 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
315 VT = getVectorType(EltTy, NumElts);
318 // The common case is that we will only create one register for this
319 // value. If we have that case, create and return the virtual register.
320 unsigned NV = TLI.getNumElements(VT);
322 // If we are promoting this value, pick the next largest supported type.
323 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
324 unsigned Reg = MakeReg(PromotedType);
325 // If this is a vector of supported or promoted types (e.g. 4 x i16),
326 // create all of the registers.
327 for (unsigned i = 1; i != NumVectorRegs; ++i)
328 MakeReg(PromotedType);
332 // If this value is represented with multiple target registers, make sure
333 // to create enough consecutive registers of the right (smaller) type.
334 unsigned NT = VT-1; // Find the type to use.
335 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
338 unsigned R = MakeReg((MVT::ValueType)NT);
339 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
340 MakeReg((MVT::ValueType)NT);
344 //===----------------------------------------------------------------------===//
345 /// SelectionDAGLowering - This is the common target-independent lowering
346 /// implementation that is parameterized by a TargetLowering object.
347 /// Also, targets can overload any lowering method.
350 class SelectionDAGLowering {
351 MachineBasicBlock *CurMBB;
353 std::map<const Value*, SDOperand> NodeMap;
355 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
356 /// them up and then emit token factor nodes when possible. This allows us to
357 /// get simple disambiguation between loads without worrying about alias
359 std::vector<SDOperand> PendingLoads;
361 /// Case - A pair of values to record the Value for a switch case, and the
362 /// case's target basic block.
363 typedef std::pair<Constant*, MachineBasicBlock*> Case;
364 typedef std::vector<Case>::iterator CaseItr;
365 typedef std::pair<CaseItr, CaseItr> CaseRange;
367 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
368 /// of conditional branches.
370 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
371 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
373 /// CaseBB - The MBB in which to emit the compare and branch
374 MachineBasicBlock *CaseBB;
375 /// LT, GE - If nonzero, we know the current case value must be less-than or
376 /// greater-than-or-equal-to these Constants.
379 /// Range - A pair of iterators representing the range of case values to be
380 /// processed at this point in the binary search tree.
384 /// The comparison function for sorting Case values.
386 bool operator () (const Case& C1, const Case& C2) {
387 if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first))
388 return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue();
390 const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first);
391 return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue();
396 // TLI - This is information that describes the available target features we
397 // need for lowering. This indicates when operations are unavailable,
398 // implemented with a libcall, etc.
401 const TargetData *TD;
403 /// SwitchCases - Vector of CaseBlock structures used to communicate
404 /// SwitchInst code generation information.
405 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
406 SelectionDAGISel::JumpTable JT;
408 /// FuncInfo - Information about the function as a whole.
410 FunctionLoweringInfo &FuncInfo;
412 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
413 FunctionLoweringInfo &funcinfo)
414 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
415 JT(0,0,0,0), FuncInfo(funcinfo) {
418 /// getRoot - Return the current virtual root of the Selection DAG.
420 SDOperand getRoot() {
421 if (PendingLoads.empty())
422 return DAG.getRoot();
424 if (PendingLoads.size() == 1) {
425 SDOperand Root = PendingLoads[0];
427 PendingLoads.clear();
431 // Otherwise, we have to make a token factor node.
432 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
433 PendingLoads.clear();
438 void visit(Instruction &I) { visit(I.getOpcode(), I); }
440 void visit(unsigned Opcode, User &I) {
442 default: assert(0 && "Unknown instruction type encountered!");
444 // Build the switch statement using the Instruction.def file.
445 #define HANDLE_INST(NUM, OPCODE, CLASS) \
446 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
447 #include "llvm/Instruction.def"
451 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
453 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
454 SDOperand SrcValue, SDOperand Root,
457 SDOperand getIntPtrConstant(uint64_t Val) {
458 return DAG.getConstant(Val, TLI.getPointerTy());
461 SDOperand getValue(const Value *V);
463 const SDOperand &setValue(const Value *V, SDOperand NewN) {
464 SDOperand &N = NodeMap[V];
465 assert(N.Val == 0 && "Already set a value for this node!");
469 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
471 bool OutReg, bool InReg,
472 std::set<unsigned> &OutputRegs,
473 std::set<unsigned> &InputRegs);
475 // Terminator instructions.
476 void visitRet(ReturnInst &I);
477 void visitBr(BranchInst &I);
478 void visitSwitch(SwitchInst &I);
479 void visitUnreachable(UnreachableInst &I) { /* noop */ }
481 // Helper for visitSwitch
482 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
483 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
485 // These all get lowered before this pass.
486 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
487 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
489 void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
490 void visitShift(User &I, unsigned Opcode);
491 void visitAdd(User &I) {
492 visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
494 void visitSub(User &I);
495 void visitMul(User &I) {
496 visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
498 void visitDiv(User &I) {
499 const Type *Ty = I.getType();
501 Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
502 Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
504 void visitRem(User &I) {
505 const Type *Ty = I.getType();
506 visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
508 void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
509 void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
510 void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
511 void visitShl(User &I) { visitShift(I, ISD::SHL); }
512 void visitShr(User &I) {
513 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
516 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc,
517 ISD::CondCode FPOpc);
518 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ,
520 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE,
522 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE,
524 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE,
526 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT,
528 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT,
531 void visitExtractElement(User &I);
532 void visitInsertElement(User &I);
533 void visitShuffleVector(User &I);
535 void visitGetElementPtr(User &I);
536 void visitCast(User &I);
537 void visitSelect(User &I);
539 void visitMalloc(MallocInst &I);
540 void visitFree(FreeInst &I);
541 void visitAlloca(AllocaInst &I);
542 void visitLoad(LoadInst &I);
543 void visitStore(StoreInst &I);
544 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
545 void visitCall(CallInst &I);
546 void visitInlineAsm(CallInst &I);
547 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
548 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
550 void visitVAStart(CallInst &I);
551 void visitVAArg(VAArgInst &I);
552 void visitVAEnd(CallInst &I);
553 void visitVACopy(CallInst &I);
554 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
556 void visitMemIntrinsic(CallInst &I, unsigned Op);
558 void visitUserOp1(Instruction &I) {
559 assert(0 && "UserOp1 should not exist at instruction selection time!");
562 void visitUserOp2(Instruction &I) {
563 assert(0 && "UserOp2 should not exist at instruction selection time!");
567 } // end namespace llvm
569 SDOperand SelectionDAGLowering::getValue(const Value *V) {
570 SDOperand &N = NodeMap[V];
573 const Type *VTy = V->getType();
574 MVT::ValueType VT = TLI.getValueType(VTy);
575 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
576 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
577 visit(CE->getOpcode(), *CE);
578 assert(N.Val && "visit didn't populate the ValueMap!");
580 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
581 return N = DAG.getGlobalAddress(GV, VT);
582 } else if (isa<ConstantPointerNull>(C)) {
583 return N = DAG.getConstant(0, TLI.getPointerTy());
584 } else if (isa<UndefValue>(C)) {
585 if (!isa<PackedType>(VTy))
586 return N = DAG.getNode(ISD::UNDEF, VT);
588 // Create a VBUILD_VECTOR of undef nodes.
589 const PackedType *PTy = cast<PackedType>(VTy);
590 unsigned NumElements = PTy->getNumElements();
591 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
593 std::vector<SDOperand> Ops;
594 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
596 // Create a VConstant node with generic Vector type.
597 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
598 Ops.push_back(DAG.getValueType(PVT));
599 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
600 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
601 return N = DAG.getConstantFP(CFP->getValue(), VT);
602 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
603 unsigned NumElements = PTy->getNumElements();
604 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
606 // Now that we know the number and type of the elements, push a
607 // Constant or ConstantFP node onto the ops list for each element of
608 // the packed constant.
609 std::vector<SDOperand> Ops;
610 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
611 for (unsigned i = 0; i != NumElements; ++i)
612 Ops.push_back(getValue(CP->getOperand(i)));
614 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
616 if (MVT::isFloatingPoint(PVT))
617 Op = DAG.getConstantFP(0, PVT);
619 Op = DAG.getConstant(0, PVT);
620 Ops.assign(NumElements, Op);
623 // Create a VBUILD_VECTOR node with generic Vector type.
624 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
625 Ops.push_back(DAG.getValueType(PVT));
626 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
628 // Canonicalize all constant ints to be unsigned.
629 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
633 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
634 std::map<const AllocaInst*, int>::iterator SI =
635 FuncInfo.StaticAllocaMap.find(AI);
636 if (SI != FuncInfo.StaticAllocaMap.end())
637 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
640 std::map<const Value*, unsigned>::const_iterator VMI =
641 FuncInfo.ValueMap.find(V);
642 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
644 unsigned InReg = VMI->second;
646 // If this type is not legal, make it so now.
647 if (VT != MVT::Vector) {
648 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
650 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
652 // Source must be expanded. This input value is actually coming from the
653 // register pair VMI->second and VMI->second+1.
654 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
655 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
656 } else if (DestVT > VT) { // Promotion case
657 if (MVT::isFloatingPoint(VT))
658 N = DAG.getNode(ISD::FP_ROUND, VT, N);
660 N = DAG.getNode(ISD::TRUNCATE, VT, N);
663 // Otherwise, if this is a vector, make it available as a generic vector
665 MVT::ValueType PTyElementVT, PTyLegalElementVT;
666 const PackedType *PTy = cast<PackedType>(VTy);
667 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
670 // Build a VBUILD_VECTOR with the input registers.
671 std::vector<SDOperand> Ops;
672 if (PTyElementVT == PTyLegalElementVT) {
673 // If the value types are legal, just VBUILD the CopyFromReg nodes.
674 for (unsigned i = 0; i != NE; ++i)
675 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
677 } else if (PTyElementVT < PTyLegalElementVT) {
678 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
679 for (unsigned i = 0; i != NE; ++i) {
680 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
682 if (MVT::isFloatingPoint(PTyElementVT))
683 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
685 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
689 // If the register was expanded, use BUILD_PAIR.
690 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
691 for (unsigned i = 0; i != NE/2; ++i) {
692 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
694 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
696 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
700 Ops.push_back(DAG.getConstant(NE, MVT::i32));
701 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
702 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
704 // Finally, use a VBIT_CONVERT to make this available as the appropriate
706 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
707 DAG.getConstant(PTy->getNumElements(),
709 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
716 void SelectionDAGLowering::visitRet(ReturnInst &I) {
717 if (I.getNumOperands() == 0) {
718 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
721 std::vector<SDOperand> NewValues;
722 NewValues.push_back(getRoot());
723 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
724 SDOperand RetOp = getValue(I.getOperand(i));
725 bool isSigned = I.getOperand(i)->getType()->isSigned();
727 // If this is an integer return value, we need to promote it ourselves to
728 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
730 // FIXME: C calling convention requires the return type to be promoted to
731 // at least 32-bit. But this is not necessary for non-C calling conventions.
732 if (MVT::isInteger(RetOp.getValueType()) &&
733 RetOp.getValueType() < MVT::i64) {
734 MVT::ValueType TmpVT;
735 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
736 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
741 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
743 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
745 NewValues.push_back(RetOp);
746 NewValues.push_back(DAG.getConstant(isSigned, MVT::i32));
748 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, NewValues));
751 void SelectionDAGLowering::visitBr(BranchInst &I) {
752 // Update machine-CFG edges.
753 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
754 CurMBB->addSuccessor(Succ0MBB);
756 // Figure out which block is immediately after the current one.
757 MachineBasicBlock *NextBlock = 0;
758 MachineFunction::iterator BBI = CurMBB;
759 if (++BBI != CurMBB->getParent()->end())
762 if (I.isUnconditional()) {
763 // If this is not a fall-through branch, emit the branch.
764 if (Succ0MBB != NextBlock)
765 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
766 DAG.getBasicBlock(Succ0MBB)));
768 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
769 CurMBB->addSuccessor(Succ1MBB);
771 SDOperand Cond = getValue(I.getCondition());
772 if (Succ1MBB == NextBlock) {
773 // If the condition is false, fall through. This means we should branch
774 // if the condition is true to Succ #0.
775 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
776 Cond, DAG.getBasicBlock(Succ0MBB)));
777 } else if (Succ0MBB == NextBlock) {
778 // If the condition is true, fall through. This means we should branch if
779 // the condition is false to Succ #1. Invert the condition first.
780 SDOperand True = DAG.getConstant(1, Cond.getValueType());
781 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
782 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
783 Cond, DAG.getBasicBlock(Succ1MBB)));
785 std::vector<SDOperand> Ops;
786 Ops.push_back(getRoot());
787 // If the false case is the current basic block, then this is a self
788 // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
789 // adds an extra instruction in the loop. Instead, invert the
790 // condition and emit "Loop: ... br!cond Loop; br Out.
791 if (CurMBB == Succ1MBB) {
792 std::swap(Succ0MBB, Succ1MBB);
793 SDOperand True = DAG.getConstant(1, Cond.getValueType());
794 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
796 SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
797 DAG.getBasicBlock(Succ0MBB));
798 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
799 DAG.getBasicBlock(Succ1MBB)));
804 /// visitSwitchCase - Emits the necessary code to represent a single node in
805 /// the binary search tree resulting from lowering a switch instruction.
806 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
807 SDOperand SwitchOp = getValue(CB.SwitchV);
808 SDOperand CaseOp = getValue(CB.CaseC);
809 SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC);
811 // Set NextBlock to be the MBB immediately after the current one, if any.
812 // This is used to avoid emitting unnecessary branches to the next block.
813 MachineBasicBlock *NextBlock = 0;
814 MachineFunction::iterator BBI = CurMBB;
815 if (++BBI != CurMBB->getParent()->end())
818 // If the lhs block is the next block, invert the condition so that we can
819 // fall through to the lhs instead of the rhs block.
820 if (CB.LHSBB == NextBlock) {
821 std::swap(CB.LHSBB, CB.RHSBB);
822 SDOperand True = DAG.getConstant(1, Cond.getValueType());
823 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
825 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
826 DAG.getBasicBlock(CB.LHSBB));
827 if (CB.RHSBB == NextBlock)
830 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
831 DAG.getBasicBlock(CB.RHSBB)));
832 // Update successor info
833 CurMBB->addSuccessor(CB.LHSBB);
834 CurMBB->addSuccessor(CB.RHSBB);
837 /// visitSwitchCase - Emits the necessary code to represent a single node in
838 /// the binary search tree resulting from lowering a switch instruction.
839 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
840 // FIXME: Need to emit different code for PIC vs. Non-PIC, specifically,
841 // we need to add the address of the jump table to the value loaded, since
842 // the entries in the jump table will be differences rather than absolute
845 // Emit the code for the jump table
846 MVT::ValueType PTy = TLI.getPointerTy();
847 unsigned PTyBytes = MVT::getSizeInBits(PTy)/8;
848 SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
849 SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy,
850 DAG.getConstant(PTyBytes, PTy));
851 SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, DAG.getJumpTable(JT.JTI,PTy));
852 SDOperand LD = DAG.getLoad(PTy, Copy.getValue(1), ADD, DAG.getSrcValue(0));
853 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD));
856 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
857 // Figure out which block is immediately after the current one.
858 MachineBasicBlock *NextBlock = 0;
859 MachineFunction::iterator BBI = CurMBB;
860 if (++BBI != CurMBB->getParent()->end())
863 // If there is only the default destination, branch to it if it is not the
864 // next basic block. Otherwise, just fall through.
865 if (I.getNumOperands() == 2) {
866 // Update machine-CFG edges.
867 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()];
868 // If this is not a fall-through branch, emit the branch.
869 if (DefaultMBB != NextBlock)
870 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
871 DAG.getBasicBlock(DefaultMBB)));
872 CurMBB->addSuccessor(DefaultMBB);
876 // If there are any non-default case statements, create a vector of Cases
877 // representing each one, and sort the vector so that we can efficiently
878 // create a binary search tree from them.
879 std::vector<Case> Cases;
880 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
881 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
882 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
884 std::sort(Cases.begin(), Cases.end(), CaseCmp());
886 // Get the Value to be switched on and default basic blocks, which will be
887 // inserted into CaseBlock records, representing basic blocks in the binary
889 Value *SV = I.getOperand(0);
890 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
892 // Get the MachineFunction which holds the current MBB. This is used during
893 // emission of jump tables, and when inserting any additional MBBs necessary
894 // to represent the switch.
895 MachineFunction *CurMF = CurMBB->getParent();
896 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
897 Reloc::Model Relocs = TLI.getTargetMachine().getRelocationModel();
899 // If the switch has more than 5 blocks, and at least 31.25% dense, and the
900 // target supports indirect branches, then emit a jump table rather than
901 // lowering the switch to a binary tree of conditional branches.
902 // FIXME: Make this work with PIC code
903 if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) &&
904 (Relocs == Reloc::Static || Relocs == Reloc::DynamicNoPIC) &&
906 uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue();
907 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getRawValue();
908 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
910 if (Density >= 0.3125) {
911 // Create a new basic block to hold the code for loading the address
912 // of the jump table, and jumping to it. Update successor information;
913 // we will either branch to the default case for the switch, or the jump
915 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
916 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
917 CurMBB->addSuccessor(Default);
918 CurMBB->addSuccessor(JumpTableBB);
920 // Subtract the lowest switch case value from the value being switched on
921 // and conditional branch to default mbb if the result is greater than the
922 // difference between smallest and largest cases.
923 SDOperand SwitchOp = getValue(SV);
924 MVT::ValueType VT = SwitchOp.getValueType();
925 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
926 DAG.getConstant(First, VT));
928 // The SDNode we just created, which holds the value being switched on
929 // minus the the smallest case value, needs to be copied to a virtual
930 // register so it can be used as an index into the jump table in a
931 // subsequent basic block. This value may be smaller or larger than the
932 // target's pointer type, and therefore require extension or truncating.
933 if (VT > TLI.getPointerTy())
934 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
936 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
937 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
938 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
940 // Emit the range check for the jump table, and branch to the default
941 // block for the switch statement if the value being switched on exceeds
942 // the largest case in the switch.
943 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
944 DAG.getConstant(Last-First,VT), ISD::SETUGT);
945 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
946 DAG.getBasicBlock(Default)));
948 // Build a vector of destination BBs, corresponding to each target
949 // of the jump table. If the value of the jump table slot corresponds to
950 // a case statement, push the case's BB onto the vector, otherwise, push
952 std::set<MachineBasicBlock*> UniqueBBs;
953 std::vector<MachineBasicBlock*> DestBBs;
954 uint64_t TEI = First;
955 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) {
956 if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) {
957 DestBBs.push_back(ii->second);
958 UniqueBBs.insert(ii->second);
961 DestBBs.push_back(Default);
962 UniqueBBs.insert(Default);
966 // Update successor info
967 for (std::set<MachineBasicBlock*>::iterator ii = UniqueBBs.begin(),
968 ee = UniqueBBs.end(); ii != ee; ++ii)
969 JumpTableBB->addSuccessor(*ii);
971 // Create a jump table index for this jump table, or return an existing
973 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
975 // Set the jump table information so that we can codegen it as a second
977 JT.Reg = JumpTableReg;
979 JT.MBB = JumpTableBB;
980 JT.Default = Default;
985 // Push the initial CaseRec onto the worklist
986 std::vector<CaseRec> CaseVec;
987 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
989 while (!CaseVec.empty()) {
990 // Grab a record representing a case range to process off the worklist
991 CaseRec CR = CaseVec.back();
994 // Size is the number of Cases represented by this range. If Size is 1,
995 // then we are processing a leaf of the binary search tree. Otherwise,
996 // we need to pick a pivot, and push left and right ranges onto the
998 unsigned Size = CR.Range.second - CR.Range.first;
1001 // Create a CaseBlock record representing a conditional branch to
1002 // the Case's target mbb if the value being switched on SV is equal
1003 // to C. Otherwise, branch to default.
1004 Constant *C = CR.Range.first->first;
1005 MachineBasicBlock *Target = CR.Range.first->second;
1006 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1008 // If the MBB representing the leaf node is the current MBB, then just
1009 // call visitSwitchCase to emit the code into the current block.
1010 // Otherwise, push the CaseBlock onto the vector to be later processed
1011 // by SDISel, and insert the node's MBB before the next MBB.
1012 if (CR.CaseBB == CurMBB)
1013 visitSwitchCase(CB);
1015 SwitchCases.push_back(CB);
1016 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1019 // split case range at pivot
1020 CaseItr Pivot = CR.Range.first + (Size / 2);
1021 CaseRange LHSR(CR.Range.first, Pivot);
1022 CaseRange RHSR(Pivot, CR.Range.second);
1023 Constant *C = Pivot->first;
1024 MachineBasicBlock *RHSBB = 0, *LHSBB = 0;
1025 // We know that we branch to the LHS if the Value being switched on is
1026 // less than the Pivot value, C. We use this to optimize our binary
1027 // tree a bit, by recognizing that if SV is greater than or equal to the
1028 // LHS's Case Value, and that Case Value is exactly one less than the
1029 // Pivot's Value, then we can branch directly to the LHS's Target,
1030 // rather than creating a leaf node for it.
1031 if ((LHSR.second - LHSR.first) == 1 &&
1032 LHSR.first->first == CR.GE &&
1033 cast<ConstantIntegral>(C)->getRawValue() ==
1034 (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) {
1035 LHSBB = LHSR.first->second;
1037 LHSBB = new MachineBasicBlock(LLVMBB);
1038 CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR));
1040 // Similar to the optimization above, if the Value being switched on is
1041 // known to be less than the Constant CR.LT, and the current Case Value
1042 // is CR.LT - 1, then we can branch directly to the target block for
1043 // the current Case Value, rather than emitting a RHS leaf node for it.
1044 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1045 cast<ConstantIntegral>(RHSR.first->first)->getRawValue() ==
1046 (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) {
1047 RHSBB = RHSR.first->second;
1049 RHSBB = new MachineBasicBlock(LLVMBB);
1050 CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR));
1052 // Create a CaseBlock record representing a conditional branch to
1053 // the LHS node if the value being switched on SV is less than C.
1054 // Otherwise, branch to LHS.
1055 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
1056 SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB);
1057 if (CR.CaseBB == CurMBB)
1058 visitSwitchCase(CB);
1060 SwitchCases.push_back(CB);
1061 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1067 void SelectionDAGLowering::visitSub(User &I) {
1068 // -0.0 - X --> fneg
1069 if (I.getType()->isFloatingPoint()) {
1070 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1071 if (CFP->isExactlyValue(-0.0)) {
1072 SDOperand Op2 = getValue(I.getOperand(1));
1073 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1077 visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
1080 void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
1082 const Type *Ty = I.getType();
1083 SDOperand Op1 = getValue(I.getOperand(0));
1084 SDOperand Op2 = getValue(I.getOperand(1));
1086 if (Ty->isIntegral()) {
1087 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
1088 } else if (Ty->isFloatingPoint()) {
1089 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
1091 const PackedType *PTy = cast<PackedType>(Ty);
1092 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1093 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1094 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1098 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1099 SDOperand Op1 = getValue(I.getOperand(0));
1100 SDOperand Op2 = getValue(I.getOperand(1));
1102 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1104 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1107 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
1108 ISD::CondCode UnsignedOpcode,
1109 ISD::CondCode FPOpcode) {
1110 SDOperand Op1 = getValue(I.getOperand(0));
1111 SDOperand Op2 = getValue(I.getOperand(1));
1112 ISD::CondCode Opcode = SignedOpcode;
1113 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint())
1115 else if (I.getOperand(0)->getType()->isUnsigned())
1116 Opcode = UnsignedOpcode;
1117 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1120 void SelectionDAGLowering::visitSelect(User &I) {
1121 SDOperand Cond = getValue(I.getOperand(0));
1122 SDOperand TrueVal = getValue(I.getOperand(1));
1123 SDOperand FalseVal = getValue(I.getOperand(2));
1124 if (!isa<PackedType>(I.getType())) {
1125 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1126 TrueVal, FalseVal));
1128 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1129 *(TrueVal.Val->op_end()-2),
1130 *(TrueVal.Val->op_end()-1)));
1134 void SelectionDAGLowering::visitCast(User &I) {
1135 SDOperand N = getValue(I.getOperand(0));
1136 MVT::ValueType SrcVT = N.getValueType();
1137 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1139 if (DestVT == MVT::Vector) {
1140 // This is a cast to a vector from something else. This is always a bit
1141 // convert. Get information about the input vector.
1142 const PackedType *DestTy = cast<PackedType>(I.getType());
1143 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1144 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1145 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1146 DAG.getValueType(EltVT)));
1147 } else if (SrcVT == DestVT) {
1148 setValue(&I, N); // noop cast.
1149 } else if (DestVT == MVT::i1) {
1150 // Cast to bool is a comparison against zero, not truncation to zero.
1151 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
1152 DAG.getConstantFP(0.0, N.getValueType());
1153 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
1154 } else if (isInteger(SrcVT)) {
1155 if (isInteger(DestVT)) { // Int -> Int cast
1156 if (DestVT < SrcVT) // Truncating cast?
1157 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1158 else if (I.getOperand(0)->getType()->isSigned())
1159 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1161 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1162 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast
1163 if (I.getOperand(0)->getType()->isSigned())
1164 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1166 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1168 assert(0 && "Unknown cast!");
1170 } else if (isFloatingPoint(SrcVT)) {
1171 if (isFloatingPoint(DestVT)) { // FP -> FP cast
1172 if (DestVT < SrcVT) // Rounding cast?
1173 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1175 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1176 } else if (isInteger(DestVT)) { // FP -> Int cast.
1177 if (I.getType()->isSigned())
1178 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1180 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1182 assert(0 && "Unknown cast!");
1185 assert(SrcVT == MVT::Vector && "Unknown cast!");
1186 assert(DestVT != MVT::Vector && "Casts to vector already handled!");
1187 // This is a cast from a vector to something else. This is always a bit
1188 // convert. Get information about the input vector.
1189 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1193 void SelectionDAGLowering::visitInsertElement(User &I) {
1194 SDOperand InVec = getValue(I.getOperand(0));
1195 SDOperand InVal = getValue(I.getOperand(1));
1196 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1197 getValue(I.getOperand(2)));
1199 SDOperand Num = *(InVec.Val->op_end()-2);
1200 SDOperand Typ = *(InVec.Val->op_end()-1);
1201 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1202 InVec, InVal, InIdx, Num, Typ));
1205 void SelectionDAGLowering::visitExtractElement(User &I) {
1206 SDOperand InVec = getValue(I.getOperand(0));
1207 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1208 getValue(I.getOperand(1)));
1209 SDOperand Typ = *(InVec.Val->op_end()-1);
1210 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1211 TLI.getValueType(I.getType()), InVec, InIdx));
1214 void SelectionDAGLowering::visitShuffleVector(User &I) {
1215 SDOperand V1 = getValue(I.getOperand(0));
1216 SDOperand V2 = getValue(I.getOperand(1));
1217 SDOperand Mask = getValue(I.getOperand(2));
1219 SDOperand Num = *(V1.Val->op_end()-2);
1220 SDOperand Typ = *(V2.Val->op_end()-1);
1221 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1222 V1, V2, Mask, Num, Typ));
1226 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1227 SDOperand N = getValue(I.getOperand(0));
1228 const Type *Ty = I.getOperand(0)->getType();
1230 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1233 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1234 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
1237 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
1238 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1239 getIntPtrConstant(Offset));
1241 Ty = StTy->getElementType(Field);
1243 Ty = cast<SequentialType>(Ty)->getElementType();
1245 // If this is a constant subscript, handle it quickly.
1246 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1247 if (CI->getRawValue() == 0) continue;
1250 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
1251 Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
1253 Offs = TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
1254 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1258 // N = N + Idx * ElementSize;
1259 uint64_t ElementSize = TD->getTypeSize(Ty);
1260 SDOperand IdxN = getValue(Idx);
1262 // If the index is smaller or larger than intptr_t, truncate or extend
1264 if (IdxN.getValueType() < N.getValueType()) {
1265 if (Idx->getType()->isSigned())
1266 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1268 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
1269 } else if (IdxN.getValueType() > N.getValueType())
1270 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1272 // If this is a multiply by a power of two, turn it into a shl
1273 // immediately. This is a very common case.
1274 if (isPowerOf2_64(ElementSize)) {
1275 unsigned Amt = Log2_64(ElementSize);
1276 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1277 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1278 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1282 SDOperand Scale = getIntPtrConstant(ElementSize);
1283 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1284 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1290 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1291 // If this is a fixed sized alloca in the entry block of the function,
1292 // allocate it statically on the stack.
1293 if (FuncInfo.StaticAllocaMap.count(&I))
1294 return; // getValue will auto-populate this.
1296 const Type *Ty = I.getAllocatedType();
1297 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1298 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
1301 SDOperand AllocSize = getValue(I.getArraySize());
1302 MVT::ValueType IntPtr = TLI.getPointerTy();
1303 if (IntPtr < AllocSize.getValueType())
1304 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1305 else if (IntPtr > AllocSize.getValueType())
1306 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1308 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1309 getIntPtrConstant(TySize));
1311 // Handle alignment. If the requested alignment is less than or equal to the
1312 // stack alignment, ignore it and round the size of the allocation up to the
1313 // stack alignment size. If the size is greater than the stack alignment, we
1314 // note this in the DYNAMIC_STACKALLOC node.
1315 unsigned StackAlign =
1316 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1317 if (Align <= StackAlign) {
1319 // Add SA-1 to the size.
1320 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1321 getIntPtrConstant(StackAlign-1));
1322 // Mask out the low bits for alignment purposes.
1323 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1324 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1327 std::vector<MVT::ValueType> VTs;
1328 VTs.push_back(AllocSize.getValueType());
1329 VTs.push_back(MVT::Other);
1330 std::vector<SDOperand> Ops;
1331 Ops.push_back(getRoot());
1332 Ops.push_back(AllocSize);
1333 Ops.push_back(getIntPtrConstant(Align));
1334 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
1335 DAG.setRoot(setValue(&I, DSA).getValue(1));
1337 // Inform the Frame Information that we have just allocated a variable-sized
1339 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1342 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1343 SDOperand Ptr = getValue(I.getOperand(0));
1349 // Do not serialize non-volatile loads against each other.
1350 Root = DAG.getRoot();
1353 setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)),
1354 Root, I.isVolatile()));
1357 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1358 SDOperand SrcValue, SDOperand Root,
1361 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1362 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1363 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue);
1365 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue);
1369 DAG.setRoot(L.getValue(1));
1371 PendingLoads.push_back(L.getValue(1));
1377 void SelectionDAGLowering::visitStore(StoreInst &I) {
1378 Value *SrcV = I.getOperand(0);
1379 SDOperand Src = getValue(SrcV);
1380 SDOperand Ptr = getValue(I.getOperand(1));
1381 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
1382 DAG.getSrcValue(I.getOperand(1))));
1385 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1386 /// access memory and has no other side effects at all.
1387 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1388 #define GET_NO_MEMORY_INTRINSICS
1389 #include "llvm/Intrinsics.gen"
1390 #undef GET_NO_MEMORY_INTRINSICS
1394 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1395 // have any side-effects or if it only reads memory.
1396 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1397 #define GET_SIDE_EFFECT_INFO
1398 #include "llvm/Intrinsics.gen"
1399 #undef GET_SIDE_EFFECT_INFO
1403 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1405 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1406 unsigned Intrinsic) {
1407 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1408 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1410 // Build the operand list.
1411 std::vector<SDOperand> Ops;
1412 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1414 // We don't need to serialize loads against other loads.
1415 Ops.push_back(DAG.getRoot());
1417 Ops.push_back(getRoot());
1421 // Add the intrinsic ID as an integer operand.
1422 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1424 // Add all operands of the call to the operand list.
1425 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1426 SDOperand Op = getValue(I.getOperand(i));
1428 // If this is a vector type, force it to the right packed type.
1429 if (Op.getValueType() == MVT::Vector) {
1430 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1431 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1433 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1434 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1435 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1438 assert(TLI.isTypeLegal(Op.getValueType()) &&
1439 "Intrinsic uses a non-legal type?");
1443 std::vector<MVT::ValueType> VTs;
1444 if (I.getType() != Type::VoidTy) {
1445 MVT::ValueType VT = TLI.getValueType(I.getType());
1446 if (VT == MVT::Vector) {
1447 const PackedType *DestTy = cast<PackedType>(I.getType());
1448 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1450 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1451 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1454 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1458 VTs.push_back(MVT::Other);
1463 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, Ops);
1464 else if (I.getType() != Type::VoidTy)
1465 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, Ops);
1467 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
1470 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1472 PendingLoads.push_back(Chain);
1476 if (I.getType() != Type::VoidTy) {
1477 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1478 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1479 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1480 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1481 DAG.getValueType(EVT));
1483 setValue(&I, Result);
1487 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1488 /// we want to emit this as a call to a named external function, return the name
1489 /// otherwise lower it and return null.
1491 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1492 switch (Intrinsic) {
1494 // By default, turn this into a target intrinsic node.
1495 visitTargetIntrinsic(I, Intrinsic);
1497 case Intrinsic::vastart: visitVAStart(I); return 0;
1498 case Intrinsic::vaend: visitVAEnd(I); return 0;
1499 case Intrinsic::vacopy: visitVACopy(I); return 0;
1500 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1501 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1502 case Intrinsic::setjmp:
1503 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1505 case Intrinsic::longjmp:
1506 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1508 case Intrinsic::memcpy_i32:
1509 case Intrinsic::memcpy_i64:
1510 visitMemIntrinsic(I, ISD::MEMCPY);
1512 case Intrinsic::memset_i32:
1513 case Intrinsic::memset_i64:
1514 visitMemIntrinsic(I, ISD::MEMSET);
1516 case Intrinsic::memmove_i32:
1517 case Intrinsic::memmove_i64:
1518 visitMemIntrinsic(I, ISD::MEMMOVE);
1521 case Intrinsic::dbg_stoppoint: {
1522 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1523 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1524 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
1525 std::vector<SDOperand> Ops;
1527 Ops.push_back(getRoot());
1528 Ops.push_back(getValue(SPI.getLineValue()));
1529 Ops.push_back(getValue(SPI.getColumnValue()));
1531 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
1532 assert(DD && "Not a debug information descriptor");
1533 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1535 Ops.push_back(DAG.getString(CompileUnit->getFileName()));
1536 Ops.push_back(DAG.getString(CompileUnit->getDirectory()));
1538 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops));
1543 case Intrinsic::dbg_region_start: {
1544 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1545 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1546 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
1547 std::vector<SDOperand> Ops;
1549 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
1551 Ops.push_back(getRoot());
1552 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1554 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1559 case Intrinsic::dbg_region_end: {
1560 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1561 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
1562 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
1563 std::vector<SDOperand> Ops;
1565 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
1567 Ops.push_back(getRoot());
1568 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1570 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1575 case Intrinsic::dbg_func_start: {
1576 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1577 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
1578 if (DebugInfo && FSI.getSubprogram() &&
1579 DebugInfo->Verify(FSI.getSubprogram())) {
1580 std::vector<SDOperand> Ops;
1582 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
1584 Ops.push_back(getRoot());
1585 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1587 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1592 case Intrinsic::dbg_declare: {
1593 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1594 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
1595 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
1596 std::vector<SDOperand> Ops;
1598 SDOperand AddressOp = getValue(DI.getAddress());
1599 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) {
1600 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
1607 case Intrinsic::isunordered_f32:
1608 case Intrinsic::isunordered_f64:
1609 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
1610 getValue(I.getOperand(2)), ISD::SETUO));
1613 case Intrinsic::sqrt_f32:
1614 case Intrinsic::sqrt_f64:
1615 setValue(&I, DAG.getNode(ISD::FSQRT,
1616 getValue(I.getOperand(1)).getValueType(),
1617 getValue(I.getOperand(1))));
1619 case Intrinsic::pcmarker: {
1620 SDOperand Tmp = getValue(I.getOperand(1));
1621 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
1624 case Intrinsic::readcyclecounter: {
1625 std::vector<MVT::ValueType> VTs;
1626 VTs.push_back(MVT::i64);
1627 VTs.push_back(MVT::Other);
1628 std::vector<SDOperand> Ops;
1629 Ops.push_back(getRoot());
1630 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops);
1632 DAG.setRoot(Tmp.getValue(1));
1635 case Intrinsic::bswap_i16:
1636 case Intrinsic::bswap_i32:
1637 case Intrinsic::bswap_i64:
1638 setValue(&I, DAG.getNode(ISD::BSWAP,
1639 getValue(I.getOperand(1)).getValueType(),
1640 getValue(I.getOperand(1))));
1642 case Intrinsic::cttz_i8:
1643 case Intrinsic::cttz_i16:
1644 case Intrinsic::cttz_i32:
1645 case Intrinsic::cttz_i64:
1646 setValue(&I, DAG.getNode(ISD::CTTZ,
1647 getValue(I.getOperand(1)).getValueType(),
1648 getValue(I.getOperand(1))));
1650 case Intrinsic::ctlz_i8:
1651 case Intrinsic::ctlz_i16:
1652 case Intrinsic::ctlz_i32:
1653 case Intrinsic::ctlz_i64:
1654 setValue(&I, DAG.getNode(ISD::CTLZ,
1655 getValue(I.getOperand(1)).getValueType(),
1656 getValue(I.getOperand(1))));
1658 case Intrinsic::ctpop_i8:
1659 case Intrinsic::ctpop_i16:
1660 case Intrinsic::ctpop_i32:
1661 case Intrinsic::ctpop_i64:
1662 setValue(&I, DAG.getNode(ISD::CTPOP,
1663 getValue(I.getOperand(1)).getValueType(),
1664 getValue(I.getOperand(1))));
1666 case Intrinsic::stacksave: {
1667 std::vector<MVT::ValueType> VTs;
1668 VTs.push_back(TLI.getPointerTy());
1669 VTs.push_back(MVT::Other);
1670 std::vector<SDOperand> Ops;
1671 Ops.push_back(getRoot());
1672 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, Ops);
1674 DAG.setRoot(Tmp.getValue(1));
1677 case Intrinsic::stackrestore: {
1678 SDOperand Tmp = getValue(I.getOperand(1));
1679 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
1682 case Intrinsic::prefetch:
1683 // FIXME: Currently discarding prefetches.
1689 void SelectionDAGLowering::visitCall(CallInst &I) {
1690 const char *RenameFn = 0;
1691 if (Function *F = I.getCalledFunction()) {
1692 if (F->isExternal())
1693 if (unsigned IID = F->getIntrinsicID()) {
1694 RenameFn = visitIntrinsicCall(I, IID);
1697 } else { // Not an LLVM intrinsic.
1698 const std::string &Name = F->getName();
1699 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
1700 if (I.getNumOperands() == 3 && // Basic sanity checks.
1701 I.getOperand(1)->getType()->isFloatingPoint() &&
1702 I.getType() == I.getOperand(1)->getType() &&
1703 I.getType() == I.getOperand(2)->getType()) {
1704 SDOperand LHS = getValue(I.getOperand(1));
1705 SDOperand RHS = getValue(I.getOperand(2));
1706 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
1710 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
1711 if (I.getNumOperands() == 2 && // Basic sanity checks.
1712 I.getOperand(1)->getType()->isFloatingPoint() &&
1713 I.getType() == I.getOperand(1)->getType()) {
1714 SDOperand Tmp = getValue(I.getOperand(1));
1715 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
1718 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
1719 if (I.getNumOperands() == 2 && // Basic sanity checks.
1720 I.getOperand(1)->getType()->isFloatingPoint() &&
1721 I.getType() == I.getOperand(1)->getType()) {
1722 SDOperand Tmp = getValue(I.getOperand(1));
1723 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
1726 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
1727 if (I.getNumOperands() == 2 && // Basic sanity checks.
1728 I.getOperand(1)->getType()->isFloatingPoint() &&
1729 I.getType() == I.getOperand(1)->getType()) {
1730 SDOperand Tmp = getValue(I.getOperand(1));
1731 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
1736 } else if (isa<InlineAsm>(I.getOperand(0))) {
1743 Callee = getValue(I.getOperand(0));
1745 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
1746 std::vector<std::pair<SDOperand, const Type*> > Args;
1747 Args.reserve(I.getNumOperands());
1748 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1749 Value *Arg = I.getOperand(i);
1750 SDOperand ArgNode = getValue(Arg);
1751 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
1754 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
1755 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1757 std::pair<SDOperand,SDOperand> Result =
1758 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
1759 I.isTailCall(), Callee, Args, DAG);
1760 if (I.getType() != Type::VoidTy)
1761 setValue(&I, Result.first);
1762 DAG.setRoot(Result.second);
1765 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
1766 SDOperand &Chain, SDOperand &Flag)const{
1767 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
1768 Chain = Val.getValue(1);
1769 Flag = Val.getValue(2);
1771 // If the result was expanded, copy from the top part.
1772 if (Regs.size() > 1) {
1773 assert(Regs.size() == 2 &&
1774 "Cannot expand to more than 2 elts yet!");
1775 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
1776 Chain = Val.getValue(1);
1777 Flag = Val.getValue(2);
1778 if (DAG.getTargetLoweringInfo().isLittleEndian())
1779 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
1781 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
1784 // Otherwise, if the return value was promoted or extended, truncate it to the
1785 // appropriate type.
1786 if (RegVT == ValueVT)
1789 if (MVT::isInteger(RegVT)) {
1790 if (ValueVT < RegVT)
1791 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1793 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
1795 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
1799 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
1800 /// specified value into the registers specified by this object. This uses
1801 /// Chain/Flag as the input and updates them for the output Chain/Flag.
1802 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
1803 SDOperand &Chain, SDOperand &Flag) const {
1804 if (Regs.size() == 1) {
1805 // If there is a single register and the types differ, this must be
1807 if (RegVT != ValueVT) {
1808 if (MVT::isInteger(RegVT)) {
1809 if (RegVT < ValueVT)
1810 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
1812 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
1814 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
1816 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
1817 Flag = Chain.getValue(1);
1819 std::vector<unsigned> R(Regs);
1820 if (!DAG.getTargetLoweringInfo().isLittleEndian())
1821 std::reverse(R.begin(), R.end());
1823 for (unsigned i = 0, e = R.size(); i != e; ++i) {
1824 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
1825 DAG.getConstant(i, MVT::i32));
1826 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
1827 Flag = Chain.getValue(1);
1832 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
1833 /// operand list. This adds the code marker and includes the number of
1834 /// values added into it.
1835 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
1836 std::vector<SDOperand> &Ops) const {
1837 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
1838 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1839 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
1842 /// isAllocatableRegister - If the specified register is safe to allocate,
1843 /// i.e. it isn't a stack pointer or some other special register, return the
1844 /// register class for the register. Otherwise, return null.
1845 static const TargetRegisterClass *
1846 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
1847 const TargetLowering &TLI, const MRegisterInfo *MRI) {
1848 MVT::ValueType FoundVT = MVT::Other;
1849 const TargetRegisterClass *FoundRC = 0;
1850 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
1851 E = MRI->regclass_end(); RCI != E; ++RCI) {
1852 MVT::ValueType ThisVT = MVT::Other;
1854 const TargetRegisterClass *RC = *RCI;
1855 // If none of the the value types for this register class are valid, we
1856 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1857 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1859 if (TLI.isTypeLegal(*I)) {
1860 // If we have already found this register in a different register class,
1861 // choose the one with the largest VT specified. For example, on
1862 // PowerPC, we favor f64 register classes over f32.
1863 if (FoundVT == MVT::Other ||
1864 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
1871 if (ThisVT == MVT::Other) continue;
1873 // NOTE: This isn't ideal. In particular, this might allocate the
1874 // frame pointer in functions that need it (due to them not being taken
1875 // out of allocation, because a variable sized allocation hasn't been seen
1876 // yet). This is a slight code pessimization, but should still work.
1877 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
1878 E = RC->allocation_order_end(MF); I != E; ++I)
1880 // We found a matching register class. Keep looking at others in case
1881 // we find one with larger registers that this physreg is also in.
1890 RegsForValue SelectionDAGLowering::
1891 GetRegistersForValue(const std::string &ConstrCode,
1892 MVT::ValueType VT, bool isOutReg, bool isInReg,
1893 std::set<unsigned> &OutputRegs,
1894 std::set<unsigned> &InputRegs) {
1895 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
1896 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
1897 std::vector<unsigned> Regs;
1899 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
1900 MVT::ValueType RegVT;
1901 MVT::ValueType ValueVT = VT;
1903 if (PhysReg.first) {
1904 if (VT == MVT::Other)
1905 ValueVT = *PhysReg.second->vt_begin();
1907 // Get the actual register value type. This is important, because the user
1908 // may have asked for (e.g.) the AX register in i32 type. We need to
1909 // remember that AX is actually i16 to get the right extension.
1910 RegVT = *PhysReg.second->vt_begin();
1912 // This is a explicit reference to a physical register.
1913 Regs.push_back(PhysReg.first);
1915 // If this is an expanded reference, add the rest of the regs to Regs.
1917 TargetRegisterClass::iterator I = PhysReg.second->begin();
1918 TargetRegisterClass::iterator E = PhysReg.second->end();
1919 for (; *I != PhysReg.first; ++I)
1920 assert(I != E && "Didn't find reg!");
1922 // Already added the first reg.
1924 for (; NumRegs; --NumRegs, ++I) {
1925 assert(I != E && "Ran out of registers to allocate!");
1929 return RegsForValue(Regs, RegVT, ValueVT);
1932 // This is a reference to a register class. Allocate NumRegs consecutive,
1933 // available, registers from the class.
1934 std::vector<unsigned> RegClassRegs =
1935 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
1937 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
1938 MachineFunction &MF = *CurMBB->getParent();
1939 unsigned NumAllocated = 0;
1940 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
1941 unsigned Reg = RegClassRegs[i];
1942 // See if this register is available.
1943 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
1944 (isInReg && InputRegs.count(Reg))) { // Already used.
1945 // Make sure we find consecutive registers.
1950 // Check to see if this register is allocatable (i.e. don't give out the
1952 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
1954 // Make sure we find consecutive registers.
1959 // Okay, this register is good, we can use it.
1962 // If we allocated enough consecutive
1963 if (NumAllocated == NumRegs) {
1964 unsigned RegStart = (i-NumAllocated)+1;
1965 unsigned RegEnd = i+1;
1966 // Mark all of the allocated registers used.
1967 for (unsigned i = RegStart; i != RegEnd; ++i) {
1968 unsigned Reg = RegClassRegs[i];
1969 Regs.push_back(Reg);
1970 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
1971 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
1974 return RegsForValue(Regs, *RC->vt_begin(), VT);
1978 // Otherwise, we couldn't allocate enough registers for this.
1979 return RegsForValue();
1983 /// visitInlineAsm - Handle a call to an InlineAsm object.
1985 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
1986 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
1988 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
1991 // Note, we treat inline asms both with and without side-effects as the same.
1992 // If an inline asm doesn't have side effects and doesn't access memory, we
1993 // could not choose to not chain it.
1994 bool hasSideEffects = IA->hasSideEffects();
1996 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
1997 std::vector<MVT::ValueType> ConstraintVTs;
1999 /// AsmNodeOperands - A list of pairs. The first element is a register, the
2000 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
2001 /// if it is a def of that register.
2002 std::vector<SDOperand> AsmNodeOperands;
2003 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
2004 AsmNodeOperands.push_back(AsmStr);
2006 SDOperand Chain = getRoot();
2009 // We fully assign registers here at isel time. This is not optimal, but
2010 // should work. For register classes that correspond to LLVM classes, we
2011 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
2012 // over the constraints, collecting fixed registers that we know we can't use.
2013 std::set<unsigned> OutputRegs, InputRegs;
2015 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2016 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2017 std::string &ConstraintCode = Constraints[i].Codes[0];
2019 MVT::ValueType OpVT;
2021 // Compute the value type for each operand and add it to ConstraintVTs.
2022 switch (Constraints[i].Type) {
2023 case InlineAsm::isOutput:
2024 if (!Constraints[i].isIndirectOutput) {
2025 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2026 OpVT = TLI.getValueType(I.getType());
2028 const Type *OpTy = I.getOperand(OpNum)->getType();
2029 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2030 OpNum++; // Consumes a call operand.
2033 case InlineAsm::isInput:
2034 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2035 OpNum++; // Consumes a call operand.
2037 case InlineAsm::isClobber:
2042 ConstraintVTs.push_back(OpVT);
2044 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2045 continue; // Not assigned a fixed reg.
2047 // Build a list of regs that this operand uses. This always has a single
2048 // element for promoted/expanded operands.
2049 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2051 OutputRegs, InputRegs);
2053 switch (Constraints[i].Type) {
2054 case InlineAsm::isOutput:
2055 // We can't assign any other output to this register.
2056 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2057 // If this is an early-clobber output, it cannot be assigned to the same
2058 // value as the input reg.
2059 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2060 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2062 case InlineAsm::isInput:
2063 // We can't assign any other input to this register.
2064 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2066 case InlineAsm::isClobber:
2067 // Clobbered regs cannot be used as inputs or outputs.
2068 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2069 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2074 // Loop over all of the inputs, copying the operand values into the
2075 // appropriate registers and processing the output regs.
2076 RegsForValue RetValRegs;
2077 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2080 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2081 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2082 std::string &ConstraintCode = Constraints[i].Codes[0];
2084 switch (Constraints[i].Type) {
2085 case InlineAsm::isOutput: {
2086 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2087 if (ConstraintCode.size() == 1) // not a physreg name.
2088 CTy = TLI.getConstraintType(ConstraintCode[0]);
2090 if (CTy == TargetLowering::C_Memory) {
2092 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2094 // Check that the operand (the address to store to) isn't a float.
2095 if (!MVT::isInteger(InOperandVal.getValueType()))
2096 assert(0 && "MATCH FAIL!");
2098 if (!Constraints[i].isIndirectOutput)
2099 assert(0 && "MATCH FAIL!");
2101 OpNum++; // Consumes a call operand.
2103 // Extend/truncate to the right pointer type if needed.
2104 MVT::ValueType PtrType = TLI.getPointerTy();
2105 if (InOperandVal.getValueType() < PtrType)
2106 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2107 else if (InOperandVal.getValueType() > PtrType)
2108 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2110 // Add information to the INLINEASM node to know about this output.
2111 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2112 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2113 AsmNodeOperands.push_back(InOperandVal);
2117 // Otherwise, this is a register output.
2118 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2120 // If this is an early-clobber output, or if there is an input
2121 // constraint that matches this, we need to reserve the input register
2122 // so no other inputs allocate to it.
2123 bool UsesInputRegister = false;
2124 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2125 UsesInputRegister = true;
2127 // Copy the output from the appropriate register. Find a register that
2130 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2131 true, UsesInputRegister,
2132 OutputRegs, InputRegs);
2133 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
2135 if (!Constraints[i].isIndirectOutput) {
2136 assert(RetValRegs.Regs.empty() &&
2137 "Cannot have multiple output constraints yet!");
2138 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2141 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2142 I.getOperand(OpNum)));
2143 OpNum++; // Consumes a call operand.
2146 // Add information to the INLINEASM node to know that this register is
2148 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2151 case InlineAsm::isInput: {
2152 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2153 OpNum++; // Consumes a call operand.
2155 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2156 // If this is required to match an output register we have already set,
2157 // just use its register.
2158 unsigned OperandNo = atoi(ConstraintCode.c_str());
2160 // Scan until we find the definition we already emitted of this operand.
2161 // When we find it, create a RegsForValue operand.
2162 unsigned CurOp = 2; // The first operand.
2163 for (; OperandNo; --OperandNo) {
2164 // Advance to the next operand.
2166 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2167 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2168 "Skipped past definitions?");
2169 CurOp += (NumOps>>3)+1;
2173 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2174 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2175 "Skipped past definitions?");
2177 // Add NumOps>>3 registers to MatchedRegs.
2178 RegsForValue MatchedRegs;
2179 MatchedRegs.ValueVT = InOperandVal.getValueType();
2180 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2181 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2182 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2183 MatchedRegs.Regs.push_back(Reg);
2186 // Use the produced MatchedRegs object to
2187 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
2188 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2192 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2193 if (ConstraintCode.size() == 1) // not a physreg name.
2194 CTy = TLI.getConstraintType(ConstraintCode[0]);
2196 if (CTy == TargetLowering::C_Other) {
2197 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
2198 assert(0 && "MATCH FAIL!");
2200 // Add information to the INLINEASM node to know about this input.
2201 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2202 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2203 AsmNodeOperands.push_back(InOperandVal);
2205 } else if (CTy == TargetLowering::C_Memory) {
2208 // Check that the operand isn't a float.
2209 if (!MVT::isInteger(InOperandVal.getValueType()))
2210 assert(0 && "MATCH FAIL!");
2212 // Extend/truncate to the right pointer type if needed.
2213 MVT::ValueType PtrType = TLI.getPointerTy();
2214 if (InOperandVal.getValueType() < PtrType)
2215 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2216 else if (InOperandVal.getValueType() > PtrType)
2217 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2219 // Add information to the INLINEASM node to know about this input.
2220 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2221 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2222 AsmNodeOperands.push_back(InOperandVal);
2226 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2228 // Copy the input into the appropriate registers.
2229 RegsForValue InRegs =
2230 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2231 false, true, OutputRegs, InputRegs);
2232 // FIXME: should be match fail.
2233 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2235 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
2237 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2240 case InlineAsm::isClobber: {
2241 RegsForValue ClobberedRegs =
2242 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2243 OutputRegs, InputRegs);
2244 // Add the clobbered value to the operand list, so that the register
2245 // allocator is aware that the physreg got clobbered.
2246 if (!ClobberedRegs.Regs.empty())
2247 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2253 // Finish up input operands.
2254 AsmNodeOperands[0] = Chain;
2255 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2257 std::vector<MVT::ValueType> VTs;
2258 VTs.push_back(MVT::Other);
2259 VTs.push_back(MVT::Flag);
2260 Chain = DAG.getNode(ISD::INLINEASM, VTs, AsmNodeOperands);
2261 Flag = Chain.getValue(1);
2263 // If this asm returns a register value, copy the result from that register
2264 // and set it as the value of the call.
2265 if (!RetValRegs.Regs.empty())
2266 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2268 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2270 // Process indirect outputs, first output all of the flagged copies out of
2272 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2273 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2274 Value *Ptr = IndirectStoresToEmit[i].second;
2275 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2276 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2279 // Emit the non-flagged stores from the physregs.
2280 std::vector<SDOperand> OutChains;
2281 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2282 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
2283 StoresToEmit[i].first,
2284 getValue(StoresToEmit[i].second),
2285 DAG.getSrcValue(StoresToEmit[i].second)));
2286 if (!OutChains.empty())
2287 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
2292 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2293 SDOperand Src = getValue(I.getOperand(0));
2295 MVT::ValueType IntPtr = TLI.getPointerTy();
2297 if (IntPtr < Src.getValueType())
2298 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2299 else if (IntPtr > Src.getValueType())
2300 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2302 // Scale the source by the type size.
2303 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
2304 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2305 Src, getIntPtrConstant(ElementSize));
2307 std::vector<std::pair<SDOperand, const Type*> > Args;
2308 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType()));
2310 std::pair<SDOperand,SDOperand> Result =
2311 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
2312 DAG.getExternalSymbol("malloc", IntPtr),
2314 setValue(&I, Result.first); // Pointers always fit in registers
2315 DAG.setRoot(Result.second);
2318 void SelectionDAGLowering::visitFree(FreeInst &I) {
2319 std::vector<std::pair<SDOperand, const Type*> > Args;
2320 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
2321 TLI.getTargetData()->getIntPtrType()));
2322 MVT::ValueType IntPtr = TLI.getPointerTy();
2323 std::pair<SDOperand,SDOperand> Result =
2324 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
2325 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2326 DAG.setRoot(Result.second);
2329 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2330 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2331 // instructions are special in various ways, which require special support to
2332 // insert. The specified MachineInstr is created but not inserted into any
2333 // basic blocks, and the scheduler passes ownership of it to this method.
2334 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2335 MachineBasicBlock *MBB) {
2336 std::cerr << "If a target marks an instruction with "
2337 "'usesCustomDAGSchedInserter', it must implement "
2338 "TargetLowering::InsertAtEndOfBasicBlock!\n";
2343 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2344 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2345 getValue(I.getOperand(1)),
2346 DAG.getSrcValue(I.getOperand(1))));
2349 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2350 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2351 getValue(I.getOperand(0)),
2352 DAG.getSrcValue(I.getOperand(0)));
2354 DAG.setRoot(V.getValue(1));
2357 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2358 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2359 getValue(I.getOperand(1)),
2360 DAG.getSrcValue(I.getOperand(1))));
2363 void SelectionDAGLowering::visitVACopy(CallInst &I) {
2364 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2365 getValue(I.getOperand(1)),
2366 getValue(I.getOperand(2)),
2367 DAG.getSrcValue(I.getOperand(1)),
2368 DAG.getSrcValue(I.getOperand(2))));
2371 /// TargetLowering::LowerArguments - This is the default LowerArguments
2372 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
2373 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
2374 /// integrated into SDISel.
2375 std::vector<SDOperand>
2376 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2377 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2378 std::vector<SDOperand> Ops;
2379 Ops.push_back(DAG.getRoot());
2380 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2381 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2383 // Add one result value for each formal argument.
2384 std::vector<MVT::ValueType> RetVals;
2385 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2386 MVT::ValueType VT = getValueType(I->getType());
2388 switch (getTypeAction(VT)) {
2389 default: assert(0 && "Unknown type action!");
2391 RetVals.push_back(VT);
2394 RetVals.push_back(getTypeToTransformTo(VT));
2397 if (VT != MVT::Vector) {
2398 // If this is a large integer, it needs to be broken up into small
2399 // integers. Figure out what the destination type is and how many small
2400 // integers it turns into.
2401 MVT::ValueType NVT = getTypeToTransformTo(VT);
2402 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2403 for (unsigned i = 0; i != NumVals; ++i)
2404 RetVals.push_back(NVT);
2406 // Otherwise, this is a vector type. We only support legal vectors
2408 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2409 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2411 // Figure out if there is a Packed type corresponding to this Vector
2412 // type. If so, convert to the packed type.
2413 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2414 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2415 RetVals.push_back(TVT);
2417 assert(0 && "Don't support illegal by-val vector arguments yet!");
2424 RetVals.push_back(MVT::Other);
2427 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals, Ops).Val;
2429 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
2431 // Set up the return result vector.
2434 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2435 MVT::ValueType VT = getValueType(I->getType());
2437 switch (getTypeAction(VT)) {
2438 default: assert(0 && "Unknown type action!");
2440 Ops.push_back(SDOperand(Result, i++));
2443 SDOperand Op(Result, i++);
2444 if (MVT::isInteger(VT)) {
2445 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
2447 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
2448 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2450 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2451 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2457 if (VT != MVT::Vector) {
2458 // If this is a large integer, it needs to be reassembled from small
2459 // integers. Figure out what the source elt type is and how many small
2461 MVT::ValueType NVT = getTypeToTransformTo(VT);
2462 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2464 SDOperand Lo = SDOperand(Result, i++);
2465 SDOperand Hi = SDOperand(Result, i++);
2467 if (!isLittleEndian())
2470 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
2472 // Value scalarized into many values. Unimp for now.
2473 assert(0 && "Cannot expand i64 -> i16 yet!");
2476 // Otherwise, this is a vector type. We only support legal vectors
2478 const PackedType *PTy = cast<PackedType>(I->getType());
2479 unsigned NumElems = PTy->getNumElements();
2480 const Type *EltTy = PTy->getElementType();
2482 // Figure out if there is a Packed type corresponding to this Vector
2483 // type. If so, convert to the packed type.
2484 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2485 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2486 SDOperand N = SDOperand(Result, i++);
2487 // Handle copies from generic vectors to registers.
2488 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
2489 DAG.getConstant(NumElems, MVT::i32),
2490 DAG.getValueType(getValueType(EltTy)));
2493 assert(0 && "Don't support illegal by-val vector arguments yet!");
2504 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
2505 /// implementation, which just inserts an ISD::CALL node, which is later custom
2506 /// lowered by the target to something concrete. FIXME: When all targets are
2507 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
2508 std::pair<SDOperand, SDOperand>
2509 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
2510 unsigned CallingConv, bool isTailCall,
2512 ArgListTy &Args, SelectionDAG &DAG) {
2513 std::vector<SDOperand> Ops;
2514 Ops.push_back(Chain); // Op#0 - Chain
2515 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
2516 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
2517 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
2518 Ops.push_back(Callee);
2520 // Handle all of the outgoing arguments.
2521 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
2522 MVT::ValueType VT = getValueType(Args[i].second);
2523 SDOperand Op = Args[i].first;
2524 bool isSigned = Args[i].second->isSigned();
2525 switch (getTypeAction(VT)) {
2526 default: assert(0 && "Unknown type action!");
2529 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2532 if (MVT::isInteger(VT)) {
2533 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2534 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
2536 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2537 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
2540 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2543 if (VT != MVT::Vector) {
2544 // If this is a large integer, it needs to be broken down into small
2545 // integers. Figure out what the source elt type is and how many small
2547 MVT::ValueType NVT = getTypeToTransformTo(VT);
2548 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2550 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2551 DAG.getConstant(0, getPointerTy()));
2552 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2553 DAG.getConstant(1, getPointerTy()));
2554 if (!isLittleEndian())
2558 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2560 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2562 // Value scalarized into many values. Unimp for now.
2563 assert(0 && "Cannot expand i64 -> i16 yet!");
2566 // Otherwise, this is a vector type. We only support legal vectors
2568 const PackedType *PTy = cast<PackedType>(Args[i].second);
2569 unsigned NumElems = PTy->getNumElements();
2570 const Type *EltTy = PTy->getElementType();
2572 // Figure out if there is a Packed type corresponding to this Vector
2573 // type. If so, convert to the packed type.
2574 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2575 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2576 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
2577 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
2579 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2581 assert(0 && "Don't support illegal by-val vector call args yet!");
2589 // Figure out the result value types.
2590 std::vector<MVT::ValueType> RetTys;
2592 if (RetTy != Type::VoidTy) {
2593 MVT::ValueType VT = getValueType(RetTy);
2594 switch (getTypeAction(VT)) {
2595 default: assert(0 && "Unknown type action!");
2597 RetTys.push_back(VT);
2600 RetTys.push_back(getTypeToTransformTo(VT));
2603 if (VT != MVT::Vector) {
2604 // If this is a large integer, it needs to be reassembled from small
2605 // integers. Figure out what the source elt type is and how many small
2607 MVT::ValueType NVT = getTypeToTransformTo(VT);
2608 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2609 for (unsigned i = 0; i != NumVals; ++i)
2610 RetTys.push_back(NVT);
2612 // Otherwise, this is a vector type. We only support legal vectors
2614 const PackedType *PTy = cast<PackedType>(RetTy);
2615 unsigned NumElems = PTy->getNumElements();
2616 const Type *EltTy = PTy->getElementType();
2618 // Figure out if there is a Packed type corresponding to this Vector
2619 // type. If so, convert to the packed type.
2620 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2621 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2622 RetTys.push_back(TVT);
2624 assert(0 && "Don't support illegal by-val vector call results yet!");
2631 RetTys.push_back(MVT::Other); // Always has a chain.
2633 // Finally, create the CALL node.
2634 SDOperand Res = DAG.getNode(ISD::CALL, RetTys, Ops);
2636 // This returns a pair of operands. The first element is the
2637 // return value for the function (if RetTy is not VoidTy). The second
2638 // element is the outgoing token chain.
2640 if (RetTys.size() != 1) {
2641 MVT::ValueType VT = getValueType(RetTy);
2642 if (RetTys.size() == 2) {
2645 // If this value was promoted, truncate it down.
2646 if (ResVal.getValueType() != VT) {
2647 if (VT == MVT::Vector) {
2648 // Insert a VBITCONVERT to convert from the packed result type to the
2649 // MVT::Vector type.
2650 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
2651 const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
2653 // Figure out if there is a Packed type corresponding to this Vector
2654 // type. If so, convert to the packed type.
2655 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2656 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2657 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
2658 // "N x PTyElementVT" MVT::Vector type.
2659 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
2660 DAG.getConstant(NumElems, MVT::i32),
2661 DAG.getValueType(getValueType(EltTy)));
2665 } else if (MVT::isInteger(VT)) {
2666 unsigned AssertOp = RetTy->isSigned() ?
2667 ISD::AssertSext : ISD::AssertZext;
2668 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
2669 DAG.getValueType(VT));
2670 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
2672 assert(MVT::isFloatingPoint(VT));
2673 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
2676 } else if (RetTys.size() == 3) {
2677 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
2678 Res.getValue(0), Res.getValue(1));
2681 assert(0 && "Case not handled yet!");
2685 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
2690 // It is always conservatively correct for llvm.returnaddress and
2691 // llvm.frameaddress to return 0.
2693 // FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
2694 // expanded to 0 if the target wants.
2695 std::pair<SDOperand, SDOperand>
2696 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
2697 unsigned Depth, SelectionDAG &DAG) {
2698 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
2701 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2702 assert(0 && "LowerOperation not implemented for this target!");
2707 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
2708 SelectionDAG &DAG) {
2709 assert(0 && "CustomPromoteOperation not implemented for this target!");
2714 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
2715 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
2716 std::pair<SDOperand,SDOperand> Result =
2717 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
2718 setValue(&I, Result.first);
2719 DAG.setRoot(Result.second);
2722 /// getMemsetValue - Vectorized representation of the memset value
2724 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
2725 SelectionDAG &DAG) {
2726 MVT::ValueType CurVT = VT;
2727 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2728 uint64_t Val = C->getValue() & 255;
2730 while (CurVT != MVT::i8) {
2731 Val = (Val << Shift) | Val;
2733 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2735 return DAG.getConstant(Val, VT);
2737 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
2739 while (CurVT != MVT::i8) {
2741 DAG.getNode(ISD::OR, VT,
2742 DAG.getNode(ISD::SHL, VT, Value,
2743 DAG.getConstant(Shift, MVT::i8)), Value);
2745 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2752 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2753 /// used when a memcpy is turned into a memset when the source is a constant
2755 static SDOperand getMemsetStringVal(MVT::ValueType VT,
2756 SelectionDAG &DAG, TargetLowering &TLI,
2757 std::string &Str, unsigned Offset) {
2758 MVT::ValueType CurVT = VT;
2760 unsigned MSB = getSizeInBits(VT) / 8;
2761 if (TLI.isLittleEndian())
2762 Offset = Offset + MSB - 1;
2763 for (unsigned i = 0; i != MSB; ++i) {
2764 Val = (Val << 8) | Str[Offset];
2765 Offset += TLI.isLittleEndian() ? -1 : 1;
2767 return DAG.getConstant(Val, VT);
2770 /// getMemBasePlusOffset - Returns base and offset node for the
2771 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
2772 SelectionDAG &DAG, TargetLowering &TLI) {
2773 MVT::ValueType VT = Base.getValueType();
2774 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
2777 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
2778 /// to replace the memset / memcpy is below the threshold. It also returns the
2779 /// types of the sequence of memory ops to perform memset / memcpy.
2780 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
2781 unsigned Limit, uint64_t Size,
2782 unsigned Align, TargetLowering &TLI) {
2785 if (TLI.allowsUnalignedMemoryAccesses()) {
2788 switch (Align & 7) {
2804 MVT::ValueType LVT = MVT::i64;
2805 while (!TLI.isTypeLegal(LVT))
2806 LVT = (MVT::ValueType)((unsigned)LVT - 1);
2807 assert(MVT::isInteger(LVT));
2812 unsigned NumMemOps = 0;
2814 unsigned VTSize = getSizeInBits(VT) / 8;
2815 while (VTSize > Size) {
2816 VT = (MVT::ValueType)((unsigned)VT - 1);
2819 assert(MVT::isInteger(VT));
2821 if (++NumMemOps > Limit)
2823 MemOps.push_back(VT);
2830 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
2831 SDOperand Op1 = getValue(I.getOperand(1));
2832 SDOperand Op2 = getValue(I.getOperand(2));
2833 SDOperand Op3 = getValue(I.getOperand(3));
2834 SDOperand Op4 = getValue(I.getOperand(4));
2835 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
2836 if (Align == 0) Align = 1;
2838 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
2839 std::vector<MVT::ValueType> MemOps;
2841 // Expand memset / memcpy to a series of load / store ops
2842 // if the size operand falls below a certain threshold.
2843 std::vector<SDOperand> OutChains;
2845 default: break; // Do nothing for now.
2847 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
2848 Size->getValue(), Align, TLI)) {
2849 unsigned NumMemOps = MemOps.size();
2850 unsigned Offset = 0;
2851 for (unsigned i = 0; i < NumMemOps; i++) {
2852 MVT::ValueType VT = MemOps[i];
2853 unsigned VTSize = getSizeInBits(VT) / 8;
2854 SDOperand Value = getMemsetValue(Op2, VT, DAG);
2855 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(),
2857 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
2858 DAG.getSrcValue(I.getOperand(1), Offset));
2859 OutChains.push_back(Store);
2866 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
2867 Size->getValue(), Align, TLI)) {
2868 unsigned NumMemOps = MemOps.size();
2869 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
2870 GlobalAddressSDNode *G = NULL;
2872 bool CopyFromStr = false;
2874 if (Op2.getOpcode() == ISD::GlobalAddress)
2875 G = cast<GlobalAddressSDNode>(Op2);
2876 else if (Op2.getOpcode() == ISD::ADD &&
2877 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
2878 Op2.getOperand(1).getOpcode() == ISD::Constant) {
2879 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
2880 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
2883 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
2885 Str = GV->getStringValue(false);
2893 for (unsigned i = 0; i < NumMemOps; i++) {
2894 MVT::ValueType VT = MemOps[i];
2895 unsigned VTSize = getSizeInBits(VT) / 8;
2896 SDOperand Value, Chain, Store;
2899 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
2902 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2903 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2904 DAG.getSrcValue(I.getOperand(1), DstOff));
2906 Value = DAG.getLoad(VT, getRoot(),
2907 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
2908 DAG.getSrcValue(I.getOperand(2), SrcOff));
2909 Chain = Value.getValue(1);
2911 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2912 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2913 DAG.getSrcValue(I.getOperand(1), DstOff));
2915 OutChains.push_back(Store);
2924 if (!OutChains.empty()) {
2925 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
2930 std::vector<SDOperand> Ops;
2931 Ops.push_back(getRoot());
2936 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
2939 //===----------------------------------------------------------------------===//
2940 // SelectionDAGISel code
2941 //===----------------------------------------------------------------------===//
2943 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
2944 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
2947 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
2948 // FIXME: we only modify the CFG to split critical edges. This
2949 // updates dom and loop info.
2953 /// OptimizeNoopCopyExpression - We have determined that the specified cast
2954 /// instruction is a noop copy (e.g. it's casting from one pointer type to
2955 /// another, int->uint, or int->sbyte on PPC.
2957 /// Return true if any changes are made.
2958 static bool OptimizeNoopCopyExpression(CastInst *CI) {
2959 BasicBlock *DefBB = CI->getParent();
2961 /// InsertedCasts - Only insert a cast in each block once.
2962 std::map<BasicBlock*, CastInst*> InsertedCasts;
2964 bool MadeChange = false;
2965 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
2967 Use &TheUse = UI.getUse();
2968 Instruction *User = cast<Instruction>(*UI);
2970 // Figure out which BB this cast is used in. For PHI's this is the
2971 // appropriate predecessor block.
2972 BasicBlock *UserBB = User->getParent();
2973 if (PHINode *PN = dyn_cast<PHINode>(User)) {
2974 unsigned OpVal = UI.getOperandNo()/2;
2975 UserBB = PN->getIncomingBlock(OpVal);
2978 // Preincrement use iterator so we don't invalidate it.
2981 // If this user is in the same block as the cast, don't change the cast.
2982 if (UserBB == DefBB) continue;
2984 // If we have already inserted a cast into this block, use it.
2985 CastInst *&InsertedCast = InsertedCasts[UserBB];
2987 if (!InsertedCast) {
2988 BasicBlock::iterator InsertPt = UserBB->begin();
2989 while (isa<PHINode>(InsertPt)) ++InsertPt;
2992 new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
2996 // Replace a use of the cast with a use of the new casat.
2997 TheUse = InsertedCast;
3000 // If we removed all uses, nuke the cast.
3001 if (CI->use_empty())
3002 CI->eraseFromParent();
3007 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
3008 /// casting to the type of GEPI.
3009 static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
3010 Instruction *GEPI, Value *Ptr,
3012 if (V) return V; // Already computed.
3014 BasicBlock::iterator InsertPt;
3015 if (BB == GEPI->getParent()) {
3016 // If insert into the GEP's block, insert right after the GEP.
3020 // Otherwise, insert at the top of BB, after any PHI nodes
3021 InsertPt = BB->begin();
3022 while (isa<PHINode>(InsertPt)) ++InsertPt;
3025 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3026 // BB so that there is only one value live across basic blocks (the cast
3028 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3029 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3030 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3032 // Add the offset, cast it to the right type.
3033 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
3034 return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
3037 /// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3038 /// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
3039 /// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3040 /// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
3041 /// sink PtrOffset into user blocks where doing so will likely allow us to fold
3042 /// the constant add into a load or store instruction. Additionally, if a user
3043 /// is a pointer-pointer cast, we look through it to find its users.
3044 static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3045 Constant *PtrOffset, BasicBlock *DefBB,
3046 GetElementPtrInst *GEPI,
3047 std::map<BasicBlock*,Instruction*> &InsertedExprs) {
3048 while (!RepPtr->use_empty()) {
3049 Instruction *User = cast<Instruction>(RepPtr->use_back());
3051 // If the user is a Pointer-Pointer cast, recurse.
3052 if (isa<CastInst>(User) && isa<PointerType>(User->getType())) {
3053 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3055 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
3056 // could invalidate an iterator.
3057 User->setOperand(0, UndefValue::get(RepPtr->getType()));
3061 // If this is a load of the pointer, or a store through the pointer, emit
3062 // the increment into the load/store block.
3063 Instruction *NewVal;
3064 if (isa<LoadInst>(User) ||
3065 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3066 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3067 User->getParent(), GEPI,
3070 // If this use is not foldable into the addressing mode, use a version
3071 // emitted in the GEP block.
3072 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3076 if (GEPI->getType() != RepPtr->getType()) {
3077 BasicBlock::iterator IP = NewVal;
3079 NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP);
3081 User->replaceUsesOfWith(RepPtr, NewVal);
3086 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3087 /// selection, we want to be a bit careful about some things. In particular, if
3088 /// we have a GEP instruction that is used in a different block than it is
3089 /// defined, the addressing expression of the GEP cannot be folded into loads or
3090 /// stores that use it. In this case, decompose the GEP and move constant
3091 /// indices into blocks that use it.
3092 static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
3093 const TargetData *TD) {
3094 // If this GEP is only used inside the block it is defined in, there is no
3095 // need to rewrite it.
3096 bool isUsedOutsideDefBB = false;
3097 BasicBlock *DefBB = GEPI->getParent();
3098 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3100 if (cast<Instruction>(*UI)->getParent() != DefBB) {
3101 isUsedOutsideDefBB = true;
3105 if (!isUsedOutsideDefBB) return false;
3107 // If this GEP has no non-zero constant indices, there is nothing we can do,
3109 bool hasConstantIndex = false;
3110 bool hasVariableIndex = false;
3111 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3112 E = GEPI->op_end(); OI != E; ++OI) {
3113 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
3114 if (CI->getRawValue()) {
3115 hasConstantIndex = true;
3119 hasVariableIndex = true;
3123 // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3124 if (!hasConstantIndex && !hasVariableIndex) {
3125 Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(),
3126 GEPI->getName(), GEPI);
3127 GEPI->replaceAllUsesWith(NC);
3128 GEPI->eraseFromParent();
3132 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
3133 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3136 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
3137 // constant offset (which we now know is non-zero) and deal with it later.
3138 uint64_t ConstantOffset = 0;
3139 const Type *UIntPtrTy = TD->getIntPtrType();
3140 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3141 const Type *Ty = GEPI->getOperand(0)->getType();
3143 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3144 E = GEPI->op_end(); OI != E; ++OI) {
3146 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3147 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
3149 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
3150 Ty = StTy->getElementType(Field);
3152 Ty = cast<SequentialType>(Ty)->getElementType();
3154 // Handle constant subscripts.
3155 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3156 if (CI->getRawValue() == 0) continue;
3158 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
3159 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
3161 ConstantOffset+=TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
3165 // Ptr = Ptr + Idx * ElementSize;
3167 // Cast Idx to UIntPtrTy if needed.
3168 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
3170 uint64_t ElementSize = TD->getTypeSize(Ty);
3171 // Mask off bits that should not be set.
3172 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3173 Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize);
3175 // Multiply by the element size and add to the base.
3176 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3177 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3181 // Make sure that the offset fits in uintptr_t.
3182 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3183 Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset);
3185 // Okay, we have now emitted all of the variable index parts to the BB that
3186 // the GEP is defined in. Loop over all of the using instructions, inserting
3187 // an "add Ptr, ConstantOffset" into each block that uses it and update the
3188 // instruction to use the newly computed value, making GEPI dead. When the
3189 // user is a load or store instruction address, we emit the add into the user
3190 // block, otherwise we use a canonical version right next to the gep (these
3191 // won't be foldable as addresses, so we might as well share the computation).
3193 std::map<BasicBlock*,Instruction*> InsertedExprs;
3194 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3196 // Finally, the GEP is dead, remove it.
3197 GEPI->eraseFromParent();
3202 bool SelectionDAGISel::runOnFunction(Function &Fn) {
3203 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3204 RegMap = MF.getSSARegMap();
3205 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
3207 // First, split all critical edges for PHI nodes with incoming values that are
3208 // constants, this way the load of the constant into a vreg will not be placed
3209 // into MBBs that are used some other way.
3211 // In this pass we also look for GEP and cast instructions that are used
3212 // across basic blocks and rewrite them to improve basic-block-at-a-time
3216 bool MadeChange = true;
3217 while (MadeChange) {
3219 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
3221 BasicBlock::iterator BBI;
3222 for (BBI = BB->begin(); (PN = dyn_cast<PHINode>(BBI)); ++BBI)
3223 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
3224 if (isa<Constant>(PN->getIncomingValue(i)))
3225 SplitCriticalEdge(PN->getIncomingBlock(i), BB);
3227 for (BasicBlock::iterator E = BB->end(); BBI != E; ) {
3228 Instruction *I = BBI++;
3229 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
3230 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
3231 } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
3232 // If this is a noop copy, sink it into user blocks to reduce the number
3233 // of virtual registers that must be created and coallesced.
3234 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
3235 MVT::ValueType DstVT = TLI.getValueType(CI->getType());
3237 // This is an fp<->int conversion?
3238 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
3241 // If this is an extension, it will be a zero or sign extension, which
3243 if (SrcVT < DstVT) continue;
3245 // If these values will be promoted, find out what they will be promoted
3246 // to. This helps us consider truncates on PPC as noop copies when they
3248 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
3249 SrcVT = TLI.getTypeToTransformTo(SrcVT);
3250 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
3251 DstVT = TLI.getTypeToTransformTo(DstVT);
3253 // If, after promotion, these are the same types, this is a noop copy.
3255 MadeChange |= OptimizeNoopCopyExpression(CI);
3261 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
3263 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
3264 SelectBasicBlock(I, MF, FuncInfo);
3270 SDOperand SelectionDAGISel::
3271 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
3272 SDOperand Op = SDL.getValue(V);
3273 assert((Op.getOpcode() != ISD::CopyFromReg ||
3274 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
3275 "Copy from a reg to the same reg!");
3277 // If this type is not legal, we must make sure to not create an invalid
3279 MVT::ValueType SrcVT = Op.getValueType();
3280 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
3281 SelectionDAG &DAG = SDL.DAG;
3282 if (SrcVT == DestVT) {
3283 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3284 } else if (SrcVT == MVT::Vector) {
3285 // Handle copies from generic vectors to registers.
3286 MVT::ValueType PTyElementVT, PTyLegalElementVT;
3287 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
3288 PTyElementVT, PTyLegalElementVT);
3290 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
3291 // MVT::Vector type.
3292 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
3293 DAG.getConstant(NE, MVT::i32),
3294 DAG.getValueType(PTyElementVT));
3296 // Loop over all of the elements of the resultant vector,
3297 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
3298 // copying them into output registers.
3299 std::vector<SDOperand> OutChains;
3300 SDOperand Root = SDL.getRoot();
3301 for (unsigned i = 0; i != NE; ++i) {
3302 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
3303 Op, DAG.getConstant(i, MVT::i32));
3304 if (PTyElementVT == PTyLegalElementVT) {
3305 // Elements are legal.
3306 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3307 } else if (PTyLegalElementVT > PTyElementVT) {
3308 // Elements are promoted.
3309 if (MVT::isFloatingPoint(PTyLegalElementVT))
3310 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
3312 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
3313 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3315 // Elements are expanded.
3316 // The src value is expanded into multiple registers.
3317 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3318 Elt, DAG.getConstant(0, MVT::i32));
3319 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3320 Elt, DAG.getConstant(1, MVT::i32));
3321 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
3322 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
3325 return DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
3326 } else if (SrcVT < DestVT) {
3327 // The src value is promoted to the register.
3328 if (MVT::isFloatingPoint(SrcVT))
3329 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
3331 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
3332 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3334 // The src value is expanded into multiple registers.
3335 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3336 Op, DAG.getConstant(0, MVT::i32));
3337 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3338 Op, DAG.getConstant(1, MVT::i32));
3339 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
3340 return DAG.getCopyToReg(Op, Reg+1, Hi);
3344 void SelectionDAGISel::
3345 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
3346 std::vector<SDOperand> &UnorderedChains) {
3347 // If this is the entry block, emit arguments.
3348 Function &F = *BB->getParent();
3349 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
3350 SDOperand OldRoot = SDL.DAG.getRoot();
3351 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
3354 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
3356 if (!AI->use_empty()) {
3357 SDL.setValue(AI, Args[a]);
3359 // If this argument is live outside of the entry block, insert a copy from
3360 // whereever we got it to the vreg that other BB's will reference it as.
3361 if (FuncInfo.ValueMap.count(AI)) {
3363 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
3364 UnorderedChains.push_back(Copy);
3368 // Finally, if the target has anything special to do, allow it to do so.
3369 // FIXME: this should insert code into the DAG!
3370 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
3373 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3374 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
3375 FunctionLoweringInfo &FuncInfo) {
3376 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
3378 std::vector<SDOperand> UnorderedChains;
3380 // Lower any arguments needed in this block if this is the entry block.
3381 if (LLVMBB == &LLVMBB->getParent()->front())
3382 LowerArguments(LLVMBB, SDL, UnorderedChains);
3384 BB = FuncInfo.MBBMap[LLVMBB];
3385 SDL.setCurrentBasicBlock(BB);
3387 // Lower all of the non-terminator instructions.
3388 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3392 // Ensure that all instructions which are used outside of their defining
3393 // blocks are available as virtual registers.
3394 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
3395 if (!I->use_empty() && !isa<PHINode>(I)) {
3396 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
3397 if (VMI != FuncInfo.ValueMap.end())
3398 UnorderedChains.push_back(
3399 CopyValueToVirtualRegister(SDL, I, VMI->second));
3402 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
3403 // ensure constants are generated when needed. Remember the virtual registers
3404 // that need to be added to the Machine PHI nodes as input. We cannot just
3405 // directly add them, because expansion might result in multiple MBB's for one
3406 // BB. As such, the start of the BB might correspond to a different MBB than
3410 // Emit constants only once even if used by multiple PHI nodes.
3411 std::map<Constant*, unsigned> ConstantsOut;
3413 // Check successor nodes PHI nodes that expect a constant to be available from
3415 TerminatorInst *TI = LLVMBB->getTerminator();
3416 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
3417 BasicBlock *SuccBB = TI->getSuccessor(succ);
3418 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
3421 // At this point we know that there is a 1-1 correspondence between LLVM PHI
3422 // nodes and Machine PHI nodes, but the incoming operands have not been
3424 for (BasicBlock::iterator I = SuccBB->begin();
3425 (PN = dyn_cast<PHINode>(I)); ++I)
3426 if (!PN->use_empty()) {
3428 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
3429 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
3430 unsigned &RegOut = ConstantsOut[C];
3432 RegOut = FuncInfo.CreateRegForValue(C);
3433 UnorderedChains.push_back(
3434 CopyValueToVirtualRegister(SDL, C, RegOut));
3438 Reg = FuncInfo.ValueMap[PHIOp];
3440 assert(isa<AllocaInst>(PHIOp) &&
3441 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
3442 "Didn't codegen value into a register!??");
3443 Reg = FuncInfo.CreateRegForValue(PHIOp);
3444 UnorderedChains.push_back(
3445 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
3449 // Remember that this register needs to added to the machine PHI node as
3450 // the input for this MBB.
3451 MVT::ValueType VT = TLI.getValueType(PN->getType());
3452 unsigned NumElements;
3453 if (VT != MVT::Vector)
3454 NumElements = TLI.getNumElements(VT);
3456 MVT::ValueType VT1,VT2;
3458 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
3461 for (unsigned i = 0, e = NumElements; i != e; ++i)
3462 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
3465 ConstantsOut.clear();
3467 // Turn all of the unordered chains into one factored node.
3468 if (!UnorderedChains.empty()) {
3469 SDOperand Root = SDL.getRoot();
3470 if (Root.getOpcode() != ISD::EntryToken) {
3471 unsigned i = 0, e = UnorderedChains.size();
3472 for (; i != e; ++i) {
3473 assert(UnorderedChains[i].Val->getNumOperands() > 1);
3474 if (UnorderedChains[i].Val->getOperand(0) == Root)
3475 break; // Don't add the root if we already indirectly depend on it.
3479 UnorderedChains.push_back(Root);
3481 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
3484 // Lower the terminator after the copies are emitted.
3485 SDL.visit(*LLVMBB->getTerminator());
3487 // Copy over any CaseBlock records that may now exist due to SwitchInst
3488 // lowering, as well as any jump table information.
3489 SwitchCases.clear();
3490 SwitchCases = SDL.SwitchCases;
3493 // Make sure the root of the DAG is up-to-date.
3494 DAG.setRoot(SDL.getRoot());
3497 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
3498 // Run the DAG combiner in pre-legalize mode.
3501 DEBUG(std::cerr << "Lowered selection DAG:\n");
3504 // Second step, hack on the DAG until it only uses operations and types that
3505 // the target supports.
3508 DEBUG(std::cerr << "Legalized selection DAG:\n");
3511 // Run the DAG combiner in post-legalize mode.
3514 if (ViewISelDAGs) DAG.viewGraph();
3516 // Third, instruction select all of the operations to machine code, adding the
3517 // code to the MachineBasicBlock.
3518 InstructionSelectBasicBlock(DAG);
3520 DEBUG(std::cerr << "Selected machine code:\n");
3524 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
3525 FunctionLoweringInfo &FuncInfo) {
3526 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
3528 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3531 // First step, lower LLVM code to some DAG. This DAG may use operations and
3532 // types that are not supported by the target.
3533 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
3535 // Second step, emit the lowered DAG as machine code.
3536 CodeGenAndEmitDAG(DAG);
3539 // Next, now that we know what the last MBB the LLVM BB expanded is, update
3540 // PHI nodes in successors.
3541 if (SwitchCases.empty() && JT.Reg == 0) {
3542 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3543 MachineInstr *PHI = PHINodesToUpdate[i].first;
3544 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3545 "This is not a machine PHI node that we are updating!");
3546 PHI->addRegOperand(PHINodesToUpdate[i].second);
3547 PHI->addMachineBasicBlockOperand(BB);
3552 // If the JumpTable record is filled in, then we need to emit a jump table.
3553 // Updating the PHI nodes is tricky in this case, since we need to determine
3554 // whether the PHI is a successor of the range check MBB or the jump table MBB
3556 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
3557 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3559 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3560 MachineBasicBlock *RangeBB = BB;
3561 // Set the current basic block to the mbb we wish to insert the code into
3563 SDL.setCurrentBasicBlock(BB);
3565 SDL.visitJumpTable(JT);
3566 SDAG.setRoot(SDL.getRoot());
3567 CodeGenAndEmitDAG(SDAG);
3569 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3570 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3571 MachineBasicBlock *PHIBB = PHI->getParent();
3572 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3573 "This is not a machine PHI node that we are updating!");
3574 if (PHIBB == JT.Default) {
3575 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3576 PHI->addMachineBasicBlockOperand(RangeBB);
3578 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
3579 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3580 PHI->addMachineBasicBlockOperand(BB);
3586 // If we generated any switch lowering information, build and codegen any
3587 // additional DAGs necessary.
3588 for(unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
3589 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3591 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3592 // Set the current basic block to the mbb we wish to insert the code into
3593 BB = SwitchCases[i].ThisBB;
3594 SDL.setCurrentBasicBlock(BB);
3596 SDL.visitSwitchCase(SwitchCases[i]);
3597 SDAG.setRoot(SDL.getRoot());
3598 CodeGenAndEmitDAG(SDAG);
3599 // Iterate over the phi nodes, if there is a phi node in a successor of this
3600 // block (for instance, the default block), then add a pair of operands to
3601 // the phi node for this block, as if we were coming from the original
3602 // BB before switch expansion.
3603 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3604 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3605 MachineBasicBlock *PHIBB = PHI->getParent();
3606 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3607 "This is not a machine PHI node that we are updating!");
3608 if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
3609 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3610 PHI->addMachineBasicBlockOperand(BB);
3616 //===----------------------------------------------------------------------===//
3617 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
3618 /// target node in the graph.
3619 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
3620 if (ViewSchedDAGs) DAG.viewGraph();
3621 ScheduleDAG *SL = NULL;
3623 switch (ISHeuristic) {
3624 default: assert(0 && "Unrecognized scheduling heuristic");
3625 case defaultScheduling:
3626 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
3627 SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
3629 assert(TLI.getSchedulingPreference() ==
3630 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
3631 SL = createBURRListDAGScheduler(DAG, BB);
3635 SL = createBFS_DAGScheduler(DAG, BB);
3637 case simpleScheduling:
3638 SL = createSimpleDAGScheduler(false, DAG, BB);
3640 case simpleNoItinScheduling:
3641 SL = createSimpleDAGScheduler(true, DAG, BB);
3643 case listSchedulingBURR:
3644 SL = createBURRListDAGScheduler(DAG, BB);
3646 case listSchedulingTDRR:
3647 SL = createTDRRListDAGScheduler(DAG, BB);
3649 case listSchedulingTD:
3650 SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
3657 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
3658 return new HazardRecognizer();
3661 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
3662 /// by tblgen. Others should not call it.
3663 void SelectionDAGISel::
3664 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
3665 std::vector<SDOperand> InOps;
3666 std::swap(InOps, Ops);
3668 Ops.push_back(InOps[0]); // input chain.
3669 Ops.push_back(InOps[1]); // input asm string.
3671 unsigned i = 2, e = InOps.size();
3672 if (InOps[e-1].getValueType() == MVT::Flag)
3673 --e; // Don't process a flag operand if it is here.
3676 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
3677 if ((Flags & 7) != 4 /*MEM*/) {
3678 // Just skip over this operand, copying the operands verbatim.
3679 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
3680 i += (Flags >> 3) + 1;
3682 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
3683 // Otherwise, this is a memory operand. Ask the target to select it.
3684 std::vector<SDOperand> SelOps;
3685 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
3686 std::cerr << "Could not match memory address. Inline asm failure!\n";
3690 // Add this to the output node.
3691 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
3692 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
3697 // Add the flag input back if present.
3698 if (e != InOps.size())
3699 Ops.push_back(InOps.back());