1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/CodeGen/ScheduleDAG.h"
17 #include "llvm/CallingConv.h"
18 #include "llvm/Constants.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/InlineAsm.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineDebugInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/CodeGen/SSARegMap.h"
34 #include "llvm/Target/MRegisterInfo.h"
35 #include "llvm/Target/TargetData.h"
36 #include "llvm/Target/TargetFrameInfo.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetLowering.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/Visibility.h"
54 ViewISelDAGs("view-isel-dags", cl::Hidden,
55 cl::desc("Pop up a window to show isel dags as they are selected"));
57 ViewSchedDAGs("view-sched-dags", cl::Hidden,
58 cl::desc("Pop up a window to show sched dags as they are processed"));
60 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
63 // Scheduling heuristics
64 enum SchedHeuristics {
65 defaultScheduling, // Let the target specify its preference.
66 noScheduling, // No scheduling, emit breadth first sequence.
67 simpleScheduling, // Two pass, min. critical path, max. utilization.
68 simpleNoItinScheduling, // Same as above exact using generic latency.
69 listSchedulingBURR, // Bottom-up reg reduction list scheduling.
70 listSchedulingTDRR, // Top-down reg reduction list scheduling.
71 listSchedulingTD // Top-down list scheduler.
75 cl::opt<SchedHeuristics>
78 cl::desc("Choose scheduling style"),
79 cl::init(defaultScheduling),
81 clEnumValN(defaultScheduling, "default",
82 "Target preferred scheduling style"),
83 clEnumValN(noScheduling, "none",
84 "No scheduling: breadth first sequencing"),
85 clEnumValN(simpleScheduling, "simple",
86 "Simple two pass scheduling: minimize critical path "
87 "and maximize processor utilization"),
88 clEnumValN(simpleNoItinScheduling, "simple-noitin",
89 "Simple two pass scheduling: Same as simple "
90 "except using generic latency"),
91 clEnumValN(listSchedulingBURR, "list-burr",
92 "Bottom-up register reduction list scheduling"),
93 clEnumValN(listSchedulingTDRR, "list-tdrr",
94 "Top-down register reduction list scheduling"),
95 clEnumValN(listSchedulingTD, "list-td",
96 "Top-down list scheduler"),
101 /// RegsForValue - This struct represents the physical registers that a
102 /// particular value is assigned and the type information about the value.
103 /// This is needed because values can be promoted into larger registers and
104 /// expanded into multiple smaller registers than the value.
105 struct VISIBILITY_HIDDEN RegsForValue {
106 /// Regs - This list hold the register (for legal and promoted values)
107 /// or register set (for expanded values) that the value should be assigned
109 std::vector<unsigned> Regs;
111 /// RegVT - The value type of each register.
113 MVT::ValueType RegVT;
115 /// ValueVT - The value type of the LLVM value, which may be promoted from
116 /// RegVT or made from merging the two expanded parts.
117 MVT::ValueType ValueVT;
119 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
121 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
122 : RegVT(regvt), ValueVT(valuevt) {
125 RegsForValue(const std::vector<unsigned> ®s,
126 MVT::ValueType regvt, MVT::ValueType valuevt)
127 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
130 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
131 /// this value and returns the result as a ValueVT value. This uses
132 /// Chain/Flag as the input and updates them for the output Chain/Flag.
133 SDOperand getCopyFromRegs(SelectionDAG &DAG,
134 SDOperand &Chain, SDOperand &Flag) const;
136 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
137 /// specified value into the registers specified by this object. This uses
138 /// Chain/Flag as the input and updates them for the output Chain/Flag.
139 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
140 SDOperand &Chain, SDOperand &Flag,
141 MVT::ValueType PtrVT) const;
143 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
144 /// operand list. This adds the code marker and includes the number of
145 /// values added into it.
146 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
147 std::vector<SDOperand> &Ops) const;
152 //===--------------------------------------------------------------------===//
153 /// FunctionLoweringInfo - This contains information that is global to a
154 /// function that is used when lowering a region of the function.
155 class FunctionLoweringInfo {
162 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
164 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
165 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
167 /// ValueMap - Since we emit code for the function a basic block at a time,
168 /// we must remember which virtual registers hold the values for
169 /// cross-basic-block values.
170 std::map<const Value*, unsigned> ValueMap;
172 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
173 /// the entry block. This allows the allocas to be efficiently referenced
174 /// anywhere in the function.
175 std::map<const AllocaInst*, int> StaticAllocaMap;
177 unsigned MakeReg(MVT::ValueType VT) {
178 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
181 unsigned CreateRegForValue(const Value *V);
183 unsigned InitializeRegForValue(const Value *V) {
184 unsigned &R = ValueMap[V];
185 assert(R == 0 && "Already initialized this value register!");
186 return R = CreateRegForValue(V);
191 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
192 /// PHI nodes or outside of the basic block that defines it, or used by a
193 /// switch instruction, which may expand to multiple basic blocks.
194 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
195 if (isa<PHINode>(I)) return true;
196 BasicBlock *BB = I->getParent();
197 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
198 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
199 isa<SwitchInst>(*UI))
204 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
205 /// entry block, return true. This includes arguments used by switches, since
206 /// the switch may expand into multiple basic blocks.
207 static bool isOnlyUsedInEntryBlock(Argument *A) {
208 BasicBlock *Entry = A->getParent()->begin();
209 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
210 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
211 return false; // Use not in entry block.
215 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
216 Function &fn, MachineFunction &mf)
217 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
219 // Create a vreg for each argument register that is not dead and is used
220 // outside of the entry block for the function.
221 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
223 if (!isOnlyUsedInEntryBlock(AI))
224 InitializeRegForValue(AI);
226 // Initialize the mapping of values to registers. This is only set up for
227 // instruction values that are used outside of the block that defines
229 Function::iterator BB = Fn.begin(), EB = Fn.end();
230 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
231 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
232 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
233 const Type *Ty = AI->getAllocatedType();
234 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
236 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
239 // If the alignment of the value is smaller than the size of the value,
240 // and if the size of the value is particularly small (<= 8 bytes),
241 // round up to the size of the value for potentially better performance.
243 // FIXME: This could be made better with a preferred alignment hook in
244 // TargetData. It serves primarily to 8-byte align doubles for X86.
245 if (Align < TySize && TySize <= 8) Align = TySize;
246 TySize *= CUI->getValue(); // Get total allocated size.
247 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
248 StaticAllocaMap[AI] =
249 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
252 for (; BB != EB; ++BB)
253 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
254 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
255 if (!isa<AllocaInst>(I) ||
256 !StaticAllocaMap.count(cast<AllocaInst>(I)))
257 InitializeRegForValue(I);
259 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
260 // also creates the initial PHI MachineInstrs, though none of the input
261 // operands are populated.
262 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
263 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
265 MF.getBasicBlockList().push_back(MBB);
267 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
270 for (BasicBlock::iterator I = BB->begin();
271 (PN = dyn_cast<PHINode>(I)); ++I)
272 if (!PN->use_empty()) {
273 MVT::ValueType VT = TLI.getValueType(PN->getType());
274 unsigned NumElements;
275 if (VT != MVT::Vector)
276 NumElements = TLI.getNumElements(VT);
278 MVT::ValueType VT1,VT2;
280 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
283 unsigned PHIReg = ValueMap[PN];
284 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
285 for (unsigned i = 0; i != NumElements; ++i)
286 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
291 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
292 /// the correctly promoted or expanded types. Assign these registers
293 /// consecutive vreg numbers and return the first assigned number.
294 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
295 MVT::ValueType VT = TLI.getValueType(V->getType());
297 // The number of multiples of registers that we need, to, e.g., split up
298 // a <2 x int64> -> 4 x i32 registers.
299 unsigned NumVectorRegs = 1;
301 // If this is a packed type, figure out what type it will decompose into
302 // and how many of the elements it will use.
303 if (VT == MVT::Vector) {
304 const PackedType *PTy = cast<PackedType>(V->getType());
305 unsigned NumElts = PTy->getNumElements();
306 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
308 // Divide the input until we get to a supported size. This will always
309 // end with a scalar if the target doesn't support vectors.
310 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
317 VT = getVectorType(EltTy, NumElts);
320 // The common case is that we will only create one register for this
321 // value. If we have that case, create and return the virtual register.
322 unsigned NV = TLI.getNumElements(VT);
324 // If we are promoting this value, pick the next largest supported type.
325 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
326 unsigned Reg = MakeReg(PromotedType);
327 // If this is a vector of supported or promoted types (e.g. 4 x i16),
328 // create all of the registers.
329 for (unsigned i = 1; i != NumVectorRegs; ++i)
330 MakeReg(PromotedType);
334 // If this value is represented with multiple target registers, make sure
335 // to create enough consecutive registers of the right (smaller) type.
336 unsigned NT = VT-1; // Find the type to use.
337 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
340 unsigned R = MakeReg((MVT::ValueType)NT);
341 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
342 MakeReg((MVT::ValueType)NT);
346 //===----------------------------------------------------------------------===//
347 /// SelectionDAGLowering - This is the common target-independent lowering
348 /// implementation that is parameterized by a TargetLowering object.
349 /// Also, targets can overload any lowering method.
352 class SelectionDAGLowering {
353 MachineBasicBlock *CurMBB;
355 std::map<const Value*, SDOperand> NodeMap;
357 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
358 /// them up and then emit token factor nodes when possible. This allows us to
359 /// get simple disambiguation between loads without worrying about alias
361 std::vector<SDOperand> PendingLoads;
363 /// Case - A pair of values to record the Value for a switch case, and the
364 /// case's target basic block.
365 typedef std::pair<Constant*, MachineBasicBlock*> Case;
366 typedef std::vector<Case>::iterator CaseItr;
367 typedef std::pair<CaseItr, CaseItr> CaseRange;
369 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
370 /// of conditional branches.
372 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
373 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
375 /// CaseBB - The MBB in which to emit the compare and branch
376 MachineBasicBlock *CaseBB;
377 /// LT, GE - If nonzero, we know the current case value must be less-than or
378 /// greater-than-or-equal-to these Constants.
381 /// Range - A pair of iterators representing the range of case values to be
382 /// processed at this point in the binary search tree.
386 /// The comparison function for sorting Case values.
388 bool operator () (const Case& C1, const Case& C2) {
389 if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first))
390 return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue();
392 const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first);
393 return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue();
398 // TLI - This is information that describes the available target features we
399 // need for lowering. This indicates when operations are unavailable,
400 // implemented with a libcall, etc.
403 const TargetData *TD;
405 /// SwitchCases - Vector of CaseBlock structures used to communicate
406 /// SwitchInst code generation information.
407 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
408 SelectionDAGISel::JumpTable JT;
410 /// FuncInfo - Information about the function as a whole.
412 FunctionLoweringInfo &FuncInfo;
414 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
415 FunctionLoweringInfo &funcinfo)
416 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
417 JT(0,0,0,0), FuncInfo(funcinfo) {
420 /// getRoot - Return the current virtual root of the Selection DAG.
422 SDOperand getRoot() {
423 if (PendingLoads.empty())
424 return DAG.getRoot();
426 if (PendingLoads.size() == 1) {
427 SDOperand Root = PendingLoads[0];
429 PendingLoads.clear();
433 // Otherwise, we have to make a token factor node.
434 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
435 PendingLoads.clear();
440 void visit(Instruction &I) { visit(I.getOpcode(), I); }
442 void visit(unsigned Opcode, User &I) {
444 default: assert(0 && "Unknown instruction type encountered!");
446 // Build the switch statement using the Instruction.def file.
447 #define HANDLE_INST(NUM, OPCODE, CLASS) \
448 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
449 #include "llvm/Instruction.def"
453 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
455 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
456 SDOperand SrcValue, SDOperand Root,
459 SDOperand getIntPtrConstant(uint64_t Val) {
460 return DAG.getConstant(Val, TLI.getPointerTy());
463 SDOperand getValue(const Value *V);
465 const SDOperand &setValue(const Value *V, SDOperand NewN) {
466 SDOperand &N = NodeMap[V];
467 assert(N.Val == 0 && "Already set a value for this node!");
471 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
473 bool OutReg, bool InReg,
474 std::set<unsigned> &OutputRegs,
475 std::set<unsigned> &InputRegs);
477 // Terminator instructions.
478 void visitRet(ReturnInst &I);
479 void visitBr(BranchInst &I);
480 void visitSwitch(SwitchInst &I);
481 void visitUnreachable(UnreachableInst &I) { /* noop */ }
483 // Helper for visitSwitch
484 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
485 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
487 // These all get lowered before this pass.
488 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
489 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
491 void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
492 void visitShift(User &I, unsigned Opcode);
493 void visitAdd(User &I) {
494 visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
496 void visitSub(User &I);
497 void visitMul(User &I) {
498 visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
500 void visitDiv(User &I) {
501 const Type *Ty = I.getType();
503 Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
504 Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
506 void visitRem(User &I) {
507 const Type *Ty = I.getType();
508 visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
510 void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
511 void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
512 void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
513 void visitShl(User &I) { visitShift(I, ISD::SHL); }
514 void visitShr(User &I) {
515 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
518 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc,
519 ISD::CondCode FPOpc);
520 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ,
522 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE,
524 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE,
526 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE,
528 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT,
530 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT,
533 void visitExtractElement(User &I);
534 void visitInsertElement(User &I);
535 void visitShuffleVector(User &I);
537 void visitGetElementPtr(User &I);
538 void visitCast(User &I);
539 void visitSelect(User &I);
541 void visitMalloc(MallocInst &I);
542 void visitFree(FreeInst &I);
543 void visitAlloca(AllocaInst &I);
544 void visitLoad(LoadInst &I);
545 void visitStore(StoreInst &I);
546 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
547 void visitCall(CallInst &I);
548 void visitInlineAsm(CallInst &I);
549 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
550 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
552 void visitVAStart(CallInst &I);
553 void visitVAArg(VAArgInst &I);
554 void visitVAEnd(CallInst &I);
555 void visitVACopy(CallInst &I);
556 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
558 void visitMemIntrinsic(CallInst &I, unsigned Op);
560 void visitUserOp1(Instruction &I) {
561 assert(0 && "UserOp1 should not exist at instruction selection time!");
564 void visitUserOp2(Instruction &I) {
565 assert(0 && "UserOp2 should not exist at instruction selection time!");
569 } // end namespace llvm
571 SDOperand SelectionDAGLowering::getValue(const Value *V) {
572 SDOperand &N = NodeMap[V];
575 const Type *VTy = V->getType();
576 MVT::ValueType VT = TLI.getValueType(VTy);
577 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
578 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
579 visit(CE->getOpcode(), *CE);
580 assert(N.Val && "visit didn't populate the ValueMap!");
582 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
583 return N = DAG.getGlobalAddress(GV, VT);
584 } else if (isa<ConstantPointerNull>(C)) {
585 return N = DAG.getConstant(0, TLI.getPointerTy());
586 } else if (isa<UndefValue>(C)) {
587 if (!isa<PackedType>(VTy))
588 return N = DAG.getNode(ISD::UNDEF, VT);
590 // Create a VBUILD_VECTOR of undef nodes.
591 const PackedType *PTy = cast<PackedType>(VTy);
592 unsigned NumElements = PTy->getNumElements();
593 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
595 std::vector<SDOperand> Ops;
596 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
598 // Create a VConstant node with generic Vector type.
599 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
600 Ops.push_back(DAG.getValueType(PVT));
601 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
602 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
603 return N = DAG.getConstantFP(CFP->getValue(), VT);
604 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
605 unsigned NumElements = PTy->getNumElements();
606 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
608 // Now that we know the number and type of the elements, push a
609 // Constant or ConstantFP node onto the ops list for each element of
610 // the packed constant.
611 std::vector<SDOperand> Ops;
612 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
613 for (unsigned i = 0; i != NumElements; ++i)
614 Ops.push_back(getValue(CP->getOperand(i)));
616 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
618 if (MVT::isFloatingPoint(PVT))
619 Op = DAG.getConstantFP(0, PVT);
621 Op = DAG.getConstant(0, PVT);
622 Ops.assign(NumElements, Op);
625 // Create a VBUILD_VECTOR node with generic Vector type.
626 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
627 Ops.push_back(DAG.getValueType(PVT));
628 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
630 // Canonicalize all constant ints to be unsigned.
631 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
635 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
636 std::map<const AllocaInst*, int>::iterator SI =
637 FuncInfo.StaticAllocaMap.find(AI);
638 if (SI != FuncInfo.StaticAllocaMap.end())
639 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
642 std::map<const Value*, unsigned>::const_iterator VMI =
643 FuncInfo.ValueMap.find(V);
644 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
646 unsigned InReg = VMI->second;
648 // If this type is not legal, make it so now.
649 if (VT != MVT::Vector) {
650 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
652 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
654 // Source must be expanded. This input value is actually coming from the
655 // register pair VMI->second and VMI->second+1.
656 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
657 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
658 } else if (DestVT > VT) { // Promotion case
659 if (MVT::isFloatingPoint(VT))
660 N = DAG.getNode(ISD::FP_ROUND, VT, N);
662 N = DAG.getNode(ISD::TRUNCATE, VT, N);
665 // Otherwise, if this is a vector, make it available as a generic vector
667 MVT::ValueType PTyElementVT, PTyLegalElementVT;
668 const PackedType *PTy = cast<PackedType>(VTy);
669 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
672 // Build a VBUILD_VECTOR with the input registers.
673 std::vector<SDOperand> Ops;
674 if (PTyElementVT == PTyLegalElementVT) {
675 // If the value types are legal, just VBUILD the CopyFromReg nodes.
676 for (unsigned i = 0; i != NE; ++i)
677 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
679 } else if (PTyElementVT < PTyLegalElementVT) {
680 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
681 for (unsigned i = 0; i != NE; ++i) {
682 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
684 if (MVT::isFloatingPoint(PTyElementVT))
685 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
687 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
691 // If the register was expanded, use BUILD_PAIR.
692 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
693 for (unsigned i = 0; i != NE/2; ++i) {
694 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
696 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
698 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
702 Ops.push_back(DAG.getConstant(NE, MVT::i32));
703 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
704 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
706 // Finally, use a VBIT_CONVERT to make this available as the appropriate
708 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
709 DAG.getConstant(PTy->getNumElements(),
711 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
718 void SelectionDAGLowering::visitRet(ReturnInst &I) {
719 if (I.getNumOperands() == 0) {
720 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
723 std::vector<SDOperand> NewValues;
724 NewValues.push_back(getRoot());
725 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
726 SDOperand RetOp = getValue(I.getOperand(i));
727 bool isSigned = I.getOperand(i)->getType()->isSigned();
729 // If this is an integer return value, we need to promote it ourselves to
730 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
732 // FIXME: C calling convention requires the return type to be promoted to
733 // at least 32-bit. But this is not necessary for non-C calling conventions.
734 if (MVT::isInteger(RetOp.getValueType()) &&
735 RetOp.getValueType() < MVT::i64) {
736 MVT::ValueType TmpVT;
737 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
738 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
743 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
745 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
747 NewValues.push_back(RetOp);
748 NewValues.push_back(DAG.getConstant(isSigned, MVT::i32));
750 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, NewValues));
753 void SelectionDAGLowering::visitBr(BranchInst &I) {
754 // Update machine-CFG edges.
755 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
756 CurMBB->addSuccessor(Succ0MBB);
758 // Figure out which block is immediately after the current one.
759 MachineBasicBlock *NextBlock = 0;
760 MachineFunction::iterator BBI = CurMBB;
761 if (++BBI != CurMBB->getParent()->end())
764 if (I.isUnconditional()) {
765 // If this is not a fall-through branch, emit the branch.
766 if (Succ0MBB != NextBlock)
767 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
768 DAG.getBasicBlock(Succ0MBB)));
770 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
771 CurMBB->addSuccessor(Succ1MBB);
773 SDOperand Cond = getValue(I.getCondition());
774 if (Succ1MBB == NextBlock) {
775 // If the condition is false, fall through. This means we should branch
776 // if the condition is true to Succ #0.
777 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
778 Cond, DAG.getBasicBlock(Succ0MBB)));
779 } else if (Succ0MBB == NextBlock) {
780 // If the condition is true, fall through. This means we should branch if
781 // the condition is false to Succ #1. Invert the condition first.
782 SDOperand True = DAG.getConstant(1, Cond.getValueType());
783 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
784 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
785 Cond, DAG.getBasicBlock(Succ1MBB)));
787 std::vector<SDOperand> Ops;
788 Ops.push_back(getRoot());
789 // If the false case is the current basic block, then this is a self
790 // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
791 // adds an extra instruction in the loop. Instead, invert the
792 // condition and emit "Loop: ... br!cond Loop; br Out.
793 if (CurMBB == Succ1MBB) {
794 std::swap(Succ0MBB, Succ1MBB);
795 SDOperand True = DAG.getConstant(1, Cond.getValueType());
796 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
798 SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
799 DAG.getBasicBlock(Succ0MBB));
800 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
801 DAG.getBasicBlock(Succ1MBB)));
806 /// visitSwitchCase - Emits the necessary code to represent a single node in
807 /// the binary search tree resulting from lowering a switch instruction.
808 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
809 SDOperand SwitchOp = getValue(CB.SwitchV);
810 SDOperand CaseOp = getValue(CB.CaseC);
811 SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC);
813 // Set NextBlock to be the MBB immediately after the current one, if any.
814 // This is used to avoid emitting unnecessary branches to the next block.
815 MachineBasicBlock *NextBlock = 0;
816 MachineFunction::iterator BBI = CurMBB;
817 if (++BBI != CurMBB->getParent()->end())
820 // If the lhs block is the next block, invert the condition so that we can
821 // fall through to the lhs instead of the rhs block.
822 if (CB.LHSBB == NextBlock) {
823 std::swap(CB.LHSBB, CB.RHSBB);
824 SDOperand True = DAG.getConstant(1, Cond.getValueType());
825 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
827 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
828 DAG.getBasicBlock(CB.LHSBB));
829 if (CB.RHSBB == NextBlock)
832 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
833 DAG.getBasicBlock(CB.RHSBB)));
834 // Update successor info
835 CurMBB->addSuccessor(CB.LHSBB);
836 CurMBB->addSuccessor(CB.RHSBB);
839 /// visitSwitchCase - Emits the necessary code to represent a single node in
840 /// the binary search tree resulting from lowering a switch instruction.
841 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
842 // FIXME: Need to emit different code for PIC vs. Non-PIC, specifically,
843 // we need to add the address of the jump table to the value loaded, since
844 // the entries in the jump table will be differences rather than absolute
847 // Emit the code for the jump table
848 MVT::ValueType PTy = TLI.getPointerTy();
849 unsigned PTyBytes = MVT::getSizeInBits(PTy)/8;
850 SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
851 SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy,
852 DAG.getConstant(PTyBytes, PTy));
853 SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, DAG.getJumpTable(JT.JTI,PTy));
854 SDOperand LD = DAG.getLoad(PTy, Copy.getValue(1), ADD, DAG.getSrcValue(0));
855 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD));
858 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
859 // Figure out which block is immediately after the current one.
860 MachineBasicBlock *NextBlock = 0;
861 MachineFunction::iterator BBI = CurMBB;
862 if (++BBI != CurMBB->getParent()->end())
865 // If there is only the default destination, branch to it if it is not the
866 // next basic block. Otherwise, just fall through.
867 if (I.getNumOperands() == 2) {
868 // Update machine-CFG edges.
869 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()];
870 // If this is not a fall-through branch, emit the branch.
871 if (DefaultMBB != NextBlock)
872 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
873 DAG.getBasicBlock(DefaultMBB)));
874 CurMBB->addSuccessor(DefaultMBB);
878 // If there are any non-default case statements, create a vector of Cases
879 // representing each one, and sort the vector so that we can efficiently
880 // create a binary search tree from them.
881 std::vector<Case> Cases;
882 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
883 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
884 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
886 std::sort(Cases.begin(), Cases.end(), CaseCmp());
888 // Get the Value to be switched on and default basic blocks, which will be
889 // inserted into CaseBlock records, representing basic blocks in the binary
891 Value *SV = I.getOperand(0);
892 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
894 // Get the MachineFunction which holds the current MBB. This is used during
895 // emission of jump tables, and when inserting any additional MBBs necessary
896 // to represent the switch.
897 MachineFunction *CurMF = CurMBB->getParent();
898 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
899 Reloc::Model Relocs = TLI.getTargetMachine().getRelocationModel();
901 // If the switch has more than 5 blocks, and at least 31.25% dense, and the
902 // target supports indirect branches, then emit a jump table rather than
903 // lowering the switch to a binary tree of conditional branches.
904 // FIXME: Make this work with PIC code
905 if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) &&
906 (Relocs == Reloc::Static || Relocs == Reloc::DynamicNoPIC) &&
908 uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue();
909 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getRawValue();
910 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
912 if (Density >= 0.3125) {
913 // Create a new basic block to hold the code for loading the address
914 // of the jump table, and jumping to it. Update successor information;
915 // we will either branch to the default case for the switch, or the jump
917 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
918 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
919 CurMBB->addSuccessor(Default);
920 CurMBB->addSuccessor(JumpTableBB);
922 // Subtract the lowest switch case value from the value being switched on
923 // and conditional branch to default mbb if the result is greater than the
924 // difference between smallest and largest cases.
925 SDOperand SwitchOp = getValue(SV);
926 MVT::ValueType VT = SwitchOp.getValueType();
927 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
928 DAG.getConstant(First, VT));
930 // The SDNode we just created, which holds the value being switched on
931 // minus the the smallest case value, needs to be copied to a virtual
932 // register so it can be used as an index into the jump table in a
933 // subsequent basic block. This value may be smaller or larger than the
934 // target's pointer type, and therefore require extension or truncating.
935 if (VT > TLI.getPointerTy())
936 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
938 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
939 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
940 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
942 // Emit the range check for the jump table, and branch to the default
943 // block for the switch statement if the value being switched on exceeds
944 // the largest case in the switch.
945 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
946 DAG.getConstant(Last-First,VT), ISD::SETUGT);
947 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
948 DAG.getBasicBlock(Default)));
950 // Build a vector of destination BBs, corresponding to each target
951 // of the jump table. If the value of the jump table slot corresponds to
952 // a case statement, push the case's BB onto the vector, otherwise, push
954 std::set<MachineBasicBlock*> UniqueBBs;
955 std::vector<MachineBasicBlock*> DestBBs;
956 uint64_t TEI = First;
957 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) {
958 if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) {
959 DestBBs.push_back(ii->second);
960 UniqueBBs.insert(ii->second);
963 DestBBs.push_back(Default);
964 UniqueBBs.insert(Default);
968 // Update successor info
969 for (std::set<MachineBasicBlock*>::iterator ii = UniqueBBs.begin(),
970 ee = UniqueBBs.end(); ii != ee; ++ii)
971 JumpTableBB->addSuccessor(*ii);
973 // Create a jump table index for this jump table, or return an existing
975 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
977 // Set the jump table information so that we can codegen it as a second
979 JT.Reg = JumpTableReg;
981 JT.MBB = JumpTableBB;
982 JT.Default = Default;
987 // Push the initial CaseRec onto the worklist
988 std::vector<CaseRec> CaseVec;
989 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
991 while (!CaseVec.empty()) {
992 // Grab a record representing a case range to process off the worklist
993 CaseRec CR = CaseVec.back();
996 // Size is the number of Cases represented by this range. If Size is 1,
997 // then we are processing a leaf of the binary search tree. Otherwise,
998 // we need to pick a pivot, and push left and right ranges onto the
1000 unsigned Size = CR.Range.second - CR.Range.first;
1003 // Create a CaseBlock record representing a conditional branch to
1004 // the Case's target mbb if the value being switched on SV is equal
1005 // to C. Otherwise, branch to default.
1006 Constant *C = CR.Range.first->first;
1007 MachineBasicBlock *Target = CR.Range.first->second;
1008 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1010 // If the MBB representing the leaf node is the current MBB, then just
1011 // call visitSwitchCase to emit the code into the current block.
1012 // Otherwise, push the CaseBlock onto the vector to be later processed
1013 // by SDISel, and insert the node's MBB before the next MBB.
1014 if (CR.CaseBB == CurMBB)
1015 visitSwitchCase(CB);
1017 SwitchCases.push_back(CB);
1018 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1021 // split case range at pivot
1022 CaseItr Pivot = CR.Range.first + (Size / 2);
1023 CaseRange LHSR(CR.Range.first, Pivot);
1024 CaseRange RHSR(Pivot, CR.Range.second);
1025 Constant *C = Pivot->first;
1026 MachineBasicBlock *RHSBB = 0, *LHSBB = 0;
1027 // We know that we branch to the LHS if the Value being switched on is
1028 // less than the Pivot value, C. We use this to optimize our binary
1029 // tree a bit, by recognizing that if SV is greater than or equal to the
1030 // LHS's Case Value, and that Case Value is exactly one less than the
1031 // Pivot's Value, then we can branch directly to the LHS's Target,
1032 // rather than creating a leaf node for it.
1033 if ((LHSR.second - LHSR.first) == 1 &&
1034 LHSR.first->first == CR.GE &&
1035 cast<ConstantIntegral>(C)->getRawValue() ==
1036 (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) {
1037 LHSBB = LHSR.first->second;
1039 LHSBB = new MachineBasicBlock(LLVMBB);
1040 CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR));
1042 // Similar to the optimization above, if the Value being switched on is
1043 // known to be less than the Constant CR.LT, and the current Case Value
1044 // is CR.LT - 1, then we can branch directly to the target block for
1045 // the current Case Value, rather than emitting a RHS leaf node for it.
1046 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1047 cast<ConstantIntegral>(RHSR.first->first)->getRawValue() ==
1048 (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) {
1049 RHSBB = RHSR.first->second;
1051 RHSBB = new MachineBasicBlock(LLVMBB);
1052 CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR));
1054 // Create a CaseBlock record representing a conditional branch to
1055 // the LHS node if the value being switched on SV is less than C.
1056 // Otherwise, branch to LHS.
1057 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
1058 SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB);
1059 if (CR.CaseBB == CurMBB)
1060 visitSwitchCase(CB);
1062 SwitchCases.push_back(CB);
1063 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1069 void SelectionDAGLowering::visitSub(User &I) {
1070 // -0.0 - X --> fneg
1071 if (I.getType()->isFloatingPoint()) {
1072 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1073 if (CFP->isExactlyValue(-0.0)) {
1074 SDOperand Op2 = getValue(I.getOperand(1));
1075 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1079 visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
1082 void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
1084 const Type *Ty = I.getType();
1085 SDOperand Op1 = getValue(I.getOperand(0));
1086 SDOperand Op2 = getValue(I.getOperand(1));
1088 if (Ty->isIntegral()) {
1089 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
1090 } else if (Ty->isFloatingPoint()) {
1091 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
1093 const PackedType *PTy = cast<PackedType>(Ty);
1094 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1095 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1096 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1100 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1101 SDOperand Op1 = getValue(I.getOperand(0));
1102 SDOperand Op2 = getValue(I.getOperand(1));
1104 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1106 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1109 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
1110 ISD::CondCode UnsignedOpcode,
1111 ISD::CondCode FPOpcode) {
1112 SDOperand Op1 = getValue(I.getOperand(0));
1113 SDOperand Op2 = getValue(I.getOperand(1));
1114 ISD::CondCode Opcode = SignedOpcode;
1115 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint())
1117 else if (I.getOperand(0)->getType()->isUnsigned())
1118 Opcode = UnsignedOpcode;
1119 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1122 void SelectionDAGLowering::visitSelect(User &I) {
1123 SDOperand Cond = getValue(I.getOperand(0));
1124 SDOperand TrueVal = getValue(I.getOperand(1));
1125 SDOperand FalseVal = getValue(I.getOperand(2));
1126 if (!isa<PackedType>(I.getType())) {
1127 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1128 TrueVal, FalseVal));
1130 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1131 *(TrueVal.Val->op_end()-2),
1132 *(TrueVal.Val->op_end()-1)));
1136 void SelectionDAGLowering::visitCast(User &I) {
1137 SDOperand N = getValue(I.getOperand(0));
1138 MVT::ValueType SrcVT = N.getValueType();
1139 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1141 if (DestVT == MVT::Vector) {
1142 // This is a cast to a vector from something else. This is always a bit
1143 // convert. Get information about the input vector.
1144 const PackedType *DestTy = cast<PackedType>(I.getType());
1145 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1146 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1147 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1148 DAG.getValueType(EltVT)));
1149 } else if (SrcVT == DestVT) {
1150 setValue(&I, N); // noop cast.
1151 } else if (DestVT == MVT::i1) {
1152 // Cast to bool is a comparison against zero, not truncation to zero.
1153 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
1154 DAG.getConstantFP(0.0, N.getValueType());
1155 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
1156 } else if (isInteger(SrcVT)) {
1157 if (isInteger(DestVT)) { // Int -> Int cast
1158 if (DestVT < SrcVT) // Truncating cast?
1159 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1160 else if (I.getOperand(0)->getType()->isSigned())
1161 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1163 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1164 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast
1165 if (I.getOperand(0)->getType()->isSigned())
1166 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1168 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1170 assert(0 && "Unknown cast!");
1172 } else if (isFloatingPoint(SrcVT)) {
1173 if (isFloatingPoint(DestVT)) { // FP -> FP cast
1174 if (DestVT < SrcVT) // Rounding cast?
1175 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1177 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1178 } else if (isInteger(DestVT)) { // FP -> Int cast.
1179 if (I.getType()->isSigned())
1180 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1182 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1184 assert(0 && "Unknown cast!");
1187 assert(SrcVT == MVT::Vector && "Unknown cast!");
1188 assert(DestVT != MVT::Vector && "Casts to vector already handled!");
1189 // This is a cast from a vector to something else. This is always a bit
1190 // convert. Get information about the input vector.
1191 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1195 void SelectionDAGLowering::visitInsertElement(User &I) {
1196 SDOperand InVec = getValue(I.getOperand(0));
1197 SDOperand InVal = getValue(I.getOperand(1));
1198 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1199 getValue(I.getOperand(2)));
1201 SDOperand Num = *(InVec.Val->op_end()-2);
1202 SDOperand Typ = *(InVec.Val->op_end()-1);
1203 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1204 InVec, InVal, InIdx, Num, Typ));
1207 void SelectionDAGLowering::visitExtractElement(User &I) {
1208 SDOperand InVec = getValue(I.getOperand(0));
1209 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1210 getValue(I.getOperand(1)));
1211 SDOperand Typ = *(InVec.Val->op_end()-1);
1212 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1213 TLI.getValueType(I.getType()), InVec, InIdx));
1216 void SelectionDAGLowering::visitShuffleVector(User &I) {
1217 SDOperand V1 = getValue(I.getOperand(0));
1218 SDOperand V2 = getValue(I.getOperand(1));
1219 SDOperand Mask = getValue(I.getOperand(2));
1221 SDOperand Num = *(V1.Val->op_end()-2);
1222 SDOperand Typ = *(V2.Val->op_end()-1);
1223 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1224 V1, V2, Mask, Num, Typ));
1228 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1229 SDOperand N = getValue(I.getOperand(0));
1230 const Type *Ty = I.getOperand(0)->getType();
1232 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1235 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1236 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
1239 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
1240 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1241 getIntPtrConstant(Offset));
1243 Ty = StTy->getElementType(Field);
1245 Ty = cast<SequentialType>(Ty)->getElementType();
1247 // If this is a constant subscript, handle it quickly.
1248 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1249 if (CI->getRawValue() == 0) continue;
1252 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
1253 Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
1255 Offs = TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
1256 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1260 // N = N + Idx * ElementSize;
1261 uint64_t ElementSize = TD->getTypeSize(Ty);
1262 SDOperand IdxN = getValue(Idx);
1264 // If the index is smaller or larger than intptr_t, truncate or extend
1266 if (IdxN.getValueType() < N.getValueType()) {
1267 if (Idx->getType()->isSigned())
1268 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1270 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
1271 } else if (IdxN.getValueType() > N.getValueType())
1272 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1274 // If this is a multiply by a power of two, turn it into a shl
1275 // immediately. This is a very common case.
1276 if (isPowerOf2_64(ElementSize)) {
1277 unsigned Amt = Log2_64(ElementSize);
1278 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1279 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1280 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1284 SDOperand Scale = getIntPtrConstant(ElementSize);
1285 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1286 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1292 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1293 // If this is a fixed sized alloca in the entry block of the function,
1294 // allocate it statically on the stack.
1295 if (FuncInfo.StaticAllocaMap.count(&I))
1296 return; // getValue will auto-populate this.
1298 const Type *Ty = I.getAllocatedType();
1299 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1300 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
1303 SDOperand AllocSize = getValue(I.getArraySize());
1304 MVT::ValueType IntPtr = TLI.getPointerTy();
1305 if (IntPtr < AllocSize.getValueType())
1306 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1307 else if (IntPtr > AllocSize.getValueType())
1308 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1310 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1311 getIntPtrConstant(TySize));
1313 // Handle alignment. If the requested alignment is less than or equal to the
1314 // stack alignment, ignore it and round the size of the allocation up to the
1315 // stack alignment size. If the size is greater than the stack alignment, we
1316 // note this in the DYNAMIC_STACKALLOC node.
1317 unsigned StackAlign =
1318 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1319 if (Align <= StackAlign) {
1321 // Add SA-1 to the size.
1322 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1323 getIntPtrConstant(StackAlign-1));
1324 // Mask out the low bits for alignment purposes.
1325 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1326 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1329 std::vector<MVT::ValueType> VTs;
1330 VTs.push_back(AllocSize.getValueType());
1331 VTs.push_back(MVT::Other);
1332 std::vector<SDOperand> Ops;
1333 Ops.push_back(getRoot());
1334 Ops.push_back(AllocSize);
1335 Ops.push_back(getIntPtrConstant(Align));
1336 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
1337 DAG.setRoot(setValue(&I, DSA).getValue(1));
1339 // Inform the Frame Information that we have just allocated a variable-sized
1341 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1344 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1345 SDOperand Ptr = getValue(I.getOperand(0));
1351 // Do not serialize non-volatile loads against each other.
1352 Root = DAG.getRoot();
1355 setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)),
1356 Root, I.isVolatile()));
1359 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1360 SDOperand SrcValue, SDOperand Root,
1363 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1364 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1365 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue);
1367 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue);
1371 DAG.setRoot(L.getValue(1));
1373 PendingLoads.push_back(L.getValue(1));
1379 void SelectionDAGLowering::visitStore(StoreInst &I) {
1380 Value *SrcV = I.getOperand(0);
1381 SDOperand Src = getValue(SrcV);
1382 SDOperand Ptr = getValue(I.getOperand(1));
1383 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
1384 DAG.getSrcValue(I.getOperand(1))));
1387 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1388 /// access memory and has no other side effects at all.
1389 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1390 #define GET_NO_MEMORY_INTRINSICS
1391 #include "llvm/Intrinsics.gen"
1392 #undef GET_NO_MEMORY_INTRINSICS
1396 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1397 // have any side-effects or if it only reads memory.
1398 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1399 #define GET_SIDE_EFFECT_INFO
1400 #include "llvm/Intrinsics.gen"
1401 #undef GET_SIDE_EFFECT_INFO
1405 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1407 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1408 unsigned Intrinsic) {
1409 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1410 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1412 // Build the operand list.
1413 std::vector<SDOperand> Ops;
1414 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1416 // We don't need to serialize loads against other loads.
1417 Ops.push_back(DAG.getRoot());
1419 Ops.push_back(getRoot());
1423 // Add the intrinsic ID as an integer operand.
1424 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1426 // Add all operands of the call to the operand list.
1427 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1428 SDOperand Op = getValue(I.getOperand(i));
1430 // If this is a vector type, force it to the right packed type.
1431 if (Op.getValueType() == MVT::Vector) {
1432 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1433 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1435 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1436 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1437 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1440 assert(TLI.isTypeLegal(Op.getValueType()) &&
1441 "Intrinsic uses a non-legal type?");
1445 std::vector<MVT::ValueType> VTs;
1446 if (I.getType() != Type::VoidTy) {
1447 MVT::ValueType VT = TLI.getValueType(I.getType());
1448 if (VT == MVT::Vector) {
1449 const PackedType *DestTy = cast<PackedType>(I.getType());
1450 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1452 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1453 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1456 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1460 VTs.push_back(MVT::Other);
1465 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, Ops);
1466 else if (I.getType() != Type::VoidTy)
1467 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, Ops);
1469 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
1472 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1474 PendingLoads.push_back(Chain);
1478 if (I.getType() != Type::VoidTy) {
1479 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1480 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1481 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1482 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1483 DAG.getValueType(EVT));
1485 setValue(&I, Result);
1489 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1490 /// we want to emit this as a call to a named external function, return the name
1491 /// otherwise lower it and return null.
1493 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1494 switch (Intrinsic) {
1496 // By default, turn this into a target intrinsic node.
1497 visitTargetIntrinsic(I, Intrinsic);
1499 case Intrinsic::vastart: visitVAStart(I); return 0;
1500 case Intrinsic::vaend: visitVAEnd(I); return 0;
1501 case Intrinsic::vacopy: visitVACopy(I); return 0;
1502 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1503 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1504 case Intrinsic::setjmp:
1505 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1507 case Intrinsic::longjmp:
1508 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1510 case Intrinsic::memcpy_i32:
1511 case Intrinsic::memcpy_i64:
1512 visitMemIntrinsic(I, ISD::MEMCPY);
1514 case Intrinsic::memset_i32:
1515 case Intrinsic::memset_i64:
1516 visitMemIntrinsic(I, ISD::MEMSET);
1518 case Intrinsic::memmove_i32:
1519 case Intrinsic::memmove_i64:
1520 visitMemIntrinsic(I, ISD::MEMMOVE);
1523 case Intrinsic::dbg_stoppoint: {
1524 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1525 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1526 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
1527 std::vector<SDOperand> Ops;
1529 Ops.push_back(getRoot());
1530 Ops.push_back(getValue(SPI.getLineValue()));
1531 Ops.push_back(getValue(SPI.getColumnValue()));
1533 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
1534 assert(DD && "Not a debug information descriptor");
1535 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1537 Ops.push_back(DAG.getString(CompileUnit->getFileName()));
1538 Ops.push_back(DAG.getString(CompileUnit->getDirectory()));
1540 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops));
1545 case Intrinsic::dbg_region_start: {
1546 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1547 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1548 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
1549 std::vector<SDOperand> Ops;
1551 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
1553 Ops.push_back(getRoot());
1554 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1556 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1561 case Intrinsic::dbg_region_end: {
1562 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1563 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
1564 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
1565 std::vector<SDOperand> Ops;
1567 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
1569 Ops.push_back(getRoot());
1570 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1572 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1577 case Intrinsic::dbg_func_start: {
1578 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1579 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
1580 if (DebugInfo && FSI.getSubprogram() &&
1581 DebugInfo->Verify(FSI.getSubprogram())) {
1582 std::vector<SDOperand> Ops;
1584 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
1586 Ops.push_back(getRoot());
1587 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1589 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1594 case Intrinsic::dbg_declare: {
1595 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1596 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
1597 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
1598 std::vector<SDOperand> Ops;
1600 SDOperand AddressOp = getValue(DI.getAddress());
1601 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) {
1602 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
1609 case Intrinsic::isunordered_f32:
1610 case Intrinsic::isunordered_f64:
1611 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
1612 getValue(I.getOperand(2)), ISD::SETUO));
1615 case Intrinsic::sqrt_f32:
1616 case Intrinsic::sqrt_f64:
1617 setValue(&I, DAG.getNode(ISD::FSQRT,
1618 getValue(I.getOperand(1)).getValueType(),
1619 getValue(I.getOperand(1))));
1621 case Intrinsic::pcmarker: {
1622 SDOperand Tmp = getValue(I.getOperand(1));
1623 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
1626 case Intrinsic::readcyclecounter: {
1627 std::vector<MVT::ValueType> VTs;
1628 VTs.push_back(MVT::i64);
1629 VTs.push_back(MVT::Other);
1630 std::vector<SDOperand> Ops;
1631 Ops.push_back(getRoot());
1632 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops);
1634 DAG.setRoot(Tmp.getValue(1));
1637 case Intrinsic::bswap_i16:
1638 case Intrinsic::bswap_i32:
1639 case Intrinsic::bswap_i64:
1640 setValue(&I, DAG.getNode(ISD::BSWAP,
1641 getValue(I.getOperand(1)).getValueType(),
1642 getValue(I.getOperand(1))));
1644 case Intrinsic::cttz_i8:
1645 case Intrinsic::cttz_i16:
1646 case Intrinsic::cttz_i32:
1647 case Intrinsic::cttz_i64:
1648 setValue(&I, DAG.getNode(ISD::CTTZ,
1649 getValue(I.getOperand(1)).getValueType(),
1650 getValue(I.getOperand(1))));
1652 case Intrinsic::ctlz_i8:
1653 case Intrinsic::ctlz_i16:
1654 case Intrinsic::ctlz_i32:
1655 case Intrinsic::ctlz_i64:
1656 setValue(&I, DAG.getNode(ISD::CTLZ,
1657 getValue(I.getOperand(1)).getValueType(),
1658 getValue(I.getOperand(1))));
1660 case Intrinsic::ctpop_i8:
1661 case Intrinsic::ctpop_i16:
1662 case Intrinsic::ctpop_i32:
1663 case Intrinsic::ctpop_i64:
1664 setValue(&I, DAG.getNode(ISD::CTPOP,
1665 getValue(I.getOperand(1)).getValueType(),
1666 getValue(I.getOperand(1))));
1668 case Intrinsic::stacksave: {
1669 std::vector<MVT::ValueType> VTs;
1670 VTs.push_back(TLI.getPointerTy());
1671 VTs.push_back(MVT::Other);
1672 std::vector<SDOperand> Ops;
1673 Ops.push_back(getRoot());
1674 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, Ops);
1676 DAG.setRoot(Tmp.getValue(1));
1679 case Intrinsic::stackrestore: {
1680 SDOperand Tmp = getValue(I.getOperand(1));
1681 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
1684 case Intrinsic::prefetch:
1685 // FIXME: Currently discarding prefetches.
1691 void SelectionDAGLowering::visitCall(CallInst &I) {
1692 const char *RenameFn = 0;
1693 if (Function *F = I.getCalledFunction()) {
1694 if (F->isExternal())
1695 if (unsigned IID = F->getIntrinsicID()) {
1696 RenameFn = visitIntrinsicCall(I, IID);
1699 } else { // Not an LLVM intrinsic.
1700 const std::string &Name = F->getName();
1701 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
1702 if (I.getNumOperands() == 3 && // Basic sanity checks.
1703 I.getOperand(1)->getType()->isFloatingPoint() &&
1704 I.getType() == I.getOperand(1)->getType() &&
1705 I.getType() == I.getOperand(2)->getType()) {
1706 SDOperand LHS = getValue(I.getOperand(1));
1707 SDOperand RHS = getValue(I.getOperand(2));
1708 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
1712 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
1713 if (I.getNumOperands() == 2 && // Basic sanity checks.
1714 I.getOperand(1)->getType()->isFloatingPoint() &&
1715 I.getType() == I.getOperand(1)->getType()) {
1716 SDOperand Tmp = getValue(I.getOperand(1));
1717 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
1720 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
1721 if (I.getNumOperands() == 2 && // Basic sanity checks.
1722 I.getOperand(1)->getType()->isFloatingPoint() &&
1723 I.getType() == I.getOperand(1)->getType()) {
1724 SDOperand Tmp = getValue(I.getOperand(1));
1725 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
1728 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
1729 if (I.getNumOperands() == 2 && // Basic sanity checks.
1730 I.getOperand(1)->getType()->isFloatingPoint() &&
1731 I.getType() == I.getOperand(1)->getType()) {
1732 SDOperand Tmp = getValue(I.getOperand(1));
1733 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
1738 } else if (isa<InlineAsm>(I.getOperand(0))) {
1745 Callee = getValue(I.getOperand(0));
1747 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
1748 std::vector<std::pair<SDOperand, const Type*> > Args;
1749 Args.reserve(I.getNumOperands());
1750 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1751 Value *Arg = I.getOperand(i);
1752 SDOperand ArgNode = getValue(Arg);
1753 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
1756 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
1757 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1759 std::pair<SDOperand,SDOperand> Result =
1760 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
1761 I.isTailCall(), Callee, Args, DAG);
1762 if (I.getType() != Type::VoidTy)
1763 setValue(&I, Result.first);
1764 DAG.setRoot(Result.second);
1767 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
1768 SDOperand &Chain, SDOperand &Flag)const{
1769 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
1770 Chain = Val.getValue(1);
1771 Flag = Val.getValue(2);
1773 // If the result was expanded, copy from the top part.
1774 if (Regs.size() > 1) {
1775 assert(Regs.size() == 2 &&
1776 "Cannot expand to more than 2 elts yet!");
1777 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
1778 Chain = Val.getValue(1);
1779 Flag = Val.getValue(2);
1780 if (DAG.getTargetLoweringInfo().isLittleEndian())
1781 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
1783 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
1786 // Otherwise, if the return value was promoted or extended, truncate it to the
1787 // appropriate type.
1788 if (RegVT == ValueVT)
1791 if (MVT::isInteger(RegVT)) {
1792 if (ValueVT < RegVT)
1793 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1795 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
1797 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
1801 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
1802 /// specified value into the registers specified by this object. This uses
1803 /// Chain/Flag as the input and updates them for the output Chain/Flag.
1804 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
1805 SDOperand &Chain, SDOperand &Flag,
1806 MVT::ValueType PtrVT) const {
1807 if (Regs.size() == 1) {
1808 // If there is a single register and the types differ, this must be
1810 if (RegVT != ValueVT) {
1811 if (MVT::isInteger(RegVT)) {
1812 if (RegVT < ValueVT)
1813 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
1815 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
1817 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
1819 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
1820 Flag = Chain.getValue(1);
1822 std::vector<unsigned> R(Regs);
1823 if (!DAG.getTargetLoweringInfo().isLittleEndian())
1824 std::reverse(R.begin(), R.end());
1826 for (unsigned i = 0, e = R.size(); i != e; ++i) {
1827 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
1828 DAG.getConstant(i, PtrVT));
1829 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
1830 Flag = Chain.getValue(1);
1835 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
1836 /// operand list. This adds the code marker and includes the number of
1837 /// values added into it.
1838 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
1839 std::vector<SDOperand> &Ops) const {
1840 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
1841 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1842 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
1845 /// isAllocatableRegister - If the specified register is safe to allocate,
1846 /// i.e. it isn't a stack pointer or some other special register, return the
1847 /// register class for the register. Otherwise, return null.
1848 static const TargetRegisterClass *
1849 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
1850 const TargetLowering &TLI, const MRegisterInfo *MRI) {
1851 MVT::ValueType FoundVT = MVT::Other;
1852 const TargetRegisterClass *FoundRC = 0;
1853 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
1854 E = MRI->regclass_end(); RCI != E; ++RCI) {
1855 MVT::ValueType ThisVT = MVT::Other;
1857 const TargetRegisterClass *RC = *RCI;
1858 // If none of the the value types for this register class are valid, we
1859 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1860 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1862 if (TLI.isTypeLegal(*I)) {
1863 // If we have already found this register in a different register class,
1864 // choose the one with the largest VT specified. For example, on
1865 // PowerPC, we favor f64 register classes over f32.
1866 if (FoundVT == MVT::Other ||
1867 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
1874 if (ThisVT == MVT::Other) continue;
1876 // NOTE: This isn't ideal. In particular, this might allocate the
1877 // frame pointer in functions that need it (due to them not being taken
1878 // out of allocation, because a variable sized allocation hasn't been seen
1879 // yet). This is a slight code pessimization, but should still work.
1880 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
1881 E = RC->allocation_order_end(MF); I != E; ++I)
1883 // We found a matching register class. Keep looking at others in case
1884 // we find one with larger registers that this physreg is also in.
1893 RegsForValue SelectionDAGLowering::
1894 GetRegistersForValue(const std::string &ConstrCode,
1895 MVT::ValueType VT, bool isOutReg, bool isInReg,
1896 std::set<unsigned> &OutputRegs,
1897 std::set<unsigned> &InputRegs) {
1898 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
1899 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
1900 std::vector<unsigned> Regs;
1902 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
1903 MVT::ValueType RegVT;
1904 MVT::ValueType ValueVT = VT;
1906 if (PhysReg.first) {
1907 if (VT == MVT::Other)
1908 ValueVT = *PhysReg.second->vt_begin();
1910 // Get the actual register value type. This is important, because the user
1911 // may have asked for (e.g.) the AX register in i32 type. We need to
1912 // remember that AX is actually i16 to get the right extension.
1913 RegVT = *PhysReg.second->vt_begin();
1915 // This is a explicit reference to a physical register.
1916 Regs.push_back(PhysReg.first);
1918 // If this is an expanded reference, add the rest of the regs to Regs.
1920 TargetRegisterClass::iterator I = PhysReg.second->begin();
1921 TargetRegisterClass::iterator E = PhysReg.second->end();
1922 for (; *I != PhysReg.first; ++I)
1923 assert(I != E && "Didn't find reg!");
1925 // Already added the first reg.
1927 for (; NumRegs; --NumRegs, ++I) {
1928 assert(I != E && "Ran out of registers to allocate!");
1932 return RegsForValue(Regs, RegVT, ValueVT);
1935 // This is a reference to a register class. Allocate NumRegs consecutive,
1936 // available, registers from the class.
1937 std::vector<unsigned> RegClassRegs =
1938 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
1940 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
1941 MachineFunction &MF = *CurMBB->getParent();
1942 unsigned NumAllocated = 0;
1943 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
1944 unsigned Reg = RegClassRegs[i];
1945 // See if this register is available.
1946 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
1947 (isInReg && InputRegs.count(Reg))) { // Already used.
1948 // Make sure we find consecutive registers.
1953 // Check to see if this register is allocatable (i.e. don't give out the
1955 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
1957 // Make sure we find consecutive registers.
1962 // Okay, this register is good, we can use it.
1965 // If we allocated enough consecutive
1966 if (NumAllocated == NumRegs) {
1967 unsigned RegStart = (i-NumAllocated)+1;
1968 unsigned RegEnd = i+1;
1969 // Mark all of the allocated registers used.
1970 for (unsigned i = RegStart; i != RegEnd; ++i) {
1971 unsigned Reg = RegClassRegs[i];
1972 Regs.push_back(Reg);
1973 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
1974 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
1977 return RegsForValue(Regs, *RC->vt_begin(), VT);
1981 // Otherwise, we couldn't allocate enough registers for this.
1982 return RegsForValue();
1986 /// visitInlineAsm - Handle a call to an InlineAsm object.
1988 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
1989 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
1991 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
1994 // Note, we treat inline asms both with and without side-effects as the same.
1995 // If an inline asm doesn't have side effects and doesn't access memory, we
1996 // could not choose to not chain it.
1997 bool hasSideEffects = IA->hasSideEffects();
1999 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
2000 std::vector<MVT::ValueType> ConstraintVTs;
2002 /// AsmNodeOperands - A list of pairs. The first element is a register, the
2003 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
2004 /// if it is a def of that register.
2005 std::vector<SDOperand> AsmNodeOperands;
2006 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
2007 AsmNodeOperands.push_back(AsmStr);
2009 SDOperand Chain = getRoot();
2012 // We fully assign registers here at isel time. This is not optimal, but
2013 // should work. For register classes that correspond to LLVM classes, we
2014 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
2015 // over the constraints, collecting fixed registers that we know we can't use.
2016 std::set<unsigned> OutputRegs, InputRegs;
2018 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2019 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2020 std::string &ConstraintCode = Constraints[i].Codes[0];
2022 MVT::ValueType OpVT;
2024 // Compute the value type for each operand and add it to ConstraintVTs.
2025 switch (Constraints[i].Type) {
2026 case InlineAsm::isOutput:
2027 if (!Constraints[i].isIndirectOutput) {
2028 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2029 OpVT = TLI.getValueType(I.getType());
2031 const Type *OpTy = I.getOperand(OpNum)->getType();
2032 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2033 OpNum++; // Consumes a call operand.
2036 case InlineAsm::isInput:
2037 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2038 OpNum++; // Consumes a call operand.
2040 case InlineAsm::isClobber:
2045 ConstraintVTs.push_back(OpVT);
2047 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2048 continue; // Not assigned a fixed reg.
2050 // Build a list of regs that this operand uses. This always has a single
2051 // element for promoted/expanded operands.
2052 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2054 OutputRegs, InputRegs);
2056 switch (Constraints[i].Type) {
2057 case InlineAsm::isOutput:
2058 // We can't assign any other output to this register.
2059 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2060 // If this is an early-clobber output, it cannot be assigned to the same
2061 // value as the input reg.
2062 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2063 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2065 case InlineAsm::isInput:
2066 // We can't assign any other input to this register.
2067 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2069 case InlineAsm::isClobber:
2070 // Clobbered regs cannot be used as inputs or outputs.
2071 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2072 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2077 // Loop over all of the inputs, copying the operand values into the
2078 // appropriate registers and processing the output regs.
2079 RegsForValue RetValRegs;
2080 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2083 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2084 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2085 std::string &ConstraintCode = Constraints[i].Codes[0];
2087 switch (Constraints[i].Type) {
2088 case InlineAsm::isOutput: {
2089 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2090 if (ConstraintCode.size() == 1) // not a physreg name.
2091 CTy = TLI.getConstraintType(ConstraintCode[0]);
2093 if (CTy == TargetLowering::C_Memory) {
2095 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2097 // Check that the operand (the address to store to) isn't a float.
2098 if (!MVT::isInteger(InOperandVal.getValueType()))
2099 assert(0 && "MATCH FAIL!");
2101 if (!Constraints[i].isIndirectOutput)
2102 assert(0 && "MATCH FAIL!");
2104 OpNum++; // Consumes a call operand.
2106 // Extend/truncate to the right pointer type if needed.
2107 MVT::ValueType PtrType = TLI.getPointerTy();
2108 if (InOperandVal.getValueType() < PtrType)
2109 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2110 else if (InOperandVal.getValueType() > PtrType)
2111 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2113 // Add information to the INLINEASM node to know about this output.
2114 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2115 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2116 AsmNodeOperands.push_back(InOperandVal);
2120 // Otherwise, this is a register output.
2121 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2123 // If this is an early-clobber output, or if there is an input
2124 // constraint that matches this, we need to reserve the input register
2125 // so no other inputs allocate to it.
2126 bool UsesInputRegister = false;
2127 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2128 UsesInputRegister = true;
2130 // Copy the output from the appropriate register. Find a register that
2133 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2134 true, UsesInputRegister,
2135 OutputRegs, InputRegs);
2136 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
2138 if (!Constraints[i].isIndirectOutput) {
2139 assert(RetValRegs.Regs.empty() &&
2140 "Cannot have multiple output constraints yet!");
2141 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2144 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2145 I.getOperand(OpNum)));
2146 OpNum++; // Consumes a call operand.
2149 // Add information to the INLINEASM node to know that this register is
2151 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2154 case InlineAsm::isInput: {
2155 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2156 OpNum++; // Consumes a call operand.
2158 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2159 // If this is required to match an output register we have already set,
2160 // just use its register.
2161 unsigned OperandNo = atoi(ConstraintCode.c_str());
2163 // Scan until we find the definition we already emitted of this operand.
2164 // When we find it, create a RegsForValue operand.
2165 unsigned CurOp = 2; // The first operand.
2166 for (; OperandNo; --OperandNo) {
2167 // Advance to the next operand.
2169 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2170 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
2171 (NumOps & 7) == 4 /*MEM*/) &&
2172 "Skipped past definitions?");
2173 CurOp += (NumOps>>3)+1;
2177 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2178 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2179 "Skipped past definitions?");
2181 // Add NumOps>>3 registers to MatchedRegs.
2182 RegsForValue MatchedRegs;
2183 MatchedRegs.ValueVT = InOperandVal.getValueType();
2184 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2185 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2186 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2187 MatchedRegs.Regs.push_back(Reg);
2190 // Use the produced MatchedRegs object to
2191 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag,
2192 TLI.getPointerTy());
2193 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2197 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2198 if (ConstraintCode.size() == 1) // not a physreg name.
2199 CTy = TLI.getConstraintType(ConstraintCode[0]);
2201 if (CTy == TargetLowering::C_Other) {
2202 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
2203 assert(0 && "MATCH FAIL!");
2205 // Add information to the INLINEASM node to know about this input.
2206 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2207 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2208 AsmNodeOperands.push_back(InOperandVal);
2210 } else if (CTy == TargetLowering::C_Memory) {
2213 // Check that the operand isn't a float.
2214 if (!MVT::isInteger(InOperandVal.getValueType()))
2215 assert(0 && "MATCH FAIL!");
2217 // Extend/truncate to the right pointer type if needed.
2218 MVT::ValueType PtrType = TLI.getPointerTy();
2219 if (InOperandVal.getValueType() < PtrType)
2220 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2221 else if (InOperandVal.getValueType() > PtrType)
2222 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2224 // Add information to the INLINEASM node to know about this input.
2225 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2226 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2227 AsmNodeOperands.push_back(InOperandVal);
2231 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2233 // Copy the input into the appropriate registers.
2234 RegsForValue InRegs =
2235 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2236 false, true, OutputRegs, InputRegs);
2237 // FIXME: should be match fail.
2238 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2240 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy());
2242 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2245 case InlineAsm::isClobber: {
2246 RegsForValue ClobberedRegs =
2247 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2248 OutputRegs, InputRegs);
2249 // Add the clobbered value to the operand list, so that the register
2250 // allocator is aware that the physreg got clobbered.
2251 if (!ClobberedRegs.Regs.empty())
2252 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2258 // Finish up input operands.
2259 AsmNodeOperands[0] = Chain;
2260 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2262 std::vector<MVT::ValueType> VTs;
2263 VTs.push_back(MVT::Other);
2264 VTs.push_back(MVT::Flag);
2265 Chain = DAG.getNode(ISD::INLINEASM, VTs, AsmNodeOperands);
2266 Flag = Chain.getValue(1);
2268 // If this asm returns a register value, copy the result from that register
2269 // and set it as the value of the call.
2270 if (!RetValRegs.Regs.empty())
2271 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2273 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2275 // Process indirect outputs, first output all of the flagged copies out of
2277 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2278 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2279 Value *Ptr = IndirectStoresToEmit[i].second;
2280 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2281 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2284 // Emit the non-flagged stores from the physregs.
2285 std::vector<SDOperand> OutChains;
2286 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2287 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
2288 StoresToEmit[i].first,
2289 getValue(StoresToEmit[i].second),
2290 DAG.getSrcValue(StoresToEmit[i].second)));
2291 if (!OutChains.empty())
2292 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
2297 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2298 SDOperand Src = getValue(I.getOperand(0));
2300 MVT::ValueType IntPtr = TLI.getPointerTy();
2302 if (IntPtr < Src.getValueType())
2303 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2304 else if (IntPtr > Src.getValueType())
2305 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2307 // Scale the source by the type size.
2308 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
2309 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2310 Src, getIntPtrConstant(ElementSize));
2312 std::vector<std::pair<SDOperand, const Type*> > Args;
2313 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType()));
2315 std::pair<SDOperand,SDOperand> Result =
2316 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
2317 DAG.getExternalSymbol("malloc", IntPtr),
2319 setValue(&I, Result.first); // Pointers always fit in registers
2320 DAG.setRoot(Result.second);
2323 void SelectionDAGLowering::visitFree(FreeInst &I) {
2324 std::vector<std::pair<SDOperand, const Type*> > Args;
2325 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
2326 TLI.getTargetData()->getIntPtrType()));
2327 MVT::ValueType IntPtr = TLI.getPointerTy();
2328 std::pair<SDOperand,SDOperand> Result =
2329 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
2330 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2331 DAG.setRoot(Result.second);
2334 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2335 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2336 // instructions are special in various ways, which require special support to
2337 // insert. The specified MachineInstr is created but not inserted into any
2338 // basic blocks, and the scheduler passes ownership of it to this method.
2339 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2340 MachineBasicBlock *MBB) {
2341 std::cerr << "If a target marks an instruction with "
2342 "'usesCustomDAGSchedInserter', it must implement "
2343 "TargetLowering::InsertAtEndOfBasicBlock!\n";
2348 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2349 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2350 getValue(I.getOperand(1)),
2351 DAG.getSrcValue(I.getOperand(1))));
2354 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2355 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2356 getValue(I.getOperand(0)),
2357 DAG.getSrcValue(I.getOperand(0)));
2359 DAG.setRoot(V.getValue(1));
2362 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2363 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2364 getValue(I.getOperand(1)),
2365 DAG.getSrcValue(I.getOperand(1))));
2368 void SelectionDAGLowering::visitVACopy(CallInst &I) {
2369 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2370 getValue(I.getOperand(1)),
2371 getValue(I.getOperand(2)),
2372 DAG.getSrcValue(I.getOperand(1)),
2373 DAG.getSrcValue(I.getOperand(2))));
2376 /// TargetLowering::LowerArguments - This is the default LowerArguments
2377 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
2378 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
2379 /// integrated into SDISel.
2380 std::vector<SDOperand>
2381 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2382 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2383 std::vector<SDOperand> Ops;
2384 Ops.push_back(DAG.getRoot());
2385 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2386 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2388 // Add one result value for each formal argument.
2389 std::vector<MVT::ValueType> RetVals;
2390 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2391 MVT::ValueType VT = getValueType(I->getType());
2393 switch (getTypeAction(VT)) {
2394 default: assert(0 && "Unknown type action!");
2396 RetVals.push_back(VT);
2399 RetVals.push_back(getTypeToTransformTo(VT));
2402 if (VT != MVT::Vector) {
2403 // If this is a large integer, it needs to be broken up into small
2404 // integers. Figure out what the destination type is and how many small
2405 // integers it turns into.
2406 MVT::ValueType NVT = getTypeToTransformTo(VT);
2407 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2408 for (unsigned i = 0; i != NumVals; ++i)
2409 RetVals.push_back(NVT);
2411 // Otherwise, this is a vector type. We only support legal vectors
2413 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2414 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2416 // Figure out if there is a Packed type corresponding to this Vector
2417 // type. If so, convert to the packed type.
2418 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2419 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2420 RetVals.push_back(TVT);
2422 assert(0 && "Don't support illegal by-val vector arguments yet!");
2429 RetVals.push_back(MVT::Other);
2432 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals, Ops).Val;
2434 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
2436 // Set up the return result vector.
2439 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2440 MVT::ValueType VT = getValueType(I->getType());
2442 switch (getTypeAction(VT)) {
2443 default: assert(0 && "Unknown type action!");
2445 Ops.push_back(SDOperand(Result, i++));
2448 SDOperand Op(Result, i++);
2449 if (MVT::isInteger(VT)) {
2450 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
2452 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
2453 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2455 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2456 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2462 if (VT != MVT::Vector) {
2463 // If this is a large integer, it needs to be reassembled from small
2464 // integers. Figure out what the source elt type is and how many small
2466 MVT::ValueType NVT = getTypeToTransformTo(VT);
2467 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2469 SDOperand Lo = SDOperand(Result, i++);
2470 SDOperand Hi = SDOperand(Result, i++);
2472 if (!isLittleEndian())
2475 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
2477 // Value scalarized into many values. Unimp for now.
2478 assert(0 && "Cannot expand i64 -> i16 yet!");
2481 // Otherwise, this is a vector type. We only support legal vectors
2483 const PackedType *PTy = cast<PackedType>(I->getType());
2484 unsigned NumElems = PTy->getNumElements();
2485 const Type *EltTy = PTy->getElementType();
2487 // Figure out if there is a Packed type corresponding to this Vector
2488 // type. If so, convert to the packed type.
2489 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2490 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2491 SDOperand N = SDOperand(Result, i++);
2492 // Handle copies from generic vectors to registers.
2493 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
2494 DAG.getConstant(NumElems, MVT::i32),
2495 DAG.getValueType(getValueType(EltTy)));
2498 assert(0 && "Don't support illegal by-val vector arguments yet!");
2509 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
2510 /// implementation, which just inserts an ISD::CALL node, which is later custom
2511 /// lowered by the target to something concrete. FIXME: When all targets are
2512 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
2513 std::pair<SDOperand, SDOperand>
2514 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
2515 unsigned CallingConv, bool isTailCall,
2517 ArgListTy &Args, SelectionDAG &DAG) {
2518 std::vector<SDOperand> Ops;
2519 Ops.push_back(Chain); // Op#0 - Chain
2520 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
2521 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
2522 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
2523 Ops.push_back(Callee);
2525 // Handle all of the outgoing arguments.
2526 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
2527 MVT::ValueType VT = getValueType(Args[i].second);
2528 SDOperand Op = Args[i].first;
2529 bool isSigned = Args[i].second->isSigned();
2530 switch (getTypeAction(VT)) {
2531 default: assert(0 && "Unknown type action!");
2534 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2537 if (MVT::isInteger(VT)) {
2538 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2539 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
2541 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2542 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
2545 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2548 if (VT != MVT::Vector) {
2549 // If this is a large integer, it needs to be broken down into small
2550 // integers. Figure out what the source elt type is and how many small
2552 MVT::ValueType NVT = getTypeToTransformTo(VT);
2553 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2555 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2556 DAG.getConstant(0, getPointerTy()));
2557 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2558 DAG.getConstant(1, getPointerTy()));
2559 if (!isLittleEndian())
2563 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2565 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2567 // Value scalarized into many values. Unimp for now.
2568 assert(0 && "Cannot expand i64 -> i16 yet!");
2571 // Otherwise, this is a vector type. We only support legal vectors
2573 const PackedType *PTy = cast<PackedType>(Args[i].second);
2574 unsigned NumElems = PTy->getNumElements();
2575 const Type *EltTy = PTy->getElementType();
2577 // Figure out if there is a Packed type corresponding to this Vector
2578 // type. If so, convert to the packed type.
2579 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2580 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2581 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
2582 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
2584 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2586 assert(0 && "Don't support illegal by-val vector call args yet!");
2594 // Figure out the result value types.
2595 std::vector<MVT::ValueType> RetTys;
2597 if (RetTy != Type::VoidTy) {
2598 MVT::ValueType VT = getValueType(RetTy);
2599 switch (getTypeAction(VT)) {
2600 default: assert(0 && "Unknown type action!");
2602 RetTys.push_back(VT);
2605 RetTys.push_back(getTypeToTransformTo(VT));
2608 if (VT != MVT::Vector) {
2609 // If this is a large integer, it needs to be reassembled from small
2610 // integers. Figure out what the source elt type is and how many small
2612 MVT::ValueType NVT = getTypeToTransformTo(VT);
2613 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2614 for (unsigned i = 0; i != NumVals; ++i)
2615 RetTys.push_back(NVT);
2617 // Otherwise, this is a vector type. We only support legal vectors
2619 const PackedType *PTy = cast<PackedType>(RetTy);
2620 unsigned NumElems = PTy->getNumElements();
2621 const Type *EltTy = PTy->getElementType();
2623 // Figure out if there is a Packed type corresponding to this Vector
2624 // type. If so, convert to the packed type.
2625 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2626 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2627 RetTys.push_back(TVT);
2629 assert(0 && "Don't support illegal by-val vector call results yet!");
2636 RetTys.push_back(MVT::Other); // Always has a chain.
2638 // Finally, create the CALL node.
2639 SDOperand Res = DAG.getNode(ISD::CALL, RetTys, Ops);
2641 // This returns a pair of operands. The first element is the
2642 // return value for the function (if RetTy is not VoidTy). The second
2643 // element is the outgoing token chain.
2645 if (RetTys.size() != 1) {
2646 MVT::ValueType VT = getValueType(RetTy);
2647 if (RetTys.size() == 2) {
2650 // If this value was promoted, truncate it down.
2651 if (ResVal.getValueType() != VT) {
2652 if (VT == MVT::Vector) {
2653 // Insert a VBITCONVERT to convert from the packed result type to the
2654 // MVT::Vector type.
2655 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
2656 const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
2658 // Figure out if there is a Packed type corresponding to this Vector
2659 // type. If so, convert to the packed type.
2660 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2661 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2662 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
2663 // "N x PTyElementVT" MVT::Vector type.
2664 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
2665 DAG.getConstant(NumElems, MVT::i32),
2666 DAG.getValueType(getValueType(EltTy)));
2670 } else if (MVT::isInteger(VT)) {
2671 unsigned AssertOp = RetTy->isSigned() ?
2672 ISD::AssertSext : ISD::AssertZext;
2673 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
2674 DAG.getValueType(VT));
2675 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
2677 assert(MVT::isFloatingPoint(VT));
2678 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
2681 } else if (RetTys.size() == 3) {
2682 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
2683 Res.getValue(0), Res.getValue(1));
2686 assert(0 && "Case not handled yet!");
2690 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
2695 // It is always conservatively correct for llvm.returnaddress and
2696 // llvm.frameaddress to return 0.
2698 // FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
2699 // expanded to 0 if the target wants.
2700 std::pair<SDOperand, SDOperand>
2701 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
2702 unsigned Depth, SelectionDAG &DAG) {
2703 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
2706 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2707 assert(0 && "LowerOperation not implemented for this target!");
2712 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
2713 SelectionDAG &DAG) {
2714 assert(0 && "CustomPromoteOperation not implemented for this target!");
2719 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
2720 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
2721 std::pair<SDOperand,SDOperand> Result =
2722 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
2723 setValue(&I, Result.first);
2724 DAG.setRoot(Result.second);
2727 /// getMemsetValue - Vectorized representation of the memset value
2729 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
2730 SelectionDAG &DAG) {
2731 MVT::ValueType CurVT = VT;
2732 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2733 uint64_t Val = C->getValue() & 255;
2735 while (CurVT != MVT::i8) {
2736 Val = (Val << Shift) | Val;
2738 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2740 return DAG.getConstant(Val, VT);
2742 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
2744 while (CurVT != MVT::i8) {
2746 DAG.getNode(ISD::OR, VT,
2747 DAG.getNode(ISD::SHL, VT, Value,
2748 DAG.getConstant(Shift, MVT::i8)), Value);
2750 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2757 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2758 /// used when a memcpy is turned into a memset when the source is a constant
2760 static SDOperand getMemsetStringVal(MVT::ValueType VT,
2761 SelectionDAG &DAG, TargetLowering &TLI,
2762 std::string &Str, unsigned Offset) {
2763 MVT::ValueType CurVT = VT;
2765 unsigned MSB = getSizeInBits(VT) / 8;
2766 if (TLI.isLittleEndian())
2767 Offset = Offset + MSB - 1;
2768 for (unsigned i = 0; i != MSB; ++i) {
2769 Val = (Val << 8) | Str[Offset];
2770 Offset += TLI.isLittleEndian() ? -1 : 1;
2772 return DAG.getConstant(Val, VT);
2775 /// getMemBasePlusOffset - Returns base and offset node for the
2776 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
2777 SelectionDAG &DAG, TargetLowering &TLI) {
2778 MVT::ValueType VT = Base.getValueType();
2779 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
2782 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
2783 /// to replace the memset / memcpy is below the threshold. It also returns the
2784 /// types of the sequence of memory ops to perform memset / memcpy.
2785 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
2786 unsigned Limit, uint64_t Size,
2787 unsigned Align, TargetLowering &TLI) {
2790 if (TLI.allowsUnalignedMemoryAccesses()) {
2793 switch (Align & 7) {
2809 MVT::ValueType LVT = MVT::i64;
2810 while (!TLI.isTypeLegal(LVT))
2811 LVT = (MVT::ValueType)((unsigned)LVT - 1);
2812 assert(MVT::isInteger(LVT));
2817 unsigned NumMemOps = 0;
2819 unsigned VTSize = getSizeInBits(VT) / 8;
2820 while (VTSize > Size) {
2821 VT = (MVT::ValueType)((unsigned)VT - 1);
2824 assert(MVT::isInteger(VT));
2826 if (++NumMemOps > Limit)
2828 MemOps.push_back(VT);
2835 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
2836 SDOperand Op1 = getValue(I.getOperand(1));
2837 SDOperand Op2 = getValue(I.getOperand(2));
2838 SDOperand Op3 = getValue(I.getOperand(3));
2839 SDOperand Op4 = getValue(I.getOperand(4));
2840 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
2841 if (Align == 0) Align = 1;
2843 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
2844 std::vector<MVT::ValueType> MemOps;
2846 // Expand memset / memcpy to a series of load / store ops
2847 // if the size operand falls below a certain threshold.
2848 std::vector<SDOperand> OutChains;
2850 default: break; // Do nothing for now.
2852 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
2853 Size->getValue(), Align, TLI)) {
2854 unsigned NumMemOps = MemOps.size();
2855 unsigned Offset = 0;
2856 for (unsigned i = 0; i < NumMemOps; i++) {
2857 MVT::ValueType VT = MemOps[i];
2858 unsigned VTSize = getSizeInBits(VT) / 8;
2859 SDOperand Value = getMemsetValue(Op2, VT, DAG);
2860 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(),
2862 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
2863 DAG.getSrcValue(I.getOperand(1), Offset));
2864 OutChains.push_back(Store);
2871 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
2872 Size->getValue(), Align, TLI)) {
2873 unsigned NumMemOps = MemOps.size();
2874 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
2875 GlobalAddressSDNode *G = NULL;
2877 bool CopyFromStr = false;
2879 if (Op2.getOpcode() == ISD::GlobalAddress)
2880 G = cast<GlobalAddressSDNode>(Op2);
2881 else if (Op2.getOpcode() == ISD::ADD &&
2882 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
2883 Op2.getOperand(1).getOpcode() == ISD::Constant) {
2884 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
2885 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
2888 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
2890 Str = GV->getStringValue(false);
2898 for (unsigned i = 0; i < NumMemOps; i++) {
2899 MVT::ValueType VT = MemOps[i];
2900 unsigned VTSize = getSizeInBits(VT) / 8;
2901 SDOperand Value, Chain, Store;
2904 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
2907 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2908 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2909 DAG.getSrcValue(I.getOperand(1), DstOff));
2911 Value = DAG.getLoad(VT, getRoot(),
2912 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
2913 DAG.getSrcValue(I.getOperand(2), SrcOff));
2914 Chain = Value.getValue(1);
2916 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2917 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2918 DAG.getSrcValue(I.getOperand(1), DstOff));
2920 OutChains.push_back(Store);
2929 if (!OutChains.empty()) {
2930 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
2935 std::vector<SDOperand> Ops;
2936 Ops.push_back(getRoot());
2941 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
2944 //===----------------------------------------------------------------------===//
2945 // SelectionDAGISel code
2946 //===----------------------------------------------------------------------===//
2948 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
2949 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
2952 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
2953 // FIXME: we only modify the CFG to split critical edges. This
2954 // updates dom and loop info.
2958 /// OptimizeNoopCopyExpression - We have determined that the specified cast
2959 /// instruction is a noop copy (e.g. it's casting from one pointer type to
2960 /// another, int->uint, or int->sbyte on PPC.
2962 /// Return true if any changes are made.
2963 static bool OptimizeNoopCopyExpression(CastInst *CI) {
2964 BasicBlock *DefBB = CI->getParent();
2966 /// InsertedCasts - Only insert a cast in each block once.
2967 std::map<BasicBlock*, CastInst*> InsertedCasts;
2969 bool MadeChange = false;
2970 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
2972 Use &TheUse = UI.getUse();
2973 Instruction *User = cast<Instruction>(*UI);
2975 // Figure out which BB this cast is used in. For PHI's this is the
2976 // appropriate predecessor block.
2977 BasicBlock *UserBB = User->getParent();
2978 if (PHINode *PN = dyn_cast<PHINode>(User)) {
2979 unsigned OpVal = UI.getOperandNo()/2;
2980 UserBB = PN->getIncomingBlock(OpVal);
2983 // Preincrement use iterator so we don't invalidate it.
2986 // If this user is in the same block as the cast, don't change the cast.
2987 if (UserBB == DefBB) continue;
2989 // If we have already inserted a cast into this block, use it.
2990 CastInst *&InsertedCast = InsertedCasts[UserBB];
2992 if (!InsertedCast) {
2993 BasicBlock::iterator InsertPt = UserBB->begin();
2994 while (isa<PHINode>(InsertPt)) ++InsertPt;
2997 new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3001 // Replace a use of the cast with a use of the new casat.
3002 TheUse = InsertedCast;
3005 // If we removed all uses, nuke the cast.
3006 if (CI->use_empty())
3007 CI->eraseFromParent();
3012 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
3013 /// casting to the type of GEPI.
3014 static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
3015 Instruction *GEPI, Value *Ptr,
3017 if (V) return V; // Already computed.
3019 BasicBlock::iterator InsertPt;
3020 if (BB == GEPI->getParent()) {
3021 // If insert into the GEP's block, insert right after the GEP.
3025 // Otherwise, insert at the top of BB, after any PHI nodes
3026 InsertPt = BB->begin();
3027 while (isa<PHINode>(InsertPt)) ++InsertPt;
3030 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3031 // BB so that there is only one value live across basic blocks (the cast
3033 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3034 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3035 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3037 // Add the offset, cast it to the right type.
3038 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
3039 return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
3042 /// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3043 /// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
3044 /// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3045 /// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
3046 /// sink PtrOffset into user blocks where doing so will likely allow us to fold
3047 /// the constant add into a load or store instruction. Additionally, if a user
3048 /// is a pointer-pointer cast, we look through it to find its users.
3049 static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3050 Constant *PtrOffset, BasicBlock *DefBB,
3051 GetElementPtrInst *GEPI,
3052 std::map<BasicBlock*,Instruction*> &InsertedExprs) {
3053 while (!RepPtr->use_empty()) {
3054 Instruction *User = cast<Instruction>(RepPtr->use_back());
3056 // If the user is a Pointer-Pointer cast, recurse.
3057 if (isa<CastInst>(User) && isa<PointerType>(User->getType())) {
3058 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3060 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
3061 // could invalidate an iterator.
3062 User->setOperand(0, UndefValue::get(RepPtr->getType()));
3066 // If this is a load of the pointer, or a store through the pointer, emit
3067 // the increment into the load/store block.
3068 Instruction *NewVal;
3069 if (isa<LoadInst>(User) ||
3070 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3071 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3072 User->getParent(), GEPI,
3075 // If this use is not foldable into the addressing mode, use a version
3076 // emitted in the GEP block.
3077 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3081 if (GEPI->getType() != RepPtr->getType()) {
3082 BasicBlock::iterator IP = NewVal;
3084 NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP);
3086 User->replaceUsesOfWith(RepPtr, NewVal);
3091 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3092 /// selection, we want to be a bit careful about some things. In particular, if
3093 /// we have a GEP instruction that is used in a different block than it is
3094 /// defined, the addressing expression of the GEP cannot be folded into loads or
3095 /// stores that use it. In this case, decompose the GEP and move constant
3096 /// indices into blocks that use it.
3097 static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
3098 const TargetData *TD) {
3099 // If this GEP is only used inside the block it is defined in, there is no
3100 // need to rewrite it.
3101 bool isUsedOutsideDefBB = false;
3102 BasicBlock *DefBB = GEPI->getParent();
3103 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3105 if (cast<Instruction>(*UI)->getParent() != DefBB) {
3106 isUsedOutsideDefBB = true;
3110 if (!isUsedOutsideDefBB) return false;
3112 // If this GEP has no non-zero constant indices, there is nothing we can do,
3114 bool hasConstantIndex = false;
3115 bool hasVariableIndex = false;
3116 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3117 E = GEPI->op_end(); OI != E; ++OI) {
3118 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
3119 if (CI->getRawValue()) {
3120 hasConstantIndex = true;
3124 hasVariableIndex = true;
3128 // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3129 if (!hasConstantIndex && !hasVariableIndex) {
3130 Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(),
3131 GEPI->getName(), GEPI);
3132 GEPI->replaceAllUsesWith(NC);
3133 GEPI->eraseFromParent();
3137 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
3138 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3141 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
3142 // constant offset (which we now know is non-zero) and deal with it later.
3143 uint64_t ConstantOffset = 0;
3144 const Type *UIntPtrTy = TD->getIntPtrType();
3145 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3146 const Type *Ty = GEPI->getOperand(0)->getType();
3148 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3149 E = GEPI->op_end(); OI != E; ++OI) {
3151 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3152 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
3154 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
3155 Ty = StTy->getElementType(Field);
3157 Ty = cast<SequentialType>(Ty)->getElementType();
3159 // Handle constant subscripts.
3160 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3161 if (CI->getRawValue() == 0) continue;
3163 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
3164 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
3166 ConstantOffset+=TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
3170 // Ptr = Ptr + Idx * ElementSize;
3172 // Cast Idx to UIntPtrTy if needed.
3173 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
3175 uint64_t ElementSize = TD->getTypeSize(Ty);
3176 // Mask off bits that should not be set.
3177 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3178 Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize);
3180 // Multiply by the element size and add to the base.
3181 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3182 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3186 // Make sure that the offset fits in uintptr_t.
3187 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3188 Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset);
3190 // Okay, we have now emitted all of the variable index parts to the BB that
3191 // the GEP is defined in. Loop over all of the using instructions, inserting
3192 // an "add Ptr, ConstantOffset" into each block that uses it and update the
3193 // instruction to use the newly computed value, making GEPI dead. When the
3194 // user is a load or store instruction address, we emit the add into the user
3195 // block, otherwise we use a canonical version right next to the gep (these
3196 // won't be foldable as addresses, so we might as well share the computation).
3198 std::map<BasicBlock*,Instruction*> InsertedExprs;
3199 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3201 // Finally, the GEP is dead, remove it.
3202 GEPI->eraseFromParent();
3207 bool SelectionDAGISel::runOnFunction(Function &Fn) {
3208 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3209 RegMap = MF.getSSARegMap();
3210 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
3212 // First, split all critical edges for PHI nodes with incoming values that are
3213 // constants, this way the load of the constant into a vreg will not be placed
3214 // into MBBs that are used some other way.
3216 // In this pass we also look for GEP and cast instructions that are used
3217 // across basic blocks and rewrite them to improve basic-block-at-a-time
3221 bool MadeChange = true;
3222 while (MadeChange) {
3224 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
3226 BasicBlock::iterator BBI;
3227 for (BBI = BB->begin(); (PN = dyn_cast<PHINode>(BBI)); ++BBI)
3228 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
3229 if (isa<Constant>(PN->getIncomingValue(i)))
3230 SplitCriticalEdge(PN->getIncomingBlock(i), BB);
3232 for (BasicBlock::iterator E = BB->end(); BBI != E; ) {
3233 Instruction *I = BBI++;
3234 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
3235 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
3236 } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
3237 // If this is a noop copy, sink it into user blocks to reduce the number
3238 // of virtual registers that must be created and coallesced.
3239 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
3240 MVT::ValueType DstVT = TLI.getValueType(CI->getType());
3242 // This is an fp<->int conversion?
3243 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
3246 // If this is an extension, it will be a zero or sign extension, which
3248 if (SrcVT < DstVT) continue;
3250 // If these values will be promoted, find out what they will be promoted
3251 // to. This helps us consider truncates on PPC as noop copies when they
3253 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
3254 SrcVT = TLI.getTypeToTransformTo(SrcVT);
3255 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
3256 DstVT = TLI.getTypeToTransformTo(DstVT);
3258 // If, after promotion, these are the same types, this is a noop copy.
3260 MadeChange |= OptimizeNoopCopyExpression(CI);
3266 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
3268 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
3269 SelectBasicBlock(I, MF, FuncInfo);
3275 SDOperand SelectionDAGISel::
3276 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
3277 SDOperand Op = SDL.getValue(V);
3278 assert((Op.getOpcode() != ISD::CopyFromReg ||
3279 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
3280 "Copy from a reg to the same reg!");
3282 // If this type is not legal, we must make sure to not create an invalid
3284 MVT::ValueType SrcVT = Op.getValueType();
3285 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
3286 SelectionDAG &DAG = SDL.DAG;
3287 if (SrcVT == DestVT) {
3288 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3289 } else if (SrcVT == MVT::Vector) {
3290 // Handle copies from generic vectors to registers.
3291 MVT::ValueType PTyElementVT, PTyLegalElementVT;
3292 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
3293 PTyElementVT, PTyLegalElementVT);
3295 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
3296 // MVT::Vector type.
3297 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
3298 DAG.getConstant(NE, MVT::i32),
3299 DAG.getValueType(PTyElementVT));
3301 // Loop over all of the elements of the resultant vector,
3302 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
3303 // copying them into output registers.
3304 std::vector<SDOperand> OutChains;
3305 SDOperand Root = SDL.getRoot();
3306 for (unsigned i = 0; i != NE; ++i) {
3307 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
3308 Op, DAG.getConstant(i, TLI.getPointerTy()));
3309 if (PTyElementVT == PTyLegalElementVT) {
3310 // Elements are legal.
3311 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3312 } else if (PTyLegalElementVT > PTyElementVT) {
3313 // Elements are promoted.
3314 if (MVT::isFloatingPoint(PTyLegalElementVT))
3315 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
3317 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
3318 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3320 // Elements are expanded.
3321 // The src value is expanded into multiple registers.
3322 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3323 Elt, DAG.getConstant(0, TLI.getPointerTy()));
3324 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3325 Elt, DAG.getConstant(1, TLI.getPointerTy()));
3326 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
3327 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
3330 return DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
3331 } else if (SrcVT < DestVT) {
3332 // The src value is promoted to the register.
3333 if (MVT::isFloatingPoint(SrcVT))
3334 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
3336 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
3337 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3339 // The src value is expanded into multiple registers.
3340 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3341 Op, DAG.getConstant(0, TLI.getPointerTy()));
3342 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3343 Op, DAG.getConstant(1, TLI.getPointerTy()));
3344 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
3345 return DAG.getCopyToReg(Op, Reg+1, Hi);
3349 void SelectionDAGISel::
3350 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
3351 std::vector<SDOperand> &UnorderedChains) {
3352 // If this is the entry block, emit arguments.
3353 Function &F = *BB->getParent();
3354 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
3355 SDOperand OldRoot = SDL.DAG.getRoot();
3356 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
3359 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
3361 if (!AI->use_empty()) {
3362 SDL.setValue(AI, Args[a]);
3364 // If this argument is live outside of the entry block, insert a copy from
3365 // whereever we got it to the vreg that other BB's will reference it as.
3366 if (FuncInfo.ValueMap.count(AI)) {
3368 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
3369 UnorderedChains.push_back(Copy);
3373 // Finally, if the target has anything special to do, allow it to do so.
3374 // FIXME: this should insert code into the DAG!
3375 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
3378 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3379 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
3380 FunctionLoweringInfo &FuncInfo) {
3381 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
3383 std::vector<SDOperand> UnorderedChains;
3385 // Lower any arguments needed in this block if this is the entry block.
3386 if (LLVMBB == &LLVMBB->getParent()->front())
3387 LowerArguments(LLVMBB, SDL, UnorderedChains);
3389 BB = FuncInfo.MBBMap[LLVMBB];
3390 SDL.setCurrentBasicBlock(BB);
3392 // Lower all of the non-terminator instructions.
3393 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3397 // Ensure that all instructions which are used outside of their defining
3398 // blocks are available as virtual registers.
3399 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
3400 if (!I->use_empty() && !isa<PHINode>(I)) {
3401 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
3402 if (VMI != FuncInfo.ValueMap.end())
3403 UnorderedChains.push_back(
3404 CopyValueToVirtualRegister(SDL, I, VMI->second));
3407 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
3408 // ensure constants are generated when needed. Remember the virtual registers
3409 // that need to be added to the Machine PHI nodes as input. We cannot just
3410 // directly add them, because expansion might result in multiple MBB's for one
3411 // BB. As such, the start of the BB might correspond to a different MBB than
3415 // Emit constants only once even if used by multiple PHI nodes.
3416 std::map<Constant*, unsigned> ConstantsOut;
3418 // Check successor nodes PHI nodes that expect a constant to be available from
3420 TerminatorInst *TI = LLVMBB->getTerminator();
3421 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
3422 BasicBlock *SuccBB = TI->getSuccessor(succ);
3423 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
3426 // At this point we know that there is a 1-1 correspondence between LLVM PHI
3427 // nodes and Machine PHI nodes, but the incoming operands have not been
3429 for (BasicBlock::iterator I = SuccBB->begin();
3430 (PN = dyn_cast<PHINode>(I)); ++I)
3431 if (!PN->use_empty()) {
3433 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
3434 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
3435 unsigned &RegOut = ConstantsOut[C];
3437 RegOut = FuncInfo.CreateRegForValue(C);
3438 UnorderedChains.push_back(
3439 CopyValueToVirtualRegister(SDL, C, RegOut));
3443 Reg = FuncInfo.ValueMap[PHIOp];
3445 assert(isa<AllocaInst>(PHIOp) &&
3446 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
3447 "Didn't codegen value into a register!??");
3448 Reg = FuncInfo.CreateRegForValue(PHIOp);
3449 UnorderedChains.push_back(
3450 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
3454 // Remember that this register needs to added to the machine PHI node as
3455 // the input for this MBB.
3456 MVT::ValueType VT = TLI.getValueType(PN->getType());
3457 unsigned NumElements;
3458 if (VT != MVT::Vector)
3459 NumElements = TLI.getNumElements(VT);
3461 MVT::ValueType VT1,VT2;
3463 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
3466 for (unsigned i = 0, e = NumElements; i != e; ++i)
3467 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
3470 ConstantsOut.clear();
3472 // Turn all of the unordered chains into one factored node.
3473 if (!UnorderedChains.empty()) {
3474 SDOperand Root = SDL.getRoot();
3475 if (Root.getOpcode() != ISD::EntryToken) {
3476 unsigned i = 0, e = UnorderedChains.size();
3477 for (; i != e; ++i) {
3478 assert(UnorderedChains[i].Val->getNumOperands() > 1);
3479 if (UnorderedChains[i].Val->getOperand(0) == Root)
3480 break; // Don't add the root if we already indirectly depend on it.
3484 UnorderedChains.push_back(Root);
3486 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
3489 // Lower the terminator after the copies are emitted.
3490 SDL.visit(*LLVMBB->getTerminator());
3492 // Copy over any CaseBlock records that may now exist due to SwitchInst
3493 // lowering, as well as any jump table information.
3494 SwitchCases.clear();
3495 SwitchCases = SDL.SwitchCases;
3498 // Make sure the root of the DAG is up-to-date.
3499 DAG.setRoot(SDL.getRoot());
3502 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
3503 // Run the DAG combiner in pre-legalize mode.
3506 DEBUG(std::cerr << "Lowered selection DAG:\n");
3509 // Second step, hack on the DAG until it only uses operations and types that
3510 // the target supports.
3513 DEBUG(std::cerr << "Legalized selection DAG:\n");
3516 // Run the DAG combiner in post-legalize mode.
3519 if (ViewISelDAGs) DAG.viewGraph();
3521 // Third, instruction select all of the operations to machine code, adding the
3522 // code to the MachineBasicBlock.
3523 InstructionSelectBasicBlock(DAG);
3525 DEBUG(std::cerr << "Selected machine code:\n");
3529 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
3530 FunctionLoweringInfo &FuncInfo) {
3531 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
3533 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3536 // First step, lower LLVM code to some DAG. This DAG may use operations and
3537 // types that are not supported by the target.
3538 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
3540 // Second step, emit the lowered DAG as machine code.
3541 CodeGenAndEmitDAG(DAG);
3544 // Next, now that we know what the last MBB the LLVM BB expanded is, update
3545 // PHI nodes in successors.
3546 if (SwitchCases.empty() && JT.Reg == 0) {
3547 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3548 MachineInstr *PHI = PHINodesToUpdate[i].first;
3549 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3550 "This is not a machine PHI node that we are updating!");
3551 PHI->addRegOperand(PHINodesToUpdate[i].second);
3552 PHI->addMachineBasicBlockOperand(BB);
3557 // If the JumpTable record is filled in, then we need to emit a jump table.
3558 // Updating the PHI nodes is tricky in this case, since we need to determine
3559 // whether the PHI is a successor of the range check MBB or the jump table MBB
3561 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
3562 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3564 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3565 MachineBasicBlock *RangeBB = BB;
3566 // Set the current basic block to the mbb we wish to insert the code into
3568 SDL.setCurrentBasicBlock(BB);
3570 SDL.visitJumpTable(JT);
3571 SDAG.setRoot(SDL.getRoot());
3572 CodeGenAndEmitDAG(SDAG);
3574 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3575 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3576 MachineBasicBlock *PHIBB = PHI->getParent();
3577 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3578 "This is not a machine PHI node that we are updating!");
3579 if (PHIBB == JT.Default) {
3580 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3581 PHI->addMachineBasicBlockOperand(RangeBB);
3583 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
3584 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3585 PHI->addMachineBasicBlockOperand(BB);
3591 // If we generated any switch lowering information, build and codegen any
3592 // additional DAGs necessary.
3593 for(unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
3594 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3596 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3597 // Set the current basic block to the mbb we wish to insert the code into
3598 BB = SwitchCases[i].ThisBB;
3599 SDL.setCurrentBasicBlock(BB);
3601 SDL.visitSwitchCase(SwitchCases[i]);
3602 SDAG.setRoot(SDL.getRoot());
3603 CodeGenAndEmitDAG(SDAG);
3604 // Iterate over the phi nodes, if there is a phi node in a successor of this
3605 // block (for instance, the default block), then add a pair of operands to
3606 // the phi node for this block, as if we were coming from the original
3607 // BB before switch expansion.
3608 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3609 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3610 MachineBasicBlock *PHIBB = PHI->getParent();
3611 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3612 "This is not a machine PHI node that we are updating!");
3613 if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
3614 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3615 PHI->addMachineBasicBlockOperand(BB);
3621 //===----------------------------------------------------------------------===//
3622 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
3623 /// target node in the graph.
3624 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
3625 if (ViewSchedDAGs) DAG.viewGraph();
3626 ScheduleDAG *SL = NULL;
3628 switch (ISHeuristic) {
3629 default: assert(0 && "Unrecognized scheduling heuristic");
3630 case defaultScheduling:
3631 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
3632 SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
3634 assert(TLI.getSchedulingPreference() ==
3635 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
3636 SL = createBURRListDAGScheduler(DAG, BB);
3640 SL = createBFS_DAGScheduler(DAG, BB);
3642 case simpleScheduling:
3643 SL = createSimpleDAGScheduler(false, DAG, BB);
3645 case simpleNoItinScheduling:
3646 SL = createSimpleDAGScheduler(true, DAG, BB);
3648 case listSchedulingBURR:
3649 SL = createBURRListDAGScheduler(DAG, BB);
3651 case listSchedulingTDRR:
3652 SL = createTDRRListDAGScheduler(DAG, BB);
3654 case listSchedulingTD:
3655 SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
3662 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
3663 return new HazardRecognizer();
3666 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
3667 /// by tblgen. Others should not call it.
3668 void SelectionDAGISel::
3669 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
3670 std::vector<SDOperand> InOps;
3671 std::swap(InOps, Ops);
3673 Ops.push_back(InOps[0]); // input chain.
3674 Ops.push_back(InOps[1]); // input asm string.
3676 unsigned i = 2, e = InOps.size();
3677 if (InOps[e-1].getValueType() == MVT::Flag)
3678 --e; // Don't process a flag operand if it is here.
3681 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
3682 if ((Flags & 7) != 4 /*MEM*/) {
3683 // Just skip over this operand, copying the operands verbatim.
3684 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
3685 i += (Flags >> 3) + 1;
3687 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
3688 // Otherwise, this is a memory operand. Ask the target to select it.
3689 std::vector<SDOperand> SelOps;
3690 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
3691 std::cerr << "Could not match memory address. Inline asm failure!\n";
3695 // Add this to the output node.
3696 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
3697 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
3702 // Add the flag input back if present.
3703 if (e != InOps.size())
3704 Ops.push_back(InOps.back());