1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/CodeGen/ScheduleDAG.h"
17 #include "llvm/CallingConv.h"
18 #include "llvm/Constants.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/InlineAsm.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineDebugInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SchedulerRegistry.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/CodeGen/SSARegMap.h"
35 #include "llvm/Target/MRegisterInfo.h"
36 #include "llvm/Target/TargetData.h"
37 #include "llvm/Target/TargetFrameInfo.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetLowering.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/Compiler.h"
54 ViewISelDAGs("view-isel-dags", cl::Hidden,
55 cl::desc("Pop up a window to show isel dags as they are selected"));
57 ViewSchedDAGs("view-sched-dags", cl::Hidden,
58 cl::desc("Pop up a window to show sched dags as they are processed"));
60 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
64 //===---------------------------------------------------------------------===//
66 /// RegisterScheduler class - Track the registration of instruction schedulers.
68 //===---------------------------------------------------------------------===//
69 MachinePassRegistry RegisterScheduler::Registry;
71 //===---------------------------------------------------------------------===//
73 /// ISHeuristic command line option for instruction schedulers.
75 //===---------------------------------------------------------------------===//
77 cl::opt<RegisterScheduler::FunctionPassCtor, false,
78 RegisterPassParser<RegisterScheduler> >
80 cl::init(&createDefaultScheduler),
81 cl::desc("Instruction schedulers available:"));
83 static RegisterScheduler
84 defaultListDAGScheduler("default", " Best scheduler for the target",
85 createDefaultScheduler);
89 /// RegsForValue - This struct represents the physical registers that a
90 /// particular value is assigned and the type information about the value.
91 /// This is needed because values can be promoted into larger registers and
92 /// expanded into multiple smaller registers than the value.
93 struct VISIBILITY_HIDDEN RegsForValue {
94 /// Regs - This list hold the register (for legal and promoted values)
95 /// or register set (for expanded values) that the value should be assigned
97 std::vector<unsigned> Regs;
99 /// RegVT - The value type of each register.
101 MVT::ValueType RegVT;
103 /// ValueVT - The value type of the LLVM value, which may be promoted from
104 /// RegVT or made from merging the two expanded parts.
105 MVT::ValueType ValueVT;
107 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
109 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
110 : RegVT(regvt), ValueVT(valuevt) {
113 RegsForValue(const std::vector<unsigned> ®s,
114 MVT::ValueType regvt, MVT::ValueType valuevt)
115 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
118 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
119 /// this value and returns the result as a ValueVT value. This uses
120 /// Chain/Flag as the input and updates them for the output Chain/Flag.
121 SDOperand getCopyFromRegs(SelectionDAG &DAG,
122 SDOperand &Chain, SDOperand &Flag) const;
124 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
125 /// specified value into the registers specified by this object. This uses
126 /// Chain/Flag as the input and updates them for the output Chain/Flag.
127 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
128 SDOperand &Chain, SDOperand &Flag,
129 MVT::ValueType PtrVT) const;
131 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
132 /// operand list. This adds the code marker and includes the number of
133 /// values added into it.
134 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
135 std::vector<SDOperand> &Ops) const;
140 //===--------------------------------------------------------------------===//
141 /// createDefaultScheduler - This creates an instruction scheduler appropriate
143 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
145 MachineBasicBlock *BB) {
146 TargetLowering &TLI = IS->getTargetLowering();
148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
149 return createTDListDAGScheduler(IS, DAG, BB);
151 assert(TLI.getSchedulingPreference() ==
152 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
153 return createBURRListDAGScheduler(IS, DAG, BB);
158 //===--------------------------------------------------------------------===//
159 /// FunctionLoweringInfo - This contains information that is global to a
160 /// function that is used when lowering a region of the function.
161 class FunctionLoweringInfo {
168 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
170 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
171 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
173 /// ValueMap - Since we emit code for the function a basic block at a time,
174 /// we must remember which virtual registers hold the values for
175 /// cross-basic-block values.
176 std::map<const Value*, unsigned> ValueMap;
178 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
179 /// the entry block. This allows the allocas to be efficiently referenced
180 /// anywhere in the function.
181 std::map<const AllocaInst*, int> StaticAllocaMap;
183 unsigned MakeReg(MVT::ValueType VT) {
184 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
187 unsigned CreateRegForValue(const Value *V);
189 unsigned InitializeRegForValue(const Value *V) {
190 unsigned &R = ValueMap[V];
191 assert(R == 0 && "Already initialized this value register!");
192 return R = CreateRegForValue(V);
197 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
198 /// PHI nodes or outside of the basic block that defines it, or used by a
199 /// switch instruction, which may expand to multiple basic blocks.
200 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
201 if (isa<PHINode>(I)) return true;
202 BasicBlock *BB = I->getParent();
203 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
204 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
205 isa<SwitchInst>(*UI))
210 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
211 /// entry block, return true. This includes arguments used by switches, since
212 /// the switch may expand into multiple basic blocks.
213 static bool isOnlyUsedInEntryBlock(Argument *A) {
214 BasicBlock *Entry = A->getParent()->begin();
215 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
216 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
217 return false; // Use not in entry block.
221 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
222 Function &fn, MachineFunction &mf)
223 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
225 // Create a vreg for each argument register that is not dead and is used
226 // outside of the entry block for the function.
227 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
229 if (!isOnlyUsedInEntryBlock(AI))
230 InitializeRegForValue(AI);
232 // Initialize the mapping of values to registers. This is only set up for
233 // instruction values that are used outside of the block that defines
235 Function::iterator BB = Fn.begin(), EB = Fn.end();
236 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
237 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
238 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
239 const Type *Ty = AI->getAllocatedType();
240 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
242 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
245 // If the alignment of the value is smaller than the size of the value,
246 // and if the size of the value is particularly small (<= 8 bytes),
247 // round up to the size of the value for potentially better performance.
249 // FIXME: This could be made better with a preferred alignment hook in
250 // TargetData. It serves primarily to 8-byte align doubles for X86.
251 if (Align < TySize && TySize <= 8) Align = TySize;
252 TySize *= CUI->getValue(); // Get total allocated size.
253 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
254 StaticAllocaMap[AI] =
255 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
258 for (; BB != EB; ++BB)
259 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
260 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
261 if (!isa<AllocaInst>(I) ||
262 !StaticAllocaMap.count(cast<AllocaInst>(I)))
263 InitializeRegForValue(I);
265 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
266 // also creates the initial PHI MachineInstrs, though none of the input
267 // operands are populated.
268 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
269 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
271 MF.getBasicBlockList().push_back(MBB);
273 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
276 for (BasicBlock::iterator I = BB->begin();
277 (PN = dyn_cast<PHINode>(I)); ++I)
278 if (!PN->use_empty()) {
279 MVT::ValueType VT = TLI.getValueType(PN->getType());
280 unsigned NumElements;
281 if (VT != MVT::Vector)
282 NumElements = TLI.getNumElements(VT);
284 MVT::ValueType VT1,VT2;
286 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
289 unsigned PHIReg = ValueMap[PN];
290 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
291 for (unsigned i = 0; i != NumElements; ++i)
292 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
297 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
298 /// the correctly promoted or expanded types. Assign these registers
299 /// consecutive vreg numbers and return the first assigned number.
300 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
301 MVT::ValueType VT = TLI.getValueType(V->getType());
303 // The number of multiples of registers that we need, to, e.g., split up
304 // a <2 x int64> -> 4 x i32 registers.
305 unsigned NumVectorRegs = 1;
307 // If this is a packed type, figure out what type it will decompose into
308 // and how many of the elements it will use.
309 if (VT == MVT::Vector) {
310 const PackedType *PTy = cast<PackedType>(V->getType());
311 unsigned NumElts = PTy->getNumElements();
312 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
314 // Divide the input until we get to a supported size. This will always
315 // end with a scalar if the target doesn't support vectors.
316 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
323 VT = getVectorType(EltTy, NumElts);
326 // The common case is that we will only create one register for this
327 // value. If we have that case, create and return the virtual register.
328 unsigned NV = TLI.getNumElements(VT);
330 // If we are promoting this value, pick the next largest supported type.
331 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
332 unsigned Reg = MakeReg(PromotedType);
333 // If this is a vector of supported or promoted types (e.g. 4 x i16),
334 // create all of the registers.
335 for (unsigned i = 1; i != NumVectorRegs; ++i)
336 MakeReg(PromotedType);
340 // If this value is represented with multiple target registers, make sure
341 // to create enough consecutive registers of the right (smaller) type.
342 unsigned NT = VT-1; // Find the type to use.
343 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
346 unsigned R = MakeReg((MVT::ValueType)NT);
347 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
348 MakeReg((MVT::ValueType)NT);
352 //===----------------------------------------------------------------------===//
353 /// SelectionDAGLowering - This is the common target-independent lowering
354 /// implementation that is parameterized by a TargetLowering object.
355 /// Also, targets can overload any lowering method.
358 class SelectionDAGLowering {
359 MachineBasicBlock *CurMBB;
361 std::map<const Value*, SDOperand> NodeMap;
363 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
364 /// them up and then emit token factor nodes when possible. This allows us to
365 /// get simple disambiguation between loads without worrying about alias
367 std::vector<SDOperand> PendingLoads;
369 /// Case - A pair of values to record the Value for a switch case, and the
370 /// case's target basic block.
371 typedef std::pair<Constant*, MachineBasicBlock*> Case;
372 typedef std::vector<Case>::iterator CaseItr;
373 typedef std::pair<CaseItr, CaseItr> CaseRange;
375 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
376 /// of conditional branches.
378 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
379 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
381 /// CaseBB - The MBB in which to emit the compare and branch
382 MachineBasicBlock *CaseBB;
383 /// LT, GE - If nonzero, we know the current case value must be less-than or
384 /// greater-than-or-equal-to these Constants.
387 /// Range - A pair of iterators representing the range of case values to be
388 /// processed at this point in the binary search tree.
392 /// The comparison function for sorting Case values.
394 bool operator () (const Case& C1, const Case& C2) {
395 if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first))
396 return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue();
398 const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first);
399 return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue();
404 // TLI - This is information that describes the available target features we
405 // need for lowering. This indicates when operations are unavailable,
406 // implemented with a libcall, etc.
409 const TargetData *TD;
411 /// SwitchCases - Vector of CaseBlock structures used to communicate
412 /// SwitchInst code generation information.
413 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
414 SelectionDAGISel::JumpTable JT;
416 /// FuncInfo - Information about the function as a whole.
418 FunctionLoweringInfo &FuncInfo;
420 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
421 FunctionLoweringInfo &funcinfo)
422 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
423 JT(0,0,0,0), FuncInfo(funcinfo) {
426 /// getRoot - Return the current virtual root of the Selection DAG.
428 SDOperand getRoot() {
429 if (PendingLoads.empty())
430 return DAG.getRoot();
432 if (PendingLoads.size() == 1) {
433 SDOperand Root = PendingLoads[0];
435 PendingLoads.clear();
439 // Otherwise, we have to make a token factor node.
440 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
441 &PendingLoads[0], PendingLoads.size());
442 PendingLoads.clear();
447 void visit(Instruction &I) { visit(I.getOpcode(), I); }
449 void visit(unsigned Opcode, User &I) {
451 default: assert(0 && "Unknown instruction type encountered!");
453 // Build the switch statement using the Instruction.def file.
454 #define HANDLE_INST(NUM, OPCODE, CLASS) \
455 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
456 #include "llvm/Instruction.def"
460 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
462 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
463 const Value *SV, SDOperand Root,
466 SDOperand getIntPtrConstant(uint64_t Val) {
467 return DAG.getConstant(Val, TLI.getPointerTy());
470 SDOperand getValue(const Value *V);
472 const SDOperand &setValue(const Value *V, SDOperand NewN) {
473 SDOperand &N = NodeMap[V];
474 assert(N.Val == 0 && "Already set a value for this node!");
478 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
480 bool OutReg, bool InReg,
481 std::set<unsigned> &OutputRegs,
482 std::set<unsigned> &InputRegs);
484 // Terminator instructions.
485 void visitRet(ReturnInst &I);
486 void visitBr(BranchInst &I);
487 void visitSwitch(SwitchInst &I);
488 void visitUnreachable(UnreachableInst &I) { /* noop */ }
490 // Helper for visitSwitch
491 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
492 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
494 // These all get lowered before this pass.
495 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
496 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
498 void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
499 void visitShift(User &I, unsigned Opcode);
500 void visitAdd(User &I) {
501 visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
503 void visitSub(User &I);
504 void visitMul(User &I) {
505 visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
507 void visitDiv(User &I) {
508 const Type *Ty = I.getType();
510 Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
511 Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
513 void visitRem(User &I) {
514 const Type *Ty = I.getType();
515 visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
517 void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
518 void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
519 void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
520 void visitShl(User &I) { visitShift(I, ISD::SHL); }
521 void visitShr(User &I) {
522 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
525 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc,
526 ISD::CondCode FPOpc);
527 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ,
529 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE,
531 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE,
533 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE,
535 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT,
537 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT,
540 void visitExtractElement(User &I);
541 void visitInsertElement(User &I);
542 void visitShuffleVector(User &I);
544 void visitGetElementPtr(User &I);
545 void visitCast(User &I);
546 void visitSelect(User &I);
548 void visitMalloc(MallocInst &I);
549 void visitFree(FreeInst &I);
550 void visitAlloca(AllocaInst &I);
551 void visitLoad(LoadInst &I);
552 void visitStore(StoreInst &I);
553 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
554 void visitCall(CallInst &I);
555 void visitInlineAsm(CallInst &I);
556 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
557 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
559 void visitVAStart(CallInst &I);
560 void visitVAArg(VAArgInst &I);
561 void visitVAEnd(CallInst &I);
562 void visitVACopy(CallInst &I);
563 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
565 void visitMemIntrinsic(CallInst &I, unsigned Op);
567 void visitUserOp1(Instruction &I) {
568 assert(0 && "UserOp1 should not exist at instruction selection time!");
571 void visitUserOp2(Instruction &I) {
572 assert(0 && "UserOp2 should not exist at instruction selection time!");
576 } // end namespace llvm
578 SDOperand SelectionDAGLowering::getValue(const Value *V) {
579 SDOperand &N = NodeMap[V];
582 const Type *VTy = V->getType();
583 MVT::ValueType VT = TLI.getValueType(VTy);
584 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
585 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
586 visit(CE->getOpcode(), *CE);
587 assert(N.Val && "visit didn't populate the ValueMap!");
589 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
590 return N = DAG.getGlobalAddress(GV, VT);
591 } else if (isa<ConstantPointerNull>(C)) {
592 return N = DAG.getConstant(0, TLI.getPointerTy());
593 } else if (isa<UndefValue>(C)) {
594 if (!isa<PackedType>(VTy))
595 return N = DAG.getNode(ISD::UNDEF, VT);
597 // Create a VBUILD_VECTOR of undef nodes.
598 const PackedType *PTy = cast<PackedType>(VTy);
599 unsigned NumElements = PTy->getNumElements();
600 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
602 SmallVector<SDOperand, 8> Ops;
603 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
605 // Create a VConstant node with generic Vector type.
606 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
607 Ops.push_back(DAG.getValueType(PVT));
608 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
609 &Ops[0], Ops.size());
610 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
611 return N = DAG.getConstantFP(CFP->getValue(), VT);
612 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
613 unsigned NumElements = PTy->getNumElements();
614 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
616 // Now that we know the number and type of the elements, push a
617 // Constant or ConstantFP node onto the ops list for each element of
618 // the packed constant.
619 SmallVector<SDOperand, 8> Ops;
620 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
621 for (unsigned i = 0; i != NumElements; ++i)
622 Ops.push_back(getValue(CP->getOperand(i)));
624 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
626 if (MVT::isFloatingPoint(PVT))
627 Op = DAG.getConstantFP(0, PVT);
629 Op = DAG.getConstant(0, PVT);
630 Ops.assign(NumElements, Op);
633 // Create a VBUILD_VECTOR node with generic Vector type.
634 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
635 Ops.push_back(DAG.getValueType(PVT));
636 return N = DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector,&Ops[0],Ops.size());
638 // Canonicalize all constant ints to be unsigned.
639 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
643 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
644 std::map<const AllocaInst*, int>::iterator SI =
645 FuncInfo.StaticAllocaMap.find(AI);
646 if (SI != FuncInfo.StaticAllocaMap.end())
647 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
650 std::map<const Value*, unsigned>::const_iterator VMI =
651 FuncInfo.ValueMap.find(V);
652 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
654 unsigned InReg = VMI->second;
656 // If this type is not legal, make it so now.
657 if (VT != MVT::Vector) {
658 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
660 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
662 // Source must be expanded. This input value is actually coming from the
663 // register pair VMI->second and VMI->second+1.
664 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
665 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
666 } else if (DestVT > VT) { // Promotion case
667 if (MVT::isFloatingPoint(VT))
668 N = DAG.getNode(ISD::FP_ROUND, VT, N);
670 N = DAG.getNode(ISD::TRUNCATE, VT, N);
673 // Otherwise, if this is a vector, make it available as a generic vector
675 MVT::ValueType PTyElementVT, PTyLegalElementVT;
676 const PackedType *PTy = cast<PackedType>(VTy);
677 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
680 // Build a VBUILD_VECTOR with the input registers.
681 SmallVector<SDOperand, 8> Ops;
682 if (PTyElementVT == PTyLegalElementVT) {
683 // If the value types are legal, just VBUILD the CopyFromReg nodes.
684 for (unsigned i = 0; i != NE; ++i)
685 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
687 } else if (PTyElementVT < PTyLegalElementVT) {
688 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
689 for (unsigned i = 0; i != NE; ++i) {
690 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
692 if (MVT::isFloatingPoint(PTyElementVT))
693 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
695 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
699 // If the register was expanded, use BUILD_PAIR.
700 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
701 for (unsigned i = 0; i != NE/2; ++i) {
702 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
704 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
706 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
710 Ops.push_back(DAG.getConstant(NE, MVT::i32));
711 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
712 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
714 // Finally, use a VBIT_CONVERT to make this available as the appropriate
716 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
717 DAG.getConstant(PTy->getNumElements(),
719 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
726 void SelectionDAGLowering::visitRet(ReturnInst &I) {
727 if (I.getNumOperands() == 0) {
728 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
731 SmallVector<SDOperand, 8> NewValues;
732 NewValues.push_back(getRoot());
733 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
734 SDOperand RetOp = getValue(I.getOperand(i));
735 bool isSigned = I.getOperand(i)->getType()->isSigned();
737 // If this is an integer return value, we need to promote it ourselves to
738 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
740 // FIXME: C calling convention requires the return type to be promoted to
741 // at least 32-bit. But this is not necessary for non-C calling conventions.
742 if (MVT::isInteger(RetOp.getValueType()) &&
743 RetOp.getValueType() < MVT::i64) {
744 MVT::ValueType TmpVT;
745 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
746 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
751 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
753 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
755 NewValues.push_back(RetOp);
756 NewValues.push_back(DAG.getConstant(isSigned, MVT::i32));
758 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
759 &NewValues[0], NewValues.size()));
762 void SelectionDAGLowering::visitBr(BranchInst &I) {
763 // Update machine-CFG edges.
764 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
765 CurMBB->addSuccessor(Succ0MBB);
767 // Figure out which block is immediately after the current one.
768 MachineBasicBlock *NextBlock = 0;
769 MachineFunction::iterator BBI = CurMBB;
770 if (++BBI != CurMBB->getParent()->end())
773 if (I.isUnconditional()) {
774 // If this is not a fall-through branch, emit the branch.
775 if (Succ0MBB != NextBlock)
776 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
777 DAG.getBasicBlock(Succ0MBB)));
779 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
780 CurMBB->addSuccessor(Succ1MBB);
782 SDOperand Cond = getValue(I.getCondition());
783 if (Succ1MBB == NextBlock) {
784 // If the condition is false, fall through. This means we should branch
785 // if the condition is true to Succ #0.
786 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
787 Cond, DAG.getBasicBlock(Succ0MBB)));
788 } else if (Succ0MBB == NextBlock) {
789 // If the condition is true, fall through. This means we should branch if
790 // the condition is false to Succ #1. Invert the condition first.
791 SDOperand True = DAG.getConstant(1, Cond.getValueType());
792 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
793 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
794 Cond, DAG.getBasicBlock(Succ1MBB)));
796 std::vector<SDOperand> Ops;
797 Ops.push_back(getRoot());
798 // If the false case is the current basic block, then this is a self
799 // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
800 // adds an extra instruction in the loop. Instead, invert the
801 // condition and emit "Loop: ... br!cond Loop; br Out.
802 if (CurMBB == Succ1MBB) {
803 std::swap(Succ0MBB, Succ1MBB);
804 SDOperand True = DAG.getConstant(1, Cond.getValueType());
805 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
807 SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
808 DAG.getBasicBlock(Succ0MBB));
809 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
810 DAG.getBasicBlock(Succ1MBB)));
815 /// visitSwitchCase - Emits the necessary code to represent a single node in
816 /// the binary search tree resulting from lowering a switch instruction.
817 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
818 SDOperand SwitchOp = getValue(CB.SwitchV);
819 SDOperand CaseOp = getValue(CB.CaseC);
820 SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC);
822 // Set NextBlock to be the MBB immediately after the current one, if any.
823 // This is used to avoid emitting unnecessary branches to the next block.
824 MachineBasicBlock *NextBlock = 0;
825 MachineFunction::iterator BBI = CurMBB;
826 if (++BBI != CurMBB->getParent()->end())
829 // If the lhs block is the next block, invert the condition so that we can
830 // fall through to the lhs instead of the rhs block.
831 if (CB.LHSBB == NextBlock) {
832 std::swap(CB.LHSBB, CB.RHSBB);
833 SDOperand True = DAG.getConstant(1, Cond.getValueType());
834 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
836 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
837 DAG.getBasicBlock(CB.LHSBB));
838 if (CB.RHSBB == NextBlock)
841 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
842 DAG.getBasicBlock(CB.RHSBB)));
843 // Update successor info
844 CurMBB->addSuccessor(CB.LHSBB);
845 CurMBB->addSuccessor(CB.RHSBB);
848 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
849 // Emit the code for the jump table
850 MVT::ValueType PTy = TLI.getPointerTy();
851 assert((PTy == MVT::i32 || PTy == MVT::i64) &&
852 "Jump table entries are 32-bit values");
853 bool isPIC = TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_;
854 // PIC jump table entries are 32-bit values.
855 unsigned EntrySize = isPIC ? 4 : MVT::getSizeInBits(PTy)/8;
856 SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
857 SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy,
858 DAG.getConstant(EntrySize, PTy));
859 SDOperand TAB = DAG.getJumpTable(JT.JTI,PTy);
860 SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, TAB);
861 SDOperand LD = DAG.getLoad(isPIC ? MVT::i32 : PTy, Copy.getValue(1), ADD,
864 // For Pic, the sequence is:
865 // BRIND(load(Jumptable + index) + RelocBase)
866 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
867 SDOperand Reloc = DAG.getNode(ISD::JumpTableRelocBase, PTy, TAB);
868 ADD = DAG.getNode(ISD::ADD, PTy,
869 ((PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD), Reloc);
870 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), ADD));
872 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD));
876 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
877 // Figure out which block is immediately after the current one.
878 MachineBasicBlock *NextBlock = 0;
879 MachineFunction::iterator BBI = CurMBB;
880 if (++BBI != CurMBB->getParent()->end())
883 // If there is only the default destination, branch to it if it is not the
884 // next basic block. Otherwise, just fall through.
885 if (I.getNumOperands() == 2) {
886 // Update machine-CFG edges.
887 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()];
888 // If this is not a fall-through branch, emit the branch.
889 if (DefaultMBB != NextBlock)
890 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
891 DAG.getBasicBlock(DefaultMBB)));
892 CurMBB->addSuccessor(DefaultMBB);
896 // If there are any non-default case statements, create a vector of Cases
897 // representing each one, and sort the vector so that we can efficiently
898 // create a binary search tree from them.
899 std::vector<Case> Cases;
900 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
901 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
902 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
904 std::sort(Cases.begin(), Cases.end(), CaseCmp());
906 // Get the Value to be switched on and default basic blocks, which will be
907 // inserted into CaseBlock records, representing basic blocks in the binary
909 Value *SV = I.getOperand(0);
910 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
912 // Get the MachineFunction which holds the current MBB. This is used during
913 // emission of jump tables, and when inserting any additional MBBs necessary
914 // to represent the switch.
915 MachineFunction *CurMF = CurMBB->getParent();
916 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
918 // If the switch has more than 5 blocks, and at least 31.25% dense, and the
919 // target supports indirect branches, then emit a jump table rather than
920 // lowering the switch to a binary tree of conditional branches.
921 if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) &&
923 uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue();
924 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getRawValue();
925 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
927 if (Density >= 0.3125) {
928 // Create a new basic block to hold the code for loading the address
929 // of the jump table, and jumping to it. Update successor information;
930 // we will either branch to the default case for the switch, or the jump
932 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
933 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
934 CurMBB->addSuccessor(Default);
935 CurMBB->addSuccessor(JumpTableBB);
937 // Subtract the lowest switch case value from the value being switched on
938 // and conditional branch to default mbb if the result is greater than the
939 // difference between smallest and largest cases.
940 SDOperand SwitchOp = getValue(SV);
941 MVT::ValueType VT = SwitchOp.getValueType();
942 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
943 DAG.getConstant(First, VT));
945 // The SDNode we just created, which holds the value being switched on
946 // minus the the smallest case value, needs to be copied to a virtual
947 // register so it can be used as an index into the jump table in a
948 // subsequent basic block. This value may be smaller or larger than the
949 // target's pointer type, and therefore require extension or truncating.
950 if (VT > TLI.getPointerTy())
951 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
953 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
954 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
955 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
957 // Emit the range check for the jump table, and branch to the default
958 // block for the switch statement if the value being switched on exceeds
959 // the largest case in the switch.
960 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
961 DAG.getConstant(Last-First,VT), ISD::SETUGT);
962 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
963 DAG.getBasicBlock(Default)));
965 // Build a vector of destination BBs, corresponding to each target
966 // of the jump table. If the value of the jump table slot corresponds to
967 // a case statement, push the case's BB onto the vector, otherwise, push
969 std::vector<MachineBasicBlock*> DestBBs;
970 uint64_t TEI = First;
971 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) {
972 if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) {
973 DestBBs.push_back(ii->second);
976 DestBBs.push_back(Default);
980 // Update successor info
981 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
982 E = DestBBs.end(); I != E; ++I)
983 JumpTableBB->addSuccessor(*I);
985 // Create a jump table index for this jump table, or return an existing
987 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
989 // Set the jump table information so that we can codegen it as a second
991 JT.Reg = JumpTableReg;
993 JT.MBB = JumpTableBB;
994 JT.Default = Default;
999 // Push the initial CaseRec onto the worklist
1000 std::vector<CaseRec> CaseVec;
1001 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1003 while (!CaseVec.empty()) {
1004 // Grab a record representing a case range to process off the worklist
1005 CaseRec CR = CaseVec.back();
1008 // Size is the number of Cases represented by this range. If Size is 1,
1009 // then we are processing a leaf of the binary search tree. Otherwise,
1010 // we need to pick a pivot, and push left and right ranges onto the
1012 unsigned Size = CR.Range.second - CR.Range.first;
1015 // Create a CaseBlock record representing a conditional branch to
1016 // the Case's target mbb if the value being switched on SV is equal
1017 // to C. Otherwise, branch to default.
1018 Constant *C = CR.Range.first->first;
1019 MachineBasicBlock *Target = CR.Range.first->second;
1020 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1022 // If the MBB representing the leaf node is the current MBB, then just
1023 // call visitSwitchCase to emit the code into the current block.
1024 // Otherwise, push the CaseBlock onto the vector to be later processed
1025 // by SDISel, and insert the node's MBB before the next MBB.
1026 if (CR.CaseBB == CurMBB)
1027 visitSwitchCase(CB);
1029 SwitchCases.push_back(CB);
1030 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1033 // split case range at pivot
1034 CaseItr Pivot = CR.Range.first + (Size / 2);
1035 CaseRange LHSR(CR.Range.first, Pivot);
1036 CaseRange RHSR(Pivot, CR.Range.second);
1037 Constant *C = Pivot->first;
1038 MachineBasicBlock *RHSBB = 0, *LHSBB = 0;
1039 // We know that we branch to the LHS if the Value being switched on is
1040 // less than the Pivot value, C. We use this to optimize our binary
1041 // tree a bit, by recognizing that if SV is greater than or equal to the
1042 // LHS's Case Value, and that Case Value is exactly one less than the
1043 // Pivot's Value, then we can branch directly to the LHS's Target,
1044 // rather than creating a leaf node for it.
1045 if ((LHSR.second - LHSR.first) == 1 &&
1046 LHSR.first->first == CR.GE &&
1047 cast<ConstantIntegral>(C)->getRawValue() ==
1048 (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) {
1049 LHSBB = LHSR.first->second;
1051 LHSBB = new MachineBasicBlock(LLVMBB);
1052 CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR));
1054 // Similar to the optimization above, if the Value being switched on is
1055 // known to be less than the Constant CR.LT, and the current Case Value
1056 // is CR.LT - 1, then we can branch directly to the target block for
1057 // the current Case Value, rather than emitting a RHS leaf node for it.
1058 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1059 cast<ConstantIntegral>(RHSR.first->first)->getRawValue() ==
1060 (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) {
1061 RHSBB = RHSR.first->second;
1063 RHSBB = new MachineBasicBlock(LLVMBB);
1064 CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR));
1066 // Create a CaseBlock record representing a conditional branch to
1067 // the LHS node if the value being switched on SV is less than C.
1068 // Otherwise, branch to LHS.
1069 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
1070 SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB);
1071 if (CR.CaseBB == CurMBB)
1072 visitSwitchCase(CB);
1074 SwitchCases.push_back(CB);
1075 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1081 void SelectionDAGLowering::visitSub(User &I) {
1082 // -0.0 - X --> fneg
1083 if (I.getType()->isFloatingPoint()) {
1084 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1085 if (CFP->isExactlyValue(-0.0)) {
1086 SDOperand Op2 = getValue(I.getOperand(1));
1087 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1091 visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
1094 void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
1096 const Type *Ty = I.getType();
1097 SDOperand Op1 = getValue(I.getOperand(0));
1098 SDOperand Op2 = getValue(I.getOperand(1));
1100 if (Ty->isIntegral()) {
1101 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
1102 } else if (Ty->isFloatingPoint()) {
1103 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
1105 const PackedType *PTy = cast<PackedType>(Ty);
1106 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1107 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1108 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1112 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1113 SDOperand Op1 = getValue(I.getOperand(0));
1114 SDOperand Op2 = getValue(I.getOperand(1));
1116 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1118 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1121 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
1122 ISD::CondCode UnsignedOpcode,
1123 ISD::CondCode FPOpcode) {
1124 SDOperand Op1 = getValue(I.getOperand(0));
1125 SDOperand Op2 = getValue(I.getOperand(1));
1126 ISD::CondCode Opcode = SignedOpcode;
1127 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint())
1129 else if (I.getOperand(0)->getType()->isUnsigned())
1130 Opcode = UnsignedOpcode;
1131 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1134 void SelectionDAGLowering::visitSelect(User &I) {
1135 SDOperand Cond = getValue(I.getOperand(0));
1136 SDOperand TrueVal = getValue(I.getOperand(1));
1137 SDOperand FalseVal = getValue(I.getOperand(2));
1138 if (!isa<PackedType>(I.getType())) {
1139 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1140 TrueVal, FalseVal));
1142 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1143 *(TrueVal.Val->op_end()-2),
1144 *(TrueVal.Val->op_end()-1)));
1148 void SelectionDAGLowering::visitCast(User &I) {
1149 SDOperand N = getValue(I.getOperand(0));
1150 MVT::ValueType SrcVT = N.getValueType();
1151 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1153 if (DestVT == MVT::Vector) {
1154 // This is a cast to a vector from something else. This is always a bit
1155 // convert. Get information about the input vector.
1156 const PackedType *DestTy = cast<PackedType>(I.getType());
1157 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1158 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1159 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1160 DAG.getValueType(EltVT)));
1161 } else if (SrcVT == DestVT) {
1162 setValue(&I, N); // noop cast.
1163 } else if (DestVT == MVT::i1) {
1164 // Cast to bool is a comparison against zero, not truncation to zero.
1165 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
1166 DAG.getConstantFP(0.0, N.getValueType());
1167 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
1168 } else if (isInteger(SrcVT)) {
1169 if (isInteger(DestVT)) { // Int -> Int cast
1170 if (DestVT < SrcVT) // Truncating cast?
1171 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1172 else if (I.getOperand(0)->getType()->isSigned())
1173 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1175 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1176 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast
1177 if (I.getOperand(0)->getType()->isSigned())
1178 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1180 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1182 assert(0 && "Unknown cast!");
1184 } else if (isFloatingPoint(SrcVT)) {
1185 if (isFloatingPoint(DestVT)) { // FP -> FP cast
1186 if (DestVT < SrcVT) // Rounding cast?
1187 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1189 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1190 } else if (isInteger(DestVT)) { // FP -> Int cast.
1191 if (I.getType()->isSigned())
1192 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1194 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1196 assert(0 && "Unknown cast!");
1199 assert(SrcVT == MVT::Vector && "Unknown cast!");
1200 assert(DestVT != MVT::Vector && "Casts to vector already handled!");
1201 // This is a cast from a vector to something else. This is always a bit
1202 // convert. Get information about the input vector.
1203 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1207 void SelectionDAGLowering::visitInsertElement(User &I) {
1208 SDOperand InVec = getValue(I.getOperand(0));
1209 SDOperand InVal = getValue(I.getOperand(1));
1210 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1211 getValue(I.getOperand(2)));
1213 SDOperand Num = *(InVec.Val->op_end()-2);
1214 SDOperand Typ = *(InVec.Val->op_end()-1);
1215 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1216 InVec, InVal, InIdx, Num, Typ));
1219 void SelectionDAGLowering::visitExtractElement(User &I) {
1220 SDOperand InVec = getValue(I.getOperand(0));
1221 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1222 getValue(I.getOperand(1)));
1223 SDOperand Typ = *(InVec.Val->op_end()-1);
1224 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1225 TLI.getValueType(I.getType()), InVec, InIdx));
1228 void SelectionDAGLowering::visitShuffleVector(User &I) {
1229 SDOperand V1 = getValue(I.getOperand(0));
1230 SDOperand V2 = getValue(I.getOperand(1));
1231 SDOperand Mask = getValue(I.getOperand(2));
1233 SDOperand Num = *(V1.Val->op_end()-2);
1234 SDOperand Typ = *(V2.Val->op_end()-1);
1235 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1236 V1, V2, Mask, Num, Typ));
1240 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1241 SDOperand N = getValue(I.getOperand(0));
1242 const Type *Ty = I.getOperand(0)->getType();
1244 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1247 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1248 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
1251 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
1252 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1253 getIntPtrConstant(Offset));
1255 Ty = StTy->getElementType(Field);
1257 Ty = cast<SequentialType>(Ty)->getElementType();
1259 // If this is a constant subscript, handle it quickly.
1260 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1261 if (CI->getRawValue() == 0) continue;
1264 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
1265 Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
1267 Offs = TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
1268 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1272 // N = N + Idx * ElementSize;
1273 uint64_t ElementSize = TD->getTypeSize(Ty);
1274 SDOperand IdxN = getValue(Idx);
1276 // If the index is smaller or larger than intptr_t, truncate or extend
1278 if (IdxN.getValueType() < N.getValueType()) {
1279 if (Idx->getType()->isSigned())
1280 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1282 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
1283 } else if (IdxN.getValueType() > N.getValueType())
1284 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1286 // If this is a multiply by a power of two, turn it into a shl
1287 // immediately. This is a very common case.
1288 if (isPowerOf2_64(ElementSize)) {
1289 unsigned Amt = Log2_64(ElementSize);
1290 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1291 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1292 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1296 SDOperand Scale = getIntPtrConstant(ElementSize);
1297 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1298 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1304 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1305 // If this is a fixed sized alloca in the entry block of the function,
1306 // allocate it statically on the stack.
1307 if (FuncInfo.StaticAllocaMap.count(&I))
1308 return; // getValue will auto-populate this.
1310 const Type *Ty = I.getAllocatedType();
1311 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1312 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
1315 SDOperand AllocSize = getValue(I.getArraySize());
1316 MVT::ValueType IntPtr = TLI.getPointerTy();
1317 if (IntPtr < AllocSize.getValueType())
1318 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1319 else if (IntPtr > AllocSize.getValueType())
1320 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1322 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1323 getIntPtrConstant(TySize));
1325 // Handle alignment. If the requested alignment is less than or equal to the
1326 // stack alignment, ignore it and round the size of the allocation up to the
1327 // stack alignment size. If the size is greater than the stack alignment, we
1328 // note this in the DYNAMIC_STACKALLOC node.
1329 unsigned StackAlign =
1330 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1331 if (Align <= StackAlign) {
1333 // Add SA-1 to the size.
1334 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1335 getIntPtrConstant(StackAlign-1));
1336 // Mask out the low bits for alignment purposes.
1337 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1338 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1341 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
1342 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
1344 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
1345 DAG.setRoot(setValue(&I, DSA).getValue(1));
1347 // Inform the Frame Information that we have just allocated a variable-sized
1349 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1352 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1353 SDOperand Ptr = getValue(I.getOperand(0));
1359 // Do not serialize non-volatile loads against each other.
1360 Root = DAG.getRoot();
1363 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
1364 Root, I.isVolatile()));
1367 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1368 const Value *SV, SDOperand Root,
1371 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1372 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1373 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr,
1374 DAG.getSrcValue(SV));
1376 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, isVolatile);
1380 DAG.setRoot(L.getValue(1));
1382 PendingLoads.push_back(L.getValue(1));
1388 void SelectionDAGLowering::visitStore(StoreInst &I) {
1389 Value *SrcV = I.getOperand(0);
1390 SDOperand Src = getValue(SrcV);
1391 SDOperand Ptr = getValue(I.getOperand(1));
1392 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr,
1393 DAG.getSrcValue(I.getOperand(1))));
1396 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1397 /// access memory and has no other side effects at all.
1398 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1399 #define GET_NO_MEMORY_INTRINSICS
1400 #include "llvm/Intrinsics.gen"
1401 #undef GET_NO_MEMORY_INTRINSICS
1405 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1406 // have any side-effects or if it only reads memory.
1407 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1408 #define GET_SIDE_EFFECT_INFO
1409 #include "llvm/Intrinsics.gen"
1410 #undef GET_SIDE_EFFECT_INFO
1414 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1416 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1417 unsigned Intrinsic) {
1418 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1419 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1421 // Build the operand list.
1422 SmallVector<SDOperand, 8> Ops;
1423 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1425 // We don't need to serialize loads against other loads.
1426 Ops.push_back(DAG.getRoot());
1428 Ops.push_back(getRoot());
1432 // Add the intrinsic ID as an integer operand.
1433 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1435 // Add all operands of the call to the operand list.
1436 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1437 SDOperand Op = getValue(I.getOperand(i));
1439 // If this is a vector type, force it to the right packed type.
1440 if (Op.getValueType() == MVT::Vector) {
1441 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1442 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1444 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1445 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1446 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1449 assert(TLI.isTypeLegal(Op.getValueType()) &&
1450 "Intrinsic uses a non-legal type?");
1454 std::vector<MVT::ValueType> VTs;
1455 if (I.getType() != Type::VoidTy) {
1456 MVT::ValueType VT = TLI.getValueType(I.getType());
1457 if (VT == MVT::Vector) {
1458 const PackedType *DestTy = cast<PackedType>(I.getType());
1459 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1461 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1462 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1465 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1469 VTs.push_back(MVT::Other);
1471 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
1476 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
1477 &Ops[0], Ops.size());
1478 else if (I.getType() != Type::VoidTy)
1479 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
1480 &Ops[0], Ops.size());
1482 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
1483 &Ops[0], Ops.size());
1486 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1488 PendingLoads.push_back(Chain);
1492 if (I.getType() != Type::VoidTy) {
1493 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1494 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1495 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1496 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1497 DAG.getValueType(EVT));
1499 setValue(&I, Result);
1503 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1504 /// we want to emit this as a call to a named external function, return the name
1505 /// otherwise lower it and return null.
1507 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1508 switch (Intrinsic) {
1510 // By default, turn this into a target intrinsic node.
1511 visitTargetIntrinsic(I, Intrinsic);
1513 case Intrinsic::vastart: visitVAStart(I); return 0;
1514 case Intrinsic::vaend: visitVAEnd(I); return 0;
1515 case Intrinsic::vacopy: visitVACopy(I); return 0;
1516 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1517 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1518 case Intrinsic::setjmp:
1519 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1521 case Intrinsic::longjmp:
1522 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1524 case Intrinsic::memcpy_i32:
1525 case Intrinsic::memcpy_i64:
1526 visitMemIntrinsic(I, ISD::MEMCPY);
1528 case Intrinsic::memset_i32:
1529 case Intrinsic::memset_i64:
1530 visitMemIntrinsic(I, ISD::MEMSET);
1532 case Intrinsic::memmove_i32:
1533 case Intrinsic::memmove_i64:
1534 visitMemIntrinsic(I, ISD::MEMMOVE);
1537 case Intrinsic::dbg_stoppoint: {
1538 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1539 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1540 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
1544 Ops[1] = getValue(SPI.getLineValue());
1545 Ops[2] = getValue(SPI.getColumnValue());
1547 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
1548 assert(DD && "Not a debug information descriptor");
1549 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1551 Ops[3] = DAG.getString(CompileUnit->getFileName());
1552 Ops[4] = DAG.getString(CompileUnit->getDirectory());
1554 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
1559 case Intrinsic::dbg_region_start: {
1560 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1561 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1562 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
1563 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
1564 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
1565 DAG.getConstant(LabelID, MVT::i32)));
1570 case Intrinsic::dbg_region_end: {
1571 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1572 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
1573 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
1574 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
1575 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
1576 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
1581 case Intrinsic::dbg_func_start: {
1582 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1583 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
1584 if (DebugInfo && FSI.getSubprogram() &&
1585 DebugInfo->Verify(FSI.getSubprogram())) {
1586 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
1587 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
1588 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
1593 case Intrinsic::dbg_declare: {
1594 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1595 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
1596 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
1597 SDOperand AddressOp = getValue(DI.getAddress());
1598 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
1599 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
1605 case Intrinsic::isunordered_f32:
1606 case Intrinsic::isunordered_f64:
1607 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
1608 getValue(I.getOperand(2)), ISD::SETUO));
1611 case Intrinsic::sqrt_f32:
1612 case Intrinsic::sqrt_f64:
1613 setValue(&I, DAG.getNode(ISD::FSQRT,
1614 getValue(I.getOperand(1)).getValueType(),
1615 getValue(I.getOperand(1))));
1617 case Intrinsic::powi_f32:
1618 case Intrinsic::powi_f64:
1619 setValue(&I, DAG.getNode(ISD::FPOWI,
1620 getValue(I.getOperand(1)).getValueType(),
1621 getValue(I.getOperand(1)),
1622 getValue(I.getOperand(2))));
1624 case Intrinsic::pcmarker: {
1625 SDOperand Tmp = getValue(I.getOperand(1));
1626 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
1629 case Intrinsic::readcyclecounter: {
1630 SDOperand Op = getRoot();
1631 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
1632 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
1635 DAG.setRoot(Tmp.getValue(1));
1638 case Intrinsic::bswap_i16:
1639 case Intrinsic::bswap_i32:
1640 case Intrinsic::bswap_i64:
1641 setValue(&I, DAG.getNode(ISD::BSWAP,
1642 getValue(I.getOperand(1)).getValueType(),
1643 getValue(I.getOperand(1))));
1645 case Intrinsic::cttz_i8:
1646 case Intrinsic::cttz_i16:
1647 case Intrinsic::cttz_i32:
1648 case Intrinsic::cttz_i64:
1649 setValue(&I, DAG.getNode(ISD::CTTZ,
1650 getValue(I.getOperand(1)).getValueType(),
1651 getValue(I.getOperand(1))));
1653 case Intrinsic::ctlz_i8:
1654 case Intrinsic::ctlz_i16:
1655 case Intrinsic::ctlz_i32:
1656 case Intrinsic::ctlz_i64:
1657 setValue(&I, DAG.getNode(ISD::CTLZ,
1658 getValue(I.getOperand(1)).getValueType(),
1659 getValue(I.getOperand(1))));
1661 case Intrinsic::ctpop_i8:
1662 case Intrinsic::ctpop_i16:
1663 case Intrinsic::ctpop_i32:
1664 case Intrinsic::ctpop_i64:
1665 setValue(&I, DAG.getNode(ISD::CTPOP,
1666 getValue(I.getOperand(1)).getValueType(),
1667 getValue(I.getOperand(1))));
1669 case Intrinsic::stacksave: {
1670 SDOperand Op = getRoot();
1671 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
1672 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
1674 DAG.setRoot(Tmp.getValue(1));
1677 case Intrinsic::stackrestore: {
1678 SDOperand Tmp = getValue(I.getOperand(1));
1679 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
1682 case Intrinsic::prefetch:
1683 // FIXME: Currently discarding prefetches.
1689 void SelectionDAGLowering::visitCall(CallInst &I) {
1690 const char *RenameFn = 0;
1691 if (Function *F = I.getCalledFunction()) {
1692 if (F->isExternal())
1693 if (unsigned IID = F->getIntrinsicID()) {
1694 RenameFn = visitIntrinsicCall(I, IID);
1697 } else { // Not an LLVM intrinsic.
1698 const std::string &Name = F->getName();
1699 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
1700 if (I.getNumOperands() == 3 && // Basic sanity checks.
1701 I.getOperand(1)->getType()->isFloatingPoint() &&
1702 I.getType() == I.getOperand(1)->getType() &&
1703 I.getType() == I.getOperand(2)->getType()) {
1704 SDOperand LHS = getValue(I.getOperand(1));
1705 SDOperand RHS = getValue(I.getOperand(2));
1706 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
1710 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
1711 if (I.getNumOperands() == 2 && // Basic sanity checks.
1712 I.getOperand(1)->getType()->isFloatingPoint() &&
1713 I.getType() == I.getOperand(1)->getType()) {
1714 SDOperand Tmp = getValue(I.getOperand(1));
1715 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
1718 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
1719 if (I.getNumOperands() == 2 && // Basic sanity checks.
1720 I.getOperand(1)->getType()->isFloatingPoint() &&
1721 I.getType() == I.getOperand(1)->getType()) {
1722 SDOperand Tmp = getValue(I.getOperand(1));
1723 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
1726 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
1727 if (I.getNumOperands() == 2 && // Basic sanity checks.
1728 I.getOperand(1)->getType()->isFloatingPoint() &&
1729 I.getType() == I.getOperand(1)->getType()) {
1730 SDOperand Tmp = getValue(I.getOperand(1));
1731 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
1736 } else if (isa<InlineAsm>(I.getOperand(0))) {
1743 Callee = getValue(I.getOperand(0));
1745 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
1746 std::vector<std::pair<SDOperand, const Type*> > Args;
1747 Args.reserve(I.getNumOperands());
1748 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1749 Value *Arg = I.getOperand(i);
1750 SDOperand ArgNode = getValue(Arg);
1751 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
1754 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
1755 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1757 std::pair<SDOperand,SDOperand> Result =
1758 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
1759 I.isTailCall(), Callee, Args, DAG);
1760 if (I.getType() != Type::VoidTy)
1761 setValue(&I, Result.first);
1762 DAG.setRoot(Result.second);
1765 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
1766 SDOperand &Chain, SDOperand &Flag)const{
1767 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
1768 Chain = Val.getValue(1);
1769 Flag = Val.getValue(2);
1771 // If the result was expanded, copy from the top part.
1772 if (Regs.size() > 1) {
1773 assert(Regs.size() == 2 &&
1774 "Cannot expand to more than 2 elts yet!");
1775 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
1776 Chain = Hi.getValue(1);
1777 Flag = Hi.getValue(2);
1778 if (DAG.getTargetLoweringInfo().isLittleEndian())
1779 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
1781 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
1784 // Otherwise, if the return value was promoted or extended, truncate it to the
1785 // appropriate type.
1786 if (RegVT == ValueVT)
1789 if (MVT::isInteger(RegVT)) {
1790 if (ValueVT < RegVT)
1791 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1793 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
1795 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
1799 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
1800 /// specified value into the registers specified by this object. This uses
1801 /// Chain/Flag as the input and updates them for the output Chain/Flag.
1802 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
1803 SDOperand &Chain, SDOperand &Flag,
1804 MVT::ValueType PtrVT) const {
1805 if (Regs.size() == 1) {
1806 // If there is a single register and the types differ, this must be
1808 if (RegVT != ValueVT) {
1809 if (MVT::isInteger(RegVT)) {
1810 if (RegVT < ValueVT)
1811 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
1813 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
1815 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
1817 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
1818 Flag = Chain.getValue(1);
1820 std::vector<unsigned> R(Regs);
1821 if (!DAG.getTargetLoweringInfo().isLittleEndian())
1822 std::reverse(R.begin(), R.end());
1824 for (unsigned i = 0, e = R.size(); i != e; ++i) {
1825 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
1826 DAG.getConstant(i, PtrVT));
1827 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
1828 Flag = Chain.getValue(1);
1833 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
1834 /// operand list. This adds the code marker and includes the number of
1835 /// values added into it.
1836 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
1837 std::vector<SDOperand> &Ops) const {
1838 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
1839 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1840 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
1843 /// isAllocatableRegister - If the specified register is safe to allocate,
1844 /// i.e. it isn't a stack pointer or some other special register, return the
1845 /// register class for the register. Otherwise, return null.
1846 static const TargetRegisterClass *
1847 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
1848 const TargetLowering &TLI, const MRegisterInfo *MRI) {
1849 MVT::ValueType FoundVT = MVT::Other;
1850 const TargetRegisterClass *FoundRC = 0;
1851 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
1852 E = MRI->regclass_end(); RCI != E; ++RCI) {
1853 MVT::ValueType ThisVT = MVT::Other;
1855 const TargetRegisterClass *RC = *RCI;
1856 // If none of the the value types for this register class are valid, we
1857 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1858 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1860 if (TLI.isTypeLegal(*I)) {
1861 // If we have already found this register in a different register class,
1862 // choose the one with the largest VT specified. For example, on
1863 // PowerPC, we favor f64 register classes over f32.
1864 if (FoundVT == MVT::Other ||
1865 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
1872 if (ThisVT == MVT::Other) continue;
1874 // NOTE: This isn't ideal. In particular, this might allocate the
1875 // frame pointer in functions that need it (due to them not being taken
1876 // out of allocation, because a variable sized allocation hasn't been seen
1877 // yet). This is a slight code pessimization, but should still work.
1878 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
1879 E = RC->allocation_order_end(MF); I != E; ++I)
1881 // We found a matching register class. Keep looking at others in case
1882 // we find one with larger registers that this physreg is also in.
1891 RegsForValue SelectionDAGLowering::
1892 GetRegistersForValue(const std::string &ConstrCode,
1893 MVT::ValueType VT, bool isOutReg, bool isInReg,
1894 std::set<unsigned> &OutputRegs,
1895 std::set<unsigned> &InputRegs) {
1896 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
1897 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
1898 std::vector<unsigned> Regs;
1900 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
1901 MVT::ValueType RegVT;
1902 MVT::ValueType ValueVT = VT;
1904 if (PhysReg.first) {
1905 if (VT == MVT::Other)
1906 ValueVT = *PhysReg.second->vt_begin();
1908 // Get the actual register value type. This is important, because the user
1909 // may have asked for (e.g.) the AX register in i32 type. We need to
1910 // remember that AX is actually i16 to get the right extension.
1911 RegVT = *PhysReg.second->vt_begin();
1913 // This is a explicit reference to a physical register.
1914 Regs.push_back(PhysReg.first);
1916 // If this is an expanded reference, add the rest of the regs to Regs.
1918 TargetRegisterClass::iterator I = PhysReg.second->begin();
1919 TargetRegisterClass::iterator E = PhysReg.second->end();
1920 for (; *I != PhysReg.first; ++I)
1921 assert(I != E && "Didn't find reg!");
1923 // Already added the first reg.
1925 for (; NumRegs; --NumRegs, ++I) {
1926 assert(I != E && "Ran out of registers to allocate!");
1930 return RegsForValue(Regs, RegVT, ValueVT);
1933 // This is a reference to a register class. Allocate NumRegs consecutive,
1934 // available, registers from the class.
1935 std::vector<unsigned> RegClassRegs =
1936 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
1938 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
1939 MachineFunction &MF = *CurMBB->getParent();
1940 unsigned NumAllocated = 0;
1941 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
1942 unsigned Reg = RegClassRegs[i];
1943 // See if this register is available.
1944 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
1945 (isInReg && InputRegs.count(Reg))) { // Already used.
1946 // Make sure we find consecutive registers.
1951 // Check to see if this register is allocatable (i.e. don't give out the
1953 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
1955 // Make sure we find consecutive registers.
1960 // Okay, this register is good, we can use it.
1963 // If we allocated enough consecutive
1964 if (NumAllocated == NumRegs) {
1965 unsigned RegStart = (i-NumAllocated)+1;
1966 unsigned RegEnd = i+1;
1967 // Mark all of the allocated registers used.
1968 for (unsigned i = RegStart; i != RegEnd; ++i) {
1969 unsigned Reg = RegClassRegs[i];
1970 Regs.push_back(Reg);
1971 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
1972 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
1975 return RegsForValue(Regs, *RC->vt_begin(), VT);
1979 // Otherwise, we couldn't allocate enough registers for this.
1980 return RegsForValue();
1984 /// visitInlineAsm - Handle a call to an InlineAsm object.
1986 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
1987 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
1989 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
1992 // Note, we treat inline asms both with and without side-effects as the same.
1993 // If an inline asm doesn't have side effects and doesn't access memory, we
1994 // could not choose to not chain it.
1995 bool hasSideEffects = IA->hasSideEffects();
1997 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
1998 std::vector<MVT::ValueType> ConstraintVTs;
2000 /// AsmNodeOperands - A list of pairs. The first element is a register, the
2001 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
2002 /// if it is a def of that register.
2003 std::vector<SDOperand> AsmNodeOperands;
2004 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
2005 AsmNodeOperands.push_back(AsmStr);
2007 SDOperand Chain = getRoot();
2010 // We fully assign registers here at isel time. This is not optimal, but
2011 // should work. For register classes that correspond to LLVM classes, we
2012 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
2013 // over the constraints, collecting fixed registers that we know we can't use.
2014 std::set<unsigned> OutputRegs, InputRegs;
2016 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2017 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2018 std::string &ConstraintCode = Constraints[i].Codes[0];
2020 MVT::ValueType OpVT;
2022 // Compute the value type for each operand and add it to ConstraintVTs.
2023 switch (Constraints[i].Type) {
2024 case InlineAsm::isOutput:
2025 if (!Constraints[i].isIndirectOutput) {
2026 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2027 OpVT = TLI.getValueType(I.getType());
2029 const Type *OpTy = I.getOperand(OpNum)->getType();
2030 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2031 OpNum++; // Consumes a call operand.
2034 case InlineAsm::isInput:
2035 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2036 OpNum++; // Consumes a call operand.
2038 case InlineAsm::isClobber:
2043 ConstraintVTs.push_back(OpVT);
2045 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2046 continue; // Not assigned a fixed reg.
2048 // Build a list of regs that this operand uses. This always has a single
2049 // element for promoted/expanded operands.
2050 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2052 OutputRegs, InputRegs);
2054 switch (Constraints[i].Type) {
2055 case InlineAsm::isOutput:
2056 // We can't assign any other output to this register.
2057 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2058 // If this is an early-clobber output, it cannot be assigned to the same
2059 // value as the input reg.
2060 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2061 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2063 case InlineAsm::isInput:
2064 // We can't assign any other input to this register.
2065 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2067 case InlineAsm::isClobber:
2068 // Clobbered regs cannot be used as inputs or outputs.
2069 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2070 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2075 // Loop over all of the inputs, copying the operand values into the
2076 // appropriate registers and processing the output regs.
2077 RegsForValue RetValRegs;
2078 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2081 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2082 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2083 std::string &ConstraintCode = Constraints[i].Codes[0];
2085 switch (Constraints[i].Type) {
2086 case InlineAsm::isOutput: {
2087 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2088 if (ConstraintCode.size() == 1) // not a physreg name.
2089 CTy = TLI.getConstraintType(ConstraintCode[0]);
2091 if (CTy == TargetLowering::C_Memory) {
2093 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2095 // Check that the operand (the address to store to) isn't a float.
2096 if (!MVT::isInteger(InOperandVal.getValueType()))
2097 assert(0 && "MATCH FAIL!");
2099 if (!Constraints[i].isIndirectOutput)
2100 assert(0 && "MATCH FAIL!");
2102 OpNum++; // Consumes a call operand.
2104 // Extend/truncate to the right pointer type if needed.
2105 MVT::ValueType PtrType = TLI.getPointerTy();
2106 if (InOperandVal.getValueType() < PtrType)
2107 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2108 else if (InOperandVal.getValueType() > PtrType)
2109 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2111 // Add information to the INLINEASM node to know about this output.
2112 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2113 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2114 AsmNodeOperands.push_back(InOperandVal);
2118 // Otherwise, this is a register output.
2119 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2121 // If this is an early-clobber output, or if there is an input
2122 // constraint that matches this, we need to reserve the input register
2123 // so no other inputs allocate to it.
2124 bool UsesInputRegister = false;
2125 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2126 UsesInputRegister = true;
2128 // Copy the output from the appropriate register. Find a register that
2131 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2132 true, UsesInputRegister,
2133 OutputRegs, InputRegs);
2134 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
2136 if (!Constraints[i].isIndirectOutput) {
2137 assert(RetValRegs.Regs.empty() &&
2138 "Cannot have multiple output constraints yet!");
2139 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2142 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2143 I.getOperand(OpNum)));
2144 OpNum++; // Consumes a call operand.
2147 // Add information to the INLINEASM node to know that this register is
2149 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2152 case InlineAsm::isInput: {
2153 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2154 OpNum++; // Consumes a call operand.
2156 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2157 // If this is required to match an output register we have already set,
2158 // just use its register.
2159 unsigned OperandNo = atoi(ConstraintCode.c_str());
2161 // Scan until we find the definition we already emitted of this operand.
2162 // When we find it, create a RegsForValue operand.
2163 unsigned CurOp = 2; // The first operand.
2164 for (; OperandNo; --OperandNo) {
2165 // Advance to the next operand.
2167 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2168 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
2169 (NumOps & 7) == 4 /*MEM*/) &&
2170 "Skipped past definitions?");
2171 CurOp += (NumOps>>3)+1;
2175 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2176 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2177 "Skipped past definitions?");
2179 // Add NumOps>>3 registers to MatchedRegs.
2180 RegsForValue MatchedRegs;
2181 MatchedRegs.ValueVT = InOperandVal.getValueType();
2182 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2183 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2184 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2185 MatchedRegs.Regs.push_back(Reg);
2188 // Use the produced MatchedRegs object to
2189 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag,
2190 TLI.getPointerTy());
2191 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2195 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2196 if (ConstraintCode.size() == 1) // not a physreg name.
2197 CTy = TLI.getConstraintType(ConstraintCode[0]);
2199 if (CTy == TargetLowering::C_Other) {
2200 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
2201 assert(0 && "MATCH FAIL!");
2203 // Add information to the INLINEASM node to know about this input.
2204 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2205 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2206 AsmNodeOperands.push_back(InOperandVal);
2208 } else if (CTy == TargetLowering::C_Memory) {
2211 // Check that the operand isn't a float.
2212 if (!MVT::isInteger(InOperandVal.getValueType()))
2213 assert(0 && "MATCH FAIL!");
2215 // Extend/truncate to the right pointer type if needed.
2216 MVT::ValueType PtrType = TLI.getPointerTy();
2217 if (InOperandVal.getValueType() < PtrType)
2218 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2219 else if (InOperandVal.getValueType() > PtrType)
2220 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2222 // Add information to the INLINEASM node to know about this input.
2223 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2224 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2225 AsmNodeOperands.push_back(InOperandVal);
2229 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2231 // Copy the input into the appropriate registers.
2232 RegsForValue InRegs =
2233 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2234 false, true, OutputRegs, InputRegs);
2235 // FIXME: should be match fail.
2236 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2238 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy());
2240 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2243 case InlineAsm::isClobber: {
2244 RegsForValue ClobberedRegs =
2245 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2246 OutputRegs, InputRegs);
2247 // Add the clobbered value to the operand list, so that the register
2248 // allocator is aware that the physreg got clobbered.
2249 if (!ClobberedRegs.Regs.empty())
2250 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2256 // Finish up input operands.
2257 AsmNodeOperands[0] = Chain;
2258 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2260 Chain = DAG.getNode(ISD::INLINEASM,
2261 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
2262 &AsmNodeOperands[0], AsmNodeOperands.size());
2263 Flag = Chain.getValue(1);
2265 // If this asm returns a register value, copy the result from that register
2266 // and set it as the value of the call.
2267 if (!RetValRegs.Regs.empty())
2268 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2270 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2272 // Process indirect outputs, first output all of the flagged copies out of
2274 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2275 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2276 Value *Ptr = IndirectStoresToEmit[i].second;
2277 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2278 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2281 // Emit the non-flagged stores from the physregs.
2282 SmallVector<SDOperand, 8> OutChains;
2283 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2284 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
2285 getValue(StoresToEmit[i].second),
2286 DAG.getSrcValue(StoresToEmit[i].second)));
2287 if (!OutChains.empty())
2288 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2289 &OutChains[0], OutChains.size());
2294 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2295 SDOperand Src = getValue(I.getOperand(0));
2297 MVT::ValueType IntPtr = TLI.getPointerTy();
2299 if (IntPtr < Src.getValueType())
2300 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2301 else if (IntPtr > Src.getValueType())
2302 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2304 // Scale the source by the type size.
2305 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
2306 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2307 Src, getIntPtrConstant(ElementSize));
2309 std::vector<std::pair<SDOperand, const Type*> > Args;
2310 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType()));
2312 std::pair<SDOperand,SDOperand> Result =
2313 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
2314 DAG.getExternalSymbol("malloc", IntPtr),
2316 setValue(&I, Result.first); // Pointers always fit in registers
2317 DAG.setRoot(Result.second);
2320 void SelectionDAGLowering::visitFree(FreeInst &I) {
2321 std::vector<std::pair<SDOperand, const Type*> > Args;
2322 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
2323 TLI.getTargetData()->getIntPtrType()));
2324 MVT::ValueType IntPtr = TLI.getPointerTy();
2325 std::pair<SDOperand,SDOperand> Result =
2326 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
2327 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2328 DAG.setRoot(Result.second);
2331 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2332 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2333 // instructions are special in various ways, which require special support to
2334 // insert. The specified MachineInstr is created but not inserted into any
2335 // basic blocks, and the scheduler passes ownership of it to this method.
2336 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2337 MachineBasicBlock *MBB) {
2338 std::cerr << "If a target marks an instruction with "
2339 "'usesCustomDAGSchedInserter', it must implement "
2340 "TargetLowering::InsertAtEndOfBasicBlock!\n";
2345 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2346 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2347 getValue(I.getOperand(1)),
2348 DAG.getSrcValue(I.getOperand(1))));
2351 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2352 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2353 getValue(I.getOperand(0)),
2354 DAG.getSrcValue(I.getOperand(0)));
2356 DAG.setRoot(V.getValue(1));
2359 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2360 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2361 getValue(I.getOperand(1)),
2362 DAG.getSrcValue(I.getOperand(1))));
2365 void SelectionDAGLowering::visitVACopy(CallInst &I) {
2366 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2367 getValue(I.getOperand(1)),
2368 getValue(I.getOperand(2)),
2369 DAG.getSrcValue(I.getOperand(1)),
2370 DAG.getSrcValue(I.getOperand(2))));
2373 /// TargetLowering::LowerArguments - This is the default LowerArguments
2374 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
2375 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
2376 /// integrated into SDISel.
2377 std::vector<SDOperand>
2378 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2379 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2380 std::vector<SDOperand> Ops;
2381 Ops.push_back(DAG.getRoot());
2382 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2383 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2385 // Add one result value for each formal argument.
2386 std::vector<MVT::ValueType> RetVals;
2387 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2388 MVT::ValueType VT = getValueType(I->getType());
2390 switch (getTypeAction(VT)) {
2391 default: assert(0 && "Unknown type action!");
2393 RetVals.push_back(VT);
2396 RetVals.push_back(getTypeToTransformTo(VT));
2399 if (VT != MVT::Vector) {
2400 // If this is a large integer, it needs to be broken up into small
2401 // integers. Figure out what the destination type is and how many small
2402 // integers it turns into.
2403 MVT::ValueType NVT = getTypeToTransformTo(VT);
2404 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2405 for (unsigned i = 0; i != NumVals; ++i)
2406 RetVals.push_back(NVT);
2408 // Otherwise, this is a vector type. We only support legal vectors
2410 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2411 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2413 // Figure out if there is a Packed type corresponding to this Vector
2414 // type. If so, convert to the packed type.
2415 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2416 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2417 RetVals.push_back(TVT);
2419 assert(0 && "Don't support illegal by-val vector arguments yet!");
2426 RetVals.push_back(MVT::Other);
2429 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
2430 DAG.getNodeValueTypes(RetVals), RetVals.size(),
2431 &Ops[0], Ops.size()).Val;
2433 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
2435 // Set up the return result vector.
2438 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2439 MVT::ValueType VT = getValueType(I->getType());
2441 switch (getTypeAction(VT)) {
2442 default: assert(0 && "Unknown type action!");
2444 Ops.push_back(SDOperand(Result, i++));
2447 SDOperand Op(Result, i++);
2448 if (MVT::isInteger(VT)) {
2449 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
2451 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
2452 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2454 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2455 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2461 if (VT != MVT::Vector) {
2462 // If this is a large integer, it needs to be reassembled from small
2463 // integers. Figure out what the source elt type is and how many small
2465 MVT::ValueType NVT = getTypeToTransformTo(VT);
2466 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2468 SDOperand Lo = SDOperand(Result, i++);
2469 SDOperand Hi = SDOperand(Result, i++);
2471 if (!isLittleEndian())
2474 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
2476 // Value scalarized into many values. Unimp for now.
2477 assert(0 && "Cannot expand i64 -> i16 yet!");
2480 // Otherwise, this is a vector type. We only support legal vectors
2482 const PackedType *PTy = cast<PackedType>(I->getType());
2483 unsigned NumElems = PTy->getNumElements();
2484 const Type *EltTy = PTy->getElementType();
2486 // Figure out if there is a Packed type corresponding to this Vector
2487 // type. If so, convert to the packed type.
2488 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2489 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2490 SDOperand N = SDOperand(Result, i++);
2491 // Handle copies from generic vectors to registers.
2492 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
2493 DAG.getConstant(NumElems, MVT::i32),
2494 DAG.getValueType(getValueType(EltTy)));
2497 assert(0 && "Don't support illegal by-val vector arguments yet!");
2508 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
2509 /// implementation, which just inserts an ISD::CALL node, which is later custom
2510 /// lowered by the target to something concrete. FIXME: When all targets are
2511 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
2512 std::pair<SDOperand, SDOperand>
2513 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
2514 unsigned CallingConv, bool isTailCall,
2516 ArgListTy &Args, SelectionDAG &DAG) {
2517 SmallVector<SDOperand, 32> Ops;
2518 Ops.push_back(Chain); // Op#0 - Chain
2519 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
2520 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
2521 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
2522 Ops.push_back(Callee);
2524 // Handle all of the outgoing arguments.
2525 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
2526 MVT::ValueType VT = getValueType(Args[i].second);
2527 SDOperand Op = Args[i].first;
2528 bool isSigned = Args[i].second->isSigned();
2529 switch (getTypeAction(VT)) {
2530 default: assert(0 && "Unknown type action!");
2533 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2536 if (MVT::isInteger(VT)) {
2537 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2538 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
2540 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2541 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
2544 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2547 if (VT != MVT::Vector) {
2548 // If this is a large integer, it needs to be broken down into small
2549 // integers. Figure out what the source elt type is and how many small
2551 MVT::ValueType NVT = getTypeToTransformTo(VT);
2552 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2554 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2555 DAG.getConstant(0, getPointerTy()));
2556 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2557 DAG.getConstant(1, getPointerTy()));
2558 if (!isLittleEndian())
2562 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2564 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2566 // Value scalarized into many values. Unimp for now.
2567 assert(0 && "Cannot expand i64 -> i16 yet!");
2570 // Otherwise, this is a vector type. We only support legal vectors
2572 const PackedType *PTy = cast<PackedType>(Args[i].second);
2573 unsigned NumElems = PTy->getNumElements();
2574 const Type *EltTy = PTy->getElementType();
2576 // Figure out if there is a Packed type corresponding to this Vector
2577 // type. If so, convert to the packed type.
2578 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2579 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2580 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
2581 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
2583 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2585 assert(0 && "Don't support illegal by-val vector call args yet!");
2593 // Figure out the result value types.
2594 SmallVector<MVT::ValueType, 4> RetTys;
2596 if (RetTy != Type::VoidTy) {
2597 MVT::ValueType VT = getValueType(RetTy);
2598 switch (getTypeAction(VT)) {
2599 default: assert(0 && "Unknown type action!");
2601 RetTys.push_back(VT);
2604 RetTys.push_back(getTypeToTransformTo(VT));
2607 if (VT != MVT::Vector) {
2608 // If this is a large integer, it needs to be reassembled from small
2609 // integers. Figure out what the source elt type is and how many small
2611 MVT::ValueType NVT = getTypeToTransformTo(VT);
2612 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2613 for (unsigned i = 0; i != NumVals; ++i)
2614 RetTys.push_back(NVT);
2616 // Otherwise, this is a vector type. We only support legal vectors
2618 const PackedType *PTy = cast<PackedType>(RetTy);
2619 unsigned NumElems = PTy->getNumElements();
2620 const Type *EltTy = PTy->getElementType();
2622 // Figure out if there is a Packed type corresponding to this Vector
2623 // type. If so, convert to the packed type.
2624 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2625 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2626 RetTys.push_back(TVT);
2628 assert(0 && "Don't support illegal by-val vector call results yet!");
2635 RetTys.push_back(MVT::Other); // Always has a chain.
2637 // Finally, create the CALL node.
2638 SDOperand Res = DAG.getNode(ISD::CALL,
2639 DAG.getVTList(&RetTys[0], RetTys.size()),
2640 &Ops[0], Ops.size());
2642 // This returns a pair of operands. The first element is the
2643 // return value for the function (if RetTy is not VoidTy). The second
2644 // element is the outgoing token chain.
2646 if (RetTys.size() != 1) {
2647 MVT::ValueType VT = getValueType(RetTy);
2648 if (RetTys.size() == 2) {
2651 // If this value was promoted, truncate it down.
2652 if (ResVal.getValueType() != VT) {
2653 if (VT == MVT::Vector) {
2654 // Insert a VBITCONVERT to convert from the packed result type to the
2655 // MVT::Vector type.
2656 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
2657 const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
2659 // Figure out if there is a Packed type corresponding to this Vector
2660 // type. If so, convert to the packed type.
2661 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2662 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2663 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
2664 // "N x PTyElementVT" MVT::Vector type.
2665 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
2666 DAG.getConstant(NumElems, MVT::i32),
2667 DAG.getValueType(getValueType(EltTy)));
2671 } else if (MVT::isInteger(VT)) {
2672 unsigned AssertOp = RetTy->isSigned() ?
2673 ISD::AssertSext : ISD::AssertZext;
2674 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
2675 DAG.getValueType(VT));
2676 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
2678 assert(MVT::isFloatingPoint(VT));
2679 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
2682 } else if (RetTys.size() == 3) {
2683 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
2684 Res.getValue(0), Res.getValue(1));
2687 assert(0 && "Case not handled yet!");
2691 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
2696 // It is always conservatively correct for llvm.returnaddress and
2697 // llvm.frameaddress to return 0.
2699 // FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
2700 // expanded to 0 if the target wants.
2701 std::pair<SDOperand, SDOperand>
2702 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
2703 unsigned Depth, SelectionDAG &DAG) {
2704 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
2707 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2708 assert(0 && "LowerOperation not implemented for this target!");
2713 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
2714 SelectionDAG &DAG) {
2715 assert(0 && "CustomPromoteOperation not implemented for this target!");
2720 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
2721 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
2722 std::pair<SDOperand,SDOperand> Result =
2723 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
2724 setValue(&I, Result.first);
2725 DAG.setRoot(Result.second);
2728 /// getMemsetValue - Vectorized representation of the memset value
2730 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
2731 SelectionDAG &DAG) {
2732 MVT::ValueType CurVT = VT;
2733 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2734 uint64_t Val = C->getValue() & 255;
2736 while (CurVT != MVT::i8) {
2737 Val = (Val << Shift) | Val;
2739 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2741 return DAG.getConstant(Val, VT);
2743 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
2745 while (CurVT != MVT::i8) {
2747 DAG.getNode(ISD::OR, VT,
2748 DAG.getNode(ISD::SHL, VT, Value,
2749 DAG.getConstant(Shift, MVT::i8)), Value);
2751 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2758 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2759 /// used when a memcpy is turned into a memset when the source is a constant
2761 static SDOperand getMemsetStringVal(MVT::ValueType VT,
2762 SelectionDAG &DAG, TargetLowering &TLI,
2763 std::string &Str, unsigned Offset) {
2764 MVT::ValueType CurVT = VT;
2766 unsigned MSB = getSizeInBits(VT) / 8;
2767 if (TLI.isLittleEndian())
2768 Offset = Offset + MSB - 1;
2769 for (unsigned i = 0; i != MSB; ++i) {
2770 Val = (Val << 8) | Str[Offset];
2771 Offset += TLI.isLittleEndian() ? -1 : 1;
2773 return DAG.getConstant(Val, VT);
2776 /// getMemBasePlusOffset - Returns base and offset node for the
2777 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
2778 SelectionDAG &DAG, TargetLowering &TLI) {
2779 MVT::ValueType VT = Base.getValueType();
2780 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
2783 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
2784 /// to replace the memset / memcpy is below the threshold. It also returns the
2785 /// types of the sequence of memory ops to perform memset / memcpy.
2786 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
2787 unsigned Limit, uint64_t Size,
2788 unsigned Align, TargetLowering &TLI) {
2791 if (TLI.allowsUnalignedMemoryAccesses()) {
2794 switch (Align & 7) {
2810 MVT::ValueType LVT = MVT::i64;
2811 while (!TLI.isTypeLegal(LVT))
2812 LVT = (MVT::ValueType)((unsigned)LVT - 1);
2813 assert(MVT::isInteger(LVT));
2818 unsigned NumMemOps = 0;
2820 unsigned VTSize = getSizeInBits(VT) / 8;
2821 while (VTSize > Size) {
2822 VT = (MVT::ValueType)((unsigned)VT - 1);
2825 assert(MVT::isInteger(VT));
2827 if (++NumMemOps > Limit)
2829 MemOps.push_back(VT);
2836 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
2837 SDOperand Op1 = getValue(I.getOperand(1));
2838 SDOperand Op2 = getValue(I.getOperand(2));
2839 SDOperand Op3 = getValue(I.getOperand(3));
2840 SDOperand Op4 = getValue(I.getOperand(4));
2841 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
2842 if (Align == 0) Align = 1;
2844 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
2845 std::vector<MVT::ValueType> MemOps;
2847 // Expand memset / memcpy to a series of load / store ops
2848 // if the size operand falls below a certain threshold.
2849 SmallVector<SDOperand, 8> OutChains;
2851 default: break; // Do nothing for now.
2853 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
2854 Size->getValue(), Align, TLI)) {
2855 unsigned NumMemOps = MemOps.size();
2856 unsigned Offset = 0;
2857 for (unsigned i = 0; i < NumMemOps; i++) {
2858 MVT::ValueType VT = MemOps[i];
2859 unsigned VTSize = getSizeInBits(VT) / 8;
2860 SDOperand Value = getMemsetValue(Op2, VT, DAG);
2861 SDOperand Store = DAG.getStore(getRoot(), Value,
2862 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
2863 DAG.getSrcValue(I.getOperand(1), Offset));
2864 OutChains.push_back(Store);
2871 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
2872 Size->getValue(), Align, TLI)) {
2873 unsigned NumMemOps = MemOps.size();
2874 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
2875 GlobalAddressSDNode *G = NULL;
2877 bool CopyFromStr = false;
2879 if (Op2.getOpcode() == ISD::GlobalAddress)
2880 G = cast<GlobalAddressSDNode>(Op2);
2881 else if (Op2.getOpcode() == ISD::ADD &&
2882 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
2883 Op2.getOperand(1).getOpcode() == ISD::Constant) {
2884 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
2885 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
2888 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
2890 Str = GV->getStringValue(false);
2898 for (unsigned i = 0; i < NumMemOps; i++) {
2899 MVT::ValueType VT = MemOps[i];
2900 unsigned VTSize = getSizeInBits(VT) / 8;
2901 SDOperand Value, Chain, Store;
2904 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
2907 DAG.getStore(Chain, Value,
2908 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2909 DAG.getSrcValue(I.getOperand(1), DstOff));
2911 Value = DAG.getLoad(VT, getRoot(),
2912 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
2913 I.getOperand(2), SrcOff);
2914 Chain = Value.getValue(1);
2916 DAG.getStore(Chain, Value,
2917 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2918 DAG.getSrcValue(I.getOperand(1), DstOff));
2920 OutChains.push_back(Store);
2929 if (!OutChains.empty()) {
2930 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
2931 &OutChains[0], OutChains.size()));
2936 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
2939 //===----------------------------------------------------------------------===//
2940 // SelectionDAGISel code
2941 //===----------------------------------------------------------------------===//
2943 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
2944 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
2947 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
2948 // FIXME: we only modify the CFG to split critical edges. This
2949 // updates dom and loop info.
2953 /// OptimizeNoopCopyExpression - We have determined that the specified cast
2954 /// instruction is a noop copy (e.g. it's casting from one pointer type to
2955 /// another, int->uint, or int->sbyte on PPC.
2957 /// Return true if any changes are made.
2958 static bool OptimizeNoopCopyExpression(CastInst *CI) {
2959 BasicBlock *DefBB = CI->getParent();
2961 /// InsertedCasts - Only insert a cast in each block once.
2962 std::map<BasicBlock*, CastInst*> InsertedCasts;
2964 bool MadeChange = false;
2965 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
2967 Use &TheUse = UI.getUse();
2968 Instruction *User = cast<Instruction>(*UI);
2970 // Figure out which BB this cast is used in. For PHI's this is the
2971 // appropriate predecessor block.
2972 BasicBlock *UserBB = User->getParent();
2973 if (PHINode *PN = dyn_cast<PHINode>(User)) {
2974 unsigned OpVal = UI.getOperandNo()/2;
2975 UserBB = PN->getIncomingBlock(OpVal);
2978 // Preincrement use iterator so we don't invalidate it.
2981 // If this user is in the same block as the cast, don't change the cast.
2982 if (UserBB == DefBB) continue;
2984 // If we have already inserted a cast into this block, use it.
2985 CastInst *&InsertedCast = InsertedCasts[UserBB];
2987 if (!InsertedCast) {
2988 BasicBlock::iterator InsertPt = UserBB->begin();
2989 while (isa<PHINode>(InsertPt)) ++InsertPt;
2992 new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
2996 // Replace a use of the cast with a use of the new casat.
2997 TheUse = InsertedCast;
3000 // If we removed all uses, nuke the cast.
3001 if (CI->use_empty())
3002 CI->eraseFromParent();
3007 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
3008 /// casting to the type of GEPI.
3009 static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
3010 Instruction *GEPI, Value *Ptr,
3012 if (V) return V; // Already computed.
3014 BasicBlock::iterator InsertPt;
3015 if (BB == GEPI->getParent()) {
3016 // If insert into the GEP's block, insert right after the GEP.
3020 // Otherwise, insert at the top of BB, after any PHI nodes
3021 InsertPt = BB->begin();
3022 while (isa<PHINode>(InsertPt)) ++InsertPt;
3025 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3026 // BB so that there is only one value live across basic blocks (the cast
3028 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3029 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3030 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3032 // Add the offset, cast it to the right type.
3033 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
3034 return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
3037 /// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3038 /// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
3039 /// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3040 /// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
3041 /// sink PtrOffset into user blocks where doing so will likely allow us to fold
3042 /// the constant add into a load or store instruction. Additionally, if a user
3043 /// is a pointer-pointer cast, we look through it to find its users.
3044 static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3045 Constant *PtrOffset, BasicBlock *DefBB,
3046 GetElementPtrInst *GEPI,
3047 std::map<BasicBlock*,Instruction*> &InsertedExprs) {
3048 while (!RepPtr->use_empty()) {
3049 Instruction *User = cast<Instruction>(RepPtr->use_back());
3051 // If the user is a Pointer-Pointer cast, recurse.
3052 if (isa<CastInst>(User) && isa<PointerType>(User->getType())) {
3053 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3055 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
3056 // could invalidate an iterator.
3057 User->setOperand(0, UndefValue::get(RepPtr->getType()));
3061 // If this is a load of the pointer, or a store through the pointer, emit
3062 // the increment into the load/store block.
3063 Instruction *NewVal;
3064 if (isa<LoadInst>(User) ||
3065 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3066 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3067 User->getParent(), GEPI,
3070 // If this use is not foldable into the addressing mode, use a version
3071 // emitted in the GEP block.
3072 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3076 if (GEPI->getType() != RepPtr->getType()) {
3077 BasicBlock::iterator IP = NewVal;
3079 NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP);
3081 User->replaceUsesOfWith(RepPtr, NewVal);
3086 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3087 /// selection, we want to be a bit careful about some things. In particular, if
3088 /// we have a GEP instruction that is used in a different block than it is
3089 /// defined, the addressing expression of the GEP cannot be folded into loads or
3090 /// stores that use it. In this case, decompose the GEP and move constant
3091 /// indices into blocks that use it.
3092 static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
3093 const TargetData *TD) {
3094 // If this GEP is only used inside the block it is defined in, there is no
3095 // need to rewrite it.
3096 bool isUsedOutsideDefBB = false;
3097 BasicBlock *DefBB = GEPI->getParent();
3098 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3100 if (cast<Instruction>(*UI)->getParent() != DefBB) {
3101 isUsedOutsideDefBB = true;
3105 if (!isUsedOutsideDefBB) return false;
3107 // If this GEP has no non-zero constant indices, there is nothing we can do,
3109 bool hasConstantIndex = false;
3110 bool hasVariableIndex = false;
3111 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3112 E = GEPI->op_end(); OI != E; ++OI) {
3113 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
3114 if (CI->getRawValue()) {
3115 hasConstantIndex = true;
3119 hasVariableIndex = true;
3123 // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3124 if (!hasConstantIndex && !hasVariableIndex) {
3125 Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(),
3126 GEPI->getName(), GEPI);
3127 GEPI->replaceAllUsesWith(NC);
3128 GEPI->eraseFromParent();
3132 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
3133 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3136 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
3137 // constant offset (which we now know is non-zero) and deal with it later.
3138 uint64_t ConstantOffset = 0;
3139 const Type *UIntPtrTy = TD->getIntPtrType();
3140 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3141 const Type *Ty = GEPI->getOperand(0)->getType();
3143 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3144 E = GEPI->op_end(); OI != E; ++OI) {
3146 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3147 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
3149 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
3150 Ty = StTy->getElementType(Field);
3152 Ty = cast<SequentialType>(Ty)->getElementType();
3154 // Handle constant subscripts.
3155 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3156 if (CI->getRawValue() == 0) continue;
3158 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
3159 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
3161 ConstantOffset+=TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
3165 // Ptr = Ptr + Idx * ElementSize;
3167 // Cast Idx to UIntPtrTy if needed.
3168 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
3170 uint64_t ElementSize = TD->getTypeSize(Ty);
3171 // Mask off bits that should not be set.
3172 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3173 Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize);
3175 // Multiply by the element size and add to the base.
3176 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3177 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3181 // Make sure that the offset fits in uintptr_t.
3182 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3183 Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset);
3185 // Okay, we have now emitted all of the variable index parts to the BB that
3186 // the GEP is defined in. Loop over all of the using instructions, inserting
3187 // an "add Ptr, ConstantOffset" into each block that uses it and update the
3188 // instruction to use the newly computed value, making GEPI dead. When the
3189 // user is a load or store instruction address, we emit the add into the user
3190 // block, otherwise we use a canonical version right next to the gep (these
3191 // won't be foldable as addresses, so we might as well share the computation).
3193 std::map<BasicBlock*,Instruction*> InsertedExprs;
3194 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3196 // Finally, the GEP is dead, remove it.
3197 GEPI->eraseFromParent();
3202 /// SplitCritEdgesForPHIConstants - If this block has any PHI nodes with
3203 /// constant operands, and if any of the edges feeding the PHI node are
3204 /// critical, split them so that the assignments of a constant to a register
3205 /// will not be executed on a path that isn't relevant.
3206 void SelectionDAGISel::SplitCritEdgesForPHIConstants(BasicBlock *BB) {
3208 BasicBlock::iterator BBI = BB->begin();
3209 while ((PN = dyn_cast<PHINode>(BBI++))) {
3210 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
3211 if (isa<Constant>(PN->getIncomingValue(i)))
3212 SplitCriticalEdge(PN->getIncomingBlock(i), BB);
3217 bool SelectionDAGISel::runOnFunction(Function &Fn) {
3218 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3219 RegMap = MF.getSSARegMap();
3220 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
3222 // First, split all critical edges for PHI nodes with incoming values that are
3223 // constants, this way the load of the constant into a vreg will not be placed
3224 // into MBBs that are used some other way.
3226 // In this pass we also look for GEP and cast instructions that are used
3227 // across basic blocks and rewrite them to improve basic-block-at-a-time
3231 bool MadeChange = true;
3232 while (MadeChange) {
3234 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
3235 // If this block has any PHI nodes with constant operands, and if any of the
3236 // edges feeding the PHI node are critical, split them.
3237 if (isa<PHINode>(BB->begin()))
3238 SplitCritEdgesForPHIConstants(BB);
3240 for (BasicBlock::iterator BBI = BB->begin(), E = BB->end(); BBI != E; ) {
3241 Instruction *I = BBI++;
3242 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
3243 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
3244 } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
3245 // If the source of the cast is a constant, then this should have
3246 // already been constant folded. The only reason NOT to constant fold
3247 // it is if something (e.g. LSR) was careful to place the constant
3248 // evaluation in a block other than then one that uses it (e.g. to hoist
3249 // the address of globals out of a loop). If this is the case, we don't
3250 // want to forward-subst the cast.
3251 if (isa<Constant>(CI->getOperand(0)))
3254 // If this is a noop copy, sink it into user blocks to reduce the number
3255 // of virtual registers that must be created and coallesced.
3256 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
3257 MVT::ValueType DstVT = TLI.getValueType(CI->getType());
3259 // This is an fp<->int conversion?
3260 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
3263 // If this is an extension, it will be a zero or sign extension, which
3265 if (SrcVT < DstVT) continue;
3267 // If these values will be promoted, find out what they will be promoted
3268 // to. This helps us consider truncates on PPC as noop copies when they
3270 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
3271 SrcVT = TLI.getTypeToTransformTo(SrcVT);
3272 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
3273 DstVT = TLI.getTypeToTransformTo(DstVT);
3275 // If, after promotion, these are the same types, this is a noop copy.
3277 MadeChange |= OptimizeNoopCopyExpression(CI);
3283 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
3285 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
3286 SelectBasicBlock(I, MF, FuncInfo);
3292 SDOperand SelectionDAGISel::
3293 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
3294 SDOperand Op = SDL.getValue(V);
3295 assert((Op.getOpcode() != ISD::CopyFromReg ||
3296 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
3297 "Copy from a reg to the same reg!");
3299 // If this type is not legal, we must make sure to not create an invalid
3301 MVT::ValueType SrcVT = Op.getValueType();
3302 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
3303 SelectionDAG &DAG = SDL.DAG;
3304 if (SrcVT == DestVT) {
3305 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3306 } else if (SrcVT == MVT::Vector) {
3307 // Handle copies from generic vectors to registers.
3308 MVT::ValueType PTyElementVT, PTyLegalElementVT;
3309 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
3310 PTyElementVT, PTyLegalElementVT);
3312 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
3313 // MVT::Vector type.
3314 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
3315 DAG.getConstant(NE, MVT::i32),
3316 DAG.getValueType(PTyElementVT));
3318 // Loop over all of the elements of the resultant vector,
3319 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
3320 // copying them into output registers.
3321 SmallVector<SDOperand, 8> OutChains;
3322 SDOperand Root = SDL.getRoot();
3323 for (unsigned i = 0; i != NE; ++i) {
3324 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
3325 Op, DAG.getConstant(i, TLI.getPointerTy()));
3326 if (PTyElementVT == PTyLegalElementVT) {
3327 // Elements are legal.
3328 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3329 } else if (PTyLegalElementVT > PTyElementVT) {
3330 // Elements are promoted.
3331 if (MVT::isFloatingPoint(PTyLegalElementVT))
3332 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
3334 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
3335 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3337 // Elements are expanded.
3338 // The src value is expanded into multiple registers.
3339 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3340 Elt, DAG.getConstant(0, TLI.getPointerTy()));
3341 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3342 Elt, DAG.getConstant(1, TLI.getPointerTy()));
3343 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
3344 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
3347 return DAG.getNode(ISD::TokenFactor, MVT::Other,
3348 &OutChains[0], OutChains.size());
3349 } else if (SrcVT < DestVT) {
3350 // The src value is promoted to the register.
3351 if (MVT::isFloatingPoint(SrcVT))
3352 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
3354 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
3355 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3357 // The src value is expanded into multiple registers.
3358 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3359 Op, DAG.getConstant(0, TLI.getPointerTy()));
3360 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3361 Op, DAG.getConstant(1, TLI.getPointerTy()));
3362 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
3363 return DAG.getCopyToReg(Op, Reg+1, Hi);
3367 void SelectionDAGISel::
3368 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
3369 std::vector<SDOperand> &UnorderedChains) {
3370 // If this is the entry block, emit arguments.
3371 Function &F = *BB->getParent();
3372 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
3373 SDOperand OldRoot = SDL.DAG.getRoot();
3374 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
3377 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
3379 if (!AI->use_empty()) {
3380 SDL.setValue(AI, Args[a]);
3382 // If this argument is live outside of the entry block, insert a copy from
3383 // whereever we got it to the vreg that other BB's will reference it as.
3384 if (FuncInfo.ValueMap.count(AI)) {
3386 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
3387 UnorderedChains.push_back(Copy);
3391 // Finally, if the target has anything special to do, allow it to do so.
3392 // FIXME: this should insert code into the DAG!
3393 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
3396 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3397 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
3398 FunctionLoweringInfo &FuncInfo) {
3399 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
3401 std::vector<SDOperand> UnorderedChains;
3403 // Lower any arguments needed in this block if this is the entry block.
3404 if (LLVMBB == &LLVMBB->getParent()->front())
3405 LowerArguments(LLVMBB, SDL, UnorderedChains);
3407 BB = FuncInfo.MBBMap[LLVMBB];
3408 SDL.setCurrentBasicBlock(BB);
3410 // Lower all of the non-terminator instructions.
3411 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3415 // Ensure that all instructions which are used outside of their defining
3416 // blocks are available as virtual registers.
3417 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
3418 if (!I->use_empty() && !isa<PHINode>(I)) {
3419 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
3420 if (VMI != FuncInfo.ValueMap.end())
3421 UnorderedChains.push_back(
3422 CopyValueToVirtualRegister(SDL, I, VMI->second));
3425 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
3426 // ensure constants are generated when needed. Remember the virtual registers
3427 // that need to be added to the Machine PHI nodes as input. We cannot just
3428 // directly add them, because expansion might result in multiple MBB's for one
3429 // BB. As such, the start of the BB might correspond to a different MBB than
3433 // Emit constants only once even if used by multiple PHI nodes.
3434 std::map<Constant*, unsigned> ConstantsOut;
3436 // Check successor nodes PHI nodes that expect a constant to be available from
3438 TerminatorInst *TI = LLVMBB->getTerminator();
3439 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
3440 BasicBlock *SuccBB = TI->getSuccessor(succ);
3441 if (!isa<PHINode>(SuccBB->begin())) continue;
3443 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
3446 // At this point we know that there is a 1-1 correspondence between LLVM PHI
3447 // nodes and Machine PHI nodes, but the incoming operands have not been
3449 for (BasicBlock::iterator I = SuccBB->begin();
3450 (PN = dyn_cast<PHINode>(I)); ++I)
3451 if (!PN->use_empty()) {
3453 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
3454 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
3455 unsigned &RegOut = ConstantsOut[C];
3457 RegOut = FuncInfo.CreateRegForValue(C);
3458 UnorderedChains.push_back(
3459 CopyValueToVirtualRegister(SDL, C, RegOut));
3463 Reg = FuncInfo.ValueMap[PHIOp];
3465 assert(isa<AllocaInst>(PHIOp) &&
3466 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
3467 "Didn't codegen value into a register!??");
3468 Reg = FuncInfo.CreateRegForValue(PHIOp);
3469 UnorderedChains.push_back(
3470 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
3474 // Remember that this register needs to added to the machine PHI node as
3475 // the input for this MBB.
3476 MVT::ValueType VT = TLI.getValueType(PN->getType());
3477 unsigned NumElements;
3478 if (VT != MVT::Vector)
3479 NumElements = TLI.getNumElements(VT);
3481 MVT::ValueType VT1,VT2;
3483 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
3486 for (unsigned i = 0, e = NumElements; i != e; ++i)
3487 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
3490 ConstantsOut.clear();
3492 // Turn all of the unordered chains into one factored node.
3493 if (!UnorderedChains.empty()) {
3494 SDOperand Root = SDL.getRoot();
3495 if (Root.getOpcode() != ISD::EntryToken) {
3496 unsigned i = 0, e = UnorderedChains.size();
3497 for (; i != e; ++i) {
3498 assert(UnorderedChains[i].Val->getNumOperands() > 1);
3499 if (UnorderedChains[i].Val->getOperand(0) == Root)
3500 break; // Don't add the root if we already indirectly depend on it.
3504 UnorderedChains.push_back(Root);
3506 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
3507 &UnorderedChains[0], UnorderedChains.size()));
3510 // Lower the terminator after the copies are emitted.
3511 SDL.visit(*LLVMBB->getTerminator());
3513 // Copy over any CaseBlock records that may now exist due to SwitchInst
3514 // lowering, as well as any jump table information.
3515 SwitchCases.clear();
3516 SwitchCases = SDL.SwitchCases;
3519 // Make sure the root of the DAG is up-to-date.
3520 DAG.setRoot(SDL.getRoot());
3523 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
3524 // Run the DAG combiner in pre-legalize mode.
3527 DEBUG(std::cerr << "Lowered selection DAG:\n");
3530 // Second step, hack on the DAG until it only uses operations and types that
3531 // the target supports.
3534 DEBUG(std::cerr << "Legalized selection DAG:\n");
3537 // Run the DAG combiner in post-legalize mode.
3540 if (ViewISelDAGs) DAG.viewGraph();
3542 // Third, instruction select all of the operations to machine code, adding the
3543 // code to the MachineBasicBlock.
3544 InstructionSelectBasicBlock(DAG);
3546 DEBUG(std::cerr << "Selected machine code:\n");
3550 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
3551 FunctionLoweringInfo &FuncInfo) {
3552 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
3554 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3557 // First step, lower LLVM code to some DAG. This DAG may use operations and
3558 // types that are not supported by the target.
3559 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
3561 // Second step, emit the lowered DAG as machine code.
3562 CodeGenAndEmitDAG(DAG);
3565 // Next, now that we know what the last MBB the LLVM BB expanded is, update
3566 // PHI nodes in successors.
3567 if (SwitchCases.empty() && JT.Reg == 0) {
3568 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3569 MachineInstr *PHI = PHINodesToUpdate[i].first;
3570 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3571 "This is not a machine PHI node that we are updating!");
3572 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
3573 PHI->addMachineBasicBlockOperand(BB);
3578 // If the JumpTable record is filled in, then we need to emit a jump table.
3579 // Updating the PHI nodes is tricky in this case, since we need to determine
3580 // whether the PHI is a successor of the range check MBB or the jump table MBB
3582 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
3583 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3585 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3586 MachineBasicBlock *RangeBB = BB;
3587 // Set the current basic block to the mbb we wish to insert the code into
3589 SDL.setCurrentBasicBlock(BB);
3591 SDL.visitJumpTable(JT);
3592 SDAG.setRoot(SDL.getRoot());
3593 CodeGenAndEmitDAG(SDAG);
3595 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3596 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3597 MachineBasicBlock *PHIBB = PHI->getParent();
3598 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3599 "This is not a machine PHI node that we are updating!");
3600 if (PHIBB == JT.Default) {
3601 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
3602 PHI->addMachineBasicBlockOperand(RangeBB);
3604 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
3605 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
3606 PHI->addMachineBasicBlockOperand(BB);
3612 // If we generated any switch lowering information, build and codegen any
3613 // additional DAGs necessary.
3614 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
3615 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3617 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3619 // Set the current basic block to the mbb we wish to insert the code into
3620 BB = SwitchCases[i].ThisBB;
3621 SDL.setCurrentBasicBlock(BB);
3624 SDL.visitSwitchCase(SwitchCases[i]);
3625 SDAG.setRoot(SDL.getRoot());
3626 CodeGenAndEmitDAG(SDAG);
3628 // Handle any PHI nodes in successors of this chunk, as if we were coming
3629 // from the original BB before switch expansion. Note that PHI nodes can
3630 // occur multiple times in PHINodesToUpdate. We have to be very careful to
3631 // handle them the right number of times.
3632 while ((BB = SwitchCases[i].LHSBB)) { // Handle LHS and RHS.
3633 for (MachineBasicBlock::iterator Phi = BB->begin();
3634 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
3635 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
3636 for (unsigned pn = 0; ; ++pn) {
3637 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
3638 if (PHINodesToUpdate[pn].first == Phi) {
3639 Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
3640 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
3646 // Don't process RHS if same block as LHS.
3647 if (BB == SwitchCases[i].RHSBB)
3648 SwitchCases[i].RHSBB = 0;
3650 // If we haven't handled the RHS, do so now. Otherwise, we're done.
3651 SwitchCases[i].LHSBB = SwitchCases[i].RHSBB;
3652 SwitchCases[i].RHSBB = 0;
3654 assert(SwitchCases[i].LHSBB == 0 && SwitchCases[i].RHSBB == 0);
3659 //===----------------------------------------------------------------------===//
3660 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
3661 /// target node in the graph.
3662 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
3663 if (ViewSchedDAGs) DAG.viewGraph();
3665 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
3669 RegisterScheduler::setDefault(Ctor);
3672 ScheduleDAG *SL = Ctor(this, &DAG, BB);
3678 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
3679 return new HazardRecognizer();
3683 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
3684 /// by tblgen. Others should not call it.
3685 void SelectionDAGISel::
3686 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
3687 std::vector<SDOperand> InOps;
3688 std::swap(InOps, Ops);
3690 Ops.push_back(InOps[0]); // input chain.
3691 Ops.push_back(InOps[1]); // input asm string.
3693 unsigned i = 2, e = InOps.size();
3694 if (InOps[e-1].getValueType() == MVT::Flag)
3695 --e; // Don't process a flag operand if it is here.
3698 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
3699 if ((Flags & 7) != 4 /*MEM*/) {
3700 // Just skip over this operand, copying the operands verbatim.
3701 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
3702 i += (Flags >> 3) + 1;
3704 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
3705 // Otherwise, this is a memory operand. Ask the target to select it.
3706 std::vector<SDOperand> SelOps;
3707 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
3708 std::cerr << "Could not match memory address. Inline asm failure!\n";
3712 // Add this to the output node.
3713 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
3714 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
3719 // Add the flag input back if present.
3720 if (e != InOps.size())
3721 Ops.push_back(InOps.back());