1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetIntrinsicInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/ADT/Statistic.h"
53 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
54 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
57 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
58 cl::desc("Enable verbose messages in the \"fast\" "
59 "instruction selector"));
61 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
62 cl::desc("Enable abort calls when \"fast\" instruction fails"));
66 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
67 cl::desc("Pop up a window to show dags before the first "
70 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
71 cl::desc("Pop up a window to show dags before legalize types"));
73 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
74 cl::desc("Pop up a window to show dags before legalize"));
76 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
77 cl::desc("Pop up a window to show dags before the second "
80 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before the post legalize types"
82 " dag combine pass"));
84 ViewISelDAGs("view-isel-dags", cl::Hidden,
85 cl::desc("Pop up a window to show isel dags as they are selected"));
87 ViewSchedDAGs("view-sched-dags", cl::Hidden,
88 cl::desc("Pop up a window to show sched dags as they are processed"));
90 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
91 cl::desc("Pop up a window to show SUnit dags after they are processed"));
93 static const bool ViewDAGCombine1 = false,
94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
95 ViewDAGCombine2 = false,
96 ViewDAGCombineLT = false,
97 ViewISelDAGs = false, ViewSchedDAGs = false,
98 ViewSUnitDAGs = false;
101 //===---------------------------------------------------------------------===//
103 /// RegisterScheduler class - Track the registration of instruction schedulers.
105 //===---------------------------------------------------------------------===//
106 MachinePassRegistry RegisterScheduler::Registry;
108 //===---------------------------------------------------------------------===//
110 /// ISHeuristic command line option for instruction schedulers.
112 //===---------------------------------------------------------------------===//
113 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
114 RegisterPassParser<RegisterScheduler> >
115 ISHeuristic("pre-RA-sched",
116 cl::init(&createDefaultScheduler),
117 cl::desc("Instruction schedulers available (before register"
120 static RegisterScheduler
121 defaultListDAGScheduler("default", "Best scheduler for the target",
122 createDefaultScheduler);
125 //===--------------------------------------------------------------------===//
126 /// createDefaultScheduler - This creates an instruction scheduler appropriate
128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
129 CodeGenOpt::Level OptLevel) {
130 const TargetLowering &TLI = IS->getTargetLowering();
132 if (OptLevel == CodeGenOpt::None)
133 return createFastDAGScheduler(IS, OptLevel);
134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
135 return createTDListDAGScheduler(IS, OptLevel);
136 assert(TLI.getSchedulingPreference() ==
137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
138 return createBURRListDAGScheduler(IS, OptLevel);
142 // EmitInstrWithCustomInserter - This method should be implemented by targets
143 // that mark instructions with the 'usesCustomInserter' flag. These
144 // instructions are special in various ways, which require special support to
145 // insert. The specified MachineInstr is created but not inserted into any
146 // basic blocks, and this method is called to expand it into a sequence of
147 // instructions, potentially also creating new basic blocks and control flow.
148 // When new basic blocks are inserted and the edges from MBB to its successors
149 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
151 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
152 MachineBasicBlock *MBB,
153 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
155 dbgs() << "If a target marks an instruction with "
156 "'usesCustomInserter', it must implement "
157 "TargetLowering::EmitInstrWithCustomInserter!";
163 //===----------------------------------------------------------------------===//
164 // SelectionDAGISel code
165 //===----------------------------------------------------------------------===//
167 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
169 FuncInfo(new FunctionLoweringInfo(TLI)),
170 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
171 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
177 SelectionDAGISel::~SelectionDAGISel() {
183 unsigned SelectionDAGISel::MakeReg(EVT VT) {
184 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
187 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
188 AU.addRequired<AliasAnalysis>();
189 AU.addPreserved<AliasAnalysis>();
190 AU.addRequired<GCModuleInfo>();
191 AU.addPreserved<GCModuleInfo>();
192 MachineFunctionPass::getAnalysisUsage(AU);
195 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
196 Function &Fn = *mf.getFunction();
198 // Do some sanity-checking on the command-line options.
199 assert((!EnableFastISelVerbose || EnableFastISel) &&
200 "-fast-isel-verbose requires -fast-isel");
201 assert((!EnableFastISelAbort || EnableFastISel) &&
202 "-fast-isel-abort requires -fast-isel");
204 // Get alias analysis for load/store combining.
205 AA = &getAnalysis<AliasAnalysis>();
208 const TargetInstrInfo &TII = *TM.getInstrInfo();
209 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
212 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn);
215 RegInfo = &MF->getRegInfo();
216 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
219 FuncInfo->set(Fn, *MF, EnableFastISel);
222 SelectAllBasicBlocks(Fn, *MF, TII);
224 // If the first basic block in the function has live ins that need to be
225 // copied into vregs, emit the copies into the top of the block before
226 // emitting the code for the block.
227 RegInfo->EmitLiveInCopies(MF->begin(), TRI, TII);
229 // Add function live-ins to entry block live-in set.
230 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
231 E = RegInfo->livein_end(); I != E; ++I)
232 MF->begin()->addLiveIn(I->first);
235 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
236 "Not all catch info was assigned to a landing pad!");
244 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
245 /// attached with this instruction.
246 static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB,
247 FastISel *FastIS, MachineFunction *MF) {
248 DebugLoc DL = I->getDebugLoc();
249 if (DL.isUnknown()) return;
251 SDB->setCurDebugLoc(DL);
254 FastIS->setCurDebugLoc(DL);
256 // If the function doesn't have a default debug location yet, set
257 // it. This is kind of a hack.
258 if (MF->getDefaultDebugLoc().isUnknown())
259 MF->setDefaultDebugLoc(DL);
262 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
263 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
264 SDB->setCurDebugLoc(DebugLoc());
266 FastIS->setCurDebugLoc(DebugLoc());
269 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
270 BasicBlock::iterator Begin,
271 BasicBlock::iterator End,
273 SDB->setCurrentBasicBlock(BB);
275 // Lower all of the non-terminator instructions. If a call is emitted
276 // as a tail call, cease emitting nodes for this block.
277 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
278 SetDebugLoc(I, SDB, 0, MF);
280 if (!isa<TerminatorInst>(I)) {
283 // Set the current debug location back to "unknown" so that it doesn't
284 // spuriously apply to subsequent instructions.
285 ResetDebugLoc(SDB, 0);
289 if (!SDB->HasTailCall) {
290 // Ensure that all instructions which are used outside of their defining
291 // blocks are available as virtual registers. Invoke is handled elsewhere.
292 for (BasicBlock::iterator I = Begin; I != End; ++I)
293 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
294 SDB->CopyToExportRegsIfNeeded(I);
296 // Handle PHI nodes in successor blocks.
297 if (End == LLVMBB->end()) {
298 HandlePHINodesInSuccessorBlocks(LLVMBB);
300 // Lower the terminator after the copies are emitted.
301 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF);
302 SDB->visit(*LLVMBB->getTerminator());
303 ResetDebugLoc(SDB, 0);
307 // Make sure the root of the DAG is up-to-date.
308 CurDAG->setRoot(SDB->getControlRoot());
310 // Final step, emit the lowered DAG as machine code.
312 HadTailCall = SDB->HasTailCall;
317 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
318 /// nodes from the worklist.
319 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
320 SmallVector<SDNode*, 128> &Worklist;
321 SmallPtrSet<SDNode*, 128> &InWorklist;
323 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
324 SmallPtrSet<SDNode*, 128> &inwl)
325 : Worklist(wl), InWorklist(inwl) {}
327 void RemoveFromWorklist(SDNode *N) {
328 if (!InWorklist.erase(N)) return;
330 SmallVector<SDNode*, 128>::iterator I =
331 std::find(Worklist.begin(), Worklist.end(), N);
332 assert(I != Worklist.end() && "Not in worklist");
334 *I = Worklist.back();
338 virtual void NodeDeleted(SDNode *N, SDNode *E) {
339 RemoveFromWorklist(N);
342 virtual void NodeUpdated(SDNode *N) {
348 /// TrivialTruncElim - Eliminate some trivial nops that can result from
349 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
350 static bool TrivialTruncElim(SDValue Op,
351 TargetLowering::TargetLoweringOpt &TLO) {
352 SDValue N0 = Op.getOperand(0);
353 EVT VT = Op.getValueType();
354 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
355 N0.getOpcode() == ISD::SIGN_EXTEND ||
356 N0.getOpcode() == ISD::ANY_EXTEND) &&
357 N0.getOperand(0).getValueType() == VT) {
358 return TLO.CombineTo(Op, N0.getOperand(0));
363 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
364 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
365 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
366 void SelectionDAGISel::ShrinkDemandedOps() {
367 SmallVector<SDNode*, 128> Worklist;
368 SmallPtrSet<SDNode*, 128> InWorklist;
370 // Add all the dag nodes to the worklist.
371 Worklist.reserve(CurDAG->allnodes_size());
372 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
373 E = CurDAG->allnodes_end(); I != E; ++I) {
374 Worklist.push_back(I);
375 InWorklist.insert(I);
378 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
379 while (!Worklist.empty()) {
380 SDNode *N = Worklist.pop_back_val();
383 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
384 // Deleting this node may make its operands dead, add them to the worklist
385 // if they aren't already there.
386 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
387 if (InWorklist.insert(N->getOperand(i).getNode()))
388 Worklist.push_back(N->getOperand(i).getNode());
390 CurDAG->DeleteNode(N);
394 // Run ShrinkDemandedOp on scalar binary operations.
395 if (N->getNumValues() != 1 ||
396 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
399 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
400 APInt Demanded = APInt::getAllOnesValue(BitWidth);
401 APInt KnownZero, KnownOne;
402 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
403 KnownZero, KnownOne, TLO) &&
404 (N->getOpcode() != ISD::TRUNCATE ||
405 !TrivialTruncElim(SDValue(N, 0), TLO)))
409 assert(!InWorklist.count(N) && "Already in worklist");
410 Worklist.push_back(N);
411 InWorklist.insert(N);
413 // Replace the old value with the new one.
414 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
415 TLO.Old.getNode()->dump(CurDAG);
416 errs() << "\nWith: ";
417 TLO.New.getNode()->dump(CurDAG);
420 if (InWorklist.insert(TLO.New.getNode()))
421 Worklist.push_back(TLO.New.getNode());
423 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
424 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
426 if (!TLO.Old.getNode()->use_empty()) continue;
428 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
430 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
431 if (OpNode->hasOneUse()) {
432 // Add OpNode to the end of the list to revisit.
433 DeadNodes.RemoveFromWorklist(OpNode);
434 Worklist.push_back(OpNode);
435 InWorklist.insert(OpNode);
439 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
440 CurDAG->DeleteNode(TLO.Old.getNode());
444 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
445 SmallPtrSet<SDNode*, 128> VisitedNodes;
446 SmallVector<SDNode*, 128> Worklist;
448 Worklist.push_back(CurDAG->getRoot().getNode());
455 SDNode *N = Worklist.pop_back_val();
457 // If we've already seen this node, ignore it.
458 if (!VisitedNodes.insert(N))
461 // Otherwise, add all chain operands to the worklist.
462 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
463 if (N->getOperand(i).getValueType() == MVT::Other)
464 Worklist.push_back(N->getOperand(i).getNode());
466 // If this is a CopyToReg with a vreg dest, process it.
467 if (N->getOpcode() != ISD::CopyToReg)
470 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
471 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
474 // Ignore non-scalar or non-integer values.
475 SDValue Src = N->getOperand(2);
476 EVT SrcVT = Src.getValueType();
477 if (!SrcVT.isInteger() || SrcVT.isVector())
480 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
481 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
482 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
484 // Only install this information if it tells us something.
485 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
486 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
487 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
488 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
489 FunctionLoweringInfo::LiveOutInfo &LOI =
490 FuncInfo->LiveOutRegInfo[DestReg];
491 LOI.NumSignBits = NumSignBits;
492 LOI.KnownOne = KnownOne;
493 LOI.KnownZero = KnownZero;
495 } while (!Worklist.empty());
498 void SelectionDAGISel::CodeGenAndEmitDAG() {
499 std::string GroupName;
500 if (TimePassesIsEnabled)
501 GroupName = "Instruction Selection and Scheduling";
502 std::string BlockName;
503 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
504 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
506 BlockName = MF->getFunction()->getNameStr() + ":" +
507 BB->getBasicBlock()->getNameStr();
509 DEBUG(dbgs() << "Initial selection DAG:\n");
510 DEBUG(CurDAG->dump());
512 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
514 // Run the DAG combiner in pre-legalize mode.
515 if (TimePassesIsEnabled) {
516 NamedRegionTimer T("DAG Combining 1", GroupName);
517 CurDAG->Combine(Unrestricted, *AA, OptLevel);
519 CurDAG->Combine(Unrestricted, *AA, OptLevel);
522 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
523 DEBUG(CurDAG->dump());
525 // Second step, hack on the DAG until it only uses operations and types that
526 // the target supports.
527 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
531 if (TimePassesIsEnabled) {
532 NamedRegionTimer T("Type Legalization", GroupName);
533 Changed = CurDAG->LegalizeTypes();
535 Changed = CurDAG->LegalizeTypes();
538 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
539 DEBUG(CurDAG->dump());
542 if (ViewDAGCombineLT)
543 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
545 // Run the DAG combiner in post-type-legalize mode.
546 if (TimePassesIsEnabled) {
547 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
548 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
550 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
553 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
554 DEBUG(CurDAG->dump());
557 if (TimePassesIsEnabled) {
558 NamedRegionTimer T("Vector Legalization", GroupName);
559 Changed = CurDAG->LegalizeVectors();
561 Changed = CurDAG->LegalizeVectors();
565 if (TimePassesIsEnabled) {
566 NamedRegionTimer T("Type Legalization 2", GroupName);
567 CurDAG->LegalizeTypes();
569 CurDAG->LegalizeTypes();
572 if (ViewDAGCombineLT)
573 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
575 // Run the DAG combiner in post-type-legalize mode.
576 if (TimePassesIsEnabled) {
577 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
578 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
580 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
583 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
584 DEBUG(CurDAG->dump());
587 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
589 if (TimePassesIsEnabled) {
590 NamedRegionTimer T("DAG Legalization", GroupName);
591 CurDAG->Legalize(OptLevel);
593 CurDAG->Legalize(OptLevel);
596 DEBUG(dbgs() << "Legalized selection DAG:\n");
597 DEBUG(CurDAG->dump());
599 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
601 // Run the DAG combiner in post-legalize mode.
602 if (TimePassesIsEnabled) {
603 NamedRegionTimer T("DAG Combining 2", GroupName);
604 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
606 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
609 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
610 DEBUG(CurDAG->dump());
612 if (OptLevel != CodeGenOpt::None) {
614 ComputeLiveOutVRegInfo();
617 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
619 // Third, instruction select all of the operations to machine code, adding the
620 // code to the MachineBasicBlock.
621 if (TimePassesIsEnabled) {
622 NamedRegionTimer T("Instruction Selection", GroupName);
623 DoInstructionSelection();
625 DoInstructionSelection();
628 DEBUG(dbgs() << "Selected selection DAG:\n");
629 DEBUG(CurDAG->dump());
631 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
633 // Schedule machine code.
634 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
635 if (TimePassesIsEnabled) {
636 NamedRegionTimer T("Instruction Scheduling", GroupName);
637 Scheduler->Run(CurDAG, BB, BB->end());
639 Scheduler->Run(CurDAG, BB, BB->end());
642 if (ViewSUnitDAGs) Scheduler->viewGraph();
644 // Emit machine code to BB. This can change 'BB' to the last block being
646 if (TimePassesIsEnabled) {
647 NamedRegionTimer T("Instruction Creation", GroupName);
648 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
650 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
653 // Free the scheduler state.
654 if (TimePassesIsEnabled) {
655 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
661 DEBUG(dbgs() << "Selected machine code:\n");
665 void SelectionDAGISel::DoInstructionSelection() {
666 DEBUG(errs() << "===== Instruction selection begins:\n");
670 // Select target instructions for the DAG.
672 // Number all nodes with a topological order and set DAGSize.
673 DAGSize = CurDAG->AssignTopologicalOrder();
675 // Create a dummy node (which is not added to allnodes), that adds
676 // a reference to the root node, preventing it from being deleted,
677 // and tracking any changes of the root.
678 HandleSDNode Dummy(CurDAG->getRoot());
679 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
682 // The AllNodes list is now topological-sorted. Visit the
683 // nodes by starting at the end of the list (the root of the
684 // graph) and preceding back toward the beginning (the entry
686 while (ISelPosition != CurDAG->allnodes_begin()) {
687 SDNode *Node = --ISelPosition;
688 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
689 // but there are currently some corner cases that it misses. Also, this
690 // makes it theoretically possible to disable the DAGCombiner.
691 if (Node->use_empty())
694 SDNode *ResNode = Select(Node);
696 // FIXME: This is pretty gross. 'Select' should be changed to not return
697 // anything at all and this code should be nuked with a tactical strike.
699 // If node should not be replaced, continue with the next one.
700 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
704 ReplaceUses(Node, ResNode);
706 // If after the replacement this node is not used any more,
707 // remove this dead node.
708 if (Node->use_empty()) { // Don't delete EntryToken, etc.
709 ISelUpdater ISU(ISelPosition);
710 CurDAG->RemoveDeadNode(Node, &ISU);
714 CurDAG->setRoot(Dummy.getValue());
716 DEBUG(errs() << "===== Instruction selection ends:\n");
718 PostprocessISelDAG();
722 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
724 const TargetInstrInfo &TII) {
725 // Initialize the Fast-ISel state, if needed.
726 FastISel *FastIS = 0;
728 FastIS = TLI.createFastISel(MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
729 FuncInfo->StaticAllocaMap
731 , FuncInfo->CatchInfoLost
735 // Iterate over all basic blocks in the function.
736 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
737 BasicBlock *LLVMBB = &*I;
738 BB = FuncInfo->MBBMap[LLVMBB];
740 BasicBlock::iterator const Begin = LLVMBB->begin();
741 BasicBlock::iterator const End = LLVMBB->end();
742 BasicBlock::iterator BI = Begin;
744 // Lower any arguments needed in this block if this is the entry block.
745 bool SuppressFastISel = false;
746 if (LLVMBB == &Fn.getEntryBlock()) {
747 LowerArguments(LLVMBB);
749 // If any of the arguments has the byval attribute, forgo
750 // fast-isel in the entry block.
753 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
755 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
756 if (EnableFastISelVerbose || EnableFastISelAbort)
757 dbgs() << "FastISel skips entry block due to byval argument\n";
758 SuppressFastISel = true;
764 if (BB->isLandingPad()) {
765 // Add a label to mark the beginning of the landing pad. Deletion of the
766 // landing pad can thus be detected via the MachineModuleInfo.
767 MCSymbol *Label = MF.getMMI().addLandingPad(BB);
769 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
770 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
772 // Mark exception register as live in.
773 unsigned Reg = TLI.getExceptionAddressRegister();
774 if (Reg) BB->addLiveIn(Reg);
776 // Mark exception selector register as live in.
777 Reg = TLI.getExceptionSelectorRegister();
778 if (Reg) BB->addLiveIn(Reg);
780 // FIXME: Hack around an exception handling flaw (PR1508): the personality
781 // function and list of typeids logically belong to the invoke (or, if you
782 // like, the basic block containing the invoke), and need to be associated
783 // with it in the dwarf exception handling tables. Currently however the
784 // information is provided by an intrinsic (eh.selector) that can be moved
785 // to unexpected places by the optimizers: if the unwind edge is critical,
786 // then breaking it can result in the intrinsics being in the successor of
787 // the landing pad, not the landing pad itself. This results
788 // in exceptions not being caught because no typeids are associated with
789 // the invoke. This may not be the only way things can go wrong, but it
790 // is the only way we try to work around for the moment.
791 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
793 if (Br && Br->isUnconditional()) { // Critical edge?
794 BasicBlock::iterator I, E;
795 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
796 if (isa<EHSelectorInst>(I))
800 // No catch info found - try to extract some from the successor.
801 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF.getMMI(), *FuncInfo);
805 // Before doing SelectionDAG ISel, see if FastISel has been requested.
806 if (FastIS && !SuppressFastISel) {
807 // Emit code for any incoming arguments. This must happen before
808 // beginning FastISel on the entry block.
809 if (LLVMBB == &Fn.getEntryBlock()) {
810 CurDAG->setRoot(SDB->getControlRoot());
814 FastIS->startNewBlock(BB);
815 // Do FastISel on as many instructions as possible.
816 for (; BI != End; ++BI) {
817 // Just before the terminator instruction, insert instructions to
818 // feed PHI nodes in successor blocks.
819 if (isa<TerminatorInst>(BI))
820 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
821 ++NumFastIselFailures;
822 ResetDebugLoc(SDB, FastIS);
823 if (EnableFastISelVerbose || EnableFastISelAbort) {
824 dbgs() << "FastISel miss: ";
827 assert(!EnableFastISelAbort &&
828 "FastISel didn't handle a PHI in a successor");
832 SetDebugLoc(BI, SDB, FastIS, &MF);
834 // Try to select the instruction with FastISel.
835 if (FastIS->SelectInstruction(BI)) {
836 ResetDebugLoc(SDB, FastIS);
840 // Clear out the debug location so that it doesn't carry over to
841 // unrelated instructions.
842 ResetDebugLoc(SDB, FastIS);
844 // Then handle certain instructions as single-LLVM-Instruction blocks.
845 if (isa<CallInst>(BI)) {
846 ++NumFastIselFailures;
847 if (EnableFastISelVerbose || EnableFastISelAbort) {
848 dbgs() << "FastISel missed call: ";
852 if (!BI->getType()->isVoidTy()) {
853 unsigned &R = FuncInfo->ValueMap[BI];
855 R = FuncInfo->CreateRegForValue(BI);
858 bool HadTailCall = false;
859 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
861 // If the call was emitted as a tail call, we're done with the block.
867 // If the instruction was codegen'd with multiple blocks,
868 // inform the FastISel object where to resume inserting.
869 FastIS->setCurrentBlock(BB);
873 // Otherwise, give up on FastISel for the rest of the block.
874 // For now, be a little lenient about non-branch terminators.
875 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
876 ++NumFastIselFailures;
877 if (EnableFastISelVerbose || EnableFastISelAbort) {
878 dbgs() << "FastISel miss: ";
881 if (EnableFastISelAbort)
882 // The "fast" selector couldn't handle something and bailed.
883 // For the purpose of debugging, just abort.
884 llvm_unreachable("FastISel didn't select the entire block");
890 // Run SelectionDAG instruction selection on the remainder of the block
891 // not handled by FastISel. If FastISel is not run, this is the entire
895 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
905 SelectionDAGISel::FinishBasicBlock() {
907 DEBUG(dbgs() << "Target-post-processed machine code:\n");
910 DEBUG(dbgs() << "Total amount of phi nodes to update: "
911 << SDB->PHINodesToUpdate.size() << "\n");
912 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
913 dbgs() << "Node " << i << " : ("
914 << SDB->PHINodesToUpdate[i].first
915 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
917 // Next, now that we know what the last MBB the LLVM BB expanded is, update
918 // PHI nodes in successors.
919 if (SDB->SwitchCases.empty() &&
920 SDB->JTCases.empty() &&
921 SDB->BitTestCases.empty()) {
922 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
923 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
924 assert(PHI->isPHI() &&
925 "This is not a machine PHI node that we are updating!");
926 if (!BB->isSuccessor(PHI->getParent()))
928 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
930 PHI->addOperand(MachineOperand::CreateMBB(BB));
932 SDB->PHINodesToUpdate.clear();
936 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
937 // Lower header first, if it wasn't already lowered
938 if (!SDB->BitTestCases[i].Emitted) {
939 // Set the current basic block to the mbb we wish to insert the code into
940 BB = SDB->BitTestCases[i].Parent;
941 SDB->setCurrentBasicBlock(BB);
943 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
944 CurDAG->setRoot(SDB->getRoot());
949 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
950 // Set the current basic block to the mbb we wish to insert the code into
951 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
952 SDB->setCurrentBasicBlock(BB);
955 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
956 SDB->BitTestCases[i].Reg,
957 SDB->BitTestCases[i].Cases[j]);
959 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
960 SDB->BitTestCases[i].Reg,
961 SDB->BitTestCases[i].Cases[j]);
964 CurDAG->setRoot(SDB->getRoot());
970 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
971 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
972 MachineBasicBlock *PHIBB = PHI->getParent();
973 assert(PHI->isPHI() &&
974 "This is not a machine PHI node that we are updating!");
975 // This is "default" BB. We have two jumps to it. From "header" BB and
976 // from last "case" BB.
977 if (PHIBB == SDB->BitTestCases[i].Default) {
978 PHI->addOperand(MachineOperand::
979 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
980 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
981 PHI->addOperand(MachineOperand::
982 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
983 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
986 // One of "cases" BB.
987 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
989 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
990 if (cBB->isSuccessor(PHIBB)) {
991 PHI->addOperand(MachineOperand::
992 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
993 PHI->addOperand(MachineOperand::CreateMBB(cBB));
998 SDB->BitTestCases.clear();
1000 // If the JumpTable record is filled in, then we need to emit a jump table.
1001 // Updating the PHI nodes is tricky in this case, since we need to determine
1002 // whether the PHI is a successor of the range check MBB or the jump table MBB
1003 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1004 // Lower header first, if it wasn't already lowered
1005 if (!SDB->JTCases[i].first.Emitted) {
1006 // Set the current basic block to the mbb we wish to insert the code into
1007 BB = SDB->JTCases[i].first.HeaderBB;
1008 SDB->setCurrentBasicBlock(BB);
1010 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
1011 CurDAG->setRoot(SDB->getRoot());
1012 CodeGenAndEmitDAG();
1016 // Set the current basic block to the mbb we wish to insert the code into
1017 BB = SDB->JTCases[i].second.MBB;
1018 SDB->setCurrentBasicBlock(BB);
1020 SDB->visitJumpTable(SDB->JTCases[i].second);
1021 CurDAG->setRoot(SDB->getRoot());
1022 CodeGenAndEmitDAG();
1026 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1027 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1028 MachineBasicBlock *PHIBB = PHI->getParent();
1029 assert(PHI->isPHI() &&
1030 "This is not a machine PHI node that we are updating!");
1031 // "default" BB. We can go there only from header BB.
1032 if (PHIBB == SDB->JTCases[i].second.Default) {
1034 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1036 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1038 // JT BB. Just iterate over successors here
1039 if (BB->isSuccessor(PHIBB)) {
1041 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1042 PHI->addOperand(MachineOperand::CreateMBB(BB));
1046 SDB->JTCases.clear();
1048 // If the switch block involved a branch to one of the actual successors, we
1049 // need to update PHI nodes in that block.
1050 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1051 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1052 assert(PHI->isPHI() &&
1053 "This is not a machine PHI node that we are updating!");
1054 if (BB->isSuccessor(PHI->getParent())) {
1055 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1057 PHI->addOperand(MachineOperand::CreateMBB(BB));
1061 // If we generated any switch lowering information, build and codegen any
1062 // additional DAGs necessary.
1063 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1064 // Set the current basic block to the mbb we wish to insert the code into
1065 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1066 SDB->setCurrentBasicBlock(BB);
1069 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1070 CurDAG->setRoot(SDB->getRoot());
1071 CodeGenAndEmitDAG();
1073 // Handle any PHI nodes in successors of this chunk, as if we were coming
1074 // from the original BB before switch expansion. Note that PHI nodes can
1075 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1076 // handle them the right number of times.
1077 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1078 // If new BB's are created during scheduling, the edges may have been
1079 // updated. That is, the edge from ThisBB to BB may have been split and
1080 // BB's predecessor is now another block.
1081 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1082 SDB->EdgeMapping.find(BB);
1083 if (EI != SDB->EdgeMapping.end())
1084 ThisBB = EI->second;
1086 // BB may have been removed from the CFG if a branch was constant folded.
1087 if (ThisBB->isSuccessor(BB)) {
1088 for (MachineBasicBlock::iterator Phi = BB->begin();
1089 Phi != BB->end() && Phi->isPHI();
1091 // This value for this PHI node is recorded in PHINodesToUpdate.
1092 for (unsigned pn = 0; ; ++pn) {
1093 assert(pn != SDB->PHINodesToUpdate.size() &&
1094 "Didn't find PHI entry!");
1095 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1096 Phi->addOperand(MachineOperand::
1097 CreateReg(SDB->PHINodesToUpdate[pn].second,
1099 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1106 // Don't process RHS if same block as LHS.
1107 if (BB == SDB->SwitchCases[i].FalseBB)
1108 SDB->SwitchCases[i].FalseBB = 0;
1110 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1111 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1112 SDB->SwitchCases[i].FalseBB = 0;
1114 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1117 SDB->SwitchCases.clear();
1119 SDB->PHINodesToUpdate.clear();
1123 /// Create the scheduler. If a specific scheduler was specified
1124 /// via the SchedulerRegistry, use it, otherwise select the
1125 /// one preferred by the target.
1127 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1128 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1132 RegisterScheduler::setDefault(Ctor);
1135 return Ctor(this, OptLevel);
1138 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1139 return new ScheduleHazardRecognizer();
1142 //===----------------------------------------------------------------------===//
1143 // Helper functions used by the generated instruction selector.
1144 //===----------------------------------------------------------------------===//
1145 // Calls to these methods are generated by tblgen.
1147 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1148 /// the dag combiner simplified the 255, we still want to match. RHS is the
1149 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1150 /// specified in the .td file (e.g. 255).
1151 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1152 int64_t DesiredMaskS) const {
1153 const APInt &ActualMask = RHS->getAPIntValue();
1154 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1156 // If the actual mask exactly matches, success!
1157 if (ActualMask == DesiredMask)
1160 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1161 if (ActualMask.intersects(~DesiredMask))
1164 // Otherwise, the DAG Combiner may have proven that the value coming in is
1165 // either already zero or is not demanded. Check for known zero input bits.
1166 APInt NeededMask = DesiredMask & ~ActualMask;
1167 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1170 // TODO: check to see if missing bits are just not demanded.
1172 // Otherwise, this pattern doesn't match.
1176 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1177 /// the dag combiner simplified the 255, we still want to match. RHS is the
1178 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1179 /// specified in the .td file (e.g. 255).
1180 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1181 int64_t DesiredMaskS) const {
1182 const APInt &ActualMask = RHS->getAPIntValue();
1183 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1185 // If the actual mask exactly matches, success!
1186 if (ActualMask == DesiredMask)
1189 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1190 if (ActualMask.intersects(~DesiredMask))
1193 // Otherwise, the DAG Combiner may have proven that the value coming in is
1194 // either already zero or is not demanded. Check for known zero input bits.
1195 APInt NeededMask = DesiredMask & ~ActualMask;
1197 APInt KnownZero, KnownOne;
1198 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1200 // If all the missing bits in the or are already known to be set, match!
1201 if ((NeededMask & KnownOne) == NeededMask)
1204 // TODO: check to see if missing bits are just not demanded.
1206 // Otherwise, this pattern doesn't match.
1211 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1212 /// by tblgen. Others should not call it.
1213 void SelectionDAGISel::
1214 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1215 std::vector<SDValue> InOps;
1216 std::swap(InOps, Ops);
1218 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1219 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1220 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1222 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1223 if (InOps[e-1].getValueType() == MVT::Flag)
1224 --e; // Don't process a flag operand if it is here.
1227 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1228 if (!InlineAsm::isMemKind(Flags)) {
1229 // Just skip over this operand, copying the operands verbatim.
1230 Ops.insert(Ops.end(), InOps.begin()+i,
1231 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1232 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1234 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1235 "Memory operand with multiple values?");
1236 // Otherwise, this is a memory operand. Ask the target to select it.
1237 std::vector<SDValue> SelOps;
1238 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1239 report_fatal_error("Could not match memory address. Inline asm"
1242 // Add this to the output node.
1244 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1245 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1246 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1251 // Add the flag input back if present.
1252 if (e != InOps.size())
1253 Ops.push_back(InOps.back());
1256 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1259 static SDNode *findFlagUse(SDNode *N) {
1260 unsigned FlagResNo = N->getNumValues()-1;
1261 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1262 SDUse &Use = I.getUse();
1263 if (Use.getResNo() == FlagResNo)
1264 return Use.getUser();
1269 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1270 /// This function recursively traverses up the operand chain, ignoring
1272 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1273 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1274 bool IgnoreChains) {
1275 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1276 // greater than all of its (recursive) operands. If we scan to a point where
1277 // 'use' is smaller than the node we're scanning for, then we know we will
1280 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1281 // happen because we scan down to newly selected nodes in the case of flag
1283 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1286 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1287 // won't fail if we scan it again.
1288 if (!Visited.insert(Use))
1291 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1292 // Ignore chain uses, they are validated by HandleMergeInputChains.
1293 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1296 SDNode *N = Use->getOperand(i).getNode();
1298 if (Use == ImmedUse || Use == Root)
1299 continue; // We are not looking for immediate use.
1304 // Traverse up the operand chain.
1305 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1311 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1312 /// operand node N of U during instruction selection that starts at Root.
1313 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1314 SDNode *Root) const {
1315 if (OptLevel == CodeGenOpt::None) return false;
1316 return N.hasOneUse();
1319 /// IsLegalToFold - Returns true if the specific operand node N of
1320 /// U can be folded during instruction selection that starts at Root.
1321 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1322 bool IgnoreChains) const {
1323 if (OptLevel == CodeGenOpt::None) return false;
1325 // If Root use can somehow reach N through a path that that doesn't contain
1326 // U then folding N would create a cycle. e.g. In the following
1327 // diagram, Root can reach N through X. If N is folded into into Root, then
1328 // X is both a predecessor and a successor of U.
1339 // * indicates nodes to be folded together.
1341 // If Root produces a flag, then it gets (even more) interesting. Since it
1342 // will be "glued" together with its flag use in the scheduler, we need to
1343 // check if it might reach N.
1362 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1363 // (call it Fold), then X is a predecessor of FU and a successor of
1364 // Fold. But since Fold and FU are flagged together, this will create
1365 // a cycle in the scheduling graph.
1367 // If the node has flags, walk down the graph to the "lowest" node in the
1369 EVT VT = Root->getValueType(Root->getNumValues()-1);
1370 while (VT == MVT::Flag) {
1371 SDNode *FU = findFlagUse(Root);
1375 VT = Root->getValueType(Root->getNumValues()-1);
1377 // If our query node has a flag result with a use, we've walked up it. If
1378 // the user (which has already been selected) has a chain or indirectly uses
1379 // the chain, our WalkChainUsers predicate will not consider it. Because of
1380 // this, we cannot ignore chains in this predicate.
1381 IgnoreChains = false;
1385 SmallPtrSet<SDNode*, 16> Visited;
1386 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1389 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1390 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1391 SelectInlineAsmMemoryOperands(Ops);
1393 std::vector<EVT> VTs;
1394 VTs.push_back(MVT::Other);
1395 VTs.push_back(MVT::Flag);
1396 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1397 VTs, &Ops[0], Ops.size());
1399 return New.getNode();
1402 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1403 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1406 /// GetVBR - decode a vbr encoding whose top bit is set.
1407 ALWAYS_INLINE static uint64_t
1408 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1409 assert(Val >= 128 && "Not a VBR");
1410 Val &= 127; // Remove first vbr bit.
1415 NextBits = MatcherTable[Idx++];
1416 Val |= (NextBits&127) << Shift;
1418 } while (NextBits & 128);
1424 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1425 /// interior flag and chain results to use the new flag and chain results.
1426 void SelectionDAGISel::
1427 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1428 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1430 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1431 bool isMorphNodeTo) {
1432 SmallVector<SDNode*, 4> NowDeadNodes;
1434 ISelUpdater ISU(ISelPosition);
1436 // Now that all the normal results are replaced, we replace the chain and
1437 // flag results if present.
1438 if (!ChainNodesMatched.empty()) {
1439 assert(InputChain.getNode() != 0 &&
1440 "Matched input chains but didn't produce a chain");
1441 // Loop over all of the nodes we matched that produced a chain result.
1442 // Replace all the chain results with the final chain we ended up with.
1443 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1444 SDNode *ChainNode = ChainNodesMatched[i];
1446 // If this node was already deleted, don't look at it.
1447 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1450 // Don't replace the results of the root node if we're doing a
1452 if (ChainNode == NodeToMatch && isMorphNodeTo)
1455 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1456 if (ChainVal.getValueType() == MVT::Flag)
1457 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1458 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1459 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1461 // If the node became dead and we haven't already seen it, delete it.
1462 if (ChainNode->use_empty() &&
1463 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1464 NowDeadNodes.push_back(ChainNode);
1468 // If the result produces a flag, update any flag results in the matched
1469 // pattern with the flag result.
1470 if (InputFlag.getNode() != 0) {
1471 // Handle any interior nodes explicitly marked.
1472 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1473 SDNode *FRN = FlagResultNodesMatched[i];
1475 // If this node was already deleted, don't look at it.
1476 if (FRN->getOpcode() == ISD::DELETED_NODE)
1479 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1480 "Doesn't have a flag result");
1481 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1484 // If the node became dead and we haven't already seen it, delete it.
1485 if (FRN->use_empty() &&
1486 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1487 NowDeadNodes.push_back(FRN);
1491 if (!NowDeadNodes.empty())
1492 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1494 DEBUG(errs() << "ISEL: Match complete!\n");
1500 CR_LeadsToInteriorNode
1503 /// WalkChainUsers - Walk down the users of the specified chained node that is
1504 /// part of the pattern we're matching, looking at all of the users we find.
1505 /// This determines whether something is an interior node, whether we have a
1506 /// non-pattern node in between two pattern nodes (which prevent folding because
1507 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1508 /// between pattern nodes (in which case the TF becomes part of the pattern).
1510 /// The walk we do here is guaranteed to be small because we quickly get down to
1511 /// already selected nodes "below" us.
1513 WalkChainUsers(SDNode *ChainedNode,
1514 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1515 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1516 ChainResult Result = CR_Simple;
1518 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1519 E = ChainedNode->use_end(); UI != E; ++UI) {
1520 // Make sure the use is of the chain, not some other value we produce.
1521 if (UI.getUse().getValueType() != MVT::Other) continue;
1525 // If we see an already-selected machine node, then we've gone beyond the
1526 // pattern that we're selecting down into the already selected chunk of the
1528 if (User->isMachineOpcode() ||
1529 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1532 if (User->getOpcode() == ISD::CopyToReg ||
1533 User->getOpcode() == ISD::CopyFromReg ||
1534 User->getOpcode() == ISD::INLINEASM ||
1535 User->getOpcode() == ISD::EH_LABEL) {
1536 // If their node ID got reset to -1 then they've already been selected.
1537 // Treat them like a MachineOpcode.
1538 if (User->getNodeId() == -1)
1542 // If we have a TokenFactor, we handle it specially.
1543 if (User->getOpcode() != ISD::TokenFactor) {
1544 // If the node isn't a token factor and isn't part of our pattern, then it
1545 // must be a random chained node in between two nodes we're selecting.
1546 // This happens when we have something like:
1551 // Because we structurally match the load/store as a read/modify/write,
1552 // but the call is chained between them. We cannot fold in this case
1553 // because it would induce a cycle in the graph.
1554 if (!std::count(ChainedNodesInPattern.begin(),
1555 ChainedNodesInPattern.end(), User))
1556 return CR_InducesCycle;
1558 // Otherwise we found a node that is part of our pattern. For example in:
1562 // This would happen when we're scanning down from the load and see the
1563 // store as a user. Record that there is a use of ChainedNode that is
1564 // part of the pattern and keep scanning uses.
1565 Result = CR_LeadsToInteriorNode;
1566 InteriorChainedNodes.push_back(User);
1570 // If we found a TokenFactor, there are two cases to consider: first if the
1571 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1572 // uses of the TF are in our pattern) we just want to ignore it. Second,
1573 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1579 // | \ DAG's like cheese
1582 // [TokenFactor] [Op]
1589 // In this case, the TokenFactor becomes part of our match and we rewrite it
1590 // as a new TokenFactor.
1592 // To distinguish these two cases, do a recursive walk down the uses.
1593 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1595 // If the uses of the TokenFactor are just already-selected nodes, ignore
1596 // it, it is "below" our pattern.
1598 case CR_InducesCycle:
1599 // If the uses of the TokenFactor lead to nodes that are not part of our
1600 // pattern that are not selected, folding would turn this into a cycle,
1602 return CR_InducesCycle;
1603 case CR_LeadsToInteriorNode:
1604 break; // Otherwise, keep processing.
1607 // Okay, we know we're in the interesting interior case. The TokenFactor
1608 // is now going to be considered part of the pattern so that we rewrite its
1609 // uses (it may have uses that are not part of the pattern) with the
1610 // ultimate chain result of the generated code. We will also add its chain
1611 // inputs as inputs to the ultimate TokenFactor we create.
1612 Result = CR_LeadsToInteriorNode;
1613 ChainedNodesInPattern.push_back(User);
1614 InteriorChainedNodes.push_back(User);
1621 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1622 /// operation for when the pattern matched at least one node with a chains. The
1623 /// input vector contains a list of all of the chained nodes that we match. We
1624 /// must determine if this is a valid thing to cover (i.e. matching it won't
1625 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1626 /// be used as the input node chain for the generated nodes.
1628 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1629 SelectionDAG *CurDAG) {
1630 // Walk all of the chained nodes we've matched, recursively scanning down the
1631 // users of the chain result. This adds any TokenFactor nodes that are caught
1632 // in between chained nodes to the chained and interior nodes list.
1633 SmallVector<SDNode*, 3> InteriorChainedNodes;
1634 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1635 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1636 InteriorChainedNodes) == CR_InducesCycle)
1637 return SDValue(); // Would induce a cycle.
1640 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1641 // that we are interested in. Form our input TokenFactor node.
1642 SmallVector<SDValue, 3> InputChains;
1643 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1644 // Add the input chain of this node to the InputChains list (which will be
1645 // the operands of the generated TokenFactor) if it's not an interior node.
1646 SDNode *N = ChainNodesMatched[i];
1647 if (N->getOpcode() != ISD::TokenFactor) {
1648 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1651 // Otherwise, add the input chain.
1652 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1653 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1654 InputChains.push_back(InChain);
1658 // If we have a token factor, we want to add all inputs of the token factor
1659 // that are not part of the pattern we're matching.
1660 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1661 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1662 N->getOperand(op).getNode()))
1663 InputChains.push_back(N->getOperand(op));
1668 if (InputChains.size() == 1)
1669 return InputChains[0];
1670 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1671 MVT::Other, &InputChains[0], InputChains.size());
1674 /// MorphNode - Handle morphing a node in place for the selector.
1675 SDNode *SelectionDAGISel::
1676 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1677 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1678 // It is possible we're using MorphNodeTo to replace a node with no
1679 // normal results with one that has a normal result (or we could be
1680 // adding a chain) and the input could have flags and chains as well.
1681 // In this case we need to shift the operands down.
1682 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1683 // than the old isel though.
1684 int OldFlagResultNo = -1, OldChainResultNo = -1;
1686 unsigned NTMNumResults = Node->getNumValues();
1687 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1688 OldFlagResultNo = NTMNumResults-1;
1689 if (NTMNumResults != 1 &&
1690 Node->getValueType(NTMNumResults-2) == MVT::Other)
1691 OldChainResultNo = NTMNumResults-2;
1692 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1693 OldChainResultNo = NTMNumResults-1;
1695 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1696 // that this deletes operands of the old node that become dead.
1697 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1699 // MorphNodeTo can operate in two ways: if an existing node with the
1700 // specified operands exists, it can just return it. Otherwise, it
1701 // updates the node in place to have the requested operands.
1703 // If we updated the node in place, reset the node ID. To the isel,
1704 // this should be just like a newly allocated machine node.
1708 unsigned ResNumResults = Res->getNumValues();
1709 // Move the flag if needed.
1710 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1711 (unsigned)OldFlagResultNo != ResNumResults-1)
1712 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1713 SDValue(Res, ResNumResults-1));
1715 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1718 // Move the chain reference if needed.
1719 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1720 (unsigned)OldChainResultNo != ResNumResults-1)
1721 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1722 SDValue(Res, ResNumResults-1));
1724 // Otherwise, no replacement happened because the node already exists. Replace
1725 // Uses of the old node with the new one.
1727 CurDAG->ReplaceAllUsesWith(Node, Res);
1732 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1733 ALWAYS_INLINE static bool
1734 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1735 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1736 // Accept if it is exactly the same as a previously recorded node.
1737 unsigned RecNo = MatcherTable[MatcherIndex++];
1738 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1739 return N == RecordedNodes[RecNo];
1742 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1743 ALWAYS_INLINE static bool
1744 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1745 SelectionDAGISel &SDISel) {
1746 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1749 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1750 ALWAYS_INLINE static bool
1751 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1752 SelectionDAGISel &SDISel, SDNode *N) {
1753 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1756 ALWAYS_INLINE static bool
1757 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1759 uint16_t Opc = MatcherTable[MatcherIndex++];
1760 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1761 return N->getOpcode() == Opc;
1764 ALWAYS_INLINE static bool
1765 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1766 SDValue N, const TargetLowering &TLI) {
1767 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1768 if (N.getValueType() == VT) return true;
1770 // Handle the case when VT is iPTR.
1771 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1774 ALWAYS_INLINE static bool
1775 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1776 SDValue N, const TargetLowering &TLI,
1778 if (ChildNo >= N.getNumOperands())
1779 return false; // Match fails if out of range child #.
1780 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1784 ALWAYS_INLINE static bool
1785 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1787 return cast<CondCodeSDNode>(N)->get() ==
1788 (ISD::CondCode)MatcherTable[MatcherIndex++];
1791 ALWAYS_INLINE static bool
1792 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1793 SDValue N, const TargetLowering &TLI) {
1794 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1795 if (cast<VTSDNode>(N)->getVT() == VT)
1798 // Handle the case when VT is iPTR.
1799 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1802 ALWAYS_INLINE static bool
1803 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1805 int64_t Val = MatcherTable[MatcherIndex++];
1807 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1809 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1810 return C != 0 && C->getSExtValue() == Val;
1813 ALWAYS_INLINE static bool
1814 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1815 SDValue N, SelectionDAGISel &SDISel) {
1816 int64_t Val = MatcherTable[MatcherIndex++];
1818 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1820 if (N->getOpcode() != ISD::AND) return false;
1822 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1823 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1826 ALWAYS_INLINE static bool
1827 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1828 SDValue N, SelectionDAGISel &SDISel) {
1829 int64_t Val = MatcherTable[MatcherIndex++];
1831 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1833 if (N->getOpcode() != ISD::OR) return false;
1835 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1836 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1839 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1840 /// scope, evaluate the current node. If the current predicate is known to
1841 /// fail, set Result=true and return anything. If the current predicate is
1842 /// known to pass, set Result=false and return the MatcherIndex to continue
1843 /// with. If the current predicate is unknown, set Result=false and return the
1844 /// MatcherIndex to continue with.
1845 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1846 unsigned Index, SDValue N,
1847 bool &Result, SelectionDAGISel &SDISel,
1848 SmallVectorImpl<SDValue> &RecordedNodes){
1849 switch (Table[Index++]) {
1852 return Index-1; // Could not evaluate this predicate.
1853 case SelectionDAGISel::OPC_CheckSame:
1854 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1856 case SelectionDAGISel::OPC_CheckPatternPredicate:
1857 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1859 case SelectionDAGISel::OPC_CheckPredicate:
1860 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1862 case SelectionDAGISel::OPC_CheckOpcode:
1863 Result = !::CheckOpcode(Table, Index, N.getNode());
1865 case SelectionDAGISel::OPC_CheckType:
1866 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1868 case SelectionDAGISel::OPC_CheckChild0Type:
1869 case SelectionDAGISel::OPC_CheckChild1Type:
1870 case SelectionDAGISel::OPC_CheckChild2Type:
1871 case SelectionDAGISel::OPC_CheckChild3Type:
1872 case SelectionDAGISel::OPC_CheckChild4Type:
1873 case SelectionDAGISel::OPC_CheckChild5Type:
1874 case SelectionDAGISel::OPC_CheckChild6Type:
1875 case SelectionDAGISel::OPC_CheckChild7Type:
1876 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1877 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1879 case SelectionDAGISel::OPC_CheckCondCode:
1880 Result = !::CheckCondCode(Table, Index, N);
1882 case SelectionDAGISel::OPC_CheckValueType:
1883 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1885 case SelectionDAGISel::OPC_CheckInteger:
1886 Result = !::CheckInteger(Table, Index, N);
1888 case SelectionDAGISel::OPC_CheckAndImm:
1889 Result = !::CheckAndImm(Table, Index, N, SDISel);
1891 case SelectionDAGISel::OPC_CheckOrImm:
1892 Result = !::CheckOrImm(Table, Index, N, SDISel);
1899 /// FailIndex - If this match fails, this is the index to continue with.
1902 /// NodeStack - The node stack when the scope was formed.
1903 SmallVector<SDValue, 4> NodeStack;
1905 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1906 unsigned NumRecordedNodes;
1908 /// NumMatchedMemRefs - The number of matched memref entries.
1909 unsigned NumMatchedMemRefs;
1911 /// InputChain/InputFlag - The current chain/flag
1912 SDValue InputChain, InputFlag;
1914 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1915 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1918 SDNode *SelectionDAGISel::
1919 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1920 unsigned TableSize) {
1921 // FIXME: Should these even be selected? Handle these cases in the caller?
1922 switch (NodeToMatch->getOpcode()) {
1925 case ISD::EntryToken: // These nodes remain the same.
1926 case ISD::BasicBlock:
1928 //case ISD::VALUETYPE:
1929 //case ISD::CONDCODE:
1930 case ISD::HANDLENODE:
1931 case ISD::MDNODE_SDNODE:
1932 case ISD::TargetConstant:
1933 case ISD::TargetConstantFP:
1934 case ISD::TargetConstantPool:
1935 case ISD::TargetFrameIndex:
1936 case ISD::TargetExternalSymbol:
1937 case ISD::TargetBlockAddress:
1938 case ISD::TargetJumpTable:
1939 case ISD::TargetGlobalTLSAddress:
1940 case ISD::TargetGlobalAddress:
1941 case ISD::TokenFactor:
1942 case ISD::CopyFromReg:
1943 case ISD::CopyToReg:
1945 NodeToMatch->setNodeId(-1); // Mark selected.
1947 case ISD::AssertSext:
1948 case ISD::AssertZext:
1949 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1950 NodeToMatch->getOperand(0));
1952 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1953 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1956 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1958 // Set up the node stack with NodeToMatch as the only node on the stack.
1959 SmallVector<SDValue, 8> NodeStack;
1960 SDValue N = SDValue(NodeToMatch, 0);
1961 NodeStack.push_back(N);
1963 // MatchScopes - Scopes used when matching, if a match failure happens, this
1964 // indicates where to continue checking.
1965 SmallVector<MatchScope, 8> MatchScopes;
1967 // RecordedNodes - This is the set of nodes that have been recorded by the
1969 SmallVector<SDValue, 8> RecordedNodes;
1971 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1973 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1975 // These are the current input chain and flag for use when generating nodes.
1976 // Various Emit operations change these. For example, emitting a copytoreg
1977 // uses and updates these.
1978 SDValue InputChain, InputFlag;
1980 // ChainNodesMatched - If a pattern matches nodes that have input/output
1981 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1982 // which ones they are. The result is captured into this list so that we can
1983 // update the chain results when the pattern is complete.
1984 SmallVector<SDNode*, 3> ChainNodesMatched;
1985 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1987 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1988 NodeToMatch->dump(CurDAG);
1991 // Determine where to start the interpreter. Normally we start at opcode #0,
1992 // but if the state machine starts with an OPC_SwitchOpcode, then we
1993 // accelerate the first lookup (which is guaranteed to be hot) with the
1994 // OpcodeOffset table.
1995 unsigned MatcherIndex = 0;
1997 if (!OpcodeOffset.empty()) {
1998 // Already computed the OpcodeOffset table, just index into it.
1999 if (N.getOpcode() < OpcodeOffset.size())
2000 MatcherIndex = OpcodeOffset[N.getOpcode()];
2001 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2003 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2004 // Otherwise, the table isn't computed, but the state machine does start
2005 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2006 // is the first time we're selecting an instruction.
2009 // Get the size of this case.
2010 unsigned CaseSize = MatcherTable[Idx++];
2012 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2013 if (CaseSize == 0) break;
2015 // Get the opcode, add the index to the table.
2016 uint16_t Opc = MatcherTable[Idx++];
2017 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2018 if (Opc >= OpcodeOffset.size())
2019 OpcodeOffset.resize((Opc+1)*2);
2020 OpcodeOffset[Opc] = Idx;
2024 // Okay, do the lookup for the first opcode.
2025 if (N.getOpcode() < OpcodeOffset.size())
2026 MatcherIndex = OpcodeOffset[N.getOpcode()];
2030 assert(MatcherIndex < TableSize && "Invalid index");
2032 unsigned CurrentOpcodeIndex = MatcherIndex;
2034 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2037 // Okay, the semantics of this operation are that we should push a scope
2038 // then evaluate the first child. However, pushing a scope only to have
2039 // the first check fail (which then pops it) is inefficient. If we can
2040 // determine immediately that the first check (or first several) will
2041 // immediately fail, don't even bother pushing a scope for them.
2045 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2046 if (NumToSkip & 128)
2047 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2048 // Found the end of the scope with no match.
2049 if (NumToSkip == 0) {
2054 FailIndex = MatcherIndex+NumToSkip;
2056 unsigned MatcherIndexOfPredicate = MatcherIndex;
2057 (void)MatcherIndexOfPredicate; // silence warning.
2059 // If we can't evaluate this predicate without pushing a scope (e.g. if
2060 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2061 // push the scope and evaluate the full predicate chain.
2063 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2064 Result, *this, RecordedNodes);
2068 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2069 << "index " << MatcherIndexOfPredicate
2070 << ", continuing at " << FailIndex << "\n");
2071 ++NumDAGIselRetries;
2073 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2074 // move to the next case.
2075 MatcherIndex = FailIndex;
2078 // If the whole scope failed to match, bail.
2079 if (FailIndex == 0) break;
2081 // Push a MatchScope which indicates where to go if the first child fails
2083 MatchScope NewEntry;
2084 NewEntry.FailIndex = FailIndex;
2085 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2086 NewEntry.NumRecordedNodes = RecordedNodes.size();
2087 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2088 NewEntry.InputChain = InputChain;
2089 NewEntry.InputFlag = InputFlag;
2090 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2091 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2092 MatchScopes.push_back(NewEntry);
2095 case OPC_RecordNode:
2096 // Remember this node, it may end up being an operand in the pattern.
2097 RecordedNodes.push_back(N);
2100 case OPC_RecordChild0: case OPC_RecordChild1:
2101 case OPC_RecordChild2: case OPC_RecordChild3:
2102 case OPC_RecordChild4: case OPC_RecordChild5:
2103 case OPC_RecordChild6: case OPC_RecordChild7: {
2104 unsigned ChildNo = Opcode-OPC_RecordChild0;
2105 if (ChildNo >= N.getNumOperands())
2106 break; // Match fails if out of range child #.
2108 RecordedNodes.push_back(N->getOperand(ChildNo));
2111 case OPC_RecordMemRef:
2112 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2115 case OPC_CaptureFlagInput:
2116 // If the current node has an input flag, capture it in InputFlag.
2117 if (N->getNumOperands() != 0 &&
2118 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2119 InputFlag = N->getOperand(N->getNumOperands()-1);
2122 case OPC_MoveChild: {
2123 unsigned ChildNo = MatcherTable[MatcherIndex++];
2124 if (ChildNo >= N.getNumOperands())
2125 break; // Match fails if out of range child #.
2126 N = N.getOperand(ChildNo);
2127 NodeStack.push_back(N);
2131 case OPC_MoveParent:
2132 // Pop the current node off the NodeStack.
2133 NodeStack.pop_back();
2134 assert(!NodeStack.empty() && "Node stack imbalance!");
2135 N = NodeStack.back();
2139 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2141 case OPC_CheckPatternPredicate:
2142 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2144 case OPC_CheckPredicate:
2145 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2149 case OPC_CheckComplexPat: {
2150 unsigned CPNum = MatcherTable[MatcherIndex++];
2151 unsigned RecNo = MatcherTable[MatcherIndex++];
2152 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2153 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2158 case OPC_CheckOpcode:
2159 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2163 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2166 case OPC_SwitchOpcode: {
2167 unsigned CurNodeOpcode = N.getOpcode();
2168 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2171 // Get the size of this case.
2172 CaseSize = MatcherTable[MatcherIndex++];
2174 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2175 if (CaseSize == 0) break;
2177 uint16_t Opc = MatcherTable[MatcherIndex++];
2178 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2180 // If the opcode matches, then we will execute this case.
2181 if (CurNodeOpcode == Opc)
2184 // Otherwise, skip over this case.
2185 MatcherIndex += CaseSize;
2188 // If no cases matched, bail out.
2189 if (CaseSize == 0) break;
2191 // Otherwise, execute the case we found.
2192 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2193 << " to " << MatcherIndex << "\n");
2197 case OPC_SwitchType: {
2198 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2199 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2202 // Get the size of this case.
2203 CaseSize = MatcherTable[MatcherIndex++];
2205 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2206 if (CaseSize == 0) break;
2208 MVT::SimpleValueType CaseVT =
2209 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2210 if (CaseVT == MVT::iPTR)
2211 CaseVT = TLI.getPointerTy().SimpleTy;
2213 // If the VT matches, then we will execute this case.
2214 if (CurNodeVT == CaseVT)
2217 // Otherwise, skip over this case.
2218 MatcherIndex += CaseSize;
2221 // If no cases matched, bail out.
2222 if (CaseSize == 0) break;
2224 // Otherwise, execute the case we found.
2225 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2226 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2229 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2230 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2231 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2232 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2233 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2234 Opcode-OPC_CheckChild0Type))
2237 case OPC_CheckCondCode:
2238 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2240 case OPC_CheckValueType:
2241 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2243 case OPC_CheckInteger:
2244 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2246 case OPC_CheckAndImm:
2247 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2249 case OPC_CheckOrImm:
2250 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2253 case OPC_CheckFoldableChainNode: {
2254 assert(NodeStack.size() != 1 && "No parent node");
2255 // Verify that all intermediate nodes between the root and this one have
2257 bool HasMultipleUses = false;
2258 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2259 if (!NodeStack[i].hasOneUse()) {
2260 HasMultipleUses = true;
2263 if (HasMultipleUses) break;
2265 // Check to see that the target thinks this is profitable to fold and that
2266 // we can fold it without inducing cycles in the graph.
2267 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2269 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2270 NodeToMatch, true/*We validate our own chains*/))
2275 case OPC_EmitInteger: {
2276 MVT::SimpleValueType VT =
2277 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2278 int64_t Val = MatcherTable[MatcherIndex++];
2280 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2281 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2284 case OPC_EmitRegister: {
2285 MVT::SimpleValueType VT =
2286 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2287 unsigned RegNo = MatcherTable[MatcherIndex++];
2288 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2292 case OPC_EmitConvertToTarget: {
2293 // Convert from IMM/FPIMM to target version.
2294 unsigned RecNo = MatcherTable[MatcherIndex++];
2295 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2296 SDValue Imm = RecordedNodes[RecNo];
2298 if (Imm->getOpcode() == ISD::Constant) {
2299 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2300 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2301 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2302 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2303 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2306 RecordedNodes.push_back(Imm);
2310 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2311 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2312 // These are space-optimized forms of OPC_EmitMergeInputChains.
2313 assert(InputChain.getNode() == 0 &&
2314 "EmitMergeInputChains should be the first chain producing node");
2315 assert(ChainNodesMatched.empty() &&
2316 "Should only have one EmitMergeInputChains per match");
2318 // Read all of the chained nodes.
2319 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2320 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2321 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2323 // FIXME: What if other value results of the node have uses not matched
2325 if (ChainNodesMatched.back() != NodeToMatch &&
2326 !RecordedNodes[RecNo].hasOneUse()) {
2327 ChainNodesMatched.clear();
2331 // Merge the input chains if they are not intra-pattern references.
2332 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2334 if (InputChain.getNode() == 0)
2335 break; // Failed to merge.
2339 case OPC_EmitMergeInputChains: {
2340 assert(InputChain.getNode() == 0 &&
2341 "EmitMergeInputChains should be the first chain producing node");
2342 // This node gets a list of nodes we matched in the input that have
2343 // chains. We want to token factor all of the input chains to these nodes
2344 // together. However, if any of the input chains is actually one of the
2345 // nodes matched in this pattern, then we have an intra-match reference.
2346 // Ignore these because the newly token factored chain should not refer to
2348 unsigned NumChains = MatcherTable[MatcherIndex++];
2349 assert(NumChains != 0 && "Can't TF zero chains");
2351 assert(ChainNodesMatched.empty() &&
2352 "Should only have one EmitMergeInputChains per match");
2354 // Read all of the chained nodes.
2355 for (unsigned i = 0; i != NumChains; ++i) {
2356 unsigned RecNo = MatcherTable[MatcherIndex++];
2357 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2358 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2360 // FIXME: What if other value results of the node have uses not matched
2362 if (ChainNodesMatched.back() != NodeToMatch &&
2363 !RecordedNodes[RecNo].hasOneUse()) {
2364 ChainNodesMatched.clear();
2369 // If the inner loop broke out, the match fails.
2370 if (ChainNodesMatched.empty())
2373 // Merge the input chains if they are not intra-pattern references.
2374 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2376 if (InputChain.getNode() == 0)
2377 break; // Failed to merge.
2382 case OPC_EmitCopyToReg: {
2383 unsigned RecNo = MatcherTable[MatcherIndex++];
2384 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2385 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2387 if (InputChain.getNode() == 0)
2388 InputChain = CurDAG->getEntryNode();
2390 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2391 DestPhysReg, RecordedNodes[RecNo],
2394 InputFlag = InputChain.getValue(1);
2398 case OPC_EmitNodeXForm: {
2399 unsigned XFormNo = MatcherTable[MatcherIndex++];
2400 unsigned RecNo = MatcherTable[MatcherIndex++];
2401 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2402 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2407 case OPC_MorphNodeTo: {
2408 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2409 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2410 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2411 // Get the result VT list.
2412 unsigned NumVTs = MatcherTable[MatcherIndex++];
2413 SmallVector<EVT, 4> VTs;
2414 for (unsigned i = 0; i != NumVTs; ++i) {
2415 MVT::SimpleValueType VT =
2416 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2417 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2421 if (EmitNodeInfo & OPFL_Chain)
2422 VTs.push_back(MVT::Other);
2423 if (EmitNodeInfo & OPFL_FlagOutput)
2424 VTs.push_back(MVT::Flag);
2426 // This is hot code, so optimize the two most common cases of 1 and 2
2429 if (VTs.size() == 1)
2430 VTList = CurDAG->getVTList(VTs[0]);
2431 else if (VTs.size() == 2)
2432 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2434 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2436 // Get the operand list.
2437 unsigned NumOps = MatcherTable[MatcherIndex++];
2438 SmallVector<SDValue, 8> Ops;
2439 for (unsigned i = 0; i != NumOps; ++i) {
2440 unsigned RecNo = MatcherTable[MatcherIndex++];
2442 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2444 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2445 Ops.push_back(RecordedNodes[RecNo]);
2448 // If there are variadic operands to add, handle them now.
2449 if (EmitNodeInfo & OPFL_VariadicInfo) {
2450 // Determine the start index to copy from.
2451 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2452 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2453 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2454 "Invalid variadic node");
2455 // Copy all of the variadic operands, not including a potential flag
2457 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2459 SDValue V = NodeToMatch->getOperand(i);
2460 if (V.getValueType() == MVT::Flag) break;
2465 // If this has chain/flag inputs, add them.
2466 if (EmitNodeInfo & OPFL_Chain)
2467 Ops.push_back(InputChain);
2468 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2469 Ops.push_back(InputFlag);
2473 if (Opcode != OPC_MorphNodeTo) {
2474 // If this is a normal EmitNode command, just create the new node and
2475 // add the results to the RecordedNodes list.
2476 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2477 VTList, Ops.data(), Ops.size());
2479 // Add all the non-flag/non-chain results to the RecordedNodes list.
2480 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2481 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2482 RecordedNodes.push_back(SDValue(Res, i));
2486 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2490 // If the node had chain/flag results, update our notion of the current
2492 if (EmitNodeInfo & OPFL_FlagOutput) {
2493 InputFlag = SDValue(Res, VTs.size()-1);
2494 if (EmitNodeInfo & OPFL_Chain)
2495 InputChain = SDValue(Res, VTs.size()-2);
2496 } else if (EmitNodeInfo & OPFL_Chain)
2497 InputChain = SDValue(Res, VTs.size()-1);
2499 // If the OPFL_MemRefs flag is set on this node, slap all of the
2500 // accumulated memrefs onto it.
2502 // FIXME: This is vastly incorrect for patterns with multiple outputs
2503 // instructions that access memory and for ComplexPatterns that match
2505 if (EmitNodeInfo & OPFL_MemRefs) {
2506 MachineSDNode::mmo_iterator MemRefs =
2507 MF->allocateMemRefsArray(MatchedMemRefs.size());
2508 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2509 cast<MachineSDNode>(Res)
2510 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2514 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2515 << " node: "; Res->dump(CurDAG); errs() << "\n");
2517 // If this was a MorphNodeTo then we're completely done!
2518 if (Opcode == OPC_MorphNodeTo) {
2519 // Update chain and flag uses.
2520 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2521 InputFlag, FlagResultNodesMatched, true);
2528 case OPC_MarkFlagResults: {
2529 unsigned NumNodes = MatcherTable[MatcherIndex++];
2531 // Read and remember all the flag-result nodes.
2532 for (unsigned i = 0; i != NumNodes; ++i) {
2533 unsigned RecNo = MatcherTable[MatcherIndex++];
2535 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2537 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2538 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2543 case OPC_CompleteMatch: {
2544 // The match has been completed, and any new nodes (if any) have been
2545 // created. Patch up references to the matched dag to use the newly
2547 unsigned NumResults = MatcherTable[MatcherIndex++];
2549 for (unsigned i = 0; i != NumResults; ++i) {
2550 unsigned ResSlot = MatcherTable[MatcherIndex++];
2552 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2554 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2555 SDValue Res = RecordedNodes[ResSlot];
2557 assert(i < NodeToMatch->getNumValues() &&
2558 NodeToMatch->getValueType(i) != MVT::Other &&
2559 NodeToMatch->getValueType(i) != MVT::Flag &&
2560 "Invalid number of results to complete!");
2561 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2562 NodeToMatch->getValueType(i) == MVT::iPTR ||
2563 Res.getValueType() == MVT::iPTR ||
2564 NodeToMatch->getValueType(i).getSizeInBits() ==
2565 Res.getValueType().getSizeInBits()) &&
2566 "invalid replacement");
2567 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2570 // If the root node defines a flag, add it to the flag nodes to update
2572 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2573 FlagResultNodesMatched.push_back(NodeToMatch);
2575 // Update chain and flag uses.
2576 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2577 InputFlag, FlagResultNodesMatched, false);
2579 assert(NodeToMatch->use_empty() &&
2580 "Didn't replace all uses of the node?");
2582 // FIXME: We just return here, which interacts correctly with SelectRoot
2583 // above. We should fix this to not return an SDNode* anymore.
2588 // If the code reached this point, then the match failed. See if there is
2589 // another child to try in the current 'Scope', otherwise pop it until we
2590 // find a case to check.
2591 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2592 ++NumDAGIselRetries;
2594 if (MatchScopes.empty()) {
2595 CannotYetSelect(NodeToMatch);
2599 // Restore the interpreter state back to the point where the scope was
2601 MatchScope &LastScope = MatchScopes.back();
2602 RecordedNodes.resize(LastScope.NumRecordedNodes);
2604 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2605 N = NodeStack.back();
2607 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2608 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2609 MatcherIndex = LastScope.FailIndex;
2611 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2613 InputChain = LastScope.InputChain;
2614 InputFlag = LastScope.InputFlag;
2615 if (!LastScope.HasChainNodesMatched)
2616 ChainNodesMatched.clear();
2617 if (!LastScope.HasFlagResultNodesMatched)
2618 FlagResultNodesMatched.clear();
2620 // Check to see what the offset is at the new MatcherIndex. If it is zero
2621 // we have reached the end of this scope, otherwise we have another child
2622 // in the current scope to try.
2623 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2624 if (NumToSkip & 128)
2625 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2627 // If we have another child in this scope to match, update FailIndex and
2629 if (NumToSkip != 0) {
2630 LastScope.FailIndex = MatcherIndex+NumToSkip;
2634 // End of this scope, pop it and try the next child in the containing
2636 MatchScopes.pop_back();
2643 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2645 raw_string_ostream Msg(msg);
2646 Msg << "Cannot yet select: ";
2648 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2649 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2650 N->getOpcode() != ISD::INTRINSIC_VOID) {
2651 N->printrFull(Msg, CurDAG);
2653 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2655 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2656 if (iid < Intrinsic::num_intrinsics)
2657 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2658 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2659 Msg << "target intrinsic %" << TII->getName(iid);
2661 Msg << "unknown intrinsic #" << iid;
2663 report_fatal_error(Msg.str());
2666 char SelectionDAGISel::ID = 0;