1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/CodeGen/ScheduleDAG.h"
17 #include "llvm/CallingConv.h"
18 #include "llvm/Constants.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/InlineAsm.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineDebugInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SchedulerRegistry.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/CodeGen/SSARegMap.h"
35 #include "llvm/Target/MRegisterInfo.h"
36 #include "llvm/Target/TargetData.h"
37 #include "llvm/Target/TargetFrameInfo.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetLowering.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/Compiler.h"
54 ViewISelDAGs("view-isel-dags", cl::Hidden,
55 cl::desc("Pop up a window to show isel dags as they are selected"));
57 ViewSchedDAGs("view-sched-dags", cl::Hidden,
58 cl::desc("Pop up a window to show sched dags as they are processed"));
60 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
64 //===---------------------------------------------------------------------===//
66 /// RegisterScheduler class - Track the registration of instruction schedulers.
68 //===---------------------------------------------------------------------===//
69 MachinePassRegistry RegisterScheduler::Registry;
71 //===---------------------------------------------------------------------===//
73 /// ISHeuristic command line option for instruction schedulers.
75 //===---------------------------------------------------------------------===//
77 cl::opt<RegisterScheduler::FunctionPassCtor, false,
78 RegisterPassParser<RegisterScheduler> >
80 cl::init(&createDefaultScheduler),
81 cl::desc("Instruction schedulers available:"));
83 static RegisterScheduler
84 defaultListDAGScheduler("default", " Best scheduler for the target",
85 createDefaultScheduler);
89 /// RegsForValue - This struct represents the physical registers that a
90 /// particular value is assigned and the type information about the value.
91 /// This is needed because values can be promoted into larger registers and
92 /// expanded into multiple smaller registers than the value.
93 struct VISIBILITY_HIDDEN RegsForValue {
94 /// Regs - This list hold the register (for legal and promoted values)
95 /// or register set (for expanded values) that the value should be assigned
97 std::vector<unsigned> Regs;
99 /// RegVT - The value type of each register.
101 MVT::ValueType RegVT;
103 /// ValueVT - The value type of the LLVM value, which may be promoted from
104 /// RegVT or made from merging the two expanded parts.
105 MVT::ValueType ValueVT;
107 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
109 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
110 : RegVT(regvt), ValueVT(valuevt) {
113 RegsForValue(const std::vector<unsigned> ®s,
114 MVT::ValueType regvt, MVT::ValueType valuevt)
115 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
118 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
119 /// this value and returns the result as a ValueVT value. This uses
120 /// Chain/Flag as the input and updates them for the output Chain/Flag.
121 SDOperand getCopyFromRegs(SelectionDAG &DAG,
122 SDOperand &Chain, SDOperand &Flag) const;
124 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
125 /// specified value into the registers specified by this object. This uses
126 /// Chain/Flag as the input and updates them for the output Chain/Flag.
127 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
128 SDOperand &Chain, SDOperand &Flag,
129 MVT::ValueType PtrVT) const;
131 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
132 /// operand list. This adds the code marker and includes the number of
133 /// values added into it.
134 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
135 std::vector<SDOperand> &Ops) const;
140 //===--------------------------------------------------------------------===//
141 /// createDefaultScheduler - This creates an instruction scheduler appropriate
143 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
145 MachineBasicBlock *BB) {
146 TargetLowering &TLI = IS->getTargetLowering();
148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
149 return createTDListDAGScheduler(IS, DAG, BB);
151 assert(TLI.getSchedulingPreference() ==
152 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
153 return createBURRListDAGScheduler(IS, DAG, BB);
158 //===--------------------------------------------------------------------===//
159 /// FunctionLoweringInfo - This contains information that is global to a
160 /// function that is used when lowering a region of the function.
161 class FunctionLoweringInfo {
168 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
170 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
171 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
173 /// ValueMap - Since we emit code for the function a basic block at a time,
174 /// we must remember which virtual registers hold the values for
175 /// cross-basic-block values.
176 std::map<const Value*, unsigned> ValueMap;
178 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
179 /// the entry block. This allows the allocas to be efficiently referenced
180 /// anywhere in the function.
181 std::map<const AllocaInst*, int> StaticAllocaMap;
183 unsigned MakeReg(MVT::ValueType VT) {
184 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
187 unsigned CreateRegForValue(const Value *V);
189 unsigned InitializeRegForValue(const Value *V) {
190 unsigned &R = ValueMap[V];
191 assert(R == 0 && "Already initialized this value register!");
192 return R = CreateRegForValue(V);
197 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
198 /// PHI nodes or outside of the basic block that defines it, or used by a
199 /// switch instruction, which may expand to multiple basic blocks.
200 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
201 if (isa<PHINode>(I)) return true;
202 BasicBlock *BB = I->getParent();
203 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
204 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
205 isa<SwitchInst>(*UI))
210 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
211 /// entry block, return true. This includes arguments used by switches, since
212 /// the switch may expand into multiple basic blocks.
213 static bool isOnlyUsedInEntryBlock(Argument *A) {
214 BasicBlock *Entry = A->getParent()->begin();
215 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
216 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
217 return false; // Use not in entry block.
221 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
222 Function &fn, MachineFunction &mf)
223 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
225 // Create a vreg for each argument register that is not dead and is used
226 // outside of the entry block for the function.
227 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
229 if (!isOnlyUsedInEntryBlock(AI))
230 InitializeRegForValue(AI);
232 // Initialize the mapping of values to registers. This is only set up for
233 // instruction values that are used outside of the block that defines
235 Function::iterator BB = Fn.begin(), EB = Fn.end();
236 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
237 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
238 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
239 const Type *Ty = AI->getAllocatedType();
240 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
242 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
245 // If the alignment of the value is smaller than the size of the value,
246 // and if the size of the value is particularly small (<= 8 bytes),
247 // round up to the size of the value for potentially better performance.
249 // FIXME: This could be made better with a preferred alignment hook in
250 // TargetData. It serves primarily to 8-byte align doubles for X86.
251 if (Align < TySize && TySize <= 8) Align = TySize;
252 TySize *= CUI->getValue(); // Get total allocated size.
253 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
254 StaticAllocaMap[AI] =
255 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
258 for (; BB != EB; ++BB)
259 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
260 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
261 if (!isa<AllocaInst>(I) ||
262 !StaticAllocaMap.count(cast<AllocaInst>(I)))
263 InitializeRegForValue(I);
265 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
266 // also creates the initial PHI MachineInstrs, though none of the input
267 // operands are populated.
268 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
269 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
271 MF.getBasicBlockList().push_back(MBB);
273 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
276 for (BasicBlock::iterator I = BB->begin();
277 (PN = dyn_cast<PHINode>(I)); ++I)
278 if (!PN->use_empty()) {
279 MVT::ValueType VT = TLI.getValueType(PN->getType());
280 unsigned NumElements;
281 if (VT != MVT::Vector)
282 NumElements = TLI.getNumElements(VT);
284 MVT::ValueType VT1,VT2;
286 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
289 unsigned PHIReg = ValueMap[PN];
290 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
291 for (unsigned i = 0; i != NumElements; ++i)
292 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
297 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
298 /// the correctly promoted or expanded types. Assign these registers
299 /// consecutive vreg numbers and return the first assigned number.
300 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
301 MVT::ValueType VT = TLI.getValueType(V->getType());
303 // The number of multiples of registers that we need, to, e.g., split up
304 // a <2 x int64> -> 4 x i32 registers.
305 unsigned NumVectorRegs = 1;
307 // If this is a packed type, figure out what type it will decompose into
308 // and how many of the elements it will use.
309 if (VT == MVT::Vector) {
310 const PackedType *PTy = cast<PackedType>(V->getType());
311 unsigned NumElts = PTy->getNumElements();
312 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
314 // Divide the input until we get to a supported size. This will always
315 // end with a scalar if the target doesn't support vectors.
316 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
323 VT = getVectorType(EltTy, NumElts);
326 // The common case is that we will only create one register for this
327 // value. If we have that case, create and return the virtual register.
328 unsigned NV = TLI.getNumElements(VT);
330 // If we are promoting this value, pick the next largest supported type.
331 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
332 unsigned Reg = MakeReg(PromotedType);
333 // If this is a vector of supported or promoted types (e.g. 4 x i16),
334 // create all of the registers.
335 for (unsigned i = 1; i != NumVectorRegs; ++i)
336 MakeReg(PromotedType);
340 // If this value is represented with multiple target registers, make sure
341 // to create enough consecutive registers of the right (smaller) type.
342 unsigned NT = VT-1; // Find the type to use.
343 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
346 unsigned R = MakeReg((MVT::ValueType)NT);
347 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
348 MakeReg((MVT::ValueType)NT);
352 //===----------------------------------------------------------------------===//
353 /// SelectionDAGLowering - This is the common target-independent lowering
354 /// implementation that is parameterized by a TargetLowering object.
355 /// Also, targets can overload any lowering method.
358 class SelectionDAGLowering {
359 MachineBasicBlock *CurMBB;
361 std::map<const Value*, SDOperand> NodeMap;
363 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
364 /// them up and then emit token factor nodes when possible. This allows us to
365 /// get simple disambiguation between loads without worrying about alias
367 std::vector<SDOperand> PendingLoads;
369 /// Case - A pair of values to record the Value for a switch case, and the
370 /// case's target basic block.
371 typedef std::pair<Constant*, MachineBasicBlock*> Case;
372 typedef std::vector<Case>::iterator CaseItr;
373 typedef std::pair<CaseItr, CaseItr> CaseRange;
375 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
376 /// of conditional branches.
378 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
379 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
381 /// CaseBB - The MBB in which to emit the compare and branch
382 MachineBasicBlock *CaseBB;
383 /// LT, GE - If nonzero, we know the current case value must be less-than or
384 /// greater-than-or-equal-to these Constants.
387 /// Range - A pair of iterators representing the range of case values to be
388 /// processed at this point in the binary search tree.
392 /// The comparison function for sorting Case values.
394 bool operator () (const Case& C1, const Case& C2) {
395 if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first))
396 return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue();
398 const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first);
399 return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue();
404 // TLI - This is information that describes the available target features we
405 // need for lowering. This indicates when operations are unavailable,
406 // implemented with a libcall, etc.
409 const TargetData *TD;
411 /// SwitchCases - Vector of CaseBlock structures used to communicate
412 /// SwitchInst code generation information.
413 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
414 SelectionDAGISel::JumpTable JT;
416 /// FuncInfo - Information about the function as a whole.
418 FunctionLoweringInfo &FuncInfo;
420 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
421 FunctionLoweringInfo &funcinfo)
422 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
423 JT(0,0,0,0), FuncInfo(funcinfo) {
426 /// getRoot - Return the current virtual root of the Selection DAG.
428 SDOperand getRoot() {
429 if (PendingLoads.empty())
430 return DAG.getRoot();
432 if (PendingLoads.size() == 1) {
433 SDOperand Root = PendingLoads[0];
435 PendingLoads.clear();
439 // Otherwise, we have to make a token factor node.
440 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
441 &PendingLoads[0], PendingLoads.size());
442 PendingLoads.clear();
447 void visit(Instruction &I) { visit(I.getOpcode(), I); }
449 void visit(unsigned Opcode, User &I) {
451 default: assert(0 && "Unknown instruction type encountered!");
453 // Build the switch statement using the Instruction.def file.
454 #define HANDLE_INST(NUM, OPCODE, CLASS) \
455 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
456 #include "llvm/Instruction.def"
460 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
462 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
463 SDOperand SrcValue, SDOperand Root,
466 SDOperand getIntPtrConstant(uint64_t Val) {
467 return DAG.getConstant(Val, TLI.getPointerTy());
470 SDOperand getValue(const Value *V);
472 const SDOperand &setValue(const Value *V, SDOperand NewN) {
473 SDOperand &N = NodeMap[V];
474 assert(N.Val == 0 && "Already set a value for this node!");
478 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
480 bool OutReg, bool InReg,
481 std::set<unsigned> &OutputRegs,
482 std::set<unsigned> &InputRegs);
484 // Terminator instructions.
485 void visitRet(ReturnInst &I);
486 void visitBr(BranchInst &I);
487 void visitSwitch(SwitchInst &I);
488 void visitUnreachable(UnreachableInst &I) { /* noop */ }
490 // Helper for visitSwitch
491 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
492 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
494 // These all get lowered before this pass.
495 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
496 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
498 void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
499 void visitShift(User &I, unsigned Opcode);
500 void visitAdd(User &I) {
501 visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
503 void visitSub(User &I);
504 void visitMul(User &I) {
505 visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
507 void visitDiv(User &I) {
508 const Type *Ty = I.getType();
510 Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
511 Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
513 void visitRem(User &I) {
514 const Type *Ty = I.getType();
515 visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
517 void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
518 void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
519 void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
520 void visitShl(User &I) { visitShift(I, ISD::SHL); }
521 void visitShr(User &I) {
522 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
525 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc,
526 ISD::CondCode FPOpc);
527 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ,
529 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE,
531 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE,
533 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE,
535 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT,
537 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT,
540 void visitExtractElement(User &I);
541 void visitInsertElement(User &I);
542 void visitShuffleVector(User &I);
544 void visitGetElementPtr(User &I);
545 void visitCast(User &I);
546 void visitSelect(User &I);
548 void visitMalloc(MallocInst &I);
549 void visitFree(FreeInst &I);
550 void visitAlloca(AllocaInst &I);
551 void visitLoad(LoadInst &I);
552 void visitStore(StoreInst &I);
553 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
554 void visitCall(CallInst &I);
555 void visitInlineAsm(CallInst &I);
556 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
557 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
559 void visitVAStart(CallInst &I);
560 void visitVAArg(VAArgInst &I);
561 void visitVAEnd(CallInst &I);
562 void visitVACopy(CallInst &I);
563 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
565 void visitMemIntrinsic(CallInst &I, unsigned Op);
567 void visitUserOp1(Instruction &I) {
568 assert(0 && "UserOp1 should not exist at instruction selection time!");
571 void visitUserOp2(Instruction &I) {
572 assert(0 && "UserOp2 should not exist at instruction selection time!");
576 } // end namespace llvm
578 SDOperand SelectionDAGLowering::getValue(const Value *V) {
579 SDOperand &N = NodeMap[V];
582 const Type *VTy = V->getType();
583 MVT::ValueType VT = TLI.getValueType(VTy);
584 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
585 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
586 visit(CE->getOpcode(), *CE);
587 assert(N.Val && "visit didn't populate the ValueMap!");
589 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
590 return N = DAG.getGlobalAddress(GV, VT);
591 } else if (isa<ConstantPointerNull>(C)) {
592 return N = DAG.getConstant(0, TLI.getPointerTy());
593 } else if (isa<UndefValue>(C)) {
594 if (!isa<PackedType>(VTy))
595 return N = DAG.getNode(ISD::UNDEF, VT);
597 // Create a VBUILD_VECTOR of undef nodes.
598 const PackedType *PTy = cast<PackedType>(VTy);
599 unsigned NumElements = PTy->getNumElements();
600 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
602 SmallVector<SDOperand, 8> Ops;
603 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
605 // Create a VConstant node with generic Vector type.
606 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
607 Ops.push_back(DAG.getValueType(PVT));
608 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
609 &Ops[0], Ops.size());
610 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
611 return N = DAG.getConstantFP(CFP->getValue(), VT);
612 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
613 unsigned NumElements = PTy->getNumElements();
614 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
616 // Now that we know the number and type of the elements, push a
617 // Constant or ConstantFP node onto the ops list for each element of
618 // the packed constant.
619 SmallVector<SDOperand, 8> Ops;
620 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
621 for (unsigned i = 0; i != NumElements; ++i)
622 Ops.push_back(getValue(CP->getOperand(i)));
624 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
626 if (MVT::isFloatingPoint(PVT))
627 Op = DAG.getConstantFP(0, PVT);
629 Op = DAG.getConstant(0, PVT);
630 Ops.assign(NumElements, Op);
633 // Create a VBUILD_VECTOR node with generic Vector type.
634 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
635 Ops.push_back(DAG.getValueType(PVT));
636 return N = DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector,&Ops[0],Ops.size());
638 // Canonicalize all constant ints to be unsigned.
639 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
643 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
644 std::map<const AllocaInst*, int>::iterator SI =
645 FuncInfo.StaticAllocaMap.find(AI);
646 if (SI != FuncInfo.StaticAllocaMap.end())
647 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
650 std::map<const Value*, unsigned>::const_iterator VMI =
651 FuncInfo.ValueMap.find(V);
652 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
654 unsigned InReg = VMI->second;
656 // If this type is not legal, make it so now.
657 if (VT != MVT::Vector) {
658 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
660 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
662 // Source must be expanded. This input value is actually coming from the
663 // register pair VMI->second and VMI->second+1.
664 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
665 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
666 } else if (DestVT > VT) { // Promotion case
667 if (MVT::isFloatingPoint(VT))
668 N = DAG.getNode(ISD::FP_ROUND, VT, N);
670 N = DAG.getNode(ISD::TRUNCATE, VT, N);
673 // Otherwise, if this is a vector, make it available as a generic vector
675 MVT::ValueType PTyElementVT, PTyLegalElementVT;
676 const PackedType *PTy = cast<PackedType>(VTy);
677 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
680 // Build a VBUILD_VECTOR with the input registers.
681 SmallVector<SDOperand, 8> Ops;
682 if (PTyElementVT == PTyLegalElementVT) {
683 // If the value types are legal, just VBUILD the CopyFromReg nodes.
684 for (unsigned i = 0; i != NE; ++i)
685 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
687 } else if (PTyElementVT < PTyLegalElementVT) {
688 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
689 for (unsigned i = 0; i != NE; ++i) {
690 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
692 if (MVT::isFloatingPoint(PTyElementVT))
693 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
695 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
699 // If the register was expanded, use BUILD_PAIR.
700 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
701 for (unsigned i = 0; i != NE/2; ++i) {
702 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
704 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
706 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
710 Ops.push_back(DAG.getConstant(NE, MVT::i32));
711 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
712 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
714 // Finally, use a VBIT_CONVERT to make this available as the appropriate
716 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
717 DAG.getConstant(PTy->getNumElements(),
719 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
726 void SelectionDAGLowering::visitRet(ReturnInst &I) {
727 if (I.getNumOperands() == 0) {
728 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
731 SmallVector<SDOperand, 8> NewValues;
732 NewValues.push_back(getRoot());
733 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
734 SDOperand RetOp = getValue(I.getOperand(i));
735 bool isSigned = I.getOperand(i)->getType()->isSigned();
737 // If this is an integer return value, we need to promote it ourselves to
738 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
740 // FIXME: C calling convention requires the return type to be promoted to
741 // at least 32-bit. But this is not necessary for non-C calling conventions.
742 if (MVT::isInteger(RetOp.getValueType()) &&
743 RetOp.getValueType() < MVT::i64) {
744 MVT::ValueType TmpVT;
745 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
746 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
751 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
753 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
755 NewValues.push_back(RetOp);
756 NewValues.push_back(DAG.getConstant(isSigned, MVT::i32));
758 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
759 &NewValues[0], NewValues.size()));
762 void SelectionDAGLowering::visitBr(BranchInst &I) {
763 // Update machine-CFG edges.
764 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
765 CurMBB->addSuccessor(Succ0MBB);
767 // Figure out which block is immediately after the current one.
768 MachineBasicBlock *NextBlock = 0;
769 MachineFunction::iterator BBI = CurMBB;
770 if (++BBI != CurMBB->getParent()->end())
773 if (I.isUnconditional()) {
774 // If this is not a fall-through branch, emit the branch.
775 if (Succ0MBB != NextBlock)
776 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
777 DAG.getBasicBlock(Succ0MBB)));
779 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
780 CurMBB->addSuccessor(Succ1MBB);
782 SDOperand Cond = getValue(I.getCondition());
783 if (Succ1MBB == NextBlock) {
784 // If the condition is false, fall through. This means we should branch
785 // if the condition is true to Succ #0.
786 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
787 Cond, DAG.getBasicBlock(Succ0MBB)));
788 } else if (Succ0MBB == NextBlock) {
789 // If the condition is true, fall through. This means we should branch if
790 // the condition is false to Succ #1. Invert the condition first.
791 SDOperand True = DAG.getConstant(1, Cond.getValueType());
792 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
793 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
794 Cond, DAG.getBasicBlock(Succ1MBB)));
796 std::vector<SDOperand> Ops;
797 Ops.push_back(getRoot());
798 // If the false case is the current basic block, then this is a self
799 // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
800 // adds an extra instruction in the loop. Instead, invert the
801 // condition and emit "Loop: ... br!cond Loop; br Out.
802 if (CurMBB == Succ1MBB) {
803 std::swap(Succ0MBB, Succ1MBB);
804 SDOperand True = DAG.getConstant(1, Cond.getValueType());
805 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
807 SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
808 DAG.getBasicBlock(Succ0MBB));
809 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
810 DAG.getBasicBlock(Succ1MBB)));
815 /// visitSwitchCase - Emits the necessary code to represent a single node in
816 /// the binary search tree resulting from lowering a switch instruction.
817 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
818 SDOperand SwitchOp = getValue(CB.SwitchV);
819 SDOperand CaseOp = getValue(CB.CaseC);
820 SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC);
822 // Set NextBlock to be the MBB immediately after the current one, if any.
823 // This is used to avoid emitting unnecessary branches to the next block.
824 MachineBasicBlock *NextBlock = 0;
825 MachineFunction::iterator BBI = CurMBB;
826 if (++BBI != CurMBB->getParent()->end())
829 // If the lhs block is the next block, invert the condition so that we can
830 // fall through to the lhs instead of the rhs block.
831 if (CB.LHSBB == NextBlock) {
832 std::swap(CB.LHSBB, CB.RHSBB);
833 SDOperand True = DAG.getConstant(1, Cond.getValueType());
834 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
836 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
837 DAG.getBasicBlock(CB.LHSBB));
838 if (CB.RHSBB == NextBlock)
841 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
842 DAG.getBasicBlock(CB.RHSBB)));
843 // Update successor info
844 CurMBB->addSuccessor(CB.LHSBB);
845 CurMBB->addSuccessor(CB.RHSBB);
848 /// visitSwitchCase - Emits the necessary code to represent a single node in
849 /// the binary search tree resulting from lowering a switch instruction.
850 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
851 // FIXME: Need to emit different code for PIC vs. Non-PIC, specifically,
852 // we need to add the address of the jump table to the value loaded, since
853 // the entries in the jump table will be differences rather than absolute
856 // Emit the code for the jump table
857 MVT::ValueType PTy = TLI.getPointerTy();
858 assert((PTy == MVT::i32 || PTy == MVT::i64) &&
859 "Jump table entries are 32-bit values");
860 bool isPIC = TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_;
861 // PIC jump table entries are 32-bit values.
862 unsigned EntrySize = isPIC ? 4 : MVT::getSizeInBits(PTy)/8;
863 SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
864 SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy,
865 DAG.getConstant(EntrySize, PTy));
866 SDOperand TAB = DAG.getJumpTable(JT.JTI,PTy);
867 SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, TAB);
868 SDOperand LD = DAG.getLoad(isPIC ? MVT::i32 : PTy, Copy.getValue(1), ADD,
871 ADD = DAG.getNode(ISD::ADD, PTy,
872 ((PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD), TAB);
873 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), ADD));
875 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD));
879 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
880 // Figure out which block is immediately after the current one.
881 MachineBasicBlock *NextBlock = 0;
882 MachineFunction::iterator BBI = CurMBB;
883 if (++BBI != CurMBB->getParent()->end())
886 // If there is only the default destination, branch to it if it is not the
887 // next basic block. Otherwise, just fall through.
888 if (I.getNumOperands() == 2) {
889 // Update machine-CFG edges.
890 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()];
891 // If this is not a fall-through branch, emit the branch.
892 if (DefaultMBB != NextBlock)
893 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
894 DAG.getBasicBlock(DefaultMBB)));
895 CurMBB->addSuccessor(DefaultMBB);
899 // If there are any non-default case statements, create a vector of Cases
900 // representing each one, and sort the vector so that we can efficiently
901 // create a binary search tree from them.
902 std::vector<Case> Cases;
903 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
904 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
905 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
907 std::sort(Cases.begin(), Cases.end(), CaseCmp());
909 // Get the Value to be switched on and default basic blocks, which will be
910 // inserted into CaseBlock records, representing basic blocks in the binary
912 Value *SV = I.getOperand(0);
913 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
915 // Get the MachineFunction which holds the current MBB. This is used during
916 // emission of jump tables, and when inserting any additional MBBs necessary
917 // to represent the switch.
918 MachineFunction *CurMF = CurMBB->getParent();
919 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
921 // If the switch has more than 5 blocks, and at least 31.25% dense, and the
922 // target supports indirect branches, then emit a jump table rather than
923 // lowering the switch to a binary tree of conditional branches.
924 if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) &&
926 uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue();
927 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getRawValue();
928 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
930 if (Density >= 0.3125) {
931 // Create a new basic block to hold the code for loading the address
932 // of the jump table, and jumping to it. Update successor information;
933 // we will either branch to the default case for the switch, or the jump
935 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
936 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
937 CurMBB->addSuccessor(Default);
938 CurMBB->addSuccessor(JumpTableBB);
940 // Subtract the lowest switch case value from the value being switched on
941 // and conditional branch to default mbb if the result is greater than the
942 // difference between smallest and largest cases.
943 SDOperand SwitchOp = getValue(SV);
944 MVT::ValueType VT = SwitchOp.getValueType();
945 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
946 DAG.getConstant(First, VT));
948 // The SDNode we just created, which holds the value being switched on
949 // minus the the smallest case value, needs to be copied to a virtual
950 // register so it can be used as an index into the jump table in a
951 // subsequent basic block. This value may be smaller or larger than the
952 // target's pointer type, and therefore require extension or truncating.
953 if (VT > TLI.getPointerTy())
954 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
956 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
957 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
958 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
960 // Emit the range check for the jump table, and branch to the default
961 // block for the switch statement if the value being switched on exceeds
962 // the largest case in the switch.
963 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
964 DAG.getConstant(Last-First,VT), ISD::SETUGT);
965 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
966 DAG.getBasicBlock(Default)));
968 // Build a vector of destination BBs, corresponding to each target
969 // of the jump table. If the value of the jump table slot corresponds to
970 // a case statement, push the case's BB onto the vector, otherwise, push
972 std::vector<MachineBasicBlock*> DestBBs;
973 uint64_t TEI = First;
974 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) {
975 if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) {
976 DestBBs.push_back(ii->second);
979 DestBBs.push_back(Default);
983 // Update successor info
984 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
985 E = DestBBs.end(); I != E; ++I)
986 JumpTableBB->addSuccessor(*I);
988 // Create a jump table index for this jump table, or return an existing
990 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
992 // Set the jump table information so that we can codegen it as a second
994 JT.Reg = JumpTableReg;
996 JT.MBB = JumpTableBB;
997 JT.Default = Default;
1002 // Push the initial CaseRec onto the worklist
1003 std::vector<CaseRec> CaseVec;
1004 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1006 while (!CaseVec.empty()) {
1007 // Grab a record representing a case range to process off the worklist
1008 CaseRec CR = CaseVec.back();
1011 // Size is the number of Cases represented by this range. If Size is 1,
1012 // then we are processing a leaf of the binary search tree. Otherwise,
1013 // we need to pick a pivot, and push left and right ranges onto the
1015 unsigned Size = CR.Range.second - CR.Range.first;
1018 // Create a CaseBlock record representing a conditional branch to
1019 // the Case's target mbb if the value being switched on SV is equal
1020 // to C. Otherwise, branch to default.
1021 Constant *C = CR.Range.first->first;
1022 MachineBasicBlock *Target = CR.Range.first->second;
1023 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1025 // If the MBB representing the leaf node is the current MBB, then just
1026 // call visitSwitchCase to emit the code into the current block.
1027 // Otherwise, push the CaseBlock onto the vector to be later processed
1028 // by SDISel, and insert the node's MBB before the next MBB.
1029 if (CR.CaseBB == CurMBB)
1030 visitSwitchCase(CB);
1032 SwitchCases.push_back(CB);
1033 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1036 // split case range at pivot
1037 CaseItr Pivot = CR.Range.first + (Size / 2);
1038 CaseRange LHSR(CR.Range.first, Pivot);
1039 CaseRange RHSR(Pivot, CR.Range.second);
1040 Constant *C = Pivot->first;
1041 MachineBasicBlock *RHSBB = 0, *LHSBB = 0;
1042 // We know that we branch to the LHS if the Value being switched on is
1043 // less than the Pivot value, C. We use this to optimize our binary
1044 // tree a bit, by recognizing that if SV is greater than or equal to the
1045 // LHS's Case Value, and that Case Value is exactly one less than the
1046 // Pivot's Value, then we can branch directly to the LHS's Target,
1047 // rather than creating a leaf node for it.
1048 if ((LHSR.second - LHSR.first) == 1 &&
1049 LHSR.first->first == CR.GE &&
1050 cast<ConstantIntegral>(C)->getRawValue() ==
1051 (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) {
1052 LHSBB = LHSR.first->second;
1054 LHSBB = new MachineBasicBlock(LLVMBB);
1055 CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR));
1057 // Similar to the optimization above, if the Value being switched on is
1058 // known to be less than the Constant CR.LT, and the current Case Value
1059 // is CR.LT - 1, then we can branch directly to the target block for
1060 // the current Case Value, rather than emitting a RHS leaf node for it.
1061 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1062 cast<ConstantIntegral>(RHSR.first->first)->getRawValue() ==
1063 (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) {
1064 RHSBB = RHSR.first->second;
1066 RHSBB = new MachineBasicBlock(LLVMBB);
1067 CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR));
1069 // Create a CaseBlock record representing a conditional branch to
1070 // the LHS node if the value being switched on SV is less than C.
1071 // Otherwise, branch to LHS.
1072 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
1073 SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB);
1074 if (CR.CaseBB == CurMBB)
1075 visitSwitchCase(CB);
1077 SwitchCases.push_back(CB);
1078 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1084 void SelectionDAGLowering::visitSub(User &I) {
1085 // -0.0 - X --> fneg
1086 if (I.getType()->isFloatingPoint()) {
1087 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1088 if (CFP->isExactlyValue(-0.0)) {
1089 SDOperand Op2 = getValue(I.getOperand(1));
1090 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1094 visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
1097 void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
1099 const Type *Ty = I.getType();
1100 SDOperand Op1 = getValue(I.getOperand(0));
1101 SDOperand Op2 = getValue(I.getOperand(1));
1103 if (Ty->isIntegral()) {
1104 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
1105 } else if (Ty->isFloatingPoint()) {
1106 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
1108 const PackedType *PTy = cast<PackedType>(Ty);
1109 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1110 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1111 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1115 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1116 SDOperand Op1 = getValue(I.getOperand(0));
1117 SDOperand Op2 = getValue(I.getOperand(1));
1119 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1121 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1124 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
1125 ISD::CondCode UnsignedOpcode,
1126 ISD::CondCode FPOpcode) {
1127 SDOperand Op1 = getValue(I.getOperand(0));
1128 SDOperand Op2 = getValue(I.getOperand(1));
1129 ISD::CondCode Opcode = SignedOpcode;
1130 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint())
1132 else if (I.getOperand(0)->getType()->isUnsigned())
1133 Opcode = UnsignedOpcode;
1134 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1137 void SelectionDAGLowering::visitSelect(User &I) {
1138 SDOperand Cond = getValue(I.getOperand(0));
1139 SDOperand TrueVal = getValue(I.getOperand(1));
1140 SDOperand FalseVal = getValue(I.getOperand(2));
1141 if (!isa<PackedType>(I.getType())) {
1142 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1143 TrueVal, FalseVal));
1145 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1146 *(TrueVal.Val->op_end()-2),
1147 *(TrueVal.Val->op_end()-1)));
1151 void SelectionDAGLowering::visitCast(User &I) {
1152 SDOperand N = getValue(I.getOperand(0));
1153 MVT::ValueType SrcVT = N.getValueType();
1154 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1156 if (DestVT == MVT::Vector) {
1157 // This is a cast to a vector from something else. This is always a bit
1158 // convert. Get information about the input vector.
1159 const PackedType *DestTy = cast<PackedType>(I.getType());
1160 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1161 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1162 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1163 DAG.getValueType(EltVT)));
1164 } else if (SrcVT == DestVT) {
1165 setValue(&I, N); // noop cast.
1166 } else if (DestVT == MVT::i1) {
1167 // Cast to bool is a comparison against zero, not truncation to zero.
1168 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
1169 DAG.getConstantFP(0.0, N.getValueType());
1170 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
1171 } else if (isInteger(SrcVT)) {
1172 if (isInteger(DestVT)) { // Int -> Int cast
1173 if (DestVT < SrcVT) // Truncating cast?
1174 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1175 else if (I.getOperand(0)->getType()->isSigned())
1176 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1178 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1179 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast
1180 if (I.getOperand(0)->getType()->isSigned())
1181 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1183 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1185 assert(0 && "Unknown cast!");
1187 } else if (isFloatingPoint(SrcVT)) {
1188 if (isFloatingPoint(DestVT)) { // FP -> FP cast
1189 if (DestVT < SrcVT) // Rounding cast?
1190 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1192 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1193 } else if (isInteger(DestVT)) { // FP -> Int cast.
1194 if (I.getType()->isSigned())
1195 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1197 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1199 assert(0 && "Unknown cast!");
1202 assert(SrcVT == MVT::Vector && "Unknown cast!");
1203 assert(DestVT != MVT::Vector && "Casts to vector already handled!");
1204 // This is a cast from a vector to something else. This is always a bit
1205 // convert. Get information about the input vector.
1206 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1210 void SelectionDAGLowering::visitInsertElement(User &I) {
1211 SDOperand InVec = getValue(I.getOperand(0));
1212 SDOperand InVal = getValue(I.getOperand(1));
1213 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1214 getValue(I.getOperand(2)));
1216 SDOperand Num = *(InVec.Val->op_end()-2);
1217 SDOperand Typ = *(InVec.Val->op_end()-1);
1218 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1219 InVec, InVal, InIdx, Num, Typ));
1222 void SelectionDAGLowering::visitExtractElement(User &I) {
1223 SDOperand InVec = getValue(I.getOperand(0));
1224 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1225 getValue(I.getOperand(1)));
1226 SDOperand Typ = *(InVec.Val->op_end()-1);
1227 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1228 TLI.getValueType(I.getType()), InVec, InIdx));
1231 void SelectionDAGLowering::visitShuffleVector(User &I) {
1232 SDOperand V1 = getValue(I.getOperand(0));
1233 SDOperand V2 = getValue(I.getOperand(1));
1234 SDOperand Mask = getValue(I.getOperand(2));
1236 SDOperand Num = *(V1.Val->op_end()-2);
1237 SDOperand Typ = *(V2.Val->op_end()-1);
1238 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1239 V1, V2, Mask, Num, Typ));
1243 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1244 SDOperand N = getValue(I.getOperand(0));
1245 const Type *Ty = I.getOperand(0)->getType();
1247 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1250 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1251 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
1254 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
1255 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1256 getIntPtrConstant(Offset));
1258 Ty = StTy->getElementType(Field);
1260 Ty = cast<SequentialType>(Ty)->getElementType();
1262 // If this is a constant subscript, handle it quickly.
1263 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1264 if (CI->getRawValue() == 0) continue;
1267 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
1268 Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
1270 Offs = TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
1271 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1275 // N = N + Idx * ElementSize;
1276 uint64_t ElementSize = TD->getTypeSize(Ty);
1277 SDOperand IdxN = getValue(Idx);
1279 // If the index is smaller or larger than intptr_t, truncate or extend
1281 if (IdxN.getValueType() < N.getValueType()) {
1282 if (Idx->getType()->isSigned())
1283 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1285 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
1286 } else if (IdxN.getValueType() > N.getValueType())
1287 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1289 // If this is a multiply by a power of two, turn it into a shl
1290 // immediately. This is a very common case.
1291 if (isPowerOf2_64(ElementSize)) {
1292 unsigned Amt = Log2_64(ElementSize);
1293 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1294 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1295 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1299 SDOperand Scale = getIntPtrConstant(ElementSize);
1300 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1301 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1307 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1308 // If this is a fixed sized alloca in the entry block of the function,
1309 // allocate it statically on the stack.
1310 if (FuncInfo.StaticAllocaMap.count(&I))
1311 return; // getValue will auto-populate this.
1313 const Type *Ty = I.getAllocatedType();
1314 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1315 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
1318 SDOperand AllocSize = getValue(I.getArraySize());
1319 MVT::ValueType IntPtr = TLI.getPointerTy();
1320 if (IntPtr < AllocSize.getValueType())
1321 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1322 else if (IntPtr > AllocSize.getValueType())
1323 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1325 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1326 getIntPtrConstant(TySize));
1328 // Handle alignment. If the requested alignment is less than or equal to the
1329 // stack alignment, ignore it and round the size of the allocation up to the
1330 // stack alignment size. If the size is greater than the stack alignment, we
1331 // note this in the DYNAMIC_STACKALLOC node.
1332 unsigned StackAlign =
1333 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1334 if (Align <= StackAlign) {
1336 // Add SA-1 to the size.
1337 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1338 getIntPtrConstant(StackAlign-1));
1339 // Mask out the low bits for alignment purposes.
1340 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1341 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1344 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
1345 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
1347 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
1348 DAG.setRoot(setValue(&I, DSA).getValue(1));
1350 // Inform the Frame Information that we have just allocated a variable-sized
1352 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1355 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1356 SDOperand Ptr = getValue(I.getOperand(0));
1362 // Do not serialize non-volatile loads against each other.
1363 Root = DAG.getRoot();
1366 setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)),
1367 Root, I.isVolatile()));
1370 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1371 SDOperand SrcValue, SDOperand Root,
1374 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1375 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1376 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue);
1378 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue);
1382 DAG.setRoot(L.getValue(1));
1384 PendingLoads.push_back(L.getValue(1));
1390 void SelectionDAGLowering::visitStore(StoreInst &I) {
1391 Value *SrcV = I.getOperand(0);
1392 SDOperand Src = getValue(SrcV);
1393 SDOperand Ptr = getValue(I.getOperand(1));
1394 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
1395 DAG.getSrcValue(I.getOperand(1))));
1398 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1399 /// access memory and has no other side effects at all.
1400 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1401 #define GET_NO_MEMORY_INTRINSICS
1402 #include "llvm/Intrinsics.gen"
1403 #undef GET_NO_MEMORY_INTRINSICS
1407 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1408 // have any side-effects or if it only reads memory.
1409 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1410 #define GET_SIDE_EFFECT_INFO
1411 #include "llvm/Intrinsics.gen"
1412 #undef GET_SIDE_EFFECT_INFO
1416 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1418 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1419 unsigned Intrinsic) {
1420 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1421 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1423 // Build the operand list.
1424 SmallVector<SDOperand, 8> Ops;
1425 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1427 // We don't need to serialize loads against other loads.
1428 Ops.push_back(DAG.getRoot());
1430 Ops.push_back(getRoot());
1434 // Add the intrinsic ID as an integer operand.
1435 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1437 // Add all operands of the call to the operand list.
1438 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1439 SDOperand Op = getValue(I.getOperand(i));
1441 // If this is a vector type, force it to the right packed type.
1442 if (Op.getValueType() == MVT::Vector) {
1443 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1444 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1446 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1447 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1448 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1451 assert(TLI.isTypeLegal(Op.getValueType()) &&
1452 "Intrinsic uses a non-legal type?");
1456 std::vector<MVT::ValueType> VTs;
1457 if (I.getType() != Type::VoidTy) {
1458 MVT::ValueType VT = TLI.getValueType(I.getType());
1459 if (VT == MVT::Vector) {
1460 const PackedType *DestTy = cast<PackedType>(I.getType());
1461 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1463 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1464 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1467 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1471 VTs.push_back(MVT::Other);
1473 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
1478 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
1479 &Ops[0], Ops.size());
1480 else if (I.getType() != Type::VoidTy)
1481 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
1482 &Ops[0], Ops.size());
1484 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
1485 &Ops[0], Ops.size());
1488 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1490 PendingLoads.push_back(Chain);
1494 if (I.getType() != Type::VoidTy) {
1495 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1496 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1497 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1498 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1499 DAG.getValueType(EVT));
1501 setValue(&I, Result);
1505 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1506 /// we want to emit this as a call to a named external function, return the name
1507 /// otherwise lower it and return null.
1509 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1510 switch (Intrinsic) {
1512 // By default, turn this into a target intrinsic node.
1513 visitTargetIntrinsic(I, Intrinsic);
1515 case Intrinsic::vastart: visitVAStart(I); return 0;
1516 case Intrinsic::vaend: visitVAEnd(I); return 0;
1517 case Intrinsic::vacopy: visitVACopy(I); return 0;
1518 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1519 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1520 case Intrinsic::setjmp:
1521 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1523 case Intrinsic::longjmp:
1524 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1526 case Intrinsic::memcpy_i32:
1527 case Intrinsic::memcpy_i64:
1528 visitMemIntrinsic(I, ISD::MEMCPY);
1530 case Intrinsic::memset_i32:
1531 case Intrinsic::memset_i64:
1532 visitMemIntrinsic(I, ISD::MEMSET);
1534 case Intrinsic::memmove_i32:
1535 case Intrinsic::memmove_i64:
1536 visitMemIntrinsic(I, ISD::MEMMOVE);
1539 case Intrinsic::dbg_stoppoint: {
1540 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1541 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1542 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
1546 Ops[1] = getValue(SPI.getLineValue());
1547 Ops[2] = getValue(SPI.getColumnValue());
1549 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
1550 assert(DD && "Not a debug information descriptor");
1551 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1553 Ops[3] = DAG.getString(CompileUnit->getFileName());
1554 Ops[4] = DAG.getString(CompileUnit->getDirectory());
1556 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
1561 case Intrinsic::dbg_region_start: {
1562 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1563 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1564 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
1565 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
1566 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
1567 DAG.getConstant(LabelID, MVT::i32)));
1572 case Intrinsic::dbg_region_end: {
1573 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1574 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
1575 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
1576 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
1577 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
1578 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
1583 case Intrinsic::dbg_func_start: {
1584 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1585 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
1586 if (DebugInfo && FSI.getSubprogram() &&
1587 DebugInfo->Verify(FSI.getSubprogram())) {
1588 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
1589 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
1590 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
1595 case Intrinsic::dbg_declare: {
1596 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1597 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
1598 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
1599 SDOperand AddressOp = getValue(DI.getAddress());
1600 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
1601 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
1607 case Intrinsic::isunordered_f32:
1608 case Intrinsic::isunordered_f64:
1609 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
1610 getValue(I.getOperand(2)), ISD::SETUO));
1613 case Intrinsic::sqrt_f32:
1614 case Intrinsic::sqrt_f64:
1615 setValue(&I, DAG.getNode(ISD::FSQRT,
1616 getValue(I.getOperand(1)).getValueType(),
1617 getValue(I.getOperand(1))));
1619 case Intrinsic::powi_f32:
1620 case Intrinsic::powi_f64:
1621 setValue(&I, DAG.getNode(ISD::FPOWI,
1622 getValue(I.getOperand(1)).getValueType(),
1623 getValue(I.getOperand(1)),
1624 getValue(I.getOperand(2))));
1626 case Intrinsic::pcmarker: {
1627 SDOperand Tmp = getValue(I.getOperand(1));
1628 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
1631 case Intrinsic::readcyclecounter: {
1632 SDOperand Op = getRoot();
1633 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
1634 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
1637 DAG.setRoot(Tmp.getValue(1));
1640 case Intrinsic::bswap_i16:
1641 case Intrinsic::bswap_i32:
1642 case Intrinsic::bswap_i64:
1643 setValue(&I, DAG.getNode(ISD::BSWAP,
1644 getValue(I.getOperand(1)).getValueType(),
1645 getValue(I.getOperand(1))));
1647 case Intrinsic::cttz_i8:
1648 case Intrinsic::cttz_i16:
1649 case Intrinsic::cttz_i32:
1650 case Intrinsic::cttz_i64:
1651 setValue(&I, DAG.getNode(ISD::CTTZ,
1652 getValue(I.getOperand(1)).getValueType(),
1653 getValue(I.getOperand(1))));
1655 case Intrinsic::ctlz_i8:
1656 case Intrinsic::ctlz_i16:
1657 case Intrinsic::ctlz_i32:
1658 case Intrinsic::ctlz_i64:
1659 setValue(&I, DAG.getNode(ISD::CTLZ,
1660 getValue(I.getOperand(1)).getValueType(),
1661 getValue(I.getOperand(1))));
1663 case Intrinsic::ctpop_i8:
1664 case Intrinsic::ctpop_i16:
1665 case Intrinsic::ctpop_i32:
1666 case Intrinsic::ctpop_i64:
1667 setValue(&I, DAG.getNode(ISD::CTPOP,
1668 getValue(I.getOperand(1)).getValueType(),
1669 getValue(I.getOperand(1))));
1671 case Intrinsic::stacksave: {
1672 SDOperand Op = getRoot();
1673 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
1674 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
1676 DAG.setRoot(Tmp.getValue(1));
1679 case Intrinsic::stackrestore: {
1680 SDOperand Tmp = getValue(I.getOperand(1));
1681 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
1684 case Intrinsic::prefetch:
1685 // FIXME: Currently discarding prefetches.
1691 void SelectionDAGLowering::visitCall(CallInst &I) {
1692 const char *RenameFn = 0;
1693 if (Function *F = I.getCalledFunction()) {
1694 if (F->isExternal())
1695 if (unsigned IID = F->getIntrinsicID()) {
1696 RenameFn = visitIntrinsicCall(I, IID);
1699 } else { // Not an LLVM intrinsic.
1700 const std::string &Name = F->getName();
1701 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
1702 if (I.getNumOperands() == 3 && // Basic sanity checks.
1703 I.getOperand(1)->getType()->isFloatingPoint() &&
1704 I.getType() == I.getOperand(1)->getType() &&
1705 I.getType() == I.getOperand(2)->getType()) {
1706 SDOperand LHS = getValue(I.getOperand(1));
1707 SDOperand RHS = getValue(I.getOperand(2));
1708 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
1712 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
1713 if (I.getNumOperands() == 2 && // Basic sanity checks.
1714 I.getOperand(1)->getType()->isFloatingPoint() &&
1715 I.getType() == I.getOperand(1)->getType()) {
1716 SDOperand Tmp = getValue(I.getOperand(1));
1717 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
1720 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
1721 if (I.getNumOperands() == 2 && // Basic sanity checks.
1722 I.getOperand(1)->getType()->isFloatingPoint() &&
1723 I.getType() == I.getOperand(1)->getType()) {
1724 SDOperand Tmp = getValue(I.getOperand(1));
1725 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
1728 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
1729 if (I.getNumOperands() == 2 && // Basic sanity checks.
1730 I.getOperand(1)->getType()->isFloatingPoint() &&
1731 I.getType() == I.getOperand(1)->getType()) {
1732 SDOperand Tmp = getValue(I.getOperand(1));
1733 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
1738 } else if (isa<InlineAsm>(I.getOperand(0))) {
1745 Callee = getValue(I.getOperand(0));
1747 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
1748 std::vector<std::pair<SDOperand, const Type*> > Args;
1749 Args.reserve(I.getNumOperands());
1750 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1751 Value *Arg = I.getOperand(i);
1752 SDOperand ArgNode = getValue(Arg);
1753 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
1756 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
1757 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1759 std::pair<SDOperand,SDOperand> Result =
1760 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
1761 I.isTailCall(), Callee, Args, DAG);
1762 if (I.getType() != Type::VoidTy)
1763 setValue(&I, Result.first);
1764 DAG.setRoot(Result.second);
1767 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
1768 SDOperand &Chain, SDOperand &Flag)const{
1769 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
1770 Chain = Val.getValue(1);
1771 Flag = Val.getValue(2);
1773 // If the result was expanded, copy from the top part.
1774 if (Regs.size() > 1) {
1775 assert(Regs.size() == 2 &&
1776 "Cannot expand to more than 2 elts yet!");
1777 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
1778 Chain = Val.getValue(1);
1779 Flag = Val.getValue(2);
1780 if (DAG.getTargetLoweringInfo().isLittleEndian())
1781 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
1783 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
1786 // Otherwise, if the return value was promoted or extended, truncate it to the
1787 // appropriate type.
1788 if (RegVT == ValueVT)
1791 if (MVT::isInteger(RegVT)) {
1792 if (ValueVT < RegVT)
1793 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1795 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
1797 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
1801 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
1802 /// specified value into the registers specified by this object. This uses
1803 /// Chain/Flag as the input and updates them for the output Chain/Flag.
1804 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
1805 SDOperand &Chain, SDOperand &Flag,
1806 MVT::ValueType PtrVT) const {
1807 if (Regs.size() == 1) {
1808 // If there is a single register and the types differ, this must be
1810 if (RegVT != ValueVT) {
1811 if (MVT::isInteger(RegVT)) {
1812 if (RegVT < ValueVT)
1813 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
1815 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
1817 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
1819 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
1820 Flag = Chain.getValue(1);
1822 std::vector<unsigned> R(Regs);
1823 if (!DAG.getTargetLoweringInfo().isLittleEndian())
1824 std::reverse(R.begin(), R.end());
1826 for (unsigned i = 0, e = R.size(); i != e; ++i) {
1827 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
1828 DAG.getConstant(i, PtrVT));
1829 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
1830 Flag = Chain.getValue(1);
1835 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
1836 /// operand list. This adds the code marker and includes the number of
1837 /// values added into it.
1838 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
1839 std::vector<SDOperand> &Ops) const {
1840 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
1841 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1842 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
1845 /// isAllocatableRegister - If the specified register is safe to allocate,
1846 /// i.e. it isn't a stack pointer or some other special register, return the
1847 /// register class for the register. Otherwise, return null.
1848 static const TargetRegisterClass *
1849 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
1850 const TargetLowering &TLI, const MRegisterInfo *MRI) {
1851 MVT::ValueType FoundVT = MVT::Other;
1852 const TargetRegisterClass *FoundRC = 0;
1853 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
1854 E = MRI->regclass_end(); RCI != E; ++RCI) {
1855 MVT::ValueType ThisVT = MVT::Other;
1857 const TargetRegisterClass *RC = *RCI;
1858 // If none of the the value types for this register class are valid, we
1859 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1860 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1862 if (TLI.isTypeLegal(*I)) {
1863 // If we have already found this register in a different register class,
1864 // choose the one with the largest VT specified. For example, on
1865 // PowerPC, we favor f64 register classes over f32.
1866 if (FoundVT == MVT::Other ||
1867 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
1874 if (ThisVT == MVT::Other) continue;
1876 // NOTE: This isn't ideal. In particular, this might allocate the
1877 // frame pointer in functions that need it (due to them not being taken
1878 // out of allocation, because a variable sized allocation hasn't been seen
1879 // yet). This is a slight code pessimization, but should still work.
1880 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
1881 E = RC->allocation_order_end(MF); I != E; ++I)
1883 // We found a matching register class. Keep looking at others in case
1884 // we find one with larger registers that this physreg is also in.
1893 RegsForValue SelectionDAGLowering::
1894 GetRegistersForValue(const std::string &ConstrCode,
1895 MVT::ValueType VT, bool isOutReg, bool isInReg,
1896 std::set<unsigned> &OutputRegs,
1897 std::set<unsigned> &InputRegs) {
1898 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
1899 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
1900 std::vector<unsigned> Regs;
1902 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
1903 MVT::ValueType RegVT;
1904 MVT::ValueType ValueVT = VT;
1906 if (PhysReg.first) {
1907 if (VT == MVT::Other)
1908 ValueVT = *PhysReg.second->vt_begin();
1910 // Get the actual register value type. This is important, because the user
1911 // may have asked for (e.g.) the AX register in i32 type. We need to
1912 // remember that AX is actually i16 to get the right extension.
1913 RegVT = *PhysReg.second->vt_begin();
1915 // This is a explicit reference to a physical register.
1916 Regs.push_back(PhysReg.first);
1918 // If this is an expanded reference, add the rest of the regs to Regs.
1920 TargetRegisterClass::iterator I = PhysReg.second->begin();
1921 TargetRegisterClass::iterator E = PhysReg.second->end();
1922 for (; *I != PhysReg.first; ++I)
1923 assert(I != E && "Didn't find reg!");
1925 // Already added the first reg.
1927 for (; NumRegs; --NumRegs, ++I) {
1928 assert(I != E && "Ran out of registers to allocate!");
1932 return RegsForValue(Regs, RegVT, ValueVT);
1935 // This is a reference to a register class. Allocate NumRegs consecutive,
1936 // available, registers from the class.
1937 std::vector<unsigned> RegClassRegs =
1938 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
1940 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
1941 MachineFunction &MF = *CurMBB->getParent();
1942 unsigned NumAllocated = 0;
1943 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
1944 unsigned Reg = RegClassRegs[i];
1945 // See if this register is available.
1946 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
1947 (isInReg && InputRegs.count(Reg))) { // Already used.
1948 // Make sure we find consecutive registers.
1953 // Check to see if this register is allocatable (i.e. don't give out the
1955 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
1957 // Make sure we find consecutive registers.
1962 // Okay, this register is good, we can use it.
1965 // If we allocated enough consecutive
1966 if (NumAllocated == NumRegs) {
1967 unsigned RegStart = (i-NumAllocated)+1;
1968 unsigned RegEnd = i+1;
1969 // Mark all of the allocated registers used.
1970 for (unsigned i = RegStart; i != RegEnd; ++i) {
1971 unsigned Reg = RegClassRegs[i];
1972 Regs.push_back(Reg);
1973 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
1974 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
1977 return RegsForValue(Regs, *RC->vt_begin(), VT);
1981 // Otherwise, we couldn't allocate enough registers for this.
1982 return RegsForValue();
1986 /// visitInlineAsm - Handle a call to an InlineAsm object.
1988 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
1989 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
1991 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
1994 // Note, we treat inline asms both with and without side-effects as the same.
1995 // If an inline asm doesn't have side effects and doesn't access memory, we
1996 // could not choose to not chain it.
1997 bool hasSideEffects = IA->hasSideEffects();
1999 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
2000 std::vector<MVT::ValueType> ConstraintVTs;
2002 /// AsmNodeOperands - A list of pairs. The first element is a register, the
2003 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
2004 /// if it is a def of that register.
2005 std::vector<SDOperand> AsmNodeOperands;
2006 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
2007 AsmNodeOperands.push_back(AsmStr);
2009 SDOperand Chain = getRoot();
2012 // We fully assign registers here at isel time. This is not optimal, but
2013 // should work. For register classes that correspond to LLVM classes, we
2014 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
2015 // over the constraints, collecting fixed registers that we know we can't use.
2016 std::set<unsigned> OutputRegs, InputRegs;
2018 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2019 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2020 std::string &ConstraintCode = Constraints[i].Codes[0];
2022 MVT::ValueType OpVT;
2024 // Compute the value type for each operand and add it to ConstraintVTs.
2025 switch (Constraints[i].Type) {
2026 case InlineAsm::isOutput:
2027 if (!Constraints[i].isIndirectOutput) {
2028 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2029 OpVT = TLI.getValueType(I.getType());
2031 const Type *OpTy = I.getOperand(OpNum)->getType();
2032 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2033 OpNum++; // Consumes a call operand.
2036 case InlineAsm::isInput:
2037 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2038 OpNum++; // Consumes a call operand.
2040 case InlineAsm::isClobber:
2045 ConstraintVTs.push_back(OpVT);
2047 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2048 continue; // Not assigned a fixed reg.
2050 // Build a list of regs that this operand uses. This always has a single
2051 // element for promoted/expanded operands.
2052 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2054 OutputRegs, InputRegs);
2056 switch (Constraints[i].Type) {
2057 case InlineAsm::isOutput:
2058 // We can't assign any other output to this register.
2059 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2060 // If this is an early-clobber output, it cannot be assigned to the same
2061 // value as the input reg.
2062 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2063 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2065 case InlineAsm::isInput:
2066 // We can't assign any other input to this register.
2067 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2069 case InlineAsm::isClobber:
2070 // Clobbered regs cannot be used as inputs or outputs.
2071 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2072 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2077 // Loop over all of the inputs, copying the operand values into the
2078 // appropriate registers and processing the output regs.
2079 RegsForValue RetValRegs;
2080 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2083 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2084 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2085 std::string &ConstraintCode = Constraints[i].Codes[0];
2087 switch (Constraints[i].Type) {
2088 case InlineAsm::isOutput: {
2089 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2090 if (ConstraintCode.size() == 1) // not a physreg name.
2091 CTy = TLI.getConstraintType(ConstraintCode[0]);
2093 if (CTy == TargetLowering::C_Memory) {
2095 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2097 // Check that the operand (the address to store to) isn't a float.
2098 if (!MVT::isInteger(InOperandVal.getValueType()))
2099 assert(0 && "MATCH FAIL!");
2101 if (!Constraints[i].isIndirectOutput)
2102 assert(0 && "MATCH FAIL!");
2104 OpNum++; // Consumes a call operand.
2106 // Extend/truncate to the right pointer type if needed.
2107 MVT::ValueType PtrType = TLI.getPointerTy();
2108 if (InOperandVal.getValueType() < PtrType)
2109 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2110 else if (InOperandVal.getValueType() > PtrType)
2111 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2113 // Add information to the INLINEASM node to know about this output.
2114 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2115 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2116 AsmNodeOperands.push_back(InOperandVal);
2120 // Otherwise, this is a register output.
2121 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2123 // If this is an early-clobber output, or if there is an input
2124 // constraint that matches this, we need to reserve the input register
2125 // so no other inputs allocate to it.
2126 bool UsesInputRegister = false;
2127 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2128 UsesInputRegister = true;
2130 // Copy the output from the appropriate register. Find a register that
2133 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2134 true, UsesInputRegister,
2135 OutputRegs, InputRegs);
2136 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
2138 if (!Constraints[i].isIndirectOutput) {
2139 assert(RetValRegs.Regs.empty() &&
2140 "Cannot have multiple output constraints yet!");
2141 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2144 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2145 I.getOperand(OpNum)));
2146 OpNum++; // Consumes a call operand.
2149 // Add information to the INLINEASM node to know that this register is
2151 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2154 case InlineAsm::isInput: {
2155 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2156 OpNum++; // Consumes a call operand.
2158 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2159 // If this is required to match an output register we have already set,
2160 // just use its register.
2161 unsigned OperandNo = atoi(ConstraintCode.c_str());
2163 // Scan until we find the definition we already emitted of this operand.
2164 // When we find it, create a RegsForValue operand.
2165 unsigned CurOp = 2; // The first operand.
2166 for (; OperandNo; --OperandNo) {
2167 // Advance to the next operand.
2169 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2170 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
2171 (NumOps & 7) == 4 /*MEM*/) &&
2172 "Skipped past definitions?");
2173 CurOp += (NumOps>>3)+1;
2177 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2178 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2179 "Skipped past definitions?");
2181 // Add NumOps>>3 registers to MatchedRegs.
2182 RegsForValue MatchedRegs;
2183 MatchedRegs.ValueVT = InOperandVal.getValueType();
2184 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2185 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2186 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2187 MatchedRegs.Regs.push_back(Reg);
2190 // Use the produced MatchedRegs object to
2191 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag,
2192 TLI.getPointerTy());
2193 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2197 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2198 if (ConstraintCode.size() == 1) // not a physreg name.
2199 CTy = TLI.getConstraintType(ConstraintCode[0]);
2201 if (CTy == TargetLowering::C_Other) {
2202 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
2203 assert(0 && "MATCH FAIL!");
2205 // Add information to the INLINEASM node to know about this input.
2206 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2207 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2208 AsmNodeOperands.push_back(InOperandVal);
2210 } else if (CTy == TargetLowering::C_Memory) {
2213 // Check that the operand isn't a float.
2214 if (!MVT::isInteger(InOperandVal.getValueType()))
2215 assert(0 && "MATCH FAIL!");
2217 // Extend/truncate to the right pointer type if needed.
2218 MVT::ValueType PtrType = TLI.getPointerTy();
2219 if (InOperandVal.getValueType() < PtrType)
2220 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2221 else if (InOperandVal.getValueType() > PtrType)
2222 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2224 // Add information to the INLINEASM node to know about this input.
2225 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2226 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2227 AsmNodeOperands.push_back(InOperandVal);
2231 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2233 // Copy the input into the appropriate registers.
2234 RegsForValue InRegs =
2235 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2236 false, true, OutputRegs, InputRegs);
2237 // FIXME: should be match fail.
2238 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2240 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy());
2242 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2245 case InlineAsm::isClobber: {
2246 RegsForValue ClobberedRegs =
2247 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2248 OutputRegs, InputRegs);
2249 // Add the clobbered value to the operand list, so that the register
2250 // allocator is aware that the physreg got clobbered.
2251 if (!ClobberedRegs.Regs.empty())
2252 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2258 // Finish up input operands.
2259 AsmNodeOperands[0] = Chain;
2260 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2262 Chain = DAG.getNode(ISD::INLINEASM,
2263 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
2264 &AsmNodeOperands[0], AsmNodeOperands.size());
2265 Flag = Chain.getValue(1);
2267 // If this asm returns a register value, copy the result from that register
2268 // and set it as the value of the call.
2269 if (!RetValRegs.Regs.empty())
2270 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2272 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2274 // Process indirect outputs, first output all of the flagged copies out of
2276 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2277 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2278 Value *Ptr = IndirectStoresToEmit[i].second;
2279 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2280 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2283 // Emit the non-flagged stores from the physregs.
2284 SmallVector<SDOperand, 8> OutChains;
2285 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2286 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
2287 StoresToEmit[i].first,
2288 getValue(StoresToEmit[i].second),
2289 DAG.getSrcValue(StoresToEmit[i].second)));
2290 if (!OutChains.empty())
2291 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2292 &OutChains[0], OutChains.size());
2297 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2298 SDOperand Src = getValue(I.getOperand(0));
2300 MVT::ValueType IntPtr = TLI.getPointerTy();
2302 if (IntPtr < Src.getValueType())
2303 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2304 else if (IntPtr > Src.getValueType())
2305 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2307 // Scale the source by the type size.
2308 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
2309 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2310 Src, getIntPtrConstant(ElementSize));
2312 std::vector<std::pair<SDOperand, const Type*> > Args;
2313 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType()));
2315 std::pair<SDOperand,SDOperand> Result =
2316 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
2317 DAG.getExternalSymbol("malloc", IntPtr),
2319 setValue(&I, Result.first); // Pointers always fit in registers
2320 DAG.setRoot(Result.second);
2323 void SelectionDAGLowering::visitFree(FreeInst &I) {
2324 std::vector<std::pair<SDOperand, const Type*> > Args;
2325 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
2326 TLI.getTargetData()->getIntPtrType()));
2327 MVT::ValueType IntPtr = TLI.getPointerTy();
2328 std::pair<SDOperand,SDOperand> Result =
2329 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
2330 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2331 DAG.setRoot(Result.second);
2334 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2335 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2336 // instructions are special in various ways, which require special support to
2337 // insert. The specified MachineInstr is created but not inserted into any
2338 // basic blocks, and the scheduler passes ownership of it to this method.
2339 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2340 MachineBasicBlock *MBB) {
2341 std::cerr << "If a target marks an instruction with "
2342 "'usesCustomDAGSchedInserter', it must implement "
2343 "TargetLowering::InsertAtEndOfBasicBlock!\n";
2348 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2349 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2350 getValue(I.getOperand(1)),
2351 DAG.getSrcValue(I.getOperand(1))));
2354 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2355 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2356 getValue(I.getOperand(0)),
2357 DAG.getSrcValue(I.getOperand(0)));
2359 DAG.setRoot(V.getValue(1));
2362 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2363 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2364 getValue(I.getOperand(1)),
2365 DAG.getSrcValue(I.getOperand(1))));
2368 void SelectionDAGLowering::visitVACopy(CallInst &I) {
2369 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2370 getValue(I.getOperand(1)),
2371 getValue(I.getOperand(2)),
2372 DAG.getSrcValue(I.getOperand(1)),
2373 DAG.getSrcValue(I.getOperand(2))));
2376 /// TargetLowering::LowerArguments - This is the default LowerArguments
2377 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
2378 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
2379 /// integrated into SDISel.
2380 std::vector<SDOperand>
2381 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2382 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2383 std::vector<SDOperand> Ops;
2384 Ops.push_back(DAG.getRoot());
2385 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2386 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2388 // Add one result value for each formal argument.
2389 std::vector<MVT::ValueType> RetVals;
2390 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2391 MVT::ValueType VT = getValueType(I->getType());
2393 switch (getTypeAction(VT)) {
2394 default: assert(0 && "Unknown type action!");
2396 RetVals.push_back(VT);
2399 RetVals.push_back(getTypeToTransformTo(VT));
2402 if (VT != MVT::Vector) {
2403 // If this is a large integer, it needs to be broken up into small
2404 // integers. Figure out what the destination type is and how many small
2405 // integers it turns into.
2406 MVT::ValueType NVT = getTypeToTransformTo(VT);
2407 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2408 for (unsigned i = 0; i != NumVals; ++i)
2409 RetVals.push_back(NVT);
2411 // Otherwise, this is a vector type. We only support legal vectors
2413 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2414 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2416 // Figure out if there is a Packed type corresponding to this Vector
2417 // type. If so, convert to the packed type.
2418 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2419 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2420 RetVals.push_back(TVT);
2422 assert(0 && "Don't support illegal by-val vector arguments yet!");
2429 RetVals.push_back(MVT::Other);
2432 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
2433 DAG.getNodeValueTypes(RetVals), RetVals.size(),
2434 &Ops[0], Ops.size()).Val;
2436 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
2438 // Set up the return result vector.
2441 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2442 MVT::ValueType VT = getValueType(I->getType());
2444 switch (getTypeAction(VT)) {
2445 default: assert(0 && "Unknown type action!");
2447 Ops.push_back(SDOperand(Result, i++));
2450 SDOperand Op(Result, i++);
2451 if (MVT::isInteger(VT)) {
2452 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
2454 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
2455 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2457 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2458 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2464 if (VT != MVT::Vector) {
2465 // If this is a large integer, it needs to be reassembled from small
2466 // integers. Figure out what the source elt type is and how many small
2468 MVT::ValueType NVT = getTypeToTransformTo(VT);
2469 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2471 SDOperand Lo = SDOperand(Result, i++);
2472 SDOperand Hi = SDOperand(Result, i++);
2474 if (!isLittleEndian())
2477 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
2479 // Value scalarized into many values. Unimp for now.
2480 assert(0 && "Cannot expand i64 -> i16 yet!");
2483 // Otherwise, this is a vector type. We only support legal vectors
2485 const PackedType *PTy = cast<PackedType>(I->getType());
2486 unsigned NumElems = PTy->getNumElements();
2487 const Type *EltTy = PTy->getElementType();
2489 // Figure out if there is a Packed type corresponding to this Vector
2490 // type. If so, convert to the packed type.
2491 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2492 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2493 SDOperand N = SDOperand(Result, i++);
2494 // Handle copies from generic vectors to registers.
2495 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
2496 DAG.getConstant(NumElems, MVT::i32),
2497 DAG.getValueType(getValueType(EltTy)));
2500 assert(0 && "Don't support illegal by-val vector arguments yet!");
2511 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
2512 /// implementation, which just inserts an ISD::CALL node, which is later custom
2513 /// lowered by the target to something concrete. FIXME: When all targets are
2514 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
2515 std::pair<SDOperand, SDOperand>
2516 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
2517 unsigned CallingConv, bool isTailCall,
2519 ArgListTy &Args, SelectionDAG &DAG) {
2520 SmallVector<SDOperand, 32> Ops;
2521 Ops.push_back(Chain); // Op#0 - Chain
2522 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
2523 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
2524 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
2525 Ops.push_back(Callee);
2527 // Handle all of the outgoing arguments.
2528 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
2529 MVT::ValueType VT = getValueType(Args[i].second);
2530 SDOperand Op = Args[i].first;
2531 bool isSigned = Args[i].second->isSigned();
2532 switch (getTypeAction(VT)) {
2533 default: assert(0 && "Unknown type action!");
2536 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2539 if (MVT::isInteger(VT)) {
2540 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2541 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
2543 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2544 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
2547 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2550 if (VT != MVT::Vector) {
2551 // If this is a large integer, it needs to be broken down into small
2552 // integers. Figure out what the source elt type is and how many small
2554 MVT::ValueType NVT = getTypeToTransformTo(VT);
2555 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2557 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2558 DAG.getConstant(0, getPointerTy()));
2559 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2560 DAG.getConstant(1, getPointerTy()));
2561 if (!isLittleEndian())
2565 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2567 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2569 // Value scalarized into many values. Unimp for now.
2570 assert(0 && "Cannot expand i64 -> i16 yet!");
2573 // Otherwise, this is a vector type. We only support legal vectors
2575 const PackedType *PTy = cast<PackedType>(Args[i].second);
2576 unsigned NumElems = PTy->getNumElements();
2577 const Type *EltTy = PTy->getElementType();
2579 // Figure out if there is a Packed type corresponding to this Vector
2580 // type. If so, convert to the packed type.
2581 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2582 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2583 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
2584 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
2586 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2588 assert(0 && "Don't support illegal by-val vector call args yet!");
2596 // Figure out the result value types.
2597 SmallVector<MVT::ValueType, 4> RetTys;
2599 if (RetTy != Type::VoidTy) {
2600 MVT::ValueType VT = getValueType(RetTy);
2601 switch (getTypeAction(VT)) {
2602 default: assert(0 && "Unknown type action!");
2604 RetTys.push_back(VT);
2607 RetTys.push_back(getTypeToTransformTo(VT));
2610 if (VT != MVT::Vector) {
2611 // If this is a large integer, it needs to be reassembled from small
2612 // integers. Figure out what the source elt type is and how many small
2614 MVT::ValueType NVT = getTypeToTransformTo(VT);
2615 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2616 for (unsigned i = 0; i != NumVals; ++i)
2617 RetTys.push_back(NVT);
2619 // Otherwise, this is a vector type. We only support legal vectors
2621 const PackedType *PTy = cast<PackedType>(RetTy);
2622 unsigned NumElems = PTy->getNumElements();
2623 const Type *EltTy = PTy->getElementType();
2625 // Figure out if there is a Packed type corresponding to this Vector
2626 // type. If so, convert to the packed type.
2627 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2628 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2629 RetTys.push_back(TVT);
2631 assert(0 && "Don't support illegal by-val vector call results yet!");
2638 RetTys.push_back(MVT::Other); // Always has a chain.
2640 // Finally, create the CALL node.
2641 SDOperand Res = DAG.getNode(ISD::CALL,
2642 DAG.getVTList(&RetTys[0], RetTys.size()),
2643 &Ops[0], Ops.size());
2645 // This returns a pair of operands. The first element is the
2646 // return value for the function (if RetTy is not VoidTy). The second
2647 // element is the outgoing token chain.
2649 if (RetTys.size() != 1) {
2650 MVT::ValueType VT = getValueType(RetTy);
2651 if (RetTys.size() == 2) {
2654 // If this value was promoted, truncate it down.
2655 if (ResVal.getValueType() != VT) {
2656 if (VT == MVT::Vector) {
2657 // Insert a VBITCONVERT to convert from the packed result type to the
2658 // MVT::Vector type.
2659 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
2660 const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
2662 // Figure out if there is a Packed type corresponding to this Vector
2663 // type. If so, convert to the packed type.
2664 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2665 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2666 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
2667 // "N x PTyElementVT" MVT::Vector type.
2668 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
2669 DAG.getConstant(NumElems, MVT::i32),
2670 DAG.getValueType(getValueType(EltTy)));
2674 } else if (MVT::isInteger(VT)) {
2675 unsigned AssertOp = RetTy->isSigned() ?
2676 ISD::AssertSext : ISD::AssertZext;
2677 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
2678 DAG.getValueType(VT));
2679 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
2681 assert(MVT::isFloatingPoint(VT));
2682 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
2685 } else if (RetTys.size() == 3) {
2686 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
2687 Res.getValue(0), Res.getValue(1));
2690 assert(0 && "Case not handled yet!");
2694 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
2699 // It is always conservatively correct for llvm.returnaddress and
2700 // llvm.frameaddress to return 0.
2702 // FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
2703 // expanded to 0 if the target wants.
2704 std::pair<SDOperand, SDOperand>
2705 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
2706 unsigned Depth, SelectionDAG &DAG) {
2707 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
2710 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2711 assert(0 && "LowerOperation not implemented for this target!");
2716 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
2717 SelectionDAG &DAG) {
2718 assert(0 && "CustomPromoteOperation not implemented for this target!");
2723 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
2724 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
2725 std::pair<SDOperand,SDOperand> Result =
2726 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
2727 setValue(&I, Result.first);
2728 DAG.setRoot(Result.second);
2731 /// getMemsetValue - Vectorized representation of the memset value
2733 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
2734 SelectionDAG &DAG) {
2735 MVT::ValueType CurVT = VT;
2736 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2737 uint64_t Val = C->getValue() & 255;
2739 while (CurVT != MVT::i8) {
2740 Val = (Val << Shift) | Val;
2742 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2744 return DAG.getConstant(Val, VT);
2746 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
2748 while (CurVT != MVT::i8) {
2750 DAG.getNode(ISD::OR, VT,
2751 DAG.getNode(ISD::SHL, VT, Value,
2752 DAG.getConstant(Shift, MVT::i8)), Value);
2754 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2761 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2762 /// used when a memcpy is turned into a memset when the source is a constant
2764 static SDOperand getMemsetStringVal(MVT::ValueType VT,
2765 SelectionDAG &DAG, TargetLowering &TLI,
2766 std::string &Str, unsigned Offset) {
2767 MVT::ValueType CurVT = VT;
2769 unsigned MSB = getSizeInBits(VT) / 8;
2770 if (TLI.isLittleEndian())
2771 Offset = Offset + MSB - 1;
2772 for (unsigned i = 0; i != MSB; ++i) {
2773 Val = (Val << 8) | Str[Offset];
2774 Offset += TLI.isLittleEndian() ? -1 : 1;
2776 return DAG.getConstant(Val, VT);
2779 /// getMemBasePlusOffset - Returns base and offset node for the
2780 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
2781 SelectionDAG &DAG, TargetLowering &TLI) {
2782 MVT::ValueType VT = Base.getValueType();
2783 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
2786 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
2787 /// to replace the memset / memcpy is below the threshold. It also returns the
2788 /// types of the sequence of memory ops to perform memset / memcpy.
2789 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
2790 unsigned Limit, uint64_t Size,
2791 unsigned Align, TargetLowering &TLI) {
2794 if (TLI.allowsUnalignedMemoryAccesses()) {
2797 switch (Align & 7) {
2813 MVT::ValueType LVT = MVT::i64;
2814 while (!TLI.isTypeLegal(LVT))
2815 LVT = (MVT::ValueType)((unsigned)LVT - 1);
2816 assert(MVT::isInteger(LVT));
2821 unsigned NumMemOps = 0;
2823 unsigned VTSize = getSizeInBits(VT) / 8;
2824 while (VTSize > Size) {
2825 VT = (MVT::ValueType)((unsigned)VT - 1);
2828 assert(MVT::isInteger(VT));
2830 if (++NumMemOps > Limit)
2832 MemOps.push_back(VT);
2839 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
2840 SDOperand Op1 = getValue(I.getOperand(1));
2841 SDOperand Op2 = getValue(I.getOperand(2));
2842 SDOperand Op3 = getValue(I.getOperand(3));
2843 SDOperand Op4 = getValue(I.getOperand(4));
2844 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
2845 if (Align == 0) Align = 1;
2847 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
2848 std::vector<MVT::ValueType> MemOps;
2850 // Expand memset / memcpy to a series of load / store ops
2851 // if the size operand falls below a certain threshold.
2852 SmallVector<SDOperand, 8> OutChains;
2854 default: break; // Do nothing for now.
2856 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
2857 Size->getValue(), Align, TLI)) {
2858 unsigned NumMemOps = MemOps.size();
2859 unsigned Offset = 0;
2860 for (unsigned i = 0; i < NumMemOps; i++) {
2861 MVT::ValueType VT = MemOps[i];
2862 unsigned VTSize = getSizeInBits(VT) / 8;
2863 SDOperand Value = getMemsetValue(Op2, VT, DAG);
2864 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(),
2866 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
2867 DAG.getSrcValue(I.getOperand(1), Offset));
2868 OutChains.push_back(Store);
2875 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
2876 Size->getValue(), Align, TLI)) {
2877 unsigned NumMemOps = MemOps.size();
2878 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
2879 GlobalAddressSDNode *G = NULL;
2881 bool CopyFromStr = false;
2883 if (Op2.getOpcode() == ISD::GlobalAddress)
2884 G = cast<GlobalAddressSDNode>(Op2);
2885 else if (Op2.getOpcode() == ISD::ADD &&
2886 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
2887 Op2.getOperand(1).getOpcode() == ISD::Constant) {
2888 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
2889 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
2892 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
2894 Str = GV->getStringValue(false);
2902 for (unsigned i = 0; i < NumMemOps; i++) {
2903 MVT::ValueType VT = MemOps[i];
2904 unsigned VTSize = getSizeInBits(VT) / 8;
2905 SDOperand Value, Chain, Store;
2908 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
2911 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2912 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2913 DAG.getSrcValue(I.getOperand(1), DstOff));
2915 Value = DAG.getLoad(VT, getRoot(),
2916 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
2917 DAG.getSrcValue(I.getOperand(2), SrcOff));
2918 Chain = Value.getValue(1);
2920 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2921 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2922 DAG.getSrcValue(I.getOperand(1), DstOff));
2924 OutChains.push_back(Store);
2933 if (!OutChains.empty()) {
2934 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
2935 &OutChains[0], OutChains.size()));
2940 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
2943 //===----------------------------------------------------------------------===//
2944 // SelectionDAGISel code
2945 //===----------------------------------------------------------------------===//
2947 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
2948 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
2951 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
2952 // FIXME: we only modify the CFG to split critical edges. This
2953 // updates dom and loop info.
2957 /// OptimizeNoopCopyExpression - We have determined that the specified cast
2958 /// instruction is a noop copy (e.g. it's casting from one pointer type to
2959 /// another, int->uint, or int->sbyte on PPC.
2961 /// Return true if any changes are made.
2962 static bool OptimizeNoopCopyExpression(CastInst *CI) {
2963 BasicBlock *DefBB = CI->getParent();
2965 /// InsertedCasts - Only insert a cast in each block once.
2966 std::map<BasicBlock*, CastInst*> InsertedCasts;
2968 bool MadeChange = false;
2969 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
2971 Use &TheUse = UI.getUse();
2972 Instruction *User = cast<Instruction>(*UI);
2974 // Figure out which BB this cast is used in. For PHI's this is the
2975 // appropriate predecessor block.
2976 BasicBlock *UserBB = User->getParent();
2977 if (PHINode *PN = dyn_cast<PHINode>(User)) {
2978 unsigned OpVal = UI.getOperandNo()/2;
2979 UserBB = PN->getIncomingBlock(OpVal);
2982 // Preincrement use iterator so we don't invalidate it.
2985 // If this user is in the same block as the cast, don't change the cast.
2986 if (UserBB == DefBB) continue;
2988 // If we have already inserted a cast into this block, use it.
2989 CastInst *&InsertedCast = InsertedCasts[UserBB];
2991 if (!InsertedCast) {
2992 BasicBlock::iterator InsertPt = UserBB->begin();
2993 while (isa<PHINode>(InsertPt)) ++InsertPt;
2996 new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3000 // Replace a use of the cast with a use of the new casat.
3001 TheUse = InsertedCast;
3004 // If we removed all uses, nuke the cast.
3005 if (CI->use_empty())
3006 CI->eraseFromParent();
3011 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
3012 /// casting to the type of GEPI.
3013 static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
3014 Instruction *GEPI, Value *Ptr,
3016 if (V) return V; // Already computed.
3018 BasicBlock::iterator InsertPt;
3019 if (BB == GEPI->getParent()) {
3020 // If insert into the GEP's block, insert right after the GEP.
3024 // Otherwise, insert at the top of BB, after any PHI nodes
3025 InsertPt = BB->begin();
3026 while (isa<PHINode>(InsertPt)) ++InsertPt;
3029 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3030 // BB so that there is only one value live across basic blocks (the cast
3032 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3033 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3034 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3036 // Add the offset, cast it to the right type.
3037 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
3038 return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
3041 /// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3042 /// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
3043 /// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3044 /// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
3045 /// sink PtrOffset into user blocks where doing so will likely allow us to fold
3046 /// the constant add into a load or store instruction. Additionally, if a user
3047 /// is a pointer-pointer cast, we look through it to find its users.
3048 static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3049 Constant *PtrOffset, BasicBlock *DefBB,
3050 GetElementPtrInst *GEPI,
3051 std::map<BasicBlock*,Instruction*> &InsertedExprs) {
3052 while (!RepPtr->use_empty()) {
3053 Instruction *User = cast<Instruction>(RepPtr->use_back());
3055 // If the user is a Pointer-Pointer cast, recurse.
3056 if (isa<CastInst>(User) && isa<PointerType>(User->getType())) {
3057 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3059 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
3060 // could invalidate an iterator.
3061 User->setOperand(0, UndefValue::get(RepPtr->getType()));
3065 // If this is a load of the pointer, or a store through the pointer, emit
3066 // the increment into the load/store block.
3067 Instruction *NewVal;
3068 if (isa<LoadInst>(User) ||
3069 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3070 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3071 User->getParent(), GEPI,
3074 // If this use is not foldable into the addressing mode, use a version
3075 // emitted in the GEP block.
3076 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3080 if (GEPI->getType() != RepPtr->getType()) {
3081 BasicBlock::iterator IP = NewVal;
3083 NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP);
3085 User->replaceUsesOfWith(RepPtr, NewVal);
3090 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3091 /// selection, we want to be a bit careful about some things. In particular, if
3092 /// we have a GEP instruction that is used in a different block than it is
3093 /// defined, the addressing expression of the GEP cannot be folded into loads or
3094 /// stores that use it. In this case, decompose the GEP and move constant
3095 /// indices into blocks that use it.
3096 static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
3097 const TargetData *TD) {
3098 // If this GEP is only used inside the block it is defined in, there is no
3099 // need to rewrite it.
3100 bool isUsedOutsideDefBB = false;
3101 BasicBlock *DefBB = GEPI->getParent();
3102 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3104 if (cast<Instruction>(*UI)->getParent() != DefBB) {
3105 isUsedOutsideDefBB = true;
3109 if (!isUsedOutsideDefBB) return false;
3111 // If this GEP has no non-zero constant indices, there is nothing we can do,
3113 bool hasConstantIndex = false;
3114 bool hasVariableIndex = false;
3115 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3116 E = GEPI->op_end(); OI != E; ++OI) {
3117 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
3118 if (CI->getRawValue()) {
3119 hasConstantIndex = true;
3123 hasVariableIndex = true;
3127 // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3128 if (!hasConstantIndex && !hasVariableIndex) {
3129 Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(),
3130 GEPI->getName(), GEPI);
3131 GEPI->replaceAllUsesWith(NC);
3132 GEPI->eraseFromParent();
3136 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
3137 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3140 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
3141 // constant offset (which we now know is non-zero) and deal with it later.
3142 uint64_t ConstantOffset = 0;
3143 const Type *UIntPtrTy = TD->getIntPtrType();
3144 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3145 const Type *Ty = GEPI->getOperand(0)->getType();
3147 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3148 E = GEPI->op_end(); OI != E; ++OI) {
3150 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3151 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
3153 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
3154 Ty = StTy->getElementType(Field);
3156 Ty = cast<SequentialType>(Ty)->getElementType();
3158 // Handle constant subscripts.
3159 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3160 if (CI->getRawValue() == 0) continue;
3162 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
3163 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
3165 ConstantOffset+=TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
3169 // Ptr = Ptr + Idx * ElementSize;
3171 // Cast Idx to UIntPtrTy if needed.
3172 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
3174 uint64_t ElementSize = TD->getTypeSize(Ty);
3175 // Mask off bits that should not be set.
3176 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3177 Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize);
3179 // Multiply by the element size and add to the base.
3180 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3181 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3185 // Make sure that the offset fits in uintptr_t.
3186 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3187 Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset);
3189 // Okay, we have now emitted all of the variable index parts to the BB that
3190 // the GEP is defined in. Loop over all of the using instructions, inserting
3191 // an "add Ptr, ConstantOffset" into each block that uses it and update the
3192 // instruction to use the newly computed value, making GEPI dead. When the
3193 // user is a load or store instruction address, we emit the add into the user
3194 // block, otherwise we use a canonical version right next to the gep (these
3195 // won't be foldable as addresses, so we might as well share the computation).
3197 std::map<BasicBlock*,Instruction*> InsertedExprs;
3198 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3200 // Finally, the GEP is dead, remove it.
3201 GEPI->eraseFromParent();
3206 bool SelectionDAGISel::runOnFunction(Function &Fn) {
3207 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3208 RegMap = MF.getSSARegMap();
3209 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
3211 // First, split all critical edges for PHI nodes with incoming values that are
3212 // constants, this way the load of the constant into a vreg will not be placed
3213 // into MBBs that are used some other way.
3215 // In this pass we also look for GEP and cast instructions that are used
3216 // across basic blocks and rewrite them to improve basic-block-at-a-time
3220 bool MadeChange = true;
3221 while (MadeChange) {
3223 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
3225 BasicBlock::iterator BBI;
3226 for (BBI = BB->begin(); (PN = dyn_cast<PHINode>(BBI)); ++BBI)
3227 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
3228 if (isa<Constant>(PN->getIncomingValue(i)))
3229 SplitCriticalEdge(PN->getIncomingBlock(i), BB);
3231 for (BasicBlock::iterator E = BB->end(); BBI != E; ) {
3232 Instruction *I = BBI++;
3233 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
3234 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
3235 } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
3236 // If the source of the cast is a constant, then this should have
3237 // already been constant folded. The only reason NOT to constant fold
3238 // it is if something (e.g. LSR) was careful to place the constant
3239 // evaluation in a block other than then one that uses it (e.g. to hoist
3240 // the address of globals out of a loop). If this is the case, we don't
3241 // want to forward-subst the cast.
3242 if (isa<Constant>(CI->getOperand(0)))
3245 // If this is a noop copy, sink it into user blocks to reduce the number
3246 // of virtual registers that must be created and coallesced.
3247 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
3248 MVT::ValueType DstVT = TLI.getValueType(CI->getType());
3250 // This is an fp<->int conversion?
3251 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
3254 // If this is an extension, it will be a zero or sign extension, which
3256 if (SrcVT < DstVT) continue;
3258 // If these values will be promoted, find out what they will be promoted
3259 // to. This helps us consider truncates on PPC as noop copies when they
3261 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
3262 SrcVT = TLI.getTypeToTransformTo(SrcVT);
3263 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
3264 DstVT = TLI.getTypeToTransformTo(DstVT);
3266 // If, after promotion, these are the same types, this is a noop copy.
3268 MadeChange |= OptimizeNoopCopyExpression(CI);
3274 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
3276 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
3277 SelectBasicBlock(I, MF, FuncInfo);
3283 SDOperand SelectionDAGISel::
3284 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
3285 SDOperand Op = SDL.getValue(V);
3286 assert((Op.getOpcode() != ISD::CopyFromReg ||
3287 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
3288 "Copy from a reg to the same reg!");
3290 // If this type is not legal, we must make sure to not create an invalid
3292 MVT::ValueType SrcVT = Op.getValueType();
3293 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
3294 SelectionDAG &DAG = SDL.DAG;
3295 if (SrcVT == DestVT) {
3296 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3297 } else if (SrcVT == MVT::Vector) {
3298 // Handle copies from generic vectors to registers.
3299 MVT::ValueType PTyElementVT, PTyLegalElementVT;
3300 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
3301 PTyElementVT, PTyLegalElementVT);
3303 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
3304 // MVT::Vector type.
3305 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
3306 DAG.getConstant(NE, MVT::i32),
3307 DAG.getValueType(PTyElementVT));
3309 // Loop over all of the elements of the resultant vector,
3310 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
3311 // copying them into output registers.
3312 SmallVector<SDOperand, 8> OutChains;
3313 SDOperand Root = SDL.getRoot();
3314 for (unsigned i = 0; i != NE; ++i) {
3315 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
3316 Op, DAG.getConstant(i, TLI.getPointerTy()));
3317 if (PTyElementVT == PTyLegalElementVT) {
3318 // Elements are legal.
3319 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3320 } else if (PTyLegalElementVT > PTyElementVT) {
3321 // Elements are promoted.
3322 if (MVT::isFloatingPoint(PTyLegalElementVT))
3323 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
3325 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
3326 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3328 // Elements are expanded.
3329 // The src value is expanded into multiple registers.
3330 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3331 Elt, DAG.getConstant(0, TLI.getPointerTy()));
3332 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3333 Elt, DAG.getConstant(1, TLI.getPointerTy()));
3334 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
3335 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
3338 return DAG.getNode(ISD::TokenFactor, MVT::Other,
3339 &OutChains[0], OutChains.size());
3340 } else if (SrcVT < DestVT) {
3341 // The src value is promoted to the register.
3342 if (MVT::isFloatingPoint(SrcVT))
3343 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
3345 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
3346 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3348 // The src value is expanded into multiple registers.
3349 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3350 Op, DAG.getConstant(0, TLI.getPointerTy()));
3351 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3352 Op, DAG.getConstant(1, TLI.getPointerTy()));
3353 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
3354 return DAG.getCopyToReg(Op, Reg+1, Hi);
3358 void SelectionDAGISel::
3359 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
3360 std::vector<SDOperand> &UnorderedChains) {
3361 // If this is the entry block, emit arguments.
3362 Function &F = *BB->getParent();
3363 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
3364 SDOperand OldRoot = SDL.DAG.getRoot();
3365 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
3368 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
3370 if (!AI->use_empty()) {
3371 SDL.setValue(AI, Args[a]);
3373 // If this argument is live outside of the entry block, insert a copy from
3374 // whereever we got it to the vreg that other BB's will reference it as.
3375 if (FuncInfo.ValueMap.count(AI)) {
3377 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
3378 UnorderedChains.push_back(Copy);
3382 // Finally, if the target has anything special to do, allow it to do so.
3383 // FIXME: this should insert code into the DAG!
3384 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
3387 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3388 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
3389 FunctionLoweringInfo &FuncInfo) {
3390 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
3392 std::vector<SDOperand> UnorderedChains;
3394 // Lower any arguments needed in this block if this is the entry block.
3395 if (LLVMBB == &LLVMBB->getParent()->front())
3396 LowerArguments(LLVMBB, SDL, UnorderedChains);
3398 BB = FuncInfo.MBBMap[LLVMBB];
3399 SDL.setCurrentBasicBlock(BB);
3401 // Lower all of the non-terminator instructions.
3402 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3406 // Ensure that all instructions which are used outside of their defining
3407 // blocks are available as virtual registers.
3408 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
3409 if (!I->use_empty() && !isa<PHINode>(I)) {
3410 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
3411 if (VMI != FuncInfo.ValueMap.end())
3412 UnorderedChains.push_back(
3413 CopyValueToVirtualRegister(SDL, I, VMI->second));
3416 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
3417 // ensure constants are generated when needed. Remember the virtual registers
3418 // that need to be added to the Machine PHI nodes as input. We cannot just
3419 // directly add them, because expansion might result in multiple MBB's for one
3420 // BB. As such, the start of the BB might correspond to a different MBB than
3424 // Emit constants only once even if used by multiple PHI nodes.
3425 std::map<Constant*, unsigned> ConstantsOut;
3427 // Check successor nodes PHI nodes that expect a constant to be available from
3429 TerminatorInst *TI = LLVMBB->getTerminator();
3430 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
3431 BasicBlock *SuccBB = TI->getSuccessor(succ);
3432 if (!isa<PHINode>(SuccBB->begin())) continue;
3434 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
3437 // At this point we know that there is a 1-1 correspondence between LLVM PHI
3438 // nodes and Machine PHI nodes, but the incoming operands have not been
3440 for (BasicBlock::iterator I = SuccBB->begin();
3441 (PN = dyn_cast<PHINode>(I)); ++I)
3442 if (!PN->use_empty()) {
3444 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
3445 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
3446 unsigned &RegOut = ConstantsOut[C];
3448 RegOut = FuncInfo.CreateRegForValue(C);
3449 UnorderedChains.push_back(
3450 CopyValueToVirtualRegister(SDL, C, RegOut));
3454 Reg = FuncInfo.ValueMap[PHIOp];
3456 assert(isa<AllocaInst>(PHIOp) &&
3457 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
3458 "Didn't codegen value into a register!??");
3459 Reg = FuncInfo.CreateRegForValue(PHIOp);
3460 UnorderedChains.push_back(
3461 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
3465 // Remember that this register needs to added to the machine PHI node as
3466 // the input for this MBB.
3467 MVT::ValueType VT = TLI.getValueType(PN->getType());
3468 unsigned NumElements;
3469 if (VT != MVT::Vector)
3470 NumElements = TLI.getNumElements(VT);
3472 MVT::ValueType VT1,VT2;
3474 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
3477 for (unsigned i = 0, e = NumElements; i != e; ++i)
3478 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
3481 ConstantsOut.clear();
3483 // Turn all of the unordered chains into one factored node.
3484 if (!UnorderedChains.empty()) {
3485 SDOperand Root = SDL.getRoot();
3486 if (Root.getOpcode() != ISD::EntryToken) {
3487 unsigned i = 0, e = UnorderedChains.size();
3488 for (; i != e; ++i) {
3489 assert(UnorderedChains[i].Val->getNumOperands() > 1);
3490 if (UnorderedChains[i].Val->getOperand(0) == Root)
3491 break; // Don't add the root if we already indirectly depend on it.
3495 UnorderedChains.push_back(Root);
3497 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
3498 &UnorderedChains[0], UnorderedChains.size()));
3501 // Lower the terminator after the copies are emitted.
3502 SDL.visit(*LLVMBB->getTerminator());
3504 // Copy over any CaseBlock records that may now exist due to SwitchInst
3505 // lowering, as well as any jump table information.
3506 SwitchCases.clear();
3507 SwitchCases = SDL.SwitchCases;
3510 // Make sure the root of the DAG is up-to-date.
3511 DAG.setRoot(SDL.getRoot());
3514 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
3515 // Run the DAG combiner in pre-legalize mode.
3518 DEBUG(std::cerr << "Lowered selection DAG:\n");
3521 // Second step, hack on the DAG until it only uses operations and types that
3522 // the target supports.
3525 DEBUG(std::cerr << "Legalized selection DAG:\n");
3528 // Run the DAG combiner in post-legalize mode.
3531 if (ViewISelDAGs) DAG.viewGraph();
3533 // Third, instruction select all of the operations to machine code, adding the
3534 // code to the MachineBasicBlock.
3535 InstructionSelectBasicBlock(DAG);
3537 DEBUG(std::cerr << "Selected machine code:\n");
3541 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
3542 FunctionLoweringInfo &FuncInfo) {
3543 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
3545 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3548 // First step, lower LLVM code to some DAG. This DAG may use operations and
3549 // types that are not supported by the target.
3550 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
3552 // Second step, emit the lowered DAG as machine code.
3553 CodeGenAndEmitDAG(DAG);
3556 // Next, now that we know what the last MBB the LLVM BB expanded is, update
3557 // PHI nodes in successors.
3558 if (SwitchCases.empty() && JT.Reg == 0) {
3559 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3560 MachineInstr *PHI = PHINodesToUpdate[i].first;
3561 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3562 "This is not a machine PHI node that we are updating!");
3563 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
3564 PHI->addMachineBasicBlockOperand(BB);
3569 // If the JumpTable record is filled in, then we need to emit a jump table.
3570 // Updating the PHI nodes is tricky in this case, since we need to determine
3571 // whether the PHI is a successor of the range check MBB or the jump table MBB
3573 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
3574 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3576 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3577 MachineBasicBlock *RangeBB = BB;
3578 // Set the current basic block to the mbb we wish to insert the code into
3580 SDL.setCurrentBasicBlock(BB);
3582 SDL.visitJumpTable(JT);
3583 SDAG.setRoot(SDL.getRoot());
3584 CodeGenAndEmitDAG(SDAG);
3586 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3587 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3588 MachineBasicBlock *PHIBB = PHI->getParent();
3589 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3590 "This is not a machine PHI node that we are updating!");
3591 if (PHIBB == JT.Default) {
3592 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
3593 PHI->addMachineBasicBlockOperand(RangeBB);
3595 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
3596 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
3597 PHI->addMachineBasicBlockOperand(BB);
3603 // If we generated any switch lowering information, build and codegen any
3604 // additional DAGs necessary.
3605 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
3606 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3608 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3610 // Set the current basic block to the mbb we wish to insert the code into
3611 BB = SwitchCases[i].ThisBB;
3612 SDL.setCurrentBasicBlock(BB);
3615 SDL.visitSwitchCase(SwitchCases[i]);
3616 SDAG.setRoot(SDL.getRoot());
3617 CodeGenAndEmitDAG(SDAG);
3619 // Handle any PHI nodes in successors of this chunk, as if we were coming
3620 // from the original BB before switch expansion. Note that PHI nodes can
3621 // occur multiple times in PHINodesToUpdate. We have to be very careful to
3622 // handle them the right number of times.
3623 while ((BB = SwitchCases[i].LHSBB)) { // Handle LHS and RHS.
3624 for (MachineBasicBlock::iterator Phi = BB->begin();
3625 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
3626 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
3627 for (unsigned pn = 0; ; ++pn) {
3628 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
3629 if (PHINodesToUpdate[pn].first == Phi) {
3630 Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
3631 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
3637 // Don't process RHS if same block as LHS.
3638 if (BB == SwitchCases[i].RHSBB)
3639 SwitchCases[i].RHSBB = 0;
3641 // If we haven't handled the RHS, do so now. Otherwise, we're done.
3642 SwitchCases[i].LHSBB = SwitchCases[i].RHSBB;
3643 SwitchCases[i].RHSBB = 0;
3645 assert(SwitchCases[i].LHSBB == 0 && SwitchCases[i].RHSBB == 0);
3650 //===----------------------------------------------------------------------===//
3651 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
3652 /// target node in the graph.
3653 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
3654 if (ViewSchedDAGs) DAG.viewGraph();
3656 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
3660 RegisterScheduler::setDefault(Ctor);
3663 ScheduleDAG *SL = Ctor(this, &DAG, BB);
3669 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
3670 return new HazardRecognizer();
3674 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
3675 /// by tblgen. Others should not call it.
3676 void SelectionDAGISel::
3677 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
3678 std::vector<SDOperand> InOps;
3679 std::swap(InOps, Ops);
3681 Ops.push_back(InOps[0]); // input chain.
3682 Ops.push_back(InOps[1]); // input asm string.
3684 unsigned i = 2, e = InOps.size();
3685 if (InOps[e-1].getValueType() == MVT::Flag)
3686 --e; // Don't process a flag operand if it is here.
3689 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
3690 if ((Flags & 7) != 4 /*MEM*/) {
3691 // Just skip over this operand, copying the operands verbatim.
3692 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
3693 i += (Flags >> 3) + 1;
3695 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
3696 // Otherwise, this is a memory operand. Ask the target to select it.
3697 std::vector<SDOperand> SelOps;
3698 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
3699 std::cerr << "Could not match memory address. Inline asm failure!\n";
3703 // Add this to the output node.
3704 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
3705 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
3710 // Add the flag input back if present.
3711 if (e != InOps.size())
3712 Ops.push_back(InOps.back());