1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/DebugInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetIntrinsicInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLowering.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/ADT/PostOrderIterator.h"
54 #include "llvm/ADT/Statistic.h"
58 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
59 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
60 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
61 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
62 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
65 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
66 cl::desc("Enable verbose messages in the \"fast\" "
67 "instruction selector"));
69 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
70 cl::desc("Enable abort calls when \"fast\" instruction fails"));
74 cl::desc("use Machine Branch Probability Info"),
75 cl::init(true), cl::Hidden);
79 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
80 cl::desc("Pop up a window to show dags before the first "
83 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize types"));
86 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before legalize"));
89 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
90 cl::desc("Pop up a window to show dags before the second "
93 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
94 cl::desc("Pop up a window to show dags before the post legalize types"
95 " dag combine pass"));
97 ViewISelDAGs("view-isel-dags", cl::Hidden,
98 cl::desc("Pop up a window to show isel dags as they are selected"));
100 ViewSchedDAGs("view-sched-dags", cl::Hidden,
101 cl::desc("Pop up a window to show sched dags as they are processed"));
103 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
104 cl::desc("Pop up a window to show SUnit dags after they are processed"));
106 static const bool ViewDAGCombine1 = false,
107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
108 ViewDAGCombine2 = false,
109 ViewDAGCombineLT = false,
110 ViewISelDAGs = false, ViewSchedDAGs = false,
111 ViewSUnitDAGs = false;
114 //===---------------------------------------------------------------------===//
116 /// RegisterScheduler class - Track the registration of instruction schedulers.
118 //===---------------------------------------------------------------------===//
119 MachinePassRegistry RegisterScheduler::Registry;
121 //===---------------------------------------------------------------------===//
123 /// ISHeuristic command line option for instruction schedulers.
125 //===---------------------------------------------------------------------===//
126 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
127 RegisterPassParser<RegisterScheduler> >
128 ISHeuristic("pre-RA-sched",
129 cl::init(&createDefaultScheduler),
130 cl::desc("Instruction schedulers available (before register"
133 static RegisterScheduler
134 defaultListDAGScheduler("default", "Best scheduler for the target",
135 createDefaultScheduler);
138 //===--------------------------------------------------------------------===//
139 /// createDefaultScheduler - This creates an instruction scheduler appropriate
141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
142 CodeGenOpt::Level OptLevel) {
143 const TargetLowering &TLI = IS->getTargetLowering();
145 if (OptLevel == CodeGenOpt::None)
146 return createSourceListDAGScheduler(IS, OptLevel);
147 if (TLI.getSchedulingPreference() == Sched::Latency)
148 return createTDListDAGScheduler(IS, OptLevel);
149 if (TLI.getSchedulingPreference() == Sched::RegPressure)
150 return createBURRListDAGScheduler(IS, OptLevel);
151 if (TLI.getSchedulingPreference() == Sched::Hybrid)
152 return createHybridListDAGScheduler(IS, OptLevel);
153 assert(TLI.getSchedulingPreference() == Sched::ILP &&
154 "Unknown sched type!");
155 return createILPListDAGScheduler(IS, OptLevel);
159 // EmitInstrWithCustomInserter - This method should be implemented by targets
160 // that mark instructions with the 'usesCustomInserter' flag. These
161 // instructions are special in various ways, which require special support to
162 // insert. The specified MachineInstr is created but not inserted into any
163 // basic blocks, and this method is called to expand it into a sequence of
164 // instructions, potentially also creating new basic blocks and control flow.
165 // When new basic blocks are inserted and the edges from MBB to its successors
166 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
169 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
170 MachineBasicBlock *MBB) const {
172 dbgs() << "If a target marks an instruction with "
173 "'usesCustomInserter', it must implement "
174 "TargetLowering::EmitInstrWithCustomInserter!";
180 //===----------------------------------------------------------------------===//
181 // SelectionDAGISel code
182 //===----------------------------------------------------------------------===//
184 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
185 CodeGenOpt::Level OL) :
186 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
187 FuncInfo(new FunctionLoweringInfo(TLI)),
188 CurDAG(new SelectionDAG(tm)),
189 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
193 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
194 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
195 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
198 SelectionDAGISel::~SelectionDAGISel() {
204 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
205 AU.addRequired<AliasAnalysis>();
206 AU.addPreserved<AliasAnalysis>();
207 AU.addRequired<GCModuleInfo>();
208 AU.addPreserved<GCModuleInfo>();
209 if (UseMBPI && OptLevel != CodeGenOpt::None)
210 AU.addRequired<BranchProbabilityInfo>();
211 MachineFunctionPass::getAnalysisUsage(AU);
214 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
215 /// may trap on it. In this case we have to split the edge so that the path
216 /// through the predecessor block that doesn't go to the phi block doesn't
217 /// execute the possibly trapping instruction.
219 /// This is required for correctness, so it must be done at -O0.
221 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
222 // Loop for blocks with phi nodes.
223 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
224 PHINode *PN = dyn_cast<PHINode>(BB->begin());
225 if (PN == 0) continue;
228 // For each block with a PHI node, check to see if any of the input values
229 // are potentially trapping constant expressions. Constant expressions are
230 // the only potentially trapping value that can occur as the argument to a
232 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
233 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
234 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
235 if (CE == 0 || !CE->canTrap()) continue;
237 // The only case we have to worry about is when the edge is critical.
238 // Since this block has a PHI Node, we assume it has multiple input
239 // edges: check to see if the pred has multiple successors.
240 BasicBlock *Pred = PN->getIncomingBlock(i);
241 if (Pred->getTerminator()->getNumSuccessors() == 1)
244 // Okay, we have to split this edge.
245 SplitCriticalEdge(Pred->getTerminator(),
246 GetSuccessorNumber(Pred, BB), SDISel, true);
252 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
253 // Do some sanity-checking on the command-line options.
254 assert((!EnableFastISelVerbose || EnableFastISel) &&
255 "-fast-isel-verbose requires -fast-isel");
256 assert((!EnableFastISelAbort || EnableFastISel) &&
257 "-fast-isel-abort requires -fast-isel");
259 const Function &Fn = *mf.getFunction();
260 const TargetInstrInfo &TII = *TM.getInstrInfo();
261 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
264 RegInfo = &MF->getRegInfo();
265 AA = &getAnalysis<AliasAnalysis>();
266 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
268 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
270 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
273 FuncInfo->set(Fn, *MF);
275 if (UseMBPI && OptLevel != CodeGenOpt::None)
276 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
282 SelectAllBasicBlocks(Fn);
284 // If the first basic block in the function has live ins that need to be
285 // copied into vregs, emit the copies into the top of the block before
286 // emitting the code for the block.
287 MachineBasicBlock *EntryMBB = MF->begin();
288 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
290 DenseMap<unsigned, unsigned> LiveInMap;
291 if (!FuncInfo->ArgDbgValues.empty())
292 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
293 E = RegInfo->livein_end(); LI != E; ++LI)
295 LiveInMap.insert(std::make_pair(LI->first, LI->second));
297 // Insert DBG_VALUE instructions for function arguments to the entry block.
298 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
299 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
300 unsigned Reg = MI->getOperand(0).getReg();
301 if (TargetRegisterInfo::isPhysicalRegister(Reg))
302 EntryMBB->insert(EntryMBB->begin(), MI);
304 MachineInstr *Def = RegInfo->getVRegDef(Reg);
305 MachineBasicBlock::iterator InsertPos = Def;
306 // FIXME: VR def may not be in entry block.
307 Def->getParent()->insert(llvm::next(InsertPos), MI);
310 // If Reg is live-in then update debug info to track its copy in a vreg.
311 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
312 if (LDI != LiveInMap.end()) {
313 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
314 MachineBasicBlock::iterator InsertPos = Def;
315 const MDNode *Variable =
316 MI->getOperand(MI->getNumOperands()-1).getMetadata();
317 unsigned Offset = MI->getOperand(1).getImm();
318 // Def is never a terminator here, so it is ok to increment InsertPos.
319 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
320 TII.get(TargetOpcode::DBG_VALUE))
321 .addReg(LDI->second, RegState::Debug)
322 .addImm(Offset).addMetadata(Variable);
324 // If this vreg is directly copied into an exported register then
325 // that COPY instructions also need DBG_VALUE, if it is the only
326 // user of LDI->second.
327 MachineInstr *CopyUseMI = NULL;
328 for (MachineRegisterInfo::use_iterator
329 UI = RegInfo->use_begin(LDI->second);
330 MachineInstr *UseMI = UI.skipInstruction();) {
331 if (UseMI->isDebugValue()) continue;
332 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
333 CopyUseMI = UseMI; continue;
335 // Otherwise this is another use or second copy use.
336 CopyUseMI = NULL; break;
339 MachineInstr *NewMI =
340 BuildMI(*MF, CopyUseMI->getDebugLoc(),
341 TII.get(TargetOpcode::DBG_VALUE))
342 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
343 .addImm(Offset).addMetadata(Variable);
344 EntryMBB->insertAfter(CopyUseMI, NewMI);
349 // Determine if there are any calls in this machine function.
350 MachineFrameInfo *MFI = MF->getFrameInfo();
351 if (!MFI->hasCalls()) {
352 for (MachineFunction::const_iterator
353 I = MF->begin(), E = MF->end(); I != E; ++I) {
354 const MachineBasicBlock *MBB = I;
355 for (MachineBasicBlock::const_iterator
356 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
357 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
359 if ((MCID.isCall() && !MCID.isReturn()) ||
360 II->isStackAligningInlineAsm()) {
361 MFI->setHasCalls(true);
369 // Determine if there is a call to setjmp in the machine function.
370 MF->setCallsSetJmp(Fn.callsFunctionThatReturnsTwice());
372 // Replace forward-declared registers with the registers containing
373 // the desired value.
374 MachineRegisterInfo &MRI = MF->getRegInfo();
375 for (DenseMap<unsigned, unsigned>::iterator
376 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
378 unsigned From = I->first;
379 unsigned To = I->second;
380 // If To is also scheduled to be replaced, find what its ultimate
383 DenseMap<unsigned, unsigned>::iterator J =
384 FuncInfo->RegFixups.find(To);
389 MRI.replaceRegWith(From, To);
392 // Release function-specific state. SDB and CurDAG are already cleared
399 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
400 BasicBlock::const_iterator End,
402 // Lower all of the non-terminator instructions. If a call is emitted
403 // as a tail call, cease emitting nodes for this block. Terminators
404 // are handled below.
405 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
408 // Make sure the root of the DAG is up-to-date.
409 CurDAG->setRoot(SDB->getControlRoot());
410 HadTailCall = SDB->HasTailCall;
413 // Final step, emit the lowered DAG as machine code.
417 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
418 SmallPtrSet<SDNode*, 128> VisitedNodes;
419 SmallVector<SDNode*, 128> Worklist;
421 Worklist.push_back(CurDAG->getRoot().getNode());
428 SDNode *N = Worklist.pop_back_val();
430 // If we've already seen this node, ignore it.
431 if (!VisitedNodes.insert(N))
434 // Otherwise, add all chain operands to the worklist.
435 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
436 if (N->getOperand(i).getValueType() == MVT::Other)
437 Worklist.push_back(N->getOperand(i).getNode());
439 // If this is a CopyToReg with a vreg dest, process it.
440 if (N->getOpcode() != ISD::CopyToReg)
443 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
444 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
447 // Ignore non-scalar or non-integer values.
448 SDValue Src = N->getOperand(2);
449 EVT SrcVT = Src.getValueType();
450 if (!SrcVT.isInteger() || SrcVT.isVector())
453 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
454 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
455 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
456 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
457 } while (!Worklist.empty());
460 void SelectionDAGISel::CodeGenAndEmitDAG() {
461 std::string GroupName;
462 if (TimePassesIsEnabled)
463 GroupName = "Instruction Selection and Scheduling";
464 std::string BlockName;
465 int BlockNumber = -1;
467 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
468 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
472 BlockNumber = FuncInfo->MBB->getNumber();
473 BlockName = MF->getFunction()->getNameStr() + ":" +
474 FuncInfo->MBB->getBasicBlock()->getNameStr();
476 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
477 << " '" << BlockName << "'\n"; CurDAG->dump());
479 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
481 // Run the DAG combiner in pre-legalize mode.
483 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
484 CurDAG->Combine(Unrestricted, *AA, OptLevel);
487 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
488 << " '" << BlockName << "'\n"; CurDAG->dump());
490 // Second step, hack on the DAG until it only uses operations and types that
491 // the target supports.
492 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
497 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
498 Changed = CurDAG->LegalizeTypes();
501 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
502 << " '" << BlockName << "'\n"; CurDAG->dump());
505 if (ViewDAGCombineLT)
506 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
508 // Run the DAG combiner in post-type-legalize mode.
510 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
511 TimePassesIsEnabled);
512 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
515 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
516 << " '" << BlockName << "'\n"; CurDAG->dump());
520 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
521 Changed = CurDAG->LegalizeVectors();
526 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
527 CurDAG->LegalizeTypes();
530 if (ViewDAGCombineLT)
531 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
533 // Run the DAG combiner in post-type-legalize mode.
535 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
536 TimePassesIsEnabled);
537 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
540 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
541 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
544 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
547 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
551 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
552 << " '" << BlockName << "'\n"; CurDAG->dump());
554 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
556 // Run the DAG combiner in post-legalize mode.
558 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
559 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
562 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
563 << " '" << BlockName << "'\n"; CurDAG->dump());
565 if (OptLevel != CodeGenOpt::None)
566 ComputeLiveOutVRegInfo();
568 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
570 // Third, instruction select all of the operations to machine code, adding the
571 // code to the MachineBasicBlock.
573 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
574 DoInstructionSelection();
577 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
578 << " '" << BlockName << "'\n"; CurDAG->dump());
580 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
582 // Schedule machine code.
583 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
585 NamedRegionTimer T("Instruction Scheduling", GroupName,
586 TimePassesIsEnabled);
587 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
590 if (ViewSUnitDAGs) Scheduler->viewGraph();
592 // Emit machine code to BB. This can change 'BB' to the last block being
594 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
596 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
598 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
599 FuncInfo->InsertPt = Scheduler->InsertPos;
602 // If the block was split, make sure we update any references that are used to
603 // update PHI nodes later on.
604 if (FirstMBB != LastMBB)
605 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
607 // Free the scheduler state.
609 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
610 TimePassesIsEnabled);
614 // Free the SelectionDAG state, now that we're finished with it.
618 void SelectionDAGISel::DoInstructionSelection() {
619 DEBUG(errs() << "===== Instruction selection begins: BB#"
620 << FuncInfo->MBB->getNumber()
621 << " '" << FuncInfo->MBB->getName() << "'\n");
625 // Select target instructions for the DAG.
627 // Number all nodes with a topological order and set DAGSize.
628 DAGSize = CurDAG->AssignTopologicalOrder();
630 // Create a dummy node (which is not added to allnodes), that adds
631 // a reference to the root node, preventing it from being deleted,
632 // and tracking any changes of the root.
633 HandleSDNode Dummy(CurDAG->getRoot());
634 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
637 // The AllNodes list is now topological-sorted. Visit the
638 // nodes by starting at the end of the list (the root of the
639 // graph) and preceding back toward the beginning (the entry
641 while (ISelPosition != CurDAG->allnodes_begin()) {
642 SDNode *Node = --ISelPosition;
643 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
644 // but there are currently some corner cases that it misses. Also, this
645 // makes it theoretically possible to disable the DAGCombiner.
646 if (Node->use_empty())
649 SDNode *ResNode = Select(Node);
651 // FIXME: This is pretty gross. 'Select' should be changed to not return
652 // anything at all and this code should be nuked with a tactical strike.
654 // If node should not be replaced, continue with the next one.
655 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
659 ReplaceUses(Node, ResNode);
661 // If after the replacement this node is not used any more,
662 // remove this dead node.
663 if (Node->use_empty()) { // Don't delete EntryToken, etc.
664 ISelUpdater ISU(ISelPosition);
665 CurDAG->RemoveDeadNode(Node, &ISU);
669 CurDAG->setRoot(Dummy.getValue());
672 DEBUG(errs() << "===== Instruction selection ends:\n");
674 PostprocessISelDAG();
677 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
678 /// do other setup for EH landing-pad blocks.
679 void SelectionDAGISel::PrepareEHLandingPad() {
680 // Add a label to mark the beginning of the landing pad. Deletion of the
681 // landing pad can thus be detected via the MachineModuleInfo.
682 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
684 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
685 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
688 // Mark exception register as live in.
689 unsigned Reg = TLI.getExceptionAddressRegister();
690 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
692 // Mark exception selector register as live in.
693 Reg = TLI.getExceptionSelectorRegister();
694 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
696 // FIXME: Hack around an exception handling flaw (PR1508): the personality
697 // function and list of typeids logically belong to the invoke (or, if you
698 // like, the basic block containing the invoke), and need to be associated
699 // with it in the dwarf exception handling tables. Currently however the
700 // information is provided by an intrinsic (eh.selector) that can be moved
701 // to unexpected places by the optimizers: if the unwind edge is critical,
702 // then breaking it can result in the intrinsics being in the successor of
703 // the landing pad, not the landing pad itself. This results
704 // in exceptions not being caught because no typeids are associated with
705 // the invoke. This may not be the only way things can go wrong, but it
706 // is the only way we try to work around for the moment.
707 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
708 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
710 if (Br && Br->isUnconditional()) { // Critical edge?
711 BasicBlock::const_iterator I, E;
712 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
713 if (isa<EHSelectorInst>(I))
717 // No catch info found - try to extract some from the successor.
718 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
724 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
725 /// load into the specified FoldInst. Note that we could have a sequence where
726 /// multiple LLVM IR instructions are folded into the same machineinstr. For
727 /// example we could have:
728 /// A: x = load i32 *P
729 /// B: y = icmp A, 42
732 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
733 /// any other folded instructions) because it is between A and C.
735 /// If we succeed in folding the load into the operation, return true.
737 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
738 const Instruction *FoldInst,
740 // We know that the load has a single use, but don't know what it is. If it
741 // isn't one of the folded instructions, then we can't succeed here. Handle
742 // this by scanning the single-use users of the load until we get to FoldInst.
743 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
745 const Instruction *TheUser = LI->use_back();
746 while (TheUser != FoldInst && // Scan up until we find FoldInst.
747 // Stay in the right block.
748 TheUser->getParent() == FoldInst->getParent() &&
749 --MaxUsers) { // Don't scan too far.
750 // If there are multiple or no uses of this instruction, then bail out.
751 if (!TheUser->hasOneUse())
754 TheUser = TheUser->use_back();
757 // Don't try to fold volatile loads. Target has to deal with alignment
759 if (LI->isVolatile()) return false;
761 // Figure out which vreg this is going into. If there is no assigned vreg yet
762 // then there actually was no reference to it. Perhaps the load is referenced
763 // by a dead instruction.
764 unsigned LoadReg = FastIS->getRegForValue(LI);
768 // Check to see what the uses of this vreg are. If it has no uses, or more
769 // than one use (at the machine instr level) then we can't fold it.
770 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
771 if (RI == RegInfo->reg_end())
774 // See if there is exactly one use of the vreg. If there are multiple uses,
775 // then the instruction got lowered to multiple machine instructions or the
776 // use of the loaded value ended up being multiple operands of the result, in
777 // either case, we can't fold this.
778 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
779 if (PostRI != RegInfo->reg_end())
782 assert(RI.getOperand().isUse() &&
783 "The only use of the vreg must be a use, we haven't emitted the def!");
785 MachineInstr *User = &*RI;
787 // Set the insertion point properly. Folding the load can cause generation of
788 // other random instructions (like sign extends) for addressing modes, make
789 // sure they get inserted in a logical place before the new instruction.
790 FuncInfo->InsertPt = User;
791 FuncInfo->MBB = User->getParent();
793 // Ask the target to try folding the load.
794 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
797 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
798 /// side-effect free and is either dead or folded into a generated instruction.
799 /// Return false if it needs to be emitted.
800 static bool isFoldedOrDeadInstruction(const Instruction *I,
801 FunctionLoweringInfo *FuncInfo) {
802 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
803 !isa<TerminatorInst>(I) && // Terminators aren't folded.
804 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
805 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
808 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
809 // Initialize the Fast-ISel state, if needed.
810 FastISel *FastIS = 0;
812 FastIS = TLI.createFastISel(*FuncInfo);
814 // Iterate over all basic blocks in the function.
815 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
816 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
817 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
818 const BasicBlock *LLVMBB = *I;
820 if (OptLevel != CodeGenOpt::None) {
821 bool AllPredsVisited = true;
822 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
824 if (!FuncInfo->VisitedBBs.count(*PI)) {
825 AllPredsVisited = false;
830 if (AllPredsVisited) {
831 for (BasicBlock::const_iterator I = LLVMBB->begin();
832 isa<PHINode>(I); ++I)
833 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
835 for (BasicBlock::const_iterator I = LLVMBB->begin();
836 isa<PHINode>(I); ++I)
837 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));
840 FuncInfo->VisitedBBs.insert(LLVMBB);
843 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
844 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
846 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
847 BasicBlock::const_iterator const End = LLVMBB->end();
848 BasicBlock::const_iterator BI = End;
850 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
852 // Setup an EH landing-pad block.
853 if (FuncInfo->MBB->isLandingPad())
854 PrepareEHLandingPad();
856 // Lower any arguments needed in this block if this is the entry block.
857 if (LLVMBB == &Fn.getEntryBlock())
858 LowerArguments(LLVMBB);
860 // Before doing SelectionDAG ISel, see if FastISel has been requested.
862 FastIS->startNewBlock();
864 // Emit code for any incoming arguments. This must happen before
865 // beginning FastISel on the entry block.
866 if (LLVMBB == &Fn.getEntryBlock()) {
867 CurDAG->setRoot(SDB->getControlRoot());
871 // If we inserted any instructions at the beginning, make a note of
872 // where they are, so we can be sure to emit subsequent instructions
874 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
875 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
877 FastIS->setLastLocalValue(0);
880 // Do FastISel on as many instructions as possible.
881 for (; BI != Begin; --BI) {
882 const Instruction *Inst = llvm::prior(BI);
884 // If we no longer require this instruction, skip it.
885 if (isFoldedOrDeadInstruction(Inst, FuncInfo))
888 // Bottom-up: reset the insert pos at the top, after any local-value
890 FastIS->recomputeInsertPt();
892 // Try to select the instruction with FastISel.
893 if (FastIS->SelectInstruction(Inst)) {
894 ++NumFastIselSuccess;
895 // If fast isel succeeded, skip over all the folded instructions, and
896 // then see if there is a load right before the selected instructions.
897 // Try to fold the load if so.
898 const Instruction *BeforeInst = Inst;
899 while (BeforeInst != Begin) {
900 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
901 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
904 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
905 BeforeInst->hasOneUse() &&
906 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS))
907 // If we succeeded, don't re-select the load.
908 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
912 // Then handle certain instructions as single-LLVM-Instruction blocks.
913 if (isa<CallInst>(Inst)) {
914 ++NumFastIselFailures;
915 if (EnableFastISelVerbose || EnableFastISelAbort) {
916 dbgs() << "FastISel missed call: ";
920 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
921 unsigned &R = FuncInfo->ValueMap[Inst];
923 R = FuncInfo->CreateRegs(Inst->getType());
926 bool HadTailCall = false;
927 SelectBasicBlock(Inst, BI, HadTailCall);
929 // If the call was emitted as a tail call, we're done with the block.
938 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
939 // Don't abort, and use a different message for terminator misses.
940 ++NumFastIselFailures;
941 if (EnableFastISelVerbose || EnableFastISelAbort) {
942 dbgs() << "FastISel missed terminator: ";
946 ++NumFastIselFailures;
947 if (EnableFastISelVerbose || EnableFastISelAbort) {
948 dbgs() << "FastISel miss: ";
951 if (EnableFastISelAbort)
952 // The "fast" selector couldn't handle something and bailed.
953 // For the purpose of debugging, just abort.
954 llvm_unreachable("FastISel didn't select the entire block");
959 FastIS->recomputeInsertPt();
967 if (FastIS && LLVMBB != &Fn.getEntryBlock())
968 FastIS->recomputeDebugLocForMaterializedRegs();
970 // Run SelectionDAG instruction selection on the remainder of the block
971 // not handled by FastISel. If FastISel is not run, this is the entire
974 SelectBasicBlock(Begin, BI, HadTailCall);
978 FuncInfo->PHINodesToUpdate.clear();
982 SDB->clearDanglingDebugInfo();
986 SelectionDAGISel::FinishBasicBlock() {
988 DEBUG(dbgs() << "Total amount of phi nodes to update: "
989 << FuncInfo->PHINodesToUpdate.size() << "\n";
990 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
991 dbgs() << "Node " << i << " : ("
992 << FuncInfo->PHINodesToUpdate[i].first
993 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
995 // Next, now that we know what the last MBB the LLVM BB expanded is, update
996 // PHI nodes in successors.
997 if (SDB->SwitchCases.empty() &&
998 SDB->JTCases.empty() &&
999 SDB->BitTestCases.empty()) {
1000 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1001 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1002 assert(PHI->isPHI() &&
1003 "This is not a machine PHI node that we are updating!");
1004 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1007 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1008 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1013 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1014 // Lower header first, if it wasn't already lowered
1015 if (!SDB->BitTestCases[i].Emitted) {
1016 // Set the current basic block to the mbb we wish to insert the code into
1017 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1018 FuncInfo->InsertPt = FuncInfo->MBB->end();
1020 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1021 CurDAG->setRoot(SDB->getRoot());
1023 CodeGenAndEmitDAG();
1026 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1027 // Set the current basic block to the mbb we wish to insert the code into
1028 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1029 FuncInfo->InsertPt = FuncInfo->MBB->end();
1032 SDB->visitBitTestCase(SDB->BitTestCases[i],
1033 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1034 SDB->BitTestCases[i].Reg,
1035 SDB->BitTestCases[i].Cases[j],
1038 SDB->visitBitTestCase(SDB->BitTestCases[i],
1039 SDB->BitTestCases[i].Default,
1040 SDB->BitTestCases[i].Reg,
1041 SDB->BitTestCases[i].Cases[j],
1045 CurDAG->setRoot(SDB->getRoot());
1047 CodeGenAndEmitDAG();
1051 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1053 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1054 MachineBasicBlock *PHIBB = PHI->getParent();
1055 assert(PHI->isPHI() &&
1056 "This is not a machine PHI node that we are updating!");
1057 // This is "default" BB. We have two jumps to it. From "header" BB and
1058 // from last "case" BB.
1059 if (PHIBB == SDB->BitTestCases[i].Default) {
1060 PHI->addOperand(MachineOperand::
1061 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1063 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1064 PHI->addOperand(MachineOperand::
1065 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1067 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1070 // One of "cases" BB.
1071 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1073 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1074 if (cBB->isSuccessor(PHIBB)) {
1075 PHI->addOperand(MachineOperand::
1076 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1078 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1083 SDB->BitTestCases.clear();
1085 // If the JumpTable record is filled in, then we need to emit a jump table.
1086 // Updating the PHI nodes is tricky in this case, since we need to determine
1087 // whether the PHI is a successor of the range check MBB or the jump table MBB
1088 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1089 // Lower header first, if it wasn't already lowered
1090 if (!SDB->JTCases[i].first.Emitted) {
1091 // Set the current basic block to the mbb we wish to insert the code into
1092 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1093 FuncInfo->InsertPt = FuncInfo->MBB->end();
1095 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1097 CurDAG->setRoot(SDB->getRoot());
1099 CodeGenAndEmitDAG();
1102 // Set the current basic block to the mbb we wish to insert the code into
1103 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1104 FuncInfo->InsertPt = FuncInfo->MBB->end();
1106 SDB->visitJumpTable(SDB->JTCases[i].second);
1107 CurDAG->setRoot(SDB->getRoot());
1109 CodeGenAndEmitDAG();
1112 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1114 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1115 MachineBasicBlock *PHIBB = PHI->getParent();
1116 assert(PHI->isPHI() &&
1117 "This is not a machine PHI node that we are updating!");
1118 // "default" BB. We can go there only from header BB.
1119 if (PHIBB == SDB->JTCases[i].second.Default) {
1121 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1124 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1126 // JT BB. Just iterate over successors here
1127 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1129 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1131 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1135 SDB->JTCases.clear();
1137 // If the switch block involved a branch to one of the actual successors, we
1138 // need to update PHI nodes in that block.
1139 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1140 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1141 assert(PHI->isPHI() &&
1142 "This is not a machine PHI node that we are updating!");
1143 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1145 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1146 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1150 // If we generated any switch lowering information, build and codegen any
1151 // additional DAGs necessary.
1152 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1153 // Set the current basic block to the mbb we wish to insert the code into
1154 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1155 FuncInfo->InsertPt = FuncInfo->MBB->end();
1157 // Determine the unique successors.
1158 SmallVector<MachineBasicBlock *, 2> Succs;
1159 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1160 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1161 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1163 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1164 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1165 CurDAG->setRoot(SDB->getRoot());
1167 CodeGenAndEmitDAG();
1169 // Remember the last block, now that any splitting is done, for use in
1170 // populating PHI nodes in successors.
1171 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1173 // Handle any PHI nodes in successors of this chunk, as if we were coming
1174 // from the original BB before switch expansion. Note that PHI nodes can
1175 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1176 // handle them the right number of times.
1177 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1178 FuncInfo->MBB = Succs[i];
1179 FuncInfo->InsertPt = FuncInfo->MBB->end();
1180 // FuncInfo->MBB may have been removed from the CFG if a branch was
1182 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1183 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1184 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1186 // This value for this PHI node is recorded in PHINodesToUpdate.
1187 for (unsigned pn = 0; ; ++pn) {
1188 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1189 "Didn't find PHI entry!");
1190 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1191 Phi->addOperand(MachineOperand::
1192 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1194 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1202 SDB->SwitchCases.clear();
1206 /// Create the scheduler. If a specific scheduler was specified
1207 /// via the SchedulerRegistry, use it, otherwise select the
1208 /// one preferred by the target.
1210 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1211 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1215 RegisterScheduler::setDefault(Ctor);
1218 return Ctor(this, OptLevel);
1221 //===----------------------------------------------------------------------===//
1222 // Helper functions used by the generated instruction selector.
1223 //===----------------------------------------------------------------------===//
1224 // Calls to these methods are generated by tblgen.
1226 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1227 /// the dag combiner simplified the 255, we still want to match. RHS is the
1228 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1229 /// specified in the .td file (e.g. 255).
1230 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1231 int64_t DesiredMaskS) const {
1232 const APInt &ActualMask = RHS->getAPIntValue();
1233 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1235 // If the actual mask exactly matches, success!
1236 if (ActualMask == DesiredMask)
1239 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1240 if (ActualMask.intersects(~DesiredMask))
1243 // Otherwise, the DAG Combiner may have proven that the value coming in is
1244 // either already zero or is not demanded. Check for known zero input bits.
1245 APInt NeededMask = DesiredMask & ~ActualMask;
1246 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1249 // TODO: check to see if missing bits are just not demanded.
1251 // Otherwise, this pattern doesn't match.
1255 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1256 /// the dag combiner simplified the 255, we still want to match. RHS is the
1257 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1258 /// specified in the .td file (e.g. 255).
1259 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1260 int64_t DesiredMaskS) const {
1261 const APInt &ActualMask = RHS->getAPIntValue();
1262 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1264 // If the actual mask exactly matches, success!
1265 if (ActualMask == DesiredMask)
1268 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1269 if (ActualMask.intersects(~DesiredMask))
1272 // Otherwise, the DAG Combiner may have proven that the value coming in is
1273 // either already zero or is not demanded. Check for known zero input bits.
1274 APInt NeededMask = DesiredMask & ~ActualMask;
1276 APInt KnownZero, KnownOne;
1277 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1279 // If all the missing bits in the or are already known to be set, match!
1280 if ((NeededMask & KnownOne) == NeededMask)
1283 // TODO: check to see if missing bits are just not demanded.
1285 // Otherwise, this pattern doesn't match.
1290 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1291 /// by tblgen. Others should not call it.
1292 void SelectionDAGISel::
1293 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1294 std::vector<SDValue> InOps;
1295 std::swap(InOps, Ops);
1297 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1298 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1299 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1300 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1302 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1303 if (InOps[e-1].getValueType() == MVT::Glue)
1304 --e; // Don't process a glue operand if it is here.
1307 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1308 if (!InlineAsm::isMemKind(Flags)) {
1309 // Just skip over this operand, copying the operands verbatim.
1310 Ops.insert(Ops.end(), InOps.begin()+i,
1311 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1312 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1314 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1315 "Memory operand with multiple values?");
1316 // Otherwise, this is a memory operand. Ask the target to select it.
1317 std::vector<SDValue> SelOps;
1318 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1319 report_fatal_error("Could not match memory address. Inline asm"
1322 // Add this to the output node.
1324 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1325 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1326 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1331 // Add the glue input back if present.
1332 if (e != InOps.size())
1333 Ops.push_back(InOps.back());
1336 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1339 static SDNode *findGlueUse(SDNode *N) {
1340 unsigned FlagResNo = N->getNumValues()-1;
1341 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1342 SDUse &Use = I.getUse();
1343 if (Use.getResNo() == FlagResNo)
1344 return Use.getUser();
1349 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1350 /// This function recursively traverses up the operand chain, ignoring
1352 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1353 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1354 bool IgnoreChains) {
1355 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1356 // greater than all of its (recursive) operands. If we scan to a point where
1357 // 'use' is smaller than the node we're scanning for, then we know we will
1360 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1361 // happen because we scan down to newly selected nodes in the case of glue
1363 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1366 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1367 // won't fail if we scan it again.
1368 if (!Visited.insert(Use))
1371 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1372 // Ignore chain uses, they are validated by HandleMergeInputChains.
1373 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1376 SDNode *N = Use->getOperand(i).getNode();
1378 if (Use == ImmedUse || Use == Root)
1379 continue; // We are not looking for immediate use.
1384 // Traverse up the operand chain.
1385 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1391 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1392 /// operand node N of U during instruction selection that starts at Root.
1393 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1394 SDNode *Root) const {
1395 if (OptLevel == CodeGenOpt::None) return false;
1396 return N.hasOneUse();
1399 /// IsLegalToFold - Returns true if the specific operand node N of
1400 /// U can be folded during instruction selection that starts at Root.
1401 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1402 CodeGenOpt::Level OptLevel,
1403 bool IgnoreChains) {
1404 if (OptLevel == CodeGenOpt::None) return false;
1406 // If Root use can somehow reach N through a path that that doesn't contain
1407 // U then folding N would create a cycle. e.g. In the following
1408 // diagram, Root can reach N through X. If N is folded into into Root, then
1409 // X is both a predecessor and a successor of U.
1420 // * indicates nodes to be folded together.
1422 // If Root produces glue, then it gets (even more) interesting. Since it
1423 // will be "glued" together with its glue use in the scheduler, we need to
1424 // check if it might reach N.
1443 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1444 // (call it Fold), then X is a predecessor of GU and a successor of
1445 // Fold. But since Fold and GU are glued together, this will create
1446 // a cycle in the scheduling graph.
1448 // If the node has glue, walk down the graph to the "lowest" node in the
1450 EVT VT = Root->getValueType(Root->getNumValues()-1);
1451 while (VT == MVT::Glue) {
1452 SDNode *GU = findGlueUse(Root);
1456 VT = Root->getValueType(Root->getNumValues()-1);
1458 // If our query node has a glue result with a use, we've walked up it. If
1459 // the user (which has already been selected) has a chain or indirectly uses
1460 // the chain, our WalkChainUsers predicate will not consider it. Because of
1461 // this, we cannot ignore chains in this predicate.
1462 IgnoreChains = false;
1466 SmallPtrSet<SDNode*, 16> Visited;
1467 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1470 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1471 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1472 SelectInlineAsmMemoryOperands(Ops);
1474 std::vector<EVT> VTs;
1475 VTs.push_back(MVT::Other);
1476 VTs.push_back(MVT::Glue);
1477 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1478 VTs, &Ops[0], Ops.size());
1480 return New.getNode();
1483 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1484 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1487 /// GetVBR - decode a vbr encoding whose top bit is set.
1488 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1489 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1490 assert(Val >= 128 && "Not a VBR");
1491 Val &= 127; // Remove first vbr bit.
1496 NextBits = MatcherTable[Idx++];
1497 Val |= (NextBits&127) << Shift;
1499 } while (NextBits & 128);
1505 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1506 /// interior glue and chain results to use the new glue and chain results.
1507 void SelectionDAGISel::
1508 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1509 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1511 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1512 bool isMorphNodeTo) {
1513 SmallVector<SDNode*, 4> NowDeadNodes;
1515 ISelUpdater ISU(ISelPosition);
1517 // Now that all the normal results are replaced, we replace the chain and
1518 // glue results if present.
1519 if (!ChainNodesMatched.empty()) {
1520 assert(InputChain.getNode() != 0 &&
1521 "Matched input chains but didn't produce a chain");
1522 // Loop over all of the nodes we matched that produced a chain result.
1523 // Replace all the chain results with the final chain we ended up with.
1524 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1525 SDNode *ChainNode = ChainNodesMatched[i];
1527 // If this node was already deleted, don't look at it.
1528 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1531 // Don't replace the results of the root node if we're doing a
1533 if (ChainNode == NodeToMatch && isMorphNodeTo)
1536 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1537 if (ChainVal.getValueType() == MVT::Glue)
1538 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1539 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1540 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1542 // If the node became dead and we haven't already seen it, delete it.
1543 if (ChainNode->use_empty() &&
1544 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1545 NowDeadNodes.push_back(ChainNode);
1549 // If the result produces glue, update any glue results in the matched
1550 // pattern with the glue result.
1551 if (InputGlue.getNode() != 0) {
1552 // Handle any interior nodes explicitly marked.
1553 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1554 SDNode *FRN = GlueResultNodesMatched[i];
1556 // If this node was already deleted, don't look at it.
1557 if (FRN->getOpcode() == ISD::DELETED_NODE)
1560 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1561 "Doesn't have a glue result");
1562 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1565 // If the node became dead and we haven't already seen it, delete it.
1566 if (FRN->use_empty() &&
1567 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1568 NowDeadNodes.push_back(FRN);
1572 if (!NowDeadNodes.empty())
1573 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1575 DEBUG(errs() << "ISEL: Match complete!\n");
1581 CR_LeadsToInteriorNode
1584 /// WalkChainUsers - Walk down the users of the specified chained node that is
1585 /// part of the pattern we're matching, looking at all of the users we find.
1586 /// This determines whether something is an interior node, whether we have a
1587 /// non-pattern node in between two pattern nodes (which prevent folding because
1588 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1589 /// between pattern nodes (in which case the TF becomes part of the pattern).
1591 /// The walk we do here is guaranteed to be small because we quickly get down to
1592 /// already selected nodes "below" us.
1594 WalkChainUsers(SDNode *ChainedNode,
1595 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1596 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1597 ChainResult Result = CR_Simple;
1599 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1600 E = ChainedNode->use_end(); UI != E; ++UI) {
1601 // Make sure the use is of the chain, not some other value we produce.
1602 if (UI.getUse().getValueType() != MVT::Other) continue;
1606 // If we see an already-selected machine node, then we've gone beyond the
1607 // pattern that we're selecting down into the already selected chunk of the
1609 if (User->isMachineOpcode() ||
1610 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1613 if (User->getOpcode() == ISD::CopyToReg ||
1614 User->getOpcode() == ISD::CopyFromReg ||
1615 User->getOpcode() == ISD::INLINEASM ||
1616 User->getOpcode() == ISD::EH_LABEL) {
1617 // If their node ID got reset to -1 then they've already been selected.
1618 // Treat them like a MachineOpcode.
1619 if (User->getNodeId() == -1)
1623 // If we have a TokenFactor, we handle it specially.
1624 if (User->getOpcode() != ISD::TokenFactor) {
1625 // If the node isn't a token factor and isn't part of our pattern, then it
1626 // must be a random chained node in between two nodes we're selecting.
1627 // This happens when we have something like:
1632 // Because we structurally match the load/store as a read/modify/write,
1633 // but the call is chained between them. We cannot fold in this case
1634 // because it would induce a cycle in the graph.
1635 if (!std::count(ChainedNodesInPattern.begin(),
1636 ChainedNodesInPattern.end(), User))
1637 return CR_InducesCycle;
1639 // Otherwise we found a node that is part of our pattern. For example in:
1643 // This would happen when we're scanning down from the load and see the
1644 // store as a user. Record that there is a use of ChainedNode that is
1645 // part of the pattern and keep scanning uses.
1646 Result = CR_LeadsToInteriorNode;
1647 InteriorChainedNodes.push_back(User);
1651 // If we found a TokenFactor, there are two cases to consider: first if the
1652 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1653 // uses of the TF are in our pattern) we just want to ignore it. Second,
1654 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1660 // | \ DAG's like cheese
1663 // [TokenFactor] [Op]
1670 // In this case, the TokenFactor becomes part of our match and we rewrite it
1671 // as a new TokenFactor.
1673 // To distinguish these two cases, do a recursive walk down the uses.
1674 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1676 // If the uses of the TokenFactor are just already-selected nodes, ignore
1677 // it, it is "below" our pattern.
1679 case CR_InducesCycle:
1680 // If the uses of the TokenFactor lead to nodes that are not part of our
1681 // pattern that are not selected, folding would turn this into a cycle,
1683 return CR_InducesCycle;
1684 case CR_LeadsToInteriorNode:
1685 break; // Otherwise, keep processing.
1688 // Okay, we know we're in the interesting interior case. The TokenFactor
1689 // is now going to be considered part of the pattern so that we rewrite its
1690 // uses (it may have uses that are not part of the pattern) with the
1691 // ultimate chain result of the generated code. We will also add its chain
1692 // inputs as inputs to the ultimate TokenFactor we create.
1693 Result = CR_LeadsToInteriorNode;
1694 ChainedNodesInPattern.push_back(User);
1695 InteriorChainedNodes.push_back(User);
1702 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1703 /// operation for when the pattern matched at least one node with a chains. The
1704 /// input vector contains a list of all of the chained nodes that we match. We
1705 /// must determine if this is a valid thing to cover (i.e. matching it won't
1706 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1707 /// be used as the input node chain for the generated nodes.
1709 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1710 SelectionDAG *CurDAG) {
1711 // Walk all of the chained nodes we've matched, recursively scanning down the
1712 // users of the chain result. This adds any TokenFactor nodes that are caught
1713 // in between chained nodes to the chained and interior nodes list.
1714 SmallVector<SDNode*, 3> InteriorChainedNodes;
1715 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1716 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1717 InteriorChainedNodes) == CR_InducesCycle)
1718 return SDValue(); // Would induce a cycle.
1721 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1722 // that we are interested in. Form our input TokenFactor node.
1723 SmallVector<SDValue, 3> InputChains;
1724 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1725 // Add the input chain of this node to the InputChains list (which will be
1726 // the operands of the generated TokenFactor) if it's not an interior node.
1727 SDNode *N = ChainNodesMatched[i];
1728 if (N->getOpcode() != ISD::TokenFactor) {
1729 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1732 // Otherwise, add the input chain.
1733 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1734 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1735 InputChains.push_back(InChain);
1739 // If we have a token factor, we want to add all inputs of the token factor
1740 // that are not part of the pattern we're matching.
1741 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1742 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1743 N->getOperand(op).getNode()))
1744 InputChains.push_back(N->getOperand(op));
1749 if (InputChains.size() == 1)
1750 return InputChains[0];
1751 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1752 MVT::Other, &InputChains[0], InputChains.size());
1755 /// MorphNode - Handle morphing a node in place for the selector.
1756 SDNode *SelectionDAGISel::
1757 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1758 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1759 // It is possible we're using MorphNodeTo to replace a node with no
1760 // normal results with one that has a normal result (or we could be
1761 // adding a chain) and the input could have glue and chains as well.
1762 // In this case we need to shift the operands down.
1763 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1764 // than the old isel though.
1765 int OldGlueResultNo = -1, OldChainResultNo = -1;
1767 unsigned NTMNumResults = Node->getNumValues();
1768 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1769 OldGlueResultNo = NTMNumResults-1;
1770 if (NTMNumResults != 1 &&
1771 Node->getValueType(NTMNumResults-2) == MVT::Other)
1772 OldChainResultNo = NTMNumResults-2;
1773 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1774 OldChainResultNo = NTMNumResults-1;
1776 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1777 // that this deletes operands of the old node that become dead.
1778 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1780 // MorphNodeTo can operate in two ways: if an existing node with the
1781 // specified operands exists, it can just return it. Otherwise, it
1782 // updates the node in place to have the requested operands.
1784 // If we updated the node in place, reset the node ID. To the isel,
1785 // this should be just like a newly allocated machine node.
1789 unsigned ResNumResults = Res->getNumValues();
1790 // Move the glue if needed.
1791 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1792 (unsigned)OldGlueResultNo != ResNumResults-1)
1793 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1794 SDValue(Res, ResNumResults-1));
1796 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1799 // Move the chain reference if needed.
1800 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1801 (unsigned)OldChainResultNo != ResNumResults-1)
1802 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1803 SDValue(Res, ResNumResults-1));
1805 // Otherwise, no replacement happened because the node already exists. Replace
1806 // Uses of the old node with the new one.
1808 CurDAG->ReplaceAllUsesWith(Node, Res);
1813 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1814 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1815 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1817 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1818 // Accept if it is exactly the same as a previously recorded node.
1819 unsigned RecNo = MatcherTable[MatcherIndex++];
1820 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1821 return N == RecordedNodes[RecNo].first;
1824 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1825 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1826 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1827 SelectionDAGISel &SDISel) {
1828 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1831 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1832 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1833 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1834 SelectionDAGISel &SDISel, SDNode *N) {
1835 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1838 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1839 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1841 uint16_t Opc = MatcherTable[MatcherIndex++];
1842 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1843 return N->getOpcode() == Opc;
1846 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1847 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1848 SDValue N, const TargetLowering &TLI) {
1849 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1850 if (N.getValueType() == VT) return true;
1852 // Handle the case when VT is iPTR.
1853 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1856 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1857 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1858 SDValue N, const TargetLowering &TLI,
1860 if (ChildNo >= N.getNumOperands())
1861 return false; // Match fails if out of range child #.
1862 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1866 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1867 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1869 return cast<CondCodeSDNode>(N)->get() ==
1870 (ISD::CondCode)MatcherTable[MatcherIndex++];
1873 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1874 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1875 SDValue N, const TargetLowering &TLI) {
1876 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1877 if (cast<VTSDNode>(N)->getVT() == VT)
1880 // Handle the case when VT is iPTR.
1881 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1884 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1885 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1887 int64_t Val = MatcherTable[MatcherIndex++];
1889 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1891 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1892 return C != 0 && C->getSExtValue() == Val;
1895 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1896 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1897 SDValue N, SelectionDAGISel &SDISel) {
1898 int64_t Val = MatcherTable[MatcherIndex++];
1900 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1902 if (N->getOpcode() != ISD::AND) return false;
1904 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1905 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1908 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1909 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1910 SDValue N, SelectionDAGISel &SDISel) {
1911 int64_t Val = MatcherTable[MatcherIndex++];
1913 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1915 if (N->getOpcode() != ISD::OR) return false;
1917 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1918 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1921 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1922 /// scope, evaluate the current node. If the current predicate is known to
1923 /// fail, set Result=true and return anything. If the current predicate is
1924 /// known to pass, set Result=false and return the MatcherIndex to continue
1925 /// with. If the current predicate is unknown, set Result=false and return the
1926 /// MatcherIndex to continue with.
1927 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1928 unsigned Index, SDValue N,
1929 bool &Result, SelectionDAGISel &SDISel,
1930 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1931 switch (Table[Index++]) {
1934 return Index-1; // Could not evaluate this predicate.
1935 case SelectionDAGISel::OPC_CheckSame:
1936 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1938 case SelectionDAGISel::OPC_CheckPatternPredicate:
1939 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1941 case SelectionDAGISel::OPC_CheckPredicate:
1942 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1944 case SelectionDAGISel::OPC_CheckOpcode:
1945 Result = !::CheckOpcode(Table, Index, N.getNode());
1947 case SelectionDAGISel::OPC_CheckType:
1948 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1950 case SelectionDAGISel::OPC_CheckChild0Type:
1951 case SelectionDAGISel::OPC_CheckChild1Type:
1952 case SelectionDAGISel::OPC_CheckChild2Type:
1953 case SelectionDAGISel::OPC_CheckChild3Type:
1954 case SelectionDAGISel::OPC_CheckChild4Type:
1955 case SelectionDAGISel::OPC_CheckChild5Type:
1956 case SelectionDAGISel::OPC_CheckChild6Type:
1957 case SelectionDAGISel::OPC_CheckChild7Type:
1958 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1959 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1961 case SelectionDAGISel::OPC_CheckCondCode:
1962 Result = !::CheckCondCode(Table, Index, N);
1964 case SelectionDAGISel::OPC_CheckValueType:
1965 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1967 case SelectionDAGISel::OPC_CheckInteger:
1968 Result = !::CheckInteger(Table, Index, N);
1970 case SelectionDAGISel::OPC_CheckAndImm:
1971 Result = !::CheckAndImm(Table, Index, N, SDISel);
1973 case SelectionDAGISel::OPC_CheckOrImm:
1974 Result = !::CheckOrImm(Table, Index, N, SDISel);
1982 /// FailIndex - If this match fails, this is the index to continue with.
1985 /// NodeStack - The node stack when the scope was formed.
1986 SmallVector<SDValue, 4> NodeStack;
1988 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1989 unsigned NumRecordedNodes;
1991 /// NumMatchedMemRefs - The number of matched memref entries.
1992 unsigned NumMatchedMemRefs;
1994 /// InputChain/InputGlue - The current chain/glue
1995 SDValue InputChain, InputGlue;
1997 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1998 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2003 SDNode *SelectionDAGISel::
2004 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2005 unsigned TableSize) {
2006 // FIXME: Should these even be selected? Handle these cases in the caller?
2007 switch (NodeToMatch->getOpcode()) {
2010 case ISD::EntryToken: // These nodes remain the same.
2011 case ISD::BasicBlock:
2013 //case ISD::VALUETYPE:
2014 //case ISD::CONDCODE:
2015 case ISD::HANDLENODE:
2016 case ISD::MDNODE_SDNODE:
2017 case ISD::TargetConstant:
2018 case ISD::TargetConstantFP:
2019 case ISD::TargetConstantPool:
2020 case ISD::TargetFrameIndex:
2021 case ISD::TargetExternalSymbol:
2022 case ISD::TargetBlockAddress:
2023 case ISD::TargetJumpTable:
2024 case ISD::TargetGlobalTLSAddress:
2025 case ISD::TargetGlobalAddress:
2026 case ISD::TokenFactor:
2027 case ISD::CopyFromReg:
2028 case ISD::CopyToReg:
2030 NodeToMatch->setNodeId(-1); // Mark selected.
2032 case ISD::AssertSext:
2033 case ISD::AssertZext:
2034 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2035 NodeToMatch->getOperand(0));
2037 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2038 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2041 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2043 // Set up the node stack with NodeToMatch as the only node on the stack.
2044 SmallVector<SDValue, 8> NodeStack;
2045 SDValue N = SDValue(NodeToMatch, 0);
2046 NodeStack.push_back(N);
2048 // MatchScopes - Scopes used when matching, if a match failure happens, this
2049 // indicates where to continue checking.
2050 SmallVector<MatchScope, 8> MatchScopes;
2052 // RecordedNodes - This is the set of nodes that have been recorded by the
2053 // state machine. The second value is the parent of the node, or null if the
2054 // root is recorded.
2055 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2057 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2059 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2061 // These are the current input chain and glue for use when generating nodes.
2062 // Various Emit operations change these. For example, emitting a copytoreg
2063 // uses and updates these.
2064 SDValue InputChain, InputGlue;
2066 // ChainNodesMatched - If a pattern matches nodes that have input/output
2067 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2068 // which ones they are. The result is captured into this list so that we can
2069 // update the chain results when the pattern is complete.
2070 SmallVector<SDNode*, 3> ChainNodesMatched;
2071 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2073 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2074 NodeToMatch->dump(CurDAG);
2077 // Determine where to start the interpreter. Normally we start at opcode #0,
2078 // but if the state machine starts with an OPC_SwitchOpcode, then we
2079 // accelerate the first lookup (which is guaranteed to be hot) with the
2080 // OpcodeOffset table.
2081 unsigned MatcherIndex = 0;
2083 if (!OpcodeOffset.empty()) {
2084 // Already computed the OpcodeOffset table, just index into it.
2085 if (N.getOpcode() < OpcodeOffset.size())
2086 MatcherIndex = OpcodeOffset[N.getOpcode()];
2087 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2089 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2090 // Otherwise, the table isn't computed, but the state machine does start
2091 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2092 // is the first time we're selecting an instruction.
2095 // Get the size of this case.
2096 unsigned CaseSize = MatcherTable[Idx++];
2098 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2099 if (CaseSize == 0) break;
2101 // Get the opcode, add the index to the table.
2102 uint16_t Opc = MatcherTable[Idx++];
2103 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2104 if (Opc >= OpcodeOffset.size())
2105 OpcodeOffset.resize((Opc+1)*2);
2106 OpcodeOffset[Opc] = Idx;
2110 // Okay, do the lookup for the first opcode.
2111 if (N.getOpcode() < OpcodeOffset.size())
2112 MatcherIndex = OpcodeOffset[N.getOpcode()];
2116 assert(MatcherIndex < TableSize && "Invalid index");
2118 unsigned CurrentOpcodeIndex = MatcherIndex;
2120 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2123 // Okay, the semantics of this operation are that we should push a scope
2124 // then evaluate the first child. However, pushing a scope only to have
2125 // the first check fail (which then pops it) is inefficient. If we can
2126 // determine immediately that the first check (or first several) will
2127 // immediately fail, don't even bother pushing a scope for them.
2131 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2132 if (NumToSkip & 128)
2133 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2134 // Found the end of the scope with no match.
2135 if (NumToSkip == 0) {
2140 FailIndex = MatcherIndex+NumToSkip;
2142 unsigned MatcherIndexOfPredicate = MatcherIndex;
2143 (void)MatcherIndexOfPredicate; // silence warning.
2145 // If we can't evaluate this predicate without pushing a scope (e.g. if
2146 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2147 // push the scope and evaluate the full predicate chain.
2149 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2150 Result, *this, RecordedNodes);
2154 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2155 << "index " << MatcherIndexOfPredicate
2156 << ", continuing at " << FailIndex << "\n");
2157 ++NumDAGIselRetries;
2159 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2160 // move to the next case.
2161 MatcherIndex = FailIndex;
2164 // If the whole scope failed to match, bail.
2165 if (FailIndex == 0) break;
2167 // Push a MatchScope which indicates where to go if the first child fails
2169 MatchScope NewEntry;
2170 NewEntry.FailIndex = FailIndex;
2171 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2172 NewEntry.NumRecordedNodes = RecordedNodes.size();
2173 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2174 NewEntry.InputChain = InputChain;
2175 NewEntry.InputGlue = InputGlue;
2176 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2177 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2178 MatchScopes.push_back(NewEntry);
2181 case OPC_RecordNode: {
2182 // Remember this node, it may end up being an operand in the pattern.
2184 if (NodeStack.size() > 1)
2185 Parent = NodeStack[NodeStack.size()-2].getNode();
2186 RecordedNodes.push_back(std::make_pair(N, Parent));
2190 case OPC_RecordChild0: case OPC_RecordChild1:
2191 case OPC_RecordChild2: case OPC_RecordChild3:
2192 case OPC_RecordChild4: case OPC_RecordChild5:
2193 case OPC_RecordChild6: case OPC_RecordChild7: {
2194 unsigned ChildNo = Opcode-OPC_RecordChild0;
2195 if (ChildNo >= N.getNumOperands())
2196 break; // Match fails if out of range child #.
2198 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2202 case OPC_RecordMemRef:
2203 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2206 case OPC_CaptureGlueInput:
2207 // If the current node has an input glue, capture it in InputGlue.
2208 if (N->getNumOperands() != 0 &&
2209 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2210 InputGlue = N->getOperand(N->getNumOperands()-1);
2213 case OPC_MoveChild: {
2214 unsigned ChildNo = MatcherTable[MatcherIndex++];
2215 if (ChildNo >= N.getNumOperands())
2216 break; // Match fails if out of range child #.
2217 N = N.getOperand(ChildNo);
2218 NodeStack.push_back(N);
2222 case OPC_MoveParent:
2223 // Pop the current node off the NodeStack.
2224 NodeStack.pop_back();
2225 assert(!NodeStack.empty() && "Node stack imbalance!");
2226 N = NodeStack.back();
2230 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2232 case OPC_CheckPatternPredicate:
2233 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2235 case OPC_CheckPredicate:
2236 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2240 case OPC_CheckComplexPat: {
2241 unsigned CPNum = MatcherTable[MatcherIndex++];
2242 unsigned RecNo = MatcherTable[MatcherIndex++];
2243 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2244 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2245 RecordedNodes[RecNo].first, CPNum,
2250 case OPC_CheckOpcode:
2251 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2255 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2258 case OPC_SwitchOpcode: {
2259 unsigned CurNodeOpcode = N.getOpcode();
2260 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2263 // Get the size of this case.
2264 CaseSize = MatcherTable[MatcherIndex++];
2266 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2267 if (CaseSize == 0) break;
2269 uint16_t Opc = MatcherTable[MatcherIndex++];
2270 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2272 // If the opcode matches, then we will execute this case.
2273 if (CurNodeOpcode == Opc)
2276 // Otherwise, skip over this case.
2277 MatcherIndex += CaseSize;
2280 // If no cases matched, bail out.
2281 if (CaseSize == 0) break;
2283 // Otherwise, execute the case we found.
2284 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2285 << " to " << MatcherIndex << "\n");
2289 case OPC_SwitchType: {
2290 MVT CurNodeVT = N.getValueType().getSimpleVT();
2291 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2294 // Get the size of this case.
2295 CaseSize = MatcherTable[MatcherIndex++];
2297 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2298 if (CaseSize == 0) break;
2300 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2301 if (CaseVT == MVT::iPTR)
2302 CaseVT = TLI.getPointerTy();
2304 // If the VT matches, then we will execute this case.
2305 if (CurNodeVT == CaseVT)
2308 // Otherwise, skip over this case.
2309 MatcherIndex += CaseSize;
2312 // If no cases matched, bail out.
2313 if (CaseSize == 0) break;
2315 // Otherwise, execute the case we found.
2316 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2317 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2320 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2321 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2322 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2323 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2324 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2325 Opcode-OPC_CheckChild0Type))
2328 case OPC_CheckCondCode:
2329 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2331 case OPC_CheckValueType:
2332 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2334 case OPC_CheckInteger:
2335 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2337 case OPC_CheckAndImm:
2338 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2340 case OPC_CheckOrImm:
2341 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2344 case OPC_CheckFoldableChainNode: {
2345 assert(NodeStack.size() != 1 && "No parent node");
2346 // Verify that all intermediate nodes between the root and this one have
2348 bool HasMultipleUses = false;
2349 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2350 if (!NodeStack[i].hasOneUse()) {
2351 HasMultipleUses = true;
2354 if (HasMultipleUses) break;
2356 // Check to see that the target thinks this is profitable to fold and that
2357 // we can fold it without inducing cycles in the graph.
2358 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2360 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2361 NodeToMatch, OptLevel,
2362 true/*We validate our own chains*/))
2367 case OPC_EmitInteger: {
2368 MVT::SimpleValueType VT =
2369 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2370 int64_t Val = MatcherTable[MatcherIndex++];
2372 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2373 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2374 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2377 case OPC_EmitRegister: {
2378 MVT::SimpleValueType VT =
2379 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2380 unsigned RegNo = MatcherTable[MatcherIndex++];
2381 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2382 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2385 case OPC_EmitRegister2: {
2386 // For targets w/ more than 256 register names, the register enum
2387 // values are stored in two bytes in the matcher table (just like
2389 MVT::SimpleValueType VT =
2390 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2391 unsigned RegNo = MatcherTable[MatcherIndex++];
2392 RegNo |= MatcherTable[MatcherIndex++] << 8;
2393 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2394 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2398 case OPC_EmitConvertToTarget: {
2399 // Convert from IMM/FPIMM to target version.
2400 unsigned RecNo = MatcherTable[MatcherIndex++];
2401 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2402 SDValue Imm = RecordedNodes[RecNo].first;
2404 if (Imm->getOpcode() == ISD::Constant) {
2405 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2406 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2407 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2408 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2409 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2412 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2416 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2417 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2418 // These are space-optimized forms of OPC_EmitMergeInputChains.
2419 assert(InputChain.getNode() == 0 &&
2420 "EmitMergeInputChains should be the first chain producing node");
2421 assert(ChainNodesMatched.empty() &&
2422 "Should only have one EmitMergeInputChains per match");
2424 // Read all of the chained nodes.
2425 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2426 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2427 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2429 // FIXME: What if other value results of the node have uses not matched
2431 if (ChainNodesMatched.back() != NodeToMatch &&
2432 !RecordedNodes[RecNo].first.hasOneUse()) {
2433 ChainNodesMatched.clear();
2437 // Merge the input chains if they are not intra-pattern references.
2438 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2440 if (InputChain.getNode() == 0)
2441 break; // Failed to merge.
2445 case OPC_EmitMergeInputChains: {
2446 assert(InputChain.getNode() == 0 &&
2447 "EmitMergeInputChains should be the first chain producing node");
2448 // This node gets a list of nodes we matched in the input that have
2449 // chains. We want to token factor all of the input chains to these nodes
2450 // together. However, if any of the input chains is actually one of the
2451 // nodes matched in this pattern, then we have an intra-match reference.
2452 // Ignore these because the newly token factored chain should not refer to
2454 unsigned NumChains = MatcherTable[MatcherIndex++];
2455 assert(NumChains != 0 && "Can't TF zero chains");
2457 assert(ChainNodesMatched.empty() &&
2458 "Should only have one EmitMergeInputChains per match");
2460 // Read all of the chained nodes.
2461 for (unsigned i = 0; i != NumChains; ++i) {
2462 unsigned RecNo = MatcherTable[MatcherIndex++];
2463 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2464 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2466 // FIXME: What if other value results of the node have uses not matched
2468 if (ChainNodesMatched.back() != NodeToMatch &&
2469 !RecordedNodes[RecNo].first.hasOneUse()) {
2470 ChainNodesMatched.clear();
2475 // If the inner loop broke out, the match fails.
2476 if (ChainNodesMatched.empty())
2479 // Merge the input chains if they are not intra-pattern references.
2480 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2482 if (InputChain.getNode() == 0)
2483 break; // Failed to merge.
2488 case OPC_EmitCopyToReg: {
2489 unsigned RecNo = MatcherTable[MatcherIndex++];
2490 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2491 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2493 if (InputChain.getNode() == 0)
2494 InputChain = CurDAG->getEntryNode();
2496 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2497 DestPhysReg, RecordedNodes[RecNo].first,
2500 InputGlue = InputChain.getValue(1);
2504 case OPC_EmitNodeXForm: {
2505 unsigned XFormNo = MatcherTable[MatcherIndex++];
2506 unsigned RecNo = MatcherTable[MatcherIndex++];
2507 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2508 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2509 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2514 case OPC_MorphNodeTo: {
2515 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2516 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2517 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2518 // Get the result VT list.
2519 unsigned NumVTs = MatcherTable[MatcherIndex++];
2520 SmallVector<EVT, 4> VTs;
2521 for (unsigned i = 0; i != NumVTs; ++i) {
2522 MVT::SimpleValueType VT =
2523 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2524 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2528 if (EmitNodeInfo & OPFL_Chain)
2529 VTs.push_back(MVT::Other);
2530 if (EmitNodeInfo & OPFL_GlueOutput)
2531 VTs.push_back(MVT::Glue);
2533 // This is hot code, so optimize the two most common cases of 1 and 2
2536 if (VTs.size() == 1)
2537 VTList = CurDAG->getVTList(VTs[0]);
2538 else if (VTs.size() == 2)
2539 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2541 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2543 // Get the operand list.
2544 unsigned NumOps = MatcherTable[MatcherIndex++];
2545 SmallVector<SDValue, 8> Ops;
2546 for (unsigned i = 0; i != NumOps; ++i) {
2547 unsigned RecNo = MatcherTable[MatcherIndex++];
2549 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2551 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2552 Ops.push_back(RecordedNodes[RecNo].first);
2555 // If there are variadic operands to add, handle them now.
2556 if (EmitNodeInfo & OPFL_VariadicInfo) {
2557 // Determine the start index to copy from.
2558 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2559 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2560 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2561 "Invalid variadic node");
2562 // Copy all of the variadic operands, not including a potential glue
2564 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2566 SDValue V = NodeToMatch->getOperand(i);
2567 if (V.getValueType() == MVT::Glue) break;
2572 // If this has chain/glue inputs, add them.
2573 if (EmitNodeInfo & OPFL_Chain)
2574 Ops.push_back(InputChain);
2575 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2576 Ops.push_back(InputGlue);
2580 if (Opcode != OPC_MorphNodeTo) {
2581 // If this is a normal EmitNode command, just create the new node and
2582 // add the results to the RecordedNodes list.
2583 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2584 VTList, Ops.data(), Ops.size());
2586 // Add all the non-glue/non-chain results to the RecordedNodes list.
2587 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2588 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2589 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2594 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2598 // If the node had chain/glue results, update our notion of the current
2600 if (EmitNodeInfo & OPFL_GlueOutput) {
2601 InputGlue = SDValue(Res, VTs.size()-1);
2602 if (EmitNodeInfo & OPFL_Chain)
2603 InputChain = SDValue(Res, VTs.size()-2);
2604 } else if (EmitNodeInfo & OPFL_Chain)
2605 InputChain = SDValue(Res, VTs.size()-1);
2607 // If the OPFL_MemRefs glue is set on this node, slap all of the
2608 // accumulated memrefs onto it.
2610 // FIXME: This is vastly incorrect for patterns with multiple outputs
2611 // instructions that access memory and for ComplexPatterns that match
2613 if (EmitNodeInfo & OPFL_MemRefs) {
2614 // Only attach load or store memory operands if the generated
2615 // instruction may load or store.
2616 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2617 bool mayLoad = MCID.mayLoad();
2618 bool mayStore = MCID.mayStore();
2620 unsigned NumMemRefs = 0;
2621 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2622 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2623 if ((*I)->isLoad()) {
2626 } else if ((*I)->isStore()) {
2634 MachineSDNode::mmo_iterator MemRefs =
2635 MF->allocateMemRefsArray(NumMemRefs);
2637 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2638 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2639 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2640 if ((*I)->isLoad()) {
2643 } else if ((*I)->isStore()) {
2651 cast<MachineSDNode>(Res)
2652 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2656 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2657 << " node: "; Res->dump(CurDAG); errs() << "\n");
2659 // If this was a MorphNodeTo then we're completely done!
2660 if (Opcode == OPC_MorphNodeTo) {
2661 // Update chain and glue uses.
2662 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2663 InputGlue, GlueResultNodesMatched, true);
2670 case OPC_MarkGlueResults: {
2671 unsigned NumNodes = MatcherTable[MatcherIndex++];
2673 // Read and remember all the glue-result nodes.
2674 for (unsigned i = 0; i != NumNodes; ++i) {
2675 unsigned RecNo = MatcherTable[MatcherIndex++];
2677 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2679 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2680 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2685 case OPC_CompleteMatch: {
2686 // The match has been completed, and any new nodes (if any) have been
2687 // created. Patch up references to the matched dag to use the newly
2689 unsigned NumResults = MatcherTable[MatcherIndex++];
2691 for (unsigned i = 0; i != NumResults; ++i) {
2692 unsigned ResSlot = MatcherTable[MatcherIndex++];
2694 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2696 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2697 SDValue Res = RecordedNodes[ResSlot].first;
2699 assert(i < NodeToMatch->getNumValues() &&
2700 NodeToMatch->getValueType(i) != MVT::Other &&
2701 NodeToMatch->getValueType(i) != MVT::Glue &&
2702 "Invalid number of results to complete!");
2703 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2704 NodeToMatch->getValueType(i) == MVT::iPTR ||
2705 Res.getValueType() == MVT::iPTR ||
2706 NodeToMatch->getValueType(i).getSizeInBits() ==
2707 Res.getValueType().getSizeInBits()) &&
2708 "invalid replacement");
2709 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2712 // If the root node defines glue, add it to the glue nodes to update list.
2713 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2714 GlueResultNodesMatched.push_back(NodeToMatch);
2716 // Update chain and glue uses.
2717 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2718 InputGlue, GlueResultNodesMatched, false);
2720 assert(NodeToMatch->use_empty() &&
2721 "Didn't replace all uses of the node?");
2723 // FIXME: We just return here, which interacts correctly with SelectRoot
2724 // above. We should fix this to not return an SDNode* anymore.
2729 // If the code reached this point, then the match failed. See if there is
2730 // another child to try in the current 'Scope', otherwise pop it until we
2731 // find a case to check.
2732 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2733 ++NumDAGIselRetries;
2735 if (MatchScopes.empty()) {
2736 CannotYetSelect(NodeToMatch);
2740 // Restore the interpreter state back to the point where the scope was
2742 MatchScope &LastScope = MatchScopes.back();
2743 RecordedNodes.resize(LastScope.NumRecordedNodes);
2745 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2746 N = NodeStack.back();
2748 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2749 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2750 MatcherIndex = LastScope.FailIndex;
2752 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2754 InputChain = LastScope.InputChain;
2755 InputGlue = LastScope.InputGlue;
2756 if (!LastScope.HasChainNodesMatched)
2757 ChainNodesMatched.clear();
2758 if (!LastScope.HasGlueResultNodesMatched)
2759 GlueResultNodesMatched.clear();
2761 // Check to see what the offset is at the new MatcherIndex. If it is zero
2762 // we have reached the end of this scope, otherwise we have another child
2763 // in the current scope to try.
2764 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2765 if (NumToSkip & 128)
2766 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2768 // If we have another child in this scope to match, update FailIndex and
2770 if (NumToSkip != 0) {
2771 LastScope.FailIndex = MatcherIndex+NumToSkip;
2775 // End of this scope, pop it and try the next child in the containing
2777 MatchScopes.pop_back();
2784 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2786 raw_string_ostream Msg(msg);
2787 Msg << "Cannot select: ";
2789 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2790 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2791 N->getOpcode() != ISD::INTRINSIC_VOID) {
2792 N->printrFull(Msg, CurDAG);
2794 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2796 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2797 if (iid < Intrinsic::num_intrinsics)
2798 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2799 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2800 Msg << "target intrinsic %" << TII->getName(iid);
2802 Msg << "unknown intrinsic #" << iid;
2804 report_fatal_error(Msg.str());
2807 char SelectionDAGISel::ID = 0;