1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/CodeGen/ScheduleDAG.h"
17 #include "llvm/CallingConv.h"
18 #include "llvm/Constants.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/InlineAsm.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineDebugInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/CodeGen/SSARegMap.h"
34 #include "llvm/Target/MRegisterInfo.h"
35 #include "llvm/Target/TargetData.h"
36 #include "llvm/Target/TargetFrameInfo.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetLowering.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/Debug.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
62 // Scheduling heuristics
63 enum SchedHeuristics {
64 defaultScheduling, // Let the target specify its preference.
65 noScheduling, // No scheduling, emit breadth first sequence.
66 simpleScheduling, // Two pass, min. critical path, max. utilization.
67 simpleNoItinScheduling, // Same as above exact using generic latency.
68 listSchedulingBURR, // Bottom-up reg reduction list scheduling.
69 listSchedulingTDRR, // Top-down reg reduction list scheduling.
70 listSchedulingTD // Top-down list scheduler.
74 cl::opt<SchedHeuristics>
77 cl::desc("Choose scheduling style"),
78 cl::init(defaultScheduling),
80 clEnumValN(defaultScheduling, "default",
81 "Target preferred scheduling style"),
82 clEnumValN(noScheduling, "none",
83 "No scheduling: breadth first sequencing"),
84 clEnumValN(simpleScheduling, "simple",
85 "Simple two pass scheduling: minimize critical path "
86 "and maximize processor utilization"),
87 clEnumValN(simpleNoItinScheduling, "simple-noitin",
88 "Simple two pass scheduling: Same as simple "
89 "except using generic latency"),
90 clEnumValN(listSchedulingBURR, "list-burr",
91 "Bottom-up register reduction list scheduling"),
92 clEnumValN(listSchedulingTDRR, "list-tdrr",
93 "Top-down register reduction list scheduling"),
94 clEnumValN(listSchedulingTD, "list-td",
95 "Top-down list scheduler"),
100 /// RegsForValue - This struct represents the physical registers that a
101 /// particular value is assigned and the type information about the value.
102 /// This is needed because values can be promoted into larger registers and
103 /// expanded into multiple smaller registers than the value.
104 struct RegsForValue {
105 /// Regs - This list hold the register (for legal and promoted values)
106 /// or register set (for expanded values) that the value should be assigned
108 std::vector<unsigned> Regs;
110 /// RegVT - The value type of each register.
112 MVT::ValueType RegVT;
114 /// ValueVT - The value type of the LLVM value, which may be promoted from
115 /// RegVT or made from merging the two expanded parts.
116 MVT::ValueType ValueVT;
118 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
120 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
121 : RegVT(regvt), ValueVT(valuevt) {
124 RegsForValue(const std::vector<unsigned> ®s,
125 MVT::ValueType regvt, MVT::ValueType valuevt)
126 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
129 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
130 /// this value and returns the result as a ValueVT value. This uses
131 /// Chain/Flag as the input and updates them for the output Chain/Flag.
132 SDOperand getCopyFromRegs(SelectionDAG &DAG,
133 SDOperand &Chain, SDOperand &Flag) const;
135 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
136 /// specified value into the registers specified by this object. This uses
137 /// Chain/Flag as the input and updates them for the output Chain/Flag.
138 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
139 SDOperand &Chain, SDOperand &Flag) const;
141 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
142 /// operand list. This adds the code marker and includes the number of
143 /// values added into it.
144 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
145 std::vector<SDOperand> &Ops) const;
150 //===--------------------------------------------------------------------===//
151 /// FunctionLoweringInfo - This contains information that is global to a
152 /// function that is used when lowering a region of the function.
153 class FunctionLoweringInfo {
160 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
162 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
163 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
165 /// ValueMap - Since we emit code for the function a basic block at a time,
166 /// we must remember which virtual registers hold the values for
167 /// cross-basic-block values.
168 std::map<const Value*, unsigned> ValueMap;
170 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
171 /// the entry block. This allows the allocas to be efficiently referenced
172 /// anywhere in the function.
173 std::map<const AllocaInst*, int> StaticAllocaMap;
175 unsigned MakeReg(MVT::ValueType VT) {
176 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
179 unsigned CreateRegForValue(const Value *V);
181 unsigned InitializeRegForValue(const Value *V) {
182 unsigned &R = ValueMap[V];
183 assert(R == 0 && "Already initialized this value register!");
184 return R = CreateRegForValue(V);
189 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
190 /// PHI nodes or outside of the basic block that defines it, or used by a
191 /// switch instruction, which may expand to multiple basic blocks.
192 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
193 if (isa<PHINode>(I)) return true;
194 BasicBlock *BB = I->getParent();
195 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
196 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
197 isa<SwitchInst>(*UI))
202 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
203 /// entry block, return true. This includes arguments used by switches, since
204 /// the switch may expand into multiple basic blocks.
205 static bool isOnlyUsedInEntryBlock(Argument *A) {
206 BasicBlock *Entry = A->getParent()->begin();
207 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
208 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
209 return false; // Use not in entry block.
213 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
214 Function &fn, MachineFunction &mf)
215 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
217 // Create a vreg for each argument register that is not dead and is used
218 // outside of the entry block for the function.
219 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
221 if (!isOnlyUsedInEntryBlock(AI))
222 InitializeRegForValue(AI);
224 // Initialize the mapping of values to registers. This is only set up for
225 // instruction values that are used outside of the block that defines
227 Function::iterator BB = Fn.begin(), EB = Fn.end();
228 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
229 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
230 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
231 const Type *Ty = AI->getAllocatedType();
232 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
234 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
237 // If the alignment of the value is smaller than the size of the value,
238 // and if the size of the value is particularly small (<= 8 bytes),
239 // round up to the size of the value for potentially better performance.
241 // FIXME: This could be made better with a preferred alignment hook in
242 // TargetData. It serves primarily to 8-byte align doubles for X86.
243 if (Align < TySize && TySize <= 8) Align = TySize;
244 TySize *= CUI->getValue(); // Get total allocated size.
245 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
246 StaticAllocaMap[AI] =
247 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
250 for (; BB != EB; ++BB)
251 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
252 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
253 if (!isa<AllocaInst>(I) ||
254 !StaticAllocaMap.count(cast<AllocaInst>(I)))
255 InitializeRegForValue(I);
257 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
258 // also creates the initial PHI MachineInstrs, though none of the input
259 // operands are populated.
260 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
261 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
263 MF.getBasicBlockList().push_back(MBB);
265 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
268 for (BasicBlock::iterator I = BB->begin();
269 (PN = dyn_cast<PHINode>(I)); ++I)
270 if (!PN->use_empty()) {
271 MVT::ValueType VT = TLI.getValueType(PN->getType());
272 unsigned NumElements;
273 if (VT != MVT::Vector)
274 NumElements = TLI.getNumElements(VT);
276 MVT::ValueType VT1,VT2;
278 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
281 unsigned PHIReg = ValueMap[PN];
282 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
283 for (unsigned i = 0; i != NumElements; ++i)
284 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
289 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
290 /// the correctly promoted or expanded types. Assign these registers
291 /// consecutive vreg numbers and return the first assigned number.
292 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
293 MVT::ValueType VT = TLI.getValueType(V->getType());
295 // The number of multiples of registers that we need, to, e.g., split up
296 // a <2 x int64> -> 4 x i32 registers.
297 unsigned NumVectorRegs = 1;
299 // If this is a packed type, figure out what type it will decompose into
300 // and how many of the elements it will use.
301 if (VT == MVT::Vector) {
302 const PackedType *PTy = cast<PackedType>(V->getType());
303 unsigned NumElts = PTy->getNumElements();
304 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
306 // Divide the input until we get to a supported size. This will always
307 // end with a scalar if the target doesn't support vectors.
308 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
315 VT = getVectorType(EltTy, NumElts);
318 // The common case is that we will only create one register for this
319 // value. If we have that case, create and return the virtual register.
320 unsigned NV = TLI.getNumElements(VT);
322 // If we are promoting this value, pick the next largest supported type.
323 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
324 unsigned Reg = MakeReg(PromotedType);
325 // If this is a vector of supported or promoted types (e.g. 4 x i16),
326 // create all of the registers.
327 for (unsigned i = 1; i != NumVectorRegs; ++i)
328 MakeReg(PromotedType);
332 // If this value is represented with multiple target registers, make sure
333 // to create enough consecutive registers of the right (smaller) type.
334 unsigned NT = VT-1; // Find the type to use.
335 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
338 unsigned R = MakeReg((MVT::ValueType)NT);
339 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
340 MakeReg((MVT::ValueType)NT);
344 //===----------------------------------------------------------------------===//
345 /// SelectionDAGLowering - This is the common target-independent lowering
346 /// implementation that is parameterized by a TargetLowering object.
347 /// Also, targets can overload any lowering method.
350 class SelectionDAGLowering {
351 MachineBasicBlock *CurMBB;
353 std::map<const Value*, SDOperand> NodeMap;
355 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
356 /// them up and then emit token factor nodes when possible. This allows us to
357 /// get simple disambiguation between loads without worrying about alias
359 std::vector<SDOperand> PendingLoads;
361 /// Case - A pair of values to record the Value for a switch case, and the
362 /// case's target basic block.
363 typedef std::pair<Constant*, MachineBasicBlock*> Case;
364 typedef std::vector<Case>::iterator CaseItr;
365 typedef std::pair<CaseItr, CaseItr> CaseRange;
367 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
368 /// of conditional branches.
370 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
371 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
373 /// CaseBB - The MBB in which to emit the compare and branch
374 MachineBasicBlock *CaseBB;
375 /// LT, GE - If nonzero, we know the current case value must be less-than or
376 /// greater-than-or-equal-to these Constants.
379 /// Range - A pair of iterators representing the range of case values to be
380 /// processed at this point in the binary search tree.
384 /// The comparison function for sorting Case values.
386 bool operator () (const Case& C1, const Case& C2) {
387 if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first))
388 return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue();
390 const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first);
391 return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue();
396 // TLI - This is information that describes the available target features we
397 // need for lowering. This indicates when operations are unavailable,
398 // implemented with a libcall, etc.
401 const TargetData *TD;
403 /// SwitchCases - Vector of CaseBlock structures used to communicate
404 /// SwitchInst code generation information.
405 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
406 SelectionDAGISel::JumpTable JT;
408 /// FuncInfo - Information about the function as a whole.
410 FunctionLoweringInfo &FuncInfo;
412 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
413 FunctionLoweringInfo &funcinfo)
414 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
415 JT(0,0,0,0), FuncInfo(funcinfo) {
418 /// getRoot - Return the current virtual root of the Selection DAG.
420 SDOperand getRoot() {
421 if (PendingLoads.empty())
422 return DAG.getRoot();
424 if (PendingLoads.size() == 1) {
425 SDOperand Root = PendingLoads[0];
427 PendingLoads.clear();
431 // Otherwise, we have to make a token factor node.
432 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
433 PendingLoads.clear();
438 void visit(Instruction &I) { visit(I.getOpcode(), I); }
440 void visit(unsigned Opcode, User &I) {
442 default: assert(0 && "Unknown instruction type encountered!");
444 // Build the switch statement using the Instruction.def file.
445 #define HANDLE_INST(NUM, OPCODE, CLASS) \
446 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
447 #include "llvm/Instruction.def"
451 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
453 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
454 SDOperand SrcValue, SDOperand Root,
457 SDOperand getIntPtrConstant(uint64_t Val) {
458 return DAG.getConstant(Val, TLI.getPointerTy());
461 SDOperand getValue(const Value *V);
463 const SDOperand &setValue(const Value *V, SDOperand NewN) {
464 SDOperand &N = NodeMap[V];
465 assert(N.Val == 0 && "Already set a value for this node!");
469 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
471 bool OutReg, bool InReg,
472 std::set<unsigned> &OutputRegs,
473 std::set<unsigned> &InputRegs);
475 // Terminator instructions.
476 void visitRet(ReturnInst &I);
477 void visitBr(BranchInst &I);
478 void visitSwitch(SwitchInst &I);
479 void visitUnreachable(UnreachableInst &I) { /* noop */ }
481 // Helper for visitSwitch
482 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
483 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
485 // These all get lowered before this pass.
486 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
487 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
489 void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
490 void visitShift(User &I, unsigned Opcode);
491 void visitAdd(User &I) {
492 visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
494 void visitSub(User &I);
495 void visitMul(User &I) {
496 visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
498 void visitDiv(User &I) {
499 const Type *Ty = I.getType();
501 Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
502 Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
504 void visitRem(User &I) {
505 const Type *Ty = I.getType();
506 visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
508 void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
509 void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
510 void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
511 void visitShl(User &I) { visitShift(I, ISD::SHL); }
512 void visitShr(User &I) {
513 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
516 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc,
517 ISD::CondCode FPOpc);
518 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ,
520 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE,
522 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE,
524 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE,
526 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT,
528 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT,
531 void visitExtractElement(User &I);
532 void visitInsertElement(User &I);
533 void visitShuffleVector(User &I);
535 void visitGetElementPtr(User &I);
536 void visitCast(User &I);
537 void visitSelect(User &I);
539 void visitMalloc(MallocInst &I);
540 void visitFree(FreeInst &I);
541 void visitAlloca(AllocaInst &I);
542 void visitLoad(LoadInst &I);
543 void visitStore(StoreInst &I);
544 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
545 void visitCall(CallInst &I);
546 void visitInlineAsm(CallInst &I);
547 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
548 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
550 void visitVAStart(CallInst &I);
551 void visitVAArg(VAArgInst &I);
552 void visitVAEnd(CallInst &I);
553 void visitVACopy(CallInst &I);
554 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
556 void visitMemIntrinsic(CallInst &I, unsigned Op);
558 void visitUserOp1(Instruction &I) {
559 assert(0 && "UserOp1 should not exist at instruction selection time!");
562 void visitUserOp2(Instruction &I) {
563 assert(0 && "UserOp2 should not exist at instruction selection time!");
567 } // end namespace llvm
569 SDOperand SelectionDAGLowering::getValue(const Value *V) {
570 SDOperand &N = NodeMap[V];
573 const Type *VTy = V->getType();
574 MVT::ValueType VT = TLI.getValueType(VTy);
575 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
576 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
577 visit(CE->getOpcode(), *CE);
578 assert(N.Val && "visit didn't populate the ValueMap!");
580 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
581 return N = DAG.getGlobalAddress(GV, VT);
582 } else if (isa<ConstantPointerNull>(C)) {
583 return N = DAG.getConstant(0, TLI.getPointerTy());
584 } else if (isa<UndefValue>(C)) {
585 if (!isa<PackedType>(VTy))
586 return N = DAG.getNode(ISD::UNDEF, VT);
588 // Create a VBUILD_VECTOR of undef nodes.
589 const PackedType *PTy = cast<PackedType>(VTy);
590 unsigned NumElements = PTy->getNumElements();
591 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
593 std::vector<SDOperand> Ops;
594 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
596 // Create a VConstant node with generic Vector type.
597 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
598 Ops.push_back(DAG.getValueType(PVT));
599 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
600 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
601 return N = DAG.getConstantFP(CFP->getValue(), VT);
602 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
603 unsigned NumElements = PTy->getNumElements();
604 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
606 // Now that we know the number and type of the elements, push a
607 // Constant or ConstantFP node onto the ops list for each element of
608 // the packed constant.
609 std::vector<SDOperand> Ops;
610 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
611 for (unsigned i = 0; i != NumElements; ++i)
612 Ops.push_back(getValue(CP->getOperand(i)));
614 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
616 if (MVT::isFloatingPoint(PVT))
617 Op = DAG.getConstantFP(0, PVT);
619 Op = DAG.getConstant(0, PVT);
620 Ops.assign(NumElements, Op);
623 // Create a VBUILD_VECTOR node with generic Vector type.
624 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
625 Ops.push_back(DAG.getValueType(PVT));
626 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
628 // Canonicalize all constant ints to be unsigned.
629 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
633 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
634 std::map<const AllocaInst*, int>::iterator SI =
635 FuncInfo.StaticAllocaMap.find(AI);
636 if (SI != FuncInfo.StaticAllocaMap.end())
637 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
640 std::map<const Value*, unsigned>::const_iterator VMI =
641 FuncInfo.ValueMap.find(V);
642 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
644 unsigned InReg = VMI->second;
646 // If this type is not legal, make it so now.
647 if (VT != MVT::Vector) {
648 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
650 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
652 // Source must be expanded. This input value is actually coming from the
653 // register pair VMI->second and VMI->second+1.
654 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
655 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
656 } else if (DestVT > VT) { // Promotion case
657 if (MVT::isFloatingPoint(VT))
658 N = DAG.getNode(ISD::FP_ROUND, VT, N);
660 N = DAG.getNode(ISD::TRUNCATE, VT, N);
663 // Otherwise, if this is a vector, make it available as a generic vector
665 MVT::ValueType PTyElementVT, PTyLegalElementVT;
666 const PackedType *PTy = cast<PackedType>(VTy);
667 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
670 // Build a VBUILD_VECTOR with the input registers.
671 std::vector<SDOperand> Ops;
672 if (PTyElementVT == PTyLegalElementVT) {
673 // If the value types are legal, just VBUILD the CopyFromReg nodes.
674 for (unsigned i = 0; i != NE; ++i)
675 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
677 } else if (PTyElementVT < PTyLegalElementVT) {
678 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
679 for (unsigned i = 0; i != NE; ++i) {
680 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
682 if (MVT::isFloatingPoint(PTyElementVT))
683 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
685 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
689 // If the register was expanded, use BUILD_PAIR.
690 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
691 for (unsigned i = 0; i != NE/2; ++i) {
692 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
694 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
696 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
700 Ops.push_back(DAG.getConstant(NE, MVT::i32));
701 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
702 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
704 // Finally, use a VBIT_CONVERT to make this available as the appropriate
706 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
707 DAG.getConstant(PTy->getNumElements(),
709 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
716 void SelectionDAGLowering::visitRet(ReturnInst &I) {
717 if (I.getNumOperands() == 0) {
718 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
721 std::vector<SDOperand> NewValues;
722 NewValues.push_back(getRoot());
723 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
724 SDOperand RetOp = getValue(I.getOperand(i));
725 bool isSigned = I.getOperand(i)->getType()->isSigned();
727 // If this is an integer return value, we need to promote it ourselves to
728 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
730 // FIXME: C calling convention requires the return type to be promoted to
731 // at least 32-bit. But this is not necessary for non-C calling conventions.
732 if (MVT::isInteger(RetOp.getValueType()) &&
733 RetOp.getValueType() < MVT::i64) {
734 MVT::ValueType TmpVT;
735 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
736 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
741 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
743 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
745 NewValues.push_back(RetOp);
746 NewValues.push_back(DAG.getConstant(isSigned, MVT::i32));
748 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, NewValues));
751 void SelectionDAGLowering::visitBr(BranchInst &I) {
752 // Update machine-CFG edges.
753 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
754 CurMBB->addSuccessor(Succ0MBB);
756 // Figure out which block is immediately after the current one.
757 MachineBasicBlock *NextBlock = 0;
758 MachineFunction::iterator BBI = CurMBB;
759 if (++BBI != CurMBB->getParent()->end())
762 if (I.isUnconditional()) {
763 // If this is not a fall-through branch, emit the branch.
764 if (Succ0MBB != NextBlock)
765 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
766 DAG.getBasicBlock(Succ0MBB)));
768 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
769 CurMBB->addSuccessor(Succ1MBB);
771 SDOperand Cond = getValue(I.getCondition());
772 if (Succ1MBB == NextBlock) {
773 // If the condition is false, fall through. This means we should branch
774 // if the condition is true to Succ #0.
775 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
776 Cond, DAG.getBasicBlock(Succ0MBB)));
777 } else if (Succ0MBB == NextBlock) {
778 // If the condition is true, fall through. This means we should branch if
779 // the condition is false to Succ #1. Invert the condition first.
780 SDOperand True = DAG.getConstant(1, Cond.getValueType());
781 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
782 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
783 Cond, DAG.getBasicBlock(Succ1MBB)));
785 std::vector<SDOperand> Ops;
786 Ops.push_back(getRoot());
787 // If the false case is the current basic block, then this is a self
788 // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
789 // adds an extra instruction in the loop. Instead, invert the
790 // condition and emit "Loop: ... br!cond Loop; br Out.
791 if (CurMBB == Succ1MBB) {
792 std::swap(Succ0MBB, Succ1MBB);
793 SDOperand True = DAG.getConstant(1, Cond.getValueType());
794 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
796 SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
797 DAG.getBasicBlock(Succ0MBB));
798 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
799 DAG.getBasicBlock(Succ1MBB)));
804 /// visitSwitchCase - Emits the necessary code to represent a single node in
805 /// the binary search tree resulting from lowering a switch instruction.
806 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
807 SDOperand SwitchOp = getValue(CB.SwitchV);
808 SDOperand CaseOp = getValue(CB.CaseC);
809 SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC);
811 // Set NextBlock to be the MBB immediately after the current one, if any.
812 // This is used to avoid emitting unnecessary branches to the next block.
813 MachineBasicBlock *NextBlock = 0;
814 MachineFunction::iterator BBI = CurMBB;
815 if (++BBI != CurMBB->getParent()->end())
818 // If the lhs block is the next block, invert the condition so that we can
819 // fall through to the lhs instead of the rhs block.
820 if (CB.LHSBB == NextBlock) {
821 std::swap(CB.LHSBB, CB.RHSBB);
822 SDOperand True = DAG.getConstant(1, Cond.getValueType());
823 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
825 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
826 DAG.getBasicBlock(CB.LHSBB));
827 if (CB.RHSBB == NextBlock)
830 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
831 DAG.getBasicBlock(CB.RHSBB)));
832 // Update successor info
833 CurMBB->addSuccessor(CB.LHSBB);
834 CurMBB->addSuccessor(CB.RHSBB);
837 /// visitSwitchCase - Emits the necessary code to represent a single node in
838 /// the binary search tree resulting from lowering a switch instruction.
839 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
840 // FIXME: Need to emit different code for PIC vs. Non-PIC, specifically,
841 // we need to add the address of the jump table to the value loaded, since
842 // the entries in the jump table will be differences rather than absolute
845 // Emit the code for the jump table
846 MVT::ValueType PTy = TLI.getPointerTy();
847 unsigned PTyBytes = MVT::getSizeInBits(PTy)/8;
848 SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
849 SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy,
850 DAG.getConstant(PTyBytes, PTy));
851 SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, DAG.getJumpTable(JT.JTI,PTy));
852 SDOperand LD = DAG.getLoad(PTy, Copy.getValue(1), ADD, DAG.getSrcValue(0));
853 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD));
856 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
857 // Figure out which block is immediately after the current one.
858 MachineBasicBlock *NextBlock = 0;
859 MachineFunction::iterator BBI = CurMBB;
860 if (++BBI != CurMBB->getParent()->end())
863 // If there is only the default destination, branch to it if it is not the
864 // next basic block. Otherwise, just fall through.
865 if (I.getNumOperands() == 2) {
866 // Update machine-CFG edges.
867 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()];
868 // If this is not a fall-through branch, emit the branch.
869 if (DefaultMBB != NextBlock)
870 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
871 DAG.getBasicBlock(DefaultMBB)));
875 // If there are any non-default case statements, create a vector of Cases
876 // representing each one, and sort the vector so that we can efficiently
877 // create a binary search tree from them.
878 std::vector<Case> Cases;
879 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
880 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
881 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
883 std::sort(Cases.begin(), Cases.end(), CaseCmp());
885 // Get the Value to be switched on and default basic blocks, which will be
886 // inserted into CaseBlock records, representing basic blocks in the binary
888 Value *SV = I.getOperand(0);
889 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
891 // Get the MachineFunction which holds the current MBB. This is used during
892 // emission of jump tables, and when inserting any additional MBBs necessary
893 // to represent the switch.
894 MachineFunction *CurMF = CurMBB->getParent();
895 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
896 Reloc::Model Relocs = TLI.getTargetMachine().getRelocationModel();
898 // If the switch has more than 5 blocks, and at least 31.25% dense, and the
899 // target supports indirect branches, then emit a jump table rather than
900 // lowering the switch to a binary tree of conditional branches.
901 // FIXME: Make this work with PIC code
902 if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) &&
903 (Relocs == Reloc::Static || Relocs == Reloc::DynamicNoPIC) &&
905 uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue();
906 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getRawValue();
907 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
909 if (Density >= 0.3125) {
910 // Create a new basic block to hold the code for loading the address
911 // of the jump table, and jumping to it. Update successor information;
912 // we will either branch to the default case for the switch, or the jump
914 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
915 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
916 CurMBB->addSuccessor(Default);
917 CurMBB->addSuccessor(JumpTableBB);
919 // Subtract the lowest switch case value from the value being switched on
920 // and conditional branch to default mbb if the result is greater than the
921 // difference between smallest and largest cases.
922 SDOperand SwitchOp = getValue(SV);
923 MVT::ValueType VT = SwitchOp.getValueType();
924 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
925 DAG.getConstant(First, VT));
927 // The SDNode we just created, which holds the value being switched on
928 // minus the the smallest case value, needs to be copied to a virtual
929 // register so it can be used as an index into the jump table in a
930 // subsequent basic block. This value may be smaller or larger than the
931 // target's pointer type, and therefore require extension or truncating.
932 if (VT > TLI.getPointerTy())
933 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
935 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
936 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
937 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
939 // Emit the range check for the jump table, and branch to the default
940 // block for the switch statement if the value being switched on exceeds
941 // the largest case in the switch.
942 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
943 DAG.getConstant(Last-First,VT), ISD::SETUGT);
944 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
945 DAG.getBasicBlock(Default)));
947 // Build a vector of destination BBs, corresponding to each target
948 // of the jump table. If the value of the jump table slot corresponds to
949 // a case statement, push the case's BB onto the vector, otherwise, push
951 std::set<MachineBasicBlock*> UniqueBBs;
952 std::vector<MachineBasicBlock*> DestBBs;
953 uint64_t TEI = First;
954 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) {
955 if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) {
956 DestBBs.push_back(ii->second);
957 UniqueBBs.insert(ii->second);
960 DestBBs.push_back(Default);
961 UniqueBBs.insert(Default);
965 // Update successor info
966 for (std::set<MachineBasicBlock*>::iterator ii = UniqueBBs.begin(),
967 ee = UniqueBBs.end(); ii != ee; ++ii)
968 JumpTableBB->addSuccessor(*ii);
970 // Create a jump table index for this jump table, or return an existing
972 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
974 // Set the jump table information so that we can codegen it as a second
976 JT.Reg = JumpTableReg;
978 JT.MBB = JumpTableBB;
979 JT.Default = Default;
984 // Push the initial CaseRec onto the worklist
985 std::vector<CaseRec> CaseVec;
986 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
988 while (!CaseVec.empty()) {
989 // Grab a record representing a case range to process off the worklist
990 CaseRec CR = CaseVec.back();
993 // Size is the number of Cases represented by this range. If Size is 1,
994 // then we are processing a leaf of the binary search tree. Otherwise,
995 // we need to pick a pivot, and push left and right ranges onto the
997 unsigned Size = CR.Range.second - CR.Range.first;
1000 // Create a CaseBlock record representing a conditional branch to
1001 // the Case's target mbb if the value being switched on SV is equal
1002 // to C. Otherwise, branch to default.
1003 Constant *C = CR.Range.first->first;
1004 MachineBasicBlock *Target = CR.Range.first->second;
1005 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1007 // If the MBB representing the leaf node is the current MBB, then just
1008 // call visitSwitchCase to emit the code into the current block.
1009 // Otherwise, push the CaseBlock onto the vector to be later processed
1010 // by SDISel, and insert the node's MBB before the next MBB.
1011 if (CR.CaseBB == CurMBB)
1012 visitSwitchCase(CB);
1014 SwitchCases.push_back(CB);
1015 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1018 // split case range at pivot
1019 CaseItr Pivot = CR.Range.first + (Size / 2);
1020 CaseRange LHSR(CR.Range.first, Pivot);
1021 CaseRange RHSR(Pivot, CR.Range.second);
1022 Constant *C = Pivot->first;
1023 MachineBasicBlock *RHSBB = 0, *LHSBB = 0;
1024 // We know that we branch to the LHS if the Value being switched on is
1025 // less than the Pivot value, C. We use this to optimize our binary
1026 // tree a bit, by recognizing that if SV is greater than or equal to the
1027 // LHS's Case Value, and that Case Value is exactly one less than the
1028 // Pivot's Value, then we can branch directly to the LHS's Target,
1029 // rather than creating a leaf node for it.
1030 if ((LHSR.second - LHSR.first) == 1 &&
1031 LHSR.first->first == CR.GE &&
1032 cast<ConstantIntegral>(C)->getRawValue() ==
1033 (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) {
1034 LHSBB = LHSR.first->second;
1036 LHSBB = new MachineBasicBlock(LLVMBB);
1037 CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR));
1039 // Similar to the optimization above, if the Value being switched on is
1040 // known to be less than the Constant CR.LT, and the current Case Value
1041 // is CR.LT - 1, then we can branch directly to the target block for
1042 // the current Case Value, rather than emitting a RHS leaf node for it.
1043 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1044 cast<ConstantIntegral>(RHSR.first->first)->getRawValue() ==
1045 (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) {
1046 RHSBB = RHSR.first->second;
1048 RHSBB = new MachineBasicBlock(LLVMBB);
1049 CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR));
1051 // Create a CaseBlock record representing a conditional branch to
1052 // the LHS node if the value being switched on SV is less than C.
1053 // Otherwise, branch to LHS.
1054 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
1055 SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB);
1056 if (CR.CaseBB == CurMBB)
1057 visitSwitchCase(CB);
1059 SwitchCases.push_back(CB);
1060 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1066 void SelectionDAGLowering::visitSub(User &I) {
1067 // -0.0 - X --> fneg
1068 if (I.getType()->isFloatingPoint()) {
1069 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1070 if (CFP->isExactlyValue(-0.0)) {
1071 SDOperand Op2 = getValue(I.getOperand(1));
1072 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1076 visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
1079 void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
1081 const Type *Ty = I.getType();
1082 SDOperand Op1 = getValue(I.getOperand(0));
1083 SDOperand Op2 = getValue(I.getOperand(1));
1085 if (Ty->isIntegral()) {
1086 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
1087 } else if (Ty->isFloatingPoint()) {
1088 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
1090 const PackedType *PTy = cast<PackedType>(Ty);
1091 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1092 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1093 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1097 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1098 SDOperand Op1 = getValue(I.getOperand(0));
1099 SDOperand Op2 = getValue(I.getOperand(1));
1101 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1103 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1106 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
1107 ISD::CondCode UnsignedOpcode,
1108 ISD::CondCode FPOpcode) {
1109 SDOperand Op1 = getValue(I.getOperand(0));
1110 SDOperand Op2 = getValue(I.getOperand(1));
1111 ISD::CondCode Opcode = SignedOpcode;
1112 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint())
1114 else if (I.getOperand(0)->getType()->isUnsigned())
1115 Opcode = UnsignedOpcode;
1116 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1119 void SelectionDAGLowering::visitSelect(User &I) {
1120 SDOperand Cond = getValue(I.getOperand(0));
1121 SDOperand TrueVal = getValue(I.getOperand(1));
1122 SDOperand FalseVal = getValue(I.getOperand(2));
1123 if (!isa<PackedType>(I.getType())) {
1124 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1125 TrueVal, FalseVal));
1127 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1128 *(TrueVal.Val->op_end()-2),
1129 *(TrueVal.Val->op_end()-1)));
1133 void SelectionDAGLowering::visitCast(User &I) {
1134 SDOperand N = getValue(I.getOperand(0));
1135 MVT::ValueType SrcVT = N.getValueType();
1136 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1138 if (DestVT == MVT::Vector) {
1139 // This is a cast to a vector from something else. This is always a bit
1140 // convert. Get information about the input vector.
1141 const PackedType *DestTy = cast<PackedType>(I.getType());
1142 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1143 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1144 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1145 DAG.getValueType(EltVT)));
1146 } else if (SrcVT == DestVT) {
1147 setValue(&I, N); // noop cast.
1148 } else if (DestVT == MVT::i1) {
1149 // Cast to bool is a comparison against zero, not truncation to zero.
1150 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
1151 DAG.getConstantFP(0.0, N.getValueType());
1152 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
1153 } else if (isInteger(SrcVT)) {
1154 if (isInteger(DestVT)) { // Int -> Int cast
1155 if (DestVT < SrcVT) // Truncating cast?
1156 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1157 else if (I.getOperand(0)->getType()->isSigned())
1158 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1160 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1161 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast
1162 if (I.getOperand(0)->getType()->isSigned())
1163 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1165 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1167 assert(0 && "Unknown cast!");
1169 } else if (isFloatingPoint(SrcVT)) {
1170 if (isFloatingPoint(DestVT)) { // FP -> FP cast
1171 if (DestVT < SrcVT) // Rounding cast?
1172 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1174 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1175 } else if (isInteger(DestVT)) { // FP -> Int cast.
1176 if (I.getType()->isSigned())
1177 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1179 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1181 assert(0 && "Unknown cast!");
1184 assert(SrcVT == MVT::Vector && "Unknown cast!");
1185 assert(DestVT != MVT::Vector && "Casts to vector already handled!");
1186 // This is a cast from a vector to something else. This is always a bit
1187 // convert. Get information about the input vector.
1188 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1192 void SelectionDAGLowering::visitInsertElement(User &I) {
1193 SDOperand InVec = getValue(I.getOperand(0));
1194 SDOperand InVal = getValue(I.getOperand(1));
1195 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1196 getValue(I.getOperand(2)));
1198 SDOperand Num = *(InVec.Val->op_end()-2);
1199 SDOperand Typ = *(InVec.Val->op_end()-1);
1200 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1201 InVec, InVal, InIdx, Num, Typ));
1204 void SelectionDAGLowering::visitExtractElement(User &I) {
1205 SDOperand InVec = getValue(I.getOperand(0));
1206 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1207 getValue(I.getOperand(1)));
1208 SDOperand Typ = *(InVec.Val->op_end()-1);
1209 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1210 TLI.getValueType(I.getType()), InVec, InIdx));
1213 void SelectionDAGLowering::visitShuffleVector(User &I) {
1214 SDOperand V1 = getValue(I.getOperand(0));
1215 SDOperand V2 = getValue(I.getOperand(1));
1216 SDOperand Mask = getValue(I.getOperand(2));
1218 SDOperand Num = *(V1.Val->op_end()-2);
1219 SDOperand Typ = *(V2.Val->op_end()-1);
1220 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1221 V1, V2, Mask, Num, Typ));
1225 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1226 SDOperand N = getValue(I.getOperand(0));
1227 const Type *Ty = I.getOperand(0)->getType();
1229 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1232 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1233 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
1236 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
1237 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1238 getIntPtrConstant(Offset));
1240 Ty = StTy->getElementType(Field);
1242 Ty = cast<SequentialType>(Ty)->getElementType();
1244 // If this is a constant subscript, handle it quickly.
1245 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1246 if (CI->getRawValue() == 0) continue;
1249 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
1250 Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
1252 Offs = TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
1253 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1257 // N = N + Idx * ElementSize;
1258 uint64_t ElementSize = TD->getTypeSize(Ty);
1259 SDOperand IdxN = getValue(Idx);
1261 // If the index is smaller or larger than intptr_t, truncate or extend
1263 if (IdxN.getValueType() < N.getValueType()) {
1264 if (Idx->getType()->isSigned())
1265 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1267 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
1268 } else if (IdxN.getValueType() > N.getValueType())
1269 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1271 // If this is a multiply by a power of two, turn it into a shl
1272 // immediately. This is a very common case.
1273 if (isPowerOf2_64(ElementSize)) {
1274 unsigned Amt = Log2_64(ElementSize);
1275 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1276 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1277 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1281 SDOperand Scale = getIntPtrConstant(ElementSize);
1282 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1283 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1289 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1290 // If this is a fixed sized alloca in the entry block of the function,
1291 // allocate it statically on the stack.
1292 if (FuncInfo.StaticAllocaMap.count(&I))
1293 return; // getValue will auto-populate this.
1295 const Type *Ty = I.getAllocatedType();
1296 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1297 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
1300 SDOperand AllocSize = getValue(I.getArraySize());
1301 MVT::ValueType IntPtr = TLI.getPointerTy();
1302 if (IntPtr < AllocSize.getValueType())
1303 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1304 else if (IntPtr > AllocSize.getValueType())
1305 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1307 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1308 getIntPtrConstant(TySize));
1310 // Handle alignment. If the requested alignment is less than or equal to the
1311 // stack alignment, ignore it and round the size of the allocation up to the
1312 // stack alignment size. If the size is greater than the stack alignment, we
1313 // note this in the DYNAMIC_STACKALLOC node.
1314 unsigned StackAlign =
1315 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1316 if (Align <= StackAlign) {
1318 // Add SA-1 to the size.
1319 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1320 getIntPtrConstant(StackAlign-1));
1321 // Mask out the low bits for alignment purposes.
1322 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1323 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1326 std::vector<MVT::ValueType> VTs;
1327 VTs.push_back(AllocSize.getValueType());
1328 VTs.push_back(MVT::Other);
1329 std::vector<SDOperand> Ops;
1330 Ops.push_back(getRoot());
1331 Ops.push_back(AllocSize);
1332 Ops.push_back(getIntPtrConstant(Align));
1333 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
1334 DAG.setRoot(setValue(&I, DSA).getValue(1));
1336 // Inform the Frame Information that we have just allocated a variable-sized
1338 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1341 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1342 SDOperand Ptr = getValue(I.getOperand(0));
1348 // Do not serialize non-volatile loads against each other.
1349 Root = DAG.getRoot();
1352 setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)),
1353 Root, I.isVolatile()));
1356 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1357 SDOperand SrcValue, SDOperand Root,
1360 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1361 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1362 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue);
1364 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue);
1368 DAG.setRoot(L.getValue(1));
1370 PendingLoads.push_back(L.getValue(1));
1376 void SelectionDAGLowering::visitStore(StoreInst &I) {
1377 Value *SrcV = I.getOperand(0);
1378 SDOperand Src = getValue(SrcV);
1379 SDOperand Ptr = getValue(I.getOperand(1));
1380 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
1381 DAG.getSrcValue(I.getOperand(1))));
1384 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1385 /// access memory and has no other side effects at all.
1386 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1387 #define GET_NO_MEMORY_INTRINSICS
1388 #include "llvm/Intrinsics.gen"
1389 #undef GET_NO_MEMORY_INTRINSICS
1393 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1394 // have any side-effects or if it only reads memory.
1395 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1396 #define GET_SIDE_EFFECT_INFO
1397 #include "llvm/Intrinsics.gen"
1398 #undef GET_SIDE_EFFECT_INFO
1402 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1404 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1405 unsigned Intrinsic) {
1406 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1407 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1409 // Build the operand list.
1410 std::vector<SDOperand> Ops;
1411 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1413 // We don't need to serialize loads against other loads.
1414 Ops.push_back(DAG.getRoot());
1416 Ops.push_back(getRoot());
1420 // Add the intrinsic ID as an integer operand.
1421 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1423 // Add all operands of the call to the operand list.
1424 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1425 SDOperand Op = getValue(I.getOperand(i));
1427 // If this is a vector type, force it to the right packed type.
1428 if (Op.getValueType() == MVT::Vector) {
1429 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1430 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1432 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1433 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1434 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1437 assert(TLI.isTypeLegal(Op.getValueType()) &&
1438 "Intrinsic uses a non-legal type?");
1442 std::vector<MVT::ValueType> VTs;
1443 if (I.getType() != Type::VoidTy) {
1444 MVT::ValueType VT = TLI.getValueType(I.getType());
1445 if (VT == MVT::Vector) {
1446 const PackedType *DestTy = cast<PackedType>(I.getType());
1447 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1449 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1450 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1453 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1457 VTs.push_back(MVT::Other);
1462 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, Ops);
1463 else if (I.getType() != Type::VoidTy)
1464 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, Ops);
1466 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
1469 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1471 PendingLoads.push_back(Chain);
1475 if (I.getType() != Type::VoidTy) {
1476 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1477 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1478 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1479 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1480 DAG.getValueType(EVT));
1482 setValue(&I, Result);
1486 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1487 /// we want to emit this as a call to a named external function, return the name
1488 /// otherwise lower it and return null.
1490 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1491 switch (Intrinsic) {
1493 // By default, turn this into a target intrinsic node.
1494 visitTargetIntrinsic(I, Intrinsic);
1496 case Intrinsic::vastart: visitVAStart(I); return 0;
1497 case Intrinsic::vaend: visitVAEnd(I); return 0;
1498 case Intrinsic::vacopy: visitVACopy(I); return 0;
1499 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1500 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1501 case Intrinsic::setjmp:
1502 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1504 case Intrinsic::longjmp:
1505 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1507 case Intrinsic::memcpy_i32:
1508 case Intrinsic::memcpy_i64:
1509 visitMemIntrinsic(I, ISD::MEMCPY);
1511 case Intrinsic::memset_i32:
1512 case Intrinsic::memset_i64:
1513 visitMemIntrinsic(I, ISD::MEMSET);
1515 case Intrinsic::memmove_i32:
1516 case Intrinsic::memmove_i64:
1517 visitMemIntrinsic(I, ISD::MEMMOVE);
1520 case Intrinsic::dbg_stoppoint: {
1521 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1522 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1523 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
1524 std::vector<SDOperand> Ops;
1526 Ops.push_back(getRoot());
1527 Ops.push_back(getValue(SPI.getLineValue()));
1528 Ops.push_back(getValue(SPI.getColumnValue()));
1530 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
1531 assert(DD && "Not a debug information descriptor");
1532 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1534 Ops.push_back(DAG.getString(CompileUnit->getFileName()));
1535 Ops.push_back(DAG.getString(CompileUnit->getDirectory()));
1537 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops));
1542 case Intrinsic::dbg_region_start: {
1543 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1544 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1545 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
1546 std::vector<SDOperand> Ops;
1548 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
1550 Ops.push_back(getRoot());
1551 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1553 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1558 case Intrinsic::dbg_region_end: {
1559 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1560 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
1561 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
1562 std::vector<SDOperand> Ops;
1564 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
1566 Ops.push_back(getRoot());
1567 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1569 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1574 case Intrinsic::dbg_func_start: {
1575 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1576 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
1577 if (DebugInfo && FSI.getSubprogram() &&
1578 DebugInfo->Verify(FSI.getSubprogram())) {
1579 std::vector<SDOperand> Ops;
1581 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
1583 Ops.push_back(getRoot());
1584 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1586 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1591 case Intrinsic::dbg_declare: {
1592 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1593 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
1594 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
1595 std::vector<SDOperand> Ops;
1597 SDOperand AddressOp = getValue(DI.getAddress());
1598 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) {
1599 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
1606 case Intrinsic::isunordered_f32:
1607 case Intrinsic::isunordered_f64:
1608 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
1609 getValue(I.getOperand(2)), ISD::SETUO));
1612 case Intrinsic::sqrt_f32:
1613 case Intrinsic::sqrt_f64:
1614 setValue(&I, DAG.getNode(ISD::FSQRT,
1615 getValue(I.getOperand(1)).getValueType(),
1616 getValue(I.getOperand(1))));
1618 case Intrinsic::pcmarker: {
1619 SDOperand Tmp = getValue(I.getOperand(1));
1620 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
1623 case Intrinsic::readcyclecounter: {
1624 std::vector<MVT::ValueType> VTs;
1625 VTs.push_back(MVT::i64);
1626 VTs.push_back(MVT::Other);
1627 std::vector<SDOperand> Ops;
1628 Ops.push_back(getRoot());
1629 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops);
1631 DAG.setRoot(Tmp.getValue(1));
1634 case Intrinsic::bswap_i16:
1635 case Intrinsic::bswap_i32:
1636 case Intrinsic::bswap_i64:
1637 setValue(&I, DAG.getNode(ISD::BSWAP,
1638 getValue(I.getOperand(1)).getValueType(),
1639 getValue(I.getOperand(1))));
1641 case Intrinsic::cttz_i8:
1642 case Intrinsic::cttz_i16:
1643 case Intrinsic::cttz_i32:
1644 case Intrinsic::cttz_i64:
1645 setValue(&I, DAG.getNode(ISD::CTTZ,
1646 getValue(I.getOperand(1)).getValueType(),
1647 getValue(I.getOperand(1))));
1649 case Intrinsic::ctlz_i8:
1650 case Intrinsic::ctlz_i16:
1651 case Intrinsic::ctlz_i32:
1652 case Intrinsic::ctlz_i64:
1653 setValue(&I, DAG.getNode(ISD::CTLZ,
1654 getValue(I.getOperand(1)).getValueType(),
1655 getValue(I.getOperand(1))));
1657 case Intrinsic::ctpop_i8:
1658 case Intrinsic::ctpop_i16:
1659 case Intrinsic::ctpop_i32:
1660 case Intrinsic::ctpop_i64:
1661 setValue(&I, DAG.getNode(ISD::CTPOP,
1662 getValue(I.getOperand(1)).getValueType(),
1663 getValue(I.getOperand(1))));
1665 case Intrinsic::stacksave: {
1666 std::vector<MVT::ValueType> VTs;
1667 VTs.push_back(TLI.getPointerTy());
1668 VTs.push_back(MVT::Other);
1669 std::vector<SDOperand> Ops;
1670 Ops.push_back(getRoot());
1671 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, Ops);
1673 DAG.setRoot(Tmp.getValue(1));
1676 case Intrinsic::stackrestore: {
1677 SDOperand Tmp = getValue(I.getOperand(1));
1678 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
1681 case Intrinsic::prefetch:
1682 // FIXME: Currently discarding prefetches.
1688 void SelectionDAGLowering::visitCall(CallInst &I) {
1689 const char *RenameFn = 0;
1690 if (Function *F = I.getCalledFunction()) {
1691 if (F->isExternal())
1692 if (unsigned IID = F->getIntrinsicID()) {
1693 RenameFn = visitIntrinsicCall(I, IID);
1696 } else { // Not an LLVM intrinsic.
1697 const std::string &Name = F->getName();
1698 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
1699 if (I.getNumOperands() == 3 && // Basic sanity checks.
1700 I.getOperand(1)->getType()->isFloatingPoint() &&
1701 I.getType() == I.getOperand(1)->getType() &&
1702 I.getType() == I.getOperand(2)->getType()) {
1703 SDOperand LHS = getValue(I.getOperand(1));
1704 SDOperand RHS = getValue(I.getOperand(2));
1705 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
1709 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
1710 if (I.getNumOperands() == 2 && // Basic sanity checks.
1711 I.getOperand(1)->getType()->isFloatingPoint() &&
1712 I.getType() == I.getOperand(1)->getType()) {
1713 SDOperand Tmp = getValue(I.getOperand(1));
1714 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
1717 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
1718 if (I.getNumOperands() == 2 && // Basic sanity checks.
1719 I.getOperand(1)->getType()->isFloatingPoint() &&
1720 I.getType() == I.getOperand(1)->getType()) {
1721 SDOperand Tmp = getValue(I.getOperand(1));
1722 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
1725 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
1726 if (I.getNumOperands() == 2 && // Basic sanity checks.
1727 I.getOperand(1)->getType()->isFloatingPoint() &&
1728 I.getType() == I.getOperand(1)->getType()) {
1729 SDOperand Tmp = getValue(I.getOperand(1));
1730 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
1735 } else if (isa<InlineAsm>(I.getOperand(0))) {
1742 Callee = getValue(I.getOperand(0));
1744 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
1745 std::vector<std::pair<SDOperand, const Type*> > Args;
1746 Args.reserve(I.getNumOperands());
1747 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1748 Value *Arg = I.getOperand(i);
1749 SDOperand ArgNode = getValue(Arg);
1750 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
1753 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
1754 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1756 std::pair<SDOperand,SDOperand> Result =
1757 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
1758 I.isTailCall(), Callee, Args, DAG);
1759 if (I.getType() != Type::VoidTy)
1760 setValue(&I, Result.first);
1761 DAG.setRoot(Result.second);
1764 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
1765 SDOperand &Chain, SDOperand &Flag)const{
1766 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
1767 Chain = Val.getValue(1);
1768 Flag = Val.getValue(2);
1770 // If the result was expanded, copy from the top part.
1771 if (Regs.size() > 1) {
1772 assert(Regs.size() == 2 &&
1773 "Cannot expand to more than 2 elts yet!");
1774 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
1775 Chain = Val.getValue(1);
1776 Flag = Val.getValue(2);
1777 if (DAG.getTargetLoweringInfo().isLittleEndian())
1778 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
1780 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
1783 // Otherwise, if the return value was promoted or extended, truncate it to the
1784 // appropriate type.
1785 if (RegVT == ValueVT)
1788 if (MVT::isInteger(RegVT)) {
1789 if (ValueVT < RegVT)
1790 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1792 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
1794 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
1798 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
1799 /// specified value into the registers specified by this object. This uses
1800 /// Chain/Flag as the input and updates them for the output Chain/Flag.
1801 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
1802 SDOperand &Chain, SDOperand &Flag) const {
1803 if (Regs.size() == 1) {
1804 // If there is a single register and the types differ, this must be
1806 if (RegVT != ValueVT) {
1807 if (MVT::isInteger(RegVT)) {
1808 if (RegVT < ValueVT)
1809 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
1811 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
1813 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
1815 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
1816 Flag = Chain.getValue(1);
1818 std::vector<unsigned> R(Regs);
1819 if (!DAG.getTargetLoweringInfo().isLittleEndian())
1820 std::reverse(R.begin(), R.end());
1822 for (unsigned i = 0, e = R.size(); i != e; ++i) {
1823 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
1824 DAG.getConstant(i, MVT::i32));
1825 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
1826 Flag = Chain.getValue(1);
1831 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
1832 /// operand list. This adds the code marker and includes the number of
1833 /// values added into it.
1834 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
1835 std::vector<SDOperand> &Ops) const {
1836 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
1837 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1838 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
1841 /// isAllocatableRegister - If the specified register is safe to allocate,
1842 /// i.e. it isn't a stack pointer or some other special register, return the
1843 /// register class for the register. Otherwise, return null.
1844 static const TargetRegisterClass *
1845 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
1846 const TargetLowering &TLI, const MRegisterInfo *MRI) {
1847 MVT::ValueType FoundVT = MVT::Other;
1848 const TargetRegisterClass *FoundRC = 0;
1849 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
1850 E = MRI->regclass_end(); RCI != E; ++RCI) {
1851 MVT::ValueType ThisVT = MVT::Other;
1853 const TargetRegisterClass *RC = *RCI;
1854 // If none of the the value types for this register class are valid, we
1855 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1856 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1858 if (TLI.isTypeLegal(*I)) {
1859 // If we have already found this register in a different register class,
1860 // choose the one with the largest VT specified. For example, on
1861 // PowerPC, we favor f64 register classes over f32.
1862 if (FoundVT == MVT::Other ||
1863 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
1870 if (ThisVT == MVT::Other) continue;
1872 // NOTE: This isn't ideal. In particular, this might allocate the
1873 // frame pointer in functions that need it (due to them not being taken
1874 // out of allocation, because a variable sized allocation hasn't been seen
1875 // yet). This is a slight code pessimization, but should still work.
1876 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
1877 E = RC->allocation_order_end(MF); I != E; ++I)
1879 // We found a matching register class. Keep looking at others in case
1880 // we find one with larger registers that this physreg is also in.
1889 RegsForValue SelectionDAGLowering::
1890 GetRegistersForValue(const std::string &ConstrCode,
1891 MVT::ValueType VT, bool isOutReg, bool isInReg,
1892 std::set<unsigned> &OutputRegs,
1893 std::set<unsigned> &InputRegs) {
1894 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
1895 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
1896 std::vector<unsigned> Regs;
1898 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
1899 MVT::ValueType RegVT;
1900 MVT::ValueType ValueVT = VT;
1902 if (PhysReg.first) {
1903 if (VT == MVT::Other)
1904 ValueVT = *PhysReg.second->vt_begin();
1906 // Get the actual register value type. This is important, because the user
1907 // may have asked for (e.g.) the AX register in i32 type. We need to
1908 // remember that AX is actually i16 to get the right extension.
1909 RegVT = *PhysReg.second->vt_begin();
1911 // This is a explicit reference to a physical register.
1912 Regs.push_back(PhysReg.first);
1914 // If this is an expanded reference, add the rest of the regs to Regs.
1916 TargetRegisterClass::iterator I = PhysReg.second->begin();
1917 TargetRegisterClass::iterator E = PhysReg.second->end();
1918 for (; *I != PhysReg.first; ++I)
1919 assert(I != E && "Didn't find reg!");
1921 // Already added the first reg.
1923 for (; NumRegs; --NumRegs, ++I) {
1924 assert(I != E && "Ran out of registers to allocate!");
1928 return RegsForValue(Regs, RegVT, ValueVT);
1931 // This is a reference to a register class. Allocate NumRegs consecutive,
1932 // available, registers from the class.
1933 std::vector<unsigned> RegClassRegs =
1934 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
1936 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
1937 MachineFunction &MF = *CurMBB->getParent();
1938 unsigned NumAllocated = 0;
1939 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
1940 unsigned Reg = RegClassRegs[i];
1941 // See if this register is available.
1942 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
1943 (isInReg && InputRegs.count(Reg))) { // Already used.
1944 // Make sure we find consecutive registers.
1949 // Check to see if this register is allocatable (i.e. don't give out the
1951 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
1953 // Make sure we find consecutive registers.
1958 // Okay, this register is good, we can use it.
1961 // If we allocated enough consecutive
1962 if (NumAllocated == NumRegs) {
1963 unsigned RegStart = (i-NumAllocated)+1;
1964 unsigned RegEnd = i+1;
1965 // Mark all of the allocated registers used.
1966 for (unsigned i = RegStart; i != RegEnd; ++i) {
1967 unsigned Reg = RegClassRegs[i];
1968 Regs.push_back(Reg);
1969 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
1970 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
1973 return RegsForValue(Regs, *RC->vt_begin(), VT);
1977 // Otherwise, we couldn't allocate enough registers for this.
1978 return RegsForValue();
1982 /// visitInlineAsm - Handle a call to an InlineAsm object.
1984 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
1985 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
1987 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
1990 // Note, we treat inline asms both with and without side-effects as the same.
1991 // If an inline asm doesn't have side effects and doesn't access memory, we
1992 // could not choose to not chain it.
1993 bool hasSideEffects = IA->hasSideEffects();
1995 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
1996 std::vector<MVT::ValueType> ConstraintVTs;
1998 /// AsmNodeOperands - A list of pairs. The first element is a register, the
1999 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
2000 /// if it is a def of that register.
2001 std::vector<SDOperand> AsmNodeOperands;
2002 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
2003 AsmNodeOperands.push_back(AsmStr);
2005 SDOperand Chain = getRoot();
2008 // We fully assign registers here at isel time. This is not optimal, but
2009 // should work. For register classes that correspond to LLVM classes, we
2010 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
2011 // over the constraints, collecting fixed registers that we know we can't use.
2012 std::set<unsigned> OutputRegs, InputRegs;
2014 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2015 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2016 std::string &ConstraintCode = Constraints[i].Codes[0];
2018 MVT::ValueType OpVT;
2020 // Compute the value type for each operand and add it to ConstraintVTs.
2021 switch (Constraints[i].Type) {
2022 case InlineAsm::isOutput:
2023 if (!Constraints[i].isIndirectOutput) {
2024 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2025 OpVT = TLI.getValueType(I.getType());
2027 const Type *OpTy = I.getOperand(OpNum)->getType();
2028 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2029 OpNum++; // Consumes a call operand.
2032 case InlineAsm::isInput:
2033 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2034 OpNum++; // Consumes a call operand.
2036 case InlineAsm::isClobber:
2041 ConstraintVTs.push_back(OpVT);
2043 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2044 continue; // Not assigned a fixed reg.
2046 // Build a list of regs that this operand uses. This always has a single
2047 // element for promoted/expanded operands.
2048 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2050 OutputRegs, InputRegs);
2052 switch (Constraints[i].Type) {
2053 case InlineAsm::isOutput:
2054 // We can't assign any other output to this register.
2055 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2056 // If this is an early-clobber output, it cannot be assigned to the same
2057 // value as the input reg.
2058 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2059 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2061 case InlineAsm::isInput:
2062 // We can't assign any other input to this register.
2063 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2065 case InlineAsm::isClobber:
2066 // Clobbered regs cannot be used as inputs or outputs.
2067 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2068 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2073 // Loop over all of the inputs, copying the operand values into the
2074 // appropriate registers and processing the output regs.
2075 RegsForValue RetValRegs;
2076 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2079 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2080 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2081 std::string &ConstraintCode = Constraints[i].Codes[0];
2083 switch (Constraints[i].Type) {
2084 case InlineAsm::isOutput: {
2085 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2086 if (ConstraintCode.size() == 1) // not a physreg name.
2087 CTy = TLI.getConstraintType(ConstraintCode[0]);
2089 if (CTy == TargetLowering::C_Memory) {
2091 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2093 // Check that the operand (the address to store to) isn't a float.
2094 if (!MVT::isInteger(InOperandVal.getValueType()))
2095 assert(0 && "MATCH FAIL!");
2097 if (!Constraints[i].isIndirectOutput)
2098 assert(0 && "MATCH FAIL!");
2100 OpNum++; // Consumes a call operand.
2102 // Extend/truncate to the right pointer type if needed.
2103 MVT::ValueType PtrType = TLI.getPointerTy();
2104 if (InOperandVal.getValueType() < PtrType)
2105 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2106 else if (InOperandVal.getValueType() > PtrType)
2107 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2109 // Add information to the INLINEASM node to know about this output.
2110 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2111 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2112 AsmNodeOperands.push_back(InOperandVal);
2116 // Otherwise, this is a register output.
2117 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2119 // If this is an early-clobber output, or if there is an input
2120 // constraint that matches this, we need to reserve the input register
2121 // so no other inputs allocate to it.
2122 bool UsesInputRegister = false;
2123 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2124 UsesInputRegister = true;
2126 // Copy the output from the appropriate register. Find a register that
2129 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2130 true, UsesInputRegister,
2131 OutputRegs, InputRegs);
2132 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
2134 if (!Constraints[i].isIndirectOutput) {
2135 assert(RetValRegs.Regs.empty() &&
2136 "Cannot have multiple output constraints yet!");
2137 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2140 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2141 I.getOperand(OpNum)));
2142 OpNum++; // Consumes a call operand.
2145 // Add information to the INLINEASM node to know that this register is
2147 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2150 case InlineAsm::isInput: {
2151 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2152 OpNum++; // Consumes a call operand.
2154 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2155 // If this is required to match an output register we have already set,
2156 // just use its register.
2157 unsigned OperandNo = atoi(ConstraintCode.c_str());
2159 // Scan until we find the definition we already emitted of this operand.
2160 // When we find it, create a RegsForValue operand.
2161 unsigned CurOp = 2; // The first operand.
2162 for (; OperandNo; --OperandNo) {
2163 // Advance to the next operand.
2165 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2166 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2167 "Skipped past definitions?");
2168 CurOp += (NumOps>>3)+1;
2172 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2173 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2174 "Skipped past definitions?");
2176 // Add NumOps>>3 registers to MatchedRegs.
2177 RegsForValue MatchedRegs;
2178 MatchedRegs.ValueVT = InOperandVal.getValueType();
2179 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2180 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2181 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2182 MatchedRegs.Regs.push_back(Reg);
2185 // Use the produced MatchedRegs object to
2186 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
2187 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2191 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2192 if (ConstraintCode.size() == 1) // not a physreg name.
2193 CTy = TLI.getConstraintType(ConstraintCode[0]);
2195 if (CTy == TargetLowering::C_Other) {
2196 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
2197 assert(0 && "MATCH FAIL!");
2199 // Add information to the INLINEASM node to know about this input.
2200 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2201 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2202 AsmNodeOperands.push_back(InOperandVal);
2204 } else if (CTy == TargetLowering::C_Memory) {
2207 // Check that the operand isn't a float.
2208 if (!MVT::isInteger(InOperandVal.getValueType()))
2209 assert(0 && "MATCH FAIL!");
2211 // Extend/truncate to the right pointer type if needed.
2212 MVT::ValueType PtrType = TLI.getPointerTy();
2213 if (InOperandVal.getValueType() < PtrType)
2214 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2215 else if (InOperandVal.getValueType() > PtrType)
2216 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2218 // Add information to the INLINEASM node to know about this input.
2219 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2220 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2221 AsmNodeOperands.push_back(InOperandVal);
2225 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2227 // Copy the input into the appropriate registers.
2228 RegsForValue InRegs =
2229 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2230 false, true, OutputRegs, InputRegs);
2231 // FIXME: should be match fail.
2232 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2234 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
2236 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2239 case InlineAsm::isClobber: {
2240 RegsForValue ClobberedRegs =
2241 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2242 OutputRegs, InputRegs);
2243 // Add the clobbered value to the operand list, so that the register
2244 // allocator is aware that the physreg got clobbered.
2245 if (!ClobberedRegs.Regs.empty())
2246 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2252 // Finish up input operands.
2253 AsmNodeOperands[0] = Chain;
2254 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2256 std::vector<MVT::ValueType> VTs;
2257 VTs.push_back(MVT::Other);
2258 VTs.push_back(MVT::Flag);
2259 Chain = DAG.getNode(ISD::INLINEASM, VTs, AsmNodeOperands);
2260 Flag = Chain.getValue(1);
2262 // If this asm returns a register value, copy the result from that register
2263 // and set it as the value of the call.
2264 if (!RetValRegs.Regs.empty())
2265 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2267 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2269 // Process indirect outputs, first output all of the flagged copies out of
2271 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2272 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2273 Value *Ptr = IndirectStoresToEmit[i].second;
2274 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2275 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2278 // Emit the non-flagged stores from the physregs.
2279 std::vector<SDOperand> OutChains;
2280 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2281 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
2282 StoresToEmit[i].first,
2283 getValue(StoresToEmit[i].second),
2284 DAG.getSrcValue(StoresToEmit[i].second)));
2285 if (!OutChains.empty())
2286 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
2291 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2292 SDOperand Src = getValue(I.getOperand(0));
2294 MVT::ValueType IntPtr = TLI.getPointerTy();
2296 if (IntPtr < Src.getValueType())
2297 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2298 else if (IntPtr > Src.getValueType())
2299 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2301 // Scale the source by the type size.
2302 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
2303 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2304 Src, getIntPtrConstant(ElementSize));
2306 std::vector<std::pair<SDOperand, const Type*> > Args;
2307 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType()));
2309 std::pair<SDOperand,SDOperand> Result =
2310 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
2311 DAG.getExternalSymbol("malloc", IntPtr),
2313 setValue(&I, Result.first); // Pointers always fit in registers
2314 DAG.setRoot(Result.second);
2317 void SelectionDAGLowering::visitFree(FreeInst &I) {
2318 std::vector<std::pair<SDOperand, const Type*> > Args;
2319 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
2320 TLI.getTargetData()->getIntPtrType()));
2321 MVT::ValueType IntPtr = TLI.getPointerTy();
2322 std::pair<SDOperand,SDOperand> Result =
2323 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
2324 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2325 DAG.setRoot(Result.second);
2328 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2329 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2330 // instructions are special in various ways, which require special support to
2331 // insert. The specified MachineInstr is created but not inserted into any
2332 // basic blocks, and the scheduler passes ownership of it to this method.
2333 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2334 MachineBasicBlock *MBB) {
2335 std::cerr << "If a target marks an instruction with "
2336 "'usesCustomDAGSchedInserter', it must implement "
2337 "TargetLowering::InsertAtEndOfBasicBlock!\n";
2342 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2343 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2344 getValue(I.getOperand(1)),
2345 DAG.getSrcValue(I.getOperand(1))));
2348 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2349 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2350 getValue(I.getOperand(0)),
2351 DAG.getSrcValue(I.getOperand(0)));
2353 DAG.setRoot(V.getValue(1));
2356 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2357 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2358 getValue(I.getOperand(1)),
2359 DAG.getSrcValue(I.getOperand(1))));
2362 void SelectionDAGLowering::visitVACopy(CallInst &I) {
2363 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2364 getValue(I.getOperand(1)),
2365 getValue(I.getOperand(2)),
2366 DAG.getSrcValue(I.getOperand(1)),
2367 DAG.getSrcValue(I.getOperand(2))));
2370 /// TargetLowering::LowerArguments - This is the default LowerArguments
2371 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
2372 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
2373 /// integrated into SDISel.
2374 std::vector<SDOperand>
2375 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2376 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2377 std::vector<SDOperand> Ops;
2378 Ops.push_back(DAG.getRoot());
2379 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2380 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2382 // Add one result value for each formal argument.
2383 std::vector<MVT::ValueType> RetVals;
2384 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2385 MVT::ValueType VT = getValueType(I->getType());
2387 switch (getTypeAction(VT)) {
2388 default: assert(0 && "Unknown type action!");
2390 RetVals.push_back(VT);
2393 RetVals.push_back(getTypeToTransformTo(VT));
2396 if (VT != MVT::Vector) {
2397 // If this is a large integer, it needs to be broken up into small
2398 // integers. Figure out what the destination type is and how many small
2399 // integers it turns into.
2400 MVT::ValueType NVT = getTypeToTransformTo(VT);
2401 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2402 for (unsigned i = 0; i != NumVals; ++i)
2403 RetVals.push_back(NVT);
2405 // Otherwise, this is a vector type. We only support legal vectors
2407 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2408 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2410 // Figure out if there is a Packed type corresponding to this Vector
2411 // type. If so, convert to the packed type.
2412 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2413 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2414 RetVals.push_back(TVT);
2416 assert(0 && "Don't support illegal by-val vector arguments yet!");
2423 RetVals.push_back(MVT::Other);
2426 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals, Ops).Val;
2428 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
2430 // Set up the return result vector.
2433 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2434 MVT::ValueType VT = getValueType(I->getType());
2436 switch (getTypeAction(VT)) {
2437 default: assert(0 && "Unknown type action!");
2439 Ops.push_back(SDOperand(Result, i++));
2442 SDOperand Op(Result, i++);
2443 if (MVT::isInteger(VT)) {
2444 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
2446 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
2447 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2449 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2450 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2456 if (VT != MVT::Vector) {
2457 // If this is a large integer, it needs to be reassembled from small
2458 // integers. Figure out what the source elt type is and how many small
2460 MVT::ValueType NVT = getTypeToTransformTo(VT);
2461 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2463 SDOperand Lo = SDOperand(Result, i++);
2464 SDOperand Hi = SDOperand(Result, i++);
2466 if (!isLittleEndian())
2469 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
2471 // Value scalarized into many values. Unimp for now.
2472 assert(0 && "Cannot expand i64 -> i16 yet!");
2475 // Otherwise, this is a vector type. We only support legal vectors
2477 const PackedType *PTy = cast<PackedType>(I->getType());
2478 unsigned NumElems = PTy->getNumElements();
2479 const Type *EltTy = PTy->getElementType();
2481 // Figure out if there is a Packed type corresponding to this Vector
2482 // type. If so, convert to the packed type.
2483 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2484 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2485 SDOperand N = SDOperand(Result, i++);
2486 // Handle copies from generic vectors to registers.
2487 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
2488 DAG.getConstant(NumElems, MVT::i32),
2489 DAG.getValueType(getValueType(EltTy)));
2492 assert(0 && "Don't support illegal by-val vector arguments yet!");
2503 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
2504 /// implementation, which just inserts an ISD::CALL node, which is later custom
2505 /// lowered by the target to something concrete. FIXME: When all targets are
2506 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
2507 std::pair<SDOperand, SDOperand>
2508 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
2509 unsigned CallingConv, bool isTailCall,
2511 ArgListTy &Args, SelectionDAG &DAG) {
2512 std::vector<SDOperand> Ops;
2513 Ops.push_back(Chain); // Op#0 - Chain
2514 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
2515 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
2516 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
2517 Ops.push_back(Callee);
2519 // Handle all of the outgoing arguments.
2520 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
2521 MVT::ValueType VT = getValueType(Args[i].second);
2522 SDOperand Op = Args[i].first;
2523 bool isSigned = Args[i].second->isSigned();
2524 switch (getTypeAction(VT)) {
2525 default: assert(0 && "Unknown type action!");
2528 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2531 if (MVT::isInteger(VT)) {
2532 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2533 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
2535 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2536 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
2539 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2542 if (VT != MVT::Vector) {
2543 // If this is a large integer, it needs to be broken down into small
2544 // integers. Figure out what the source elt type is and how many small
2546 MVT::ValueType NVT = getTypeToTransformTo(VT);
2547 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2549 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2550 DAG.getConstant(0, getPointerTy()));
2551 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2552 DAG.getConstant(1, getPointerTy()));
2553 if (!isLittleEndian())
2557 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2559 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2561 // Value scalarized into many values. Unimp for now.
2562 assert(0 && "Cannot expand i64 -> i16 yet!");
2565 // Otherwise, this is a vector type. We only support legal vectors
2567 const PackedType *PTy = cast<PackedType>(Args[i].second);
2568 unsigned NumElems = PTy->getNumElements();
2569 const Type *EltTy = PTy->getElementType();
2571 // Figure out if there is a Packed type corresponding to this Vector
2572 // type. If so, convert to the packed type.
2573 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2574 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2575 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
2576 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
2578 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2580 assert(0 && "Don't support illegal by-val vector call args yet!");
2588 // Figure out the result value types.
2589 std::vector<MVT::ValueType> RetTys;
2591 if (RetTy != Type::VoidTy) {
2592 MVT::ValueType VT = getValueType(RetTy);
2593 switch (getTypeAction(VT)) {
2594 default: assert(0 && "Unknown type action!");
2596 RetTys.push_back(VT);
2599 RetTys.push_back(getTypeToTransformTo(VT));
2602 if (VT != MVT::Vector) {
2603 // If this is a large integer, it needs to be reassembled from small
2604 // integers. Figure out what the source elt type is and how many small
2606 MVT::ValueType NVT = getTypeToTransformTo(VT);
2607 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2608 for (unsigned i = 0; i != NumVals; ++i)
2609 RetTys.push_back(NVT);
2611 // Otherwise, this is a vector type. We only support legal vectors
2613 const PackedType *PTy = cast<PackedType>(RetTy);
2614 unsigned NumElems = PTy->getNumElements();
2615 const Type *EltTy = PTy->getElementType();
2617 // Figure out if there is a Packed type corresponding to this Vector
2618 // type. If so, convert to the packed type.
2619 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2620 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2621 RetTys.push_back(TVT);
2623 assert(0 && "Don't support illegal by-val vector call results yet!");
2630 RetTys.push_back(MVT::Other); // Always has a chain.
2632 // Finally, create the CALL node.
2633 SDOperand Res = DAG.getNode(ISD::CALL, RetTys, Ops);
2635 // This returns a pair of operands. The first element is the
2636 // return value for the function (if RetTy is not VoidTy). The second
2637 // element is the outgoing token chain.
2639 if (RetTys.size() != 1) {
2640 MVT::ValueType VT = getValueType(RetTy);
2641 if (RetTys.size() == 2) {
2644 // If this value was promoted, truncate it down.
2645 if (ResVal.getValueType() != VT) {
2646 if (VT == MVT::Vector) {
2647 // Insert a VBITCONVERT to convert from the packed result type to the
2648 // MVT::Vector type.
2649 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
2650 const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
2652 // Figure out if there is a Packed type corresponding to this Vector
2653 // type. If so, convert to the packed type.
2654 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2655 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2656 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
2657 // "N x PTyElementVT" MVT::Vector type.
2658 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
2659 DAG.getConstant(NumElems, MVT::i32),
2660 DAG.getValueType(getValueType(EltTy)));
2664 } else if (MVT::isInteger(VT)) {
2665 unsigned AssertOp = RetTy->isSigned() ?
2666 ISD::AssertSext : ISD::AssertZext;
2667 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
2668 DAG.getValueType(VT));
2669 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
2671 assert(MVT::isFloatingPoint(VT));
2672 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
2675 } else if (RetTys.size() == 3) {
2676 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
2677 Res.getValue(0), Res.getValue(1));
2680 assert(0 && "Case not handled yet!");
2684 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
2689 // It is always conservatively correct for llvm.returnaddress and
2690 // llvm.frameaddress to return 0.
2692 // FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
2693 // expanded to 0 if the target wants.
2694 std::pair<SDOperand, SDOperand>
2695 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
2696 unsigned Depth, SelectionDAG &DAG) {
2697 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
2700 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2701 assert(0 && "LowerOperation not implemented for this target!");
2706 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
2707 SelectionDAG &DAG) {
2708 assert(0 && "CustomPromoteOperation not implemented for this target!");
2713 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
2714 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
2715 std::pair<SDOperand,SDOperand> Result =
2716 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
2717 setValue(&I, Result.first);
2718 DAG.setRoot(Result.second);
2721 /// getMemsetValue - Vectorized representation of the memset value
2723 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
2724 SelectionDAG &DAG) {
2725 MVT::ValueType CurVT = VT;
2726 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2727 uint64_t Val = C->getValue() & 255;
2729 while (CurVT != MVT::i8) {
2730 Val = (Val << Shift) | Val;
2732 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2734 return DAG.getConstant(Val, VT);
2736 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
2738 while (CurVT != MVT::i8) {
2740 DAG.getNode(ISD::OR, VT,
2741 DAG.getNode(ISD::SHL, VT, Value,
2742 DAG.getConstant(Shift, MVT::i8)), Value);
2744 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2751 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2752 /// used when a memcpy is turned into a memset when the source is a constant
2754 static SDOperand getMemsetStringVal(MVT::ValueType VT,
2755 SelectionDAG &DAG, TargetLowering &TLI,
2756 std::string &Str, unsigned Offset) {
2757 MVT::ValueType CurVT = VT;
2759 unsigned MSB = getSizeInBits(VT) / 8;
2760 if (TLI.isLittleEndian())
2761 Offset = Offset + MSB - 1;
2762 for (unsigned i = 0; i != MSB; ++i) {
2763 Val = (Val << 8) | Str[Offset];
2764 Offset += TLI.isLittleEndian() ? -1 : 1;
2766 return DAG.getConstant(Val, VT);
2769 /// getMemBasePlusOffset - Returns base and offset node for the
2770 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
2771 SelectionDAG &DAG, TargetLowering &TLI) {
2772 MVT::ValueType VT = Base.getValueType();
2773 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
2776 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
2777 /// to replace the memset / memcpy is below the threshold. It also returns the
2778 /// types of the sequence of memory ops to perform memset / memcpy.
2779 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
2780 unsigned Limit, uint64_t Size,
2781 unsigned Align, TargetLowering &TLI) {
2784 if (TLI.allowsUnalignedMemoryAccesses()) {
2787 switch (Align & 7) {
2803 MVT::ValueType LVT = MVT::i64;
2804 while (!TLI.isTypeLegal(LVT))
2805 LVT = (MVT::ValueType)((unsigned)LVT - 1);
2806 assert(MVT::isInteger(LVT));
2811 unsigned NumMemOps = 0;
2813 unsigned VTSize = getSizeInBits(VT) / 8;
2814 while (VTSize > Size) {
2815 VT = (MVT::ValueType)((unsigned)VT - 1);
2818 assert(MVT::isInteger(VT));
2820 if (++NumMemOps > Limit)
2822 MemOps.push_back(VT);
2829 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
2830 SDOperand Op1 = getValue(I.getOperand(1));
2831 SDOperand Op2 = getValue(I.getOperand(2));
2832 SDOperand Op3 = getValue(I.getOperand(3));
2833 SDOperand Op4 = getValue(I.getOperand(4));
2834 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
2835 if (Align == 0) Align = 1;
2837 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
2838 std::vector<MVT::ValueType> MemOps;
2840 // Expand memset / memcpy to a series of load / store ops
2841 // if the size operand falls below a certain threshold.
2842 std::vector<SDOperand> OutChains;
2844 default: break; // Do nothing for now.
2846 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
2847 Size->getValue(), Align, TLI)) {
2848 unsigned NumMemOps = MemOps.size();
2849 unsigned Offset = 0;
2850 for (unsigned i = 0; i < NumMemOps; i++) {
2851 MVT::ValueType VT = MemOps[i];
2852 unsigned VTSize = getSizeInBits(VT) / 8;
2853 SDOperand Value = getMemsetValue(Op2, VT, DAG);
2854 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(),
2856 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
2857 DAG.getSrcValue(I.getOperand(1), Offset));
2858 OutChains.push_back(Store);
2865 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
2866 Size->getValue(), Align, TLI)) {
2867 unsigned NumMemOps = MemOps.size();
2868 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
2869 GlobalAddressSDNode *G = NULL;
2871 bool CopyFromStr = false;
2873 if (Op2.getOpcode() == ISD::GlobalAddress)
2874 G = cast<GlobalAddressSDNode>(Op2);
2875 else if (Op2.getOpcode() == ISD::ADD &&
2876 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
2877 Op2.getOperand(1).getOpcode() == ISD::Constant) {
2878 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
2879 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
2882 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
2884 Str = GV->getStringValue(false);
2892 for (unsigned i = 0; i < NumMemOps; i++) {
2893 MVT::ValueType VT = MemOps[i];
2894 unsigned VTSize = getSizeInBits(VT) / 8;
2895 SDOperand Value, Chain, Store;
2898 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
2901 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2902 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2903 DAG.getSrcValue(I.getOperand(1), DstOff));
2905 Value = DAG.getLoad(VT, getRoot(),
2906 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
2907 DAG.getSrcValue(I.getOperand(2), SrcOff));
2908 Chain = Value.getValue(1);
2910 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2911 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2912 DAG.getSrcValue(I.getOperand(1), DstOff));
2914 OutChains.push_back(Store);
2923 if (!OutChains.empty()) {
2924 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
2929 std::vector<SDOperand> Ops;
2930 Ops.push_back(getRoot());
2935 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
2938 //===----------------------------------------------------------------------===//
2939 // SelectionDAGISel code
2940 //===----------------------------------------------------------------------===//
2942 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
2943 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
2946 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
2947 // FIXME: we only modify the CFG to split critical edges. This
2948 // updates dom and loop info.
2952 /// OptimizeNoopCopyExpression - We have determined that the specified cast
2953 /// instruction is a noop copy (e.g. it's casting from one pointer type to
2954 /// another, int->uint, or int->sbyte on PPC.
2956 /// Return true if any changes are made.
2957 static bool OptimizeNoopCopyExpression(CastInst *CI) {
2958 BasicBlock *DefBB = CI->getParent();
2960 /// InsertedCasts - Only insert a cast in each block once.
2961 std::map<BasicBlock*, CastInst*> InsertedCasts;
2963 bool MadeChange = false;
2964 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
2966 Use &TheUse = UI.getUse();
2967 Instruction *User = cast<Instruction>(*UI);
2969 // Figure out which BB this cast is used in. For PHI's this is the
2970 // appropriate predecessor block.
2971 BasicBlock *UserBB = User->getParent();
2972 if (PHINode *PN = dyn_cast<PHINode>(User)) {
2973 unsigned OpVal = UI.getOperandNo()/2;
2974 UserBB = PN->getIncomingBlock(OpVal);
2977 // Preincrement use iterator so we don't invalidate it.
2980 // If this user is in the same block as the cast, don't change the cast.
2981 if (UserBB == DefBB) continue;
2983 // If we have already inserted a cast into this block, use it.
2984 CastInst *&InsertedCast = InsertedCasts[UserBB];
2986 if (!InsertedCast) {
2987 BasicBlock::iterator InsertPt = UserBB->begin();
2988 while (isa<PHINode>(InsertPt)) ++InsertPt;
2991 new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
2995 // Replace a use of the cast with a use of the new casat.
2996 TheUse = InsertedCast;
2999 // If we removed all uses, nuke the cast.
3000 if (CI->use_empty())
3001 CI->eraseFromParent();
3006 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
3007 /// casting to the type of GEPI.
3008 static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
3009 Instruction *GEPI, Value *Ptr,
3011 if (V) return V; // Already computed.
3013 BasicBlock::iterator InsertPt;
3014 if (BB == GEPI->getParent()) {
3015 // If insert into the GEP's block, insert right after the GEP.
3019 // Otherwise, insert at the top of BB, after any PHI nodes
3020 InsertPt = BB->begin();
3021 while (isa<PHINode>(InsertPt)) ++InsertPt;
3024 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3025 // BB so that there is only one value live across basic blocks (the cast
3027 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3028 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3029 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3031 // Add the offset, cast it to the right type.
3032 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
3033 return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
3036 /// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3037 /// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
3038 /// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3039 /// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
3040 /// sink PtrOffset into user blocks where doing so will likely allow us to fold
3041 /// the constant add into a load or store instruction. Additionally, if a user
3042 /// is a pointer-pointer cast, we look through it to find its users.
3043 static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3044 Constant *PtrOffset, BasicBlock *DefBB,
3045 GetElementPtrInst *GEPI,
3046 std::map<BasicBlock*,Instruction*> &InsertedExprs) {
3047 while (!RepPtr->use_empty()) {
3048 Instruction *User = cast<Instruction>(RepPtr->use_back());
3050 // If the user is a Pointer-Pointer cast, recurse.
3051 if (isa<CastInst>(User) && isa<PointerType>(User->getType())) {
3052 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3054 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
3055 // could invalidate an iterator.
3056 User->setOperand(0, UndefValue::get(RepPtr->getType()));
3060 // If this is a load of the pointer, or a store through the pointer, emit
3061 // the increment into the load/store block.
3062 Instruction *NewVal;
3063 if (isa<LoadInst>(User) ||
3064 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3065 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3066 User->getParent(), GEPI,
3069 // If this use is not foldable into the addressing mode, use a version
3070 // emitted in the GEP block.
3071 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3075 if (GEPI->getType() != RepPtr->getType()) {
3076 BasicBlock::iterator IP = NewVal;
3078 NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP);
3080 User->replaceUsesOfWith(RepPtr, NewVal);
3085 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3086 /// selection, we want to be a bit careful about some things. In particular, if
3087 /// we have a GEP instruction that is used in a different block than it is
3088 /// defined, the addressing expression of the GEP cannot be folded into loads or
3089 /// stores that use it. In this case, decompose the GEP and move constant
3090 /// indices into blocks that use it.
3091 static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
3092 const TargetData *TD) {
3093 // If this GEP is only used inside the block it is defined in, there is no
3094 // need to rewrite it.
3095 bool isUsedOutsideDefBB = false;
3096 BasicBlock *DefBB = GEPI->getParent();
3097 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3099 if (cast<Instruction>(*UI)->getParent() != DefBB) {
3100 isUsedOutsideDefBB = true;
3104 if (!isUsedOutsideDefBB) return false;
3106 // If this GEP has no non-zero constant indices, there is nothing we can do,
3108 bool hasConstantIndex = false;
3109 bool hasVariableIndex = false;
3110 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3111 E = GEPI->op_end(); OI != E; ++OI) {
3112 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
3113 if (CI->getRawValue()) {
3114 hasConstantIndex = true;
3118 hasVariableIndex = true;
3122 // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3123 if (!hasConstantIndex && !hasVariableIndex) {
3124 Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(),
3125 GEPI->getName(), GEPI);
3126 GEPI->replaceAllUsesWith(NC);
3127 GEPI->eraseFromParent();
3131 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
3132 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3135 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
3136 // constant offset (which we now know is non-zero) and deal with it later.
3137 uint64_t ConstantOffset = 0;
3138 const Type *UIntPtrTy = TD->getIntPtrType();
3139 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3140 const Type *Ty = GEPI->getOperand(0)->getType();
3142 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3143 E = GEPI->op_end(); OI != E; ++OI) {
3145 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3146 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
3148 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
3149 Ty = StTy->getElementType(Field);
3151 Ty = cast<SequentialType>(Ty)->getElementType();
3153 // Handle constant subscripts.
3154 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3155 if (CI->getRawValue() == 0) continue;
3157 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
3158 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
3160 ConstantOffset+=TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
3164 // Ptr = Ptr + Idx * ElementSize;
3166 // Cast Idx to UIntPtrTy if needed.
3167 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
3169 uint64_t ElementSize = TD->getTypeSize(Ty);
3170 // Mask off bits that should not be set.
3171 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3172 Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize);
3174 // Multiply by the element size and add to the base.
3175 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3176 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3180 // Make sure that the offset fits in uintptr_t.
3181 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3182 Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset);
3184 // Okay, we have now emitted all of the variable index parts to the BB that
3185 // the GEP is defined in. Loop over all of the using instructions, inserting
3186 // an "add Ptr, ConstantOffset" into each block that uses it and update the
3187 // instruction to use the newly computed value, making GEPI dead. When the
3188 // user is a load or store instruction address, we emit the add into the user
3189 // block, otherwise we use a canonical version right next to the gep (these
3190 // won't be foldable as addresses, so we might as well share the computation).
3192 std::map<BasicBlock*,Instruction*> InsertedExprs;
3193 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3195 // Finally, the GEP is dead, remove it.
3196 GEPI->eraseFromParent();
3201 bool SelectionDAGISel::runOnFunction(Function &Fn) {
3202 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3203 RegMap = MF.getSSARegMap();
3204 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
3206 // First, split all critical edges for PHI nodes with incoming values that are
3207 // constants, this way the load of the constant into a vreg will not be placed
3208 // into MBBs that are used some other way.
3210 // In this pass we also look for GEP and cast instructions that are used
3211 // across basic blocks and rewrite them to improve basic-block-at-a-time
3215 bool MadeChange = true;
3216 while (MadeChange) {
3218 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
3220 BasicBlock::iterator BBI;
3221 for (BBI = BB->begin(); (PN = dyn_cast<PHINode>(BBI)); ++BBI)
3222 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
3223 if (isa<Constant>(PN->getIncomingValue(i)))
3224 SplitCriticalEdge(PN->getIncomingBlock(i), BB);
3226 for (BasicBlock::iterator E = BB->end(); BBI != E; ) {
3227 Instruction *I = BBI++;
3228 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
3229 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
3230 } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
3231 // If this is a noop copy, sink it into user blocks to reduce the number
3232 // of virtual registers that must be created and coallesced.
3233 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
3234 MVT::ValueType DstVT = TLI.getValueType(CI->getType());
3236 // This is an fp<->int conversion?
3237 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
3240 // If this is an extension, it will be a zero or sign extension, which
3242 if (SrcVT < DstVT) continue;
3244 // If these values will be promoted, find out what they will be promoted
3245 // to. This helps us consider truncates on PPC as noop copies when they
3247 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
3248 SrcVT = TLI.getTypeToTransformTo(SrcVT);
3249 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
3250 DstVT = TLI.getTypeToTransformTo(DstVT);
3252 // If, after promotion, these are the same types, this is a noop copy.
3254 MadeChange |= OptimizeNoopCopyExpression(CI);
3260 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
3262 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
3263 SelectBasicBlock(I, MF, FuncInfo);
3269 SDOperand SelectionDAGISel::
3270 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
3271 SDOperand Op = SDL.getValue(V);
3272 assert((Op.getOpcode() != ISD::CopyFromReg ||
3273 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
3274 "Copy from a reg to the same reg!");
3276 // If this type is not legal, we must make sure to not create an invalid
3278 MVT::ValueType SrcVT = Op.getValueType();
3279 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
3280 SelectionDAG &DAG = SDL.DAG;
3281 if (SrcVT == DestVT) {
3282 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3283 } else if (SrcVT == MVT::Vector) {
3284 // Handle copies from generic vectors to registers.
3285 MVT::ValueType PTyElementVT, PTyLegalElementVT;
3286 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
3287 PTyElementVT, PTyLegalElementVT);
3289 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
3290 // MVT::Vector type.
3291 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
3292 DAG.getConstant(NE, MVT::i32),
3293 DAG.getValueType(PTyElementVT));
3295 // Loop over all of the elements of the resultant vector,
3296 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
3297 // copying them into output registers.
3298 std::vector<SDOperand> OutChains;
3299 SDOperand Root = SDL.getRoot();
3300 for (unsigned i = 0; i != NE; ++i) {
3301 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
3302 Op, DAG.getConstant(i, MVT::i32));
3303 if (PTyElementVT == PTyLegalElementVT) {
3304 // Elements are legal.
3305 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3306 } else if (PTyLegalElementVT > PTyElementVT) {
3307 // Elements are promoted.
3308 if (MVT::isFloatingPoint(PTyLegalElementVT))
3309 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
3311 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
3312 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3314 // Elements are expanded.
3315 // The src value is expanded into multiple registers.
3316 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3317 Elt, DAG.getConstant(0, MVT::i32));
3318 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3319 Elt, DAG.getConstant(1, MVT::i32));
3320 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
3321 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
3324 return DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
3325 } else if (SrcVT < DestVT) {
3326 // The src value is promoted to the register.
3327 if (MVT::isFloatingPoint(SrcVT))
3328 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
3330 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
3331 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3333 // The src value is expanded into multiple registers.
3334 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3335 Op, DAG.getConstant(0, MVT::i32));
3336 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3337 Op, DAG.getConstant(1, MVT::i32));
3338 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
3339 return DAG.getCopyToReg(Op, Reg+1, Hi);
3343 void SelectionDAGISel::
3344 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
3345 std::vector<SDOperand> &UnorderedChains) {
3346 // If this is the entry block, emit arguments.
3347 Function &F = *BB->getParent();
3348 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
3349 SDOperand OldRoot = SDL.DAG.getRoot();
3350 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
3353 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
3355 if (!AI->use_empty()) {
3356 SDL.setValue(AI, Args[a]);
3358 // If this argument is live outside of the entry block, insert a copy from
3359 // whereever we got it to the vreg that other BB's will reference it as.
3360 if (FuncInfo.ValueMap.count(AI)) {
3362 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
3363 UnorderedChains.push_back(Copy);
3367 // Finally, if the target has anything special to do, allow it to do so.
3368 // FIXME: this should insert code into the DAG!
3369 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
3372 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3373 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
3374 FunctionLoweringInfo &FuncInfo) {
3375 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
3377 std::vector<SDOperand> UnorderedChains;
3379 // Lower any arguments needed in this block if this is the entry block.
3380 if (LLVMBB == &LLVMBB->getParent()->front())
3381 LowerArguments(LLVMBB, SDL, UnorderedChains);
3383 BB = FuncInfo.MBBMap[LLVMBB];
3384 SDL.setCurrentBasicBlock(BB);
3386 // Lower all of the non-terminator instructions.
3387 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3391 // Ensure that all instructions which are used outside of their defining
3392 // blocks are available as virtual registers.
3393 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
3394 if (!I->use_empty() && !isa<PHINode>(I)) {
3395 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
3396 if (VMI != FuncInfo.ValueMap.end())
3397 UnorderedChains.push_back(
3398 CopyValueToVirtualRegister(SDL, I, VMI->second));
3401 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
3402 // ensure constants are generated when needed. Remember the virtual registers
3403 // that need to be added to the Machine PHI nodes as input. We cannot just
3404 // directly add them, because expansion might result in multiple MBB's for one
3405 // BB. As such, the start of the BB might correspond to a different MBB than
3409 // Emit constants only once even if used by multiple PHI nodes.
3410 std::map<Constant*, unsigned> ConstantsOut;
3412 // Check successor nodes PHI nodes that expect a constant to be available from
3414 TerminatorInst *TI = LLVMBB->getTerminator();
3415 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
3416 BasicBlock *SuccBB = TI->getSuccessor(succ);
3417 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
3420 // At this point we know that there is a 1-1 correspondence between LLVM PHI
3421 // nodes and Machine PHI nodes, but the incoming operands have not been
3423 for (BasicBlock::iterator I = SuccBB->begin();
3424 (PN = dyn_cast<PHINode>(I)); ++I)
3425 if (!PN->use_empty()) {
3427 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
3428 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
3429 unsigned &RegOut = ConstantsOut[C];
3431 RegOut = FuncInfo.CreateRegForValue(C);
3432 UnorderedChains.push_back(
3433 CopyValueToVirtualRegister(SDL, C, RegOut));
3437 Reg = FuncInfo.ValueMap[PHIOp];
3439 assert(isa<AllocaInst>(PHIOp) &&
3440 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
3441 "Didn't codegen value into a register!??");
3442 Reg = FuncInfo.CreateRegForValue(PHIOp);
3443 UnorderedChains.push_back(
3444 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
3448 // Remember that this register needs to added to the machine PHI node as
3449 // the input for this MBB.
3450 MVT::ValueType VT = TLI.getValueType(PN->getType());
3451 unsigned NumElements;
3452 if (VT != MVT::Vector)
3453 NumElements = TLI.getNumElements(VT);
3455 MVT::ValueType VT1,VT2;
3457 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
3460 for (unsigned i = 0, e = NumElements; i != e; ++i)
3461 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
3464 ConstantsOut.clear();
3466 // Turn all of the unordered chains into one factored node.
3467 if (!UnorderedChains.empty()) {
3468 SDOperand Root = SDL.getRoot();
3469 if (Root.getOpcode() != ISD::EntryToken) {
3470 unsigned i = 0, e = UnorderedChains.size();
3471 for (; i != e; ++i) {
3472 assert(UnorderedChains[i].Val->getNumOperands() > 1);
3473 if (UnorderedChains[i].Val->getOperand(0) == Root)
3474 break; // Don't add the root if we already indirectly depend on it.
3478 UnorderedChains.push_back(Root);
3480 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
3483 // Lower the terminator after the copies are emitted.
3484 SDL.visit(*LLVMBB->getTerminator());
3486 // Copy over any CaseBlock records that may now exist due to SwitchInst
3487 // lowering, as well as any jump table information.
3488 SwitchCases.clear();
3489 SwitchCases = SDL.SwitchCases;
3492 // Make sure the root of the DAG is up-to-date.
3493 DAG.setRoot(SDL.getRoot());
3496 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
3497 // Run the DAG combiner in pre-legalize mode.
3500 DEBUG(std::cerr << "Lowered selection DAG:\n");
3503 // Second step, hack on the DAG until it only uses operations and types that
3504 // the target supports.
3507 DEBUG(std::cerr << "Legalized selection DAG:\n");
3510 // Run the DAG combiner in post-legalize mode.
3513 if (ViewISelDAGs) DAG.viewGraph();
3515 // Third, instruction select all of the operations to machine code, adding the
3516 // code to the MachineBasicBlock.
3517 InstructionSelectBasicBlock(DAG);
3519 DEBUG(std::cerr << "Selected machine code:\n");
3523 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
3524 FunctionLoweringInfo &FuncInfo) {
3525 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
3527 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3530 // First step, lower LLVM code to some DAG. This DAG may use operations and
3531 // types that are not supported by the target.
3532 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
3534 // Second step, emit the lowered DAG as machine code.
3535 CodeGenAndEmitDAG(DAG);
3538 // Next, now that we know what the last MBB the LLVM BB expanded is, update
3539 // PHI nodes in successors.
3540 if (SwitchCases.empty() && JT.Reg == 0) {
3541 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3542 MachineInstr *PHI = PHINodesToUpdate[i].first;
3543 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3544 "This is not a machine PHI node that we are updating!");
3545 PHI->addRegOperand(PHINodesToUpdate[i].second);
3546 PHI->addMachineBasicBlockOperand(BB);
3551 // If the JumpTable record is filled in, then we need to emit a jump table.
3552 // Updating the PHI nodes is tricky in this case, since we need to determine
3553 // whether the PHI is a successor of the range check MBB or the jump table MBB
3555 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
3556 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3558 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3559 MachineBasicBlock *RangeBB = BB;
3560 // Set the current basic block to the mbb we wish to insert the code into
3562 SDL.setCurrentBasicBlock(BB);
3564 SDL.visitJumpTable(JT);
3565 SDAG.setRoot(SDL.getRoot());
3566 CodeGenAndEmitDAG(SDAG);
3568 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3569 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3570 MachineBasicBlock *PHIBB = PHI->getParent();
3571 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3572 "This is not a machine PHI node that we are updating!");
3573 if (PHIBB == JT.Default) {
3574 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3575 PHI->addMachineBasicBlockOperand(RangeBB);
3577 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
3578 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3579 PHI->addMachineBasicBlockOperand(BB);
3585 // If we generated any switch lowering information, build and codegen any
3586 // additional DAGs necessary.
3587 for(unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
3588 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3590 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3591 // Set the current basic block to the mbb we wish to insert the code into
3592 BB = SwitchCases[i].ThisBB;
3593 SDL.setCurrentBasicBlock(BB);
3595 SDL.visitSwitchCase(SwitchCases[i]);
3596 SDAG.setRoot(SDL.getRoot());
3597 CodeGenAndEmitDAG(SDAG);
3598 // Iterate over the phi nodes, if there is a phi node in a successor of this
3599 // block (for instance, the default block), then add a pair of operands to
3600 // the phi node for this block, as if we were coming from the original
3601 // BB before switch expansion.
3602 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3603 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3604 MachineBasicBlock *PHIBB = PHI->getParent();
3605 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3606 "This is not a machine PHI node that we are updating!");
3607 if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
3608 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3609 PHI->addMachineBasicBlockOperand(BB);
3615 //===----------------------------------------------------------------------===//
3616 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
3617 /// target node in the graph.
3618 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
3619 if (ViewSchedDAGs) DAG.viewGraph();
3620 ScheduleDAG *SL = NULL;
3622 switch (ISHeuristic) {
3623 default: assert(0 && "Unrecognized scheduling heuristic");
3624 case defaultScheduling:
3625 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
3626 SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
3628 assert(TLI.getSchedulingPreference() ==
3629 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
3630 SL = createBURRListDAGScheduler(DAG, BB);
3634 SL = createBFS_DAGScheduler(DAG, BB);
3636 case simpleScheduling:
3637 SL = createSimpleDAGScheduler(false, DAG, BB);
3639 case simpleNoItinScheduling:
3640 SL = createSimpleDAGScheduler(true, DAG, BB);
3642 case listSchedulingBURR:
3643 SL = createBURRListDAGScheduler(DAG, BB);
3645 case listSchedulingTDRR:
3646 SL = createTDRRListDAGScheduler(DAG, BB);
3648 case listSchedulingTD:
3649 SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
3656 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
3657 return new HazardRecognizer();
3660 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
3661 /// by tblgen. Others should not call it.
3662 void SelectionDAGISel::
3663 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
3664 std::vector<SDOperand> InOps;
3665 std::swap(InOps, Ops);
3667 Ops.push_back(InOps[0]); // input chain.
3668 Ops.push_back(InOps[1]); // input asm string.
3670 unsigned i = 2, e = InOps.size();
3671 if (InOps[e-1].getValueType() == MVT::Flag)
3672 --e; // Don't process a flag operand if it is here.
3675 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
3676 if ((Flags & 7) != 4 /*MEM*/) {
3677 // Just skip over this operand, copying the operands verbatim.
3678 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
3679 i += (Flags >> 3) + 1;
3681 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
3682 // Otherwise, this is a memory operand. Ask the target to select it.
3683 std::vector<SDOperand> SelOps;
3684 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
3685 std::cerr << "Could not match memory address. Inline asm failure!\n";
3689 // Add this to the output node.
3690 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
3691 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
3696 // Add the flag input back if present.
3697 if (e != InOps.size())
3698 Ops.push_back(InOps.back());