1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/CFG.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/DebugInfo.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/IR/LLVMContext.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/Timer.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Target/TargetInstrInfo.h"
51 #include "llvm/Target/TargetIntrinsicInfo.h"
52 #include "llvm/Target/TargetLibraryInfo.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "llvm/Target/TargetRegisterInfo.h"
57 #include "llvm/Target/TargetSubtargetInfo.h"
58 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
62 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
63 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
64 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
65 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
66 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
68 STATISTIC(NumFastIselFailLowerArguments,
69 "Number of entry blocks where fast isel failed to lower arguments");
73 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
74 cl::desc("Enable extra verbose messages in the \"fast\" "
75 "instruction selector"));
78 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
79 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
80 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
81 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
82 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
83 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
84 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
86 // Standard binary operators...
87 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
88 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
89 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
90 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
91 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
92 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
93 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
94 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
95 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
96 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
97 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
98 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
100 // Logical operators...
101 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
102 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
103 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
105 // Memory instructions...
106 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
107 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
108 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
109 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
110 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
111 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
112 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
114 // Convert instructions...
115 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
116 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
117 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
118 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
119 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
120 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
121 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
122 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
123 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
124 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
125 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
126 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
128 // Other instructions...
129 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
130 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
131 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
132 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
133 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
134 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
135 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
136 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
137 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
138 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
139 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
140 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
141 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
142 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
143 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
147 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
148 cl::desc("Enable verbose messages in the \"fast\" "
149 "instruction selector"));
151 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
152 cl::desc("Enable abort calls when \"fast\" instruction selection "
153 "fails to lower an instruction"));
155 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
156 cl::desc("Enable abort calls when \"fast\" instruction selection "
157 "fails to lower a formal argument"));
161 cl::desc("use Machine Branch Probability Info"),
162 cl::init(true), cl::Hidden);
166 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
167 cl::desc("Pop up a window to show dags before the first "
168 "dag combine pass"));
170 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
171 cl::desc("Pop up a window to show dags before legalize types"));
173 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
174 cl::desc("Pop up a window to show dags before legalize"));
176 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
177 cl::desc("Pop up a window to show dags before the second "
178 "dag combine pass"));
180 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
181 cl::desc("Pop up a window to show dags before the post legalize types"
182 " dag combine pass"));
184 ViewISelDAGs("view-isel-dags", cl::Hidden,
185 cl::desc("Pop up a window to show isel dags as they are selected"));
187 ViewSchedDAGs("view-sched-dags", cl::Hidden,
188 cl::desc("Pop up a window to show sched dags as they are processed"));
190 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
191 cl::desc("Pop up a window to show SUnit dags after they are processed"));
193 static const bool ViewDAGCombine1 = false,
194 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
195 ViewDAGCombine2 = false,
196 ViewDAGCombineLT = false,
197 ViewISelDAGs = false, ViewSchedDAGs = false,
198 ViewSUnitDAGs = false;
201 //===---------------------------------------------------------------------===//
203 /// RegisterScheduler class - Track the registration of instruction schedulers.
205 //===---------------------------------------------------------------------===//
206 MachinePassRegistry RegisterScheduler::Registry;
208 //===---------------------------------------------------------------------===//
210 /// ISHeuristic command line option for instruction schedulers.
212 //===---------------------------------------------------------------------===//
213 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
214 RegisterPassParser<RegisterScheduler> >
215 ISHeuristic("pre-RA-sched",
216 cl::init(&createDefaultScheduler),
217 cl::desc("Instruction schedulers available (before register"
220 static RegisterScheduler
221 defaultListDAGScheduler("default", "Best scheduler for the target",
222 createDefaultScheduler);
225 //===--------------------------------------------------------------------===//
226 /// createDefaultScheduler - This creates an instruction scheduler appropriate
228 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
229 CodeGenOpt::Level OptLevel) {
230 const TargetLowering *TLI = IS->getTargetLowering();
231 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
233 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
234 TLI->getSchedulingPreference() == Sched::Source)
235 return createSourceListDAGScheduler(IS, OptLevel);
236 if (TLI->getSchedulingPreference() == Sched::RegPressure)
237 return createBURRListDAGScheduler(IS, OptLevel);
238 if (TLI->getSchedulingPreference() == Sched::Hybrid)
239 return createHybridListDAGScheduler(IS, OptLevel);
240 if (TLI->getSchedulingPreference() == Sched::VLIW)
241 return createVLIWDAGScheduler(IS, OptLevel);
242 assert(TLI->getSchedulingPreference() == Sched::ILP &&
243 "Unknown sched type!");
244 return createILPListDAGScheduler(IS, OptLevel);
248 // EmitInstrWithCustomInserter - This method should be implemented by targets
249 // that mark instructions with the 'usesCustomInserter' flag. These
250 // instructions are special in various ways, which require special support to
251 // insert. The specified MachineInstr is created but not inserted into any
252 // basic blocks, and this method is called to expand it into a sequence of
253 // instructions, potentially also creating new basic blocks and control flow.
254 // When new basic blocks are inserted and the edges from MBB to its successors
255 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
258 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
259 MachineBasicBlock *MBB) const {
261 dbgs() << "If a target marks an instruction with "
262 "'usesCustomInserter', it must implement "
263 "TargetLowering::EmitInstrWithCustomInserter!";
268 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
269 SDNode *Node) const {
270 assert(!MI->hasPostISelHook() &&
271 "If a target marks an instruction with 'hasPostISelHook', "
272 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
275 //===----------------------------------------------------------------------===//
276 // SelectionDAGISel code
277 //===----------------------------------------------------------------------===//
279 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
280 CodeGenOpt::Level OL) :
281 MachineFunctionPass(ID), TM(tm),
282 FuncInfo(new FunctionLoweringInfo(TM)),
283 CurDAG(new SelectionDAG(tm, OL)),
284 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
288 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
289 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
290 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
291 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
294 SelectionDAGISel::~SelectionDAGISel() {
300 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
301 AU.addRequired<AliasAnalysis>();
302 AU.addPreserved<AliasAnalysis>();
303 AU.addRequired<GCModuleInfo>();
304 AU.addPreserved<GCModuleInfo>();
305 AU.addRequired<TargetLibraryInfo>();
306 if (UseMBPI && OptLevel != CodeGenOpt::None)
307 AU.addRequired<BranchProbabilityInfo>();
308 MachineFunctionPass::getAnalysisUsage(AU);
311 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
312 /// may trap on it. In this case we have to split the edge so that the path
313 /// through the predecessor block that doesn't go to the phi block doesn't
314 /// execute the possibly trapping instruction.
316 /// This is required for correctness, so it must be done at -O0.
318 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
319 // Loop for blocks with phi nodes.
320 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
321 PHINode *PN = dyn_cast<PHINode>(BB->begin());
322 if (PN == 0) continue;
325 // For each block with a PHI node, check to see if any of the input values
326 // are potentially trapping constant expressions. Constant expressions are
327 // the only potentially trapping value that can occur as the argument to a
329 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
330 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
331 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
332 if (CE == 0 || !CE->canTrap()) continue;
334 // The only case we have to worry about is when the edge is critical.
335 // Since this block has a PHI Node, we assume it has multiple input
336 // edges: check to see if the pred has multiple successors.
337 BasicBlock *Pred = PN->getIncomingBlock(i);
338 if (Pred->getTerminator()->getNumSuccessors() == 1)
341 // Okay, we have to split this edge.
342 SplitCriticalEdge(Pred->getTerminator(),
343 GetSuccessorNumber(Pred, BB), SDISel, true);
349 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
350 // Do some sanity-checking on the command-line options.
351 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
352 "-fast-isel-verbose requires -fast-isel");
353 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
354 "-fast-isel-abort requires -fast-isel");
356 const Function &Fn = *mf.getFunction();
357 const TargetInstrInfo &TII = *TM.getInstrInfo();
358 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
361 RegInfo = &MF->getRegInfo();
362 AA = &getAnalysis<AliasAnalysis>();
363 LibInfo = &getAnalysis<TargetLibraryInfo>();
364 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
365 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
367 TargetSubtargetInfo &ST =
368 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
369 ST.resetSubtargetFeatures(MF);
370 TM.resetTargetOptions(MF);
372 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
374 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
376 CurDAG->init(*MF, TTI);
377 FuncInfo->set(Fn, *MF);
379 if (UseMBPI && OptLevel != CodeGenOpt::None)
380 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
384 SDB->init(GFI, *AA, LibInfo);
386 MF->setHasMSInlineAsm(false);
387 SelectAllBasicBlocks(Fn);
389 // If the first basic block in the function has live ins that need to be
390 // copied into vregs, emit the copies into the top of the block before
391 // emitting the code for the block.
392 MachineBasicBlock *EntryMBB = MF->begin();
393 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
395 DenseMap<unsigned, unsigned> LiveInMap;
396 if (!FuncInfo->ArgDbgValues.empty())
397 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
398 E = RegInfo->livein_end(); LI != E; ++LI)
400 LiveInMap.insert(std::make_pair(LI->first, LI->second));
402 // Insert DBG_VALUE instructions for function arguments to the entry block.
403 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
404 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
405 bool hasFI = MI->getOperand(0).isFI();
406 unsigned Reg = hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
407 if (TargetRegisterInfo::isPhysicalRegister(Reg))
408 EntryMBB->insert(EntryMBB->begin(), MI);
410 MachineInstr *Def = RegInfo->getVRegDef(Reg);
411 MachineBasicBlock::iterator InsertPos = Def;
412 // FIXME: VR def may not be in entry block.
413 Def->getParent()->insert(llvm::next(InsertPos), MI);
416 // If Reg is live-in then update debug info to track its copy in a vreg.
417 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
418 if (LDI != LiveInMap.end()) {
419 assert(!hasFI && "There's no handling of frame pointer updating here yet "
421 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
422 MachineBasicBlock::iterator InsertPos = Def;
423 const MDNode *Variable =
424 MI->getOperand(MI->getNumOperands()-1).getMetadata();
425 bool IsIndirect = MI->isIndirectDebugValue();
426 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
427 // Def is never a terminator here, so it is ok to increment InsertPos.
428 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
429 TII.get(TargetOpcode::DBG_VALUE),
431 LDI->second, Offset, Variable);
433 // If this vreg is directly copied into an exported register then
434 // that COPY instructions also need DBG_VALUE, if it is the only
435 // user of LDI->second.
436 MachineInstr *CopyUseMI = NULL;
437 for (MachineRegisterInfo::use_iterator
438 UI = RegInfo->use_begin(LDI->second);
439 MachineInstr *UseMI = UI.skipInstruction();) {
440 if (UseMI->isDebugValue()) continue;
441 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
442 CopyUseMI = UseMI; continue;
444 // Otherwise this is another use or second copy use.
445 CopyUseMI = NULL; break;
448 MachineInstr *NewMI =
449 BuildMI(*MF, CopyUseMI->getDebugLoc(),
450 TII.get(TargetOpcode::DBG_VALUE),
452 CopyUseMI->getOperand(0).getReg(),
454 MachineBasicBlock::iterator Pos = CopyUseMI;
455 EntryMBB->insertAfter(Pos, NewMI);
460 // Determine if there are any calls in this machine function.
461 MachineFrameInfo *MFI = MF->getFrameInfo();
462 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
465 if (MFI->hasCalls() && MF->hasMSInlineAsm())
468 const MachineBasicBlock *MBB = I;
469 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
471 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
472 if ((MCID.isCall() && !MCID.isReturn()) ||
473 II->isStackAligningInlineAsm()) {
474 MFI->setHasCalls(true);
476 if (II->isMSInlineAsm()) {
477 MF->setHasMSInlineAsm(true);
482 // Determine if there is a call to setjmp in the machine function.
483 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
485 // Replace forward-declared registers with the registers containing
486 // the desired value.
487 MachineRegisterInfo &MRI = MF->getRegInfo();
488 for (DenseMap<unsigned, unsigned>::iterator
489 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
491 unsigned From = I->first;
492 unsigned To = I->second;
493 // If To is also scheduled to be replaced, find what its ultimate
496 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
500 // Make sure the new register has a sufficiently constrained register class.
501 if (TargetRegisterInfo::isVirtualRegister(From) &&
502 TargetRegisterInfo::isVirtualRegister(To))
503 MRI.constrainRegClass(To, MRI.getRegClass(From));
505 MRI.replaceRegWith(From, To);
508 // Freeze the set of reserved registers now that MachineFrameInfo has been
509 // set up. All the information required by getReservedRegs() should be
511 MRI.freezeReservedRegs(*MF);
513 // Release function-specific state. SDB and CurDAG are already cleared
520 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
521 BasicBlock::const_iterator End,
523 // Lower all of the non-terminator instructions. If a call is emitted
524 // as a tail call, cease emitting nodes for this block. Terminators
525 // are handled below.
526 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
529 // Make sure the root of the DAG is up-to-date.
530 CurDAG->setRoot(SDB->getControlRoot());
531 HadTailCall = SDB->HasTailCall;
534 // Final step, emit the lowered DAG as machine code.
538 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
539 SmallPtrSet<SDNode*, 128> VisitedNodes;
540 SmallVector<SDNode*, 128> Worklist;
542 Worklist.push_back(CurDAG->getRoot().getNode());
548 SDNode *N = Worklist.pop_back_val();
550 // If we've already seen this node, ignore it.
551 if (!VisitedNodes.insert(N))
554 // Otherwise, add all chain operands to the worklist.
555 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
556 if (N->getOperand(i).getValueType() == MVT::Other)
557 Worklist.push_back(N->getOperand(i).getNode());
559 // If this is a CopyToReg with a vreg dest, process it.
560 if (N->getOpcode() != ISD::CopyToReg)
563 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
564 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
567 // Ignore non-scalar or non-integer values.
568 SDValue Src = N->getOperand(2);
569 EVT SrcVT = Src.getValueType();
570 if (!SrcVT.isInteger() || SrcVT.isVector())
573 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
574 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
575 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
576 } while (!Worklist.empty());
579 void SelectionDAGISel::CodeGenAndEmitDAG() {
580 std::string GroupName;
581 if (TimePassesIsEnabled)
582 GroupName = "Instruction Selection and Scheduling";
583 std::string BlockName;
584 int BlockNumber = -1;
587 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
588 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
592 BlockNumber = FuncInfo->MBB->getNumber();
593 BlockName = MF->getName().str() + ":" +
594 FuncInfo->MBB->getBasicBlock()->getName().str();
596 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
597 << " '" << BlockName << "'\n"; CurDAG->dump());
599 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
601 // Run the DAG combiner in pre-legalize mode.
603 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
604 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
607 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
608 << " '" << BlockName << "'\n"; CurDAG->dump());
610 // Second step, hack on the DAG until it only uses operations and types that
611 // the target supports.
612 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
617 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
618 Changed = CurDAG->LegalizeTypes();
621 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
622 << " '" << BlockName << "'\n"; CurDAG->dump());
625 if (ViewDAGCombineLT)
626 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
628 // Run the DAG combiner in post-type-legalize mode.
630 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
631 TimePassesIsEnabled);
632 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
635 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
636 << " '" << BlockName << "'\n"; CurDAG->dump());
641 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
642 Changed = CurDAG->LegalizeVectors();
647 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
648 CurDAG->LegalizeTypes();
651 if (ViewDAGCombineLT)
652 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
654 // Run the DAG combiner in post-type-legalize mode.
656 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
657 TimePassesIsEnabled);
658 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
661 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
662 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
665 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
668 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
672 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
673 << " '" << BlockName << "'\n"; CurDAG->dump());
675 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
677 // Run the DAG combiner in post-legalize mode.
679 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
680 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
683 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
684 << " '" << BlockName << "'\n"; CurDAG->dump());
686 if (OptLevel != CodeGenOpt::None)
687 ComputeLiveOutVRegInfo();
689 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
691 // Third, instruction select all of the operations to machine code, adding the
692 // code to the MachineBasicBlock.
694 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
695 DoInstructionSelection();
698 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
699 << " '" << BlockName << "'\n"; CurDAG->dump());
701 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
703 // Schedule machine code.
704 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
706 NamedRegionTimer T("Instruction Scheduling", GroupName,
707 TimePassesIsEnabled);
708 Scheduler->Run(CurDAG, FuncInfo->MBB);
711 if (ViewSUnitDAGs) Scheduler->viewGraph();
713 // Emit machine code to BB. This can change 'BB' to the last block being
715 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
717 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
719 // FuncInfo->InsertPt is passed by reference and set to the end of the
720 // scheduled instructions.
721 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
724 // If the block was split, make sure we update any references that are used to
725 // update PHI nodes later on.
726 if (FirstMBB != LastMBB)
727 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
729 // Free the scheduler state.
731 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
732 TimePassesIsEnabled);
736 // Free the SelectionDAG state, now that we're finished with it.
741 /// ISelUpdater - helper class to handle updates of the instruction selection
743 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
744 SelectionDAG::allnodes_iterator &ISelPosition;
746 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
747 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
749 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
750 /// deleted is the current ISelPosition node, update ISelPosition.
752 virtual void NodeDeleted(SDNode *N, SDNode *E) {
753 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
757 } // end anonymous namespace
759 void SelectionDAGISel::DoInstructionSelection() {
760 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
761 << FuncInfo->MBB->getNumber()
762 << " '" << FuncInfo->MBB->getName() << "'\n");
766 // Select target instructions for the DAG.
768 // Number all nodes with a topological order and set DAGSize.
769 DAGSize = CurDAG->AssignTopologicalOrder();
771 // Create a dummy node (which is not added to allnodes), that adds
772 // a reference to the root node, preventing it from being deleted,
773 // and tracking any changes of the root.
774 HandleSDNode Dummy(CurDAG->getRoot());
775 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
778 // Make sure that ISelPosition gets properly updated when nodes are deleted
779 // in calls made from this function.
780 ISelUpdater ISU(*CurDAG, ISelPosition);
782 // The AllNodes list is now topological-sorted. Visit the
783 // nodes by starting at the end of the list (the root of the
784 // graph) and preceding back toward the beginning (the entry
786 while (ISelPosition != CurDAG->allnodes_begin()) {
787 SDNode *Node = --ISelPosition;
788 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
789 // but there are currently some corner cases that it misses. Also, this
790 // makes it theoretically possible to disable the DAGCombiner.
791 if (Node->use_empty())
794 SDNode *ResNode = Select(Node);
796 // FIXME: This is pretty gross. 'Select' should be changed to not return
797 // anything at all and this code should be nuked with a tactical strike.
799 // If node should not be replaced, continue with the next one.
800 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
804 ReplaceUses(Node, ResNode);
807 // If after the replacement this node is not used any more,
808 // remove this dead node.
809 if (Node->use_empty()) // Don't delete EntryToken, etc.
810 CurDAG->RemoveDeadNode(Node);
813 CurDAG->setRoot(Dummy.getValue());
816 DEBUG(dbgs() << "===== Instruction selection ends:\n");
818 PostprocessISelDAG();
821 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
822 /// do other setup for EH landing-pad blocks.
823 void SelectionDAGISel::PrepareEHLandingPad() {
824 MachineBasicBlock *MBB = FuncInfo->MBB;
826 // Add a label to mark the beginning of the landing pad. Deletion of the
827 // landing pad can thus be detected via the MachineModuleInfo.
828 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
830 // Assign the call site to the landing pad's begin label.
831 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
833 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
834 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
837 // Mark exception register as live in.
838 const TargetLowering *TLI = getTargetLowering();
839 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
840 if (unsigned Reg = TLI->getExceptionPointerRegister())
841 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
843 // Mark exception selector register as live in.
844 if (unsigned Reg = TLI->getExceptionSelectorRegister())
845 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
848 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
849 /// side-effect free and is either dead or folded into a generated instruction.
850 /// Return false if it needs to be emitted.
851 static bool isFoldedOrDeadInstruction(const Instruction *I,
852 FunctionLoweringInfo *FuncInfo) {
853 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
854 !isa<TerminatorInst>(I) && // Terminators aren't folded.
855 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
856 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
857 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
861 // Collect per Instruction statistics for fast-isel misses. Only those
862 // instructions that cause the bail are accounted for. It does not account for
863 // instructions higher in the block. Thus, summing the per instructions stats
864 // will not add up to what is reported by NumFastIselFailures.
865 static void collectFailStats(const Instruction *I) {
866 switch (I->getOpcode()) {
867 default: assert (0 && "<Invalid operator> ");
870 case Instruction::Ret: NumFastIselFailRet++; return;
871 case Instruction::Br: NumFastIselFailBr++; return;
872 case Instruction::Switch: NumFastIselFailSwitch++; return;
873 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
874 case Instruction::Invoke: NumFastIselFailInvoke++; return;
875 case Instruction::Resume: NumFastIselFailResume++; return;
876 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
878 // Standard binary operators...
879 case Instruction::Add: NumFastIselFailAdd++; return;
880 case Instruction::FAdd: NumFastIselFailFAdd++; return;
881 case Instruction::Sub: NumFastIselFailSub++; return;
882 case Instruction::FSub: NumFastIselFailFSub++; return;
883 case Instruction::Mul: NumFastIselFailMul++; return;
884 case Instruction::FMul: NumFastIselFailFMul++; return;
885 case Instruction::UDiv: NumFastIselFailUDiv++; return;
886 case Instruction::SDiv: NumFastIselFailSDiv++; return;
887 case Instruction::FDiv: NumFastIselFailFDiv++; return;
888 case Instruction::URem: NumFastIselFailURem++; return;
889 case Instruction::SRem: NumFastIselFailSRem++; return;
890 case Instruction::FRem: NumFastIselFailFRem++; return;
892 // Logical operators...
893 case Instruction::And: NumFastIselFailAnd++; return;
894 case Instruction::Or: NumFastIselFailOr++; return;
895 case Instruction::Xor: NumFastIselFailXor++; return;
897 // Memory instructions...
898 case Instruction::Alloca: NumFastIselFailAlloca++; return;
899 case Instruction::Load: NumFastIselFailLoad++; return;
900 case Instruction::Store: NumFastIselFailStore++; return;
901 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
902 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
903 case Instruction::Fence: NumFastIselFailFence++; return;
904 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
906 // Convert instructions...
907 case Instruction::Trunc: NumFastIselFailTrunc++; return;
908 case Instruction::ZExt: NumFastIselFailZExt++; return;
909 case Instruction::SExt: NumFastIselFailSExt++; return;
910 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
911 case Instruction::FPExt: NumFastIselFailFPExt++; return;
912 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
913 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
914 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
915 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
916 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
917 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
918 case Instruction::BitCast: NumFastIselFailBitCast++; return;
920 // Other instructions...
921 case Instruction::ICmp: NumFastIselFailICmp++; return;
922 case Instruction::FCmp: NumFastIselFailFCmp++; return;
923 case Instruction::PHI: NumFastIselFailPHI++; return;
924 case Instruction::Select: NumFastIselFailSelect++; return;
925 case Instruction::Call: NumFastIselFailCall++; return;
926 case Instruction::Shl: NumFastIselFailShl++; return;
927 case Instruction::LShr: NumFastIselFailLShr++; return;
928 case Instruction::AShr: NumFastIselFailAShr++; return;
929 case Instruction::VAArg: NumFastIselFailVAArg++; return;
930 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
931 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
932 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
933 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
934 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
935 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
940 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
941 // Initialize the Fast-ISel state, if needed.
942 FastISel *FastIS = 0;
943 if (TM.Options.EnableFastISel)
944 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo);
946 // Iterate over all basic blocks in the function.
947 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
948 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
949 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
950 const BasicBlock *LLVMBB = *I;
952 if (OptLevel != CodeGenOpt::None) {
953 bool AllPredsVisited = true;
954 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
956 if (!FuncInfo->VisitedBBs.count(*PI)) {
957 AllPredsVisited = false;
962 if (AllPredsVisited) {
963 for (BasicBlock::const_iterator I = LLVMBB->begin();
964 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
965 FuncInfo->ComputePHILiveOutRegInfo(PN);
967 for (BasicBlock::const_iterator I = LLVMBB->begin();
968 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
969 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
972 FuncInfo->VisitedBBs.insert(LLVMBB);
975 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
976 BasicBlock::const_iterator const End = LLVMBB->end();
977 BasicBlock::const_iterator BI = End;
979 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
980 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
982 // Setup an EH landing-pad block.
983 FuncInfo->ExceptionPointerVirtReg = 0;
984 FuncInfo->ExceptionSelectorVirtReg = 0;
985 if (FuncInfo->MBB->isLandingPad())
986 PrepareEHLandingPad();
988 // Before doing SelectionDAG ISel, see if FastISel has been requested.
990 FastIS->startNewBlock();
992 // Emit code for any incoming arguments. This must happen before
993 // beginning FastISel on the entry block.
994 if (LLVMBB == &Fn.getEntryBlock()) {
997 // Lower any arguments needed in this block if this is the entry block.
998 if (!FastIS->LowerArguments()) {
999 // Fast isel failed to lower these arguments
1000 ++NumFastIselFailLowerArguments;
1001 if (EnableFastISelAbortArgs)
1002 llvm_unreachable("FastISel didn't lower all arguments");
1004 // Use SelectionDAG argument lowering
1006 CurDAG->setRoot(SDB->getControlRoot());
1008 CodeGenAndEmitDAG();
1011 // If we inserted any instructions at the beginning, make a note of
1012 // where they are, so we can be sure to emit subsequent instructions
1014 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1015 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1017 FastIS->setLastLocalValue(0);
1020 unsigned NumFastIselRemaining = std::distance(Begin, End);
1021 // Do FastISel on as many instructions as possible.
1022 for (; BI != Begin; --BI) {
1023 const Instruction *Inst = llvm::prior(BI);
1025 // If we no longer require this instruction, skip it.
1026 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1027 --NumFastIselRemaining;
1031 // Bottom-up: reset the insert pos at the top, after any local-value
1033 FastIS->recomputeInsertPt();
1035 // Try to select the instruction with FastISel.
1036 if (FastIS->SelectInstruction(Inst)) {
1037 --NumFastIselRemaining;
1038 ++NumFastIselSuccess;
1039 // If fast isel succeeded, skip over all the folded instructions, and
1040 // then see if there is a load right before the selected instructions.
1041 // Try to fold the load if so.
1042 const Instruction *BeforeInst = Inst;
1043 while (BeforeInst != Begin) {
1044 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1045 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1048 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1049 BeforeInst->hasOneUse() &&
1050 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1051 // If we succeeded, don't re-select the load.
1052 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1053 --NumFastIselRemaining;
1054 ++NumFastIselSuccess;
1060 if (EnableFastISelVerbose2)
1061 collectFailStats(Inst);
1064 // Then handle certain instructions as single-LLVM-Instruction blocks.
1065 if (isa<CallInst>(Inst)) {
1067 if (EnableFastISelVerbose || EnableFastISelAbort) {
1068 dbgs() << "FastISel missed call: ";
1072 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1073 unsigned &R = FuncInfo->ValueMap[Inst];
1075 R = FuncInfo->CreateRegs(Inst->getType());
1078 bool HadTailCall = false;
1079 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1080 SelectBasicBlock(Inst, BI, HadTailCall);
1082 // If the call was emitted as a tail call, we're done with the block.
1083 // We also need to delete any previously emitted instructions.
1085 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1090 // Recompute NumFastIselRemaining as Selection DAG instruction
1091 // selection may have handled the call, input args, etc.
1092 unsigned RemainingNow = std::distance(Begin, BI);
1093 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1094 NumFastIselRemaining = RemainingNow;
1098 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1099 // Don't abort, and use a different message for terminator misses.
1100 NumFastIselFailures += NumFastIselRemaining;
1101 if (EnableFastISelVerbose || EnableFastISelAbort) {
1102 dbgs() << "FastISel missed terminator: ";
1106 NumFastIselFailures += NumFastIselRemaining;
1107 if (EnableFastISelVerbose || EnableFastISelAbort) {
1108 dbgs() << "FastISel miss: ";
1111 if (EnableFastISelAbort)
1112 // The "fast" selector couldn't handle something and bailed.
1113 // For the purpose of debugging, just abort.
1114 llvm_unreachable("FastISel didn't select the entire block");
1119 FastIS->recomputeInsertPt();
1121 // Lower any arguments needed in this block if this is the entry block.
1122 if (LLVMBB == &Fn.getEntryBlock()) {
1131 ++NumFastIselBlocks;
1134 // Run SelectionDAG instruction selection on the remainder of the block
1135 // not handled by FastISel. If FastISel is not run, this is the entire
1138 SelectBasicBlock(Begin, BI, HadTailCall);
1142 FuncInfo->PHINodesToUpdate.clear();
1146 SDB->clearDanglingDebugInfo();
1147 SDB->SPDescriptor.resetPerFunctionState();
1150 /// Given that the input MI is before a partial terminator sequence TSeq, return
1151 /// true if M + TSeq also a partial terminator sequence.
1153 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1154 /// lowering copy vregs into physical registers, which are then passed into
1155 /// terminator instructors so we can satisfy ABI constraints. A partial
1156 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1157 /// may be the whole terminator sequence).
1158 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1159 // If we do not have a copy or an implicit def, we return true if and only if
1160 // MI is a debug value.
1161 if (!MI->isCopy() && !MI->isImplicitDef())
1162 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1163 // physical registers if there is debug info associated with the terminator
1164 // of our mbb. We want to include said debug info in our terminator
1165 // sequence, so we return true in that case.
1166 return MI->isDebugValue();
1168 // We have left the terminator sequence if we are not doing one of the
1171 // 1. Copying a vreg into a physical register.
1172 // 2. Copying a vreg into a vreg.
1173 // 3. Defining a register via an implicit def.
1175 // OPI should always be a register definition...
1176 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1177 if (!OPI->isReg() || !OPI->isDef())
1180 // Defining any register via an implicit def is always ok.
1181 if (MI->isImplicitDef())
1184 // Grab the copy source...
1185 MachineInstr::const_mop_iterator OPI2 = OPI;
1187 assert(OPI2 != MI->operands_end()
1188 && "Should have a copy implying we should have 2 arguments.");
1190 // Make sure that the copy dest is not a vreg when the copy source is a
1191 // physical register.
1192 if (!OPI2->isReg() ||
1193 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1194 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1200 /// Find the split point at which to splice the end of BB into its success stack
1201 /// protector check machine basic block.
1203 /// On many platforms, due to ABI constraints, terminators, even before register
1204 /// allocation, use physical registers. This creates an issue for us since
1205 /// physical registers at this point can not travel across basic
1206 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1207 /// when they enter functions and moves them through a sequence of copies back
1208 /// into the physical registers right before the terminator creating a
1209 /// ``Terminator Sequence''. This function is searching for the beginning of the
1210 /// terminator sequence so that we can ensure that we splice off not just the
1211 /// terminator, but additionally the copies that move the vregs into the
1212 /// physical registers.
1213 static MachineBasicBlock::iterator
1214 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1215 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1217 if (SplitPoint == BB->begin())
1220 MachineBasicBlock::iterator Start = BB->begin();
1221 MachineBasicBlock::iterator Previous = SplitPoint;
1224 while (MIIsInTerminatorSequence(Previous)) {
1225 SplitPoint = Previous;
1226 if (Previous == Start)
1235 SelectionDAGISel::FinishBasicBlock() {
1237 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1238 << FuncInfo->PHINodesToUpdate.size() << "\n";
1239 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1240 dbgs() << "Node " << i << " : ("
1241 << FuncInfo->PHINodesToUpdate[i].first
1242 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1244 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1245 SDB->JTCases.empty() &&
1246 SDB->BitTestCases.empty();
1248 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1249 // PHI nodes in successors.
1250 if (MustUpdatePHINodes) {
1251 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1252 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1253 assert(PHI->isPHI() &&
1254 "This is not a machine PHI node that we are updating!");
1255 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1257 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1261 // Handle stack protector.
1262 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1263 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1264 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1266 // Find the split point to split the parent mbb. At the same time copy all
1267 // physical registers used in the tail of parent mbb into virtual registers
1268 // before the split point and back into physical registers after the split
1269 // point. This prevents us needing to deal with Live-ins and many other
1270 // register allocation issues caused by us splitting the parent mbb. The
1271 // register allocator will clean up said virtual copies later on.
1272 MachineBasicBlock::iterator SplitPoint =
1273 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1275 // Splice the terminator of ParentMBB into SuccessMBB.
1276 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1280 // Add compare/jump on neq/jump to the parent BB.
1281 FuncInfo->MBB = ParentMBB;
1282 FuncInfo->InsertPt = ParentMBB->end();
1283 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1284 CurDAG->setRoot(SDB->getRoot());
1286 CodeGenAndEmitDAG();
1288 // CodeGen Failure MBB if we have not codegened it yet.
1289 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1290 if (!FailureMBB->size()) {
1291 FuncInfo->MBB = FailureMBB;
1292 FuncInfo->InsertPt = FailureMBB->end();
1293 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1294 CurDAG->setRoot(SDB->getRoot());
1296 CodeGenAndEmitDAG();
1299 // Clear the Per-BB State.
1300 SDB->SPDescriptor.resetPerBBState();
1303 // If we updated PHI Nodes, return early.
1304 if (MustUpdatePHINodes)
1307 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1308 // Lower header first, if it wasn't already lowered
1309 if (!SDB->BitTestCases[i].Emitted) {
1310 // Set the current basic block to the mbb we wish to insert the code into
1311 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1312 FuncInfo->InsertPt = FuncInfo->MBB->end();
1314 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1315 CurDAG->setRoot(SDB->getRoot());
1317 CodeGenAndEmitDAG();
1320 uint32_t UnhandledWeight = 0;
1321 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1322 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1324 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1325 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1326 // Set the current basic block to the mbb we wish to insert the code into
1327 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1328 FuncInfo->InsertPt = FuncInfo->MBB->end();
1331 SDB->visitBitTestCase(SDB->BitTestCases[i],
1332 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1334 SDB->BitTestCases[i].Reg,
1335 SDB->BitTestCases[i].Cases[j],
1338 SDB->visitBitTestCase(SDB->BitTestCases[i],
1339 SDB->BitTestCases[i].Default,
1341 SDB->BitTestCases[i].Reg,
1342 SDB->BitTestCases[i].Cases[j],
1346 CurDAG->setRoot(SDB->getRoot());
1348 CodeGenAndEmitDAG();
1352 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1354 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1355 MachineBasicBlock *PHIBB = PHI->getParent();
1356 assert(PHI->isPHI() &&
1357 "This is not a machine PHI node that we are updating!");
1358 // This is "default" BB. We have two jumps to it. From "header" BB and
1359 // from last "case" BB.
1360 if (PHIBB == SDB->BitTestCases[i].Default)
1361 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1362 .addMBB(SDB->BitTestCases[i].Parent)
1363 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1364 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1365 // One of "cases" BB.
1366 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1368 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1369 if (cBB->isSuccessor(PHIBB))
1370 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1374 SDB->BitTestCases.clear();
1376 // If the JumpTable record is filled in, then we need to emit a jump table.
1377 // Updating the PHI nodes is tricky in this case, since we need to determine
1378 // whether the PHI is a successor of the range check MBB or the jump table MBB
1379 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1380 // Lower header first, if it wasn't already lowered
1381 if (!SDB->JTCases[i].first.Emitted) {
1382 // Set the current basic block to the mbb we wish to insert the code into
1383 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1384 FuncInfo->InsertPt = FuncInfo->MBB->end();
1386 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1388 CurDAG->setRoot(SDB->getRoot());
1390 CodeGenAndEmitDAG();
1393 // Set the current basic block to the mbb we wish to insert the code into
1394 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1395 FuncInfo->InsertPt = FuncInfo->MBB->end();
1397 SDB->visitJumpTable(SDB->JTCases[i].second);
1398 CurDAG->setRoot(SDB->getRoot());
1400 CodeGenAndEmitDAG();
1403 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1405 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1406 MachineBasicBlock *PHIBB = PHI->getParent();
1407 assert(PHI->isPHI() &&
1408 "This is not a machine PHI node that we are updating!");
1409 // "default" BB. We can go there only from header BB.
1410 if (PHIBB == SDB->JTCases[i].second.Default)
1411 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1412 .addMBB(SDB->JTCases[i].first.HeaderBB);
1413 // JT BB. Just iterate over successors here
1414 if (FuncInfo->MBB->isSuccessor(PHIBB))
1415 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1418 SDB->JTCases.clear();
1420 // If the switch block involved a branch to one of the actual successors, we
1421 // need to update PHI nodes in that block.
1422 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1423 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1424 assert(PHI->isPHI() &&
1425 "This is not a machine PHI node that we are updating!");
1426 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1427 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1430 // If we generated any switch lowering information, build and codegen any
1431 // additional DAGs necessary.
1432 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1433 // Set the current basic block to the mbb we wish to insert the code into
1434 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1435 FuncInfo->InsertPt = FuncInfo->MBB->end();
1437 // Determine the unique successors.
1438 SmallVector<MachineBasicBlock *, 2> Succs;
1439 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1440 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1441 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1443 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1444 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1445 CurDAG->setRoot(SDB->getRoot());
1447 CodeGenAndEmitDAG();
1449 // Remember the last block, now that any splitting is done, for use in
1450 // populating PHI nodes in successors.
1451 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1453 // Handle any PHI nodes in successors of this chunk, as if we were coming
1454 // from the original BB before switch expansion. Note that PHI nodes can
1455 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1456 // handle them the right number of times.
1457 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1458 FuncInfo->MBB = Succs[i];
1459 FuncInfo->InsertPt = FuncInfo->MBB->end();
1460 // FuncInfo->MBB may have been removed from the CFG if a branch was
1462 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1463 for (MachineBasicBlock::iterator
1464 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1465 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1466 MachineInstrBuilder PHI(*MF, MBBI);
1467 // This value for this PHI node is recorded in PHINodesToUpdate.
1468 for (unsigned pn = 0; ; ++pn) {
1469 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1470 "Didn't find PHI entry!");
1471 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1472 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1480 SDB->SwitchCases.clear();
1484 /// Create the scheduler. If a specific scheduler was specified
1485 /// via the SchedulerRegistry, use it, otherwise select the
1486 /// one preferred by the target.
1488 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1489 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1493 RegisterScheduler::setDefault(Ctor);
1496 return Ctor(this, OptLevel);
1499 //===----------------------------------------------------------------------===//
1500 // Helper functions used by the generated instruction selector.
1501 //===----------------------------------------------------------------------===//
1502 // Calls to these methods are generated by tblgen.
1504 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1505 /// the dag combiner simplified the 255, we still want to match. RHS is the
1506 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1507 /// specified in the .td file (e.g. 255).
1508 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1509 int64_t DesiredMaskS) const {
1510 const APInt &ActualMask = RHS->getAPIntValue();
1511 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1513 // If the actual mask exactly matches, success!
1514 if (ActualMask == DesiredMask)
1517 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1518 if (ActualMask.intersects(~DesiredMask))
1521 // Otherwise, the DAG Combiner may have proven that the value coming in is
1522 // either already zero or is not demanded. Check for known zero input bits.
1523 APInt NeededMask = DesiredMask & ~ActualMask;
1524 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1527 // TODO: check to see if missing bits are just not demanded.
1529 // Otherwise, this pattern doesn't match.
1533 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1534 /// the dag combiner simplified the 255, we still want to match. RHS is the
1535 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1536 /// specified in the .td file (e.g. 255).
1537 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1538 int64_t DesiredMaskS) const {
1539 const APInt &ActualMask = RHS->getAPIntValue();
1540 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1542 // If the actual mask exactly matches, success!
1543 if (ActualMask == DesiredMask)
1546 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1547 if (ActualMask.intersects(~DesiredMask))
1550 // Otherwise, the DAG Combiner may have proven that the value coming in is
1551 // either already zero or is not demanded. Check for known zero input bits.
1552 APInt NeededMask = DesiredMask & ~ActualMask;
1554 APInt KnownZero, KnownOne;
1555 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1557 // If all the missing bits in the or are already known to be set, match!
1558 if ((NeededMask & KnownOne) == NeededMask)
1561 // TODO: check to see if missing bits are just not demanded.
1563 // Otherwise, this pattern doesn't match.
1568 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1569 /// by tblgen. Others should not call it.
1570 void SelectionDAGISel::
1571 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1572 std::vector<SDValue> InOps;
1573 std::swap(InOps, Ops);
1575 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1576 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1577 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1578 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1580 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1581 if (InOps[e-1].getValueType() == MVT::Glue)
1582 --e; // Don't process a glue operand if it is here.
1585 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1586 if (!InlineAsm::isMemKind(Flags)) {
1587 // Just skip over this operand, copying the operands verbatim.
1588 Ops.insert(Ops.end(), InOps.begin()+i,
1589 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1590 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1592 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1593 "Memory operand with multiple values?");
1594 // Otherwise, this is a memory operand. Ask the target to select it.
1595 std::vector<SDValue> SelOps;
1596 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1597 report_fatal_error("Could not match memory address. Inline asm"
1600 // Add this to the output node.
1602 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1603 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1604 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1609 // Add the glue input back if present.
1610 if (e != InOps.size())
1611 Ops.push_back(InOps.back());
1614 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1617 static SDNode *findGlueUse(SDNode *N) {
1618 unsigned FlagResNo = N->getNumValues()-1;
1619 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1620 SDUse &Use = I.getUse();
1621 if (Use.getResNo() == FlagResNo)
1622 return Use.getUser();
1627 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1628 /// This function recursively traverses up the operand chain, ignoring
1630 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1631 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1632 bool IgnoreChains) {
1633 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1634 // greater than all of its (recursive) operands. If we scan to a point where
1635 // 'use' is smaller than the node we're scanning for, then we know we will
1638 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1639 // happen because we scan down to newly selected nodes in the case of glue
1641 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1644 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1645 // won't fail if we scan it again.
1646 if (!Visited.insert(Use))
1649 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1650 // Ignore chain uses, they are validated by HandleMergeInputChains.
1651 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1654 SDNode *N = Use->getOperand(i).getNode();
1656 if (Use == ImmedUse || Use == Root)
1657 continue; // We are not looking for immediate use.
1662 // Traverse up the operand chain.
1663 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1669 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1670 /// operand node N of U during instruction selection that starts at Root.
1671 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1672 SDNode *Root) const {
1673 if (OptLevel == CodeGenOpt::None) return false;
1674 return N.hasOneUse();
1677 /// IsLegalToFold - Returns true if the specific operand node N of
1678 /// U can be folded during instruction selection that starts at Root.
1679 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1680 CodeGenOpt::Level OptLevel,
1681 bool IgnoreChains) {
1682 if (OptLevel == CodeGenOpt::None) return false;
1684 // If Root use can somehow reach N through a path that that doesn't contain
1685 // U then folding N would create a cycle. e.g. In the following
1686 // diagram, Root can reach N through X. If N is folded into into Root, then
1687 // X is both a predecessor and a successor of U.
1698 // * indicates nodes to be folded together.
1700 // If Root produces glue, then it gets (even more) interesting. Since it
1701 // will be "glued" together with its glue use in the scheduler, we need to
1702 // check if it might reach N.
1721 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1722 // (call it Fold), then X is a predecessor of GU and a successor of
1723 // Fold. But since Fold and GU are glued together, this will create
1724 // a cycle in the scheduling graph.
1726 // If the node has glue, walk down the graph to the "lowest" node in the
1728 EVT VT = Root->getValueType(Root->getNumValues()-1);
1729 while (VT == MVT::Glue) {
1730 SDNode *GU = findGlueUse(Root);
1734 VT = Root->getValueType(Root->getNumValues()-1);
1736 // If our query node has a glue result with a use, we've walked up it. If
1737 // the user (which has already been selected) has a chain or indirectly uses
1738 // the chain, our WalkChainUsers predicate will not consider it. Because of
1739 // this, we cannot ignore chains in this predicate.
1740 IgnoreChains = false;
1744 SmallPtrSet<SDNode*, 16> Visited;
1745 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1748 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1749 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1750 SelectInlineAsmMemoryOperands(Ops);
1752 EVT VTs[] = { MVT::Other, MVT::Glue };
1753 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
1754 VTs, &Ops[0], Ops.size());
1756 return New.getNode();
1759 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1760 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1763 /// GetVBR - decode a vbr encoding whose top bit is set.
1764 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1765 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1766 assert(Val >= 128 && "Not a VBR");
1767 Val &= 127; // Remove first vbr bit.
1772 NextBits = MatcherTable[Idx++];
1773 Val |= (NextBits&127) << Shift;
1775 } while (NextBits & 128);
1781 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1782 /// interior glue and chain results to use the new glue and chain results.
1783 void SelectionDAGISel::
1784 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1785 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1787 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1788 bool isMorphNodeTo) {
1789 SmallVector<SDNode*, 4> NowDeadNodes;
1791 // Now that all the normal results are replaced, we replace the chain and
1792 // glue results if present.
1793 if (!ChainNodesMatched.empty()) {
1794 assert(InputChain.getNode() != 0 &&
1795 "Matched input chains but didn't produce a chain");
1796 // Loop over all of the nodes we matched that produced a chain result.
1797 // Replace all the chain results with the final chain we ended up with.
1798 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1799 SDNode *ChainNode = ChainNodesMatched[i];
1801 // If this node was already deleted, don't look at it.
1802 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1805 // Don't replace the results of the root node if we're doing a
1807 if (ChainNode == NodeToMatch && isMorphNodeTo)
1810 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1811 if (ChainVal.getValueType() == MVT::Glue)
1812 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1813 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1814 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1816 // If the node became dead and we haven't already seen it, delete it.
1817 if (ChainNode->use_empty() &&
1818 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1819 NowDeadNodes.push_back(ChainNode);
1823 // If the result produces glue, update any glue results in the matched
1824 // pattern with the glue result.
1825 if (InputGlue.getNode() != 0) {
1826 // Handle any interior nodes explicitly marked.
1827 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1828 SDNode *FRN = GlueResultNodesMatched[i];
1830 // If this node was already deleted, don't look at it.
1831 if (FRN->getOpcode() == ISD::DELETED_NODE)
1834 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1835 "Doesn't have a glue result");
1836 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1839 // If the node became dead and we haven't already seen it, delete it.
1840 if (FRN->use_empty() &&
1841 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1842 NowDeadNodes.push_back(FRN);
1846 if (!NowDeadNodes.empty())
1847 CurDAG->RemoveDeadNodes(NowDeadNodes);
1849 DEBUG(dbgs() << "ISEL: Match complete!\n");
1855 CR_LeadsToInteriorNode
1858 /// WalkChainUsers - Walk down the users of the specified chained node that is
1859 /// part of the pattern we're matching, looking at all of the users we find.
1860 /// This determines whether something is an interior node, whether we have a
1861 /// non-pattern node in between two pattern nodes (which prevent folding because
1862 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1863 /// between pattern nodes (in which case the TF becomes part of the pattern).
1865 /// The walk we do here is guaranteed to be small because we quickly get down to
1866 /// already selected nodes "below" us.
1868 WalkChainUsers(const SDNode *ChainedNode,
1869 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1870 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1871 ChainResult Result = CR_Simple;
1873 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1874 E = ChainedNode->use_end(); UI != E; ++UI) {
1875 // Make sure the use is of the chain, not some other value we produce.
1876 if (UI.getUse().getValueType() != MVT::Other) continue;
1880 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1883 // If we see an already-selected machine node, then we've gone beyond the
1884 // pattern that we're selecting down into the already selected chunk of the
1886 unsigned UserOpcode = User->getOpcode();
1887 if (User->isMachineOpcode() ||
1888 UserOpcode == ISD::CopyToReg ||
1889 UserOpcode == ISD::CopyFromReg ||
1890 UserOpcode == ISD::INLINEASM ||
1891 UserOpcode == ISD::EH_LABEL ||
1892 UserOpcode == ISD::LIFETIME_START ||
1893 UserOpcode == ISD::LIFETIME_END) {
1894 // If their node ID got reset to -1 then they've already been selected.
1895 // Treat them like a MachineOpcode.
1896 if (User->getNodeId() == -1)
1900 // If we have a TokenFactor, we handle it specially.
1901 if (User->getOpcode() != ISD::TokenFactor) {
1902 // If the node isn't a token factor and isn't part of our pattern, then it
1903 // must be a random chained node in between two nodes we're selecting.
1904 // This happens when we have something like:
1909 // Because we structurally match the load/store as a read/modify/write,
1910 // but the call is chained between them. We cannot fold in this case
1911 // because it would induce a cycle in the graph.
1912 if (!std::count(ChainedNodesInPattern.begin(),
1913 ChainedNodesInPattern.end(), User))
1914 return CR_InducesCycle;
1916 // Otherwise we found a node that is part of our pattern. For example in:
1920 // This would happen when we're scanning down from the load and see the
1921 // store as a user. Record that there is a use of ChainedNode that is
1922 // part of the pattern and keep scanning uses.
1923 Result = CR_LeadsToInteriorNode;
1924 InteriorChainedNodes.push_back(User);
1928 // If we found a TokenFactor, there are two cases to consider: first if the
1929 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1930 // uses of the TF are in our pattern) we just want to ignore it. Second,
1931 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1937 // | \ DAG's like cheese
1940 // [TokenFactor] [Op]
1947 // In this case, the TokenFactor becomes part of our match and we rewrite it
1948 // as a new TokenFactor.
1950 // To distinguish these two cases, do a recursive walk down the uses.
1951 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1953 // If the uses of the TokenFactor are just already-selected nodes, ignore
1954 // it, it is "below" our pattern.
1956 case CR_InducesCycle:
1957 // If the uses of the TokenFactor lead to nodes that are not part of our
1958 // pattern that are not selected, folding would turn this into a cycle,
1960 return CR_InducesCycle;
1961 case CR_LeadsToInteriorNode:
1962 break; // Otherwise, keep processing.
1965 // Okay, we know we're in the interesting interior case. The TokenFactor
1966 // is now going to be considered part of the pattern so that we rewrite its
1967 // uses (it may have uses that are not part of the pattern) with the
1968 // ultimate chain result of the generated code. We will also add its chain
1969 // inputs as inputs to the ultimate TokenFactor we create.
1970 Result = CR_LeadsToInteriorNode;
1971 ChainedNodesInPattern.push_back(User);
1972 InteriorChainedNodes.push_back(User);
1979 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1980 /// operation for when the pattern matched at least one node with a chains. The
1981 /// input vector contains a list of all of the chained nodes that we match. We
1982 /// must determine if this is a valid thing to cover (i.e. matching it won't
1983 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1984 /// be used as the input node chain for the generated nodes.
1986 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1987 SelectionDAG *CurDAG) {
1988 // Walk all of the chained nodes we've matched, recursively scanning down the
1989 // users of the chain result. This adds any TokenFactor nodes that are caught
1990 // in between chained nodes to the chained and interior nodes list.
1991 SmallVector<SDNode*, 3> InteriorChainedNodes;
1992 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1993 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1994 InteriorChainedNodes) == CR_InducesCycle)
1995 return SDValue(); // Would induce a cycle.
1998 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1999 // that we are interested in. Form our input TokenFactor node.
2000 SmallVector<SDValue, 3> InputChains;
2001 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2002 // Add the input chain of this node to the InputChains list (which will be
2003 // the operands of the generated TokenFactor) if it's not an interior node.
2004 SDNode *N = ChainNodesMatched[i];
2005 if (N->getOpcode() != ISD::TokenFactor) {
2006 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2009 // Otherwise, add the input chain.
2010 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2011 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2012 InputChains.push_back(InChain);
2016 // If we have a token factor, we want to add all inputs of the token factor
2017 // that are not part of the pattern we're matching.
2018 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2019 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2020 N->getOperand(op).getNode()))
2021 InputChains.push_back(N->getOperand(op));
2026 if (InputChains.size() == 1)
2027 return InputChains[0];
2028 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2029 MVT::Other, &InputChains[0], InputChains.size());
2032 /// MorphNode - Handle morphing a node in place for the selector.
2033 SDNode *SelectionDAGISel::
2034 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2035 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
2036 // It is possible we're using MorphNodeTo to replace a node with no
2037 // normal results with one that has a normal result (or we could be
2038 // adding a chain) and the input could have glue and chains as well.
2039 // In this case we need to shift the operands down.
2040 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2041 // than the old isel though.
2042 int OldGlueResultNo = -1, OldChainResultNo = -1;
2044 unsigned NTMNumResults = Node->getNumValues();
2045 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2046 OldGlueResultNo = NTMNumResults-1;
2047 if (NTMNumResults != 1 &&
2048 Node->getValueType(NTMNumResults-2) == MVT::Other)
2049 OldChainResultNo = NTMNumResults-2;
2050 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2051 OldChainResultNo = NTMNumResults-1;
2053 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2054 // that this deletes operands of the old node that become dead.
2055 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
2057 // MorphNodeTo can operate in two ways: if an existing node with the
2058 // specified operands exists, it can just return it. Otherwise, it
2059 // updates the node in place to have the requested operands.
2061 // If we updated the node in place, reset the node ID. To the isel,
2062 // this should be just like a newly allocated machine node.
2066 unsigned ResNumResults = Res->getNumValues();
2067 // Move the glue if needed.
2068 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2069 (unsigned)OldGlueResultNo != ResNumResults-1)
2070 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2071 SDValue(Res, ResNumResults-1));
2073 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2076 // Move the chain reference if needed.
2077 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2078 (unsigned)OldChainResultNo != ResNumResults-1)
2079 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2080 SDValue(Res, ResNumResults-1));
2082 // Otherwise, no replacement happened because the node already exists. Replace
2083 // Uses of the old node with the new one.
2085 CurDAG->ReplaceAllUsesWith(Node, Res);
2090 /// CheckSame - Implements OP_CheckSame.
2091 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2092 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2094 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2095 // Accept if it is exactly the same as a previously recorded node.
2096 unsigned RecNo = MatcherTable[MatcherIndex++];
2097 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2098 return N == RecordedNodes[RecNo].first;
2101 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2102 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2103 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2104 const SelectionDAGISel &SDISel) {
2105 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2108 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2109 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2110 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2111 const SelectionDAGISel &SDISel, SDNode *N) {
2112 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2115 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2116 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2118 uint16_t Opc = MatcherTable[MatcherIndex++];
2119 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2120 return N->getOpcode() == Opc;
2123 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2124 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2125 SDValue N, const TargetLowering *TLI) {
2126 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2127 if (N.getValueType() == VT) return true;
2129 // Handle the case when VT is iPTR.
2130 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2133 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2134 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2135 SDValue N, const TargetLowering *TLI,
2137 if (ChildNo >= N.getNumOperands())
2138 return false; // Match fails if out of range child #.
2139 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2142 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2143 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2145 return cast<CondCodeSDNode>(N)->get() ==
2146 (ISD::CondCode)MatcherTable[MatcherIndex++];
2149 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2150 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2151 SDValue N, const TargetLowering *TLI) {
2152 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2153 if (cast<VTSDNode>(N)->getVT() == VT)
2156 // Handle the case when VT is iPTR.
2157 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2160 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2161 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2163 int64_t Val = MatcherTable[MatcherIndex++];
2165 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2167 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2168 return C != 0 && C->getSExtValue() == Val;
2171 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2172 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2173 SDValue N, const SelectionDAGISel &SDISel) {
2174 int64_t Val = MatcherTable[MatcherIndex++];
2176 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2178 if (N->getOpcode() != ISD::AND) return false;
2180 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2181 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2184 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2185 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2186 SDValue N, const SelectionDAGISel &SDISel) {
2187 int64_t Val = MatcherTable[MatcherIndex++];
2189 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2191 if (N->getOpcode() != ISD::OR) return false;
2193 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2194 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2197 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2198 /// scope, evaluate the current node. If the current predicate is known to
2199 /// fail, set Result=true and return anything. If the current predicate is
2200 /// known to pass, set Result=false and return the MatcherIndex to continue
2201 /// with. If the current predicate is unknown, set Result=false and return the
2202 /// MatcherIndex to continue with.
2203 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2204 unsigned Index, SDValue N,
2206 const SelectionDAGISel &SDISel,
2207 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2208 switch (Table[Index++]) {
2211 return Index-1; // Could not evaluate this predicate.
2212 case SelectionDAGISel::OPC_CheckSame:
2213 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2215 case SelectionDAGISel::OPC_CheckPatternPredicate:
2216 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2218 case SelectionDAGISel::OPC_CheckPredicate:
2219 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2221 case SelectionDAGISel::OPC_CheckOpcode:
2222 Result = !::CheckOpcode(Table, Index, N.getNode());
2224 case SelectionDAGISel::OPC_CheckType:
2225 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering());
2227 case SelectionDAGISel::OPC_CheckChild0Type:
2228 case SelectionDAGISel::OPC_CheckChild1Type:
2229 case SelectionDAGISel::OPC_CheckChild2Type:
2230 case SelectionDAGISel::OPC_CheckChild3Type:
2231 case SelectionDAGISel::OPC_CheckChild4Type:
2232 case SelectionDAGISel::OPC_CheckChild5Type:
2233 case SelectionDAGISel::OPC_CheckChild6Type:
2234 case SelectionDAGISel::OPC_CheckChild7Type:
2235 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(),
2236 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2238 case SelectionDAGISel::OPC_CheckCondCode:
2239 Result = !::CheckCondCode(Table, Index, N);
2241 case SelectionDAGISel::OPC_CheckValueType:
2242 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering());
2244 case SelectionDAGISel::OPC_CheckInteger:
2245 Result = !::CheckInteger(Table, Index, N);
2247 case SelectionDAGISel::OPC_CheckAndImm:
2248 Result = !::CheckAndImm(Table, Index, N, SDISel);
2250 case SelectionDAGISel::OPC_CheckOrImm:
2251 Result = !::CheckOrImm(Table, Index, N, SDISel);
2259 /// FailIndex - If this match fails, this is the index to continue with.
2262 /// NodeStack - The node stack when the scope was formed.
2263 SmallVector<SDValue, 4> NodeStack;
2265 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2266 unsigned NumRecordedNodes;
2268 /// NumMatchedMemRefs - The number of matched memref entries.
2269 unsigned NumMatchedMemRefs;
2271 /// InputChain/InputGlue - The current chain/glue
2272 SDValue InputChain, InputGlue;
2274 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2275 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2280 SDNode *SelectionDAGISel::
2281 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2282 unsigned TableSize) {
2283 // FIXME: Should these even be selected? Handle these cases in the caller?
2284 switch (NodeToMatch->getOpcode()) {
2287 case ISD::EntryToken: // These nodes remain the same.
2288 case ISD::BasicBlock:
2290 case ISD::RegisterMask:
2291 //case ISD::VALUETYPE:
2292 //case ISD::CONDCODE:
2293 case ISD::HANDLENODE:
2294 case ISD::MDNODE_SDNODE:
2295 case ISD::TargetConstant:
2296 case ISD::TargetConstantFP:
2297 case ISD::TargetConstantPool:
2298 case ISD::TargetFrameIndex:
2299 case ISD::TargetExternalSymbol:
2300 case ISD::TargetBlockAddress:
2301 case ISD::TargetJumpTable:
2302 case ISD::TargetGlobalTLSAddress:
2303 case ISD::TargetGlobalAddress:
2304 case ISD::TokenFactor:
2305 case ISD::CopyFromReg:
2306 case ISD::CopyToReg:
2308 case ISD::LIFETIME_START:
2309 case ISD::LIFETIME_END:
2310 NodeToMatch->setNodeId(-1); // Mark selected.
2312 case ISD::AssertSext:
2313 case ISD::AssertZext:
2314 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2315 NodeToMatch->getOperand(0));
2317 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2318 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2321 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2323 // Set up the node stack with NodeToMatch as the only node on the stack.
2324 SmallVector<SDValue, 8> NodeStack;
2325 SDValue N = SDValue(NodeToMatch, 0);
2326 NodeStack.push_back(N);
2328 // MatchScopes - Scopes used when matching, if a match failure happens, this
2329 // indicates where to continue checking.
2330 SmallVector<MatchScope, 8> MatchScopes;
2332 // RecordedNodes - This is the set of nodes that have been recorded by the
2333 // state machine. The second value is the parent of the node, or null if the
2334 // root is recorded.
2335 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2337 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2339 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2341 // These are the current input chain and glue for use when generating nodes.
2342 // Various Emit operations change these. For example, emitting a copytoreg
2343 // uses and updates these.
2344 SDValue InputChain, InputGlue;
2346 // ChainNodesMatched - If a pattern matches nodes that have input/output
2347 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2348 // which ones they are. The result is captured into this list so that we can
2349 // update the chain results when the pattern is complete.
2350 SmallVector<SDNode*, 3> ChainNodesMatched;
2351 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2353 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2354 NodeToMatch->dump(CurDAG);
2357 // Determine where to start the interpreter. Normally we start at opcode #0,
2358 // but if the state machine starts with an OPC_SwitchOpcode, then we
2359 // accelerate the first lookup (which is guaranteed to be hot) with the
2360 // OpcodeOffset table.
2361 unsigned MatcherIndex = 0;
2363 if (!OpcodeOffset.empty()) {
2364 // Already computed the OpcodeOffset table, just index into it.
2365 if (N.getOpcode() < OpcodeOffset.size())
2366 MatcherIndex = OpcodeOffset[N.getOpcode()];
2367 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2369 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2370 // Otherwise, the table isn't computed, but the state machine does start
2371 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2372 // is the first time we're selecting an instruction.
2375 // Get the size of this case.
2376 unsigned CaseSize = MatcherTable[Idx++];
2378 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2379 if (CaseSize == 0) break;
2381 // Get the opcode, add the index to the table.
2382 uint16_t Opc = MatcherTable[Idx++];
2383 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2384 if (Opc >= OpcodeOffset.size())
2385 OpcodeOffset.resize((Opc+1)*2);
2386 OpcodeOffset[Opc] = Idx;
2390 // Okay, do the lookup for the first opcode.
2391 if (N.getOpcode() < OpcodeOffset.size())
2392 MatcherIndex = OpcodeOffset[N.getOpcode()];
2396 assert(MatcherIndex < TableSize && "Invalid index");
2398 unsigned CurrentOpcodeIndex = MatcherIndex;
2400 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2403 // Okay, the semantics of this operation are that we should push a scope
2404 // then evaluate the first child. However, pushing a scope only to have
2405 // the first check fail (which then pops it) is inefficient. If we can
2406 // determine immediately that the first check (or first several) will
2407 // immediately fail, don't even bother pushing a scope for them.
2411 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2412 if (NumToSkip & 128)
2413 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2414 // Found the end of the scope with no match.
2415 if (NumToSkip == 0) {
2420 FailIndex = MatcherIndex+NumToSkip;
2422 unsigned MatcherIndexOfPredicate = MatcherIndex;
2423 (void)MatcherIndexOfPredicate; // silence warning.
2425 // If we can't evaluate this predicate without pushing a scope (e.g. if
2426 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2427 // push the scope and evaluate the full predicate chain.
2429 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2430 Result, *this, RecordedNodes);
2434 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2435 << "index " << MatcherIndexOfPredicate
2436 << ", continuing at " << FailIndex << "\n");
2437 ++NumDAGIselRetries;
2439 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2440 // move to the next case.
2441 MatcherIndex = FailIndex;
2444 // If the whole scope failed to match, bail.
2445 if (FailIndex == 0) break;
2447 // Push a MatchScope which indicates where to go if the first child fails
2449 MatchScope NewEntry;
2450 NewEntry.FailIndex = FailIndex;
2451 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2452 NewEntry.NumRecordedNodes = RecordedNodes.size();
2453 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2454 NewEntry.InputChain = InputChain;
2455 NewEntry.InputGlue = InputGlue;
2456 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2457 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2458 MatchScopes.push_back(NewEntry);
2461 case OPC_RecordNode: {
2462 // Remember this node, it may end up being an operand in the pattern.
2464 if (NodeStack.size() > 1)
2465 Parent = NodeStack[NodeStack.size()-2].getNode();
2466 RecordedNodes.push_back(std::make_pair(N, Parent));
2470 case OPC_RecordChild0: case OPC_RecordChild1:
2471 case OPC_RecordChild2: case OPC_RecordChild3:
2472 case OPC_RecordChild4: case OPC_RecordChild5:
2473 case OPC_RecordChild6: case OPC_RecordChild7: {
2474 unsigned ChildNo = Opcode-OPC_RecordChild0;
2475 if (ChildNo >= N.getNumOperands())
2476 break; // Match fails if out of range child #.
2478 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2482 case OPC_RecordMemRef:
2483 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2486 case OPC_CaptureGlueInput:
2487 // If the current node has an input glue, capture it in InputGlue.
2488 if (N->getNumOperands() != 0 &&
2489 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2490 InputGlue = N->getOperand(N->getNumOperands()-1);
2493 case OPC_MoveChild: {
2494 unsigned ChildNo = MatcherTable[MatcherIndex++];
2495 if (ChildNo >= N.getNumOperands())
2496 break; // Match fails if out of range child #.
2497 N = N.getOperand(ChildNo);
2498 NodeStack.push_back(N);
2502 case OPC_MoveParent:
2503 // Pop the current node off the NodeStack.
2504 NodeStack.pop_back();
2505 assert(!NodeStack.empty() && "Node stack imbalance!");
2506 N = NodeStack.back();
2510 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2512 case OPC_CheckPatternPredicate:
2513 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2515 case OPC_CheckPredicate:
2516 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2520 case OPC_CheckComplexPat: {
2521 unsigned CPNum = MatcherTable[MatcherIndex++];
2522 unsigned RecNo = MatcherTable[MatcherIndex++];
2523 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2524 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2525 RecordedNodes[RecNo].first, CPNum,
2530 case OPC_CheckOpcode:
2531 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2535 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2539 case OPC_SwitchOpcode: {
2540 unsigned CurNodeOpcode = N.getOpcode();
2541 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2544 // Get the size of this case.
2545 CaseSize = MatcherTable[MatcherIndex++];
2547 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2548 if (CaseSize == 0) break;
2550 uint16_t Opc = MatcherTable[MatcherIndex++];
2551 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2553 // If the opcode matches, then we will execute this case.
2554 if (CurNodeOpcode == Opc)
2557 // Otherwise, skip over this case.
2558 MatcherIndex += CaseSize;
2561 // If no cases matched, bail out.
2562 if (CaseSize == 0) break;
2564 // Otherwise, execute the case we found.
2565 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2566 << " to " << MatcherIndex << "\n");
2570 case OPC_SwitchType: {
2571 MVT CurNodeVT = N.getSimpleValueType();
2572 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2575 // Get the size of this case.
2576 CaseSize = MatcherTable[MatcherIndex++];
2578 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2579 if (CaseSize == 0) break;
2581 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2582 if (CaseVT == MVT::iPTR)
2583 CaseVT = getTargetLowering()->getPointerTy();
2585 // If the VT matches, then we will execute this case.
2586 if (CurNodeVT == CaseVT)
2589 // Otherwise, skip over this case.
2590 MatcherIndex += CaseSize;
2593 // If no cases matched, bail out.
2594 if (CaseSize == 0) break;
2596 // Otherwise, execute the case we found.
2597 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2598 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2601 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2602 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2603 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2604 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2605 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(),
2606 Opcode-OPC_CheckChild0Type))
2609 case OPC_CheckCondCode:
2610 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2612 case OPC_CheckValueType:
2613 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2616 case OPC_CheckInteger:
2617 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2619 case OPC_CheckAndImm:
2620 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2622 case OPC_CheckOrImm:
2623 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2626 case OPC_CheckFoldableChainNode: {
2627 assert(NodeStack.size() != 1 && "No parent node");
2628 // Verify that all intermediate nodes between the root and this one have
2630 bool HasMultipleUses = false;
2631 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2632 if (!NodeStack[i].hasOneUse()) {
2633 HasMultipleUses = true;
2636 if (HasMultipleUses) break;
2638 // Check to see that the target thinks this is profitable to fold and that
2639 // we can fold it without inducing cycles in the graph.
2640 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2642 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2643 NodeToMatch, OptLevel,
2644 true/*We validate our own chains*/))
2649 case OPC_EmitInteger: {
2650 MVT::SimpleValueType VT =
2651 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2652 int64_t Val = MatcherTable[MatcherIndex++];
2654 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2655 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2656 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2659 case OPC_EmitRegister: {
2660 MVT::SimpleValueType VT =
2661 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2662 unsigned RegNo = MatcherTable[MatcherIndex++];
2663 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2664 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2667 case OPC_EmitRegister2: {
2668 // For targets w/ more than 256 register names, the register enum
2669 // values are stored in two bytes in the matcher table (just like
2671 MVT::SimpleValueType VT =
2672 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2673 unsigned RegNo = MatcherTable[MatcherIndex++];
2674 RegNo |= MatcherTable[MatcherIndex++] << 8;
2675 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2676 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2680 case OPC_EmitConvertToTarget: {
2681 // Convert from IMM/FPIMM to target version.
2682 unsigned RecNo = MatcherTable[MatcherIndex++];
2683 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2684 SDValue Imm = RecordedNodes[RecNo].first;
2686 if (Imm->getOpcode() == ISD::Constant) {
2687 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2688 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2689 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2690 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2691 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2694 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2698 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2699 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2700 // These are space-optimized forms of OPC_EmitMergeInputChains.
2701 assert(InputChain.getNode() == 0 &&
2702 "EmitMergeInputChains should be the first chain producing node");
2703 assert(ChainNodesMatched.empty() &&
2704 "Should only have one EmitMergeInputChains per match");
2706 // Read all of the chained nodes.
2707 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2708 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2709 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2711 // FIXME: What if other value results of the node have uses not matched
2713 if (ChainNodesMatched.back() != NodeToMatch &&
2714 !RecordedNodes[RecNo].first.hasOneUse()) {
2715 ChainNodesMatched.clear();
2719 // Merge the input chains if they are not intra-pattern references.
2720 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2722 if (InputChain.getNode() == 0)
2723 break; // Failed to merge.
2727 case OPC_EmitMergeInputChains: {
2728 assert(InputChain.getNode() == 0 &&
2729 "EmitMergeInputChains should be the first chain producing node");
2730 // This node gets a list of nodes we matched in the input that have
2731 // chains. We want to token factor all of the input chains to these nodes
2732 // together. However, if any of the input chains is actually one of the
2733 // nodes matched in this pattern, then we have an intra-match reference.
2734 // Ignore these because the newly token factored chain should not refer to
2736 unsigned NumChains = MatcherTable[MatcherIndex++];
2737 assert(NumChains != 0 && "Can't TF zero chains");
2739 assert(ChainNodesMatched.empty() &&
2740 "Should only have one EmitMergeInputChains per match");
2742 // Read all of the chained nodes.
2743 for (unsigned i = 0; i != NumChains; ++i) {
2744 unsigned RecNo = MatcherTable[MatcherIndex++];
2745 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2746 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2748 // FIXME: What if other value results of the node have uses not matched
2750 if (ChainNodesMatched.back() != NodeToMatch &&
2751 !RecordedNodes[RecNo].first.hasOneUse()) {
2752 ChainNodesMatched.clear();
2757 // If the inner loop broke out, the match fails.
2758 if (ChainNodesMatched.empty())
2761 // Merge the input chains if they are not intra-pattern references.
2762 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2764 if (InputChain.getNode() == 0)
2765 break; // Failed to merge.
2770 case OPC_EmitCopyToReg: {
2771 unsigned RecNo = MatcherTable[MatcherIndex++];
2772 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2773 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2775 if (InputChain.getNode() == 0)
2776 InputChain = CurDAG->getEntryNode();
2778 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
2779 DestPhysReg, RecordedNodes[RecNo].first,
2782 InputGlue = InputChain.getValue(1);
2786 case OPC_EmitNodeXForm: {
2787 unsigned XFormNo = MatcherTable[MatcherIndex++];
2788 unsigned RecNo = MatcherTable[MatcherIndex++];
2789 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2790 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2791 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2796 case OPC_MorphNodeTo: {
2797 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2798 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2799 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2800 // Get the result VT list.
2801 unsigned NumVTs = MatcherTable[MatcherIndex++];
2802 SmallVector<EVT, 4> VTs;
2803 for (unsigned i = 0; i != NumVTs; ++i) {
2804 MVT::SimpleValueType VT =
2805 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2806 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy;
2810 if (EmitNodeInfo & OPFL_Chain)
2811 VTs.push_back(MVT::Other);
2812 if (EmitNodeInfo & OPFL_GlueOutput)
2813 VTs.push_back(MVT::Glue);
2815 // This is hot code, so optimize the two most common cases of 1 and 2
2818 if (VTs.size() == 1)
2819 VTList = CurDAG->getVTList(VTs[0]);
2820 else if (VTs.size() == 2)
2821 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2823 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2825 // Get the operand list.
2826 unsigned NumOps = MatcherTable[MatcherIndex++];
2827 SmallVector<SDValue, 8> Ops;
2828 for (unsigned i = 0; i != NumOps; ++i) {
2829 unsigned RecNo = MatcherTable[MatcherIndex++];
2831 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2833 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2834 Ops.push_back(RecordedNodes[RecNo].first);
2837 // If there are variadic operands to add, handle them now.
2838 if (EmitNodeInfo & OPFL_VariadicInfo) {
2839 // Determine the start index to copy from.
2840 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2841 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2842 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2843 "Invalid variadic node");
2844 // Copy all of the variadic operands, not including a potential glue
2846 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2848 SDValue V = NodeToMatch->getOperand(i);
2849 if (V.getValueType() == MVT::Glue) break;
2854 // If this has chain/glue inputs, add them.
2855 if (EmitNodeInfo & OPFL_Chain)
2856 Ops.push_back(InputChain);
2857 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2858 Ops.push_back(InputGlue);
2862 if (Opcode != OPC_MorphNodeTo) {
2863 // If this is a normal EmitNode command, just create the new node and
2864 // add the results to the RecordedNodes list.
2865 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
2868 // Add all the non-glue/non-chain results to the RecordedNodes list.
2869 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2870 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2871 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2875 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2876 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2879 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2880 // We will visit the equivalent node later.
2881 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2885 // If the node had chain/glue results, update our notion of the current
2887 if (EmitNodeInfo & OPFL_GlueOutput) {
2888 InputGlue = SDValue(Res, VTs.size()-1);
2889 if (EmitNodeInfo & OPFL_Chain)
2890 InputChain = SDValue(Res, VTs.size()-2);
2891 } else if (EmitNodeInfo & OPFL_Chain)
2892 InputChain = SDValue(Res, VTs.size()-1);
2894 // If the OPFL_MemRefs glue is set on this node, slap all of the
2895 // accumulated memrefs onto it.
2897 // FIXME: This is vastly incorrect for patterns with multiple outputs
2898 // instructions that access memory and for ComplexPatterns that match
2900 if (EmitNodeInfo & OPFL_MemRefs) {
2901 // Only attach load or store memory operands if the generated
2902 // instruction may load or store.
2903 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2904 bool mayLoad = MCID.mayLoad();
2905 bool mayStore = MCID.mayStore();
2907 unsigned NumMemRefs = 0;
2908 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
2909 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2910 if ((*I)->isLoad()) {
2913 } else if ((*I)->isStore()) {
2921 MachineSDNode::mmo_iterator MemRefs =
2922 MF->allocateMemRefsArray(NumMemRefs);
2924 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2925 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
2926 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2927 if ((*I)->isLoad()) {
2930 } else if ((*I)->isStore()) {
2938 cast<MachineSDNode>(Res)
2939 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2943 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2944 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
2946 // If this was a MorphNodeTo then we're completely done!
2947 if (Opcode == OPC_MorphNodeTo) {
2948 // Update chain and glue uses.
2949 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2950 InputGlue, GlueResultNodesMatched, true);
2957 case OPC_MarkGlueResults: {
2958 unsigned NumNodes = MatcherTable[MatcherIndex++];
2960 // Read and remember all the glue-result nodes.
2961 for (unsigned i = 0; i != NumNodes; ++i) {
2962 unsigned RecNo = MatcherTable[MatcherIndex++];
2964 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2966 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2967 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2972 case OPC_CompleteMatch: {
2973 // The match has been completed, and any new nodes (if any) have been
2974 // created. Patch up references to the matched dag to use the newly
2976 unsigned NumResults = MatcherTable[MatcherIndex++];
2978 for (unsigned i = 0; i != NumResults; ++i) {
2979 unsigned ResSlot = MatcherTable[MatcherIndex++];
2981 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2983 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2984 SDValue Res = RecordedNodes[ResSlot].first;
2986 assert(i < NodeToMatch->getNumValues() &&
2987 NodeToMatch->getValueType(i) != MVT::Other &&
2988 NodeToMatch->getValueType(i) != MVT::Glue &&
2989 "Invalid number of results to complete!");
2990 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2991 NodeToMatch->getValueType(i) == MVT::iPTR ||
2992 Res.getValueType() == MVT::iPTR ||
2993 NodeToMatch->getValueType(i).getSizeInBits() ==
2994 Res.getValueType().getSizeInBits()) &&
2995 "invalid replacement");
2996 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2999 // If the root node defines glue, add it to the glue nodes to update list.
3000 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3001 GlueResultNodesMatched.push_back(NodeToMatch);
3003 // Update chain and glue uses.
3004 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3005 InputGlue, GlueResultNodesMatched, false);
3007 assert(NodeToMatch->use_empty() &&
3008 "Didn't replace all uses of the node?");
3010 // FIXME: We just return here, which interacts correctly with SelectRoot
3011 // above. We should fix this to not return an SDNode* anymore.
3016 // If the code reached this point, then the match failed. See if there is
3017 // another child to try in the current 'Scope', otherwise pop it until we
3018 // find a case to check.
3019 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3020 ++NumDAGIselRetries;
3022 if (MatchScopes.empty()) {
3023 CannotYetSelect(NodeToMatch);
3027 // Restore the interpreter state back to the point where the scope was
3029 MatchScope &LastScope = MatchScopes.back();
3030 RecordedNodes.resize(LastScope.NumRecordedNodes);
3032 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3033 N = NodeStack.back();
3035 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3036 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3037 MatcherIndex = LastScope.FailIndex;
3039 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3041 InputChain = LastScope.InputChain;
3042 InputGlue = LastScope.InputGlue;
3043 if (!LastScope.HasChainNodesMatched)
3044 ChainNodesMatched.clear();
3045 if (!LastScope.HasGlueResultNodesMatched)
3046 GlueResultNodesMatched.clear();
3048 // Check to see what the offset is at the new MatcherIndex. If it is zero
3049 // we have reached the end of this scope, otherwise we have another child
3050 // in the current scope to try.
3051 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3052 if (NumToSkip & 128)
3053 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3055 // If we have another child in this scope to match, update FailIndex and
3057 if (NumToSkip != 0) {
3058 LastScope.FailIndex = MatcherIndex+NumToSkip;
3062 // End of this scope, pop it and try the next child in the containing
3064 MatchScopes.pop_back();
3071 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3073 raw_string_ostream Msg(msg);
3074 Msg << "Cannot select: ";
3076 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3077 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3078 N->getOpcode() != ISD::INTRINSIC_VOID) {
3079 N->printrFull(Msg, CurDAG);
3080 Msg << "\nIn function: " << MF->getName();
3082 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3084 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3085 if (iid < Intrinsic::num_intrinsics)
3086 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3087 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3088 Msg << "target intrinsic %" << TII->getName(iid);
3090 Msg << "unknown intrinsic #" << iid;
3092 report_fatal_error(Msg.str());
3095 char SelectionDAGISel::ID = 0;