1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/DebugInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetIntrinsicInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLowering.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/ADT/PostOrderIterator.h"
54 #include "llvm/ADT/Statistic.h"
58 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
59 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
60 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
61 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
62 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
65 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
66 cl::desc("Enable verbose messages in the \"fast\" "
67 "instruction selector"));
69 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
70 cl::desc("Enable abort calls when \"fast\" instruction fails"));
74 cl::desc("use Machine Branch Probability Info"),
75 cl::init(true), cl::Hidden);
79 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
80 cl::desc("Pop up a window to show dags before the first "
83 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize types"));
86 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before legalize"));
89 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
90 cl::desc("Pop up a window to show dags before the second "
93 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
94 cl::desc("Pop up a window to show dags before the post legalize types"
95 " dag combine pass"));
97 ViewISelDAGs("view-isel-dags", cl::Hidden,
98 cl::desc("Pop up a window to show isel dags as they are selected"));
100 ViewSchedDAGs("view-sched-dags", cl::Hidden,
101 cl::desc("Pop up a window to show sched dags as they are processed"));
103 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
104 cl::desc("Pop up a window to show SUnit dags after they are processed"));
106 static const bool ViewDAGCombine1 = false,
107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
108 ViewDAGCombine2 = false,
109 ViewDAGCombineLT = false,
110 ViewISelDAGs = false, ViewSchedDAGs = false,
111 ViewSUnitDAGs = false;
114 //===---------------------------------------------------------------------===//
116 /// RegisterScheduler class - Track the registration of instruction schedulers.
118 //===---------------------------------------------------------------------===//
119 MachinePassRegistry RegisterScheduler::Registry;
121 //===---------------------------------------------------------------------===//
123 /// ISHeuristic command line option for instruction schedulers.
125 //===---------------------------------------------------------------------===//
126 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
127 RegisterPassParser<RegisterScheduler> >
128 ISHeuristic("pre-RA-sched",
129 cl::init(&createDefaultScheduler),
130 cl::desc("Instruction schedulers available (before register"
133 static RegisterScheduler
134 defaultListDAGScheduler("default", "Best scheduler for the target",
135 createDefaultScheduler);
138 //===--------------------------------------------------------------------===//
139 /// createDefaultScheduler - This creates an instruction scheduler appropriate
141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
142 CodeGenOpt::Level OptLevel) {
143 const TargetLowering &TLI = IS->getTargetLowering();
145 if (OptLevel == CodeGenOpt::None)
146 return createSourceListDAGScheduler(IS, OptLevel);
147 if (TLI.getSchedulingPreference() == Sched::Latency)
148 return createTDListDAGScheduler(IS, OptLevel);
149 if (TLI.getSchedulingPreference() == Sched::RegPressure)
150 return createBURRListDAGScheduler(IS, OptLevel);
151 if (TLI.getSchedulingPreference() == Sched::Hybrid)
152 return createHybridListDAGScheduler(IS, OptLevel);
153 assert(TLI.getSchedulingPreference() == Sched::ILP &&
154 "Unknown sched type!");
155 return createILPListDAGScheduler(IS, OptLevel);
159 // EmitInstrWithCustomInserter - This method should be implemented by targets
160 // that mark instructions with the 'usesCustomInserter' flag. These
161 // instructions are special in various ways, which require special support to
162 // insert. The specified MachineInstr is created but not inserted into any
163 // basic blocks, and this method is called to expand it into a sequence of
164 // instructions, potentially also creating new basic blocks and control flow.
165 // When new basic blocks are inserted and the edges from MBB to its successors
166 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
169 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
170 MachineBasicBlock *MBB) const {
172 dbgs() << "If a target marks an instruction with "
173 "'usesCustomInserter', it must implement "
174 "TargetLowering::EmitInstrWithCustomInserter!";
180 //===----------------------------------------------------------------------===//
181 // SelectionDAGISel code
182 //===----------------------------------------------------------------------===//
184 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
185 CodeGenOpt::Level OL) :
186 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
187 FuncInfo(new FunctionLoweringInfo(TLI)),
188 CurDAG(new SelectionDAG(tm)),
189 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
193 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
194 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
195 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
198 SelectionDAGISel::~SelectionDAGISel() {
204 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
205 AU.addRequired<AliasAnalysis>();
206 AU.addPreserved<AliasAnalysis>();
207 AU.addRequired<GCModuleInfo>();
208 AU.addPreserved<GCModuleInfo>();
209 if (UseMBPI && OptLevel != CodeGenOpt::None)
210 AU.addRequired<BranchProbabilityInfo>();
211 MachineFunctionPass::getAnalysisUsage(AU);
214 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
215 /// may trap on it. In this case we have to split the edge so that the path
216 /// through the predecessor block that doesn't go to the phi block doesn't
217 /// execute the possibly trapping instruction.
219 /// This is required for correctness, so it must be done at -O0.
221 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
222 // Loop for blocks with phi nodes.
223 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
224 PHINode *PN = dyn_cast<PHINode>(BB->begin());
225 if (PN == 0) continue;
228 // For each block with a PHI node, check to see if any of the input values
229 // are potentially trapping constant expressions. Constant expressions are
230 // the only potentially trapping value that can occur as the argument to a
232 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
233 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
234 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
235 if (CE == 0 || !CE->canTrap()) continue;
237 // The only case we have to worry about is when the edge is critical.
238 // Since this block has a PHI Node, we assume it has multiple input
239 // edges: check to see if the pred has multiple successors.
240 BasicBlock *Pred = PN->getIncomingBlock(i);
241 if (Pred->getTerminator()->getNumSuccessors() == 1)
244 // Okay, we have to split this edge.
245 SplitCriticalEdge(Pred->getTerminator(),
246 GetSuccessorNumber(Pred, BB), SDISel, true);
252 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
253 // Do some sanity-checking on the command-line options.
254 assert((!EnableFastISelVerbose || EnableFastISel) &&
255 "-fast-isel-verbose requires -fast-isel");
256 assert((!EnableFastISelAbort || EnableFastISel) &&
257 "-fast-isel-abort requires -fast-isel");
259 const Function &Fn = *mf.getFunction();
260 const TargetInstrInfo &TII = *TM.getInstrInfo();
261 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
264 RegInfo = &MF->getRegInfo();
265 AA = &getAnalysis<AliasAnalysis>();
266 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
268 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
270 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
273 FuncInfo->set(Fn, *MF);
275 if (UseMBPI && OptLevel != CodeGenOpt::None)
276 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
282 SelectAllBasicBlocks(Fn);
284 // If the first basic block in the function has live ins that need to be
285 // copied into vregs, emit the copies into the top of the block before
286 // emitting the code for the block.
287 MachineBasicBlock *EntryMBB = MF->begin();
288 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
290 DenseMap<unsigned, unsigned> LiveInMap;
291 if (!FuncInfo->ArgDbgValues.empty())
292 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
293 E = RegInfo->livein_end(); LI != E; ++LI)
295 LiveInMap.insert(std::make_pair(LI->first, LI->second));
297 // Insert DBG_VALUE instructions for function arguments to the entry block.
298 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
299 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
300 unsigned Reg = MI->getOperand(0).getReg();
301 if (TargetRegisterInfo::isPhysicalRegister(Reg))
302 EntryMBB->insert(EntryMBB->begin(), MI);
304 MachineInstr *Def = RegInfo->getVRegDef(Reg);
305 MachineBasicBlock::iterator InsertPos = Def;
306 // FIXME: VR def may not be in entry block.
307 Def->getParent()->insert(llvm::next(InsertPos), MI);
310 // If Reg is live-in then update debug info to track its copy in a vreg.
311 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
312 if (LDI != LiveInMap.end()) {
313 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
314 MachineBasicBlock::iterator InsertPos = Def;
315 const MDNode *Variable =
316 MI->getOperand(MI->getNumOperands()-1).getMetadata();
317 unsigned Offset = MI->getOperand(1).getImm();
318 // Def is never a terminator here, so it is ok to increment InsertPos.
319 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
320 TII.get(TargetOpcode::DBG_VALUE))
321 .addReg(LDI->second, RegState::Debug)
322 .addImm(Offset).addMetadata(Variable);
324 // If this vreg is directly copied into an exported register then
325 // that COPY instructions also need DBG_VALUE, if it is the only
326 // user of LDI->second.
327 MachineInstr *CopyUseMI = NULL;
328 for (MachineRegisterInfo::use_iterator
329 UI = RegInfo->use_begin(LDI->second);
330 MachineInstr *UseMI = UI.skipInstruction();) {
331 if (UseMI->isDebugValue()) continue;
332 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
333 CopyUseMI = UseMI; continue;
335 // Otherwise this is another use or second copy use.
336 CopyUseMI = NULL; break;
339 MachineInstr *NewMI =
340 BuildMI(*MF, CopyUseMI->getDebugLoc(),
341 TII.get(TargetOpcode::DBG_VALUE))
342 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
343 .addImm(Offset).addMetadata(Variable);
344 EntryMBB->insertAfter(CopyUseMI, NewMI);
349 // Determine if there are any calls in this machine function.
350 MachineFrameInfo *MFI = MF->getFrameInfo();
351 if (!MFI->hasCalls()) {
352 for (MachineFunction::const_iterator
353 I = MF->begin(), E = MF->end(); I != E; ++I) {
354 const MachineBasicBlock *MBB = I;
355 for (MachineBasicBlock::const_iterator
356 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
357 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
359 if ((MCID.isCall() && !MCID.isReturn()) ||
360 II->isStackAligningInlineAsm()) {
361 MFI->setHasCalls(true);
369 // Determine if there is a call to setjmp in the machine function.
370 MF->setCallsSetJmp(Fn.callsFunctionThatReturnsTwice());
372 // Replace forward-declared registers with the registers containing
373 // the desired value.
374 MachineRegisterInfo &MRI = MF->getRegInfo();
375 for (DenseMap<unsigned, unsigned>::iterator
376 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
378 unsigned From = I->first;
379 unsigned To = I->second;
380 // If To is also scheduled to be replaced, find what its ultimate
383 DenseMap<unsigned, unsigned>::iterator J =
384 FuncInfo->RegFixups.find(To);
389 MRI.replaceRegWith(From, To);
392 // Release function-specific state. SDB and CurDAG are already cleared
399 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
400 BasicBlock::const_iterator End,
402 // Lower all of the non-terminator instructions. If a call is emitted
403 // as a tail call, cease emitting nodes for this block. Terminators
404 // are handled below.
405 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
408 // Make sure the root of the DAG is up-to-date.
409 CurDAG->setRoot(SDB->getControlRoot());
410 HadTailCall = SDB->HasTailCall;
413 // Final step, emit the lowered DAG as machine code.
417 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
418 SmallPtrSet<SDNode*, 128> VisitedNodes;
419 SmallVector<SDNode*, 128> Worklist;
421 Worklist.push_back(CurDAG->getRoot().getNode());
428 SDNode *N = Worklist.pop_back_val();
430 // If we've already seen this node, ignore it.
431 if (!VisitedNodes.insert(N))
434 // Otherwise, add all chain operands to the worklist.
435 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
436 if (N->getOperand(i).getValueType() == MVT::Other)
437 Worklist.push_back(N->getOperand(i).getNode());
439 // If this is a CopyToReg with a vreg dest, process it.
440 if (N->getOpcode() != ISD::CopyToReg)
443 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
444 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
447 // Ignore non-scalar or non-integer values.
448 SDValue Src = N->getOperand(2);
449 EVT SrcVT = Src.getValueType();
450 if (!SrcVT.isInteger() || SrcVT.isVector())
453 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
454 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
455 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
456 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
457 } while (!Worklist.empty());
460 void SelectionDAGISel::CodeGenAndEmitDAG() {
461 std::string GroupName;
462 if (TimePassesIsEnabled)
463 GroupName = "Instruction Selection and Scheduling";
464 std::string BlockName;
465 int BlockNumber = -1;
467 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
468 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
472 BlockNumber = FuncInfo->MBB->getNumber();
473 BlockName = MF->getFunction()->getNameStr() + ":" +
474 FuncInfo->MBB->getBasicBlock()->getNameStr();
476 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
477 << " '" << BlockName << "'\n"; CurDAG->dump());
479 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
481 // Run the DAG combiner in pre-legalize mode.
483 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
484 CurDAG->Combine(Unrestricted, *AA, OptLevel);
487 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
488 << " '" << BlockName << "'\n"; CurDAG->dump());
490 // Second step, hack on the DAG until it only uses operations and types that
491 // the target supports.
492 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
497 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
498 Changed = CurDAG->LegalizeTypes();
501 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
502 << " '" << BlockName << "'\n"; CurDAG->dump());
505 if (ViewDAGCombineLT)
506 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
508 // Run the DAG combiner in post-type-legalize mode.
510 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
511 TimePassesIsEnabled);
512 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
515 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
516 << " '" << BlockName << "'\n"; CurDAG->dump());
520 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
521 Changed = CurDAG->LegalizeVectors();
526 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
527 CurDAG->LegalizeTypes();
530 if (ViewDAGCombineLT)
531 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
533 // Run the DAG combiner in post-type-legalize mode.
535 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
536 TimePassesIsEnabled);
537 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
540 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
541 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
544 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
547 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
551 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
552 << " '" << BlockName << "'\n"; CurDAG->dump());
554 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
556 // Run the DAG combiner in post-legalize mode.
558 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
559 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
562 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
563 << " '" << BlockName << "'\n"; CurDAG->dump());
565 if (OptLevel != CodeGenOpt::None)
566 ComputeLiveOutVRegInfo();
568 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
570 // Third, instruction select all of the operations to machine code, adding the
571 // code to the MachineBasicBlock.
573 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
574 DoInstructionSelection();
577 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
578 << " '" << BlockName << "'\n"; CurDAG->dump());
580 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
582 // Schedule machine code.
583 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
585 NamedRegionTimer T("Instruction Scheduling", GroupName,
586 TimePassesIsEnabled);
587 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
590 if (ViewSUnitDAGs) Scheduler->viewGraph();
592 // Emit machine code to BB. This can change 'BB' to the last block being
594 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
596 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
598 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
599 FuncInfo->InsertPt = Scheduler->InsertPos;
602 // If the block was split, make sure we update any references that are used to
603 // update PHI nodes later on.
604 if (FirstMBB != LastMBB)
605 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
607 // Free the scheduler state.
609 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
610 TimePassesIsEnabled);
614 // Free the SelectionDAG state, now that we're finished with it.
618 void SelectionDAGISel::DoInstructionSelection() {
619 DEBUG(errs() << "===== Instruction selection begins: BB#"
620 << FuncInfo->MBB->getNumber()
621 << " '" << FuncInfo->MBB->getName() << "'\n");
625 // Select target instructions for the DAG.
627 // Number all nodes with a topological order and set DAGSize.
628 DAGSize = CurDAG->AssignTopologicalOrder();
630 // Create a dummy node (which is not added to allnodes), that adds
631 // a reference to the root node, preventing it from being deleted,
632 // and tracking any changes of the root.
633 HandleSDNode Dummy(CurDAG->getRoot());
634 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
637 // The AllNodes list is now topological-sorted. Visit the
638 // nodes by starting at the end of the list (the root of the
639 // graph) and preceding back toward the beginning (the entry
641 while (ISelPosition != CurDAG->allnodes_begin()) {
642 SDNode *Node = --ISelPosition;
643 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
644 // but there are currently some corner cases that it misses. Also, this
645 // makes it theoretically possible to disable the DAGCombiner.
646 if (Node->use_empty())
649 SDNode *ResNode = Select(Node);
651 // FIXME: This is pretty gross. 'Select' should be changed to not return
652 // anything at all and this code should be nuked with a tactical strike.
654 // If node should not be replaced, continue with the next one.
655 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
659 ReplaceUses(Node, ResNode);
661 // If after the replacement this node is not used any more,
662 // remove this dead node.
663 if (Node->use_empty()) { // Don't delete EntryToken, etc.
664 ISelUpdater ISU(ISelPosition);
665 CurDAG->RemoveDeadNode(Node, &ISU);
669 CurDAG->setRoot(Dummy.getValue());
672 DEBUG(errs() << "===== Instruction selection ends:\n");
674 PostprocessISelDAG();
677 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
678 /// do other setup for EH landing-pad blocks.
679 void SelectionDAGISel::PrepareEHLandingPad() {
680 // Add a label to mark the beginning of the landing pad. Deletion of the
681 // landing pad can thus be detected via the MachineModuleInfo.
682 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
684 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
685 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
688 // Mark exception register as live in.
689 unsigned Reg = TLI.getExceptionAddressRegister();
690 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
692 // Mark exception selector register as live in.
693 Reg = TLI.getExceptionSelectorRegister();
694 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
696 // FIXME: Hack around an exception handling flaw (PR1508): the personality
697 // function and list of typeids logically belong to the invoke (or, if you
698 // like, the basic block containing the invoke), and need to be associated
699 // with it in the dwarf exception handling tables. Currently however the
700 // information is provided by an intrinsic (eh.selector) that can be moved
701 // to unexpected places by the optimizers: if the unwind edge is critical,
702 // then breaking it can result in the intrinsics being in the successor of
703 // the landing pad, not the landing pad itself. This results
704 // in exceptions not being caught because no typeids are associated with
705 // the invoke. This may not be the only way things can go wrong, but it
706 // is the only way we try to work around for the moment.
707 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
708 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
710 if (Br && Br->isUnconditional()) { // Critical edge?
711 BasicBlock::const_iterator I, E;
712 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
713 if (isa<EHSelectorInst>(I))
717 // No catch info found - try to extract some from the successor.
718 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
724 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
725 /// load into the specified FoldInst. Note that we could have a sequence where
726 /// multiple LLVM IR instructions are folded into the same machineinstr. For
727 /// example we could have:
728 /// A: x = load i32 *P
729 /// B: y = icmp A, 42
732 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
733 /// any other folded instructions) because it is between A and C.
735 /// If we succeed in folding the load into the operation, return true.
737 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
738 const Instruction *FoldInst,
740 // We know that the load has a single use, but don't know what it is. If it
741 // isn't one of the folded instructions, then we can't succeed here. Handle
742 // this by scanning the single-use users of the load until we get to FoldInst.
743 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
745 const Instruction *TheUser = LI->use_back();
746 while (TheUser != FoldInst && // Scan up until we find FoldInst.
747 // Stay in the right block.
748 TheUser->getParent() == FoldInst->getParent() &&
749 --MaxUsers) { // Don't scan too far.
750 // If there are multiple or no uses of this instruction, then bail out.
751 if (!TheUser->hasOneUse())
754 TheUser = TheUser->use_back();
757 // If we didn't find the fold instruction, then we failed to collapse the
759 if (TheUser != FoldInst)
762 // Don't try to fold volatile loads. Target has to deal with alignment
764 if (LI->isVolatile()) return false;
766 // Figure out which vreg this is going into. If there is no assigned vreg yet
767 // then there actually was no reference to it. Perhaps the load is referenced
768 // by a dead instruction.
769 unsigned LoadReg = FastIS->getRegForValue(LI);
773 // Check to see what the uses of this vreg are. If it has no uses, or more
774 // than one use (at the machine instr level) then we can't fold it.
775 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
776 if (RI == RegInfo->reg_end())
779 // See if there is exactly one use of the vreg. If there are multiple uses,
780 // then the instruction got lowered to multiple machine instructions or the
781 // use of the loaded value ended up being multiple operands of the result, in
782 // either case, we can't fold this.
783 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
784 if (PostRI != RegInfo->reg_end())
787 assert(RI.getOperand().isUse() &&
788 "The only use of the vreg must be a use, we haven't emitted the def!");
790 MachineInstr *User = &*RI;
792 // Set the insertion point properly. Folding the load can cause generation of
793 // other random instructions (like sign extends) for addressing modes, make
794 // sure they get inserted in a logical place before the new instruction.
795 FuncInfo->InsertPt = User;
796 FuncInfo->MBB = User->getParent();
798 // Ask the target to try folding the load.
799 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
802 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
803 /// side-effect free and is either dead or folded into a generated instruction.
804 /// Return false if it needs to be emitted.
805 static bool isFoldedOrDeadInstruction(const Instruction *I,
806 FunctionLoweringInfo *FuncInfo) {
807 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
808 !isa<TerminatorInst>(I) && // Terminators aren't folded.
809 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
810 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
813 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
814 // Initialize the Fast-ISel state, if needed.
815 FastISel *FastIS = 0;
817 FastIS = TLI.createFastISel(*FuncInfo);
819 // Iterate over all basic blocks in the function.
820 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
821 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
822 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
823 const BasicBlock *LLVMBB = *I;
825 if (OptLevel != CodeGenOpt::None) {
826 bool AllPredsVisited = true;
827 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
829 if (!FuncInfo->VisitedBBs.count(*PI)) {
830 AllPredsVisited = false;
835 if (AllPredsVisited) {
836 for (BasicBlock::const_iterator I = LLVMBB->begin();
837 isa<PHINode>(I); ++I)
838 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
840 for (BasicBlock::const_iterator I = LLVMBB->begin();
841 isa<PHINode>(I); ++I)
842 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));
845 FuncInfo->VisitedBBs.insert(LLVMBB);
848 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
849 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
851 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
852 BasicBlock::const_iterator const End = LLVMBB->end();
853 BasicBlock::const_iterator BI = End;
855 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
857 // Setup an EH landing-pad block.
858 if (FuncInfo->MBB->isLandingPad())
859 PrepareEHLandingPad();
861 // Lower any arguments needed in this block if this is the entry block.
862 if (LLVMBB == &Fn.getEntryBlock())
863 LowerArguments(LLVMBB);
865 // Before doing SelectionDAG ISel, see if FastISel has been requested.
867 FastIS->startNewBlock();
869 // Emit code for any incoming arguments. This must happen before
870 // beginning FastISel on the entry block.
871 if (LLVMBB == &Fn.getEntryBlock()) {
872 CurDAG->setRoot(SDB->getControlRoot());
876 // If we inserted any instructions at the beginning, make a note of
877 // where they are, so we can be sure to emit subsequent instructions
879 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
880 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
882 FastIS->setLastLocalValue(0);
885 // Do FastISel on as many instructions as possible.
886 for (; BI != Begin; --BI) {
887 const Instruction *Inst = llvm::prior(BI);
889 // If we no longer require this instruction, skip it.
890 if (isFoldedOrDeadInstruction(Inst, FuncInfo))
893 // Bottom-up: reset the insert pos at the top, after any local-value
895 FastIS->recomputeInsertPt();
897 // Try to select the instruction with FastISel.
898 if (FastIS->SelectInstruction(Inst)) {
899 ++NumFastIselSuccess;
900 // If fast isel succeeded, skip over all the folded instructions, and
901 // then see if there is a load right before the selected instructions.
902 // Try to fold the load if so.
903 const Instruction *BeforeInst = Inst;
904 while (BeforeInst != Begin) {
905 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
906 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
909 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
910 BeforeInst->hasOneUse() &&
911 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS))
912 // If we succeeded, don't re-select the load.
913 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
917 // Then handle certain instructions as single-LLVM-Instruction blocks.
918 if (isa<CallInst>(Inst)) {
919 ++NumFastIselFailures;
920 if (EnableFastISelVerbose || EnableFastISelAbort) {
921 dbgs() << "FastISel missed call: ";
925 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
926 unsigned &R = FuncInfo->ValueMap[Inst];
928 R = FuncInfo->CreateRegs(Inst->getType());
931 bool HadTailCall = false;
932 SelectBasicBlock(Inst, BI, HadTailCall);
934 // If the call was emitted as a tail call, we're done with the block.
943 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
944 // Don't abort, and use a different message for terminator misses.
945 ++NumFastIselFailures;
946 if (EnableFastISelVerbose || EnableFastISelAbort) {
947 dbgs() << "FastISel missed terminator: ";
951 ++NumFastIselFailures;
952 if (EnableFastISelVerbose || EnableFastISelAbort) {
953 dbgs() << "FastISel miss: ";
956 if (EnableFastISelAbort)
957 // The "fast" selector couldn't handle something and bailed.
958 // For the purpose of debugging, just abort.
959 llvm_unreachable("FastISel didn't select the entire block");
964 FastIS->recomputeInsertPt();
973 // Run SelectionDAG instruction selection on the remainder of the block
974 // not handled by FastISel. If FastISel is not run, this is the entire
977 SelectBasicBlock(Begin, BI, HadTailCall);
981 FuncInfo->PHINodesToUpdate.clear();
985 SDB->clearDanglingDebugInfo();
989 SelectionDAGISel::FinishBasicBlock() {
991 DEBUG(dbgs() << "Total amount of phi nodes to update: "
992 << FuncInfo->PHINodesToUpdate.size() << "\n";
993 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
994 dbgs() << "Node " << i << " : ("
995 << FuncInfo->PHINodesToUpdate[i].first
996 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
998 // Next, now that we know what the last MBB the LLVM BB expanded is, update
999 // PHI nodes in successors.
1000 if (SDB->SwitchCases.empty() &&
1001 SDB->JTCases.empty() &&
1002 SDB->BitTestCases.empty()) {
1003 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1004 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1005 assert(PHI->isPHI() &&
1006 "This is not a machine PHI node that we are updating!");
1007 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1010 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1011 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1016 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1017 // Lower header first, if it wasn't already lowered
1018 if (!SDB->BitTestCases[i].Emitted) {
1019 // Set the current basic block to the mbb we wish to insert the code into
1020 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1021 FuncInfo->InsertPt = FuncInfo->MBB->end();
1023 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1024 CurDAG->setRoot(SDB->getRoot());
1026 CodeGenAndEmitDAG();
1029 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1030 // Set the current basic block to the mbb we wish to insert the code into
1031 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1032 FuncInfo->InsertPt = FuncInfo->MBB->end();
1035 SDB->visitBitTestCase(SDB->BitTestCases[i],
1036 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1037 SDB->BitTestCases[i].Reg,
1038 SDB->BitTestCases[i].Cases[j],
1041 SDB->visitBitTestCase(SDB->BitTestCases[i],
1042 SDB->BitTestCases[i].Default,
1043 SDB->BitTestCases[i].Reg,
1044 SDB->BitTestCases[i].Cases[j],
1048 CurDAG->setRoot(SDB->getRoot());
1050 CodeGenAndEmitDAG();
1054 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1056 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1057 MachineBasicBlock *PHIBB = PHI->getParent();
1058 assert(PHI->isPHI() &&
1059 "This is not a machine PHI node that we are updating!");
1060 // This is "default" BB. We have two jumps to it. From "header" BB and
1061 // from last "case" BB.
1062 if (PHIBB == SDB->BitTestCases[i].Default) {
1063 PHI->addOperand(MachineOperand::
1064 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1066 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1067 PHI->addOperand(MachineOperand::
1068 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1070 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1073 // One of "cases" BB.
1074 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1076 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1077 if (cBB->isSuccessor(PHIBB)) {
1078 PHI->addOperand(MachineOperand::
1079 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1081 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1086 SDB->BitTestCases.clear();
1088 // If the JumpTable record is filled in, then we need to emit a jump table.
1089 // Updating the PHI nodes is tricky in this case, since we need to determine
1090 // whether the PHI is a successor of the range check MBB or the jump table MBB
1091 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1092 // Lower header first, if it wasn't already lowered
1093 if (!SDB->JTCases[i].first.Emitted) {
1094 // Set the current basic block to the mbb we wish to insert the code into
1095 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1096 FuncInfo->InsertPt = FuncInfo->MBB->end();
1098 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1100 CurDAG->setRoot(SDB->getRoot());
1102 CodeGenAndEmitDAG();
1105 // Set the current basic block to the mbb we wish to insert the code into
1106 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1107 FuncInfo->InsertPt = FuncInfo->MBB->end();
1109 SDB->visitJumpTable(SDB->JTCases[i].second);
1110 CurDAG->setRoot(SDB->getRoot());
1112 CodeGenAndEmitDAG();
1115 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1117 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1118 MachineBasicBlock *PHIBB = PHI->getParent();
1119 assert(PHI->isPHI() &&
1120 "This is not a machine PHI node that we are updating!");
1121 // "default" BB. We can go there only from header BB.
1122 if (PHIBB == SDB->JTCases[i].second.Default) {
1124 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1127 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1129 // JT BB. Just iterate over successors here
1130 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1132 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1134 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1138 SDB->JTCases.clear();
1140 // If the switch block involved a branch to one of the actual successors, we
1141 // need to update PHI nodes in that block.
1142 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1143 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1144 assert(PHI->isPHI() &&
1145 "This is not a machine PHI node that we are updating!");
1146 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1148 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1149 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1153 // If we generated any switch lowering information, build and codegen any
1154 // additional DAGs necessary.
1155 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1156 // Set the current basic block to the mbb we wish to insert the code into
1157 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1158 FuncInfo->InsertPt = FuncInfo->MBB->end();
1160 // Determine the unique successors.
1161 SmallVector<MachineBasicBlock *, 2> Succs;
1162 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1163 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1164 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1166 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1167 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1168 CurDAG->setRoot(SDB->getRoot());
1170 CodeGenAndEmitDAG();
1172 // Remember the last block, now that any splitting is done, for use in
1173 // populating PHI nodes in successors.
1174 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1176 // Handle any PHI nodes in successors of this chunk, as if we were coming
1177 // from the original BB before switch expansion. Note that PHI nodes can
1178 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1179 // handle them the right number of times.
1180 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1181 FuncInfo->MBB = Succs[i];
1182 FuncInfo->InsertPt = FuncInfo->MBB->end();
1183 // FuncInfo->MBB may have been removed from the CFG if a branch was
1185 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1186 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1187 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1189 // This value for this PHI node is recorded in PHINodesToUpdate.
1190 for (unsigned pn = 0; ; ++pn) {
1191 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1192 "Didn't find PHI entry!");
1193 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1194 Phi->addOperand(MachineOperand::
1195 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1197 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1205 SDB->SwitchCases.clear();
1209 /// Create the scheduler. If a specific scheduler was specified
1210 /// via the SchedulerRegistry, use it, otherwise select the
1211 /// one preferred by the target.
1213 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1214 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1218 RegisterScheduler::setDefault(Ctor);
1221 return Ctor(this, OptLevel);
1224 //===----------------------------------------------------------------------===//
1225 // Helper functions used by the generated instruction selector.
1226 //===----------------------------------------------------------------------===//
1227 // Calls to these methods are generated by tblgen.
1229 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1230 /// the dag combiner simplified the 255, we still want to match. RHS is the
1231 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1232 /// specified in the .td file (e.g. 255).
1233 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1234 int64_t DesiredMaskS) const {
1235 const APInt &ActualMask = RHS->getAPIntValue();
1236 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1238 // If the actual mask exactly matches, success!
1239 if (ActualMask == DesiredMask)
1242 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1243 if (ActualMask.intersects(~DesiredMask))
1246 // Otherwise, the DAG Combiner may have proven that the value coming in is
1247 // either already zero or is not demanded. Check for known zero input bits.
1248 APInt NeededMask = DesiredMask & ~ActualMask;
1249 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1252 // TODO: check to see if missing bits are just not demanded.
1254 // Otherwise, this pattern doesn't match.
1258 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1259 /// the dag combiner simplified the 255, we still want to match. RHS is the
1260 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1261 /// specified in the .td file (e.g. 255).
1262 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1263 int64_t DesiredMaskS) const {
1264 const APInt &ActualMask = RHS->getAPIntValue();
1265 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1267 // If the actual mask exactly matches, success!
1268 if (ActualMask == DesiredMask)
1271 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1272 if (ActualMask.intersects(~DesiredMask))
1275 // Otherwise, the DAG Combiner may have proven that the value coming in is
1276 // either already zero or is not demanded. Check for known zero input bits.
1277 APInt NeededMask = DesiredMask & ~ActualMask;
1279 APInt KnownZero, KnownOne;
1280 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1282 // If all the missing bits in the or are already known to be set, match!
1283 if ((NeededMask & KnownOne) == NeededMask)
1286 // TODO: check to see if missing bits are just not demanded.
1288 // Otherwise, this pattern doesn't match.
1293 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1294 /// by tblgen. Others should not call it.
1295 void SelectionDAGISel::
1296 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1297 std::vector<SDValue> InOps;
1298 std::swap(InOps, Ops);
1300 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1301 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1302 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1303 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1305 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1306 if (InOps[e-1].getValueType() == MVT::Glue)
1307 --e; // Don't process a glue operand if it is here.
1310 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1311 if (!InlineAsm::isMemKind(Flags)) {
1312 // Just skip over this operand, copying the operands verbatim.
1313 Ops.insert(Ops.end(), InOps.begin()+i,
1314 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1315 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1317 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1318 "Memory operand with multiple values?");
1319 // Otherwise, this is a memory operand. Ask the target to select it.
1320 std::vector<SDValue> SelOps;
1321 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1322 report_fatal_error("Could not match memory address. Inline asm"
1325 // Add this to the output node.
1327 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1328 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1329 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1334 // Add the glue input back if present.
1335 if (e != InOps.size())
1336 Ops.push_back(InOps.back());
1339 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1342 static SDNode *findGlueUse(SDNode *N) {
1343 unsigned FlagResNo = N->getNumValues()-1;
1344 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1345 SDUse &Use = I.getUse();
1346 if (Use.getResNo() == FlagResNo)
1347 return Use.getUser();
1352 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1353 /// This function recursively traverses up the operand chain, ignoring
1355 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1356 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1357 bool IgnoreChains) {
1358 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1359 // greater than all of its (recursive) operands. If we scan to a point where
1360 // 'use' is smaller than the node we're scanning for, then we know we will
1363 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1364 // happen because we scan down to newly selected nodes in the case of glue
1366 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1369 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1370 // won't fail if we scan it again.
1371 if (!Visited.insert(Use))
1374 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1375 // Ignore chain uses, they are validated by HandleMergeInputChains.
1376 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1379 SDNode *N = Use->getOperand(i).getNode();
1381 if (Use == ImmedUse || Use == Root)
1382 continue; // We are not looking for immediate use.
1387 // Traverse up the operand chain.
1388 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1394 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1395 /// operand node N of U during instruction selection that starts at Root.
1396 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1397 SDNode *Root) const {
1398 if (OptLevel == CodeGenOpt::None) return false;
1399 return N.hasOneUse();
1402 /// IsLegalToFold - Returns true if the specific operand node N of
1403 /// U can be folded during instruction selection that starts at Root.
1404 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1405 CodeGenOpt::Level OptLevel,
1406 bool IgnoreChains) {
1407 if (OptLevel == CodeGenOpt::None) return false;
1409 // If Root use can somehow reach N through a path that that doesn't contain
1410 // U then folding N would create a cycle. e.g. In the following
1411 // diagram, Root can reach N through X. If N is folded into into Root, then
1412 // X is both a predecessor and a successor of U.
1423 // * indicates nodes to be folded together.
1425 // If Root produces glue, then it gets (even more) interesting. Since it
1426 // will be "glued" together with its glue use in the scheduler, we need to
1427 // check if it might reach N.
1446 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1447 // (call it Fold), then X is a predecessor of GU and a successor of
1448 // Fold. But since Fold and GU are glued together, this will create
1449 // a cycle in the scheduling graph.
1451 // If the node has glue, walk down the graph to the "lowest" node in the
1453 EVT VT = Root->getValueType(Root->getNumValues()-1);
1454 while (VT == MVT::Glue) {
1455 SDNode *GU = findGlueUse(Root);
1459 VT = Root->getValueType(Root->getNumValues()-1);
1461 // If our query node has a glue result with a use, we've walked up it. If
1462 // the user (which has already been selected) has a chain or indirectly uses
1463 // the chain, our WalkChainUsers predicate will not consider it. Because of
1464 // this, we cannot ignore chains in this predicate.
1465 IgnoreChains = false;
1469 SmallPtrSet<SDNode*, 16> Visited;
1470 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1473 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1474 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1475 SelectInlineAsmMemoryOperands(Ops);
1477 std::vector<EVT> VTs;
1478 VTs.push_back(MVT::Other);
1479 VTs.push_back(MVT::Glue);
1480 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1481 VTs, &Ops[0], Ops.size());
1483 return New.getNode();
1486 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1487 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1490 /// GetVBR - decode a vbr encoding whose top bit is set.
1491 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1492 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1493 assert(Val >= 128 && "Not a VBR");
1494 Val &= 127; // Remove first vbr bit.
1499 NextBits = MatcherTable[Idx++];
1500 Val |= (NextBits&127) << Shift;
1502 } while (NextBits & 128);
1508 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1509 /// interior glue and chain results to use the new glue and chain results.
1510 void SelectionDAGISel::
1511 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1512 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1514 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1515 bool isMorphNodeTo) {
1516 SmallVector<SDNode*, 4> NowDeadNodes;
1518 ISelUpdater ISU(ISelPosition);
1520 // Now that all the normal results are replaced, we replace the chain and
1521 // glue results if present.
1522 if (!ChainNodesMatched.empty()) {
1523 assert(InputChain.getNode() != 0 &&
1524 "Matched input chains but didn't produce a chain");
1525 // Loop over all of the nodes we matched that produced a chain result.
1526 // Replace all the chain results with the final chain we ended up with.
1527 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1528 SDNode *ChainNode = ChainNodesMatched[i];
1530 // If this node was already deleted, don't look at it.
1531 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1534 // Don't replace the results of the root node if we're doing a
1536 if (ChainNode == NodeToMatch && isMorphNodeTo)
1539 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1540 if (ChainVal.getValueType() == MVT::Glue)
1541 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1542 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1543 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1545 // If the node became dead and we haven't already seen it, delete it.
1546 if (ChainNode->use_empty() &&
1547 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1548 NowDeadNodes.push_back(ChainNode);
1552 // If the result produces glue, update any glue results in the matched
1553 // pattern with the glue result.
1554 if (InputGlue.getNode() != 0) {
1555 // Handle any interior nodes explicitly marked.
1556 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1557 SDNode *FRN = GlueResultNodesMatched[i];
1559 // If this node was already deleted, don't look at it.
1560 if (FRN->getOpcode() == ISD::DELETED_NODE)
1563 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1564 "Doesn't have a glue result");
1565 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1568 // If the node became dead and we haven't already seen it, delete it.
1569 if (FRN->use_empty() &&
1570 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1571 NowDeadNodes.push_back(FRN);
1575 if (!NowDeadNodes.empty())
1576 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1578 DEBUG(errs() << "ISEL: Match complete!\n");
1584 CR_LeadsToInteriorNode
1587 /// WalkChainUsers - Walk down the users of the specified chained node that is
1588 /// part of the pattern we're matching, looking at all of the users we find.
1589 /// This determines whether something is an interior node, whether we have a
1590 /// non-pattern node in between two pattern nodes (which prevent folding because
1591 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1592 /// between pattern nodes (in which case the TF becomes part of the pattern).
1594 /// The walk we do here is guaranteed to be small because we quickly get down to
1595 /// already selected nodes "below" us.
1597 WalkChainUsers(SDNode *ChainedNode,
1598 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1599 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1600 ChainResult Result = CR_Simple;
1602 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1603 E = ChainedNode->use_end(); UI != E; ++UI) {
1604 // Make sure the use is of the chain, not some other value we produce.
1605 if (UI.getUse().getValueType() != MVT::Other) continue;
1609 // If we see an already-selected machine node, then we've gone beyond the
1610 // pattern that we're selecting down into the already selected chunk of the
1612 if (User->isMachineOpcode() ||
1613 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1616 if (User->getOpcode() == ISD::CopyToReg ||
1617 User->getOpcode() == ISD::CopyFromReg ||
1618 User->getOpcode() == ISD::INLINEASM ||
1619 User->getOpcode() == ISD::EH_LABEL) {
1620 // If their node ID got reset to -1 then they've already been selected.
1621 // Treat them like a MachineOpcode.
1622 if (User->getNodeId() == -1)
1626 // If we have a TokenFactor, we handle it specially.
1627 if (User->getOpcode() != ISD::TokenFactor) {
1628 // If the node isn't a token factor and isn't part of our pattern, then it
1629 // must be a random chained node in between two nodes we're selecting.
1630 // This happens when we have something like:
1635 // Because we structurally match the load/store as a read/modify/write,
1636 // but the call is chained between them. We cannot fold in this case
1637 // because it would induce a cycle in the graph.
1638 if (!std::count(ChainedNodesInPattern.begin(),
1639 ChainedNodesInPattern.end(), User))
1640 return CR_InducesCycle;
1642 // Otherwise we found a node that is part of our pattern. For example in:
1646 // This would happen when we're scanning down from the load and see the
1647 // store as a user. Record that there is a use of ChainedNode that is
1648 // part of the pattern and keep scanning uses.
1649 Result = CR_LeadsToInteriorNode;
1650 InteriorChainedNodes.push_back(User);
1654 // If we found a TokenFactor, there are two cases to consider: first if the
1655 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1656 // uses of the TF are in our pattern) we just want to ignore it. Second,
1657 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1663 // | \ DAG's like cheese
1666 // [TokenFactor] [Op]
1673 // In this case, the TokenFactor becomes part of our match and we rewrite it
1674 // as a new TokenFactor.
1676 // To distinguish these two cases, do a recursive walk down the uses.
1677 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1679 // If the uses of the TokenFactor are just already-selected nodes, ignore
1680 // it, it is "below" our pattern.
1682 case CR_InducesCycle:
1683 // If the uses of the TokenFactor lead to nodes that are not part of our
1684 // pattern that are not selected, folding would turn this into a cycle,
1686 return CR_InducesCycle;
1687 case CR_LeadsToInteriorNode:
1688 break; // Otherwise, keep processing.
1691 // Okay, we know we're in the interesting interior case. The TokenFactor
1692 // is now going to be considered part of the pattern so that we rewrite its
1693 // uses (it may have uses that are not part of the pattern) with the
1694 // ultimate chain result of the generated code. We will also add its chain
1695 // inputs as inputs to the ultimate TokenFactor we create.
1696 Result = CR_LeadsToInteriorNode;
1697 ChainedNodesInPattern.push_back(User);
1698 InteriorChainedNodes.push_back(User);
1705 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1706 /// operation for when the pattern matched at least one node with a chains. The
1707 /// input vector contains a list of all of the chained nodes that we match. We
1708 /// must determine if this is a valid thing to cover (i.e. matching it won't
1709 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1710 /// be used as the input node chain for the generated nodes.
1712 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1713 SelectionDAG *CurDAG) {
1714 // Walk all of the chained nodes we've matched, recursively scanning down the
1715 // users of the chain result. This adds any TokenFactor nodes that are caught
1716 // in between chained nodes to the chained and interior nodes list.
1717 SmallVector<SDNode*, 3> InteriorChainedNodes;
1718 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1719 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1720 InteriorChainedNodes) == CR_InducesCycle)
1721 return SDValue(); // Would induce a cycle.
1724 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1725 // that we are interested in. Form our input TokenFactor node.
1726 SmallVector<SDValue, 3> InputChains;
1727 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1728 // Add the input chain of this node to the InputChains list (which will be
1729 // the operands of the generated TokenFactor) if it's not an interior node.
1730 SDNode *N = ChainNodesMatched[i];
1731 if (N->getOpcode() != ISD::TokenFactor) {
1732 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1735 // Otherwise, add the input chain.
1736 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1737 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1738 InputChains.push_back(InChain);
1742 // If we have a token factor, we want to add all inputs of the token factor
1743 // that are not part of the pattern we're matching.
1744 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1745 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1746 N->getOperand(op).getNode()))
1747 InputChains.push_back(N->getOperand(op));
1752 if (InputChains.size() == 1)
1753 return InputChains[0];
1754 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1755 MVT::Other, &InputChains[0], InputChains.size());
1758 /// MorphNode - Handle morphing a node in place for the selector.
1759 SDNode *SelectionDAGISel::
1760 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1761 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1762 // It is possible we're using MorphNodeTo to replace a node with no
1763 // normal results with one that has a normal result (or we could be
1764 // adding a chain) and the input could have glue and chains as well.
1765 // In this case we need to shift the operands down.
1766 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1767 // than the old isel though.
1768 int OldGlueResultNo = -1, OldChainResultNo = -1;
1770 unsigned NTMNumResults = Node->getNumValues();
1771 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1772 OldGlueResultNo = NTMNumResults-1;
1773 if (NTMNumResults != 1 &&
1774 Node->getValueType(NTMNumResults-2) == MVT::Other)
1775 OldChainResultNo = NTMNumResults-2;
1776 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1777 OldChainResultNo = NTMNumResults-1;
1779 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1780 // that this deletes operands of the old node that become dead.
1781 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1783 // MorphNodeTo can operate in two ways: if an existing node with the
1784 // specified operands exists, it can just return it. Otherwise, it
1785 // updates the node in place to have the requested operands.
1787 // If we updated the node in place, reset the node ID. To the isel,
1788 // this should be just like a newly allocated machine node.
1792 unsigned ResNumResults = Res->getNumValues();
1793 // Move the glue if needed.
1794 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1795 (unsigned)OldGlueResultNo != ResNumResults-1)
1796 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1797 SDValue(Res, ResNumResults-1));
1799 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1802 // Move the chain reference if needed.
1803 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1804 (unsigned)OldChainResultNo != ResNumResults-1)
1805 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1806 SDValue(Res, ResNumResults-1));
1808 // Otherwise, no replacement happened because the node already exists. Replace
1809 // Uses of the old node with the new one.
1811 CurDAG->ReplaceAllUsesWith(Node, Res);
1816 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1817 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1818 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1820 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1821 // Accept if it is exactly the same as a previously recorded node.
1822 unsigned RecNo = MatcherTable[MatcherIndex++];
1823 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1824 return N == RecordedNodes[RecNo].first;
1827 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1828 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1829 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1830 SelectionDAGISel &SDISel) {
1831 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1834 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1835 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1836 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1837 SelectionDAGISel &SDISel, SDNode *N) {
1838 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1841 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1842 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1844 uint16_t Opc = MatcherTable[MatcherIndex++];
1845 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1846 return N->getOpcode() == Opc;
1849 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1850 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1851 SDValue N, const TargetLowering &TLI) {
1852 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1853 if (N.getValueType() == VT) return true;
1855 // Handle the case when VT is iPTR.
1856 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1859 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1860 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1861 SDValue N, const TargetLowering &TLI,
1863 if (ChildNo >= N.getNumOperands())
1864 return false; // Match fails if out of range child #.
1865 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1869 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1870 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1872 return cast<CondCodeSDNode>(N)->get() ==
1873 (ISD::CondCode)MatcherTable[MatcherIndex++];
1876 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1877 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1878 SDValue N, const TargetLowering &TLI) {
1879 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1880 if (cast<VTSDNode>(N)->getVT() == VT)
1883 // Handle the case when VT is iPTR.
1884 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1887 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1888 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1890 int64_t Val = MatcherTable[MatcherIndex++];
1892 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1894 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1895 return C != 0 && C->getSExtValue() == Val;
1898 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1899 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1900 SDValue N, SelectionDAGISel &SDISel) {
1901 int64_t Val = MatcherTable[MatcherIndex++];
1903 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1905 if (N->getOpcode() != ISD::AND) return false;
1907 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1908 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1911 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1912 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1913 SDValue N, SelectionDAGISel &SDISel) {
1914 int64_t Val = MatcherTable[MatcherIndex++];
1916 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1918 if (N->getOpcode() != ISD::OR) return false;
1920 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1921 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1924 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1925 /// scope, evaluate the current node. If the current predicate is known to
1926 /// fail, set Result=true and return anything. If the current predicate is
1927 /// known to pass, set Result=false and return the MatcherIndex to continue
1928 /// with. If the current predicate is unknown, set Result=false and return the
1929 /// MatcherIndex to continue with.
1930 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1931 unsigned Index, SDValue N,
1932 bool &Result, SelectionDAGISel &SDISel,
1933 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1934 switch (Table[Index++]) {
1937 return Index-1; // Could not evaluate this predicate.
1938 case SelectionDAGISel::OPC_CheckSame:
1939 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1941 case SelectionDAGISel::OPC_CheckPatternPredicate:
1942 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1944 case SelectionDAGISel::OPC_CheckPredicate:
1945 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1947 case SelectionDAGISel::OPC_CheckOpcode:
1948 Result = !::CheckOpcode(Table, Index, N.getNode());
1950 case SelectionDAGISel::OPC_CheckType:
1951 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1953 case SelectionDAGISel::OPC_CheckChild0Type:
1954 case SelectionDAGISel::OPC_CheckChild1Type:
1955 case SelectionDAGISel::OPC_CheckChild2Type:
1956 case SelectionDAGISel::OPC_CheckChild3Type:
1957 case SelectionDAGISel::OPC_CheckChild4Type:
1958 case SelectionDAGISel::OPC_CheckChild5Type:
1959 case SelectionDAGISel::OPC_CheckChild6Type:
1960 case SelectionDAGISel::OPC_CheckChild7Type:
1961 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1962 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1964 case SelectionDAGISel::OPC_CheckCondCode:
1965 Result = !::CheckCondCode(Table, Index, N);
1967 case SelectionDAGISel::OPC_CheckValueType:
1968 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1970 case SelectionDAGISel::OPC_CheckInteger:
1971 Result = !::CheckInteger(Table, Index, N);
1973 case SelectionDAGISel::OPC_CheckAndImm:
1974 Result = !::CheckAndImm(Table, Index, N, SDISel);
1976 case SelectionDAGISel::OPC_CheckOrImm:
1977 Result = !::CheckOrImm(Table, Index, N, SDISel);
1985 /// FailIndex - If this match fails, this is the index to continue with.
1988 /// NodeStack - The node stack when the scope was formed.
1989 SmallVector<SDValue, 4> NodeStack;
1991 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1992 unsigned NumRecordedNodes;
1994 /// NumMatchedMemRefs - The number of matched memref entries.
1995 unsigned NumMatchedMemRefs;
1997 /// InputChain/InputGlue - The current chain/glue
1998 SDValue InputChain, InputGlue;
2000 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2001 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2006 SDNode *SelectionDAGISel::
2007 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2008 unsigned TableSize) {
2009 // FIXME: Should these even be selected? Handle these cases in the caller?
2010 switch (NodeToMatch->getOpcode()) {
2013 case ISD::EntryToken: // These nodes remain the same.
2014 case ISD::BasicBlock:
2016 //case ISD::VALUETYPE:
2017 //case ISD::CONDCODE:
2018 case ISD::HANDLENODE:
2019 case ISD::MDNODE_SDNODE:
2020 case ISD::TargetConstant:
2021 case ISD::TargetConstantFP:
2022 case ISD::TargetConstantPool:
2023 case ISD::TargetFrameIndex:
2024 case ISD::TargetExternalSymbol:
2025 case ISD::TargetBlockAddress:
2026 case ISD::TargetJumpTable:
2027 case ISD::TargetGlobalTLSAddress:
2028 case ISD::TargetGlobalAddress:
2029 case ISD::TokenFactor:
2030 case ISD::CopyFromReg:
2031 case ISD::CopyToReg:
2033 NodeToMatch->setNodeId(-1); // Mark selected.
2035 case ISD::AssertSext:
2036 case ISD::AssertZext:
2037 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2038 NodeToMatch->getOperand(0));
2040 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2041 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2044 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2046 // Set up the node stack with NodeToMatch as the only node on the stack.
2047 SmallVector<SDValue, 8> NodeStack;
2048 SDValue N = SDValue(NodeToMatch, 0);
2049 NodeStack.push_back(N);
2051 // MatchScopes - Scopes used when matching, if a match failure happens, this
2052 // indicates where to continue checking.
2053 SmallVector<MatchScope, 8> MatchScopes;
2055 // RecordedNodes - This is the set of nodes that have been recorded by the
2056 // state machine. The second value is the parent of the node, or null if the
2057 // root is recorded.
2058 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2060 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2062 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2064 // These are the current input chain and glue for use when generating nodes.
2065 // Various Emit operations change these. For example, emitting a copytoreg
2066 // uses and updates these.
2067 SDValue InputChain, InputGlue;
2069 // ChainNodesMatched - If a pattern matches nodes that have input/output
2070 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2071 // which ones they are. The result is captured into this list so that we can
2072 // update the chain results when the pattern is complete.
2073 SmallVector<SDNode*, 3> ChainNodesMatched;
2074 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2076 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2077 NodeToMatch->dump(CurDAG);
2080 // Determine where to start the interpreter. Normally we start at opcode #0,
2081 // but if the state machine starts with an OPC_SwitchOpcode, then we
2082 // accelerate the first lookup (which is guaranteed to be hot) with the
2083 // OpcodeOffset table.
2084 unsigned MatcherIndex = 0;
2086 if (!OpcodeOffset.empty()) {
2087 // Already computed the OpcodeOffset table, just index into it.
2088 if (N.getOpcode() < OpcodeOffset.size())
2089 MatcherIndex = OpcodeOffset[N.getOpcode()];
2090 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2092 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2093 // Otherwise, the table isn't computed, but the state machine does start
2094 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2095 // is the first time we're selecting an instruction.
2098 // Get the size of this case.
2099 unsigned CaseSize = MatcherTable[Idx++];
2101 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2102 if (CaseSize == 0) break;
2104 // Get the opcode, add the index to the table.
2105 uint16_t Opc = MatcherTable[Idx++];
2106 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2107 if (Opc >= OpcodeOffset.size())
2108 OpcodeOffset.resize((Opc+1)*2);
2109 OpcodeOffset[Opc] = Idx;
2113 // Okay, do the lookup for the first opcode.
2114 if (N.getOpcode() < OpcodeOffset.size())
2115 MatcherIndex = OpcodeOffset[N.getOpcode()];
2119 assert(MatcherIndex < TableSize && "Invalid index");
2121 unsigned CurrentOpcodeIndex = MatcherIndex;
2123 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2126 // Okay, the semantics of this operation are that we should push a scope
2127 // then evaluate the first child. However, pushing a scope only to have
2128 // the first check fail (which then pops it) is inefficient. If we can
2129 // determine immediately that the first check (or first several) will
2130 // immediately fail, don't even bother pushing a scope for them.
2134 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2135 if (NumToSkip & 128)
2136 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2137 // Found the end of the scope with no match.
2138 if (NumToSkip == 0) {
2143 FailIndex = MatcherIndex+NumToSkip;
2145 unsigned MatcherIndexOfPredicate = MatcherIndex;
2146 (void)MatcherIndexOfPredicate; // silence warning.
2148 // If we can't evaluate this predicate without pushing a scope (e.g. if
2149 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2150 // push the scope and evaluate the full predicate chain.
2152 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2153 Result, *this, RecordedNodes);
2157 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2158 << "index " << MatcherIndexOfPredicate
2159 << ", continuing at " << FailIndex << "\n");
2160 ++NumDAGIselRetries;
2162 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2163 // move to the next case.
2164 MatcherIndex = FailIndex;
2167 // If the whole scope failed to match, bail.
2168 if (FailIndex == 0) break;
2170 // Push a MatchScope which indicates where to go if the first child fails
2172 MatchScope NewEntry;
2173 NewEntry.FailIndex = FailIndex;
2174 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2175 NewEntry.NumRecordedNodes = RecordedNodes.size();
2176 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2177 NewEntry.InputChain = InputChain;
2178 NewEntry.InputGlue = InputGlue;
2179 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2180 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2181 MatchScopes.push_back(NewEntry);
2184 case OPC_RecordNode: {
2185 // Remember this node, it may end up being an operand in the pattern.
2187 if (NodeStack.size() > 1)
2188 Parent = NodeStack[NodeStack.size()-2].getNode();
2189 RecordedNodes.push_back(std::make_pair(N, Parent));
2193 case OPC_RecordChild0: case OPC_RecordChild1:
2194 case OPC_RecordChild2: case OPC_RecordChild3:
2195 case OPC_RecordChild4: case OPC_RecordChild5:
2196 case OPC_RecordChild6: case OPC_RecordChild7: {
2197 unsigned ChildNo = Opcode-OPC_RecordChild0;
2198 if (ChildNo >= N.getNumOperands())
2199 break; // Match fails if out of range child #.
2201 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2205 case OPC_RecordMemRef:
2206 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2209 case OPC_CaptureGlueInput:
2210 // If the current node has an input glue, capture it in InputGlue.
2211 if (N->getNumOperands() != 0 &&
2212 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2213 InputGlue = N->getOperand(N->getNumOperands()-1);
2216 case OPC_MoveChild: {
2217 unsigned ChildNo = MatcherTable[MatcherIndex++];
2218 if (ChildNo >= N.getNumOperands())
2219 break; // Match fails if out of range child #.
2220 N = N.getOperand(ChildNo);
2221 NodeStack.push_back(N);
2225 case OPC_MoveParent:
2226 // Pop the current node off the NodeStack.
2227 NodeStack.pop_back();
2228 assert(!NodeStack.empty() && "Node stack imbalance!");
2229 N = NodeStack.back();
2233 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2235 case OPC_CheckPatternPredicate:
2236 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2238 case OPC_CheckPredicate:
2239 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2243 case OPC_CheckComplexPat: {
2244 unsigned CPNum = MatcherTable[MatcherIndex++];
2245 unsigned RecNo = MatcherTable[MatcherIndex++];
2246 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2247 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2248 RecordedNodes[RecNo].first, CPNum,
2253 case OPC_CheckOpcode:
2254 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2258 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2261 case OPC_SwitchOpcode: {
2262 unsigned CurNodeOpcode = N.getOpcode();
2263 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2266 // Get the size of this case.
2267 CaseSize = MatcherTable[MatcherIndex++];
2269 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2270 if (CaseSize == 0) break;
2272 uint16_t Opc = MatcherTable[MatcherIndex++];
2273 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2275 // If the opcode matches, then we will execute this case.
2276 if (CurNodeOpcode == Opc)
2279 // Otherwise, skip over this case.
2280 MatcherIndex += CaseSize;
2283 // If no cases matched, bail out.
2284 if (CaseSize == 0) break;
2286 // Otherwise, execute the case we found.
2287 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2288 << " to " << MatcherIndex << "\n");
2292 case OPC_SwitchType: {
2293 MVT CurNodeVT = N.getValueType().getSimpleVT();
2294 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2297 // Get the size of this case.
2298 CaseSize = MatcherTable[MatcherIndex++];
2300 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2301 if (CaseSize == 0) break;
2303 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2304 if (CaseVT == MVT::iPTR)
2305 CaseVT = TLI.getPointerTy();
2307 // If the VT matches, then we will execute this case.
2308 if (CurNodeVT == CaseVT)
2311 // Otherwise, skip over this case.
2312 MatcherIndex += CaseSize;
2315 // If no cases matched, bail out.
2316 if (CaseSize == 0) break;
2318 // Otherwise, execute the case we found.
2319 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2320 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2323 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2324 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2325 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2326 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2327 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2328 Opcode-OPC_CheckChild0Type))
2331 case OPC_CheckCondCode:
2332 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2334 case OPC_CheckValueType:
2335 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2337 case OPC_CheckInteger:
2338 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2340 case OPC_CheckAndImm:
2341 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2343 case OPC_CheckOrImm:
2344 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2347 case OPC_CheckFoldableChainNode: {
2348 assert(NodeStack.size() != 1 && "No parent node");
2349 // Verify that all intermediate nodes between the root and this one have
2351 bool HasMultipleUses = false;
2352 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2353 if (!NodeStack[i].hasOneUse()) {
2354 HasMultipleUses = true;
2357 if (HasMultipleUses) break;
2359 // Check to see that the target thinks this is profitable to fold and that
2360 // we can fold it without inducing cycles in the graph.
2361 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2363 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2364 NodeToMatch, OptLevel,
2365 true/*We validate our own chains*/))
2370 case OPC_EmitInteger: {
2371 MVT::SimpleValueType VT =
2372 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2373 int64_t Val = MatcherTable[MatcherIndex++];
2375 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2376 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2377 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2380 case OPC_EmitRegister: {
2381 MVT::SimpleValueType VT =
2382 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2383 unsigned RegNo = MatcherTable[MatcherIndex++];
2384 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2385 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2388 case OPC_EmitRegister2: {
2389 // For targets w/ more than 256 register names, the register enum
2390 // values are stored in two bytes in the matcher table (just like
2392 MVT::SimpleValueType VT =
2393 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2394 unsigned RegNo = MatcherTable[MatcherIndex++];
2395 RegNo |= MatcherTable[MatcherIndex++] << 8;
2396 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2397 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2401 case OPC_EmitConvertToTarget: {
2402 // Convert from IMM/FPIMM to target version.
2403 unsigned RecNo = MatcherTable[MatcherIndex++];
2404 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2405 SDValue Imm = RecordedNodes[RecNo].first;
2407 if (Imm->getOpcode() == ISD::Constant) {
2408 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2409 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2410 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2411 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2412 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2415 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2419 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2420 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2421 // These are space-optimized forms of OPC_EmitMergeInputChains.
2422 assert(InputChain.getNode() == 0 &&
2423 "EmitMergeInputChains should be the first chain producing node");
2424 assert(ChainNodesMatched.empty() &&
2425 "Should only have one EmitMergeInputChains per match");
2427 // Read all of the chained nodes.
2428 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2429 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2430 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2432 // FIXME: What if other value results of the node have uses not matched
2434 if (ChainNodesMatched.back() != NodeToMatch &&
2435 !RecordedNodes[RecNo].first.hasOneUse()) {
2436 ChainNodesMatched.clear();
2440 // Merge the input chains if they are not intra-pattern references.
2441 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2443 if (InputChain.getNode() == 0)
2444 break; // Failed to merge.
2448 case OPC_EmitMergeInputChains: {
2449 assert(InputChain.getNode() == 0 &&
2450 "EmitMergeInputChains should be the first chain producing node");
2451 // This node gets a list of nodes we matched in the input that have
2452 // chains. We want to token factor all of the input chains to these nodes
2453 // together. However, if any of the input chains is actually one of the
2454 // nodes matched in this pattern, then we have an intra-match reference.
2455 // Ignore these because the newly token factored chain should not refer to
2457 unsigned NumChains = MatcherTable[MatcherIndex++];
2458 assert(NumChains != 0 && "Can't TF zero chains");
2460 assert(ChainNodesMatched.empty() &&
2461 "Should only have one EmitMergeInputChains per match");
2463 // Read all of the chained nodes.
2464 for (unsigned i = 0; i != NumChains; ++i) {
2465 unsigned RecNo = MatcherTable[MatcherIndex++];
2466 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2467 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2469 // FIXME: What if other value results of the node have uses not matched
2471 if (ChainNodesMatched.back() != NodeToMatch &&
2472 !RecordedNodes[RecNo].first.hasOneUse()) {
2473 ChainNodesMatched.clear();
2478 // If the inner loop broke out, the match fails.
2479 if (ChainNodesMatched.empty())
2482 // Merge the input chains if they are not intra-pattern references.
2483 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2485 if (InputChain.getNode() == 0)
2486 break; // Failed to merge.
2491 case OPC_EmitCopyToReg: {
2492 unsigned RecNo = MatcherTable[MatcherIndex++];
2493 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2494 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2496 if (InputChain.getNode() == 0)
2497 InputChain = CurDAG->getEntryNode();
2499 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2500 DestPhysReg, RecordedNodes[RecNo].first,
2503 InputGlue = InputChain.getValue(1);
2507 case OPC_EmitNodeXForm: {
2508 unsigned XFormNo = MatcherTable[MatcherIndex++];
2509 unsigned RecNo = MatcherTable[MatcherIndex++];
2510 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2511 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2512 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2517 case OPC_MorphNodeTo: {
2518 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2519 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2520 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2521 // Get the result VT list.
2522 unsigned NumVTs = MatcherTable[MatcherIndex++];
2523 SmallVector<EVT, 4> VTs;
2524 for (unsigned i = 0; i != NumVTs; ++i) {
2525 MVT::SimpleValueType VT =
2526 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2527 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2531 if (EmitNodeInfo & OPFL_Chain)
2532 VTs.push_back(MVT::Other);
2533 if (EmitNodeInfo & OPFL_GlueOutput)
2534 VTs.push_back(MVT::Glue);
2536 // This is hot code, so optimize the two most common cases of 1 and 2
2539 if (VTs.size() == 1)
2540 VTList = CurDAG->getVTList(VTs[0]);
2541 else if (VTs.size() == 2)
2542 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2544 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2546 // Get the operand list.
2547 unsigned NumOps = MatcherTable[MatcherIndex++];
2548 SmallVector<SDValue, 8> Ops;
2549 for (unsigned i = 0; i != NumOps; ++i) {
2550 unsigned RecNo = MatcherTable[MatcherIndex++];
2552 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2554 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2555 Ops.push_back(RecordedNodes[RecNo].first);
2558 // If there are variadic operands to add, handle them now.
2559 if (EmitNodeInfo & OPFL_VariadicInfo) {
2560 // Determine the start index to copy from.
2561 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2562 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2563 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2564 "Invalid variadic node");
2565 // Copy all of the variadic operands, not including a potential glue
2567 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2569 SDValue V = NodeToMatch->getOperand(i);
2570 if (V.getValueType() == MVT::Glue) break;
2575 // If this has chain/glue inputs, add them.
2576 if (EmitNodeInfo & OPFL_Chain)
2577 Ops.push_back(InputChain);
2578 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2579 Ops.push_back(InputGlue);
2583 if (Opcode != OPC_MorphNodeTo) {
2584 // If this is a normal EmitNode command, just create the new node and
2585 // add the results to the RecordedNodes list.
2586 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2587 VTList, Ops.data(), Ops.size());
2589 // Add all the non-glue/non-chain results to the RecordedNodes list.
2590 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2591 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2592 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2597 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2601 // If the node had chain/glue results, update our notion of the current
2603 if (EmitNodeInfo & OPFL_GlueOutput) {
2604 InputGlue = SDValue(Res, VTs.size()-1);
2605 if (EmitNodeInfo & OPFL_Chain)
2606 InputChain = SDValue(Res, VTs.size()-2);
2607 } else if (EmitNodeInfo & OPFL_Chain)
2608 InputChain = SDValue(Res, VTs.size()-1);
2610 // If the OPFL_MemRefs glue is set on this node, slap all of the
2611 // accumulated memrefs onto it.
2613 // FIXME: This is vastly incorrect for patterns with multiple outputs
2614 // instructions that access memory and for ComplexPatterns that match
2616 if (EmitNodeInfo & OPFL_MemRefs) {
2617 // Only attach load or store memory operands if the generated
2618 // instruction may load or store.
2619 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2620 bool mayLoad = MCID.mayLoad();
2621 bool mayStore = MCID.mayStore();
2623 unsigned NumMemRefs = 0;
2624 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2625 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2626 if ((*I)->isLoad()) {
2629 } else if ((*I)->isStore()) {
2637 MachineSDNode::mmo_iterator MemRefs =
2638 MF->allocateMemRefsArray(NumMemRefs);
2640 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2641 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2642 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2643 if ((*I)->isLoad()) {
2646 } else if ((*I)->isStore()) {
2654 cast<MachineSDNode>(Res)
2655 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2659 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2660 << " node: "; Res->dump(CurDAG); errs() << "\n");
2662 // If this was a MorphNodeTo then we're completely done!
2663 if (Opcode == OPC_MorphNodeTo) {
2664 // Update chain and glue uses.
2665 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2666 InputGlue, GlueResultNodesMatched, true);
2673 case OPC_MarkGlueResults: {
2674 unsigned NumNodes = MatcherTable[MatcherIndex++];
2676 // Read and remember all the glue-result nodes.
2677 for (unsigned i = 0; i != NumNodes; ++i) {
2678 unsigned RecNo = MatcherTable[MatcherIndex++];
2680 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2682 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2683 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2688 case OPC_CompleteMatch: {
2689 // The match has been completed, and any new nodes (if any) have been
2690 // created. Patch up references to the matched dag to use the newly
2692 unsigned NumResults = MatcherTable[MatcherIndex++];
2694 for (unsigned i = 0; i != NumResults; ++i) {
2695 unsigned ResSlot = MatcherTable[MatcherIndex++];
2697 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2699 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2700 SDValue Res = RecordedNodes[ResSlot].first;
2702 assert(i < NodeToMatch->getNumValues() &&
2703 NodeToMatch->getValueType(i) != MVT::Other &&
2704 NodeToMatch->getValueType(i) != MVT::Glue &&
2705 "Invalid number of results to complete!");
2706 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2707 NodeToMatch->getValueType(i) == MVT::iPTR ||
2708 Res.getValueType() == MVT::iPTR ||
2709 NodeToMatch->getValueType(i).getSizeInBits() ==
2710 Res.getValueType().getSizeInBits()) &&
2711 "invalid replacement");
2712 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2715 // If the root node defines glue, add it to the glue nodes to update list.
2716 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2717 GlueResultNodesMatched.push_back(NodeToMatch);
2719 // Update chain and glue uses.
2720 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2721 InputGlue, GlueResultNodesMatched, false);
2723 assert(NodeToMatch->use_empty() &&
2724 "Didn't replace all uses of the node?");
2726 // FIXME: We just return here, which interacts correctly with SelectRoot
2727 // above. We should fix this to not return an SDNode* anymore.
2732 // If the code reached this point, then the match failed. See if there is
2733 // another child to try in the current 'Scope', otherwise pop it until we
2734 // find a case to check.
2735 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2736 ++NumDAGIselRetries;
2738 if (MatchScopes.empty()) {
2739 CannotYetSelect(NodeToMatch);
2743 // Restore the interpreter state back to the point where the scope was
2745 MatchScope &LastScope = MatchScopes.back();
2746 RecordedNodes.resize(LastScope.NumRecordedNodes);
2748 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2749 N = NodeStack.back();
2751 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2752 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2753 MatcherIndex = LastScope.FailIndex;
2755 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2757 InputChain = LastScope.InputChain;
2758 InputGlue = LastScope.InputGlue;
2759 if (!LastScope.HasChainNodesMatched)
2760 ChainNodesMatched.clear();
2761 if (!LastScope.HasGlueResultNodesMatched)
2762 GlueResultNodesMatched.clear();
2764 // Check to see what the offset is at the new MatcherIndex. If it is zero
2765 // we have reached the end of this scope, otherwise we have another child
2766 // in the current scope to try.
2767 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2768 if (NumToSkip & 128)
2769 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2771 // If we have another child in this scope to match, update FailIndex and
2773 if (NumToSkip != 0) {
2774 LastScope.FailIndex = MatcherIndex+NumToSkip;
2778 // End of this scope, pop it and try the next child in the containing
2780 MatchScopes.pop_back();
2787 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2789 raw_string_ostream Msg(msg);
2790 Msg << "Cannot select: ";
2792 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2793 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2794 N->getOpcode() != ISD::INTRINSIC_VOID) {
2795 N->printrFull(Msg, CurDAG);
2797 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2799 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2800 if (iid < Intrinsic::num_intrinsics)
2801 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2802 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2803 Msg << "target intrinsic %" << TII->getName(iid);
2805 Msg << "unknown intrinsic #" << iid;
2807 report_fatal_error(Msg.str());
2810 char SelectionDAGISel::ID = 0;