1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/DebugInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetIntrinsicInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLowering.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/ADT/PostOrderIterator.h"
54 #include "llvm/ADT/Statistic.h"
58 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
59 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
60 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
61 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
62 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
65 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
66 cl::desc("Enable verbose messages in the \"fast\" "
67 "instruction selector"));
69 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
70 cl::desc("Enable abort calls when \"fast\" instruction fails"));
74 cl::desc("use Machine Branch Probability Info"),
75 cl::init(true), cl::Hidden);
79 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
80 cl::desc("Pop up a window to show dags before the first "
83 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize types"));
86 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before legalize"));
89 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
90 cl::desc("Pop up a window to show dags before the second "
93 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
94 cl::desc("Pop up a window to show dags before the post legalize types"
95 " dag combine pass"));
97 ViewISelDAGs("view-isel-dags", cl::Hidden,
98 cl::desc("Pop up a window to show isel dags as they are selected"));
100 ViewSchedDAGs("view-sched-dags", cl::Hidden,
101 cl::desc("Pop up a window to show sched dags as they are processed"));
103 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
104 cl::desc("Pop up a window to show SUnit dags after they are processed"));
106 static const bool ViewDAGCombine1 = false,
107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
108 ViewDAGCombine2 = false,
109 ViewDAGCombineLT = false,
110 ViewISelDAGs = false, ViewSchedDAGs = false,
111 ViewSUnitDAGs = false;
114 //===---------------------------------------------------------------------===//
116 /// RegisterScheduler class - Track the registration of instruction schedulers.
118 //===---------------------------------------------------------------------===//
119 MachinePassRegistry RegisterScheduler::Registry;
121 //===---------------------------------------------------------------------===//
123 /// ISHeuristic command line option for instruction schedulers.
125 //===---------------------------------------------------------------------===//
126 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
127 RegisterPassParser<RegisterScheduler> >
128 ISHeuristic("pre-RA-sched",
129 cl::init(&createDefaultScheduler),
130 cl::desc("Instruction schedulers available (before register"
133 static RegisterScheduler
134 defaultListDAGScheduler("default", "Best scheduler for the target",
135 createDefaultScheduler);
138 //===--------------------------------------------------------------------===//
139 /// createDefaultScheduler - This creates an instruction scheduler appropriate
141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
142 CodeGenOpt::Level OptLevel) {
143 const TargetLowering &TLI = IS->getTargetLowering();
145 if (OptLevel == CodeGenOpt::None)
146 return createSourceListDAGScheduler(IS, OptLevel);
147 if (TLI.getSchedulingPreference() == Sched::RegPressure)
148 return createBURRListDAGScheduler(IS, OptLevel);
149 if (TLI.getSchedulingPreference() == Sched::Hybrid)
150 return createHybridListDAGScheduler(IS, OptLevel);
151 assert(TLI.getSchedulingPreference() == Sched::ILP &&
152 "Unknown sched type!");
153 return createILPListDAGScheduler(IS, OptLevel);
157 // EmitInstrWithCustomInserter - This method should be implemented by targets
158 // that mark instructions with the 'usesCustomInserter' flag. These
159 // instructions are special in various ways, which require special support to
160 // insert. The specified MachineInstr is created but not inserted into any
161 // basic blocks, and this method is called to expand it into a sequence of
162 // instructions, potentially also creating new basic blocks and control flow.
163 // When new basic blocks are inserted and the edges from MBB to its successors
164 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
167 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
168 MachineBasicBlock *MBB) const {
170 dbgs() << "If a target marks an instruction with "
171 "'usesCustomInserter', it must implement "
172 "TargetLowering::EmitInstrWithCustomInserter!";
178 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
179 SDNode *Node) const {
180 assert(!MI->getDesc().hasPostISelHook() &&
181 "If a target marks an instruction with 'hasPostISelHook', "
182 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
185 //===----------------------------------------------------------------------===//
186 // SelectionDAGISel code
187 //===----------------------------------------------------------------------===//
189 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
190 CodeGenOpt::Level OL) :
191 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
192 FuncInfo(new FunctionLoweringInfo(TLI)),
193 CurDAG(new SelectionDAG(tm)),
194 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
198 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
199 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
200 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
203 SelectionDAGISel::~SelectionDAGISel() {
209 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
210 AU.addRequired<AliasAnalysis>();
211 AU.addPreserved<AliasAnalysis>();
212 AU.addRequired<GCModuleInfo>();
213 AU.addPreserved<GCModuleInfo>();
214 if (UseMBPI && OptLevel != CodeGenOpt::None)
215 AU.addRequired<BranchProbabilityInfo>();
216 MachineFunctionPass::getAnalysisUsage(AU);
219 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
220 /// may trap on it. In this case we have to split the edge so that the path
221 /// through the predecessor block that doesn't go to the phi block doesn't
222 /// execute the possibly trapping instruction.
224 /// This is required for correctness, so it must be done at -O0.
226 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
227 // Loop for blocks with phi nodes.
228 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
229 PHINode *PN = dyn_cast<PHINode>(BB->begin());
230 if (PN == 0) continue;
233 // For each block with a PHI node, check to see if any of the input values
234 // are potentially trapping constant expressions. Constant expressions are
235 // the only potentially trapping value that can occur as the argument to a
237 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
238 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
239 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
240 if (CE == 0 || !CE->canTrap()) continue;
242 // The only case we have to worry about is when the edge is critical.
243 // Since this block has a PHI Node, we assume it has multiple input
244 // edges: check to see if the pred has multiple successors.
245 BasicBlock *Pred = PN->getIncomingBlock(i);
246 if (Pred->getTerminator()->getNumSuccessors() == 1)
249 // Okay, we have to split this edge.
250 SplitCriticalEdge(Pred->getTerminator(),
251 GetSuccessorNumber(Pred, BB), SDISel, true);
257 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
258 // Do some sanity-checking on the command-line options.
259 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
260 "-fast-isel-verbose requires -fast-isel");
261 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
262 "-fast-isel-abort requires -fast-isel");
264 const Function &Fn = *mf.getFunction();
265 const TargetInstrInfo &TII = *TM.getInstrInfo();
266 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
269 RegInfo = &MF->getRegInfo();
270 AA = &getAnalysis<AliasAnalysis>();
271 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
273 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
275 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
278 FuncInfo->set(Fn, *MF);
280 if (UseMBPI && OptLevel != CodeGenOpt::None)
281 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
287 SelectAllBasicBlocks(Fn);
289 // If the first basic block in the function has live ins that need to be
290 // copied into vregs, emit the copies into the top of the block before
291 // emitting the code for the block.
292 MachineBasicBlock *EntryMBB = MF->begin();
293 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
295 DenseMap<unsigned, unsigned> LiveInMap;
296 if (!FuncInfo->ArgDbgValues.empty())
297 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
298 E = RegInfo->livein_end(); LI != E; ++LI)
300 LiveInMap.insert(std::make_pair(LI->first, LI->second));
302 // Insert DBG_VALUE instructions for function arguments to the entry block.
303 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
304 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
305 unsigned Reg = MI->getOperand(0).getReg();
306 if (TargetRegisterInfo::isPhysicalRegister(Reg))
307 EntryMBB->insert(EntryMBB->begin(), MI);
309 MachineInstr *Def = RegInfo->getVRegDef(Reg);
310 MachineBasicBlock::iterator InsertPos = Def;
311 // FIXME: VR def may not be in entry block.
312 Def->getParent()->insert(llvm::next(InsertPos), MI);
315 // If Reg is live-in then update debug info to track its copy in a vreg.
316 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
317 if (LDI != LiveInMap.end()) {
318 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
319 MachineBasicBlock::iterator InsertPos = Def;
320 const MDNode *Variable =
321 MI->getOperand(MI->getNumOperands()-1).getMetadata();
322 unsigned Offset = MI->getOperand(1).getImm();
323 // Def is never a terminator here, so it is ok to increment InsertPos.
324 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
325 TII.get(TargetOpcode::DBG_VALUE))
326 .addReg(LDI->second, RegState::Debug)
327 .addImm(Offset).addMetadata(Variable);
329 // If this vreg is directly copied into an exported register then
330 // that COPY instructions also need DBG_VALUE, if it is the only
331 // user of LDI->second.
332 MachineInstr *CopyUseMI = NULL;
333 for (MachineRegisterInfo::use_iterator
334 UI = RegInfo->use_begin(LDI->second);
335 MachineInstr *UseMI = UI.skipInstruction();) {
336 if (UseMI->isDebugValue()) continue;
337 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
338 CopyUseMI = UseMI; continue;
340 // Otherwise this is another use or second copy use.
341 CopyUseMI = NULL; break;
344 MachineInstr *NewMI =
345 BuildMI(*MF, CopyUseMI->getDebugLoc(),
346 TII.get(TargetOpcode::DBG_VALUE))
347 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
348 .addImm(Offset).addMetadata(Variable);
349 MachineBasicBlock::iterator Pos = CopyUseMI;
350 EntryMBB->insertAfter(Pos, NewMI);
355 // Determine if there are any calls in this machine function.
356 MachineFrameInfo *MFI = MF->getFrameInfo();
357 if (!MFI->hasCalls()) {
358 for (MachineFunction::const_iterator
359 I = MF->begin(), E = MF->end(); I != E; ++I) {
360 const MachineBasicBlock *MBB = I;
361 for (MachineBasicBlock::const_iterator
362 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
363 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
365 if ((MCID.isCall() && !MCID.isReturn()) ||
366 II->isStackAligningInlineAsm()) {
367 MFI->setHasCalls(true);
375 // Determine if there is a call to setjmp in the machine function.
376 MF->setCallsSetJmp(Fn.callsFunctionThatReturnsTwice());
378 // Replace forward-declared registers with the registers containing
379 // the desired value.
380 MachineRegisterInfo &MRI = MF->getRegInfo();
381 for (DenseMap<unsigned, unsigned>::iterator
382 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
384 unsigned From = I->first;
385 unsigned To = I->second;
386 // If To is also scheduled to be replaced, find what its ultimate
389 DenseMap<unsigned, unsigned>::iterator J =
390 FuncInfo->RegFixups.find(To);
395 MRI.replaceRegWith(From, To);
398 // Release function-specific state. SDB and CurDAG are already cleared
405 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
406 BasicBlock::const_iterator End,
408 // Lower all of the non-terminator instructions. If a call is emitted
409 // as a tail call, cease emitting nodes for this block. Terminators
410 // are handled below.
411 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
414 // Make sure the root of the DAG is up-to-date.
415 CurDAG->setRoot(SDB->getControlRoot());
416 HadTailCall = SDB->HasTailCall;
419 // Final step, emit the lowered DAG as machine code.
423 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
424 SmallPtrSet<SDNode*, 128> VisitedNodes;
425 SmallVector<SDNode*, 128> Worklist;
427 Worklist.push_back(CurDAG->getRoot().getNode());
434 SDNode *N = Worklist.pop_back_val();
436 // If we've already seen this node, ignore it.
437 if (!VisitedNodes.insert(N))
440 // Otherwise, add all chain operands to the worklist.
441 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
442 if (N->getOperand(i).getValueType() == MVT::Other)
443 Worklist.push_back(N->getOperand(i).getNode());
445 // If this is a CopyToReg with a vreg dest, process it.
446 if (N->getOpcode() != ISD::CopyToReg)
449 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
450 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
453 // Ignore non-scalar or non-integer values.
454 SDValue Src = N->getOperand(2);
455 EVT SrcVT = Src.getValueType();
456 if (!SrcVT.isInteger() || SrcVT.isVector())
459 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
460 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
461 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
462 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
463 } while (!Worklist.empty());
466 void SelectionDAGISel::CodeGenAndEmitDAG() {
467 std::string GroupName;
468 if (TimePassesIsEnabled)
469 GroupName = "Instruction Selection and Scheduling";
470 std::string BlockName;
471 int BlockNumber = -1;
474 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
475 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
479 BlockNumber = FuncInfo->MBB->getNumber();
480 BlockName = MF->getFunction()->getName().str() + ":" +
481 FuncInfo->MBB->getBasicBlock()->getName().str();
483 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
484 << " '" << BlockName << "'\n"; CurDAG->dump());
486 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
488 // Run the DAG combiner in pre-legalize mode.
490 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
491 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
494 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
495 << " '" << BlockName << "'\n"; CurDAG->dump());
497 // Second step, hack on the DAG until it only uses operations and types that
498 // the target supports.
499 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
504 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
505 Changed = CurDAG->LegalizeTypes();
508 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
509 << " '" << BlockName << "'\n"; CurDAG->dump());
512 if (ViewDAGCombineLT)
513 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
515 // Run the DAG combiner in post-type-legalize mode.
517 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
518 TimePassesIsEnabled);
519 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
522 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
523 << " '" << BlockName << "'\n"; CurDAG->dump());
527 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
528 Changed = CurDAG->LegalizeVectors();
533 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
534 CurDAG->LegalizeTypes();
537 if (ViewDAGCombineLT)
538 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
540 // Run the DAG combiner in post-type-legalize mode.
542 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
543 TimePassesIsEnabled);
544 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
547 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
548 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
551 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
554 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
558 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
559 << " '" << BlockName << "'\n"; CurDAG->dump());
561 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
563 // Run the DAG combiner in post-legalize mode.
565 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
566 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
569 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
570 << " '" << BlockName << "'\n"; CurDAG->dump());
572 if (OptLevel != CodeGenOpt::None)
573 ComputeLiveOutVRegInfo();
575 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
577 // Third, instruction select all of the operations to machine code, adding the
578 // code to the MachineBasicBlock.
580 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
581 DoInstructionSelection();
584 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
585 << " '" << BlockName << "'\n"; CurDAG->dump());
587 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
589 // Schedule machine code.
590 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
592 NamedRegionTimer T("Instruction Scheduling", GroupName,
593 TimePassesIsEnabled);
594 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
597 if (ViewSUnitDAGs) Scheduler->viewGraph();
599 // Emit machine code to BB. This can change 'BB' to the last block being
601 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
603 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
605 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
606 FuncInfo->InsertPt = Scheduler->InsertPos;
609 // If the block was split, make sure we update any references that are used to
610 // update PHI nodes later on.
611 if (FirstMBB != LastMBB)
612 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
614 // Free the scheduler state.
616 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
617 TimePassesIsEnabled);
621 // Free the SelectionDAG state, now that we're finished with it.
625 void SelectionDAGISel::DoInstructionSelection() {
626 DEBUG(errs() << "===== Instruction selection begins: BB#"
627 << FuncInfo->MBB->getNumber()
628 << " '" << FuncInfo->MBB->getName() << "'\n");
632 // Select target instructions for the DAG.
634 // Number all nodes with a topological order and set DAGSize.
635 DAGSize = CurDAG->AssignTopologicalOrder();
637 // Create a dummy node (which is not added to allnodes), that adds
638 // a reference to the root node, preventing it from being deleted,
639 // and tracking any changes of the root.
640 HandleSDNode Dummy(CurDAG->getRoot());
641 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
644 // The AllNodes list is now topological-sorted. Visit the
645 // nodes by starting at the end of the list (the root of the
646 // graph) and preceding back toward the beginning (the entry
648 while (ISelPosition != CurDAG->allnodes_begin()) {
649 SDNode *Node = --ISelPosition;
650 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
651 // but there are currently some corner cases that it misses. Also, this
652 // makes it theoretically possible to disable the DAGCombiner.
653 if (Node->use_empty())
656 SDNode *ResNode = Select(Node);
658 // FIXME: This is pretty gross. 'Select' should be changed to not return
659 // anything at all and this code should be nuked with a tactical strike.
661 // If node should not be replaced, continue with the next one.
662 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
666 ReplaceUses(Node, ResNode);
668 // If after the replacement this node is not used any more,
669 // remove this dead node.
670 if (Node->use_empty()) { // Don't delete EntryToken, etc.
671 ISelUpdater ISU(ISelPosition);
672 CurDAG->RemoveDeadNode(Node, &ISU);
676 CurDAG->setRoot(Dummy.getValue());
679 DEBUG(errs() << "===== Instruction selection ends:\n");
681 PostprocessISelDAG();
684 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
685 /// do other setup for EH landing-pad blocks.
686 void SelectionDAGISel::PrepareEHLandingPad() {
687 MachineBasicBlock *MBB = FuncInfo->MBB;
689 // Add a label to mark the beginning of the landing pad. Deletion of the
690 // landing pad can thus be detected via the MachineModuleInfo.
691 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
693 // Assign the call site to the landing pad's begin label.
694 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
696 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
697 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
700 // Mark exception register as live in.
701 unsigned Reg = TLI.getExceptionAddressRegister();
702 if (Reg) MBB->addLiveIn(Reg);
704 // Mark exception selector register as live in.
705 Reg = TLI.getExceptionSelectorRegister();
706 if (Reg) MBB->addLiveIn(Reg);
708 // FIXME: Hack around an exception handling flaw (PR1508): the personality
709 // function and list of typeids logically belong to the invoke (or, if you
710 // like, the basic block containing the invoke), and need to be associated
711 // with it in the dwarf exception handling tables. Currently however the
712 // information is provided by an intrinsic (eh.selector) that can be moved
713 // to unexpected places by the optimizers: if the unwind edge is critical,
714 // then breaking it can result in the intrinsics being in the successor of
715 // the landing pad, not the landing pad itself. This results
716 // in exceptions not being caught because no typeids are associated with
717 // the invoke. This may not be the only way things can go wrong, but it
718 // is the only way we try to work around for the moment.
719 const BasicBlock *LLVMBB = MBB->getBasicBlock();
720 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
722 if (Br && Br->isUnconditional()) { // Critical edge?
723 BasicBlock::const_iterator I, E;
724 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
725 if (isa<EHSelectorInst>(I))
729 // No catch info found - try to extract some from the successor.
730 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
734 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
735 /// load into the specified FoldInst. Note that we could have a sequence where
736 /// multiple LLVM IR instructions are folded into the same machineinstr. For
737 /// example we could have:
738 /// A: x = load i32 *P
739 /// B: y = icmp A, 42
742 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
743 /// any other folded instructions) because it is between A and C.
745 /// If we succeed in folding the load into the operation, return true.
747 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
748 const Instruction *FoldInst,
750 // We know that the load has a single use, but don't know what it is. If it
751 // isn't one of the folded instructions, then we can't succeed here. Handle
752 // this by scanning the single-use users of the load until we get to FoldInst.
753 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
755 const Instruction *TheUser = LI->use_back();
756 while (TheUser != FoldInst && // Scan up until we find FoldInst.
757 // Stay in the right block.
758 TheUser->getParent() == FoldInst->getParent() &&
759 --MaxUsers) { // Don't scan too far.
760 // If there are multiple or no uses of this instruction, then bail out.
761 if (!TheUser->hasOneUse())
764 TheUser = TheUser->use_back();
767 // If we didn't find the fold instruction, then we failed to collapse the
769 if (TheUser != FoldInst)
772 // Don't try to fold volatile loads. Target has to deal with alignment
774 if (LI->isVolatile()) return false;
776 // Figure out which vreg this is going into. If there is no assigned vreg yet
777 // then there actually was no reference to it. Perhaps the load is referenced
778 // by a dead instruction.
779 unsigned LoadReg = FastIS->getRegForValue(LI);
783 // Check to see what the uses of this vreg are. If it has no uses, or more
784 // than one use (at the machine instr level) then we can't fold it.
785 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
786 if (RI == RegInfo->reg_end())
789 // See if there is exactly one use of the vreg. If there are multiple uses,
790 // then the instruction got lowered to multiple machine instructions or the
791 // use of the loaded value ended up being multiple operands of the result, in
792 // either case, we can't fold this.
793 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
794 if (PostRI != RegInfo->reg_end())
797 assert(RI.getOperand().isUse() &&
798 "The only use of the vreg must be a use, we haven't emitted the def!");
800 MachineInstr *User = &*RI;
802 // Set the insertion point properly. Folding the load can cause generation of
803 // other random instructions (like sign extends) for addressing modes, make
804 // sure they get inserted in a logical place before the new instruction.
805 FuncInfo->InsertPt = User;
806 FuncInfo->MBB = User->getParent();
808 // Ask the target to try folding the load.
809 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
812 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
813 /// side-effect free and is either dead or folded into a generated instruction.
814 /// Return false if it needs to be emitted.
815 static bool isFoldedOrDeadInstruction(const Instruction *I,
816 FunctionLoweringInfo *FuncInfo) {
817 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
818 !isa<TerminatorInst>(I) && // Terminators aren't folded.
819 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
820 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
821 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
824 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
825 // Initialize the Fast-ISel state, if needed.
826 FastISel *FastIS = 0;
827 if (TM.Options.EnableFastISel)
828 FastIS = TLI.createFastISel(*FuncInfo);
830 // Iterate over all basic blocks in the function.
831 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
832 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
833 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
834 const BasicBlock *LLVMBB = *I;
836 if (OptLevel != CodeGenOpt::None) {
837 bool AllPredsVisited = true;
838 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
840 if (!FuncInfo->VisitedBBs.count(*PI)) {
841 AllPredsVisited = false;
846 if (AllPredsVisited) {
847 for (BasicBlock::const_iterator I = LLVMBB->begin();
848 isa<PHINode>(I); ++I)
849 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
851 for (BasicBlock::const_iterator I = LLVMBB->begin();
852 isa<PHINode>(I); ++I)
853 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));
856 FuncInfo->VisitedBBs.insert(LLVMBB);
859 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
860 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
862 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
863 BasicBlock::const_iterator const End = LLVMBB->end();
864 BasicBlock::const_iterator BI = End;
866 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
868 // Setup an EH landing-pad block.
869 if (FuncInfo->MBB->isLandingPad())
870 PrepareEHLandingPad();
872 // Lower any arguments needed in this block if this is the entry block.
873 if (LLVMBB == &Fn.getEntryBlock())
874 LowerArguments(LLVMBB);
876 // Before doing SelectionDAG ISel, see if FastISel has been requested.
878 FastIS->startNewBlock();
880 // Emit code for any incoming arguments. This must happen before
881 // beginning FastISel on the entry block.
882 if (LLVMBB == &Fn.getEntryBlock()) {
883 CurDAG->setRoot(SDB->getControlRoot());
887 // If we inserted any instructions at the beginning, make a note of
888 // where they are, so we can be sure to emit subsequent instructions
890 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
891 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
893 FastIS->setLastLocalValue(0);
896 unsigned NumFastIselRemaining = std::distance(Begin, End);
897 // Do FastISel on as many instructions as possible.
898 for (; BI != Begin; --BI) {
899 const Instruction *Inst = llvm::prior(BI);
901 // If we no longer require this instruction, skip it.
902 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
903 --NumFastIselRemaining;
907 // Bottom-up: reset the insert pos at the top, after any local-value
909 FastIS->recomputeInsertPt();
911 // Try to select the instruction with FastISel.
912 if (FastIS->SelectInstruction(Inst)) {
913 --NumFastIselRemaining;
914 ++NumFastIselSuccess;
915 // If fast isel succeeded, skip over all the folded instructions, and
916 // then see if there is a load right before the selected instructions.
917 // Try to fold the load if so.
918 const Instruction *BeforeInst = Inst;
919 while (BeforeInst != Begin) {
920 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
921 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
924 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
925 BeforeInst->hasOneUse() &&
926 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
927 // If we succeeded, don't re-select the load.
928 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
929 --NumFastIselRemaining;
930 ++NumFastIselSuccess;
935 // Then handle certain instructions as single-LLVM-Instruction blocks.
936 if (isa<CallInst>(Inst)) {
938 if (EnableFastISelVerbose || EnableFastISelAbort) {
939 dbgs() << "FastISel missed call: ";
943 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
944 unsigned &R = FuncInfo->ValueMap[Inst];
946 R = FuncInfo->CreateRegs(Inst->getType());
949 bool HadTailCall = false;
950 SelectBasicBlock(Inst, BI, HadTailCall);
952 // Recompute NumFastIselRemaining as Selection DAG instruction
953 // selection may have handled the call, input args, etc.
954 unsigned RemainingNow = std::distance(Begin, BI);
955 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
957 // If the call was emitted as a tail call, we're done with the block.
963 NumFastIselRemaining = RemainingNow;
967 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
968 // Don't abort, and use a different message for terminator misses.
969 NumFastIselFailures += NumFastIselRemaining;
970 if (EnableFastISelVerbose || EnableFastISelAbort) {
971 dbgs() << "FastISel missed terminator: ";
975 NumFastIselFailures += NumFastIselRemaining;
976 if (EnableFastISelVerbose || EnableFastISelAbort) {
977 dbgs() << "FastISel miss: ";
980 if (EnableFastISelAbort)
981 // The "fast" selector couldn't handle something and bailed.
982 // For the purpose of debugging, just abort.
983 llvm_unreachable("FastISel didn't select the entire block");
988 FastIS->recomputeInsertPt();
997 // Run SelectionDAG instruction selection on the remainder of the block
998 // not handled by FastISel. If FastISel is not run, this is the entire
1001 SelectBasicBlock(Begin, BI, HadTailCall);
1005 FuncInfo->PHINodesToUpdate.clear();
1009 SDB->clearDanglingDebugInfo();
1013 SelectionDAGISel::FinishBasicBlock() {
1015 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1016 << FuncInfo->PHINodesToUpdate.size() << "\n";
1017 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1018 dbgs() << "Node " << i << " : ("
1019 << FuncInfo->PHINodesToUpdate[i].first
1020 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1022 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1023 // PHI nodes in successors.
1024 if (SDB->SwitchCases.empty() &&
1025 SDB->JTCases.empty() &&
1026 SDB->BitTestCases.empty()) {
1027 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1028 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1029 assert(PHI->isPHI() &&
1030 "This is not a machine PHI node that we are updating!");
1031 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1034 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1035 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1040 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1041 // Lower header first, if it wasn't already lowered
1042 if (!SDB->BitTestCases[i].Emitted) {
1043 // Set the current basic block to the mbb we wish to insert the code into
1044 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1045 FuncInfo->InsertPt = FuncInfo->MBB->end();
1047 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1048 CurDAG->setRoot(SDB->getRoot());
1050 CodeGenAndEmitDAG();
1053 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1054 // Set the current basic block to the mbb we wish to insert the code into
1055 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1056 FuncInfo->InsertPt = FuncInfo->MBB->end();
1059 SDB->visitBitTestCase(SDB->BitTestCases[i],
1060 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1061 SDB->BitTestCases[i].Reg,
1062 SDB->BitTestCases[i].Cases[j],
1065 SDB->visitBitTestCase(SDB->BitTestCases[i],
1066 SDB->BitTestCases[i].Default,
1067 SDB->BitTestCases[i].Reg,
1068 SDB->BitTestCases[i].Cases[j],
1072 CurDAG->setRoot(SDB->getRoot());
1074 CodeGenAndEmitDAG();
1078 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1080 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1081 MachineBasicBlock *PHIBB = PHI->getParent();
1082 assert(PHI->isPHI() &&
1083 "This is not a machine PHI node that we are updating!");
1084 // This is "default" BB. We have two jumps to it. From "header" BB and
1085 // from last "case" BB.
1086 if (PHIBB == SDB->BitTestCases[i].Default) {
1087 PHI->addOperand(MachineOperand::
1088 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1090 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1091 PHI->addOperand(MachineOperand::
1092 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1094 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1097 // One of "cases" BB.
1098 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1100 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1101 if (cBB->isSuccessor(PHIBB)) {
1102 PHI->addOperand(MachineOperand::
1103 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1105 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1110 SDB->BitTestCases.clear();
1112 // If the JumpTable record is filled in, then we need to emit a jump table.
1113 // Updating the PHI nodes is tricky in this case, since we need to determine
1114 // whether the PHI is a successor of the range check MBB or the jump table MBB
1115 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1116 // Lower header first, if it wasn't already lowered
1117 if (!SDB->JTCases[i].first.Emitted) {
1118 // Set the current basic block to the mbb we wish to insert the code into
1119 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1120 FuncInfo->InsertPt = FuncInfo->MBB->end();
1122 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1124 CurDAG->setRoot(SDB->getRoot());
1126 CodeGenAndEmitDAG();
1129 // Set the current basic block to the mbb we wish to insert the code into
1130 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1131 FuncInfo->InsertPt = FuncInfo->MBB->end();
1133 SDB->visitJumpTable(SDB->JTCases[i].second);
1134 CurDAG->setRoot(SDB->getRoot());
1136 CodeGenAndEmitDAG();
1139 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1141 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1142 MachineBasicBlock *PHIBB = PHI->getParent();
1143 assert(PHI->isPHI() &&
1144 "This is not a machine PHI node that we are updating!");
1145 // "default" BB. We can go there only from header BB.
1146 if (PHIBB == SDB->JTCases[i].second.Default) {
1148 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1151 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1153 // JT BB. Just iterate over successors here
1154 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1156 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1158 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1162 SDB->JTCases.clear();
1164 // If the switch block involved a branch to one of the actual successors, we
1165 // need to update PHI nodes in that block.
1166 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1167 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1168 assert(PHI->isPHI() &&
1169 "This is not a machine PHI node that we are updating!");
1170 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1172 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1173 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1177 // If we generated any switch lowering information, build and codegen any
1178 // additional DAGs necessary.
1179 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1180 // Set the current basic block to the mbb we wish to insert the code into
1181 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1182 FuncInfo->InsertPt = FuncInfo->MBB->end();
1184 // Determine the unique successors.
1185 SmallVector<MachineBasicBlock *, 2> Succs;
1186 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1187 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1188 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1190 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1191 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1192 CurDAG->setRoot(SDB->getRoot());
1194 CodeGenAndEmitDAG();
1196 // Remember the last block, now that any splitting is done, for use in
1197 // populating PHI nodes in successors.
1198 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1200 // Handle any PHI nodes in successors of this chunk, as if we were coming
1201 // from the original BB before switch expansion. Note that PHI nodes can
1202 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1203 // handle them the right number of times.
1204 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1205 FuncInfo->MBB = Succs[i];
1206 FuncInfo->InsertPt = FuncInfo->MBB->end();
1207 // FuncInfo->MBB may have been removed from the CFG if a branch was
1209 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1210 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1211 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1213 // This value for this PHI node is recorded in PHINodesToUpdate.
1214 for (unsigned pn = 0; ; ++pn) {
1215 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1216 "Didn't find PHI entry!");
1217 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1218 Phi->addOperand(MachineOperand::
1219 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1221 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1229 SDB->SwitchCases.clear();
1233 /// Create the scheduler. If a specific scheduler was specified
1234 /// via the SchedulerRegistry, use it, otherwise select the
1235 /// one preferred by the target.
1237 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1238 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1242 RegisterScheduler::setDefault(Ctor);
1245 return Ctor(this, OptLevel);
1248 //===----------------------------------------------------------------------===//
1249 // Helper functions used by the generated instruction selector.
1250 //===----------------------------------------------------------------------===//
1251 // Calls to these methods are generated by tblgen.
1253 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1254 /// the dag combiner simplified the 255, we still want to match. RHS is the
1255 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1256 /// specified in the .td file (e.g. 255).
1257 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1258 int64_t DesiredMaskS) const {
1259 const APInt &ActualMask = RHS->getAPIntValue();
1260 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1262 // If the actual mask exactly matches, success!
1263 if (ActualMask == DesiredMask)
1266 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1267 if (ActualMask.intersects(~DesiredMask))
1270 // Otherwise, the DAG Combiner may have proven that the value coming in is
1271 // either already zero or is not demanded. Check for known zero input bits.
1272 APInt NeededMask = DesiredMask & ~ActualMask;
1273 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1276 // TODO: check to see if missing bits are just not demanded.
1278 // Otherwise, this pattern doesn't match.
1282 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1283 /// the dag combiner simplified the 255, we still want to match. RHS is the
1284 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1285 /// specified in the .td file (e.g. 255).
1286 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1287 int64_t DesiredMaskS) const {
1288 const APInt &ActualMask = RHS->getAPIntValue();
1289 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1291 // If the actual mask exactly matches, success!
1292 if (ActualMask == DesiredMask)
1295 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1296 if (ActualMask.intersects(~DesiredMask))
1299 // Otherwise, the DAG Combiner may have proven that the value coming in is
1300 // either already zero or is not demanded. Check for known zero input bits.
1301 APInt NeededMask = DesiredMask & ~ActualMask;
1303 APInt KnownZero, KnownOne;
1304 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1306 // If all the missing bits in the or are already known to be set, match!
1307 if ((NeededMask & KnownOne) == NeededMask)
1310 // TODO: check to see if missing bits are just not demanded.
1312 // Otherwise, this pattern doesn't match.
1317 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1318 /// by tblgen. Others should not call it.
1319 void SelectionDAGISel::
1320 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1321 std::vector<SDValue> InOps;
1322 std::swap(InOps, Ops);
1324 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1325 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1326 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1327 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1329 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1330 if (InOps[e-1].getValueType() == MVT::Glue)
1331 --e; // Don't process a glue operand if it is here.
1334 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1335 if (!InlineAsm::isMemKind(Flags)) {
1336 // Just skip over this operand, copying the operands verbatim.
1337 Ops.insert(Ops.end(), InOps.begin()+i,
1338 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1339 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1341 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1342 "Memory operand with multiple values?");
1343 // Otherwise, this is a memory operand. Ask the target to select it.
1344 std::vector<SDValue> SelOps;
1345 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1346 report_fatal_error("Could not match memory address. Inline asm"
1349 // Add this to the output node.
1351 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1352 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1353 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1358 // Add the glue input back if present.
1359 if (e != InOps.size())
1360 Ops.push_back(InOps.back());
1363 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1366 static SDNode *findGlueUse(SDNode *N) {
1367 unsigned FlagResNo = N->getNumValues()-1;
1368 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1369 SDUse &Use = I.getUse();
1370 if (Use.getResNo() == FlagResNo)
1371 return Use.getUser();
1376 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1377 /// This function recursively traverses up the operand chain, ignoring
1379 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1380 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1381 bool IgnoreChains) {
1382 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1383 // greater than all of its (recursive) operands. If we scan to a point where
1384 // 'use' is smaller than the node we're scanning for, then we know we will
1387 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1388 // happen because we scan down to newly selected nodes in the case of glue
1390 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1393 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1394 // won't fail if we scan it again.
1395 if (!Visited.insert(Use))
1398 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1399 // Ignore chain uses, they are validated by HandleMergeInputChains.
1400 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1403 SDNode *N = Use->getOperand(i).getNode();
1405 if (Use == ImmedUse || Use == Root)
1406 continue; // We are not looking for immediate use.
1411 // Traverse up the operand chain.
1412 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1418 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1419 /// operand node N of U during instruction selection that starts at Root.
1420 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1421 SDNode *Root) const {
1422 if (OptLevel == CodeGenOpt::None) return false;
1423 return N.hasOneUse();
1426 /// IsLegalToFold - Returns true if the specific operand node N of
1427 /// U can be folded during instruction selection that starts at Root.
1428 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1429 CodeGenOpt::Level OptLevel,
1430 bool IgnoreChains) {
1431 if (OptLevel == CodeGenOpt::None) return false;
1433 // If Root use can somehow reach N through a path that that doesn't contain
1434 // U then folding N would create a cycle. e.g. In the following
1435 // diagram, Root can reach N through X. If N is folded into into Root, then
1436 // X is both a predecessor and a successor of U.
1447 // * indicates nodes to be folded together.
1449 // If Root produces glue, then it gets (even more) interesting. Since it
1450 // will be "glued" together with its glue use in the scheduler, we need to
1451 // check if it might reach N.
1470 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1471 // (call it Fold), then X is a predecessor of GU and a successor of
1472 // Fold. But since Fold and GU are glued together, this will create
1473 // a cycle in the scheduling graph.
1475 // If the node has glue, walk down the graph to the "lowest" node in the
1477 EVT VT = Root->getValueType(Root->getNumValues()-1);
1478 while (VT == MVT::Glue) {
1479 SDNode *GU = findGlueUse(Root);
1483 VT = Root->getValueType(Root->getNumValues()-1);
1485 // If our query node has a glue result with a use, we've walked up it. If
1486 // the user (which has already been selected) has a chain or indirectly uses
1487 // the chain, our WalkChainUsers predicate will not consider it. Because of
1488 // this, we cannot ignore chains in this predicate.
1489 IgnoreChains = false;
1493 SmallPtrSet<SDNode*, 16> Visited;
1494 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1497 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1498 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1499 SelectInlineAsmMemoryOperands(Ops);
1501 std::vector<EVT> VTs;
1502 VTs.push_back(MVT::Other);
1503 VTs.push_back(MVT::Glue);
1504 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1505 VTs, &Ops[0], Ops.size());
1507 return New.getNode();
1510 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1511 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1514 /// GetVBR - decode a vbr encoding whose top bit is set.
1515 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1516 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1517 assert(Val >= 128 && "Not a VBR");
1518 Val &= 127; // Remove first vbr bit.
1523 NextBits = MatcherTable[Idx++];
1524 Val |= (NextBits&127) << Shift;
1526 } while (NextBits & 128);
1532 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1533 /// interior glue and chain results to use the new glue and chain results.
1534 void SelectionDAGISel::
1535 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1536 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1538 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1539 bool isMorphNodeTo) {
1540 SmallVector<SDNode*, 4> NowDeadNodes;
1542 ISelUpdater ISU(ISelPosition);
1544 // Now that all the normal results are replaced, we replace the chain and
1545 // glue results if present.
1546 if (!ChainNodesMatched.empty()) {
1547 assert(InputChain.getNode() != 0 &&
1548 "Matched input chains but didn't produce a chain");
1549 // Loop over all of the nodes we matched that produced a chain result.
1550 // Replace all the chain results with the final chain we ended up with.
1551 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1552 SDNode *ChainNode = ChainNodesMatched[i];
1554 // If this node was already deleted, don't look at it.
1555 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1558 // Don't replace the results of the root node if we're doing a
1560 if (ChainNode == NodeToMatch && isMorphNodeTo)
1563 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1564 if (ChainVal.getValueType() == MVT::Glue)
1565 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1566 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1567 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1569 // If the node became dead and we haven't already seen it, delete it.
1570 if (ChainNode->use_empty() &&
1571 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1572 NowDeadNodes.push_back(ChainNode);
1576 // If the result produces glue, update any glue results in the matched
1577 // pattern with the glue result.
1578 if (InputGlue.getNode() != 0) {
1579 // Handle any interior nodes explicitly marked.
1580 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1581 SDNode *FRN = GlueResultNodesMatched[i];
1583 // If this node was already deleted, don't look at it.
1584 if (FRN->getOpcode() == ISD::DELETED_NODE)
1587 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1588 "Doesn't have a glue result");
1589 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1592 // If the node became dead and we haven't already seen it, delete it.
1593 if (FRN->use_empty() &&
1594 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1595 NowDeadNodes.push_back(FRN);
1599 if (!NowDeadNodes.empty())
1600 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1602 DEBUG(errs() << "ISEL: Match complete!\n");
1608 CR_LeadsToInteriorNode
1611 /// WalkChainUsers - Walk down the users of the specified chained node that is
1612 /// part of the pattern we're matching, looking at all of the users we find.
1613 /// This determines whether something is an interior node, whether we have a
1614 /// non-pattern node in between two pattern nodes (which prevent folding because
1615 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1616 /// between pattern nodes (in which case the TF becomes part of the pattern).
1618 /// The walk we do here is guaranteed to be small because we quickly get down to
1619 /// already selected nodes "below" us.
1621 WalkChainUsers(SDNode *ChainedNode,
1622 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1623 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1624 ChainResult Result = CR_Simple;
1626 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1627 E = ChainedNode->use_end(); UI != E; ++UI) {
1628 // Make sure the use is of the chain, not some other value we produce.
1629 if (UI.getUse().getValueType() != MVT::Other) continue;
1633 // If we see an already-selected machine node, then we've gone beyond the
1634 // pattern that we're selecting down into the already selected chunk of the
1636 if (User->isMachineOpcode() ||
1637 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1640 if (User->getOpcode() == ISD::CopyToReg ||
1641 User->getOpcode() == ISD::CopyFromReg ||
1642 User->getOpcode() == ISD::INLINEASM ||
1643 User->getOpcode() == ISD::EH_LABEL) {
1644 // If their node ID got reset to -1 then they've already been selected.
1645 // Treat them like a MachineOpcode.
1646 if (User->getNodeId() == -1)
1650 // If we have a TokenFactor, we handle it specially.
1651 if (User->getOpcode() != ISD::TokenFactor) {
1652 // If the node isn't a token factor and isn't part of our pattern, then it
1653 // must be a random chained node in between two nodes we're selecting.
1654 // This happens when we have something like:
1659 // Because we structurally match the load/store as a read/modify/write,
1660 // but the call is chained between them. We cannot fold in this case
1661 // because it would induce a cycle in the graph.
1662 if (!std::count(ChainedNodesInPattern.begin(),
1663 ChainedNodesInPattern.end(), User))
1664 return CR_InducesCycle;
1666 // Otherwise we found a node that is part of our pattern. For example in:
1670 // This would happen when we're scanning down from the load and see the
1671 // store as a user. Record that there is a use of ChainedNode that is
1672 // part of the pattern and keep scanning uses.
1673 Result = CR_LeadsToInteriorNode;
1674 InteriorChainedNodes.push_back(User);
1678 // If we found a TokenFactor, there are two cases to consider: first if the
1679 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1680 // uses of the TF are in our pattern) we just want to ignore it. Second,
1681 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1687 // | \ DAG's like cheese
1690 // [TokenFactor] [Op]
1697 // In this case, the TokenFactor becomes part of our match and we rewrite it
1698 // as a new TokenFactor.
1700 // To distinguish these two cases, do a recursive walk down the uses.
1701 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1703 // If the uses of the TokenFactor are just already-selected nodes, ignore
1704 // it, it is "below" our pattern.
1706 case CR_InducesCycle:
1707 // If the uses of the TokenFactor lead to nodes that are not part of our
1708 // pattern that are not selected, folding would turn this into a cycle,
1710 return CR_InducesCycle;
1711 case CR_LeadsToInteriorNode:
1712 break; // Otherwise, keep processing.
1715 // Okay, we know we're in the interesting interior case. The TokenFactor
1716 // is now going to be considered part of the pattern so that we rewrite its
1717 // uses (it may have uses that are not part of the pattern) with the
1718 // ultimate chain result of the generated code. We will also add its chain
1719 // inputs as inputs to the ultimate TokenFactor we create.
1720 Result = CR_LeadsToInteriorNode;
1721 ChainedNodesInPattern.push_back(User);
1722 InteriorChainedNodes.push_back(User);
1729 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1730 /// operation for when the pattern matched at least one node with a chains. The
1731 /// input vector contains a list of all of the chained nodes that we match. We
1732 /// must determine if this is a valid thing to cover (i.e. matching it won't
1733 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1734 /// be used as the input node chain for the generated nodes.
1736 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1737 SelectionDAG *CurDAG) {
1738 // Walk all of the chained nodes we've matched, recursively scanning down the
1739 // users of the chain result. This adds any TokenFactor nodes that are caught
1740 // in between chained nodes to the chained and interior nodes list.
1741 SmallVector<SDNode*, 3> InteriorChainedNodes;
1742 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1743 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1744 InteriorChainedNodes) == CR_InducesCycle)
1745 return SDValue(); // Would induce a cycle.
1748 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1749 // that we are interested in. Form our input TokenFactor node.
1750 SmallVector<SDValue, 3> InputChains;
1751 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1752 // Add the input chain of this node to the InputChains list (which will be
1753 // the operands of the generated TokenFactor) if it's not an interior node.
1754 SDNode *N = ChainNodesMatched[i];
1755 if (N->getOpcode() != ISD::TokenFactor) {
1756 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1759 // Otherwise, add the input chain.
1760 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1761 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1762 InputChains.push_back(InChain);
1766 // If we have a token factor, we want to add all inputs of the token factor
1767 // that are not part of the pattern we're matching.
1768 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1769 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1770 N->getOperand(op).getNode()))
1771 InputChains.push_back(N->getOperand(op));
1776 if (InputChains.size() == 1)
1777 return InputChains[0];
1778 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1779 MVT::Other, &InputChains[0], InputChains.size());
1782 /// MorphNode - Handle morphing a node in place for the selector.
1783 SDNode *SelectionDAGISel::
1784 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1785 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1786 // It is possible we're using MorphNodeTo to replace a node with no
1787 // normal results with one that has a normal result (or we could be
1788 // adding a chain) and the input could have glue and chains as well.
1789 // In this case we need to shift the operands down.
1790 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1791 // than the old isel though.
1792 int OldGlueResultNo = -1, OldChainResultNo = -1;
1794 unsigned NTMNumResults = Node->getNumValues();
1795 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1796 OldGlueResultNo = NTMNumResults-1;
1797 if (NTMNumResults != 1 &&
1798 Node->getValueType(NTMNumResults-2) == MVT::Other)
1799 OldChainResultNo = NTMNumResults-2;
1800 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1801 OldChainResultNo = NTMNumResults-1;
1803 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1804 // that this deletes operands of the old node that become dead.
1805 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1807 // MorphNodeTo can operate in two ways: if an existing node with the
1808 // specified operands exists, it can just return it. Otherwise, it
1809 // updates the node in place to have the requested operands.
1811 // If we updated the node in place, reset the node ID. To the isel,
1812 // this should be just like a newly allocated machine node.
1816 unsigned ResNumResults = Res->getNumValues();
1817 // Move the glue if needed.
1818 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1819 (unsigned)OldGlueResultNo != ResNumResults-1)
1820 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1821 SDValue(Res, ResNumResults-1));
1823 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1826 // Move the chain reference if needed.
1827 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1828 (unsigned)OldChainResultNo != ResNumResults-1)
1829 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1830 SDValue(Res, ResNumResults-1));
1832 // Otherwise, no replacement happened because the node already exists. Replace
1833 // Uses of the old node with the new one.
1835 CurDAG->ReplaceAllUsesWith(Node, Res);
1840 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1841 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1842 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1844 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1845 // Accept if it is exactly the same as a previously recorded node.
1846 unsigned RecNo = MatcherTable[MatcherIndex++];
1847 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1848 return N == RecordedNodes[RecNo].first;
1851 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1852 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1853 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1854 SelectionDAGISel &SDISel) {
1855 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1858 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1859 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1860 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1861 SelectionDAGISel &SDISel, SDNode *N) {
1862 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1865 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1866 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1868 uint16_t Opc = MatcherTable[MatcherIndex++];
1869 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1870 return N->getOpcode() == Opc;
1873 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1874 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1875 SDValue N, const TargetLowering &TLI) {
1876 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1877 if (N.getValueType() == VT) return true;
1879 // Handle the case when VT is iPTR.
1880 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1883 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1884 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1885 SDValue N, const TargetLowering &TLI,
1887 if (ChildNo >= N.getNumOperands())
1888 return false; // Match fails if out of range child #.
1889 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1893 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1894 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1896 return cast<CondCodeSDNode>(N)->get() ==
1897 (ISD::CondCode)MatcherTable[MatcherIndex++];
1900 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1901 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1902 SDValue N, const TargetLowering &TLI) {
1903 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1904 if (cast<VTSDNode>(N)->getVT() == VT)
1907 // Handle the case when VT is iPTR.
1908 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1911 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1912 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1914 int64_t Val = MatcherTable[MatcherIndex++];
1916 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1918 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1919 return C != 0 && C->getSExtValue() == Val;
1922 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1923 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1924 SDValue N, SelectionDAGISel &SDISel) {
1925 int64_t Val = MatcherTable[MatcherIndex++];
1927 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1929 if (N->getOpcode() != ISD::AND) return false;
1931 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1932 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1935 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1936 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1937 SDValue N, SelectionDAGISel &SDISel) {
1938 int64_t Val = MatcherTable[MatcherIndex++];
1940 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1942 if (N->getOpcode() != ISD::OR) return false;
1944 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1945 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1948 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1949 /// scope, evaluate the current node. If the current predicate is known to
1950 /// fail, set Result=true and return anything. If the current predicate is
1951 /// known to pass, set Result=false and return the MatcherIndex to continue
1952 /// with. If the current predicate is unknown, set Result=false and return the
1953 /// MatcherIndex to continue with.
1954 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1955 unsigned Index, SDValue N,
1956 bool &Result, SelectionDAGISel &SDISel,
1957 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1958 switch (Table[Index++]) {
1961 return Index-1; // Could not evaluate this predicate.
1962 case SelectionDAGISel::OPC_CheckSame:
1963 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1965 case SelectionDAGISel::OPC_CheckPatternPredicate:
1966 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1968 case SelectionDAGISel::OPC_CheckPredicate:
1969 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1971 case SelectionDAGISel::OPC_CheckOpcode:
1972 Result = !::CheckOpcode(Table, Index, N.getNode());
1974 case SelectionDAGISel::OPC_CheckType:
1975 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1977 case SelectionDAGISel::OPC_CheckChild0Type:
1978 case SelectionDAGISel::OPC_CheckChild1Type:
1979 case SelectionDAGISel::OPC_CheckChild2Type:
1980 case SelectionDAGISel::OPC_CheckChild3Type:
1981 case SelectionDAGISel::OPC_CheckChild4Type:
1982 case SelectionDAGISel::OPC_CheckChild5Type:
1983 case SelectionDAGISel::OPC_CheckChild6Type:
1984 case SelectionDAGISel::OPC_CheckChild7Type:
1985 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1986 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1988 case SelectionDAGISel::OPC_CheckCondCode:
1989 Result = !::CheckCondCode(Table, Index, N);
1991 case SelectionDAGISel::OPC_CheckValueType:
1992 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1994 case SelectionDAGISel::OPC_CheckInteger:
1995 Result = !::CheckInteger(Table, Index, N);
1997 case SelectionDAGISel::OPC_CheckAndImm:
1998 Result = !::CheckAndImm(Table, Index, N, SDISel);
2000 case SelectionDAGISel::OPC_CheckOrImm:
2001 Result = !::CheckOrImm(Table, Index, N, SDISel);
2009 /// FailIndex - If this match fails, this is the index to continue with.
2012 /// NodeStack - The node stack when the scope was formed.
2013 SmallVector<SDValue, 4> NodeStack;
2015 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2016 unsigned NumRecordedNodes;
2018 /// NumMatchedMemRefs - The number of matched memref entries.
2019 unsigned NumMatchedMemRefs;
2021 /// InputChain/InputGlue - The current chain/glue
2022 SDValue InputChain, InputGlue;
2024 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2025 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2030 SDNode *SelectionDAGISel::
2031 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2032 unsigned TableSize) {
2033 // FIXME: Should these even be selected? Handle these cases in the caller?
2034 switch (NodeToMatch->getOpcode()) {
2037 case ISD::EntryToken: // These nodes remain the same.
2038 case ISD::BasicBlock:
2040 //case ISD::VALUETYPE:
2041 //case ISD::CONDCODE:
2042 case ISD::HANDLENODE:
2043 case ISD::MDNODE_SDNODE:
2044 case ISD::TargetConstant:
2045 case ISD::TargetConstantFP:
2046 case ISD::TargetConstantPool:
2047 case ISD::TargetFrameIndex:
2048 case ISD::TargetExternalSymbol:
2049 case ISD::TargetBlockAddress:
2050 case ISD::TargetJumpTable:
2051 case ISD::TargetGlobalTLSAddress:
2052 case ISD::TargetGlobalAddress:
2053 case ISD::TokenFactor:
2054 case ISD::CopyFromReg:
2055 case ISD::CopyToReg:
2057 NodeToMatch->setNodeId(-1); // Mark selected.
2059 case ISD::AssertSext:
2060 case ISD::AssertZext:
2061 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2062 NodeToMatch->getOperand(0));
2064 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2065 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2068 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2070 // Set up the node stack with NodeToMatch as the only node on the stack.
2071 SmallVector<SDValue, 8> NodeStack;
2072 SDValue N = SDValue(NodeToMatch, 0);
2073 NodeStack.push_back(N);
2075 // MatchScopes - Scopes used when matching, if a match failure happens, this
2076 // indicates where to continue checking.
2077 SmallVector<MatchScope, 8> MatchScopes;
2079 // RecordedNodes - This is the set of nodes that have been recorded by the
2080 // state machine. The second value is the parent of the node, or null if the
2081 // root is recorded.
2082 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2084 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2086 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2088 // These are the current input chain and glue for use when generating nodes.
2089 // Various Emit operations change these. For example, emitting a copytoreg
2090 // uses and updates these.
2091 SDValue InputChain, InputGlue;
2093 // ChainNodesMatched - If a pattern matches nodes that have input/output
2094 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2095 // which ones they are. The result is captured into this list so that we can
2096 // update the chain results when the pattern is complete.
2097 SmallVector<SDNode*, 3> ChainNodesMatched;
2098 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2100 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2101 NodeToMatch->dump(CurDAG);
2104 // Determine where to start the interpreter. Normally we start at opcode #0,
2105 // but if the state machine starts with an OPC_SwitchOpcode, then we
2106 // accelerate the first lookup (which is guaranteed to be hot) with the
2107 // OpcodeOffset table.
2108 unsigned MatcherIndex = 0;
2110 if (!OpcodeOffset.empty()) {
2111 // Already computed the OpcodeOffset table, just index into it.
2112 if (N.getOpcode() < OpcodeOffset.size())
2113 MatcherIndex = OpcodeOffset[N.getOpcode()];
2114 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2116 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2117 // Otherwise, the table isn't computed, but the state machine does start
2118 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2119 // is the first time we're selecting an instruction.
2122 // Get the size of this case.
2123 unsigned CaseSize = MatcherTable[Idx++];
2125 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2126 if (CaseSize == 0) break;
2128 // Get the opcode, add the index to the table.
2129 uint16_t Opc = MatcherTable[Idx++];
2130 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2131 if (Opc >= OpcodeOffset.size())
2132 OpcodeOffset.resize((Opc+1)*2);
2133 OpcodeOffset[Opc] = Idx;
2137 // Okay, do the lookup for the first opcode.
2138 if (N.getOpcode() < OpcodeOffset.size())
2139 MatcherIndex = OpcodeOffset[N.getOpcode()];
2143 assert(MatcherIndex < TableSize && "Invalid index");
2145 unsigned CurrentOpcodeIndex = MatcherIndex;
2147 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2150 // Okay, the semantics of this operation are that we should push a scope
2151 // then evaluate the first child. However, pushing a scope only to have
2152 // the first check fail (which then pops it) is inefficient. If we can
2153 // determine immediately that the first check (or first several) will
2154 // immediately fail, don't even bother pushing a scope for them.
2158 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2159 if (NumToSkip & 128)
2160 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2161 // Found the end of the scope with no match.
2162 if (NumToSkip == 0) {
2167 FailIndex = MatcherIndex+NumToSkip;
2169 unsigned MatcherIndexOfPredicate = MatcherIndex;
2170 (void)MatcherIndexOfPredicate; // silence warning.
2172 // If we can't evaluate this predicate without pushing a scope (e.g. if
2173 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2174 // push the scope and evaluate the full predicate chain.
2176 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2177 Result, *this, RecordedNodes);
2181 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2182 << "index " << MatcherIndexOfPredicate
2183 << ", continuing at " << FailIndex << "\n");
2184 ++NumDAGIselRetries;
2186 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2187 // move to the next case.
2188 MatcherIndex = FailIndex;
2191 // If the whole scope failed to match, bail.
2192 if (FailIndex == 0) break;
2194 // Push a MatchScope which indicates where to go if the first child fails
2196 MatchScope NewEntry;
2197 NewEntry.FailIndex = FailIndex;
2198 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2199 NewEntry.NumRecordedNodes = RecordedNodes.size();
2200 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2201 NewEntry.InputChain = InputChain;
2202 NewEntry.InputGlue = InputGlue;
2203 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2204 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2205 MatchScopes.push_back(NewEntry);
2208 case OPC_RecordNode: {
2209 // Remember this node, it may end up being an operand in the pattern.
2211 if (NodeStack.size() > 1)
2212 Parent = NodeStack[NodeStack.size()-2].getNode();
2213 RecordedNodes.push_back(std::make_pair(N, Parent));
2217 case OPC_RecordChild0: case OPC_RecordChild1:
2218 case OPC_RecordChild2: case OPC_RecordChild3:
2219 case OPC_RecordChild4: case OPC_RecordChild5:
2220 case OPC_RecordChild6: case OPC_RecordChild7: {
2221 unsigned ChildNo = Opcode-OPC_RecordChild0;
2222 if (ChildNo >= N.getNumOperands())
2223 break; // Match fails if out of range child #.
2225 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2229 case OPC_RecordMemRef:
2230 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2233 case OPC_CaptureGlueInput:
2234 // If the current node has an input glue, capture it in InputGlue.
2235 if (N->getNumOperands() != 0 &&
2236 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2237 InputGlue = N->getOperand(N->getNumOperands()-1);
2240 case OPC_MoveChild: {
2241 unsigned ChildNo = MatcherTable[MatcherIndex++];
2242 if (ChildNo >= N.getNumOperands())
2243 break; // Match fails if out of range child #.
2244 N = N.getOperand(ChildNo);
2245 NodeStack.push_back(N);
2249 case OPC_MoveParent:
2250 // Pop the current node off the NodeStack.
2251 NodeStack.pop_back();
2252 assert(!NodeStack.empty() && "Node stack imbalance!");
2253 N = NodeStack.back();
2257 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2259 case OPC_CheckPatternPredicate:
2260 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2262 case OPC_CheckPredicate:
2263 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2267 case OPC_CheckComplexPat: {
2268 unsigned CPNum = MatcherTable[MatcherIndex++];
2269 unsigned RecNo = MatcherTable[MatcherIndex++];
2270 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2271 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2272 RecordedNodes[RecNo].first, CPNum,
2277 case OPC_CheckOpcode:
2278 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2282 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2285 case OPC_SwitchOpcode: {
2286 unsigned CurNodeOpcode = N.getOpcode();
2287 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2290 // Get the size of this case.
2291 CaseSize = MatcherTable[MatcherIndex++];
2293 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2294 if (CaseSize == 0) break;
2296 uint16_t Opc = MatcherTable[MatcherIndex++];
2297 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2299 // If the opcode matches, then we will execute this case.
2300 if (CurNodeOpcode == Opc)
2303 // Otherwise, skip over this case.
2304 MatcherIndex += CaseSize;
2307 // If no cases matched, bail out.
2308 if (CaseSize == 0) break;
2310 // Otherwise, execute the case we found.
2311 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2312 << " to " << MatcherIndex << "\n");
2316 case OPC_SwitchType: {
2317 MVT CurNodeVT = N.getValueType().getSimpleVT();
2318 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2321 // Get the size of this case.
2322 CaseSize = MatcherTable[MatcherIndex++];
2324 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2325 if (CaseSize == 0) break;
2327 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2328 if (CaseVT == MVT::iPTR)
2329 CaseVT = TLI.getPointerTy();
2331 // If the VT matches, then we will execute this case.
2332 if (CurNodeVT == CaseVT)
2335 // Otherwise, skip over this case.
2336 MatcherIndex += CaseSize;
2339 // If no cases matched, bail out.
2340 if (CaseSize == 0) break;
2342 // Otherwise, execute the case we found.
2343 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2344 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2347 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2348 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2349 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2350 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2351 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2352 Opcode-OPC_CheckChild0Type))
2355 case OPC_CheckCondCode:
2356 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2358 case OPC_CheckValueType:
2359 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2361 case OPC_CheckInteger:
2362 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2364 case OPC_CheckAndImm:
2365 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2367 case OPC_CheckOrImm:
2368 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2371 case OPC_CheckFoldableChainNode: {
2372 assert(NodeStack.size() != 1 && "No parent node");
2373 // Verify that all intermediate nodes between the root and this one have
2375 bool HasMultipleUses = false;
2376 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2377 if (!NodeStack[i].hasOneUse()) {
2378 HasMultipleUses = true;
2381 if (HasMultipleUses) break;
2383 // Check to see that the target thinks this is profitable to fold and that
2384 // we can fold it without inducing cycles in the graph.
2385 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2387 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2388 NodeToMatch, OptLevel,
2389 true/*We validate our own chains*/))
2394 case OPC_EmitInteger: {
2395 MVT::SimpleValueType VT =
2396 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2397 int64_t Val = MatcherTable[MatcherIndex++];
2399 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2400 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2401 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2404 case OPC_EmitRegister: {
2405 MVT::SimpleValueType VT =
2406 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2407 unsigned RegNo = MatcherTable[MatcherIndex++];
2408 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2409 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2412 case OPC_EmitRegister2: {
2413 // For targets w/ more than 256 register names, the register enum
2414 // values are stored in two bytes in the matcher table (just like
2416 MVT::SimpleValueType VT =
2417 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2418 unsigned RegNo = MatcherTable[MatcherIndex++];
2419 RegNo |= MatcherTable[MatcherIndex++] << 8;
2420 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2421 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2425 case OPC_EmitConvertToTarget: {
2426 // Convert from IMM/FPIMM to target version.
2427 unsigned RecNo = MatcherTable[MatcherIndex++];
2428 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2429 SDValue Imm = RecordedNodes[RecNo].first;
2431 if (Imm->getOpcode() == ISD::Constant) {
2432 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2433 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2434 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2435 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2436 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2439 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2443 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2444 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2445 // These are space-optimized forms of OPC_EmitMergeInputChains.
2446 assert(InputChain.getNode() == 0 &&
2447 "EmitMergeInputChains should be the first chain producing node");
2448 assert(ChainNodesMatched.empty() &&
2449 "Should only have one EmitMergeInputChains per match");
2451 // Read all of the chained nodes.
2452 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2453 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2454 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2456 // FIXME: What if other value results of the node have uses not matched
2458 if (ChainNodesMatched.back() != NodeToMatch &&
2459 !RecordedNodes[RecNo].first.hasOneUse()) {
2460 ChainNodesMatched.clear();
2464 // Merge the input chains if they are not intra-pattern references.
2465 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2467 if (InputChain.getNode() == 0)
2468 break; // Failed to merge.
2472 case OPC_EmitMergeInputChains: {
2473 assert(InputChain.getNode() == 0 &&
2474 "EmitMergeInputChains should be the first chain producing node");
2475 // This node gets a list of nodes we matched in the input that have
2476 // chains. We want to token factor all of the input chains to these nodes
2477 // together. However, if any of the input chains is actually one of the
2478 // nodes matched in this pattern, then we have an intra-match reference.
2479 // Ignore these because the newly token factored chain should not refer to
2481 unsigned NumChains = MatcherTable[MatcherIndex++];
2482 assert(NumChains != 0 && "Can't TF zero chains");
2484 assert(ChainNodesMatched.empty() &&
2485 "Should only have one EmitMergeInputChains per match");
2487 // Read all of the chained nodes.
2488 for (unsigned i = 0; i != NumChains; ++i) {
2489 unsigned RecNo = MatcherTable[MatcherIndex++];
2490 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2491 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2493 // FIXME: What if other value results of the node have uses not matched
2495 if (ChainNodesMatched.back() != NodeToMatch &&
2496 !RecordedNodes[RecNo].first.hasOneUse()) {
2497 ChainNodesMatched.clear();
2502 // If the inner loop broke out, the match fails.
2503 if (ChainNodesMatched.empty())
2506 // Merge the input chains if they are not intra-pattern references.
2507 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2509 if (InputChain.getNode() == 0)
2510 break; // Failed to merge.
2515 case OPC_EmitCopyToReg: {
2516 unsigned RecNo = MatcherTable[MatcherIndex++];
2517 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2518 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2520 if (InputChain.getNode() == 0)
2521 InputChain = CurDAG->getEntryNode();
2523 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2524 DestPhysReg, RecordedNodes[RecNo].first,
2527 InputGlue = InputChain.getValue(1);
2531 case OPC_EmitNodeXForm: {
2532 unsigned XFormNo = MatcherTable[MatcherIndex++];
2533 unsigned RecNo = MatcherTable[MatcherIndex++];
2534 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2535 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2536 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2541 case OPC_MorphNodeTo: {
2542 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2543 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2544 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2545 // Get the result VT list.
2546 unsigned NumVTs = MatcherTable[MatcherIndex++];
2547 SmallVector<EVT, 4> VTs;
2548 for (unsigned i = 0; i != NumVTs; ++i) {
2549 MVT::SimpleValueType VT =
2550 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2551 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2555 if (EmitNodeInfo & OPFL_Chain)
2556 VTs.push_back(MVT::Other);
2557 if (EmitNodeInfo & OPFL_GlueOutput)
2558 VTs.push_back(MVT::Glue);
2560 // This is hot code, so optimize the two most common cases of 1 and 2
2563 if (VTs.size() == 1)
2564 VTList = CurDAG->getVTList(VTs[0]);
2565 else if (VTs.size() == 2)
2566 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2568 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2570 // Get the operand list.
2571 unsigned NumOps = MatcherTable[MatcherIndex++];
2572 SmallVector<SDValue, 8> Ops;
2573 for (unsigned i = 0; i != NumOps; ++i) {
2574 unsigned RecNo = MatcherTable[MatcherIndex++];
2576 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2578 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2579 Ops.push_back(RecordedNodes[RecNo].first);
2582 // If there are variadic operands to add, handle them now.
2583 if (EmitNodeInfo & OPFL_VariadicInfo) {
2584 // Determine the start index to copy from.
2585 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2586 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2587 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2588 "Invalid variadic node");
2589 // Copy all of the variadic operands, not including a potential glue
2591 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2593 SDValue V = NodeToMatch->getOperand(i);
2594 if (V.getValueType() == MVT::Glue) break;
2599 // If this has chain/glue inputs, add them.
2600 if (EmitNodeInfo & OPFL_Chain)
2601 Ops.push_back(InputChain);
2602 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2603 Ops.push_back(InputGlue);
2607 if (Opcode != OPC_MorphNodeTo) {
2608 // If this is a normal EmitNode command, just create the new node and
2609 // add the results to the RecordedNodes list.
2610 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2611 VTList, Ops.data(), Ops.size());
2613 // Add all the non-glue/non-chain results to the RecordedNodes list.
2614 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2615 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2616 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2621 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2625 // If the node had chain/glue results, update our notion of the current
2627 if (EmitNodeInfo & OPFL_GlueOutput) {
2628 InputGlue = SDValue(Res, VTs.size()-1);
2629 if (EmitNodeInfo & OPFL_Chain)
2630 InputChain = SDValue(Res, VTs.size()-2);
2631 } else if (EmitNodeInfo & OPFL_Chain)
2632 InputChain = SDValue(Res, VTs.size()-1);
2634 // If the OPFL_MemRefs glue is set on this node, slap all of the
2635 // accumulated memrefs onto it.
2637 // FIXME: This is vastly incorrect for patterns with multiple outputs
2638 // instructions that access memory and for ComplexPatterns that match
2640 if (EmitNodeInfo & OPFL_MemRefs) {
2641 // Only attach load or store memory operands if the generated
2642 // instruction may load or store.
2643 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2644 bool mayLoad = MCID.mayLoad();
2645 bool mayStore = MCID.mayStore();
2647 unsigned NumMemRefs = 0;
2648 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2649 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2650 if ((*I)->isLoad()) {
2653 } else if ((*I)->isStore()) {
2661 MachineSDNode::mmo_iterator MemRefs =
2662 MF->allocateMemRefsArray(NumMemRefs);
2664 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2665 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2666 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2667 if ((*I)->isLoad()) {
2670 } else if ((*I)->isStore()) {
2678 cast<MachineSDNode>(Res)
2679 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2683 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2684 << " node: "; Res->dump(CurDAG); errs() << "\n");
2686 // If this was a MorphNodeTo then we're completely done!
2687 if (Opcode == OPC_MorphNodeTo) {
2688 // Update chain and glue uses.
2689 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2690 InputGlue, GlueResultNodesMatched, true);
2697 case OPC_MarkGlueResults: {
2698 unsigned NumNodes = MatcherTable[MatcherIndex++];
2700 // Read and remember all the glue-result nodes.
2701 for (unsigned i = 0; i != NumNodes; ++i) {
2702 unsigned RecNo = MatcherTable[MatcherIndex++];
2704 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2706 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2707 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2712 case OPC_CompleteMatch: {
2713 // The match has been completed, and any new nodes (if any) have been
2714 // created. Patch up references to the matched dag to use the newly
2716 unsigned NumResults = MatcherTable[MatcherIndex++];
2718 for (unsigned i = 0; i != NumResults; ++i) {
2719 unsigned ResSlot = MatcherTable[MatcherIndex++];
2721 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2723 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2724 SDValue Res = RecordedNodes[ResSlot].first;
2726 assert(i < NodeToMatch->getNumValues() &&
2727 NodeToMatch->getValueType(i) != MVT::Other &&
2728 NodeToMatch->getValueType(i) != MVT::Glue &&
2729 "Invalid number of results to complete!");
2730 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2731 NodeToMatch->getValueType(i) == MVT::iPTR ||
2732 Res.getValueType() == MVT::iPTR ||
2733 NodeToMatch->getValueType(i).getSizeInBits() ==
2734 Res.getValueType().getSizeInBits()) &&
2735 "invalid replacement");
2736 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2739 // If the root node defines glue, add it to the glue nodes to update list.
2740 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2741 GlueResultNodesMatched.push_back(NodeToMatch);
2743 // Update chain and glue uses.
2744 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2745 InputGlue, GlueResultNodesMatched, false);
2747 assert(NodeToMatch->use_empty() &&
2748 "Didn't replace all uses of the node?");
2750 // FIXME: We just return here, which interacts correctly with SelectRoot
2751 // above. We should fix this to not return an SDNode* anymore.
2756 // If the code reached this point, then the match failed. See if there is
2757 // another child to try in the current 'Scope', otherwise pop it until we
2758 // find a case to check.
2759 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2760 ++NumDAGIselRetries;
2762 if (MatchScopes.empty()) {
2763 CannotYetSelect(NodeToMatch);
2767 // Restore the interpreter state back to the point where the scope was
2769 MatchScope &LastScope = MatchScopes.back();
2770 RecordedNodes.resize(LastScope.NumRecordedNodes);
2772 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2773 N = NodeStack.back();
2775 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2776 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2777 MatcherIndex = LastScope.FailIndex;
2779 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2781 InputChain = LastScope.InputChain;
2782 InputGlue = LastScope.InputGlue;
2783 if (!LastScope.HasChainNodesMatched)
2784 ChainNodesMatched.clear();
2785 if (!LastScope.HasGlueResultNodesMatched)
2786 GlueResultNodesMatched.clear();
2788 // Check to see what the offset is at the new MatcherIndex. If it is zero
2789 // we have reached the end of this scope, otherwise we have another child
2790 // in the current scope to try.
2791 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2792 if (NumToSkip & 128)
2793 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2795 // If we have another child in this scope to match, update FailIndex and
2797 if (NumToSkip != 0) {
2798 LastScope.FailIndex = MatcherIndex+NumToSkip;
2802 // End of this scope, pop it and try the next child in the containing
2804 MatchScopes.pop_back();
2811 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2813 raw_string_ostream Msg(msg);
2814 Msg << "Cannot select: ";
2816 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2817 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2818 N->getOpcode() != ISD::INTRINSIC_VOID) {
2819 N->printrFull(Msg, CurDAG);
2821 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2823 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2824 if (iid < Intrinsic::num_intrinsics)
2825 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2826 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2827 Msg << "target intrinsic %" << TII->getName(iid);
2829 Msg << "unknown intrinsic #" << iid;
2831 report_fatal_error(Msg.str());
2834 char SelectionDAGISel::ID = 0;