1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/CodeGen/ScheduleDAG.h"
17 #include "llvm/CallingConv.h"
18 #include "llvm/Constants.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/InlineAsm.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineDebugInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/CodeGen/SSARegMap.h"
34 #include "llvm/Target/MRegisterInfo.h"
35 #include "llvm/Target/TargetData.h"
36 #include "llvm/Target/TargetFrameInfo.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetLowering.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/Debug.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
62 // Scheduling heuristics
63 enum SchedHeuristics {
64 defaultScheduling, // Let the target specify its preference.
65 noScheduling, // No scheduling, emit breadth first sequence.
66 simpleScheduling, // Two pass, min. critical path, max. utilization.
67 simpleNoItinScheduling, // Same as above exact using generic latency.
68 listSchedulingBURR, // Bottom-up reg reduction list scheduling.
69 listSchedulingTDRR, // Top-down reg reduction list scheduling.
70 listSchedulingTD // Top-down list scheduler.
74 cl::opt<SchedHeuristics>
77 cl::desc("Choose scheduling style"),
78 cl::init(defaultScheduling),
80 clEnumValN(defaultScheduling, "default",
81 "Target preferred scheduling style"),
82 clEnumValN(noScheduling, "none",
83 "No scheduling: breadth first sequencing"),
84 clEnumValN(simpleScheduling, "simple",
85 "Simple two pass scheduling: minimize critical path "
86 "and maximize processor utilization"),
87 clEnumValN(simpleNoItinScheduling, "simple-noitin",
88 "Simple two pass scheduling: Same as simple "
89 "except using generic latency"),
90 clEnumValN(listSchedulingBURR, "list-burr",
91 "Bottom-up register reduction list scheduling"),
92 clEnumValN(listSchedulingTDRR, "list-tdrr",
93 "Top-down register reduction list scheduling"),
94 clEnumValN(listSchedulingTD, "list-td",
95 "Top-down list scheduler"),
100 /// RegsForValue - This struct represents the physical registers that a
101 /// particular value is assigned and the type information about the value.
102 /// This is needed because values can be promoted into larger registers and
103 /// expanded into multiple smaller registers than the value.
104 struct RegsForValue {
105 /// Regs - This list hold the register (for legal and promoted values)
106 /// or register set (for expanded values) that the value should be assigned
108 std::vector<unsigned> Regs;
110 /// RegVT - The value type of each register.
112 MVT::ValueType RegVT;
114 /// ValueVT - The value type of the LLVM value, which may be promoted from
115 /// RegVT or made from merging the two expanded parts.
116 MVT::ValueType ValueVT;
118 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
120 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
121 : RegVT(regvt), ValueVT(valuevt) {
124 RegsForValue(const std::vector<unsigned> ®s,
125 MVT::ValueType regvt, MVT::ValueType valuevt)
126 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
129 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
130 /// this value and returns the result as a ValueVT value. This uses
131 /// Chain/Flag as the input and updates them for the output Chain/Flag.
132 SDOperand getCopyFromRegs(SelectionDAG &DAG,
133 SDOperand &Chain, SDOperand &Flag) const;
135 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
136 /// specified value into the registers specified by this object. This uses
137 /// Chain/Flag as the input and updates them for the output Chain/Flag.
138 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
139 SDOperand &Chain, SDOperand &Flag) const;
141 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
142 /// operand list. This adds the code marker and includes the number of
143 /// values added into it.
144 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
145 std::vector<SDOperand> &Ops) const;
150 //===--------------------------------------------------------------------===//
151 /// FunctionLoweringInfo - This contains information that is global to a
152 /// function that is used when lowering a region of the function.
153 class FunctionLoweringInfo {
160 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
162 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
163 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
165 /// ValueMap - Since we emit code for the function a basic block at a time,
166 /// we must remember which virtual registers hold the values for
167 /// cross-basic-block values.
168 std::map<const Value*, unsigned> ValueMap;
170 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
171 /// the entry block. This allows the allocas to be efficiently referenced
172 /// anywhere in the function.
173 std::map<const AllocaInst*, int> StaticAllocaMap;
175 unsigned MakeReg(MVT::ValueType VT) {
176 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
179 unsigned CreateRegForValue(const Value *V);
181 unsigned InitializeRegForValue(const Value *V) {
182 unsigned &R = ValueMap[V];
183 assert(R == 0 && "Already initialized this value register!");
184 return R = CreateRegForValue(V);
189 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
190 /// PHI nodes or outside of the basic block that defines it, or used by a
191 /// switch instruction, which may expand to multiple basic blocks.
192 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
193 if (isa<PHINode>(I)) return true;
194 BasicBlock *BB = I->getParent();
195 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
196 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
197 isa<SwitchInst>(*UI))
202 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
203 /// entry block, return true. This includes arguments used by switches, since
204 /// the switch may expand into multiple basic blocks.
205 static bool isOnlyUsedInEntryBlock(Argument *A) {
206 BasicBlock *Entry = A->getParent()->begin();
207 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
208 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
209 return false; // Use not in entry block.
213 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
214 Function &fn, MachineFunction &mf)
215 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
217 // Create a vreg for each argument register that is not dead and is used
218 // outside of the entry block for the function.
219 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
221 if (!isOnlyUsedInEntryBlock(AI))
222 InitializeRegForValue(AI);
224 // Initialize the mapping of values to registers. This is only set up for
225 // instruction values that are used outside of the block that defines
227 Function::iterator BB = Fn.begin(), EB = Fn.end();
228 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
229 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
230 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
231 const Type *Ty = AI->getAllocatedType();
232 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
234 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
237 // If the alignment of the value is smaller than the size of the value,
238 // and if the size of the value is particularly small (<= 8 bytes),
239 // round up to the size of the value for potentially better performance.
241 // FIXME: This could be made better with a preferred alignment hook in
242 // TargetData. It serves primarily to 8-byte align doubles for X86.
243 if (Align < TySize && TySize <= 8) Align = TySize;
244 TySize *= CUI->getValue(); // Get total allocated size.
245 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
246 StaticAllocaMap[AI] =
247 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
250 for (; BB != EB; ++BB)
251 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
252 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
253 if (!isa<AllocaInst>(I) ||
254 !StaticAllocaMap.count(cast<AllocaInst>(I)))
255 InitializeRegForValue(I);
257 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
258 // also creates the initial PHI MachineInstrs, though none of the input
259 // operands are populated.
260 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
261 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
263 MF.getBasicBlockList().push_back(MBB);
265 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
268 for (BasicBlock::iterator I = BB->begin();
269 (PN = dyn_cast<PHINode>(I)); ++I)
270 if (!PN->use_empty()) {
271 MVT::ValueType VT = TLI.getValueType(PN->getType());
272 unsigned NumElements;
273 if (VT != MVT::Vector)
274 NumElements = TLI.getNumElements(VT);
276 MVT::ValueType VT1,VT2;
278 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
281 unsigned PHIReg = ValueMap[PN];
282 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
283 for (unsigned i = 0; i != NumElements; ++i)
284 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
289 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
290 /// the correctly promoted or expanded types. Assign these registers
291 /// consecutive vreg numbers and return the first assigned number.
292 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
293 MVT::ValueType VT = TLI.getValueType(V->getType());
295 // The number of multiples of registers that we need, to, e.g., split up
296 // a <2 x int64> -> 4 x i32 registers.
297 unsigned NumVectorRegs = 1;
299 // If this is a packed type, figure out what type it will decompose into
300 // and how many of the elements it will use.
301 if (VT == MVT::Vector) {
302 const PackedType *PTy = cast<PackedType>(V->getType());
303 unsigned NumElts = PTy->getNumElements();
304 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
306 // Divide the input until we get to a supported size. This will always
307 // end with a scalar if the target doesn't support vectors.
308 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
315 VT = getVectorType(EltTy, NumElts);
318 // The common case is that we will only create one register for this
319 // value. If we have that case, create and return the virtual register.
320 unsigned NV = TLI.getNumElements(VT);
322 // If we are promoting this value, pick the next largest supported type.
323 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
324 unsigned Reg = MakeReg(PromotedType);
325 // If this is a vector of supported or promoted types (e.g. 4 x i16),
326 // create all of the registers.
327 for (unsigned i = 1; i != NumVectorRegs; ++i)
328 MakeReg(PromotedType);
332 // If this value is represented with multiple target registers, make sure
333 // to create enough consecutive registers of the right (smaller) type.
334 unsigned NT = VT-1; // Find the type to use.
335 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
338 unsigned R = MakeReg((MVT::ValueType)NT);
339 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
340 MakeReg((MVT::ValueType)NT);
344 //===----------------------------------------------------------------------===//
345 /// SelectionDAGLowering - This is the common target-independent lowering
346 /// implementation that is parameterized by a TargetLowering object.
347 /// Also, targets can overload any lowering method.
350 class SelectionDAGLowering {
351 MachineBasicBlock *CurMBB;
353 std::map<const Value*, SDOperand> NodeMap;
355 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
356 /// them up and then emit token factor nodes when possible. This allows us to
357 /// get simple disambiguation between loads without worrying about alias
359 std::vector<SDOperand> PendingLoads;
361 /// Case - A pair of values to record the Value for a switch case, and the
362 /// case's target basic block.
363 typedef std::pair<Constant*, MachineBasicBlock*> Case;
364 typedef std::vector<Case>::iterator CaseItr;
365 typedef std::pair<CaseItr, CaseItr> CaseRange;
367 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
368 /// of conditional branches.
370 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
371 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
373 /// CaseBB - The MBB in which to emit the compare and branch
374 MachineBasicBlock *CaseBB;
375 /// LT, GE - If nonzero, we know the current case value must be less-than or
376 /// greater-than-or-equal-to these Constants.
379 /// Range - A pair of iterators representing the range of case values to be
380 /// processed at this point in the binary search tree.
384 /// The comparison function for sorting Case values.
386 bool operator () (const Case& C1, const Case& C2) {
387 if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first))
388 return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue();
390 const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first);
391 return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue();
396 // TLI - This is information that describes the available target features we
397 // need for lowering. This indicates when operations are unavailable,
398 // implemented with a libcall, etc.
401 const TargetData *TD;
403 /// SwitchCases - Vector of CaseBlock structures used to communicate
404 /// SwitchInst code generation information.
405 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
406 SelectionDAGISel::JumpTable JT;
408 /// FuncInfo - Information about the function as a whole.
410 FunctionLoweringInfo &FuncInfo;
412 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
413 FunctionLoweringInfo &funcinfo)
414 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
415 JT(0,0,0,0), FuncInfo(funcinfo) {
418 /// getRoot - Return the current virtual root of the Selection DAG.
420 SDOperand getRoot() {
421 if (PendingLoads.empty())
422 return DAG.getRoot();
424 if (PendingLoads.size() == 1) {
425 SDOperand Root = PendingLoads[0];
427 PendingLoads.clear();
431 // Otherwise, we have to make a token factor node.
432 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
433 PendingLoads.clear();
438 void visit(Instruction &I) { visit(I.getOpcode(), I); }
440 void visit(unsigned Opcode, User &I) {
442 default: assert(0 && "Unknown instruction type encountered!");
444 // Build the switch statement using the Instruction.def file.
445 #define HANDLE_INST(NUM, OPCODE, CLASS) \
446 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
447 #include "llvm/Instruction.def"
451 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
453 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
454 SDOperand SrcValue, SDOperand Root,
457 SDOperand getIntPtrConstant(uint64_t Val) {
458 return DAG.getConstant(Val, TLI.getPointerTy());
461 SDOperand getValue(const Value *V);
463 const SDOperand &setValue(const Value *V, SDOperand NewN) {
464 SDOperand &N = NodeMap[V];
465 assert(N.Val == 0 && "Already set a value for this node!");
469 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
471 bool OutReg, bool InReg,
472 std::set<unsigned> &OutputRegs,
473 std::set<unsigned> &InputRegs);
475 // Terminator instructions.
476 void visitRet(ReturnInst &I);
477 void visitBr(BranchInst &I);
478 void visitSwitch(SwitchInst &I);
479 void visitUnreachable(UnreachableInst &I) { /* noop */ }
481 // Helper for visitSwitch
482 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
483 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
485 // These all get lowered before this pass.
486 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
487 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
489 void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
490 void visitShift(User &I, unsigned Opcode);
491 void visitAdd(User &I) {
492 visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
494 void visitSub(User &I);
495 void visitMul(User &I) {
496 visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
498 void visitDiv(User &I) {
499 const Type *Ty = I.getType();
501 Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
502 Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
504 void visitRem(User &I) {
505 const Type *Ty = I.getType();
506 visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
508 void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
509 void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
510 void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
511 void visitShl(User &I) { visitShift(I, ISD::SHL); }
512 void visitShr(User &I) {
513 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
516 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc,
517 ISD::CondCode FPOpc);
518 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ,
520 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE,
522 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE,
524 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE,
526 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT,
528 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT,
531 void visitExtractElement(User &I);
532 void visitInsertElement(User &I);
533 void visitShuffleVector(User &I);
535 void visitGetElementPtr(User &I);
536 void visitCast(User &I);
537 void visitSelect(User &I);
539 void visitMalloc(MallocInst &I);
540 void visitFree(FreeInst &I);
541 void visitAlloca(AllocaInst &I);
542 void visitLoad(LoadInst &I);
543 void visitStore(StoreInst &I);
544 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
545 void visitCall(CallInst &I);
546 void visitInlineAsm(CallInst &I);
547 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
548 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
550 void visitVAStart(CallInst &I);
551 void visitVAArg(VAArgInst &I);
552 void visitVAEnd(CallInst &I);
553 void visitVACopy(CallInst &I);
554 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
556 void visitMemIntrinsic(CallInst &I, unsigned Op);
558 void visitUserOp1(Instruction &I) {
559 assert(0 && "UserOp1 should not exist at instruction selection time!");
562 void visitUserOp2(Instruction &I) {
563 assert(0 && "UserOp2 should not exist at instruction selection time!");
567 } // end namespace llvm
569 SDOperand SelectionDAGLowering::getValue(const Value *V) {
570 SDOperand &N = NodeMap[V];
573 const Type *VTy = V->getType();
574 MVT::ValueType VT = TLI.getValueType(VTy);
575 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
576 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
577 visit(CE->getOpcode(), *CE);
578 assert(N.Val && "visit didn't populate the ValueMap!");
580 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
581 return N = DAG.getGlobalAddress(GV, VT);
582 } else if (isa<ConstantPointerNull>(C)) {
583 return N = DAG.getConstant(0, TLI.getPointerTy());
584 } else if (isa<UndefValue>(C)) {
585 if (!isa<PackedType>(VTy))
586 return N = DAG.getNode(ISD::UNDEF, VT);
588 // Create a VBUILD_VECTOR of undef nodes.
589 const PackedType *PTy = cast<PackedType>(VTy);
590 unsigned NumElements = PTy->getNumElements();
591 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
593 std::vector<SDOperand> Ops;
594 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
596 // Create a VConstant node with generic Vector type.
597 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
598 Ops.push_back(DAG.getValueType(PVT));
599 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
600 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
601 return N = DAG.getConstantFP(CFP->getValue(), VT);
602 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
603 unsigned NumElements = PTy->getNumElements();
604 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
606 // Now that we know the number and type of the elements, push a
607 // Constant or ConstantFP node onto the ops list for each element of
608 // the packed constant.
609 std::vector<SDOperand> Ops;
610 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
611 for (unsigned i = 0; i != NumElements; ++i)
612 Ops.push_back(getValue(CP->getOperand(i)));
614 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
616 if (MVT::isFloatingPoint(PVT))
617 Op = DAG.getConstantFP(0, PVT);
619 Op = DAG.getConstant(0, PVT);
620 Ops.assign(NumElements, Op);
623 // Create a VBUILD_VECTOR node with generic Vector type.
624 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
625 Ops.push_back(DAG.getValueType(PVT));
626 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
628 // Canonicalize all constant ints to be unsigned.
629 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
633 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
634 std::map<const AllocaInst*, int>::iterator SI =
635 FuncInfo.StaticAllocaMap.find(AI);
636 if (SI != FuncInfo.StaticAllocaMap.end())
637 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
640 std::map<const Value*, unsigned>::const_iterator VMI =
641 FuncInfo.ValueMap.find(V);
642 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
644 unsigned InReg = VMI->second;
646 // If this type is not legal, make it so now.
647 if (VT != MVT::Vector) {
648 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
650 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
652 // Source must be expanded. This input value is actually coming from the
653 // register pair VMI->second and VMI->second+1.
654 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
655 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
656 } else if (DestVT > VT) { // Promotion case
657 if (MVT::isFloatingPoint(VT))
658 N = DAG.getNode(ISD::FP_ROUND, VT, N);
660 N = DAG.getNode(ISD::TRUNCATE, VT, N);
663 // Otherwise, if this is a vector, make it available as a generic vector
665 MVT::ValueType PTyElementVT, PTyLegalElementVT;
666 const PackedType *PTy = cast<PackedType>(VTy);
667 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
670 // Build a VBUILD_VECTOR with the input registers.
671 std::vector<SDOperand> Ops;
672 if (PTyElementVT == PTyLegalElementVT) {
673 // If the value types are legal, just VBUILD the CopyFromReg nodes.
674 for (unsigned i = 0; i != NE; ++i)
675 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
677 } else if (PTyElementVT < PTyLegalElementVT) {
678 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
679 for (unsigned i = 0; i != NE; ++i) {
680 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
682 if (MVT::isFloatingPoint(PTyElementVT))
683 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
685 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
689 // If the register was expanded, use BUILD_PAIR.
690 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
691 for (unsigned i = 0; i != NE/2; ++i) {
692 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
694 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
696 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
700 Ops.push_back(DAG.getConstant(NE, MVT::i32));
701 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
702 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
704 // Finally, use a VBIT_CONVERT to make this available as the appropriate
706 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
707 DAG.getConstant(PTy->getNumElements(),
709 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
716 void SelectionDAGLowering::visitRet(ReturnInst &I) {
717 if (I.getNumOperands() == 0) {
718 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
721 std::vector<SDOperand> NewValues;
722 NewValues.push_back(getRoot());
723 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
724 SDOperand RetOp = getValue(I.getOperand(i));
726 // If this is an integer return value, we need to promote it ourselves to
727 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
729 if (MVT::isInteger(RetOp.getValueType()) &&
730 RetOp.getValueType() < MVT::i64) {
731 MVT::ValueType TmpVT;
732 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
733 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
737 if (I.getOperand(i)->getType()->isSigned())
738 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
740 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
742 NewValues.push_back(RetOp);
744 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, NewValues));
747 void SelectionDAGLowering::visitBr(BranchInst &I) {
748 // Update machine-CFG edges.
749 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
750 CurMBB->addSuccessor(Succ0MBB);
752 // Figure out which block is immediately after the current one.
753 MachineBasicBlock *NextBlock = 0;
754 MachineFunction::iterator BBI = CurMBB;
755 if (++BBI != CurMBB->getParent()->end())
758 if (I.isUnconditional()) {
759 // If this is not a fall-through branch, emit the branch.
760 if (Succ0MBB != NextBlock)
761 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
762 DAG.getBasicBlock(Succ0MBB)));
764 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
765 CurMBB->addSuccessor(Succ1MBB);
767 SDOperand Cond = getValue(I.getCondition());
768 if (Succ1MBB == NextBlock) {
769 // If the condition is false, fall through. This means we should branch
770 // if the condition is true to Succ #0.
771 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
772 Cond, DAG.getBasicBlock(Succ0MBB)));
773 } else if (Succ0MBB == NextBlock) {
774 // If the condition is true, fall through. This means we should branch if
775 // the condition is false to Succ #1. Invert the condition first.
776 SDOperand True = DAG.getConstant(1, Cond.getValueType());
777 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
778 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
779 Cond, DAG.getBasicBlock(Succ1MBB)));
781 std::vector<SDOperand> Ops;
782 Ops.push_back(getRoot());
783 // If the false case is the current basic block, then this is a self
784 // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
785 // adds an extra instruction in the loop. Instead, invert the
786 // condition and emit "Loop: ... br!cond Loop; br Out.
787 if (CurMBB == Succ1MBB) {
788 std::swap(Succ0MBB, Succ1MBB);
789 SDOperand True = DAG.getConstant(1, Cond.getValueType());
790 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
792 SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
793 DAG.getBasicBlock(Succ0MBB));
794 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
795 DAG.getBasicBlock(Succ1MBB)));
800 /// visitSwitchCase - Emits the necessary code to represent a single node in
801 /// the binary search tree resulting from lowering a switch instruction.
802 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
803 SDOperand SwitchOp = getValue(CB.SwitchV);
804 SDOperand CaseOp = getValue(CB.CaseC);
805 SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC);
807 // Set NextBlock to be the MBB immediately after the current one, if any.
808 // This is used to avoid emitting unnecessary branches to the next block.
809 MachineBasicBlock *NextBlock = 0;
810 MachineFunction::iterator BBI = CurMBB;
811 if (++BBI != CurMBB->getParent()->end())
814 // If the lhs block is the next block, invert the condition so that we can
815 // fall through to the lhs instead of the rhs block.
816 if (CB.LHSBB == NextBlock) {
817 std::swap(CB.LHSBB, CB.RHSBB);
818 SDOperand True = DAG.getConstant(1, Cond.getValueType());
819 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
821 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
822 DAG.getBasicBlock(CB.LHSBB));
823 if (CB.RHSBB == NextBlock)
826 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
827 DAG.getBasicBlock(CB.RHSBB)));
828 // Update successor info
829 CurMBB->addSuccessor(CB.LHSBB);
830 CurMBB->addSuccessor(CB.RHSBB);
833 /// visitSwitchCase - Emits the necessary code to represent a single node in
834 /// the binary search tree resulting from lowering a switch instruction.
835 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
836 // FIXME: Need to emit different code for PIC vs. Non-PIC, specifically,
837 // we need to add the address of the jump table to the value loaded, since
838 // the entries in the jump table will be differences rather than absolute
841 // Emit the code for the jump table
842 MVT::ValueType PTy = TLI.getPointerTy();
843 unsigned PTyBytes = MVT::getSizeInBits(PTy)/8;
844 SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
845 SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy,
846 DAG.getConstant(PTyBytes, PTy));
847 SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, DAG.getJumpTable(JT.JTI,PTy));
848 SDOperand LD = DAG.getLoad(PTy, Copy.getValue(1), ADD, DAG.getSrcValue(0));
849 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD));
852 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
853 // Figure out which block is immediately after the current one.
854 MachineBasicBlock *NextBlock = 0;
855 MachineFunction::iterator BBI = CurMBB;
856 if (++BBI != CurMBB->getParent()->end())
859 // If there is only the default destination, branch to it if it is not the
860 // next basic block. Otherwise, just fall through.
861 if (I.getNumOperands() == 2) {
862 // Update machine-CFG edges.
863 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()];
864 // If this is not a fall-through branch, emit the branch.
865 if (DefaultMBB != NextBlock)
866 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
867 DAG.getBasicBlock(DefaultMBB)));
871 // If there are any non-default case statements, create a vector of Cases
872 // representing each one, and sort the vector so that we can efficiently
873 // create a binary search tree from them.
874 std::vector<Case> Cases;
875 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
876 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
877 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
879 std::sort(Cases.begin(), Cases.end(), CaseCmp());
881 // Get the Value to be switched on and default basic blocks, which will be
882 // inserted into CaseBlock records, representing basic blocks in the binary
884 Value *SV = I.getOperand(0);
885 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
887 // Get the MachineFunction which holds the current MBB. This is used during
888 // emission of jump tables, and when inserting any additional MBBs necessary
889 // to represent the switch.
890 MachineFunction *CurMF = CurMBB->getParent();
891 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
892 Reloc::Model Relocs = TLI.getTargetMachine().getRelocationModel();
894 // If the switch has more than 5 blocks, and at least 31.25% dense, and the
895 // target supports indirect branches, then emit a jump table rather than
896 // lowering the switch to a binary tree of conditional branches.
897 // FIXME: Make this work with PIC code
898 if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) &&
899 (Relocs == Reloc::Static || Relocs == Reloc::DynamicNoPIC) &&
901 uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue();
902 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getRawValue();
903 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
905 if (Density >= 0.3125) {
906 // Create a new basic block to hold the code for loading the address
907 // of the jump table, and jumping to it. Update successor information;
908 // we will either branch to the default case for the switch, or the jump
910 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
911 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
912 CurMBB->addSuccessor(Default);
913 CurMBB->addSuccessor(JumpTableBB);
915 // Subtract the lowest switch case value from the value being switched on
916 // and conditional branch to default mbb if the result is greater than the
917 // difference between smallest and largest cases.
918 SDOperand SwitchOp = getValue(SV);
919 MVT::ValueType VT = SwitchOp.getValueType();
920 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
921 DAG.getConstant(First, VT));
923 // The SDNode we just created, which holds the value being switched on
924 // minus the the smallest case value, needs to be copied to a virtual
925 // register so it can be used as an index into the jump table in a
926 // subsequent basic block. This value may be smaller or larger than the
927 // target's pointer type, and therefore require extension or truncating.
928 if (VT > TLI.getPointerTy())
929 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
931 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
932 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
933 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
935 // Emit the range check for the jump table, and branch to the default
936 // block for the switch statement if the value being switched on exceeds
937 // the largest case in the switch.
938 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
939 DAG.getConstant(Last-First,VT), ISD::SETUGT);
940 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
941 DAG.getBasicBlock(Default)));
943 // Build a vector of destination BBs, corresponding to each target
944 // of the jump table. If the value of the jump table slot corresponds to
945 // a case statement, push the case's BB onto the vector, otherwise, push
947 std::set<MachineBasicBlock*> UniqueBBs;
948 std::vector<MachineBasicBlock*> DestBBs;
949 uint64_t TEI = First;
950 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) {
951 if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) {
952 DestBBs.push_back(ii->second);
953 UniqueBBs.insert(ii->second);
956 DestBBs.push_back(Default);
957 UniqueBBs.insert(Default);
961 // Update successor info
962 for (std::set<MachineBasicBlock*>::iterator ii = UniqueBBs.begin(),
963 ee = UniqueBBs.end(); ii != ee; ++ii)
964 JumpTableBB->addSuccessor(*ii);
966 // Create a jump table index for this jump table, or return an existing
968 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
970 // Set the jump table information so that we can codegen it as a second
972 JT.Reg = JumpTableReg;
974 JT.MBB = JumpTableBB;
975 JT.Default = Default;
980 // Push the initial CaseRec onto the worklist
981 std::vector<CaseRec> CaseVec;
982 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
984 while (!CaseVec.empty()) {
985 // Grab a record representing a case range to process off the worklist
986 CaseRec CR = CaseVec.back();
989 // Size is the number of Cases represented by this range. If Size is 1,
990 // then we are processing a leaf of the binary search tree. Otherwise,
991 // we need to pick a pivot, and push left and right ranges onto the
993 unsigned Size = CR.Range.second - CR.Range.first;
996 // Create a CaseBlock record representing a conditional branch to
997 // the Case's target mbb if the value being switched on SV is equal
998 // to C. Otherwise, branch to default.
999 Constant *C = CR.Range.first->first;
1000 MachineBasicBlock *Target = CR.Range.first->second;
1001 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1003 // If the MBB representing the leaf node is the current MBB, then just
1004 // call visitSwitchCase to emit the code into the current block.
1005 // Otherwise, push the CaseBlock onto the vector to be later processed
1006 // by SDISel, and insert the node's MBB before the next MBB.
1007 if (CR.CaseBB == CurMBB)
1008 visitSwitchCase(CB);
1010 SwitchCases.push_back(CB);
1011 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1014 // split case range at pivot
1015 CaseItr Pivot = CR.Range.first + (Size / 2);
1016 CaseRange LHSR(CR.Range.first, Pivot);
1017 CaseRange RHSR(Pivot, CR.Range.second);
1018 Constant *C = Pivot->first;
1019 MachineBasicBlock *RHSBB = 0, *LHSBB = 0;
1020 // We know that we branch to the LHS if the Value being switched on is
1021 // less than the Pivot value, C. We use this to optimize our binary
1022 // tree a bit, by recognizing that if SV is greater than or equal to the
1023 // LHS's Case Value, and that Case Value is exactly one less than the
1024 // Pivot's Value, then we can branch directly to the LHS's Target,
1025 // rather than creating a leaf node for it.
1026 if ((LHSR.second - LHSR.first) == 1 &&
1027 LHSR.first->first == CR.GE &&
1028 cast<ConstantIntegral>(C)->getRawValue() ==
1029 (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) {
1030 LHSBB = LHSR.first->second;
1032 LHSBB = new MachineBasicBlock(LLVMBB);
1033 CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR));
1035 // Similar to the optimization above, if the Value being switched on is
1036 // known to be less than the Constant CR.LT, and the current Case Value
1037 // is CR.LT - 1, then we can branch directly to the target block for
1038 // the current Case Value, rather than emitting a RHS leaf node for it.
1039 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1040 cast<ConstantIntegral>(RHSR.first->first)->getRawValue() ==
1041 (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) {
1042 RHSBB = RHSR.first->second;
1044 RHSBB = new MachineBasicBlock(LLVMBB);
1045 CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR));
1047 // Create a CaseBlock record representing a conditional branch to
1048 // the LHS node if the value being switched on SV is less than C.
1049 // Otherwise, branch to LHS.
1050 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
1051 SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB);
1052 if (CR.CaseBB == CurMBB)
1053 visitSwitchCase(CB);
1055 SwitchCases.push_back(CB);
1056 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1062 void SelectionDAGLowering::visitSub(User &I) {
1063 // -0.0 - X --> fneg
1064 if (I.getType()->isFloatingPoint()) {
1065 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1066 if (CFP->isExactlyValue(-0.0)) {
1067 SDOperand Op2 = getValue(I.getOperand(1));
1068 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1072 visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
1075 void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
1077 const Type *Ty = I.getType();
1078 SDOperand Op1 = getValue(I.getOperand(0));
1079 SDOperand Op2 = getValue(I.getOperand(1));
1081 if (Ty->isIntegral()) {
1082 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
1083 } else if (Ty->isFloatingPoint()) {
1084 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
1086 const PackedType *PTy = cast<PackedType>(Ty);
1087 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1088 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1089 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1093 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1094 SDOperand Op1 = getValue(I.getOperand(0));
1095 SDOperand Op2 = getValue(I.getOperand(1));
1097 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1099 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1102 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
1103 ISD::CondCode UnsignedOpcode,
1104 ISD::CondCode FPOpcode) {
1105 SDOperand Op1 = getValue(I.getOperand(0));
1106 SDOperand Op2 = getValue(I.getOperand(1));
1107 ISD::CondCode Opcode = SignedOpcode;
1108 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint())
1110 else if (I.getOperand(0)->getType()->isUnsigned())
1111 Opcode = UnsignedOpcode;
1112 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1115 void SelectionDAGLowering::visitSelect(User &I) {
1116 SDOperand Cond = getValue(I.getOperand(0));
1117 SDOperand TrueVal = getValue(I.getOperand(1));
1118 SDOperand FalseVal = getValue(I.getOperand(2));
1119 if (!isa<PackedType>(I.getType())) {
1120 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1121 TrueVal, FalseVal));
1123 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1124 *(TrueVal.Val->op_end()-2),
1125 *(TrueVal.Val->op_end()-1)));
1129 void SelectionDAGLowering::visitCast(User &I) {
1130 SDOperand N = getValue(I.getOperand(0));
1131 MVT::ValueType SrcVT = N.getValueType();
1132 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1134 if (DestVT == MVT::Vector) {
1135 // This is a cast to a vector from something else. This is always a bit
1136 // convert. Get information about the input vector.
1137 const PackedType *DestTy = cast<PackedType>(I.getType());
1138 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1139 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1140 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1141 DAG.getValueType(EltVT)));
1142 } else if (SrcVT == DestVT) {
1143 setValue(&I, N); // noop cast.
1144 } else if (DestVT == MVT::i1) {
1145 // Cast to bool is a comparison against zero, not truncation to zero.
1146 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
1147 DAG.getConstantFP(0.0, N.getValueType());
1148 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
1149 } else if (isInteger(SrcVT)) {
1150 if (isInteger(DestVT)) { // Int -> Int cast
1151 if (DestVT < SrcVT) // Truncating cast?
1152 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1153 else if (I.getOperand(0)->getType()->isSigned())
1154 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1156 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1157 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast
1158 if (I.getOperand(0)->getType()->isSigned())
1159 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1161 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1163 assert(0 && "Unknown cast!");
1165 } else if (isFloatingPoint(SrcVT)) {
1166 if (isFloatingPoint(DestVT)) { // FP -> FP cast
1167 if (DestVT < SrcVT) // Rounding cast?
1168 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1170 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1171 } else if (isInteger(DestVT)) { // FP -> Int cast.
1172 if (I.getType()->isSigned())
1173 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1175 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1177 assert(0 && "Unknown cast!");
1180 assert(SrcVT == MVT::Vector && "Unknown cast!");
1181 assert(DestVT != MVT::Vector && "Casts to vector already handled!");
1182 // This is a cast from a vector to something else. This is always a bit
1183 // convert. Get information about the input vector.
1184 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1188 void SelectionDAGLowering::visitInsertElement(User &I) {
1189 SDOperand InVec = getValue(I.getOperand(0));
1190 SDOperand InVal = getValue(I.getOperand(1));
1191 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1192 getValue(I.getOperand(2)));
1194 SDOperand Num = *(InVec.Val->op_end()-2);
1195 SDOperand Typ = *(InVec.Val->op_end()-1);
1196 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1197 InVec, InVal, InIdx, Num, Typ));
1200 void SelectionDAGLowering::visitExtractElement(User &I) {
1201 SDOperand InVec = getValue(I.getOperand(0));
1202 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1203 getValue(I.getOperand(1)));
1204 SDOperand Typ = *(InVec.Val->op_end()-1);
1205 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1206 TLI.getValueType(I.getType()), InVec, InIdx));
1209 void SelectionDAGLowering::visitShuffleVector(User &I) {
1210 SDOperand V1 = getValue(I.getOperand(0));
1211 SDOperand V2 = getValue(I.getOperand(1));
1212 SDOperand Mask = getValue(I.getOperand(2));
1214 SDOperand Num = *(V1.Val->op_end()-2);
1215 SDOperand Typ = *(V2.Val->op_end()-1);
1216 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1217 V1, V2, Mask, Num, Typ));
1221 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1222 SDOperand N = getValue(I.getOperand(0));
1223 const Type *Ty = I.getOperand(0)->getType();
1225 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1228 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1229 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
1232 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
1233 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1234 getIntPtrConstant(Offset));
1236 Ty = StTy->getElementType(Field);
1238 Ty = cast<SequentialType>(Ty)->getElementType();
1240 // If this is a constant subscript, handle it quickly.
1241 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1242 if (CI->getRawValue() == 0) continue;
1245 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
1246 Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
1248 Offs = TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
1249 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1253 // N = N + Idx * ElementSize;
1254 uint64_t ElementSize = TD->getTypeSize(Ty);
1255 SDOperand IdxN = getValue(Idx);
1257 // If the index is smaller or larger than intptr_t, truncate or extend
1259 if (IdxN.getValueType() < N.getValueType()) {
1260 if (Idx->getType()->isSigned())
1261 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1263 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
1264 } else if (IdxN.getValueType() > N.getValueType())
1265 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1267 // If this is a multiply by a power of two, turn it into a shl
1268 // immediately. This is a very common case.
1269 if (isPowerOf2_64(ElementSize)) {
1270 unsigned Amt = Log2_64(ElementSize);
1271 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1272 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1273 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1277 SDOperand Scale = getIntPtrConstant(ElementSize);
1278 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1279 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1285 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1286 // If this is a fixed sized alloca in the entry block of the function,
1287 // allocate it statically on the stack.
1288 if (FuncInfo.StaticAllocaMap.count(&I))
1289 return; // getValue will auto-populate this.
1291 const Type *Ty = I.getAllocatedType();
1292 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1293 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
1296 SDOperand AllocSize = getValue(I.getArraySize());
1297 MVT::ValueType IntPtr = TLI.getPointerTy();
1298 if (IntPtr < AllocSize.getValueType())
1299 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1300 else if (IntPtr > AllocSize.getValueType())
1301 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1303 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1304 getIntPtrConstant(TySize));
1306 // Handle alignment. If the requested alignment is less than or equal to the
1307 // stack alignment, ignore it and round the size of the allocation up to the
1308 // stack alignment size. If the size is greater than the stack alignment, we
1309 // note this in the DYNAMIC_STACKALLOC node.
1310 unsigned StackAlign =
1311 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1312 if (Align <= StackAlign) {
1314 // Add SA-1 to the size.
1315 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1316 getIntPtrConstant(StackAlign-1));
1317 // Mask out the low bits for alignment purposes.
1318 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1319 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1322 std::vector<MVT::ValueType> VTs;
1323 VTs.push_back(AllocSize.getValueType());
1324 VTs.push_back(MVT::Other);
1325 std::vector<SDOperand> Ops;
1326 Ops.push_back(getRoot());
1327 Ops.push_back(AllocSize);
1328 Ops.push_back(getIntPtrConstant(Align));
1329 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
1330 DAG.setRoot(setValue(&I, DSA).getValue(1));
1332 // Inform the Frame Information that we have just allocated a variable-sized
1334 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1337 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1338 SDOperand Ptr = getValue(I.getOperand(0));
1344 // Do not serialize non-volatile loads against each other.
1345 Root = DAG.getRoot();
1348 setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)),
1349 Root, I.isVolatile()));
1352 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1353 SDOperand SrcValue, SDOperand Root,
1356 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1357 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1358 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue);
1360 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue);
1364 DAG.setRoot(L.getValue(1));
1366 PendingLoads.push_back(L.getValue(1));
1372 void SelectionDAGLowering::visitStore(StoreInst &I) {
1373 Value *SrcV = I.getOperand(0);
1374 SDOperand Src = getValue(SrcV);
1375 SDOperand Ptr = getValue(I.getOperand(1));
1376 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
1377 DAG.getSrcValue(I.getOperand(1))));
1380 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1381 /// access memory and has no other side effects at all.
1382 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1383 #define GET_NO_MEMORY_INTRINSICS
1384 #include "llvm/Intrinsics.gen"
1385 #undef GET_NO_MEMORY_INTRINSICS
1389 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1390 // have any side-effects or if it only reads memory.
1391 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1392 #define GET_SIDE_EFFECT_INFO
1393 #include "llvm/Intrinsics.gen"
1394 #undef GET_SIDE_EFFECT_INFO
1398 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1400 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1401 unsigned Intrinsic) {
1402 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1403 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1405 // Build the operand list.
1406 std::vector<SDOperand> Ops;
1407 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1409 // We don't need to serialize loads against other loads.
1410 Ops.push_back(DAG.getRoot());
1412 Ops.push_back(getRoot());
1416 // Add the intrinsic ID as an integer operand.
1417 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1419 // Add all operands of the call to the operand list.
1420 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1421 SDOperand Op = getValue(I.getOperand(i));
1423 // If this is a vector type, force it to the right packed type.
1424 if (Op.getValueType() == MVT::Vector) {
1425 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1426 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1428 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1429 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1430 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1433 assert(TLI.isTypeLegal(Op.getValueType()) &&
1434 "Intrinsic uses a non-legal type?");
1438 std::vector<MVT::ValueType> VTs;
1439 if (I.getType() != Type::VoidTy) {
1440 MVT::ValueType VT = TLI.getValueType(I.getType());
1441 if (VT == MVT::Vector) {
1442 const PackedType *DestTy = cast<PackedType>(I.getType());
1443 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1445 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1446 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1449 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1453 VTs.push_back(MVT::Other);
1458 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, Ops);
1459 else if (I.getType() != Type::VoidTy)
1460 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, Ops);
1462 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
1465 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1467 PendingLoads.push_back(Chain);
1471 if (I.getType() != Type::VoidTy) {
1472 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1473 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1474 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1475 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1476 DAG.getValueType(EVT));
1478 setValue(&I, Result);
1482 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1483 /// we want to emit this as a call to a named external function, return the name
1484 /// otherwise lower it and return null.
1486 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1487 switch (Intrinsic) {
1489 // By default, turn this into a target intrinsic node.
1490 visitTargetIntrinsic(I, Intrinsic);
1492 case Intrinsic::vastart: visitVAStart(I); return 0;
1493 case Intrinsic::vaend: visitVAEnd(I); return 0;
1494 case Intrinsic::vacopy: visitVACopy(I); return 0;
1495 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1496 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1497 case Intrinsic::setjmp:
1498 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1500 case Intrinsic::longjmp:
1501 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1503 case Intrinsic::memcpy_i32:
1504 case Intrinsic::memcpy_i64:
1505 visitMemIntrinsic(I, ISD::MEMCPY);
1507 case Intrinsic::memset_i32:
1508 case Intrinsic::memset_i64:
1509 visitMemIntrinsic(I, ISD::MEMSET);
1511 case Intrinsic::memmove_i32:
1512 case Intrinsic::memmove_i64:
1513 visitMemIntrinsic(I, ISD::MEMMOVE);
1516 case Intrinsic::dbg_stoppoint: {
1517 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1518 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1519 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
1520 std::vector<SDOperand> Ops;
1522 Ops.push_back(getRoot());
1523 Ops.push_back(getValue(SPI.getLineValue()));
1524 Ops.push_back(getValue(SPI.getColumnValue()));
1526 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
1527 assert(DD && "Not a debug information descriptor");
1528 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1530 Ops.push_back(DAG.getString(CompileUnit->getFileName()));
1531 Ops.push_back(DAG.getString(CompileUnit->getDirectory()));
1533 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops));
1538 case Intrinsic::dbg_region_start: {
1539 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1540 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1541 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
1542 std::vector<SDOperand> Ops;
1544 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
1546 Ops.push_back(getRoot());
1547 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1549 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1554 case Intrinsic::dbg_region_end: {
1555 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1556 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
1557 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
1558 std::vector<SDOperand> Ops;
1560 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
1562 Ops.push_back(getRoot());
1563 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1565 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1570 case Intrinsic::dbg_func_start: {
1571 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1572 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
1573 if (DebugInfo && FSI.getSubprogram() &&
1574 DebugInfo->Verify(FSI.getSubprogram())) {
1575 std::vector<SDOperand> Ops;
1577 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
1579 Ops.push_back(getRoot());
1580 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1582 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1587 case Intrinsic::dbg_declare: {
1588 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1589 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
1590 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
1591 std::vector<SDOperand> Ops;
1593 SDOperand AddressOp = getValue(DI.getAddress());
1594 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) {
1595 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
1602 case Intrinsic::isunordered_f32:
1603 case Intrinsic::isunordered_f64:
1604 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
1605 getValue(I.getOperand(2)), ISD::SETUO));
1608 case Intrinsic::sqrt_f32:
1609 case Intrinsic::sqrt_f64:
1610 setValue(&I, DAG.getNode(ISD::FSQRT,
1611 getValue(I.getOperand(1)).getValueType(),
1612 getValue(I.getOperand(1))));
1614 case Intrinsic::pcmarker: {
1615 SDOperand Tmp = getValue(I.getOperand(1));
1616 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
1619 case Intrinsic::readcyclecounter: {
1620 std::vector<MVT::ValueType> VTs;
1621 VTs.push_back(MVT::i64);
1622 VTs.push_back(MVT::Other);
1623 std::vector<SDOperand> Ops;
1624 Ops.push_back(getRoot());
1625 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops);
1627 DAG.setRoot(Tmp.getValue(1));
1630 case Intrinsic::bswap_i16:
1631 case Intrinsic::bswap_i32:
1632 case Intrinsic::bswap_i64:
1633 setValue(&I, DAG.getNode(ISD::BSWAP,
1634 getValue(I.getOperand(1)).getValueType(),
1635 getValue(I.getOperand(1))));
1637 case Intrinsic::cttz_i8:
1638 case Intrinsic::cttz_i16:
1639 case Intrinsic::cttz_i32:
1640 case Intrinsic::cttz_i64:
1641 setValue(&I, DAG.getNode(ISD::CTTZ,
1642 getValue(I.getOperand(1)).getValueType(),
1643 getValue(I.getOperand(1))));
1645 case Intrinsic::ctlz_i8:
1646 case Intrinsic::ctlz_i16:
1647 case Intrinsic::ctlz_i32:
1648 case Intrinsic::ctlz_i64:
1649 setValue(&I, DAG.getNode(ISD::CTLZ,
1650 getValue(I.getOperand(1)).getValueType(),
1651 getValue(I.getOperand(1))));
1653 case Intrinsic::ctpop_i8:
1654 case Intrinsic::ctpop_i16:
1655 case Intrinsic::ctpop_i32:
1656 case Intrinsic::ctpop_i64:
1657 setValue(&I, DAG.getNode(ISD::CTPOP,
1658 getValue(I.getOperand(1)).getValueType(),
1659 getValue(I.getOperand(1))));
1661 case Intrinsic::stacksave: {
1662 std::vector<MVT::ValueType> VTs;
1663 VTs.push_back(TLI.getPointerTy());
1664 VTs.push_back(MVT::Other);
1665 std::vector<SDOperand> Ops;
1666 Ops.push_back(getRoot());
1667 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, Ops);
1669 DAG.setRoot(Tmp.getValue(1));
1672 case Intrinsic::stackrestore: {
1673 SDOperand Tmp = getValue(I.getOperand(1));
1674 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
1677 case Intrinsic::prefetch:
1678 // FIXME: Currently discarding prefetches.
1684 void SelectionDAGLowering::visitCall(CallInst &I) {
1685 const char *RenameFn = 0;
1686 if (Function *F = I.getCalledFunction()) {
1687 if (F->isExternal())
1688 if (unsigned IID = F->getIntrinsicID()) {
1689 RenameFn = visitIntrinsicCall(I, IID);
1692 } else { // Not an LLVM intrinsic.
1693 const std::string &Name = F->getName();
1694 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
1695 if (I.getNumOperands() == 3 && // Basic sanity checks.
1696 I.getOperand(1)->getType()->isFloatingPoint() &&
1697 I.getType() == I.getOperand(1)->getType() &&
1698 I.getType() == I.getOperand(2)->getType()) {
1699 SDOperand LHS = getValue(I.getOperand(1));
1700 SDOperand RHS = getValue(I.getOperand(2));
1701 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
1705 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
1706 if (I.getNumOperands() == 2 && // Basic sanity checks.
1707 I.getOperand(1)->getType()->isFloatingPoint() &&
1708 I.getType() == I.getOperand(1)->getType()) {
1709 SDOperand Tmp = getValue(I.getOperand(1));
1710 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
1713 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
1714 if (I.getNumOperands() == 2 && // Basic sanity checks.
1715 I.getOperand(1)->getType()->isFloatingPoint() &&
1716 I.getType() == I.getOperand(1)->getType()) {
1717 SDOperand Tmp = getValue(I.getOperand(1));
1718 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
1721 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
1722 if (I.getNumOperands() == 2 && // Basic sanity checks.
1723 I.getOperand(1)->getType()->isFloatingPoint() &&
1724 I.getType() == I.getOperand(1)->getType()) {
1725 SDOperand Tmp = getValue(I.getOperand(1));
1726 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
1731 } else if (isa<InlineAsm>(I.getOperand(0))) {
1738 Callee = getValue(I.getOperand(0));
1740 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
1741 std::vector<std::pair<SDOperand, const Type*> > Args;
1742 Args.reserve(I.getNumOperands());
1743 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1744 Value *Arg = I.getOperand(i);
1745 SDOperand ArgNode = getValue(Arg);
1746 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
1749 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
1750 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1752 std::pair<SDOperand,SDOperand> Result =
1753 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
1754 I.isTailCall(), Callee, Args, DAG);
1755 if (I.getType() != Type::VoidTy)
1756 setValue(&I, Result.first);
1757 DAG.setRoot(Result.second);
1760 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
1761 SDOperand &Chain, SDOperand &Flag)const{
1762 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
1763 Chain = Val.getValue(1);
1764 Flag = Val.getValue(2);
1766 // If the result was expanded, copy from the top part.
1767 if (Regs.size() > 1) {
1768 assert(Regs.size() == 2 &&
1769 "Cannot expand to more than 2 elts yet!");
1770 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
1771 Chain = Val.getValue(1);
1772 Flag = Val.getValue(2);
1773 if (DAG.getTargetLoweringInfo().isLittleEndian())
1774 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
1776 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
1779 // Otherwise, if the return value was promoted, truncate it to the
1780 // appropriate type.
1781 if (RegVT == ValueVT)
1784 if (MVT::isInteger(RegVT))
1785 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1787 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
1790 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
1791 /// specified value into the registers specified by this object. This uses
1792 /// Chain/Flag as the input and updates them for the output Chain/Flag.
1793 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
1794 SDOperand &Chain, SDOperand &Flag) const {
1795 if (Regs.size() == 1) {
1796 // If there is a single register and the types differ, this must be
1798 if (RegVT != ValueVT) {
1799 if (MVT::isInteger(RegVT))
1800 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
1802 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
1804 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
1805 Flag = Chain.getValue(1);
1807 std::vector<unsigned> R(Regs);
1808 if (!DAG.getTargetLoweringInfo().isLittleEndian())
1809 std::reverse(R.begin(), R.end());
1811 for (unsigned i = 0, e = R.size(); i != e; ++i) {
1812 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
1813 DAG.getConstant(i, MVT::i32));
1814 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
1815 Flag = Chain.getValue(1);
1820 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
1821 /// operand list. This adds the code marker and includes the number of
1822 /// values added into it.
1823 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
1824 std::vector<SDOperand> &Ops) const {
1825 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
1826 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1827 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
1830 /// isAllocatableRegister - If the specified register is safe to allocate,
1831 /// i.e. it isn't a stack pointer or some other special register, return the
1832 /// register class for the register. Otherwise, return null.
1833 static const TargetRegisterClass *
1834 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
1835 const TargetLowering &TLI, const MRegisterInfo *MRI) {
1836 MVT::ValueType FoundVT = MVT::Other;
1837 const TargetRegisterClass *FoundRC = 0;
1838 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
1839 E = MRI->regclass_end(); RCI != E; ++RCI) {
1840 MVT::ValueType ThisVT = MVT::Other;
1842 const TargetRegisterClass *RC = *RCI;
1843 // If none of the the value types for this register class are valid, we
1844 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1845 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1847 if (TLI.isTypeLegal(*I)) {
1848 // If we have already found this register in a different register class,
1849 // choose the one with the largest VT specified. For example, on
1850 // PowerPC, we favor f64 register classes over f32.
1851 if (FoundVT == MVT::Other ||
1852 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
1859 if (ThisVT == MVT::Other) continue;
1861 // NOTE: This isn't ideal. In particular, this might allocate the
1862 // frame pointer in functions that need it (due to them not being taken
1863 // out of allocation, because a variable sized allocation hasn't been seen
1864 // yet). This is a slight code pessimization, but should still work.
1865 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
1866 E = RC->allocation_order_end(MF); I != E; ++I)
1868 // We found a matching register class. Keep looking at others in case
1869 // we find one with larger registers that this physreg is also in.
1878 RegsForValue SelectionDAGLowering::
1879 GetRegistersForValue(const std::string &ConstrCode,
1880 MVT::ValueType VT, bool isOutReg, bool isInReg,
1881 std::set<unsigned> &OutputRegs,
1882 std::set<unsigned> &InputRegs) {
1883 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
1884 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
1885 std::vector<unsigned> Regs;
1887 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
1888 MVT::ValueType RegVT;
1889 MVT::ValueType ValueVT = VT;
1891 if (PhysReg.first) {
1892 if (VT == MVT::Other)
1893 ValueVT = *PhysReg.second->vt_begin();
1896 // This is a explicit reference to a physical register.
1897 Regs.push_back(PhysReg.first);
1899 // If this is an expanded reference, add the rest of the regs to Regs.
1901 RegVT = *PhysReg.second->vt_begin();
1902 TargetRegisterClass::iterator I = PhysReg.second->begin();
1903 TargetRegisterClass::iterator E = PhysReg.second->end();
1904 for (; *I != PhysReg.first; ++I)
1905 assert(I != E && "Didn't find reg!");
1907 // Already added the first reg.
1909 for (; NumRegs; --NumRegs, ++I) {
1910 assert(I != E && "Ran out of registers to allocate!");
1914 return RegsForValue(Regs, RegVT, ValueVT);
1917 // This is a reference to a register class. Allocate NumRegs consecutive,
1918 // available, registers from the class.
1919 std::vector<unsigned> RegClassRegs =
1920 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
1922 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
1923 MachineFunction &MF = *CurMBB->getParent();
1924 unsigned NumAllocated = 0;
1925 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
1926 unsigned Reg = RegClassRegs[i];
1927 // See if this register is available.
1928 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
1929 (isInReg && InputRegs.count(Reg))) { // Already used.
1930 // Make sure we find consecutive registers.
1935 // Check to see if this register is allocatable (i.e. don't give out the
1937 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
1939 // Make sure we find consecutive registers.
1944 // Okay, this register is good, we can use it.
1947 // If we allocated enough consecutive
1948 if (NumAllocated == NumRegs) {
1949 unsigned RegStart = (i-NumAllocated)+1;
1950 unsigned RegEnd = i+1;
1951 // Mark all of the allocated registers used.
1952 for (unsigned i = RegStart; i != RegEnd; ++i) {
1953 unsigned Reg = RegClassRegs[i];
1954 Regs.push_back(Reg);
1955 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
1956 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
1959 return RegsForValue(Regs, *RC->vt_begin(), VT);
1963 // Otherwise, we couldn't allocate enough registers for this.
1964 return RegsForValue();
1968 /// visitInlineAsm - Handle a call to an InlineAsm object.
1970 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
1971 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
1973 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
1976 // Note, we treat inline asms both with and without side-effects as the same.
1977 // If an inline asm doesn't have side effects and doesn't access memory, we
1978 // could not choose to not chain it.
1979 bool hasSideEffects = IA->hasSideEffects();
1981 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
1982 std::vector<MVT::ValueType> ConstraintVTs;
1984 /// AsmNodeOperands - A list of pairs. The first element is a register, the
1985 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
1986 /// if it is a def of that register.
1987 std::vector<SDOperand> AsmNodeOperands;
1988 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
1989 AsmNodeOperands.push_back(AsmStr);
1991 SDOperand Chain = getRoot();
1994 // We fully assign registers here at isel time. This is not optimal, but
1995 // should work. For register classes that correspond to LLVM classes, we
1996 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
1997 // over the constraints, collecting fixed registers that we know we can't use.
1998 std::set<unsigned> OutputRegs, InputRegs;
2000 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2001 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2002 std::string &ConstraintCode = Constraints[i].Codes[0];
2004 MVT::ValueType OpVT;
2006 // Compute the value type for each operand and add it to ConstraintVTs.
2007 switch (Constraints[i].Type) {
2008 case InlineAsm::isOutput:
2009 if (!Constraints[i].isIndirectOutput) {
2010 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2011 OpVT = TLI.getValueType(I.getType());
2013 const Type *OpTy = I.getOperand(OpNum)->getType();
2014 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2015 OpNum++; // Consumes a call operand.
2018 case InlineAsm::isInput:
2019 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2020 OpNum++; // Consumes a call operand.
2022 case InlineAsm::isClobber:
2027 ConstraintVTs.push_back(OpVT);
2029 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2030 continue; // Not assigned a fixed reg.
2032 // Build a list of regs that this operand uses. This always has a single
2033 // element for promoted/expanded operands.
2034 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2036 OutputRegs, InputRegs);
2038 switch (Constraints[i].Type) {
2039 case InlineAsm::isOutput:
2040 // We can't assign any other output to this register.
2041 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2042 // If this is an early-clobber output, it cannot be assigned to the same
2043 // value as the input reg.
2044 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2045 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2047 case InlineAsm::isInput:
2048 // We can't assign any other input to this register.
2049 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2051 case InlineAsm::isClobber:
2052 // Clobbered regs cannot be used as inputs or outputs.
2053 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2054 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2059 // Loop over all of the inputs, copying the operand values into the
2060 // appropriate registers and processing the output regs.
2061 RegsForValue RetValRegs;
2062 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2065 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2066 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2067 std::string &ConstraintCode = Constraints[i].Codes[0];
2069 switch (Constraints[i].Type) {
2070 case InlineAsm::isOutput: {
2071 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2072 if (ConstraintCode.size() == 1) // not a physreg name.
2073 CTy = TLI.getConstraintType(ConstraintCode[0]);
2075 if (CTy == TargetLowering::C_Memory) {
2077 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2079 // Check that the operand (the address to store to) isn't a float.
2080 if (!MVT::isInteger(InOperandVal.getValueType()))
2081 assert(0 && "MATCH FAIL!");
2083 if (!Constraints[i].isIndirectOutput)
2084 assert(0 && "MATCH FAIL!");
2086 OpNum++; // Consumes a call operand.
2088 // Extend/truncate to the right pointer type if needed.
2089 MVT::ValueType PtrType = TLI.getPointerTy();
2090 if (InOperandVal.getValueType() < PtrType)
2091 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2092 else if (InOperandVal.getValueType() > PtrType)
2093 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2095 // Add information to the INLINEASM node to know about this output.
2096 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2097 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2098 AsmNodeOperands.push_back(InOperandVal);
2102 // Otherwise, this is a register output.
2103 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2105 // If this is an early-clobber output, or if there is an input
2106 // constraint that matches this, we need to reserve the input register
2107 // so no other inputs allocate to it.
2108 bool UsesInputRegister = false;
2109 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2110 UsesInputRegister = true;
2112 // Copy the output from the appropriate register. Find a register that
2115 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2116 true, UsesInputRegister,
2117 OutputRegs, InputRegs);
2118 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
2120 if (!Constraints[i].isIndirectOutput) {
2121 assert(RetValRegs.Regs.empty() &&
2122 "Cannot have multiple output constraints yet!");
2123 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2126 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2127 I.getOperand(OpNum)));
2128 OpNum++; // Consumes a call operand.
2131 // Add information to the INLINEASM node to know that this register is
2133 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2136 case InlineAsm::isInput: {
2137 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2138 OpNum++; // Consumes a call operand.
2140 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2141 // If this is required to match an output register we have already set,
2142 // just use its register.
2143 unsigned OperandNo = atoi(ConstraintCode.c_str());
2145 // Scan until we find the definition we already emitted of this operand.
2146 // When we find it, create a RegsForValue operand.
2147 unsigned CurOp = 2; // The first operand.
2148 for (; OperandNo; --OperandNo) {
2149 // Advance to the next operand.
2151 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2152 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2153 "Skipped past definitions?");
2154 CurOp += (NumOps>>3)+1;
2158 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2159 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2160 "Skipped past definitions?");
2162 // Add NumOps>>3 registers to MatchedRegs.
2163 RegsForValue MatchedRegs;
2164 MatchedRegs.ValueVT = InOperandVal.getValueType();
2165 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2166 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2167 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2168 MatchedRegs.Regs.push_back(Reg);
2171 // Use the produced MatchedRegs object to
2172 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
2173 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2177 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2178 if (ConstraintCode.size() == 1) // not a physreg name.
2179 CTy = TLI.getConstraintType(ConstraintCode[0]);
2181 if (CTy == TargetLowering::C_Other) {
2182 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
2183 assert(0 && "MATCH FAIL!");
2185 // Add information to the INLINEASM node to know about this input.
2186 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2187 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2188 AsmNodeOperands.push_back(InOperandVal);
2190 } else if (CTy == TargetLowering::C_Memory) {
2193 // Check that the operand isn't a float.
2194 if (!MVT::isInteger(InOperandVal.getValueType()))
2195 assert(0 && "MATCH FAIL!");
2197 // Extend/truncate to the right pointer type if needed.
2198 MVT::ValueType PtrType = TLI.getPointerTy();
2199 if (InOperandVal.getValueType() < PtrType)
2200 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2201 else if (InOperandVal.getValueType() > PtrType)
2202 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2204 // Add information to the INLINEASM node to know about this input.
2205 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2206 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2207 AsmNodeOperands.push_back(InOperandVal);
2211 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2213 // Copy the input into the appropriate registers.
2214 RegsForValue InRegs =
2215 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2216 false, true, OutputRegs, InputRegs);
2217 // FIXME: should be match fail.
2218 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2220 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
2222 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2225 case InlineAsm::isClobber: {
2226 RegsForValue ClobberedRegs =
2227 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2228 OutputRegs, InputRegs);
2229 // Add the clobbered value to the operand list, so that the register
2230 // allocator is aware that the physreg got clobbered.
2231 if (!ClobberedRegs.Regs.empty())
2232 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2238 // Finish up input operands.
2239 AsmNodeOperands[0] = Chain;
2240 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2242 std::vector<MVT::ValueType> VTs;
2243 VTs.push_back(MVT::Other);
2244 VTs.push_back(MVT::Flag);
2245 Chain = DAG.getNode(ISD::INLINEASM, VTs, AsmNodeOperands);
2246 Flag = Chain.getValue(1);
2248 // If this asm returns a register value, copy the result from that register
2249 // and set it as the value of the call.
2250 if (!RetValRegs.Regs.empty())
2251 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2253 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2255 // Process indirect outputs, first output all of the flagged copies out of
2257 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2258 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2259 Value *Ptr = IndirectStoresToEmit[i].second;
2260 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2261 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2264 // Emit the non-flagged stores from the physregs.
2265 std::vector<SDOperand> OutChains;
2266 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2267 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
2268 StoresToEmit[i].first,
2269 getValue(StoresToEmit[i].second),
2270 DAG.getSrcValue(StoresToEmit[i].second)));
2271 if (!OutChains.empty())
2272 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
2277 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2278 SDOperand Src = getValue(I.getOperand(0));
2280 MVT::ValueType IntPtr = TLI.getPointerTy();
2282 if (IntPtr < Src.getValueType())
2283 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2284 else if (IntPtr > Src.getValueType())
2285 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2287 // Scale the source by the type size.
2288 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
2289 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2290 Src, getIntPtrConstant(ElementSize));
2292 std::vector<std::pair<SDOperand, const Type*> > Args;
2293 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType()));
2295 std::pair<SDOperand,SDOperand> Result =
2296 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
2297 DAG.getExternalSymbol("malloc", IntPtr),
2299 setValue(&I, Result.first); // Pointers always fit in registers
2300 DAG.setRoot(Result.second);
2303 void SelectionDAGLowering::visitFree(FreeInst &I) {
2304 std::vector<std::pair<SDOperand, const Type*> > Args;
2305 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
2306 TLI.getTargetData()->getIntPtrType()));
2307 MVT::ValueType IntPtr = TLI.getPointerTy();
2308 std::pair<SDOperand,SDOperand> Result =
2309 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
2310 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2311 DAG.setRoot(Result.second);
2314 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2315 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2316 // instructions are special in various ways, which require special support to
2317 // insert. The specified MachineInstr is created but not inserted into any
2318 // basic blocks, and the scheduler passes ownership of it to this method.
2319 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2320 MachineBasicBlock *MBB) {
2321 std::cerr << "If a target marks an instruction with "
2322 "'usesCustomDAGSchedInserter', it must implement "
2323 "TargetLowering::InsertAtEndOfBasicBlock!\n";
2328 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2329 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2330 getValue(I.getOperand(1)),
2331 DAG.getSrcValue(I.getOperand(1))));
2334 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2335 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2336 getValue(I.getOperand(0)),
2337 DAG.getSrcValue(I.getOperand(0)));
2339 DAG.setRoot(V.getValue(1));
2342 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2343 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2344 getValue(I.getOperand(1)),
2345 DAG.getSrcValue(I.getOperand(1))));
2348 void SelectionDAGLowering::visitVACopy(CallInst &I) {
2349 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2350 getValue(I.getOperand(1)),
2351 getValue(I.getOperand(2)),
2352 DAG.getSrcValue(I.getOperand(1)),
2353 DAG.getSrcValue(I.getOperand(2))));
2356 /// TargetLowering::LowerArguments - This is the default LowerArguments
2357 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
2358 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
2359 /// integrated into SDISel.
2360 std::vector<SDOperand>
2361 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2362 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2363 std::vector<SDOperand> Ops;
2364 Ops.push_back(DAG.getRoot());
2365 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2366 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2368 // Add one result value for each formal argument.
2369 std::vector<MVT::ValueType> RetVals;
2370 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2371 MVT::ValueType VT = getValueType(I->getType());
2373 switch (getTypeAction(VT)) {
2374 default: assert(0 && "Unknown type action!");
2376 RetVals.push_back(VT);
2379 RetVals.push_back(getTypeToTransformTo(VT));
2382 if (VT != MVT::Vector) {
2383 // If this is a large integer, it needs to be broken up into small
2384 // integers. Figure out what the destination type is and how many small
2385 // integers it turns into.
2386 MVT::ValueType NVT = getTypeToTransformTo(VT);
2387 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2388 for (unsigned i = 0; i != NumVals; ++i)
2389 RetVals.push_back(NVT);
2391 // Otherwise, this is a vector type. We only support legal vectors
2393 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2394 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2396 // Figure out if there is a Packed type corresponding to this Vector
2397 // type. If so, convert to the packed type.
2398 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2399 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2400 RetVals.push_back(TVT);
2402 assert(0 && "Don't support illegal by-val vector arguments yet!");
2409 RetVals.push_back(MVT::Other);
2412 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals, Ops).Val;
2414 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
2416 // Set up the return result vector.
2419 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2420 MVT::ValueType VT = getValueType(I->getType());
2422 switch (getTypeAction(VT)) {
2423 default: assert(0 && "Unknown type action!");
2425 Ops.push_back(SDOperand(Result, i++));
2428 SDOperand Op(Result, i++);
2429 if (MVT::isInteger(VT)) {
2430 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
2432 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
2433 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2435 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2436 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2442 if (VT != MVT::Vector) {
2443 // If this is a large integer, it needs to be reassembled from small
2444 // integers. Figure out what the source elt type is and how many small
2446 MVT::ValueType NVT = getTypeToTransformTo(VT);
2447 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2449 SDOperand Lo = SDOperand(Result, i++);
2450 SDOperand Hi = SDOperand(Result, i++);
2452 if (!isLittleEndian())
2455 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
2457 // Value scalarized into many values. Unimp for now.
2458 assert(0 && "Cannot expand i64 -> i16 yet!");
2461 // Otherwise, this is a vector type. We only support legal vectors
2463 const PackedType *PTy = cast<PackedType>(I->getType());
2464 unsigned NumElems = PTy->getNumElements();
2465 const Type *EltTy = PTy->getElementType();
2467 // Figure out if there is a Packed type corresponding to this Vector
2468 // type. If so, convert to the packed type.
2469 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2470 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2471 SDOperand N = SDOperand(Result, i++);
2472 // Handle copies from generic vectors to registers.
2473 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
2474 DAG.getConstant(NumElems, MVT::i32),
2475 DAG.getValueType(getValueType(EltTy)));
2478 assert(0 && "Don't support illegal by-val vector arguments yet!");
2489 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
2490 /// implementation, which just inserts an ISD::CALL node, which is later custom
2491 /// lowered by the target to something concrete. FIXME: When all targets are
2492 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
2493 std::pair<SDOperand, SDOperand>
2494 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
2495 unsigned CallingConv, bool isTailCall,
2497 ArgListTy &Args, SelectionDAG &DAG) {
2498 std::vector<SDOperand> Ops;
2499 Ops.push_back(Chain); // Op#0 - Chain
2500 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
2501 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
2502 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
2503 Ops.push_back(Callee);
2505 // Handle all of the outgoing arguments.
2506 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
2507 MVT::ValueType VT = getValueType(Args[i].second);
2508 SDOperand Op = Args[i].first;
2509 switch (getTypeAction(VT)) {
2510 default: assert(0 && "Unknown type action!");
2515 if (MVT::isInteger(VT)) {
2516 unsigned ExtOp = Args[i].second->isSigned() ?
2517 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2518 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
2520 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2521 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
2526 if (VT != MVT::Vector) {
2527 // If this is a large integer, it needs to be broken down into small
2528 // integers. Figure out what the source elt type is and how many small
2530 MVT::ValueType NVT = getTypeToTransformTo(VT);
2531 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2533 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2534 DAG.getConstant(0, getPointerTy()));
2535 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2536 DAG.getConstant(1, getPointerTy()));
2537 if (!isLittleEndian())
2543 // Value scalarized into many values. Unimp for now.
2544 assert(0 && "Cannot expand i64 -> i16 yet!");
2547 // Otherwise, this is a vector type. We only support legal vectors
2549 const PackedType *PTy = cast<PackedType>(Args[i].second);
2550 unsigned NumElems = PTy->getNumElements();
2551 const Type *EltTy = PTy->getElementType();
2553 // Figure out if there is a Packed type corresponding to this Vector
2554 // type. If so, convert to the packed type.
2555 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2556 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2557 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
2558 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
2561 assert(0 && "Don't support illegal by-val vector call args yet!");
2569 // Figure out the result value types.
2570 std::vector<MVT::ValueType> RetTys;
2572 if (RetTy != Type::VoidTy) {
2573 MVT::ValueType VT = getValueType(RetTy);
2574 switch (getTypeAction(VT)) {
2575 default: assert(0 && "Unknown type action!");
2577 RetTys.push_back(VT);
2580 RetTys.push_back(getTypeToTransformTo(VT));
2583 if (VT != MVT::Vector) {
2584 // If this is a large integer, it needs to be reassembled from small
2585 // integers. Figure out what the source elt type is and how many small
2587 MVT::ValueType NVT = getTypeToTransformTo(VT);
2588 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2589 for (unsigned i = 0; i != NumVals; ++i)
2590 RetTys.push_back(NVT);
2592 // Otherwise, this is a vector type. We only support legal vectors
2594 const PackedType *PTy = cast<PackedType>(RetTy);
2595 unsigned NumElems = PTy->getNumElements();
2596 const Type *EltTy = PTy->getElementType();
2598 // Figure out if there is a Packed type corresponding to this Vector
2599 // type. If so, convert to the packed type.
2600 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2601 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2602 RetTys.push_back(TVT);
2604 assert(0 && "Don't support illegal by-val vector call results yet!");
2611 RetTys.push_back(MVT::Other); // Always has a chain.
2613 // Finally, create the CALL node.
2614 SDOperand Res = DAG.getNode(ISD::CALL, RetTys, Ops);
2616 // This returns a pair of operands. The first element is the
2617 // return value for the function (if RetTy is not VoidTy). The second
2618 // element is the outgoing token chain.
2620 if (RetTys.size() != 1) {
2621 MVT::ValueType VT = getValueType(RetTy);
2622 if (RetTys.size() == 2) {
2625 // If this value was promoted, truncate it down.
2626 if (ResVal.getValueType() != VT) {
2627 if (VT == MVT::Vector) {
2628 // Insert a VBITCONVERT to convert from the packed result type to the
2629 // MVT::Vector type.
2630 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
2631 const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
2633 // Figure out if there is a Packed type corresponding to this Vector
2634 // type. If so, convert to the packed type.
2635 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2636 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2637 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
2638 // "N x PTyElementVT" MVT::Vector type.
2639 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
2640 DAG.getConstant(NumElems, MVT::i32),
2641 DAG.getValueType(getValueType(EltTy)));
2645 } else if (MVT::isInteger(VT)) {
2646 unsigned AssertOp = RetTy->isSigned() ?
2647 ISD::AssertSext : ISD::AssertZext;
2648 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
2649 DAG.getValueType(VT));
2650 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
2652 assert(MVT::isFloatingPoint(VT));
2653 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
2656 } else if (RetTys.size() == 3) {
2657 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
2658 Res.getValue(0), Res.getValue(1));
2661 assert(0 && "Case not handled yet!");
2665 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
2670 // It is always conservatively correct for llvm.returnaddress and
2671 // llvm.frameaddress to return 0.
2673 // FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
2674 // expanded to 0 if the target wants.
2675 std::pair<SDOperand, SDOperand>
2676 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
2677 unsigned Depth, SelectionDAG &DAG) {
2678 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
2681 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2682 assert(0 && "LowerOperation not implemented for this target!");
2687 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
2688 SelectionDAG &DAG) {
2689 assert(0 && "CustomPromoteOperation not implemented for this target!");
2694 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
2695 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
2696 std::pair<SDOperand,SDOperand> Result =
2697 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
2698 setValue(&I, Result.first);
2699 DAG.setRoot(Result.second);
2702 /// getMemsetValue - Vectorized representation of the memset value
2704 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
2705 SelectionDAG &DAG) {
2706 MVT::ValueType CurVT = VT;
2707 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2708 uint64_t Val = C->getValue() & 255;
2710 while (CurVT != MVT::i8) {
2711 Val = (Val << Shift) | Val;
2713 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2715 return DAG.getConstant(Val, VT);
2717 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
2719 while (CurVT != MVT::i8) {
2721 DAG.getNode(ISD::OR, VT,
2722 DAG.getNode(ISD::SHL, VT, Value,
2723 DAG.getConstant(Shift, MVT::i8)), Value);
2725 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2732 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2733 /// used when a memcpy is turned into a memset when the source is a constant
2735 static SDOperand getMemsetStringVal(MVT::ValueType VT,
2736 SelectionDAG &DAG, TargetLowering &TLI,
2737 std::string &Str, unsigned Offset) {
2738 MVT::ValueType CurVT = VT;
2740 unsigned MSB = getSizeInBits(VT) / 8;
2741 if (TLI.isLittleEndian())
2742 Offset = Offset + MSB - 1;
2743 for (unsigned i = 0; i != MSB; ++i) {
2744 Val = (Val << 8) | Str[Offset];
2745 Offset += TLI.isLittleEndian() ? -1 : 1;
2747 return DAG.getConstant(Val, VT);
2750 /// getMemBasePlusOffset - Returns base and offset node for the
2751 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
2752 SelectionDAG &DAG, TargetLowering &TLI) {
2753 MVT::ValueType VT = Base.getValueType();
2754 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
2757 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
2758 /// to replace the memset / memcpy is below the threshold. It also returns the
2759 /// types of the sequence of memory ops to perform memset / memcpy.
2760 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
2761 unsigned Limit, uint64_t Size,
2762 unsigned Align, TargetLowering &TLI) {
2765 if (TLI.allowsUnalignedMemoryAccesses()) {
2768 switch (Align & 7) {
2784 MVT::ValueType LVT = MVT::i64;
2785 while (!TLI.isTypeLegal(LVT))
2786 LVT = (MVT::ValueType)((unsigned)LVT - 1);
2787 assert(MVT::isInteger(LVT));
2792 unsigned NumMemOps = 0;
2794 unsigned VTSize = getSizeInBits(VT) / 8;
2795 while (VTSize > Size) {
2796 VT = (MVT::ValueType)((unsigned)VT - 1);
2799 assert(MVT::isInteger(VT));
2801 if (++NumMemOps > Limit)
2803 MemOps.push_back(VT);
2810 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
2811 SDOperand Op1 = getValue(I.getOperand(1));
2812 SDOperand Op2 = getValue(I.getOperand(2));
2813 SDOperand Op3 = getValue(I.getOperand(3));
2814 SDOperand Op4 = getValue(I.getOperand(4));
2815 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
2816 if (Align == 0) Align = 1;
2818 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
2819 std::vector<MVT::ValueType> MemOps;
2821 // Expand memset / memcpy to a series of load / store ops
2822 // if the size operand falls below a certain threshold.
2823 std::vector<SDOperand> OutChains;
2825 default: break; // Do nothing for now.
2827 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
2828 Size->getValue(), Align, TLI)) {
2829 unsigned NumMemOps = MemOps.size();
2830 unsigned Offset = 0;
2831 for (unsigned i = 0; i < NumMemOps; i++) {
2832 MVT::ValueType VT = MemOps[i];
2833 unsigned VTSize = getSizeInBits(VT) / 8;
2834 SDOperand Value = getMemsetValue(Op2, VT, DAG);
2835 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(),
2837 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
2838 DAG.getSrcValue(I.getOperand(1), Offset));
2839 OutChains.push_back(Store);
2846 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
2847 Size->getValue(), Align, TLI)) {
2848 unsigned NumMemOps = MemOps.size();
2849 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
2850 GlobalAddressSDNode *G = NULL;
2852 bool CopyFromStr = false;
2854 if (Op2.getOpcode() == ISD::GlobalAddress)
2855 G = cast<GlobalAddressSDNode>(Op2);
2856 else if (Op2.getOpcode() == ISD::ADD &&
2857 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
2858 Op2.getOperand(1).getOpcode() == ISD::Constant) {
2859 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
2860 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
2863 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
2865 Str = GV->getStringValue(false);
2873 for (unsigned i = 0; i < NumMemOps; i++) {
2874 MVT::ValueType VT = MemOps[i];
2875 unsigned VTSize = getSizeInBits(VT) / 8;
2876 SDOperand Value, Chain, Store;
2879 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
2882 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2883 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2884 DAG.getSrcValue(I.getOperand(1), DstOff));
2886 Value = DAG.getLoad(VT, getRoot(),
2887 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
2888 DAG.getSrcValue(I.getOperand(2), SrcOff));
2889 Chain = Value.getValue(1);
2891 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2892 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2893 DAG.getSrcValue(I.getOperand(1), DstOff));
2895 OutChains.push_back(Store);
2904 if (!OutChains.empty()) {
2905 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
2910 std::vector<SDOperand> Ops;
2911 Ops.push_back(getRoot());
2916 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
2919 //===----------------------------------------------------------------------===//
2920 // SelectionDAGISel code
2921 //===----------------------------------------------------------------------===//
2923 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
2924 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
2927 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
2928 // FIXME: we only modify the CFG to split critical edges. This
2929 // updates dom and loop info.
2933 /// OptimizeNoopCopyExpression - We have determined that the specified cast
2934 /// instruction is a noop copy (e.g. it's casting from one pointer type to
2935 /// another, int->uint, or int->sbyte on PPC.
2937 /// Return true if any changes are made.
2938 static bool OptimizeNoopCopyExpression(CastInst *CI) {
2939 BasicBlock *DefBB = CI->getParent();
2941 /// InsertedCasts - Only insert a cast in each block once.
2942 std::map<BasicBlock*, CastInst*> InsertedCasts;
2944 bool MadeChange = false;
2945 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
2947 Use &TheUse = UI.getUse();
2948 Instruction *User = cast<Instruction>(*UI);
2950 // Figure out which BB this cast is used in. For PHI's this is the
2951 // appropriate predecessor block.
2952 BasicBlock *UserBB = User->getParent();
2953 if (PHINode *PN = dyn_cast<PHINode>(User)) {
2954 unsigned OpVal = UI.getOperandNo()/2;
2955 UserBB = PN->getIncomingBlock(OpVal);
2958 // Preincrement use iterator so we don't invalidate it.
2961 // If this user is in the same block as the cast, don't change the cast.
2962 if (UserBB == DefBB) continue;
2964 // If we have already inserted a cast into this block, use it.
2965 CastInst *&InsertedCast = InsertedCasts[UserBB];
2967 if (!InsertedCast) {
2968 BasicBlock::iterator InsertPt = UserBB->begin();
2969 while (isa<PHINode>(InsertPt)) ++InsertPt;
2972 new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
2976 // Replace a use of the cast with a use of the new casat.
2977 TheUse = InsertedCast;
2980 // If we removed all uses, nuke the cast.
2981 if (CI->use_empty())
2982 CI->eraseFromParent();
2987 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
2988 /// casting to the type of GEPI.
2989 static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
2990 Instruction *GEPI, Value *Ptr,
2992 if (V) return V; // Already computed.
2994 BasicBlock::iterator InsertPt;
2995 if (BB == GEPI->getParent()) {
2996 // If insert into the GEP's block, insert right after the GEP.
3000 // Otherwise, insert at the top of BB, after any PHI nodes
3001 InsertPt = BB->begin();
3002 while (isa<PHINode>(InsertPt)) ++InsertPt;
3005 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3006 // BB so that there is only one value live across basic blocks (the cast
3008 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3009 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3010 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3012 // Add the offset, cast it to the right type.
3013 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
3014 return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
3017 /// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3018 /// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
3019 /// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3020 /// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
3021 /// sink PtrOffset into user blocks where doing so will likely allow us to fold
3022 /// the constant add into a load or store instruction. Additionally, if a user
3023 /// is a pointer-pointer cast, we look through it to find its users.
3024 static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3025 Constant *PtrOffset, BasicBlock *DefBB,
3026 GetElementPtrInst *GEPI,
3027 std::map<BasicBlock*,Instruction*> &InsertedExprs) {
3028 while (!RepPtr->use_empty()) {
3029 Instruction *User = cast<Instruction>(RepPtr->use_back());
3031 // If the user is a Pointer-Pointer cast, recurse.
3032 if (isa<CastInst>(User) && isa<PointerType>(User->getType())) {
3033 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3035 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
3036 // could invalidate an iterator.
3037 User->setOperand(0, UndefValue::get(RepPtr->getType()));
3041 // If this is a load of the pointer, or a store through the pointer, emit
3042 // the increment into the load/store block.
3043 Instruction *NewVal;
3044 if (isa<LoadInst>(User) ||
3045 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3046 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3047 User->getParent(), GEPI,
3050 // If this use is not foldable into the addressing mode, use a version
3051 // emitted in the GEP block.
3052 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3056 if (GEPI->getType() != RepPtr->getType()) {
3057 BasicBlock::iterator IP = NewVal;
3059 NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP);
3061 User->replaceUsesOfWith(RepPtr, NewVal);
3066 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3067 /// selection, we want to be a bit careful about some things. In particular, if
3068 /// we have a GEP instruction that is used in a different block than it is
3069 /// defined, the addressing expression of the GEP cannot be folded into loads or
3070 /// stores that use it. In this case, decompose the GEP and move constant
3071 /// indices into blocks that use it.
3072 static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
3073 const TargetData *TD) {
3074 // If this GEP is only used inside the block it is defined in, there is no
3075 // need to rewrite it.
3076 bool isUsedOutsideDefBB = false;
3077 BasicBlock *DefBB = GEPI->getParent();
3078 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3080 if (cast<Instruction>(*UI)->getParent() != DefBB) {
3081 isUsedOutsideDefBB = true;
3085 if (!isUsedOutsideDefBB) return false;
3087 // If this GEP has no non-zero constant indices, there is nothing we can do,
3089 bool hasConstantIndex = false;
3090 bool hasVariableIndex = false;
3091 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3092 E = GEPI->op_end(); OI != E; ++OI) {
3093 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
3094 if (CI->getRawValue()) {
3095 hasConstantIndex = true;
3099 hasVariableIndex = true;
3103 // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3104 if (!hasConstantIndex && !hasVariableIndex) {
3105 Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(),
3106 GEPI->getName(), GEPI);
3107 GEPI->replaceAllUsesWith(NC);
3108 GEPI->eraseFromParent();
3112 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
3113 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3116 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
3117 // constant offset (which we now know is non-zero) and deal with it later.
3118 uint64_t ConstantOffset = 0;
3119 const Type *UIntPtrTy = TD->getIntPtrType();
3120 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3121 const Type *Ty = GEPI->getOperand(0)->getType();
3123 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3124 E = GEPI->op_end(); OI != E; ++OI) {
3126 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3127 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
3129 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
3130 Ty = StTy->getElementType(Field);
3132 Ty = cast<SequentialType>(Ty)->getElementType();
3134 // Handle constant subscripts.
3135 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3136 if (CI->getRawValue() == 0) continue;
3138 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
3139 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
3141 ConstantOffset+=TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
3145 // Ptr = Ptr + Idx * ElementSize;
3147 // Cast Idx to UIntPtrTy if needed.
3148 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
3150 uint64_t ElementSize = TD->getTypeSize(Ty);
3151 // Mask off bits that should not be set.
3152 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3153 Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize);
3155 // Multiply by the element size and add to the base.
3156 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3157 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3161 // Make sure that the offset fits in uintptr_t.
3162 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3163 Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset);
3165 // Okay, we have now emitted all of the variable index parts to the BB that
3166 // the GEP is defined in. Loop over all of the using instructions, inserting
3167 // an "add Ptr, ConstantOffset" into each block that uses it and update the
3168 // instruction to use the newly computed value, making GEPI dead. When the
3169 // user is a load or store instruction address, we emit the add into the user
3170 // block, otherwise we use a canonical version right next to the gep (these
3171 // won't be foldable as addresses, so we might as well share the computation).
3173 std::map<BasicBlock*,Instruction*> InsertedExprs;
3174 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3176 // Finally, the GEP is dead, remove it.
3177 GEPI->eraseFromParent();
3182 bool SelectionDAGISel::runOnFunction(Function &Fn) {
3183 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3184 RegMap = MF.getSSARegMap();
3185 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
3187 // First, split all critical edges for PHI nodes with incoming values that are
3188 // constants, this way the load of the constant into a vreg will not be placed
3189 // into MBBs that are used some other way.
3191 // In this pass we also look for GEP and cast instructions that are used
3192 // across basic blocks and rewrite them to improve basic-block-at-a-time
3196 bool MadeChange = true;
3197 while (MadeChange) {
3199 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
3201 BasicBlock::iterator BBI;
3202 for (BBI = BB->begin(); (PN = dyn_cast<PHINode>(BBI)); ++BBI)
3203 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
3204 if (isa<Constant>(PN->getIncomingValue(i)))
3205 SplitCriticalEdge(PN->getIncomingBlock(i), BB);
3207 for (BasicBlock::iterator E = BB->end(); BBI != E; ) {
3208 Instruction *I = BBI++;
3209 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
3210 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
3211 } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
3212 // If this is a noop copy, sink it into user blocks to reduce the number
3213 // of virtual registers that must be created and coallesced.
3214 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
3215 MVT::ValueType DstVT = TLI.getValueType(CI->getType());
3217 // This is an fp<->int conversion?
3218 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
3221 // If this is an extension, it will be a zero or sign extension, which
3223 if (SrcVT < DstVT) continue;
3225 // If these values will be promoted, find out what they will be promoted
3226 // to. This helps us consider truncates on PPC as noop copies when they
3228 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
3229 SrcVT = TLI.getTypeToTransformTo(SrcVT);
3230 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
3231 DstVT = TLI.getTypeToTransformTo(DstVT);
3233 // If, after promotion, these are the same types, this is a noop copy.
3235 MadeChange |= OptimizeNoopCopyExpression(CI);
3241 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
3243 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
3244 SelectBasicBlock(I, MF, FuncInfo);
3250 SDOperand SelectionDAGISel::
3251 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
3252 SDOperand Op = SDL.getValue(V);
3253 assert((Op.getOpcode() != ISD::CopyFromReg ||
3254 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
3255 "Copy from a reg to the same reg!");
3257 // If this type is not legal, we must make sure to not create an invalid
3259 MVT::ValueType SrcVT = Op.getValueType();
3260 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
3261 SelectionDAG &DAG = SDL.DAG;
3262 if (SrcVT == DestVT) {
3263 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3264 } else if (SrcVT == MVT::Vector) {
3265 // Handle copies from generic vectors to registers.
3266 MVT::ValueType PTyElementVT, PTyLegalElementVT;
3267 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
3268 PTyElementVT, PTyLegalElementVT);
3270 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
3271 // MVT::Vector type.
3272 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
3273 DAG.getConstant(NE, MVT::i32),
3274 DAG.getValueType(PTyElementVT));
3276 // Loop over all of the elements of the resultant vector,
3277 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
3278 // copying them into output registers.
3279 std::vector<SDOperand> OutChains;
3280 SDOperand Root = SDL.getRoot();
3281 for (unsigned i = 0; i != NE; ++i) {
3282 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
3283 Op, DAG.getConstant(i, MVT::i32));
3284 if (PTyElementVT == PTyLegalElementVT) {
3285 // Elements are legal.
3286 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3287 } else if (PTyLegalElementVT > PTyElementVT) {
3288 // Elements are promoted.
3289 if (MVT::isFloatingPoint(PTyLegalElementVT))
3290 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
3292 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
3293 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3295 // Elements are expanded.
3296 // The src value is expanded into multiple registers.
3297 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3298 Elt, DAG.getConstant(0, MVT::i32));
3299 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3300 Elt, DAG.getConstant(1, MVT::i32));
3301 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
3302 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
3305 return DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
3306 } else if (SrcVT < DestVT) {
3307 // The src value is promoted to the register.
3308 if (MVT::isFloatingPoint(SrcVT))
3309 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
3311 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
3312 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3314 // The src value is expanded into multiple registers.
3315 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3316 Op, DAG.getConstant(0, MVT::i32));
3317 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3318 Op, DAG.getConstant(1, MVT::i32));
3319 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
3320 return DAG.getCopyToReg(Op, Reg+1, Hi);
3324 void SelectionDAGISel::
3325 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
3326 std::vector<SDOperand> &UnorderedChains) {
3327 // If this is the entry block, emit arguments.
3328 Function &F = *BB->getParent();
3329 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
3330 SDOperand OldRoot = SDL.DAG.getRoot();
3331 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
3334 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
3336 if (!AI->use_empty()) {
3337 SDL.setValue(AI, Args[a]);
3339 // If this argument is live outside of the entry block, insert a copy from
3340 // whereever we got it to the vreg that other BB's will reference it as.
3341 if (FuncInfo.ValueMap.count(AI)) {
3343 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
3344 UnorderedChains.push_back(Copy);
3348 // Finally, if the target has anything special to do, allow it to do so.
3349 // FIXME: this should insert code into the DAG!
3350 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
3353 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3354 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
3355 FunctionLoweringInfo &FuncInfo) {
3356 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
3358 std::vector<SDOperand> UnorderedChains;
3360 // Lower any arguments needed in this block if this is the entry block.
3361 if (LLVMBB == &LLVMBB->getParent()->front())
3362 LowerArguments(LLVMBB, SDL, UnorderedChains);
3364 BB = FuncInfo.MBBMap[LLVMBB];
3365 SDL.setCurrentBasicBlock(BB);
3367 // Lower all of the non-terminator instructions.
3368 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3372 // Ensure that all instructions which are used outside of their defining
3373 // blocks are available as virtual registers.
3374 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
3375 if (!I->use_empty() && !isa<PHINode>(I)) {
3376 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
3377 if (VMI != FuncInfo.ValueMap.end())
3378 UnorderedChains.push_back(
3379 CopyValueToVirtualRegister(SDL, I, VMI->second));
3382 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
3383 // ensure constants are generated when needed. Remember the virtual registers
3384 // that need to be added to the Machine PHI nodes as input. We cannot just
3385 // directly add them, because expansion might result in multiple MBB's for one
3386 // BB. As such, the start of the BB might correspond to a different MBB than
3390 // Emit constants only once even if used by multiple PHI nodes.
3391 std::map<Constant*, unsigned> ConstantsOut;
3393 // Check successor nodes PHI nodes that expect a constant to be available from
3395 TerminatorInst *TI = LLVMBB->getTerminator();
3396 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
3397 BasicBlock *SuccBB = TI->getSuccessor(succ);
3398 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
3401 // At this point we know that there is a 1-1 correspondence between LLVM PHI
3402 // nodes and Machine PHI nodes, but the incoming operands have not been
3404 for (BasicBlock::iterator I = SuccBB->begin();
3405 (PN = dyn_cast<PHINode>(I)); ++I)
3406 if (!PN->use_empty()) {
3408 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
3409 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
3410 unsigned &RegOut = ConstantsOut[C];
3412 RegOut = FuncInfo.CreateRegForValue(C);
3413 UnorderedChains.push_back(
3414 CopyValueToVirtualRegister(SDL, C, RegOut));
3418 Reg = FuncInfo.ValueMap[PHIOp];
3420 assert(isa<AllocaInst>(PHIOp) &&
3421 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
3422 "Didn't codegen value into a register!??");
3423 Reg = FuncInfo.CreateRegForValue(PHIOp);
3424 UnorderedChains.push_back(
3425 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
3429 // Remember that this register needs to added to the machine PHI node as
3430 // the input for this MBB.
3431 MVT::ValueType VT = TLI.getValueType(PN->getType());
3432 unsigned NumElements;
3433 if (VT != MVT::Vector)
3434 NumElements = TLI.getNumElements(VT);
3436 MVT::ValueType VT1,VT2;
3438 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
3441 for (unsigned i = 0, e = NumElements; i != e; ++i)
3442 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
3445 ConstantsOut.clear();
3447 // Turn all of the unordered chains into one factored node.
3448 if (!UnorderedChains.empty()) {
3449 SDOperand Root = SDL.getRoot();
3450 if (Root.getOpcode() != ISD::EntryToken) {
3451 unsigned i = 0, e = UnorderedChains.size();
3452 for (; i != e; ++i) {
3453 assert(UnorderedChains[i].Val->getNumOperands() > 1);
3454 if (UnorderedChains[i].Val->getOperand(0) == Root)
3455 break; // Don't add the root if we already indirectly depend on it.
3459 UnorderedChains.push_back(Root);
3461 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
3464 // Lower the terminator after the copies are emitted.
3465 SDL.visit(*LLVMBB->getTerminator());
3467 // Copy over any CaseBlock records that may now exist due to SwitchInst
3468 // lowering, as well as any jump table information.
3469 SwitchCases.clear();
3470 SwitchCases = SDL.SwitchCases;
3473 // Make sure the root of the DAG is up-to-date.
3474 DAG.setRoot(SDL.getRoot());
3477 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
3478 // Run the DAG combiner in pre-legalize mode.
3481 DEBUG(std::cerr << "Lowered selection DAG:\n");
3484 // Second step, hack on the DAG until it only uses operations and types that
3485 // the target supports.
3488 DEBUG(std::cerr << "Legalized selection DAG:\n");
3491 // Run the DAG combiner in post-legalize mode.
3494 if (ViewISelDAGs) DAG.viewGraph();
3496 // Third, instruction select all of the operations to machine code, adding the
3497 // code to the MachineBasicBlock.
3498 InstructionSelectBasicBlock(DAG);
3500 DEBUG(std::cerr << "Selected machine code:\n");
3504 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
3505 FunctionLoweringInfo &FuncInfo) {
3506 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
3508 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3511 // First step, lower LLVM code to some DAG. This DAG may use operations and
3512 // types that are not supported by the target.
3513 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
3515 // Second step, emit the lowered DAG as machine code.
3516 CodeGenAndEmitDAG(DAG);
3519 // Next, now that we know what the last MBB the LLVM BB expanded is, update
3520 // PHI nodes in successors.
3521 if (SwitchCases.empty() && JT.Reg == 0) {
3522 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3523 MachineInstr *PHI = PHINodesToUpdate[i].first;
3524 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3525 "This is not a machine PHI node that we are updating!");
3526 PHI->addRegOperand(PHINodesToUpdate[i].second);
3527 PHI->addMachineBasicBlockOperand(BB);
3532 // If the JumpTable record is filled in, then we need to emit a jump table.
3533 // Updating the PHI nodes is tricky in this case, since we need to determine
3534 // whether the PHI is a successor of the range check MBB or the jump table MBB
3536 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
3537 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3539 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3540 MachineBasicBlock *RangeBB = BB;
3541 // Set the current basic block to the mbb we wish to insert the code into
3543 SDL.setCurrentBasicBlock(BB);
3545 SDL.visitJumpTable(JT);
3546 SDAG.setRoot(SDL.getRoot());
3547 CodeGenAndEmitDAG(SDAG);
3549 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3550 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3551 MachineBasicBlock *PHIBB = PHI->getParent();
3552 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3553 "This is not a machine PHI node that we are updating!");
3554 if (PHIBB == JT.Default) {
3555 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3556 PHI->addMachineBasicBlockOperand(RangeBB);
3558 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
3559 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3560 PHI->addMachineBasicBlockOperand(BB);
3566 // If we generated any switch lowering information, build and codegen any
3567 // additional DAGs necessary.
3568 for(unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
3569 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3571 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3572 // Set the current basic block to the mbb we wish to insert the code into
3573 BB = SwitchCases[i].ThisBB;
3574 SDL.setCurrentBasicBlock(BB);
3576 SDL.visitSwitchCase(SwitchCases[i]);
3577 SDAG.setRoot(SDL.getRoot());
3578 CodeGenAndEmitDAG(SDAG);
3579 // Iterate over the phi nodes, if there is a phi node in a successor of this
3580 // block (for instance, the default block), then add a pair of operands to
3581 // the phi node for this block, as if we were coming from the original
3582 // BB before switch expansion.
3583 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3584 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3585 MachineBasicBlock *PHIBB = PHI->getParent();
3586 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3587 "This is not a machine PHI node that we are updating!");
3588 if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
3589 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3590 PHI->addMachineBasicBlockOperand(BB);
3596 //===----------------------------------------------------------------------===//
3597 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
3598 /// target node in the graph.
3599 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
3600 if (ViewSchedDAGs) DAG.viewGraph();
3601 ScheduleDAG *SL = NULL;
3603 switch (ISHeuristic) {
3604 default: assert(0 && "Unrecognized scheduling heuristic");
3605 case defaultScheduling:
3606 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
3607 SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
3609 assert(TLI.getSchedulingPreference() ==
3610 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
3611 SL = createBURRListDAGScheduler(DAG, BB);
3615 SL = createBFS_DAGScheduler(DAG, BB);
3617 case simpleScheduling:
3618 SL = createSimpleDAGScheduler(false, DAG, BB);
3620 case simpleNoItinScheduling:
3621 SL = createSimpleDAGScheduler(true, DAG, BB);
3623 case listSchedulingBURR:
3624 SL = createBURRListDAGScheduler(DAG, BB);
3626 case listSchedulingTDRR:
3627 SL = createTDRRListDAGScheduler(DAG, BB);
3629 case listSchedulingTD:
3630 SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
3637 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
3638 return new HazardRecognizer();
3641 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
3642 /// by tblgen. Others should not call it.
3643 void SelectionDAGISel::
3644 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
3645 std::vector<SDOperand> InOps;
3646 std::swap(InOps, Ops);
3648 Ops.push_back(InOps[0]); // input chain.
3649 Ops.push_back(InOps[1]); // input asm string.
3651 unsigned i = 2, e = InOps.size();
3652 if (InOps[e-1].getValueType() == MVT::Flag)
3653 --e; // Don't process a flag operand if it is here.
3656 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
3657 if ((Flags & 7) != 4 /*MEM*/) {
3658 // Just skip over this operand, copying the operands verbatim.
3659 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
3660 i += (Flags >> 3) + 1;
3662 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
3663 // Otherwise, this is a memory operand. Ask the target to select it.
3664 std::vector<SDOperand> SelOps;
3665 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
3666 std::cerr << "Could not match memory address. Inline asm failure!\n";
3670 // Add this to the output node.
3671 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
3672 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
3677 // Add the flag input back if present.
3678 if (e != InOps.size())
3679 Ops.push_back(InOps.back());