1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/DebugInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetIntrinsicInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLowering.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/ADT/PostOrderIterator.h"
54 #include "llvm/ADT/Statistic.h"
58 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
59 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
60 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
61 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
62 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
66 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
67 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
68 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
69 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
70 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
71 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
72 STATISTIC(NumFastIselFailUnwind,"Fast isel fails on Unwind");
73 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
75 // Standard binary operators...
76 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
77 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
78 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
79 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
80 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
81 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
82 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
83 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
84 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
85 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
86 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
87 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
89 // Logical operators...
90 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
91 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
92 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
94 // Memory instructions...
95 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
96 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
97 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
98 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
99 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
100 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
101 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
103 // Convert instructions...
104 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
105 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
106 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
107 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
108 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
109 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
110 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
111 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
112 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
113 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
114 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
115 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
117 // Other instructions...
118 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
119 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
120 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
121 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
122 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
123 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
124 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
125 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
126 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
127 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
128 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
129 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
130 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
131 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
132 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
136 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
137 cl::desc("Enable verbose messages in the \"fast\" "
138 "instruction selector"));
140 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
141 cl::desc("Enable abort calls when \"fast\" instruction fails"));
145 cl::desc("use Machine Branch Probability Info"),
146 cl::init(true), cl::Hidden);
150 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
151 cl::desc("Pop up a window to show dags before the first "
152 "dag combine pass"));
154 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
155 cl::desc("Pop up a window to show dags before legalize types"));
157 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
158 cl::desc("Pop up a window to show dags before legalize"));
160 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
161 cl::desc("Pop up a window to show dags before the second "
162 "dag combine pass"));
164 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
165 cl::desc("Pop up a window to show dags before the post legalize types"
166 " dag combine pass"));
168 ViewISelDAGs("view-isel-dags", cl::Hidden,
169 cl::desc("Pop up a window to show isel dags as they are selected"));
171 ViewSchedDAGs("view-sched-dags", cl::Hidden,
172 cl::desc("Pop up a window to show sched dags as they are processed"));
174 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
175 cl::desc("Pop up a window to show SUnit dags after they are processed"));
177 static const bool ViewDAGCombine1 = false,
178 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
179 ViewDAGCombine2 = false,
180 ViewDAGCombineLT = false,
181 ViewISelDAGs = false, ViewSchedDAGs = false,
182 ViewSUnitDAGs = false;
185 //===---------------------------------------------------------------------===//
187 /// RegisterScheduler class - Track the registration of instruction schedulers.
189 //===---------------------------------------------------------------------===//
190 MachinePassRegistry RegisterScheduler::Registry;
192 //===---------------------------------------------------------------------===//
194 /// ISHeuristic command line option for instruction schedulers.
196 //===---------------------------------------------------------------------===//
197 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
198 RegisterPassParser<RegisterScheduler> >
199 ISHeuristic("pre-RA-sched",
200 cl::init(&createDefaultScheduler),
201 cl::desc("Instruction schedulers available (before register"
204 static RegisterScheduler
205 defaultListDAGScheduler("default", "Best scheduler for the target",
206 createDefaultScheduler);
209 //===--------------------------------------------------------------------===//
210 /// createDefaultScheduler - This creates an instruction scheduler appropriate
212 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
213 CodeGenOpt::Level OptLevel) {
214 const TargetLowering &TLI = IS->getTargetLowering();
216 if (OptLevel == CodeGenOpt::None)
217 return createSourceListDAGScheduler(IS, OptLevel);
218 if (TLI.getSchedulingPreference() == Sched::RegPressure)
219 return createBURRListDAGScheduler(IS, OptLevel);
220 if (TLI.getSchedulingPreference() == Sched::Hybrid)
221 return createHybridListDAGScheduler(IS, OptLevel);
222 assert(TLI.getSchedulingPreference() == Sched::ILP &&
223 "Unknown sched type!");
224 return createILPListDAGScheduler(IS, OptLevel);
228 // EmitInstrWithCustomInserter - This method should be implemented by targets
229 // that mark instructions with the 'usesCustomInserter' flag. These
230 // instructions are special in various ways, which require special support to
231 // insert. The specified MachineInstr is created but not inserted into any
232 // basic blocks, and this method is called to expand it into a sequence of
233 // instructions, potentially also creating new basic blocks and control flow.
234 // When new basic blocks are inserted and the edges from MBB to its successors
235 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
238 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
239 MachineBasicBlock *MBB) const {
241 dbgs() << "If a target marks an instruction with "
242 "'usesCustomInserter', it must implement "
243 "TargetLowering::EmitInstrWithCustomInserter!";
249 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
250 SDNode *Node) const {
251 assert(!MI->hasPostISelHook() &&
252 "If a target marks an instruction with 'hasPostISelHook', "
253 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
256 //===----------------------------------------------------------------------===//
257 // SelectionDAGISel code
258 //===----------------------------------------------------------------------===//
260 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
261 CodeGenOpt::Level OL) :
262 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
263 FuncInfo(new FunctionLoweringInfo(TLI)),
264 CurDAG(new SelectionDAG(tm)),
265 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
269 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
270 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
271 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
274 SelectionDAGISel::~SelectionDAGISel() {
280 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
281 AU.addRequired<AliasAnalysis>();
282 AU.addPreserved<AliasAnalysis>();
283 AU.addRequired<GCModuleInfo>();
284 AU.addPreserved<GCModuleInfo>();
285 if (UseMBPI && OptLevel != CodeGenOpt::None)
286 AU.addRequired<BranchProbabilityInfo>();
287 MachineFunctionPass::getAnalysisUsage(AU);
290 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
291 /// may trap on it. In this case we have to split the edge so that the path
292 /// through the predecessor block that doesn't go to the phi block doesn't
293 /// execute the possibly trapping instruction.
295 /// This is required for correctness, so it must be done at -O0.
297 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
298 // Loop for blocks with phi nodes.
299 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
300 PHINode *PN = dyn_cast<PHINode>(BB->begin());
301 if (PN == 0) continue;
304 // For each block with a PHI node, check to see if any of the input values
305 // are potentially trapping constant expressions. Constant expressions are
306 // the only potentially trapping value that can occur as the argument to a
308 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
309 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
310 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
311 if (CE == 0 || !CE->canTrap()) continue;
313 // The only case we have to worry about is when the edge is critical.
314 // Since this block has a PHI Node, we assume it has multiple input
315 // edges: check to see if the pred has multiple successors.
316 BasicBlock *Pred = PN->getIncomingBlock(i);
317 if (Pred->getTerminator()->getNumSuccessors() == 1)
320 // Okay, we have to split this edge.
321 SplitCriticalEdge(Pred->getTerminator(),
322 GetSuccessorNumber(Pred, BB), SDISel, true);
328 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
329 // Do some sanity-checking on the command-line options.
330 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
331 "-fast-isel-verbose requires -fast-isel");
332 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
333 "-fast-isel-abort requires -fast-isel");
335 const Function &Fn = *mf.getFunction();
336 const TargetInstrInfo &TII = *TM.getInstrInfo();
337 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
340 RegInfo = &MF->getRegInfo();
341 AA = &getAnalysis<AliasAnalysis>();
342 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
344 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
346 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
349 FuncInfo->set(Fn, *MF);
351 if (UseMBPI && OptLevel != CodeGenOpt::None)
352 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
358 SelectAllBasicBlocks(Fn);
360 // If the first basic block in the function has live ins that need to be
361 // copied into vregs, emit the copies into the top of the block before
362 // emitting the code for the block.
363 MachineBasicBlock *EntryMBB = MF->begin();
364 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
366 DenseMap<unsigned, unsigned> LiveInMap;
367 if (!FuncInfo->ArgDbgValues.empty())
368 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
369 E = RegInfo->livein_end(); LI != E; ++LI)
371 LiveInMap.insert(std::make_pair(LI->first, LI->second));
373 // Insert DBG_VALUE instructions for function arguments to the entry block.
374 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
375 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
376 unsigned Reg = MI->getOperand(0).getReg();
377 if (TargetRegisterInfo::isPhysicalRegister(Reg))
378 EntryMBB->insert(EntryMBB->begin(), MI);
380 MachineInstr *Def = RegInfo->getVRegDef(Reg);
381 MachineBasicBlock::iterator InsertPos = Def;
382 // FIXME: VR def may not be in entry block.
383 Def->getParent()->insert(llvm::next(InsertPos), MI);
386 // If Reg is live-in then update debug info to track its copy in a vreg.
387 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
388 if (LDI != LiveInMap.end()) {
389 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
390 MachineBasicBlock::iterator InsertPos = Def;
391 const MDNode *Variable =
392 MI->getOperand(MI->getNumOperands()-1).getMetadata();
393 unsigned Offset = MI->getOperand(1).getImm();
394 // Def is never a terminator here, so it is ok to increment InsertPos.
395 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
396 TII.get(TargetOpcode::DBG_VALUE))
397 .addReg(LDI->second, RegState::Debug)
398 .addImm(Offset).addMetadata(Variable);
400 // If this vreg is directly copied into an exported register then
401 // that COPY instructions also need DBG_VALUE, if it is the only
402 // user of LDI->second.
403 MachineInstr *CopyUseMI = NULL;
404 for (MachineRegisterInfo::use_iterator
405 UI = RegInfo->use_begin(LDI->second);
406 MachineInstr *UseMI = UI.skipInstruction();) {
407 if (UseMI->isDebugValue()) continue;
408 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
409 CopyUseMI = UseMI; continue;
411 // Otherwise this is another use or second copy use.
412 CopyUseMI = NULL; break;
415 MachineInstr *NewMI =
416 BuildMI(*MF, CopyUseMI->getDebugLoc(),
417 TII.get(TargetOpcode::DBG_VALUE))
418 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
419 .addImm(Offset).addMetadata(Variable);
420 MachineBasicBlock::iterator Pos = CopyUseMI;
421 EntryMBB->insertAfter(Pos, NewMI);
426 // Determine if there are any calls in this machine function.
427 MachineFrameInfo *MFI = MF->getFrameInfo();
428 if (!MFI->hasCalls()) {
429 for (MachineFunction::const_iterator
430 I = MF->begin(), E = MF->end(); I != E; ++I) {
431 const MachineBasicBlock *MBB = I;
432 for (MachineBasicBlock::const_iterator
433 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
434 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
436 if ((MCID.isCall() && !MCID.isReturn()) ||
437 II->isStackAligningInlineAsm()) {
438 MFI->setHasCalls(true);
446 // Determine if there is a call to setjmp in the machine function.
447 MF->setCallsSetJmp(Fn.callsFunctionThatReturnsTwice());
449 // Replace forward-declared registers with the registers containing
450 // the desired value.
451 MachineRegisterInfo &MRI = MF->getRegInfo();
452 for (DenseMap<unsigned, unsigned>::iterator
453 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
455 unsigned From = I->first;
456 unsigned To = I->second;
457 // If To is also scheduled to be replaced, find what its ultimate
460 DenseMap<unsigned, unsigned>::iterator J =
461 FuncInfo->RegFixups.find(To);
466 MRI.replaceRegWith(From, To);
469 // Release function-specific state. SDB and CurDAG are already cleared
476 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
477 BasicBlock::const_iterator End,
479 // Lower all of the non-terminator instructions. If a call is emitted
480 // as a tail call, cease emitting nodes for this block. Terminators
481 // are handled below.
482 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
485 // Make sure the root of the DAG is up-to-date.
486 CurDAG->setRoot(SDB->getControlRoot());
487 HadTailCall = SDB->HasTailCall;
490 // Final step, emit the lowered DAG as machine code.
494 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
495 SmallPtrSet<SDNode*, 128> VisitedNodes;
496 SmallVector<SDNode*, 128> Worklist;
498 Worklist.push_back(CurDAG->getRoot().getNode());
505 SDNode *N = Worklist.pop_back_val();
507 // If we've already seen this node, ignore it.
508 if (!VisitedNodes.insert(N))
511 // Otherwise, add all chain operands to the worklist.
512 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
513 if (N->getOperand(i).getValueType() == MVT::Other)
514 Worklist.push_back(N->getOperand(i).getNode());
516 // If this is a CopyToReg with a vreg dest, process it.
517 if (N->getOpcode() != ISD::CopyToReg)
520 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
521 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
524 // Ignore non-scalar or non-integer values.
525 SDValue Src = N->getOperand(2);
526 EVT SrcVT = Src.getValueType();
527 if (!SrcVT.isInteger() || SrcVT.isVector())
530 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
531 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
532 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
533 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
534 } while (!Worklist.empty());
537 void SelectionDAGISel::CodeGenAndEmitDAG() {
538 std::string GroupName;
539 if (TimePassesIsEnabled)
540 GroupName = "Instruction Selection and Scheduling";
541 std::string BlockName;
542 int BlockNumber = -1;
545 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
546 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
550 BlockNumber = FuncInfo->MBB->getNumber();
551 BlockName = MF->getFunction()->getName().str() + ":" +
552 FuncInfo->MBB->getBasicBlock()->getName().str();
554 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
555 << " '" << BlockName << "'\n"; CurDAG->dump());
557 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
559 // Run the DAG combiner in pre-legalize mode.
561 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
562 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
565 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
566 << " '" << BlockName << "'\n"; CurDAG->dump());
568 // Second step, hack on the DAG until it only uses operations and types that
569 // the target supports.
570 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
575 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
576 Changed = CurDAG->LegalizeTypes();
579 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
580 << " '" << BlockName << "'\n"; CurDAG->dump());
583 if (ViewDAGCombineLT)
584 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
586 // Run the DAG combiner in post-type-legalize mode.
588 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
589 TimePassesIsEnabled);
590 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
593 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
594 << " '" << BlockName << "'\n"; CurDAG->dump());
598 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
599 Changed = CurDAG->LegalizeVectors();
604 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
605 CurDAG->LegalizeTypes();
608 if (ViewDAGCombineLT)
609 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
611 // Run the DAG combiner in post-type-legalize mode.
613 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
614 TimePassesIsEnabled);
615 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
618 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
619 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
622 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
625 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
629 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
630 << " '" << BlockName << "'\n"; CurDAG->dump());
632 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
634 // Run the DAG combiner in post-legalize mode.
636 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
637 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
640 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
641 << " '" << BlockName << "'\n"; CurDAG->dump());
643 if (OptLevel != CodeGenOpt::None)
644 ComputeLiveOutVRegInfo();
646 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
648 // Third, instruction select all of the operations to machine code, adding the
649 // code to the MachineBasicBlock.
651 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
652 DoInstructionSelection();
655 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
656 << " '" << BlockName << "'\n"; CurDAG->dump());
658 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
660 // Schedule machine code.
661 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
663 NamedRegionTimer T("Instruction Scheduling", GroupName,
664 TimePassesIsEnabled);
665 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
668 if (ViewSUnitDAGs) Scheduler->viewGraph();
670 // Emit machine code to BB. This can change 'BB' to the last block being
672 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
674 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
676 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
677 FuncInfo->InsertPt = Scheduler->InsertPos;
680 // If the block was split, make sure we update any references that are used to
681 // update PHI nodes later on.
682 if (FirstMBB != LastMBB)
683 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
685 // Free the scheduler state.
687 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
688 TimePassesIsEnabled);
692 // Free the SelectionDAG state, now that we're finished with it.
696 void SelectionDAGISel::DoInstructionSelection() {
697 DEBUG(errs() << "===== Instruction selection begins: BB#"
698 << FuncInfo->MBB->getNumber()
699 << " '" << FuncInfo->MBB->getName() << "'\n");
703 // Select target instructions for the DAG.
705 // Number all nodes with a topological order and set DAGSize.
706 DAGSize = CurDAG->AssignTopologicalOrder();
708 // Create a dummy node (which is not added to allnodes), that adds
709 // a reference to the root node, preventing it from being deleted,
710 // and tracking any changes of the root.
711 HandleSDNode Dummy(CurDAG->getRoot());
712 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
715 // The AllNodes list is now topological-sorted. Visit the
716 // nodes by starting at the end of the list (the root of the
717 // graph) and preceding back toward the beginning (the entry
719 while (ISelPosition != CurDAG->allnodes_begin()) {
720 SDNode *Node = --ISelPosition;
721 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
722 // but there are currently some corner cases that it misses. Also, this
723 // makes it theoretically possible to disable the DAGCombiner.
724 if (Node->use_empty())
727 SDNode *ResNode = Select(Node);
729 // FIXME: This is pretty gross. 'Select' should be changed to not return
730 // anything at all and this code should be nuked with a tactical strike.
732 // If node should not be replaced, continue with the next one.
733 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
737 ReplaceUses(Node, ResNode);
739 // If after the replacement this node is not used any more,
740 // remove this dead node.
741 if (Node->use_empty()) { // Don't delete EntryToken, etc.
742 ISelUpdater ISU(ISelPosition);
743 CurDAG->RemoveDeadNode(Node, &ISU);
747 CurDAG->setRoot(Dummy.getValue());
750 DEBUG(errs() << "===== Instruction selection ends:\n");
752 PostprocessISelDAG();
755 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
756 /// do other setup for EH landing-pad blocks.
757 void SelectionDAGISel::PrepareEHLandingPad() {
758 MachineBasicBlock *MBB = FuncInfo->MBB;
760 // Add a label to mark the beginning of the landing pad. Deletion of the
761 // landing pad can thus be detected via the MachineModuleInfo.
762 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
764 // Assign the call site to the landing pad's begin label.
765 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
767 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
768 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
771 // Mark exception register as live in.
772 unsigned Reg = TLI.getExceptionAddressRegister();
773 if (Reg) MBB->addLiveIn(Reg);
775 // Mark exception selector register as live in.
776 Reg = TLI.getExceptionSelectorRegister();
777 if (Reg) MBB->addLiveIn(Reg);
779 // FIXME: Hack around an exception handling flaw (PR1508): the personality
780 // function and list of typeids logically belong to the invoke (or, if you
781 // like, the basic block containing the invoke), and need to be associated
782 // with it in the dwarf exception handling tables. Currently however the
783 // information is provided by an intrinsic (eh.selector) that can be moved
784 // to unexpected places by the optimizers: if the unwind edge is critical,
785 // then breaking it can result in the intrinsics being in the successor of
786 // the landing pad, not the landing pad itself. This results
787 // in exceptions not being caught because no typeids are associated with
788 // the invoke. This may not be the only way things can go wrong, but it
789 // is the only way we try to work around for the moment.
790 const BasicBlock *LLVMBB = MBB->getBasicBlock();
791 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
793 if (Br && Br->isUnconditional()) { // Critical edge?
794 BasicBlock::const_iterator I, E;
795 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
796 if (isa<EHSelectorInst>(I))
800 // No catch info found - try to extract some from the successor.
801 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
805 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
806 /// load into the specified FoldInst. Note that we could have a sequence where
807 /// multiple LLVM IR instructions are folded into the same machineinstr. For
808 /// example we could have:
809 /// A: x = load i32 *P
810 /// B: y = icmp A, 42
813 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
814 /// any other folded instructions) because it is between A and C.
816 /// If we succeed in folding the load into the operation, return true.
818 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
819 const Instruction *FoldInst,
821 // We know that the load has a single use, but don't know what it is. If it
822 // isn't one of the folded instructions, then we can't succeed here. Handle
823 // this by scanning the single-use users of the load until we get to FoldInst.
824 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
826 const Instruction *TheUser = LI->use_back();
827 while (TheUser != FoldInst && // Scan up until we find FoldInst.
828 // Stay in the right block.
829 TheUser->getParent() == FoldInst->getParent() &&
830 --MaxUsers) { // Don't scan too far.
831 // If there are multiple or no uses of this instruction, then bail out.
832 if (!TheUser->hasOneUse())
835 TheUser = TheUser->use_back();
838 // If we didn't find the fold instruction, then we failed to collapse the
840 if (TheUser != FoldInst)
843 // Don't try to fold volatile loads. Target has to deal with alignment
845 if (LI->isVolatile()) return false;
847 // Figure out which vreg this is going into. If there is no assigned vreg yet
848 // then there actually was no reference to it. Perhaps the load is referenced
849 // by a dead instruction.
850 unsigned LoadReg = FastIS->getRegForValue(LI);
854 // Check to see what the uses of this vreg are. If it has no uses, or more
855 // than one use (at the machine instr level) then we can't fold it.
856 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
857 if (RI == RegInfo->reg_end())
860 // See if there is exactly one use of the vreg. If there are multiple uses,
861 // then the instruction got lowered to multiple machine instructions or the
862 // use of the loaded value ended up being multiple operands of the result, in
863 // either case, we can't fold this.
864 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
865 if (PostRI != RegInfo->reg_end())
868 assert(RI.getOperand().isUse() &&
869 "The only use of the vreg must be a use, we haven't emitted the def!");
871 MachineInstr *User = &*RI;
873 // Set the insertion point properly. Folding the load can cause generation of
874 // other random instructions (like sign extends) for addressing modes, make
875 // sure they get inserted in a logical place before the new instruction.
876 FuncInfo->InsertPt = User;
877 FuncInfo->MBB = User->getParent();
879 // Ask the target to try folding the load.
880 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
883 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
884 /// side-effect free and is either dead or folded into a generated instruction.
885 /// Return false if it needs to be emitted.
886 static bool isFoldedOrDeadInstruction(const Instruction *I,
887 FunctionLoweringInfo *FuncInfo) {
888 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
889 !isa<TerminatorInst>(I) && // Terminators aren't folded.
890 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
891 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
892 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
896 static void collectFailStats(const Instruction *I) {
897 switch (I->getOpcode()) {
898 default: assert (0 && "<Invalid operator> ");
901 case Instruction::Ret: NumFastIselFailRet++; return;
902 case Instruction::Br: NumFastIselFailBr++; return;
903 case Instruction::Switch: NumFastIselFailSwitch++; return;
904 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
905 case Instruction::Invoke: NumFastIselFailInvoke++; return;
906 case Instruction::Resume: NumFastIselFailResume++; return;
907 case Instruction::Unwind: NumFastIselFailUnwind++; return;
908 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
910 // Standard binary operators...
911 case Instruction::Add: NumFastIselFailAdd++; return;
912 case Instruction::FAdd: NumFastIselFailFAdd++; return;
913 case Instruction::Sub: NumFastIselFailSub++; return;
914 case Instruction::FSub: NumFastIselFailFSub++; return;
915 case Instruction::Mul: NumFastIselFailMul++; return;
916 case Instruction::FMul: NumFastIselFailFMul++; return;
917 case Instruction::UDiv: NumFastIselFailUDiv++; return;
918 case Instruction::SDiv: NumFastIselFailSDiv++; return;
919 case Instruction::FDiv: NumFastIselFailFDiv++; return;
920 case Instruction::URem: NumFastIselFailURem++; return;
921 case Instruction::SRem: NumFastIselFailSRem++; return;
922 case Instruction::FRem: NumFastIselFailFRem++; return;
924 // Logical operators...
925 case Instruction::And: NumFastIselFailAnd++; return;
926 case Instruction::Or: NumFastIselFailOr++; return;
927 case Instruction::Xor: NumFastIselFailXor++; return;
929 // Memory instructions...
930 case Instruction::Alloca: NumFastIselFailAlloca++; return;
931 case Instruction::Load: NumFastIselFailLoad++; return;
932 case Instruction::Store: NumFastIselFailStore++; return;
933 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
934 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
935 case Instruction::Fence: NumFastIselFailFence++; return;
936 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
938 // Convert instructions...
939 case Instruction::Trunc: NumFastIselFailTrunc++; return;
940 case Instruction::ZExt: NumFastIselFailZExt++; return;
941 case Instruction::SExt: NumFastIselFailSExt++; return;
942 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
943 case Instruction::FPExt: NumFastIselFailFPExt++; return;
944 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
945 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
946 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
947 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
948 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
949 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
950 case Instruction::BitCast: NumFastIselFailBitCast++; return;
952 // Other instructions...
953 case Instruction::ICmp: NumFastIselFailICmp++; return;
954 case Instruction::FCmp: NumFastIselFailFCmp++; return;
955 case Instruction::PHI: NumFastIselFailPHI++; return;
956 case Instruction::Select: NumFastIselFailSelect++; return;
957 case Instruction::Call: NumFastIselFailCall++; return;
958 case Instruction::Shl: NumFastIselFailShl++; return;
959 case Instruction::LShr: NumFastIselFailLShr++; return;
960 case Instruction::AShr: NumFastIselFailAShr++; return;
961 case Instruction::VAArg: NumFastIselFailVAArg++; return;
962 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
963 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
964 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
965 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
966 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
967 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
973 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
974 // Initialize the Fast-ISel state, if needed.
975 FastISel *FastIS = 0;
976 if (TM.Options.EnableFastISel)
977 FastIS = TLI.createFastISel(*FuncInfo);
979 // Iterate over all basic blocks in the function.
980 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
981 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
982 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
983 const BasicBlock *LLVMBB = *I;
985 if (OptLevel != CodeGenOpt::None) {
986 bool AllPredsVisited = true;
987 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
989 if (!FuncInfo->VisitedBBs.count(*PI)) {
990 AllPredsVisited = false;
995 if (AllPredsVisited) {
996 for (BasicBlock::const_iterator I = LLVMBB->begin();
997 isa<PHINode>(I); ++I)
998 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
1000 for (BasicBlock::const_iterator I = LLVMBB->begin();
1001 isa<PHINode>(I); ++I)
1002 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));
1005 FuncInfo->VisitedBBs.insert(LLVMBB);
1008 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1009 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1011 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1012 BasicBlock::const_iterator const End = LLVMBB->end();
1013 BasicBlock::const_iterator BI = End;
1015 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1017 // Setup an EH landing-pad block.
1018 if (FuncInfo->MBB->isLandingPad())
1019 PrepareEHLandingPad();
1021 // Lower any arguments needed in this block if this is the entry block.
1022 if (LLVMBB == &Fn.getEntryBlock())
1023 LowerArguments(LLVMBB);
1025 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1027 FastIS->startNewBlock();
1029 // Emit code for any incoming arguments. This must happen before
1030 // beginning FastISel on the entry block.
1031 if (LLVMBB == &Fn.getEntryBlock()) {
1032 CurDAG->setRoot(SDB->getControlRoot());
1034 CodeGenAndEmitDAG();
1036 // If we inserted any instructions at the beginning, make a note of
1037 // where they are, so we can be sure to emit subsequent instructions
1039 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1040 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1042 FastIS->setLastLocalValue(0);
1045 unsigned NumFastIselRemaining = std::distance(Begin, End);
1046 // Do FastISel on as many instructions as possible.
1047 for (; BI != Begin; --BI) {
1048 const Instruction *Inst = llvm::prior(BI);
1050 // If we no longer require this instruction, skip it.
1051 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1052 --NumFastIselRemaining;
1056 // Bottom-up: reset the insert pos at the top, after any local-value
1058 FastIS->recomputeInsertPt();
1060 // Try to select the instruction with FastISel.
1061 if (FastIS->SelectInstruction(Inst)) {
1062 --NumFastIselRemaining;
1063 ++NumFastIselSuccess;
1064 // If fast isel succeeded, skip over all the folded instructions, and
1065 // then see if there is a load right before the selected instructions.
1066 // Try to fold the load if so.
1067 const Instruction *BeforeInst = Inst;
1068 while (BeforeInst != Begin) {
1069 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1070 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1073 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1074 BeforeInst->hasOneUse() &&
1075 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1076 // If we succeeded, don't re-select the load.
1077 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1078 --NumFastIselRemaining;
1079 ++NumFastIselSuccess;
1085 collectFailStats(Inst);
1088 // Then handle certain instructions as single-LLVM-Instruction blocks.
1089 if (isa<CallInst>(Inst)) {
1091 if (EnableFastISelVerbose || EnableFastISelAbort) {
1092 dbgs() << "FastISel missed call: ";
1096 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1097 unsigned &R = FuncInfo->ValueMap[Inst];
1099 R = FuncInfo->CreateRegs(Inst->getType());
1102 bool HadTailCall = false;
1103 SelectBasicBlock(Inst, BI, HadTailCall);
1105 // Recompute NumFastIselRemaining as Selection DAG instruction
1106 // selection may have handled the call, input args, etc.
1107 unsigned RemainingNow = std::distance(Begin, BI);
1108 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1110 // If the call was emitted as a tail call, we're done with the block.
1116 NumFastIselRemaining = RemainingNow;
1120 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1121 // Don't abort, and use a different message for terminator misses.
1122 NumFastIselFailures += NumFastIselRemaining;
1123 if (EnableFastISelVerbose || EnableFastISelAbort) {
1124 dbgs() << "FastISel missed terminator: ";
1128 NumFastIselFailures += NumFastIselRemaining;
1129 if (EnableFastISelVerbose || EnableFastISelAbort) {
1130 dbgs() << "FastISel miss: ";
1133 if (EnableFastISelAbort)
1134 // The "fast" selector couldn't handle something and bailed.
1135 // For the purpose of debugging, just abort.
1136 llvm_unreachable("FastISel didn't select the entire block");
1141 FastIS->recomputeInsertPt();
1147 ++NumFastIselBlocks;
1150 // Run SelectionDAG instruction selection on the remainder of the block
1151 // not handled by FastISel. If FastISel is not run, this is the entire
1154 SelectBasicBlock(Begin, BI, HadTailCall);
1158 FuncInfo->PHINodesToUpdate.clear();
1162 SDB->clearDanglingDebugInfo();
1166 SelectionDAGISel::FinishBasicBlock() {
1168 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1169 << FuncInfo->PHINodesToUpdate.size() << "\n";
1170 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1171 dbgs() << "Node " << i << " : ("
1172 << FuncInfo->PHINodesToUpdate[i].first
1173 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1175 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1176 // PHI nodes in successors.
1177 if (SDB->SwitchCases.empty() &&
1178 SDB->JTCases.empty() &&
1179 SDB->BitTestCases.empty()) {
1180 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1181 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1182 assert(PHI->isPHI() &&
1183 "This is not a machine PHI node that we are updating!");
1184 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1187 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1188 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1193 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1194 // Lower header first, if it wasn't already lowered
1195 if (!SDB->BitTestCases[i].Emitted) {
1196 // Set the current basic block to the mbb we wish to insert the code into
1197 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1198 FuncInfo->InsertPt = FuncInfo->MBB->end();
1200 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1201 CurDAG->setRoot(SDB->getRoot());
1203 CodeGenAndEmitDAG();
1206 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1207 // Set the current basic block to the mbb we wish to insert the code into
1208 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1209 FuncInfo->InsertPt = FuncInfo->MBB->end();
1212 SDB->visitBitTestCase(SDB->BitTestCases[i],
1213 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1214 SDB->BitTestCases[i].Reg,
1215 SDB->BitTestCases[i].Cases[j],
1218 SDB->visitBitTestCase(SDB->BitTestCases[i],
1219 SDB->BitTestCases[i].Default,
1220 SDB->BitTestCases[i].Reg,
1221 SDB->BitTestCases[i].Cases[j],
1225 CurDAG->setRoot(SDB->getRoot());
1227 CodeGenAndEmitDAG();
1231 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1233 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1234 MachineBasicBlock *PHIBB = PHI->getParent();
1235 assert(PHI->isPHI() &&
1236 "This is not a machine PHI node that we are updating!");
1237 // This is "default" BB. We have two jumps to it. From "header" BB and
1238 // from last "case" BB.
1239 if (PHIBB == SDB->BitTestCases[i].Default) {
1240 PHI->addOperand(MachineOperand::
1241 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1243 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1244 PHI->addOperand(MachineOperand::
1245 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1247 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1250 // One of "cases" BB.
1251 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1253 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1254 if (cBB->isSuccessor(PHIBB)) {
1255 PHI->addOperand(MachineOperand::
1256 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1258 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1263 SDB->BitTestCases.clear();
1265 // If the JumpTable record is filled in, then we need to emit a jump table.
1266 // Updating the PHI nodes is tricky in this case, since we need to determine
1267 // whether the PHI is a successor of the range check MBB or the jump table MBB
1268 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1269 // Lower header first, if it wasn't already lowered
1270 if (!SDB->JTCases[i].first.Emitted) {
1271 // Set the current basic block to the mbb we wish to insert the code into
1272 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1273 FuncInfo->InsertPt = FuncInfo->MBB->end();
1275 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1277 CurDAG->setRoot(SDB->getRoot());
1279 CodeGenAndEmitDAG();
1282 // Set the current basic block to the mbb we wish to insert the code into
1283 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1284 FuncInfo->InsertPt = FuncInfo->MBB->end();
1286 SDB->visitJumpTable(SDB->JTCases[i].second);
1287 CurDAG->setRoot(SDB->getRoot());
1289 CodeGenAndEmitDAG();
1292 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1294 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1295 MachineBasicBlock *PHIBB = PHI->getParent();
1296 assert(PHI->isPHI() &&
1297 "This is not a machine PHI node that we are updating!");
1298 // "default" BB. We can go there only from header BB.
1299 if (PHIBB == SDB->JTCases[i].second.Default) {
1301 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1304 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1306 // JT BB. Just iterate over successors here
1307 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1309 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1311 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1315 SDB->JTCases.clear();
1317 // If the switch block involved a branch to one of the actual successors, we
1318 // need to update PHI nodes in that block.
1319 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1320 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1321 assert(PHI->isPHI() &&
1322 "This is not a machine PHI node that we are updating!");
1323 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1325 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1326 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1330 // If we generated any switch lowering information, build and codegen any
1331 // additional DAGs necessary.
1332 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1333 // Set the current basic block to the mbb we wish to insert the code into
1334 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1335 FuncInfo->InsertPt = FuncInfo->MBB->end();
1337 // Determine the unique successors.
1338 SmallVector<MachineBasicBlock *, 2> Succs;
1339 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1340 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1341 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1343 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1344 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1345 CurDAG->setRoot(SDB->getRoot());
1347 CodeGenAndEmitDAG();
1349 // Remember the last block, now that any splitting is done, for use in
1350 // populating PHI nodes in successors.
1351 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1353 // Handle any PHI nodes in successors of this chunk, as if we were coming
1354 // from the original BB before switch expansion. Note that PHI nodes can
1355 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1356 // handle them the right number of times.
1357 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1358 FuncInfo->MBB = Succs[i];
1359 FuncInfo->InsertPt = FuncInfo->MBB->end();
1360 // FuncInfo->MBB may have been removed from the CFG if a branch was
1362 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1363 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1364 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1366 // This value for this PHI node is recorded in PHINodesToUpdate.
1367 for (unsigned pn = 0; ; ++pn) {
1368 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1369 "Didn't find PHI entry!");
1370 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1371 Phi->addOperand(MachineOperand::
1372 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1374 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1382 SDB->SwitchCases.clear();
1386 /// Create the scheduler. If a specific scheduler was specified
1387 /// via the SchedulerRegistry, use it, otherwise select the
1388 /// one preferred by the target.
1390 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1391 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1395 RegisterScheduler::setDefault(Ctor);
1398 return Ctor(this, OptLevel);
1401 //===----------------------------------------------------------------------===//
1402 // Helper functions used by the generated instruction selector.
1403 //===----------------------------------------------------------------------===//
1404 // Calls to these methods are generated by tblgen.
1406 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1407 /// the dag combiner simplified the 255, we still want to match. RHS is the
1408 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1409 /// specified in the .td file (e.g. 255).
1410 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1411 int64_t DesiredMaskS) const {
1412 const APInt &ActualMask = RHS->getAPIntValue();
1413 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1415 // If the actual mask exactly matches, success!
1416 if (ActualMask == DesiredMask)
1419 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1420 if (ActualMask.intersects(~DesiredMask))
1423 // Otherwise, the DAG Combiner may have proven that the value coming in is
1424 // either already zero or is not demanded. Check for known zero input bits.
1425 APInt NeededMask = DesiredMask & ~ActualMask;
1426 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1429 // TODO: check to see if missing bits are just not demanded.
1431 // Otherwise, this pattern doesn't match.
1435 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1436 /// the dag combiner simplified the 255, we still want to match. RHS is the
1437 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1438 /// specified in the .td file (e.g. 255).
1439 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1440 int64_t DesiredMaskS) const {
1441 const APInt &ActualMask = RHS->getAPIntValue();
1442 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1444 // If the actual mask exactly matches, success!
1445 if (ActualMask == DesiredMask)
1448 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1449 if (ActualMask.intersects(~DesiredMask))
1452 // Otherwise, the DAG Combiner may have proven that the value coming in is
1453 // either already zero or is not demanded. Check for known zero input bits.
1454 APInt NeededMask = DesiredMask & ~ActualMask;
1456 APInt KnownZero, KnownOne;
1457 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1459 // If all the missing bits in the or are already known to be set, match!
1460 if ((NeededMask & KnownOne) == NeededMask)
1463 // TODO: check to see if missing bits are just not demanded.
1465 // Otherwise, this pattern doesn't match.
1470 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1471 /// by tblgen. Others should not call it.
1472 void SelectionDAGISel::
1473 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1474 std::vector<SDValue> InOps;
1475 std::swap(InOps, Ops);
1477 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1478 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1479 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1480 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1482 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1483 if (InOps[e-1].getValueType() == MVT::Glue)
1484 --e; // Don't process a glue operand if it is here.
1487 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1488 if (!InlineAsm::isMemKind(Flags)) {
1489 // Just skip over this operand, copying the operands verbatim.
1490 Ops.insert(Ops.end(), InOps.begin()+i,
1491 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1492 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1494 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1495 "Memory operand with multiple values?");
1496 // Otherwise, this is a memory operand. Ask the target to select it.
1497 std::vector<SDValue> SelOps;
1498 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1499 report_fatal_error("Could not match memory address. Inline asm"
1502 // Add this to the output node.
1504 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1505 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1506 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1511 // Add the glue input back if present.
1512 if (e != InOps.size())
1513 Ops.push_back(InOps.back());
1516 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1519 static SDNode *findGlueUse(SDNode *N) {
1520 unsigned FlagResNo = N->getNumValues()-1;
1521 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1522 SDUse &Use = I.getUse();
1523 if (Use.getResNo() == FlagResNo)
1524 return Use.getUser();
1529 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1530 /// This function recursively traverses up the operand chain, ignoring
1532 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1533 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1534 bool IgnoreChains) {
1535 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1536 // greater than all of its (recursive) operands. If we scan to a point where
1537 // 'use' is smaller than the node we're scanning for, then we know we will
1540 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1541 // happen because we scan down to newly selected nodes in the case of glue
1543 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1546 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1547 // won't fail if we scan it again.
1548 if (!Visited.insert(Use))
1551 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1552 // Ignore chain uses, they are validated by HandleMergeInputChains.
1553 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1556 SDNode *N = Use->getOperand(i).getNode();
1558 if (Use == ImmedUse || Use == Root)
1559 continue; // We are not looking for immediate use.
1564 // Traverse up the operand chain.
1565 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1571 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1572 /// operand node N of U during instruction selection that starts at Root.
1573 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1574 SDNode *Root) const {
1575 if (OptLevel == CodeGenOpt::None) return false;
1576 return N.hasOneUse();
1579 /// IsLegalToFold - Returns true if the specific operand node N of
1580 /// U can be folded during instruction selection that starts at Root.
1581 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1582 CodeGenOpt::Level OptLevel,
1583 bool IgnoreChains) {
1584 if (OptLevel == CodeGenOpt::None) return false;
1586 // If Root use can somehow reach N through a path that that doesn't contain
1587 // U then folding N would create a cycle. e.g. In the following
1588 // diagram, Root can reach N through X. If N is folded into into Root, then
1589 // X is both a predecessor and a successor of U.
1600 // * indicates nodes to be folded together.
1602 // If Root produces glue, then it gets (even more) interesting. Since it
1603 // will be "glued" together with its glue use in the scheduler, we need to
1604 // check if it might reach N.
1623 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1624 // (call it Fold), then X is a predecessor of GU and a successor of
1625 // Fold. But since Fold and GU are glued together, this will create
1626 // a cycle in the scheduling graph.
1628 // If the node has glue, walk down the graph to the "lowest" node in the
1630 EVT VT = Root->getValueType(Root->getNumValues()-1);
1631 while (VT == MVT::Glue) {
1632 SDNode *GU = findGlueUse(Root);
1636 VT = Root->getValueType(Root->getNumValues()-1);
1638 // If our query node has a glue result with a use, we've walked up it. If
1639 // the user (which has already been selected) has a chain or indirectly uses
1640 // the chain, our WalkChainUsers predicate will not consider it. Because of
1641 // this, we cannot ignore chains in this predicate.
1642 IgnoreChains = false;
1646 SmallPtrSet<SDNode*, 16> Visited;
1647 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1650 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1651 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1652 SelectInlineAsmMemoryOperands(Ops);
1654 std::vector<EVT> VTs;
1655 VTs.push_back(MVT::Other);
1656 VTs.push_back(MVT::Glue);
1657 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1658 VTs, &Ops[0], Ops.size());
1660 return New.getNode();
1663 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1664 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1667 /// GetVBR - decode a vbr encoding whose top bit is set.
1668 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1669 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1670 assert(Val >= 128 && "Not a VBR");
1671 Val &= 127; // Remove first vbr bit.
1676 NextBits = MatcherTable[Idx++];
1677 Val |= (NextBits&127) << Shift;
1679 } while (NextBits & 128);
1685 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1686 /// interior glue and chain results to use the new glue and chain results.
1687 void SelectionDAGISel::
1688 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1689 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1691 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1692 bool isMorphNodeTo) {
1693 SmallVector<SDNode*, 4> NowDeadNodes;
1695 ISelUpdater ISU(ISelPosition);
1697 // Now that all the normal results are replaced, we replace the chain and
1698 // glue results if present.
1699 if (!ChainNodesMatched.empty()) {
1700 assert(InputChain.getNode() != 0 &&
1701 "Matched input chains but didn't produce a chain");
1702 // Loop over all of the nodes we matched that produced a chain result.
1703 // Replace all the chain results with the final chain we ended up with.
1704 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1705 SDNode *ChainNode = ChainNodesMatched[i];
1707 // If this node was already deleted, don't look at it.
1708 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1711 // Don't replace the results of the root node if we're doing a
1713 if (ChainNode == NodeToMatch && isMorphNodeTo)
1716 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1717 if (ChainVal.getValueType() == MVT::Glue)
1718 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1719 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1720 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1722 // If the node became dead and we haven't already seen it, delete it.
1723 if (ChainNode->use_empty() &&
1724 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1725 NowDeadNodes.push_back(ChainNode);
1729 // If the result produces glue, update any glue results in the matched
1730 // pattern with the glue result.
1731 if (InputGlue.getNode() != 0) {
1732 // Handle any interior nodes explicitly marked.
1733 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1734 SDNode *FRN = GlueResultNodesMatched[i];
1736 // If this node was already deleted, don't look at it.
1737 if (FRN->getOpcode() == ISD::DELETED_NODE)
1740 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1741 "Doesn't have a glue result");
1742 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1745 // If the node became dead and we haven't already seen it, delete it.
1746 if (FRN->use_empty() &&
1747 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1748 NowDeadNodes.push_back(FRN);
1752 if (!NowDeadNodes.empty())
1753 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1755 DEBUG(errs() << "ISEL: Match complete!\n");
1761 CR_LeadsToInteriorNode
1764 /// WalkChainUsers - Walk down the users of the specified chained node that is
1765 /// part of the pattern we're matching, looking at all of the users we find.
1766 /// This determines whether something is an interior node, whether we have a
1767 /// non-pattern node in between two pattern nodes (which prevent folding because
1768 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1769 /// between pattern nodes (in which case the TF becomes part of the pattern).
1771 /// The walk we do here is guaranteed to be small because we quickly get down to
1772 /// already selected nodes "below" us.
1774 WalkChainUsers(SDNode *ChainedNode,
1775 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1776 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1777 ChainResult Result = CR_Simple;
1779 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1780 E = ChainedNode->use_end(); UI != E; ++UI) {
1781 // Make sure the use is of the chain, not some other value we produce.
1782 if (UI.getUse().getValueType() != MVT::Other) continue;
1786 // If we see an already-selected machine node, then we've gone beyond the
1787 // pattern that we're selecting down into the already selected chunk of the
1789 if (User->isMachineOpcode() ||
1790 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1793 if (User->getOpcode() == ISD::CopyToReg ||
1794 User->getOpcode() == ISD::CopyFromReg ||
1795 User->getOpcode() == ISD::INLINEASM ||
1796 User->getOpcode() == ISD::EH_LABEL) {
1797 // If their node ID got reset to -1 then they've already been selected.
1798 // Treat them like a MachineOpcode.
1799 if (User->getNodeId() == -1)
1803 // If we have a TokenFactor, we handle it specially.
1804 if (User->getOpcode() != ISD::TokenFactor) {
1805 // If the node isn't a token factor and isn't part of our pattern, then it
1806 // must be a random chained node in between two nodes we're selecting.
1807 // This happens when we have something like:
1812 // Because we structurally match the load/store as a read/modify/write,
1813 // but the call is chained between them. We cannot fold in this case
1814 // because it would induce a cycle in the graph.
1815 if (!std::count(ChainedNodesInPattern.begin(),
1816 ChainedNodesInPattern.end(), User))
1817 return CR_InducesCycle;
1819 // Otherwise we found a node that is part of our pattern. For example in:
1823 // This would happen when we're scanning down from the load and see the
1824 // store as a user. Record that there is a use of ChainedNode that is
1825 // part of the pattern and keep scanning uses.
1826 Result = CR_LeadsToInteriorNode;
1827 InteriorChainedNodes.push_back(User);
1831 // If we found a TokenFactor, there are two cases to consider: first if the
1832 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1833 // uses of the TF are in our pattern) we just want to ignore it. Second,
1834 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1840 // | \ DAG's like cheese
1843 // [TokenFactor] [Op]
1850 // In this case, the TokenFactor becomes part of our match and we rewrite it
1851 // as a new TokenFactor.
1853 // To distinguish these two cases, do a recursive walk down the uses.
1854 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1856 // If the uses of the TokenFactor are just already-selected nodes, ignore
1857 // it, it is "below" our pattern.
1859 case CR_InducesCycle:
1860 // If the uses of the TokenFactor lead to nodes that are not part of our
1861 // pattern that are not selected, folding would turn this into a cycle,
1863 return CR_InducesCycle;
1864 case CR_LeadsToInteriorNode:
1865 break; // Otherwise, keep processing.
1868 // Okay, we know we're in the interesting interior case. The TokenFactor
1869 // is now going to be considered part of the pattern so that we rewrite its
1870 // uses (it may have uses that are not part of the pattern) with the
1871 // ultimate chain result of the generated code. We will also add its chain
1872 // inputs as inputs to the ultimate TokenFactor we create.
1873 Result = CR_LeadsToInteriorNode;
1874 ChainedNodesInPattern.push_back(User);
1875 InteriorChainedNodes.push_back(User);
1882 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1883 /// operation for when the pattern matched at least one node with a chains. The
1884 /// input vector contains a list of all of the chained nodes that we match. We
1885 /// must determine if this is a valid thing to cover (i.e. matching it won't
1886 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1887 /// be used as the input node chain for the generated nodes.
1889 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1890 SelectionDAG *CurDAG) {
1891 // Walk all of the chained nodes we've matched, recursively scanning down the
1892 // users of the chain result. This adds any TokenFactor nodes that are caught
1893 // in between chained nodes to the chained and interior nodes list.
1894 SmallVector<SDNode*, 3> InteriorChainedNodes;
1895 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1896 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1897 InteriorChainedNodes) == CR_InducesCycle)
1898 return SDValue(); // Would induce a cycle.
1901 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1902 // that we are interested in. Form our input TokenFactor node.
1903 SmallVector<SDValue, 3> InputChains;
1904 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1905 // Add the input chain of this node to the InputChains list (which will be
1906 // the operands of the generated TokenFactor) if it's not an interior node.
1907 SDNode *N = ChainNodesMatched[i];
1908 if (N->getOpcode() != ISD::TokenFactor) {
1909 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1912 // Otherwise, add the input chain.
1913 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1914 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1915 InputChains.push_back(InChain);
1919 // If we have a token factor, we want to add all inputs of the token factor
1920 // that are not part of the pattern we're matching.
1921 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1922 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1923 N->getOperand(op).getNode()))
1924 InputChains.push_back(N->getOperand(op));
1929 if (InputChains.size() == 1)
1930 return InputChains[0];
1931 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1932 MVT::Other, &InputChains[0], InputChains.size());
1935 /// MorphNode - Handle morphing a node in place for the selector.
1936 SDNode *SelectionDAGISel::
1937 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1938 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1939 // It is possible we're using MorphNodeTo to replace a node with no
1940 // normal results with one that has a normal result (or we could be
1941 // adding a chain) and the input could have glue and chains as well.
1942 // In this case we need to shift the operands down.
1943 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1944 // than the old isel though.
1945 int OldGlueResultNo = -1, OldChainResultNo = -1;
1947 unsigned NTMNumResults = Node->getNumValues();
1948 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1949 OldGlueResultNo = NTMNumResults-1;
1950 if (NTMNumResults != 1 &&
1951 Node->getValueType(NTMNumResults-2) == MVT::Other)
1952 OldChainResultNo = NTMNumResults-2;
1953 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1954 OldChainResultNo = NTMNumResults-1;
1956 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1957 // that this deletes operands of the old node that become dead.
1958 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1960 // MorphNodeTo can operate in two ways: if an existing node with the
1961 // specified operands exists, it can just return it. Otherwise, it
1962 // updates the node in place to have the requested operands.
1964 // If we updated the node in place, reset the node ID. To the isel,
1965 // this should be just like a newly allocated machine node.
1969 unsigned ResNumResults = Res->getNumValues();
1970 // Move the glue if needed.
1971 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1972 (unsigned)OldGlueResultNo != ResNumResults-1)
1973 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1974 SDValue(Res, ResNumResults-1));
1976 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1979 // Move the chain reference if needed.
1980 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1981 (unsigned)OldChainResultNo != ResNumResults-1)
1982 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1983 SDValue(Res, ResNumResults-1));
1985 // Otherwise, no replacement happened because the node already exists. Replace
1986 // Uses of the old node with the new one.
1988 CurDAG->ReplaceAllUsesWith(Node, Res);
1993 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1994 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1995 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1997 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1998 // Accept if it is exactly the same as a previously recorded node.
1999 unsigned RecNo = MatcherTable[MatcherIndex++];
2000 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2001 return N == RecordedNodes[RecNo].first;
2004 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2005 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2006 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2007 SelectionDAGISel &SDISel) {
2008 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2011 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2012 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2013 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2014 SelectionDAGISel &SDISel, SDNode *N) {
2015 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2018 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2019 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2021 uint16_t Opc = MatcherTable[MatcherIndex++];
2022 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2023 return N->getOpcode() == Opc;
2026 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2027 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2028 SDValue N, const TargetLowering &TLI) {
2029 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2030 if (N.getValueType() == VT) return true;
2032 // Handle the case when VT is iPTR.
2033 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2036 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2037 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2038 SDValue N, const TargetLowering &TLI,
2040 if (ChildNo >= N.getNumOperands())
2041 return false; // Match fails if out of range child #.
2042 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2046 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2047 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2049 return cast<CondCodeSDNode>(N)->get() ==
2050 (ISD::CondCode)MatcherTable[MatcherIndex++];
2053 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2054 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2055 SDValue N, const TargetLowering &TLI) {
2056 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2057 if (cast<VTSDNode>(N)->getVT() == VT)
2060 // Handle the case when VT is iPTR.
2061 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2064 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2065 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2067 int64_t Val = MatcherTable[MatcherIndex++];
2069 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2071 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2072 return C != 0 && C->getSExtValue() == Val;
2075 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2076 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2077 SDValue N, SelectionDAGISel &SDISel) {
2078 int64_t Val = MatcherTable[MatcherIndex++];
2080 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2082 if (N->getOpcode() != ISD::AND) return false;
2084 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2085 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2088 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2089 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2090 SDValue N, SelectionDAGISel &SDISel) {
2091 int64_t Val = MatcherTable[MatcherIndex++];
2093 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2095 if (N->getOpcode() != ISD::OR) return false;
2097 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2098 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2101 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2102 /// scope, evaluate the current node. If the current predicate is known to
2103 /// fail, set Result=true and return anything. If the current predicate is
2104 /// known to pass, set Result=false and return the MatcherIndex to continue
2105 /// with. If the current predicate is unknown, set Result=false and return the
2106 /// MatcherIndex to continue with.
2107 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2108 unsigned Index, SDValue N,
2109 bool &Result, SelectionDAGISel &SDISel,
2110 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2111 switch (Table[Index++]) {
2114 return Index-1; // Could not evaluate this predicate.
2115 case SelectionDAGISel::OPC_CheckSame:
2116 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2118 case SelectionDAGISel::OPC_CheckPatternPredicate:
2119 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2121 case SelectionDAGISel::OPC_CheckPredicate:
2122 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2124 case SelectionDAGISel::OPC_CheckOpcode:
2125 Result = !::CheckOpcode(Table, Index, N.getNode());
2127 case SelectionDAGISel::OPC_CheckType:
2128 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2130 case SelectionDAGISel::OPC_CheckChild0Type:
2131 case SelectionDAGISel::OPC_CheckChild1Type:
2132 case SelectionDAGISel::OPC_CheckChild2Type:
2133 case SelectionDAGISel::OPC_CheckChild3Type:
2134 case SelectionDAGISel::OPC_CheckChild4Type:
2135 case SelectionDAGISel::OPC_CheckChild5Type:
2136 case SelectionDAGISel::OPC_CheckChild6Type:
2137 case SelectionDAGISel::OPC_CheckChild7Type:
2138 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2139 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2141 case SelectionDAGISel::OPC_CheckCondCode:
2142 Result = !::CheckCondCode(Table, Index, N);
2144 case SelectionDAGISel::OPC_CheckValueType:
2145 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2147 case SelectionDAGISel::OPC_CheckInteger:
2148 Result = !::CheckInteger(Table, Index, N);
2150 case SelectionDAGISel::OPC_CheckAndImm:
2151 Result = !::CheckAndImm(Table, Index, N, SDISel);
2153 case SelectionDAGISel::OPC_CheckOrImm:
2154 Result = !::CheckOrImm(Table, Index, N, SDISel);
2162 /// FailIndex - If this match fails, this is the index to continue with.
2165 /// NodeStack - The node stack when the scope was formed.
2166 SmallVector<SDValue, 4> NodeStack;
2168 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2169 unsigned NumRecordedNodes;
2171 /// NumMatchedMemRefs - The number of matched memref entries.
2172 unsigned NumMatchedMemRefs;
2174 /// InputChain/InputGlue - The current chain/glue
2175 SDValue InputChain, InputGlue;
2177 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2178 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2183 SDNode *SelectionDAGISel::
2184 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2185 unsigned TableSize) {
2186 // FIXME: Should these even be selected? Handle these cases in the caller?
2187 switch (NodeToMatch->getOpcode()) {
2190 case ISD::EntryToken: // These nodes remain the same.
2191 case ISD::BasicBlock:
2193 //case ISD::VALUETYPE:
2194 //case ISD::CONDCODE:
2195 case ISD::HANDLENODE:
2196 case ISD::MDNODE_SDNODE:
2197 case ISD::TargetConstant:
2198 case ISD::TargetConstantFP:
2199 case ISD::TargetConstantPool:
2200 case ISD::TargetFrameIndex:
2201 case ISD::TargetExternalSymbol:
2202 case ISD::TargetBlockAddress:
2203 case ISD::TargetJumpTable:
2204 case ISD::TargetGlobalTLSAddress:
2205 case ISD::TargetGlobalAddress:
2206 case ISD::TokenFactor:
2207 case ISD::CopyFromReg:
2208 case ISD::CopyToReg:
2210 NodeToMatch->setNodeId(-1); // Mark selected.
2212 case ISD::AssertSext:
2213 case ISD::AssertZext:
2214 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2215 NodeToMatch->getOperand(0));
2217 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2218 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2221 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2223 // Set up the node stack with NodeToMatch as the only node on the stack.
2224 SmallVector<SDValue, 8> NodeStack;
2225 SDValue N = SDValue(NodeToMatch, 0);
2226 NodeStack.push_back(N);
2228 // MatchScopes - Scopes used when matching, if a match failure happens, this
2229 // indicates where to continue checking.
2230 SmallVector<MatchScope, 8> MatchScopes;
2232 // RecordedNodes - This is the set of nodes that have been recorded by the
2233 // state machine. The second value is the parent of the node, or null if the
2234 // root is recorded.
2235 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2237 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2239 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2241 // These are the current input chain and glue for use when generating nodes.
2242 // Various Emit operations change these. For example, emitting a copytoreg
2243 // uses and updates these.
2244 SDValue InputChain, InputGlue;
2246 // ChainNodesMatched - If a pattern matches nodes that have input/output
2247 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2248 // which ones they are. The result is captured into this list so that we can
2249 // update the chain results when the pattern is complete.
2250 SmallVector<SDNode*, 3> ChainNodesMatched;
2251 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2253 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2254 NodeToMatch->dump(CurDAG);
2257 // Determine where to start the interpreter. Normally we start at opcode #0,
2258 // but if the state machine starts with an OPC_SwitchOpcode, then we
2259 // accelerate the first lookup (which is guaranteed to be hot) with the
2260 // OpcodeOffset table.
2261 unsigned MatcherIndex = 0;
2263 if (!OpcodeOffset.empty()) {
2264 // Already computed the OpcodeOffset table, just index into it.
2265 if (N.getOpcode() < OpcodeOffset.size())
2266 MatcherIndex = OpcodeOffset[N.getOpcode()];
2267 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2269 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2270 // Otherwise, the table isn't computed, but the state machine does start
2271 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2272 // is the first time we're selecting an instruction.
2275 // Get the size of this case.
2276 unsigned CaseSize = MatcherTable[Idx++];
2278 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2279 if (CaseSize == 0) break;
2281 // Get the opcode, add the index to the table.
2282 uint16_t Opc = MatcherTable[Idx++];
2283 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2284 if (Opc >= OpcodeOffset.size())
2285 OpcodeOffset.resize((Opc+1)*2);
2286 OpcodeOffset[Opc] = Idx;
2290 // Okay, do the lookup for the first opcode.
2291 if (N.getOpcode() < OpcodeOffset.size())
2292 MatcherIndex = OpcodeOffset[N.getOpcode()];
2296 assert(MatcherIndex < TableSize && "Invalid index");
2298 unsigned CurrentOpcodeIndex = MatcherIndex;
2300 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2303 // Okay, the semantics of this operation are that we should push a scope
2304 // then evaluate the first child. However, pushing a scope only to have
2305 // the first check fail (which then pops it) is inefficient. If we can
2306 // determine immediately that the first check (or first several) will
2307 // immediately fail, don't even bother pushing a scope for them.
2311 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2312 if (NumToSkip & 128)
2313 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2314 // Found the end of the scope with no match.
2315 if (NumToSkip == 0) {
2320 FailIndex = MatcherIndex+NumToSkip;
2322 unsigned MatcherIndexOfPredicate = MatcherIndex;
2323 (void)MatcherIndexOfPredicate; // silence warning.
2325 // If we can't evaluate this predicate without pushing a scope (e.g. if
2326 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2327 // push the scope and evaluate the full predicate chain.
2329 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2330 Result, *this, RecordedNodes);
2334 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2335 << "index " << MatcherIndexOfPredicate
2336 << ", continuing at " << FailIndex << "\n");
2337 ++NumDAGIselRetries;
2339 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2340 // move to the next case.
2341 MatcherIndex = FailIndex;
2344 // If the whole scope failed to match, bail.
2345 if (FailIndex == 0) break;
2347 // Push a MatchScope which indicates where to go if the first child fails
2349 MatchScope NewEntry;
2350 NewEntry.FailIndex = FailIndex;
2351 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2352 NewEntry.NumRecordedNodes = RecordedNodes.size();
2353 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2354 NewEntry.InputChain = InputChain;
2355 NewEntry.InputGlue = InputGlue;
2356 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2357 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2358 MatchScopes.push_back(NewEntry);
2361 case OPC_RecordNode: {
2362 // Remember this node, it may end up being an operand in the pattern.
2364 if (NodeStack.size() > 1)
2365 Parent = NodeStack[NodeStack.size()-2].getNode();
2366 RecordedNodes.push_back(std::make_pair(N, Parent));
2370 case OPC_RecordChild0: case OPC_RecordChild1:
2371 case OPC_RecordChild2: case OPC_RecordChild3:
2372 case OPC_RecordChild4: case OPC_RecordChild5:
2373 case OPC_RecordChild6: case OPC_RecordChild7: {
2374 unsigned ChildNo = Opcode-OPC_RecordChild0;
2375 if (ChildNo >= N.getNumOperands())
2376 break; // Match fails if out of range child #.
2378 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2382 case OPC_RecordMemRef:
2383 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2386 case OPC_CaptureGlueInput:
2387 // If the current node has an input glue, capture it in InputGlue.
2388 if (N->getNumOperands() != 0 &&
2389 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2390 InputGlue = N->getOperand(N->getNumOperands()-1);
2393 case OPC_MoveChild: {
2394 unsigned ChildNo = MatcherTable[MatcherIndex++];
2395 if (ChildNo >= N.getNumOperands())
2396 break; // Match fails if out of range child #.
2397 N = N.getOperand(ChildNo);
2398 NodeStack.push_back(N);
2402 case OPC_MoveParent:
2403 // Pop the current node off the NodeStack.
2404 NodeStack.pop_back();
2405 assert(!NodeStack.empty() && "Node stack imbalance!");
2406 N = NodeStack.back();
2410 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2412 case OPC_CheckPatternPredicate:
2413 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2415 case OPC_CheckPredicate:
2416 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2420 case OPC_CheckComplexPat: {
2421 unsigned CPNum = MatcherTable[MatcherIndex++];
2422 unsigned RecNo = MatcherTable[MatcherIndex++];
2423 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2424 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2425 RecordedNodes[RecNo].first, CPNum,
2430 case OPC_CheckOpcode:
2431 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2435 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2438 case OPC_SwitchOpcode: {
2439 unsigned CurNodeOpcode = N.getOpcode();
2440 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2443 // Get the size of this case.
2444 CaseSize = MatcherTable[MatcherIndex++];
2446 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2447 if (CaseSize == 0) break;
2449 uint16_t Opc = MatcherTable[MatcherIndex++];
2450 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2452 // If the opcode matches, then we will execute this case.
2453 if (CurNodeOpcode == Opc)
2456 // Otherwise, skip over this case.
2457 MatcherIndex += CaseSize;
2460 // If no cases matched, bail out.
2461 if (CaseSize == 0) break;
2463 // Otherwise, execute the case we found.
2464 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2465 << " to " << MatcherIndex << "\n");
2469 case OPC_SwitchType: {
2470 MVT CurNodeVT = N.getValueType().getSimpleVT();
2471 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2474 // Get the size of this case.
2475 CaseSize = MatcherTable[MatcherIndex++];
2477 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2478 if (CaseSize == 0) break;
2480 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2481 if (CaseVT == MVT::iPTR)
2482 CaseVT = TLI.getPointerTy();
2484 // If the VT matches, then we will execute this case.
2485 if (CurNodeVT == CaseVT)
2488 // Otherwise, skip over this case.
2489 MatcherIndex += CaseSize;
2492 // If no cases matched, bail out.
2493 if (CaseSize == 0) break;
2495 // Otherwise, execute the case we found.
2496 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2497 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2500 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2501 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2502 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2503 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2504 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2505 Opcode-OPC_CheckChild0Type))
2508 case OPC_CheckCondCode:
2509 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2511 case OPC_CheckValueType:
2512 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2514 case OPC_CheckInteger:
2515 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2517 case OPC_CheckAndImm:
2518 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2520 case OPC_CheckOrImm:
2521 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2524 case OPC_CheckFoldableChainNode: {
2525 assert(NodeStack.size() != 1 && "No parent node");
2526 // Verify that all intermediate nodes between the root and this one have
2528 bool HasMultipleUses = false;
2529 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2530 if (!NodeStack[i].hasOneUse()) {
2531 HasMultipleUses = true;
2534 if (HasMultipleUses) break;
2536 // Check to see that the target thinks this is profitable to fold and that
2537 // we can fold it without inducing cycles in the graph.
2538 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2540 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2541 NodeToMatch, OptLevel,
2542 true/*We validate our own chains*/))
2547 case OPC_EmitInteger: {
2548 MVT::SimpleValueType VT =
2549 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2550 int64_t Val = MatcherTable[MatcherIndex++];
2552 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2553 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2554 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2557 case OPC_EmitRegister: {
2558 MVT::SimpleValueType VT =
2559 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2560 unsigned RegNo = MatcherTable[MatcherIndex++];
2561 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2562 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2565 case OPC_EmitRegister2: {
2566 // For targets w/ more than 256 register names, the register enum
2567 // values are stored in two bytes in the matcher table (just like
2569 MVT::SimpleValueType VT =
2570 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2571 unsigned RegNo = MatcherTable[MatcherIndex++];
2572 RegNo |= MatcherTable[MatcherIndex++] << 8;
2573 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2574 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2578 case OPC_EmitConvertToTarget: {
2579 // Convert from IMM/FPIMM to target version.
2580 unsigned RecNo = MatcherTable[MatcherIndex++];
2581 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2582 SDValue Imm = RecordedNodes[RecNo].first;
2584 if (Imm->getOpcode() == ISD::Constant) {
2585 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2586 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2587 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2588 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2589 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2592 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2596 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2597 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2598 // These are space-optimized forms of OPC_EmitMergeInputChains.
2599 assert(InputChain.getNode() == 0 &&
2600 "EmitMergeInputChains should be the first chain producing node");
2601 assert(ChainNodesMatched.empty() &&
2602 "Should only have one EmitMergeInputChains per match");
2604 // Read all of the chained nodes.
2605 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2606 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2607 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2609 // FIXME: What if other value results of the node have uses not matched
2611 if (ChainNodesMatched.back() != NodeToMatch &&
2612 !RecordedNodes[RecNo].first.hasOneUse()) {
2613 ChainNodesMatched.clear();
2617 // Merge the input chains if they are not intra-pattern references.
2618 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2620 if (InputChain.getNode() == 0)
2621 break; // Failed to merge.
2625 case OPC_EmitMergeInputChains: {
2626 assert(InputChain.getNode() == 0 &&
2627 "EmitMergeInputChains should be the first chain producing node");
2628 // This node gets a list of nodes we matched in the input that have
2629 // chains. We want to token factor all of the input chains to these nodes
2630 // together. However, if any of the input chains is actually one of the
2631 // nodes matched in this pattern, then we have an intra-match reference.
2632 // Ignore these because the newly token factored chain should not refer to
2634 unsigned NumChains = MatcherTable[MatcherIndex++];
2635 assert(NumChains != 0 && "Can't TF zero chains");
2637 assert(ChainNodesMatched.empty() &&
2638 "Should only have one EmitMergeInputChains per match");
2640 // Read all of the chained nodes.
2641 for (unsigned i = 0; i != NumChains; ++i) {
2642 unsigned RecNo = MatcherTable[MatcherIndex++];
2643 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2644 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2646 // FIXME: What if other value results of the node have uses not matched
2648 if (ChainNodesMatched.back() != NodeToMatch &&
2649 !RecordedNodes[RecNo].first.hasOneUse()) {
2650 ChainNodesMatched.clear();
2655 // If the inner loop broke out, the match fails.
2656 if (ChainNodesMatched.empty())
2659 // Merge the input chains if they are not intra-pattern references.
2660 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2662 if (InputChain.getNode() == 0)
2663 break; // Failed to merge.
2668 case OPC_EmitCopyToReg: {
2669 unsigned RecNo = MatcherTable[MatcherIndex++];
2670 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2671 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2673 if (InputChain.getNode() == 0)
2674 InputChain = CurDAG->getEntryNode();
2676 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2677 DestPhysReg, RecordedNodes[RecNo].first,
2680 InputGlue = InputChain.getValue(1);
2684 case OPC_EmitNodeXForm: {
2685 unsigned XFormNo = MatcherTable[MatcherIndex++];
2686 unsigned RecNo = MatcherTable[MatcherIndex++];
2687 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2688 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2689 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2694 case OPC_MorphNodeTo: {
2695 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2696 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2697 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2698 // Get the result VT list.
2699 unsigned NumVTs = MatcherTable[MatcherIndex++];
2700 SmallVector<EVT, 4> VTs;
2701 for (unsigned i = 0; i != NumVTs; ++i) {
2702 MVT::SimpleValueType VT =
2703 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2704 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2708 if (EmitNodeInfo & OPFL_Chain)
2709 VTs.push_back(MVT::Other);
2710 if (EmitNodeInfo & OPFL_GlueOutput)
2711 VTs.push_back(MVT::Glue);
2713 // This is hot code, so optimize the two most common cases of 1 and 2
2716 if (VTs.size() == 1)
2717 VTList = CurDAG->getVTList(VTs[0]);
2718 else if (VTs.size() == 2)
2719 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2721 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2723 // Get the operand list.
2724 unsigned NumOps = MatcherTable[MatcherIndex++];
2725 SmallVector<SDValue, 8> Ops;
2726 for (unsigned i = 0; i != NumOps; ++i) {
2727 unsigned RecNo = MatcherTable[MatcherIndex++];
2729 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2731 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2732 Ops.push_back(RecordedNodes[RecNo].first);
2735 // If there are variadic operands to add, handle them now.
2736 if (EmitNodeInfo & OPFL_VariadicInfo) {
2737 // Determine the start index to copy from.
2738 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2739 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2740 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2741 "Invalid variadic node");
2742 // Copy all of the variadic operands, not including a potential glue
2744 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2746 SDValue V = NodeToMatch->getOperand(i);
2747 if (V.getValueType() == MVT::Glue) break;
2752 // If this has chain/glue inputs, add them.
2753 if (EmitNodeInfo & OPFL_Chain)
2754 Ops.push_back(InputChain);
2755 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2756 Ops.push_back(InputGlue);
2760 if (Opcode != OPC_MorphNodeTo) {
2761 // If this is a normal EmitNode command, just create the new node and
2762 // add the results to the RecordedNodes list.
2763 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2764 VTList, Ops.data(), Ops.size());
2766 // Add all the non-glue/non-chain results to the RecordedNodes list.
2767 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2768 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2769 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2774 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2778 // If the node had chain/glue results, update our notion of the current
2780 if (EmitNodeInfo & OPFL_GlueOutput) {
2781 InputGlue = SDValue(Res, VTs.size()-1);
2782 if (EmitNodeInfo & OPFL_Chain)
2783 InputChain = SDValue(Res, VTs.size()-2);
2784 } else if (EmitNodeInfo & OPFL_Chain)
2785 InputChain = SDValue(Res, VTs.size()-1);
2787 // If the OPFL_MemRefs glue is set on this node, slap all of the
2788 // accumulated memrefs onto it.
2790 // FIXME: This is vastly incorrect for patterns with multiple outputs
2791 // instructions that access memory and for ComplexPatterns that match
2793 if (EmitNodeInfo & OPFL_MemRefs) {
2794 // Only attach load or store memory operands if the generated
2795 // instruction may load or store.
2796 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2797 bool mayLoad = MCID.mayLoad();
2798 bool mayStore = MCID.mayStore();
2800 unsigned NumMemRefs = 0;
2801 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2802 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2803 if ((*I)->isLoad()) {
2806 } else if ((*I)->isStore()) {
2814 MachineSDNode::mmo_iterator MemRefs =
2815 MF->allocateMemRefsArray(NumMemRefs);
2817 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2818 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2819 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2820 if ((*I)->isLoad()) {
2823 } else if ((*I)->isStore()) {
2831 cast<MachineSDNode>(Res)
2832 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2836 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2837 << " node: "; Res->dump(CurDAG); errs() << "\n");
2839 // If this was a MorphNodeTo then we're completely done!
2840 if (Opcode == OPC_MorphNodeTo) {
2841 // Update chain and glue uses.
2842 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2843 InputGlue, GlueResultNodesMatched, true);
2850 case OPC_MarkGlueResults: {
2851 unsigned NumNodes = MatcherTable[MatcherIndex++];
2853 // Read and remember all the glue-result nodes.
2854 for (unsigned i = 0; i != NumNodes; ++i) {
2855 unsigned RecNo = MatcherTable[MatcherIndex++];
2857 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2859 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2860 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2865 case OPC_CompleteMatch: {
2866 // The match has been completed, and any new nodes (if any) have been
2867 // created. Patch up references to the matched dag to use the newly
2869 unsigned NumResults = MatcherTable[MatcherIndex++];
2871 for (unsigned i = 0; i != NumResults; ++i) {
2872 unsigned ResSlot = MatcherTable[MatcherIndex++];
2874 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2876 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2877 SDValue Res = RecordedNodes[ResSlot].first;
2879 assert(i < NodeToMatch->getNumValues() &&
2880 NodeToMatch->getValueType(i) != MVT::Other &&
2881 NodeToMatch->getValueType(i) != MVT::Glue &&
2882 "Invalid number of results to complete!");
2883 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2884 NodeToMatch->getValueType(i) == MVT::iPTR ||
2885 Res.getValueType() == MVT::iPTR ||
2886 NodeToMatch->getValueType(i).getSizeInBits() ==
2887 Res.getValueType().getSizeInBits()) &&
2888 "invalid replacement");
2889 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2892 // If the root node defines glue, add it to the glue nodes to update list.
2893 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2894 GlueResultNodesMatched.push_back(NodeToMatch);
2896 // Update chain and glue uses.
2897 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2898 InputGlue, GlueResultNodesMatched, false);
2900 assert(NodeToMatch->use_empty() &&
2901 "Didn't replace all uses of the node?");
2903 // FIXME: We just return here, which interacts correctly with SelectRoot
2904 // above. We should fix this to not return an SDNode* anymore.
2909 // If the code reached this point, then the match failed. See if there is
2910 // another child to try in the current 'Scope', otherwise pop it until we
2911 // find a case to check.
2912 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2913 ++NumDAGIselRetries;
2915 if (MatchScopes.empty()) {
2916 CannotYetSelect(NodeToMatch);
2920 // Restore the interpreter state back to the point where the scope was
2922 MatchScope &LastScope = MatchScopes.back();
2923 RecordedNodes.resize(LastScope.NumRecordedNodes);
2925 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2926 N = NodeStack.back();
2928 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2929 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2930 MatcherIndex = LastScope.FailIndex;
2932 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2934 InputChain = LastScope.InputChain;
2935 InputGlue = LastScope.InputGlue;
2936 if (!LastScope.HasChainNodesMatched)
2937 ChainNodesMatched.clear();
2938 if (!LastScope.HasGlueResultNodesMatched)
2939 GlueResultNodesMatched.clear();
2941 // Check to see what the offset is at the new MatcherIndex. If it is zero
2942 // we have reached the end of this scope, otherwise we have another child
2943 // in the current scope to try.
2944 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2945 if (NumToSkip & 128)
2946 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2948 // If we have another child in this scope to match, update FailIndex and
2950 if (NumToSkip != 0) {
2951 LastScope.FailIndex = MatcherIndex+NumToSkip;
2955 // End of this scope, pop it and try the next child in the containing
2957 MatchScopes.pop_back();
2964 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2966 raw_string_ostream Msg(msg);
2967 Msg << "Cannot select: ";
2969 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2970 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2971 N->getOpcode() != ISD::INTRINSIC_VOID) {
2972 N->printrFull(Msg, CurDAG);
2974 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2976 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2977 if (iid < Intrinsic::num_intrinsics)
2978 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2979 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2980 Msg << "target intrinsic %" << TII->getName(iid);
2982 Msg << "unknown intrinsic #" << iid;
2984 report_fatal_error(Msg.str());
2987 char SelectionDAGISel::ID = 0;