1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/CodeGen/ScheduleDAG.h"
17 #include "llvm/CallingConv.h"
18 #include "llvm/Constants.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/InlineAsm.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineDebugInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SchedulerRegistry.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/CodeGen/SSARegMap.h"
35 #include "llvm/Target/MRegisterInfo.h"
36 #include "llvm/Target/TargetData.h"
37 #include "llvm/Target/TargetFrameInfo.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetLowering.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/Visibility.h"
54 ViewISelDAGs("view-isel-dags", cl::Hidden,
55 cl::desc("Pop up a window to show isel dags as they are selected"));
57 ViewSchedDAGs("view-sched-dags", cl::Hidden,
58 cl::desc("Pop up a window to show sched dags as they are processed"));
60 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
64 //===---------------------------------------------------------------------===//
66 /// RegisterScheduler class - Track the registration of instruction schedulers.
68 //===---------------------------------------------------------------------===//
69 MachinePassRegistry RegisterScheduler::Registry;
71 //===---------------------------------------------------------------------===//
73 /// ISHeuristic command line option for instruction schedulers.
75 //===---------------------------------------------------------------------===//
77 cl::opt<RegisterScheduler::FunctionPassCtor, false,
78 RegisterPassParser<RegisterScheduler> >
80 cl::init(createDefaultScheduler),
81 cl::desc("Instruction schedulers available:"));
83 static RegisterScheduler
84 defaultListDAGScheduler("default", " Best scheduler for the target",
85 createDefaultScheduler);
89 /// RegsForValue - This struct represents the physical registers that a
90 /// particular value is assigned and the type information about the value.
91 /// This is needed because values can be promoted into larger registers and
92 /// expanded into multiple smaller registers than the value.
93 struct VISIBILITY_HIDDEN RegsForValue {
94 /// Regs - This list hold the register (for legal and promoted values)
95 /// or register set (for expanded values) that the value should be assigned
97 std::vector<unsigned> Regs;
99 /// RegVT - The value type of each register.
101 MVT::ValueType RegVT;
103 /// ValueVT - The value type of the LLVM value, which may be promoted from
104 /// RegVT or made from merging the two expanded parts.
105 MVT::ValueType ValueVT;
107 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
109 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
110 : RegVT(regvt), ValueVT(valuevt) {
113 RegsForValue(const std::vector<unsigned> ®s,
114 MVT::ValueType regvt, MVT::ValueType valuevt)
115 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
118 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
119 /// this value and returns the result as a ValueVT value. This uses
120 /// Chain/Flag as the input and updates them for the output Chain/Flag.
121 SDOperand getCopyFromRegs(SelectionDAG &DAG,
122 SDOperand &Chain, SDOperand &Flag) const;
124 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
125 /// specified value into the registers specified by this object. This uses
126 /// Chain/Flag as the input and updates them for the output Chain/Flag.
127 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
128 SDOperand &Chain, SDOperand &Flag,
129 MVT::ValueType PtrVT) const;
131 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
132 /// operand list. This adds the code marker and includes the number of
133 /// values added into it.
134 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
135 std::vector<SDOperand> &Ops) const;
140 //===--------------------------------------------------------------------===//
141 /// createDefaultScheduler - This creates an instruction scheduler appropriate
143 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
145 MachineBasicBlock *BB) {
146 TargetLowering &TLI = IS->getTargetLowering();
148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
149 return createTDListDAGScheduler(IS, DAG, BB);
151 assert(TLI.getSchedulingPreference() ==
152 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
153 return createBURRListDAGScheduler(IS, DAG, BB);
158 //===--------------------------------------------------------------------===//
159 /// FunctionLoweringInfo - This contains information that is global to a
160 /// function that is used when lowering a region of the function.
161 class FunctionLoweringInfo {
168 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
170 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
171 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
173 /// ValueMap - Since we emit code for the function a basic block at a time,
174 /// we must remember which virtual registers hold the values for
175 /// cross-basic-block values.
176 std::map<const Value*, unsigned> ValueMap;
178 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
179 /// the entry block. This allows the allocas to be efficiently referenced
180 /// anywhere in the function.
181 std::map<const AllocaInst*, int> StaticAllocaMap;
183 unsigned MakeReg(MVT::ValueType VT) {
184 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
187 unsigned CreateRegForValue(const Value *V);
189 unsigned InitializeRegForValue(const Value *V) {
190 unsigned &R = ValueMap[V];
191 assert(R == 0 && "Already initialized this value register!");
192 return R = CreateRegForValue(V);
197 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
198 /// PHI nodes or outside of the basic block that defines it, or used by a
199 /// switch instruction, which may expand to multiple basic blocks.
200 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
201 if (isa<PHINode>(I)) return true;
202 BasicBlock *BB = I->getParent();
203 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
204 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
205 isa<SwitchInst>(*UI))
210 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
211 /// entry block, return true. This includes arguments used by switches, since
212 /// the switch may expand into multiple basic blocks.
213 static bool isOnlyUsedInEntryBlock(Argument *A) {
214 BasicBlock *Entry = A->getParent()->begin();
215 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
216 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
217 return false; // Use not in entry block.
221 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
222 Function &fn, MachineFunction &mf)
223 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
225 // Create a vreg for each argument register that is not dead and is used
226 // outside of the entry block for the function.
227 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
229 if (!isOnlyUsedInEntryBlock(AI))
230 InitializeRegForValue(AI);
232 // Initialize the mapping of values to registers. This is only set up for
233 // instruction values that are used outside of the block that defines
235 Function::iterator BB = Fn.begin(), EB = Fn.end();
236 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
237 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
238 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
239 const Type *Ty = AI->getAllocatedType();
240 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
242 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
245 // If the alignment of the value is smaller than the size of the value,
246 // and if the size of the value is particularly small (<= 8 bytes),
247 // round up to the size of the value for potentially better performance.
249 // FIXME: This could be made better with a preferred alignment hook in
250 // TargetData. It serves primarily to 8-byte align doubles for X86.
251 if (Align < TySize && TySize <= 8) Align = TySize;
252 TySize *= CUI->getValue(); // Get total allocated size.
253 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
254 StaticAllocaMap[AI] =
255 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
258 for (; BB != EB; ++BB)
259 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
260 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
261 if (!isa<AllocaInst>(I) ||
262 !StaticAllocaMap.count(cast<AllocaInst>(I)))
263 InitializeRegForValue(I);
265 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
266 // also creates the initial PHI MachineInstrs, though none of the input
267 // operands are populated.
268 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
269 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
271 MF.getBasicBlockList().push_back(MBB);
273 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
276 for (BasicBlock::iterator I = BB->begin();
277 (PN = dyn_cast<PHINode>(I)); ++I)
278 if (!PN->use_empty()) {
279 MVT::ValueType VT = TLI.getValueType(PN->getType());
280 unsigned NumElements;
281 if (VT != MVT::Vector)
282 NumElements = TLI.getNumElements(VT);
284 MVT::ValueType VT1,VT2;
286 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
289 unsigned PHIReg = ValueMap[PN];
290 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
291 for (unsigned i = 0; i != NumElements; ++i)
292 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
297 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
298 /// the correctly promoted or expanded types. Assign these registers
299 /// consecutive vreg numbers and return the first assigned number.
300 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
301 MVT::ValueType VT = TLI.getValueType(V->getType());
303 // The number of multiples of registers that we need, to, e.g., split up
304 // a <2 x int64> -> 4 x i32 registers.
305 unsigned NumVectorRegs = 1;
307 // If this is a packed type, figure out what type it will decompose into
308 // and how many of the elements it will use.
309 if (VT == MVT::Vector) {
310 const PackedType *PTy = cast<PackedType>(V->getType());
311 unsigned NumElts = PTy->getNumElements();
312 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
314 // Divide the input until we get to a supported size. This will always
315 // end with a scalar if the target doesn't support vectors.
316 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
323 VT = getVectorType(EltTy, NumElts);
326 // The common case is that we will only create one register for this
327 // value. If we have that case, create and return the virtual register.
328 unsigned NV = TLI.getNumElements(VT);
330 // If we are promoting this value, pick the next largest supported type.
331 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
332 unsigned Reg = MakeReg(PromotedType);
333 // If this is a vector of supported or promoted types (e.g. 4 x i16),
334 // create all of the registers.
335 for (unsigned i = 1; i != NumVectorRegs; ++i)
336 MakeReg(PromotedType);
340 // If this value is represented with multiple target registers, make sure
341 // to create enough consecutive registers of the right (smaller) type.
342 unsigned NT = VT-1; // Find the type to use.
343 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
346 unsigned R = MakeReg((MVT::ValueType)NT);
347 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
348 MakeReg((MVT::ValueType)NT);
352 //===----------------------------------------------------------------------===//
353 /// SelectionDAGLowering - This is the common target-independent lowering
354 /// implementation that is parameterized by a TargetLowering object.
355 /// Also, targets can overload any lowering method.
358 class SelectionDAGLowering {
359 MachineBasicBlock *CurMBB;
361 std::map<const Value*, SDOperand> NodeMap;
363 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
364 /// them up and then emit token factor nodes when possible. This allows us to
365 /// get simple disambiguation between loads without worrying about alias
367 std::vector<SDOperand> PendingLoads;
369 /// Case - A pair of values to record the Value for a switch case, and the
370 /// case's target basic block.
371 typedef std::pair<Constant*, MachineBasicBlock*> Case;
372 typedef std::vector<Case>::iterator CaseItr;
373 typedef std::pair<CaseItr, CaseItr> CaseRange;
375 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
376 /// of conditional branches.
378 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
379 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
381 /// CaseBB - The MBB in which to emit the compare and branch
382 MachineBasicBlock *CaseBB;
383 /// LT, GE - If nonzero, we know the current case value must be less-than or
384 /// greater-than-or-equal-to these Constants.
387 /// Range - A pair of iterators representing the range of case values to be
388 /// processed at this point in the binary search tree.
392 /// The comparison function for sorting Case values.
394 bool operator () (const Case& C1, const Case& C2) {
395 if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first))
396 return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue();
398 const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first);
399 return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue();
404 // TLI - This is information that describes the available target features we
405 // need for lowering. This indicates when operations are unavailable,
406 // implemented with a libcall, etc.
409 const TargetData *TD;
411 /// SwitchCases - Vector of CaseBlock structures used to communicate
412 /// SwitchInst code generation information.
413 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
414 SelectionDAGISel::JumpTable JT;
416 /// FuncInfo - Information about the function as a whole.
418 FunctionLoweringInfo &FuncInfo;
420 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
421 FunctionLoweringInfo &funcinfo)
422 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
423 JT(0,0,0,0), FuncInfo(funcinfo) {
426 /// getRoot - Return the current virtual root of the Selection DAG.
428 SDOperand getRoot() {
429 if (PendingLoads.empty())
430 return DAG.getRoot();
432 if (PendingLoads.size() == 1) {
433 SDOperand Root = PendingLoads[0];
435 PendingLoads.clear();
439 // Otherwise, we have to make a token factor node.
440 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
441 PendingLoads.clear();
446 void visit(Instruction &I) { visit(I.getOpcode(), I); }
448 void visit(unsigned Opcode, User &I) {
450 default: assert(0 && "Unknown instruction type encountered!");
452 // Build the switch statement using the Instruction.def file.
453 #define HANDLE_INST(NUM, OPCODE, CLASS) \
454 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
455 #include "llvm/Instruction.def"
459 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
461 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
462 SDOperand SrcValue, SDOperand Root,
465 SDOperand getIntPtrConstant(uint64_t Val) {
466 return DAG.getConstant(Val, TLI.getPointerTy());
469 SDOperand getValue(const Value *V);
471 const SDOperand &setValue(const Value *V, SDOperand NewN) {
472 SDOperand &N = NodeMap[V];
473 assert(N.Val == 0 && "Already set a value for this node!");
477 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
479 bool OutReg, bool InReg,
480 std::set<unsigned> &OutputRegs,
481 std::set<unsigned> &InputRegs);
483 // Terminator instructions.
484 void visitRet(ReturnInst &I);
485 void visitBr(BranchInst &I);
486 void visitSwitch(SwitchInst &I);
487 void visitUnreachable(UnreachableInst &I) { /* noop */ }
489 // Helper for visitSwitch
490 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
491 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
493 // These all get lowered before this pass.
494 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
495 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
497 void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
498 void visitShift(User &I, unsigned Opcode);
499 void visitAdd(User &I) {
500 visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
502 void visitSub(User &I);
503 void visitMul(User &I) {
504 visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
506 void visitDiv(User &I) {
507 const Type *Ty = I.getType();
509 Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
510 Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
512 void visitRem(User &I) {
513 const Type *Ty = I.getType();
514 visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
516 void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
517 void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
518 void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
519 void visitShl(User &I) { visitShift(I, ISD::SHL); }
520 void visitShr(User &I) {
521 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
524 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc,
525 ISD::CondCode FPOpc);
526 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ,
528 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE,
530 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE,
532 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE,
534 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT,
536 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT,
539 void visitExtractElement(User &I);
540 void visitInsertElement(User &I);
541 void visitShuffleVector(User &I);
543 void visitGetElementPtr(User &I);
544 void visitCast(User &I);
545 void visitSelect(User &I);
547 void visitMalloc(MallocInst &I);
548 void visitFree(FreeInst &I);
549 void visitAlloca(AllocaInst &I);
550 void visitLoad(LoadInst &I);
551 void visitStore(StoreInst &I);
552 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
553 void visitCall(CallInst &I);
554 void visitInlineAsm(CallInst &I);
555 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
556 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
558 void visitVAStart(CallInst &I);
559 void visitVAArg(VAArgInst &I);
560 void visitVAEnd(CallInst &I);
561 void visitVACopy(CallInst &I);
562 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
564 void visitMemIntrinsic(CallInst &I, unsigned Op);
566 void visitUserOp1(Instruction &I) {
567 assert(0 && "UserOp1 should not exist at instruction selection time!");
570 void visitUserOp2(Instruction &I) {
571 assert(0 && "UserOp2 should not exist at instruction selection time!");
575 } // end namespace llvm
577 SDOperand SelectionDAGLowering::getValue(const Value *V) {
578 SDOperand &N = NodeMap[V];
581 const Type *VTy = V->getType();
582 MVT::ValueType VT = TLI.getValueType(VTy);
583 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
584 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
585 visit(CE->getOpcode(), *CE);
586 assert(N.Val && "visit didn't populate the ValueMap!");
588 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
589 return N = DAG.getGlobalAddress(GV, VT);
590 } else if (isa<ConstantPointerNull>(C)) {
591 return N = DAG.getConstant(0, TLI.getPointerTy());
592 } else if (isa<UndefValue>(C)) {
593 if (!isa<PackedType>(VTy))
594 return N = DAG.getNode(ISD::UNDEF, VT);
596 // Create a VBUILD_VECTOR of undef nodes.
597 const PackedType *PTy = cast<PackedType>(VTy);
598 unsigned NumElements = PTy->getNumElements();
599 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
601 std::vector<SDOperand> Ops;
602 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
604 // Create a VConstant node with generic Vector type.
605 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
606 Ops.push_back(DAG.getValueType(PVT));
607 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
608 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
609 return N = DAG.getConstantFP(CFP->getValue(), VT);
610 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
611 unsigned NumElements = PTy->getNumElements();
612 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
614 // Now that we know the number and type of the elements, push a
615 // Constant or ConstantFP node onto the ops list for each element of
616 // the packed constant.
617 std::vector<SDOperand> Ops;
618 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
619 for (unsigned i = 0; i != NumElements; ++i)
620 Ops.push_back(getValue(CP->getOperand(i)));
622 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
624 if (MVT::isFloatingPoint(PVT))
625 Op = DAG.getConstantFP(0, PVT);
627 Op = DAG.getConstant(0, PVT);
628 Ops.assign(NumElements, Op);
631 // Create a VBUILD_VECTOR node with generic Vector type.
632 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
633 Ops.push_back(DAG.getValueType(PVT));
634 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
636 // Canonicalize all constant ints to be unsigned.
637 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
641 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
642 std::map<const AllocaInst*, int>::iterator SI =
643 FuncInfo.StaticAllocaMap.find(AI);
644 if (SI != FuncInfo.StaticAllocaMap.end())
645 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
648 std::map<const Value*, unsigned>::const_iterator VMI =
649 FuncInfo.ValueMap.find(V);
650 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
652 unsigned InReg = VMI->second;
654 // If this type is not legal, make it so now.
655 if (VT != MVT::Vector) {
656 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
658 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
660 // Source must be expanded. This input value is actually coming from the
661 // register pair VMI->second and VMI->second+1.
662 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
663 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
664 } else if (DestVT > VT) { // Promotion case
665 if (MVT::isFloatingPoint(VT))
666 N = DAG.getNode(ISD::FP_ROUND, VT, N);
668 N = DAG.getNode(ISD::TRUNCATE, VT, N);
671 // Otherwise, if this is a vector, make it available as a generic vector
673 MVT::ValueType PTyElementVT, PTyLegalElementVT;
674 const PackedType *PTy = cast<PackedType>(VTy);
675 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
678 // Build a VBUILD_VECTOR with the input registers.
679 std::vector<SDOperand> Ops;
680 if (PTyElementVT == PTyLegalElementVT) {
681 // If the value types are legal, just VBUILD the CopyFromReg nodes.
682 for (unsigned i = 0; i != NE; ++i)
683 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
685 } else if (PTyElementVT < PTyLegalElementVT) {
686 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
687 for (unsigned i = 0; i != NE; ++i) {
688 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
690 if (MVT::isFloatingPoint(PTyElementVT))
691 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
693 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
697 // If the register was expanded, use BUILD_PAIR.
698 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
699 for (unsigned i = 0; i != NE/2; ++i) {
700 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
702 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
704 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
708 Ops.push_back(DAG.getConstant(NE, MVT::i32));
709 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
710 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
712 // Finally, use a VBIT_CONVERT to make this available as the appropriate
714 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
715 DAG.getConstant(PTy->getNumElements(),
717 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
724 void SelectionDAGLowering::visitRet(ReturnInst &I) {
725 if (I.getNumOperands() == 0) {
726 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
729 std::vector<SDOperand> NewValues;
730 NewValues.push_back(getRoot());
731 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
732 SDOperand RetOp = getValue(I.getOperand(i));
733 bool isSigned = I.getOperand(i)->getType()->isSigned();
735 // If this is an integer return value, we need to promote it ourselves to
736 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
738 // FIXME: C calling convention requires the return type to be promoted to
739 // at least 32-bit. But this is not necessary for non-C calling conventions.
740 if (MVT::isInteger(RetOp.getValueType()) &&
741 RetOp.getValueType() < MVT::i64) {
742 MVT::ValueType TmpVT;
743 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
744 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
749 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
751 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
753 NewValues.push_back(RetOp);
754 NewValues.push_back(DAG.getConstant(isSigned, MVT::i32));
756 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, NewValues));
759 void SelectionDAGLowering::visitBr(BranchInst &I) {
760 // Update machine-CFG edges.
761 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
762 CurMBB->addSuccessor(Succ0MBB);
764 // Figure out which block is immediately after the current one.
765 MachineBasicBlock *NextBlock = 0;
766 MachineFunction::iterator BBI = CurMBB;
767 if (++BBI != CurMBB->getParent()->end())
770 if (I.isUnconditional()) {
771 // If this is not a fall-through branch, emit the branch.
772 if (Succ0MBB != NextBlock)
773 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
774 DAG.getBasicBlock(Succ0MBB)));
776 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
777 CurMBB->addSuccessor(Succ1MBB);
779 SDOperand Cond = getValue(I.getCondition());
780 if (Succ1MBB == NextBlock) {
781 // If the condition is false, fall through. This means we should branch
782 // if the condition is true to Succ #0.
783 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
784 Cond, DAG.getBasicBlock(Succ0MBB)));
785 } else if (Succ0MBB == NextBlock) {
786 // If the condition is true, fall through. This means we should branch if
787 // the condition is false to Succ #1. Invert the condition first.
788 SDOperand True = DAG.getConstant(1, Cond.getValueType());
789 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
790 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
791 Cond, DAG.getBasicBlock(Succ1MBB)));
793 std::vector<SDOperand> Ops;
794 Ops.push_back(getRoot());
795 // If the false case is the current basic block, then this is a self
796 // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
797 // adds an extra instruction in the loop. Instead, invert the
798 // condition and emit "Loop: ... br!cond Loop; br Out.
799 if (CurMBB == Succ1MBB) {
800 std::swap(Succ0MBB, Succ1MBB);
801 SDOperand True = DAG.getConstant(1, Cond.getValueType());
802 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
804 SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
805 DAG.getBasicBlock(Succ0MBB));
806 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
807 DAG.getBasicBlock(Succ1MBB)));
812 /// visitSwitchCase - Emits the necessary code to represent a single node in
813 /// the binary search tree resulting from lowering a switch instruction.
814 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
815 SDOperand SwitchOp = getValue(CB.SwitchV);
816 SDOperand CaseOp = getValue(CB.CaseC);
817 SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC);
819 // Set NextBlock to be the MBB immediately after the current one, if any.
820 // This is used to avoid emitting unnecessary branches to the next block.
821 MachineBasicBlock *NextBlock = 0;
822 MachineFunction::iterator BBI = CurMBB;
823 if (++BBI != CurMBB->getParent()->end())
826 // If the lhs block is the next block, invert the condition so that we can
827 // fall through to the lhs instead of the rhs block.
828 if (CB.LHSBB == NextBlock) {
829 std::swap(CB.LHSBB, CB.RHSBB);
830 SDOperand True = DAG.getConstant(1, Cond.getValueType());
831 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
833 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
834 DAG.getBasicBlock(CB.LHSBB));
835 if (CB.RHSBB == NextBlock)
838 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
839 DAG.getBasicBlock(CB.RHSBB)));
840 // Update successor info
841 CurMBB->addSuccessor(CB.LHSBB);
842 CurMBB->addSuccessor(CB.RHSBB);
845 /// visitSwitchCase - Emits the necessary code to represent a single node in
846 /// the binary search tree resulting from lowering a switch instruction.
847 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
848 // FIXME: Need to emit different code for PIC vs. Non-PIC, specifically,
849 // we need to add the address of the jump table to the value loaded, since
850 // the entries in the jump table will be differences rather than absolute
853 // Emit the code for the jump table
854 MVT::ValueType PTy = TLI.getPointerTy();
855 assert((PTy == MVT::i32 || PTy == MVT::i64) &&
856 "Jump table entries are 32-bit values");
857 // PIC jump table entries are 32-bit values.
859 (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_)
860 ? 4 : MVT::getSizeInBits(PTy)/8;
861 SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
862 SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy,
863 DAG.getConstant(EntrySize, PTy));
864 SDOperand TAB = DAG.getJumpTable(JT.JTI,PTy);
865 SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, TAB);
866 SDOperand LD = DAG.getLoad(MVT::i32, Copy.getValue(1), ADD,
868 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
869 ADD = DAG.getNode(ISD::ADD, PTy,
870 ((PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD), TAB);
871 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), ADD));
873 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD));
877 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
878 // Figure out which block is immediately after the current one.
879 MachineBasicBlock *NextBlock = 0;
880 MachineFunction::iterator BBI = CurMBB;
881 if (++BBI != CurMBB->getParent()->end())
884 // If there is only the default destination, branch to it if it is not the
885 // next basic block. Otherwise, just fall through.
886 if (I.getNumOperands() == 2) {
887 // Update machine-CFG edges.
888 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()];
889 // If this is not a fall-through branch, emit the branch.
890 if (DefaultMBB != NextBlock)
891 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
892 DAG.getBasicBlock(DefaultMBB)));
893 CurMBB->addSuccessor(DefaultMBB);
897 // If there are any non-default case statements, create a vector of Cases
898 // representing each one, and sort the vector so that we can efficiently
899 // create a binary search tree from them.
900 std::vector<Case> Cases;
901 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
902 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
903 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
905 std::sort(Cases.begin(), Cases.end(), CaseCmp());
907 // Get the Value to be switched on and default basic blocks, which will be
908 // inserted into CaseBlock records, representing basic blocks in the binary
910 Value *SV = I.getOperand(0);
911 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
913 // Get the MachineFunction which holds the current MBB. This is used during
914 // emission of jump tables, and when inserting any additional MBBs necessary
915 // to represent the switch.
916 MachineFunction *CurMF = CurMBB->getParent();
917 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
919 // If the switch has more than 5 blocks, and at least 31.25% dense, and the
920 // target supports indirect branches, then emit a jump table rather than
921 // lowering the switch to a binary tree of conditional branches.
922 // FIXME: Make this work with PIC code
923 if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) &&
925 uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue();
926 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getRawValue();
927 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
929 if (Density >= 0.3125) {
930 // Create a new basic block to hold the code for loading the address
931 // of the jump table, and jumping to it. Update successor information;
932 // we will either branch to the default case for the switch, or the jump
934 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
935 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
936 CurMBB->addSuccessor(Default);
937 CurMBB->addSuccessor(JumpTableBB);
939 // Subtract the lowest switch case value from the value being switched on
940 // and conditional branch to default mbb if the result is greater than the
941 // difference between smallest and largest cases.
942 SDOperand SwitchOp = getValue(SV);
943 MVT::ValueType VT = SwitchOp.getValueType();
944 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
945 DAG.getConstant(First, VT));
947 // The SDNode we just created, which holds the value being switched on
948 // minus the the smallest case value, needs to be copied to a virtual
949 // register so it can be used as an index into the jump table in a
950 // subsequent basic block. This value may be smaller or larger than the
951 // target's pointer type, and therefore require extension or truncating.
952 if (VT > TLI.getPointerTy())
953 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
955 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
956 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
957 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
959 // Emit the range check for the jump table, and branch to the default
960 // block for the switch statement if the value being switched on exceeds
961 // the largest case in the switch.
962 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
963 DAG.getConstant(Last-First,VT), ISD::SETUGT);
964 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
965 DAG.getBasicBlock(Default)));
967 // Build a vector of destination BBs, corresponding to each target
968 // of the jump table. If the value of the jump table slot corresponds to
969 // a case statement, push the case's BB onto the vector, otherwise, push
971 std::set<MachineBasicBlock*> UniqueBBs;
972 std::vector<MachineBasicBlock*> DestBBs;
973 uint64_t TEI = First;
974 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) {
975 if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) {
976 DestBBs.push_back(ii->second);
977 UniqueBBs.insert(ii->second);
980 DestBBs.push_back(Default);
981 UniqueBBs.insert(Default);
985 // Update successor info
986 for (std::set<MachineBasicBlock*>::iterator ii = UniqueBBs.begin(),
987 ee = UniqueBBs.end(); ii != ee; ++ii)
988 JumpTableBB->addSuccessor(*ii);
990 // Create a jump table index for this jump table, or return an existing
992 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
994 // Set the jump table information so that we can codegen it as a second
996 JT.Reg = JumpTableReg;
998 JT.MBB = JumpTableBB;
999 JT.Default = Default;
1004 // Push the initial CaseRec onto the worklist
1005 std::vector<CaseRec> CaseVec;
1006 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1008 while (!CaseVec.empty()) {
1009 // Grab a record representing a case range to process off the worklist
1010 CaseRec CR = CaseVec.back();
1013 // Size is the number of Cases represented by this range. If Size is 1,
1014 // then we are processing a leaf of the binary search tree. Otherwise,
1015 // we need to pick a pivot, and push left and right ranges onto the
1017 unsigned Size = CR.Range.second - CR.Range.first;
1020 // Create a CaseBlock record representing a conditional branch to
1021 // the Case's target mbb if the value being switched on SV is equal
1022 // to C. Otherwise, branch to default.
1023 Constant *C = CR.Range.first->first;
1024 MachineBasicBlock *Target = CR.Range.first->second;
1025 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1027 // If the MBB representing the leaf node is the current MBB, then just
1028 // call visitSwitchCase to emit the code into the current block.
1029 // Otherwise, push the CaseBlock onto the vector to be later processed
1030 // by SDISel, and insert the node's MBB before the next MBB.
1031 if (CR.CaseBB == CurMBB)
1032 visitSwitchCase(CB);
1034 SwitchCases.push_back(CB);
1035 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1038 // split case range at pivot
1039 CaseItr Pivot = CR.Range.first + (Size / 2);
1040 CaseRange LHSR(CR.Range.first, Pivot);
1041 CaseRange RHSR(Pivot, CR.Range.second);
1042 Constant *C = Pivot->first;
1043 MachineBasicBlock *RHSBB = 0, *LHSBB = 0;
1044 // We know that we branch to the LHS if the Value being switched on is
1045 // less than the Pivot value, C. We use this to optimize our binary
1046 // tree a bit, by recognizing that if SV is greater than or equal to the
1047 // LHS's Case Value, and that Case Value is exactly one less than the
1048 // Pivot's Value, then we can branch directly to the LHS's Target,
1049 // rather than creating a leaf node for it.
1050 if ((LHSR.second - LHSR.first) == 1 &&
1051 LHSR.first->first == CR.GE &&
1052 cast<ConstantIntegral>(C)->getRawValue() ==
1053 (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) {
1054 LHSBB = LHSR.first->second;
1056 LHSBB = new MachineBasicBlock(LLVMBB);
1057 CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR));
1059 // Similar to the optimization above, if the Value being switched on is
1060 // known to be less than the Constant CR.LT, and the current Case Value
1061 // is CR.LT - 1, then we can branch directly to the target block for
1062 // the current Case Value, rather than emitting a RHS leaf node for it.
1063 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1064 cast<ConstantIntegral>(RHSR.first->first)->getRawValue() ==
1065 (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) {
1066 RHSBB = RHSR.first->second;
1068 RHSBB = new MachineBasicBlock(LLVMBB);
1069 CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR));
1071 // Create a CaseBlock record representing a conditional branch to
1072 // the LHS node if the value being switched on SV is less than C.
1073 // Otherwise, branch to LHS.
1074 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
1075 SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB);
1076 if (CR.CaseBB == CurMBB)
1077 visitSwitchCase(CB);
1079 SwitchCases.push_back(CB);
1080 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1086 void SelectionDAGLowering::visitSub(User &I) {
1087 // -0.0 - X --> fneg
1088 if (I.getType()->isFloatingPoint()) {
1089 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1090 if (CFP->isExactlyValue(-0.0)) {
1091 SDOperand Op2 = getValue(I.getOperand(1));
1092 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1096 visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
1099 void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
1101 const Type *Ty = I.getType();
1102 SDOperand Op1 = getValue(I.getOperand(0));
1103 SDOperand Op2 = getValue(I.getOperand(1));
1105 if (Ty->isIntegral()) {
1106 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
1107 } else if (Ty->isFloatingPoint()) {
1108 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
1110 const PackedType *PTy = cast<PackedType>(Ty);
1111 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1112 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1113 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1117 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1118 SDOperand Op1 = getValue(I.getOperand(0));
1119 SDOperand Op2 = getValue(I.getOperand(1));
1121 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1123 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1126 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
1127 ISD::CondCode UnsignedOpcode,
1128 ISD::CondCode FPOpcode) {
1129 SDOperand Op1 = getValue(I.getOperand(0));
1130 SDOperand Op2 = getValue(I.getOperand(1));
1131 ISD::CondCode Opcode = SignedOpcode;
1132 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint())
1134 else if (I.getOperand(0)->getType()->isUnsigned())
1135 Opcode = UnsignedOpcode;
1136 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1139 void SelectionDAGLowering::visitSelect(User &I) {
1140 SDOperand Cond = getValue(I.getOperand(0));
1141 SDOperand TrueVal = getValue(I.getOperand(1));
1142 SDOperand FalseVal = getValue(I.getOperand(2));
1143 if (!isa<PackedType>(I.getType())) {
1144 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1145 TrueVal, FalseVal));
1147 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1148 *(TrueVal.Val->op_end()-2),
1149 *(TrueVal.Val->op_end()-1)));
1153 void SelectionDAGLowering::visitCast(User &I) {
1154 SDOperand N = getValue(I.getOperand(0));
1155 MVT::ValueType SrcVT = N.getValueType();
1156 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1158 if (DestVT == MVT::Vector) {
1159 // This is a cast to a vector from something else. This is always a bit
1160 // convert. Get information about the input vector.
1161 const PackedType *DestTy = cast<PackedType>(I.getType());
1162 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1163 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1164 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1165 DAG.getValueType(EltVT)));
1166 } else if (SrcVT == DestVT) {
1167 setValue(&I, N); // noop cast.
1168 } else if (DestVT == MVT::i1) {
1169 // Cast to bool is a comparison against zero, not truncation to zero.
1170 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
1171 DAG.getConstantFP(0.0, N.getValueType());
1172 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
1173 } else if (isInteger(SrcVT)) {
1174 if (isInteger(DestVT)) { // Int -> Int cast
1175 if (DestVT < SrcVT) // Truncating cast?
1176 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1177 else if (I.getOperand(0)->getType()->isSigned())
1178 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1180 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1181 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast
1182 if (I.getOperand(0)->getType()->isSigned())
1183 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1185 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1187 assert(0 && "Unknown cast!");
1189 } else if (isFloatingPoint(SrcVT)) {
1190 if (isFloatingPoint(DestVT)) { // FP -> FP cast
1191 if (DestVT < SrcVT) // Rounding cast?
1192 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1194 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1195 } else if (isInteger(DestVT)) { // FP -> Int cast.
1196 if (I.getType()->isSigned())
1197 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1199 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1201 assert(0 && "Unknown cast!");
1204 assert(SrcVT == MVT::Vector && "Unknown cast!");
1205 assert(DestVT != MVT::Vector && "Casts to vector already handled!");
1206 // This is a cast from a vector to something else. This is always a bit
1207 // convert. Get information about the input vector.
1208 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1212 void SelectionDAGLowering::visitInsertElement(User &I) {
1213 SDOperand InVec = getValue(I.getOperand(0));
1214 SDOperand InVal = getValue(I.getOperand(1));
1215 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1216 getValue(I.getOperand(2)));
1218 SDOperand Num = *(InVec.Val->op_end()-2);
1219 SDOperand Typ = *(InVec.Val->op_end()-1);
1220 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1221 InVec, InVal, InIdx, Num, Typ));
1224 void SelectionDAGLowering::visitExtractElement(User &I) {
1225 SDOperand InVec = getValue(I.getOperand(0));
1226 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1227 getValue(I.getOperand(1)));
1228 SDOperand Typ = *(InVec.Val->op_end()-1);
1229 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1230 TLI.getValueType(I.getType()), InVec, InIdx));
1233 void SelectionDAGLowering::visitShuffleVector(User &I) {
1234 SDOperand V1 = getValue(I.getOperand(0));
1235 SDOperand V2 = getValue(I.getOperand(1));
1236 SDOperand Mask = getValue(I.getOperand(2));
1238 SDOperand Num = *(V1.Val->op_end()-2);
1239 SDOperand Typ = *(V2.Val->op_end()-1);
1240 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1241 V1, V2, Mask, Num, Typ));
1245 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1246 SDOperand N = getValue(I.getOperand(0));
1247 const Type *Ty = I.getOperand(0)->getType();
1249 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1252 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1253 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
1256 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
1257 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1258 getIntPtrConstant(Offset));
1260 Ty = StTy->getElementType(Field);
1262 Ty = cast<SequentialType>(Ty)->getElementType();
1264 // If this is a constant subscript, handle it quickly.
1265 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1266 if (CI->getRawValue() == 0) continue;
1269 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
1270 Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
1272 Offs = TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
1273 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1277 // N = N + Idx * ElementSize;
1278 uint64_t ElementSize = TD->getTypeSize(Ty);
1279 SDOperand IdxN = getValue(Idx);
1281 // If the index is smaller or larger than intptr_t, truncate or extend
1283 if (IdxN.getValueType() < N.getValueType()) {
1284 if (Idx->getType()->isSigned())
1285 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1287 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
1288 } else if (IdxN.getValueType() > N.getValueType())
1289 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1291 // If this is a multiply by a power of two, turn it into a shl
1292 // immediately. This is a very common case.
1293 if (isPowerOf2_64(ElementSize)) {
1294 unsigned Amt = Log2_64(ElementSize);
1295 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1296 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1297 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1301 SDOperand Scale = getIntPtrConstant(ElementSize);
1302 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1303 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1309 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1310 // If this is a fixed sized alloca in the entry block of the function,
1311 // allocate it statically on the stack.
1312 if (FuncInfo.StaticAllocaMap.count(&I))
1313 return; // getValue will auto-populate this.
1315 const Type *Ty = I.getAllocatedType();
1316 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1317 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
1320 SDOperand AllocSize = getValue(I.getArraySize());
1321 MVT::ValueType IntPtr = TLI.getPointerTy();
1322 if (IntPtr < AllocSize.getValueType())
1323 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1324 else if (IntPtr > AllocSize.getValueType())
1325 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1327 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1328 getIntPtrConstant(TySize));
1330 // Handle alignment. If the requested alignment is less than or equal to the
1331 // stack alignment, ignore it and round the size of the allocation up to the
1332 // stack alignment size. If the size is greater than the stack alignment, we
1333 // note this in the DYNAMIC_STACKALLOC node.
1334 unsigned StackAlign =
1335 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1336 if (Align <= StackAlign) {
1338 // Add SA-1 to the size.
1339 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1340 getIntPtrConstant(StackAlign-1));
1341 // Mask out the low bits for alignment purposes.
1342 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1343 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1346 std::vector<MVT::ValueType> VTs;
1347 VTs.push_back(AllocSize.getValueType());
1348 VTs.push_back(MVT::Other);
1349 std::vector<SDOperand> Ops;
1350 Ops.push_back(getRoot());
1351 Ops.push_back(AllocSize);
1352 Ops.push_back(getIntPtrConstant(Align));
1353 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
1354 DAG.setRoot(setValue(&I, DSA).getValue(1));
1356 // Inform the Frame Information that we have just allocated a variable-sized
1358 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1361 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1362 SDOperand Ptr = getValue(I.getOperand(0));
1368 // Do not serialize non-volatile loads against each other.
1369 Root = DAG.getRoot();
1372 setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)),
1373 Root, I.isVolatile()));
1376 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1377 SDOperand SrcValue, SDOperand Root,
1380 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1381 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1382 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue);
1384 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue);
1388 DAG.setRoot(L.getValue(1));
1390 PendingLoads.push_back(L.getValue(1));
1396 void SelectionDAGLowering::visitStore(StoreInst &I) {
1397 Value *SrcV = I.getOperand(0);
1398 SDOperand Src = getValue(SrcV);
1399 SDOperand Ptr = getValue(I.getOperand(1));
1400 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
1401 DAG.getSrcValue(I.getOperand(1))));
1404 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1405 /// access memory and has no other side effects at all.
1406 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1407 #define GET_NO_MEMORY_INTRINSICS
1408 #include "llvm/Intrinsics.gen"
1409 #undef GET_NO_MEMORY_INTRINSICS
1413 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1414 // have any side-effects or if it only reads memory.
1415 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1416 #define GET_SIDE_EFFECT_INFO
1417 #include "llvm/Intrinsics.gen"
1418 #undef GET_SIDE_EFFECT_INFO
1422 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1424 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1425 unsigned Intrinsic) {
1426 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1427 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1429 // Build the operand list.
1430 std::vector<SDOperand> Ops;
1431 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1433 // We don't need to serialize loads against other loads.
1434 Ops.push_back(DAG.getRoot());
1436 Ops.push_back(getRoot());
1440 // Add the intrinsic ID as an integer operand.
1441 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1443 // Add all operands of the call to the operand list.
1444 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1445 SDOperand Op = getValue(I.getOperand(i));
1447 // If this is a vector type, force it to the right packed type.
1448 if (Op.getValueType() == MVT::Vector) {
1449 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1450 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1452 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1453 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1454 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1457 assert(TLI.isTypeLegal(Op.getValueType()) &&
1458 "Intrinsic uses a non-legal type?");
1462 std::vector<MVT::ValueType> VTs;
1463 if (I.getType() != Type::VoidTy) {
1464 MVT::ValueType VT = TLI.getValueType(I.getType());
1465 if (VT == MVT::Vector) {
1466 const PackedType *DestTy = cast<PackedType>(I.getType());
1467 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1469 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1470 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1473 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1477 VTs.push_back(MVT::Other);
1482 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, Ops);
1483 else if (I.getType() != Type::VoidTy)
1484 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, Ops);
1486 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
1489 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1491 PendingLoads.push_back(Chain);
1495 if (I.getType() != Type::VoidTy) {
1496 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1497 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1498 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1499 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1500 DAG.getValueType(EVT));
1502 setValue(&I, Result);
1506 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1507 /// we want to emit this as a call to a named external function, return the name
1508 /// otherwise lower it and return null.
1510 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1511 switch (Intrinsic) {
1513 // By default, turn this into a target intrinsic node.
1514 visitTargetIntrinsic(I, Intrinsic);
1516 case Intrinsic::vastart: visitVAStart(I); return 0;
1517 case Intrinsic::vaend: visitVAEnd(I); return 0;
1518 case Intrinsic::vacopy: visitVACopy(I); return 0;
1519 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1520 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1521 case Intrinsic::setjmp:
1522 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1524 case Intrinsic::longjmp:
1525 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1527 case Intrinsic::memcpy_i32:
1528 case Intrinsic::memcpy_i64:
1529 visitMemIntrinsic(I, ISD::MEMCPY);
1531 case Intrinsic::memset_i32:
1532 case Intrinsic::memset_i64:
1533 visitMemIntrinsic(I, ISD::MEMSET);
1535 case Intrinsic::memmove_i32:
1536 case Intrinsic::memmove_i64:
1537 visitMemIntrinsic(I, ISD::MEMMOVE);
1540 case Intrinsic::dbg_stoppoint: {
1541 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1542 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1543 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
1544 std::vector<SDOperand> Ops;
1546 Ops.push_back(getRoot());
1547 Ops.push_back(getValue(SPI.getLineValue()));
1548 Ops.push_back(getValue(SPI.getColumnValue()));
1550 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
1551 assert(DD && "Not a debug information descriptor");
1552 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1554 Ops.push_back(DAG.getString(CompileUnit->getFileName()));
1555 Ops.push_back(DAG.getString(CompileUnit->getDirectory()));
1557 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops));
1562 case Intrinsic::dbg_region_start: {
1563 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1564 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1565 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
1566 std::vector<SDOperand> Ops;
1568 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
1570 Ops.push_back(getRoot());
1571 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1573 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1578 case Intrinsic::dbg_region_end: {
1579 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1580 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
1581 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
1582 std::vector<SDOperand> Ops;
1584 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
1586 Ops.push_back(getRoot());
1587 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1589 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1594 case Intrinsic::dbg_func_start: {
1595 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1596 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
1597 if (DebugInfo && FSI.getSubprogram() &&
1598 DebugInfo->Verify(FSI.getSubprogram())) {
1599 std::vector<SDOperand> Ops;
1601 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
1603 Ops.push_back(getRoot());
1604 Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
1606 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
1611 case Intrinsic::dbg_declare: {
1612 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1613 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
1614 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
1615 std::vector<SDOperand> Ops;
1617 SDOperand AddressOp = getValue(DI.getAddress());
1618 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) {
1619 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
1626 case Intrinsic::isunordered_f32:
1627 case Intrinsic::isunordered_f64:
1628 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
1629 getValue(I.getOperand(2)), ISD::SETUO));
1632 case Intrinsic::sqrt_f32:
1633 case Intrinsic::sqrt_f64:
1634 setValue(&I, DAG.getNode(ISD::FSQRT,
1635 getValue(I.getOperand(1)).getValueType(),
1636 getValue(I.getOperand(1))));
1638 case Intrinsic::pcmarker: {
1639 SDOperand Tmp = getValue(I.getOperand(1));
1640 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
1643 case Intrinsic::readcyclecounter: {
1644 std::vector<MVT::ValueType> VTs;
1645 VTs.push_back(MVT::i64);
1646 VTs.push_back(MVT::Other);
1647 std::vector<SDOperand> Ops;
1648 Ops.push_back(getRoot());
1649 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops);
1651 DAG.setRoot(Tmp.getValue(1));
1654 case Intrinsic::bswap_i16:
1655 case Intrinsic::bswap_i32:
1656 case Intrinsic::bswap_i64:
1657 setValue(&I, DAG.getNode(ISD::BSWAP,
1658 getValue(I.getOperand(1)).getValueType(),
1659 getValue(I.getOperand(1))));
1661 case Intrinsic::cttz_i8:
1662 case Intrinsic::cttz_i16:
1663 case Intrinsic::cttz_i32:
1664 case Intrinsic::cttz_i64:
1665 setValue(&I, DAG.getNode(ISD::CTTZ,
1666 getValue(I.getOperand(1)).getValueType(),
1667 getValue(I.getOperand(1))));
1669 case Intrinsic::ctlz_i8:
1670 case Intrinsic::ctlz_i16:
1671 case Intrinsic::ctlz_i32:
1672 case Intrinsic::ctlz_i64:
1673 setValue(&I, DAG.getNode(ISD::CTLZ,
1674 getValue(I.getOperand(1)).getValueType(),
1675 getValue(I.getOperand(1))));
1677 case Intrinsic::ctpop_i8:
1678 case Intrinsic::ctpop_i16:
1679 case Intrinsic::ctpop_i32:
1680 case Intrinsic::ctpop_i64:
1681 setValue(&I, DAG.getNode(ISD::CTPOP,
1682 getValue(I.getOperand(1)).getValueType(),
1683 getValue(I.getOperand(1))));
1685 case Intrinsic::stacksave: {
1686 std::vector<MVT::ValueType> VTs;
1687 VTs.push_back(TLI.getPointerTy());
1688 VTs.push_back(MVT::Other);
1689 std::vector<SDOperand> Ops;
1690 Ops.push_back(getRoot());
1691 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, Ops);
1693 DAG.setRoot(Tmp.getValue(1));
1696 case Intrinsic::stackrestore: {
1697 SDOperand Tmp = getValue(I.getOperand(1));
1698 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
1701 case Intrinsic::prefetch:
1702 // FIXME: Currently discarding prefetches.
1708 void SelectionDAGLowering::visitCall(CallInst &I) {
1709 const char *RenameFn = 0;
1710 if (Function *F = I.getCalledFunction()) {
1711 if (F->isExternal())
1712 if (unsigned IID = F->getIntrinsicID()) {
1713 RenameFn = visitIntrinsicCall(I, IID);
1716 } else { // Not an LLVM intrinsic.
1717 const std::string &Name = F->getName();
1718 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
1719 if (I.getNumOperands() == 3 && // Basic sanity checks.
1720 I.getOperand(1)->getType()->isFloatingPoint() &&
1721 I.getType() == I.getOperand(1)->getType() &&
1722 I.getType() == I.getOperand(2)->getType()) {
1723 SDOperand LHS = getValue(I.getOperand(1));
1724 SDOperand RHS = getValue(I.getOperand(2));
1725 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
1729 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
1730 if (I.getNumOperands() == 2 && // Basic sanity checks.
1731 I.getOperand(1)->getType()->isFloatingPoint() &&
1732 I.getType() == I.getOperand(1)->getType()) {
1733 SDOperand Tmp = getValue(I.getOperand(1));
1734 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
1737 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
1738 if (I.getNumOperands() == 2 && // Basic sanity checks.
1739 I.getOperand(1)->getType()->isFloatingPoint() &&
1740 I.getType() == I.getOperand(1)->getType()) {
1741 SDOperand Tmp = getValue(I.getOperand(1));
1742 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
1745 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
1746 if (I.getNumOperands() == 2 && // Basic sanity checks.
1747 I.getOperand(1)->getType()->isFloatingPoint() &&
1748 I.getType() == I.getOperand(1)->getType()) {
1749 SDOperand Tmp = getValue(I.getOperand(1));
1750 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
1755 } else if (isa<InlineAsm>(I.getOperand(0))) {
1762 Callee = getValue(I.getOperand(0));
1764 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
1765 std::vector<std::pair<SDOperand, const Type*> > Args;
1766 Args.reserve(I.getNumOperands());
1767 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1768 Value *Arg = I.getOperand(i);
1769 SDOperand ArgNode = getValue(Arg);
1770 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
1773 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
1774 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1776 std::pair<SDOperand,SDOperand> Result =
1777 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
1778 I.isTailCall(), Callee, Args, DAG);
1779 if (I.getType() != Type::VoidTy)
1780 setValue(&I, Result.first);
1781 DAG.setRoot(Result.second);
1784 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
1785 SDOperand &Chain, SDOperand &Flag)const{
1786 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
1787 Chain = Val.getValue(1);
1788 Flag = Val.getValue(2);
1790 // If the result was expanded, copy from the top part.
1791 if (Regs.size() > 1) {
1792 assert(Regs.size() == 2 &&
1793 "Cannot expand to more than 2 elts yet!");
1794 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
1795 Chain = Val.getValue(1);
1796 Flag = Val.getValue(2);
1797 if (DAG.getTargetLoweringInfo().isLittleEndian())
1798 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
1800 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
1803 // Otherwise, if the return value was promoted or extended, truncate it to the
1804 // appropriate type.
1805 if (RegVT == ValueVT)
1808 if (MVT::isInteger(RegVT)) {
1809 if (ValueVT < RegVT)
1810 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1812 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
1814 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
1818 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
1819 /// specified value into the registers specified by this object. This uses
1820 /// Chain/Flag as the input and updates them for the output Chain/Flag.
1821 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
1822 SDOperand &Chain, SDOperand &Flag,
1823 MVT::ValueType PtrVT) const {
1824 if (Regs.size() == 1) {
1825 // If there is a single register and the types differ, this must be
1827 if (RegVT != ValueVT) {
1828 if (MVT::isInteger(RegVT)) {
1829 if (RegVT < ValueVT)
1830 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
1832 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
1834 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
1836 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
1837 Flag = Chain.getValue(1);
1839 std::vector<unsigned> R(Regs);
1840 if (!DAG.getTargetLoweringInfo().isLittleEndian())
1841 std::reverse(R.begin(), R.end());
1843 for (unsigned i = 0, e = R.size(); i != e; ++i) {
1844 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
1845 DAG.getConstant(i, PtrVT));
1846 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
1847 Flag = Chain.getValue(1);
1852 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
1853 /// operand list. This adds the code marker and includes the number of
1854 /// values added into it.
1855 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
1856 std::vector<SDOperand> &Ops) const {
1857 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
1858 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1859 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
1862 /// isAllocatableRegister - If the specified register is safe to allocate,
1863 /// i.e. it isn't a stack pointer or some other special register, return the
1864 /// register class for the register. Otherwise, return null.
1865 static const TargetRegisterClass *
1866 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
1867 const TargetLowering &TLI, const MRegisterInfo *MRI) {
1868 MVT::ValueType FoundVT = MVT::Other;
1869 const TargetRegisterClass *FoundRC = 0;
1870 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
1871 E = MRI->regclass_end(); RCI != E; ++RCI) {
1872 MVT::ValueType ThisVT = MVT::Other;
1874 const TargetRegisterClass *RC = *RCI;
1875 // If none of the the value types for this register class are valid, we
1876 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1877 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1879 if (TLI.isTypeLegal(*I)) {
1880 // If we have already found this register in a different register class,
1881 // choose the one with the largest VT specified. For example, on
1882 // PowerPC, we favor f64 register classes over f32.
1883 if (FoundVT == MVT::Other ||
1884 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
1891 if (ThisVT == MVT::Other) continue;
1893 // NOTE: This isn't ideal. In particular, this might allocate the
1894 // frame pointer in functions that need it (due to them not being taken
1895 // out of allocation, because a variable sized allocation hasn't been seen
1896 // yet). This is a slight code pessimization, but should still work.
1897 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
1898 E = RC->allocation_order_end(MF); I != E; ++I)
1900 // We found a matching register class. Keep looking at others in case
1901 // we find one with larger registers that this physreg is also in.
1910 RegsForValue SelectionDAGLowering::
1911 GetRegistersForValue(const std::string &ConstrCode,
1912 MVT::ValueType VT, bool isOutReg, bool isInReg,
1913 std::set<unsigned> &OutputRegs,
1914 std::set<unsigned> &InputRegs) {
1915 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
1916 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
1917 std::vector<unsigned> Regs;
1919 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
1920 MVT::ValueType RegVT;
1921 MVT::ValueType ValueVT = VT;
1923 if (PhysReg.first) {
1924 if (VT == MVT::Other)
1925 ValueVT = *PhysReg.second->vt_begin();
1927 // Get the actual register value type. This is important, because the user
1928 // may have asked for (e.g.) the AX register in i32 type. We need to
1929 // remember that AX is actually i16 to get the right extension.
1930 RegVT = *PhysReg.second->vt_begin();
1932 // This is a explicit reference to a physical register.
1933 Regs.push_back(PhysReg.first);
1935 // If this is an expanded reference, add the rest of the regs to Regs.
1937 TargetRegisterClass::iterator I = PhysReg.second->begin();
1938 TargetRegisterClass::iterator E = PhysReg.second->end();
1939 for (; *I != PhysReg.first; ++I)
1940 assert(I != E && "Didn't find reg!");
1942 // Already added the first reg.
1944 for (; NumRegs; --NumRegs, ++I) {
1945 assert(I != E && "Ran out of registers to allocate!");
1949 return RegsForValue(Regs, RegVT, ValueVT);
1952 // This is a reference to a register class. Allocate NumRegs consecutive,
1953 // available, registers from the class.
1954 std::vector<unsigned> RegClassRegs =
1955 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
1957 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
1958 MachineFunction &MF = *CurMBB->getParent();
1959 unsigned NumAllocated = 0;
1960 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
1961 unsigned Reg = RegClassRegs[i];
1962 // See if this register is available.
1963 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
1964 (isInReg && InputRegs.count(Reg))) { // Already used.
1965 // Make sure we find consecutive registers.
1970 // Check to see if this register is allocatable (i.e. don't give out the
1972 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
1974 // Make sure we find consecutive registers.
1979 // Okay, this register is good, we can use it.
1982 // If we allocated enough consecutive
1983 if (NumAllocated == NumRegs) {
1984 unsigned RegStart = (i-NumAllocated)+1;
1985 unsigned RegEnd = i+1;
1986 // Mark all of the allocated registers used.
1987 for (unsigned i = RegStart; i != RegEnd; ++i) {
1988 unsigned Reg = RegClassRegs[i];
1989 Regs.push_back(Reg);
1990 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
1991 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
1994 return RegsForValue(Regs, *RC->vt_begin(), VT);
1998 // Otherwise, we couldn't allocate enough registers for this.
1999 return RegsForValue();
2003 /// visitInlineAsm - Handle a call to an InlineAsm object.
2005 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
2006 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
2008 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
2011 // Note, we treat inline asms both with and without side-effects as the same.
2012 // If an inline asm doesn't have side effects and doesn't access memory, we
2013 // could not choose to not chain it.
2014 bool hasSideEffects = IA->hasSideEffects();
2016 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
2017 std::vector<MVT::ValueType> ConstraintVTs;
2019 /// AsmNodeOperands - A list of pairs. The first element is a register, the
2020 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
2021 /// if it is a def of that register.
2022 std::vector<SDOperand> AsmNodeOperands;
2023 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
2024 AsmNodeOperands.push_back(AsmStr);
2026 SDOperand Chain = getRoot();
2029 // We fully assign registers here at isel time. This is not optimal, but
2030 // should work. For register classes that correspond to LLVM classes, we
2031 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
2032 // over the constraints, collecting fixed registers that we know we can't use.
2033 std::set<unsigned> OutputRegs, InputRegs;
2035 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2036 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2037 std::string &ConstraintCode = Constraints[i].Codes[0];
2039 MVT::ValueType OpVT;
2041 // Compute the value type for each operand and add it to ConstraintVTs.
2042 switch (Constraints[i].Type) {
2043 case InlineAsm::isOutput:
2044 if (!Constraints[i].isIndirectOutput) {
2045 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2046 OpVT = TLI.getValueType(I.getType());
2048 const Type *OpTy = I.getOperand(OpNum)->getType();
2049 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2050 OpNum++; // Consumes a call operand.
2053 case InlineAsm::isInput:
2054 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2055 OpNum++; // Consumes a call operand.
2057 case InlineAsm::isClobber:
2062 ConstraintVTs.push_back(OpVT);
2064 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2065 continue; // Not assigned a fixed reg.
2067 // Build a list of regs that this operand uses. This always has a single
2068 // element for promoted/expanded operands.
2069 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2071 OutputRegs, InputRegs);
2073 switch (Constraints[i].Type) {
2074 case InlineAsm::isOutput:
2075 // We can't assign any other output to this register.
2076 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2077 // If this is an early-clobber output, it cannot be assigned to the same
2078 // value as the input reg.
2079 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2080 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2082 case InlineAsm::isInput:
2083 // We can't assign any other input to this register.
2084 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2086 case InlineAsm::isClobber:
2087 // Clobbered regs cannot be used as inputs or outputs.
2088 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2089 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2094 // Loop over all of the inputs, copying the operand values into the
2095 // appropriate registers and processing the output regs.
2096 RegsForValue RetValRegs;
2097 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2100 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2101 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2102 std::string &ConstraintCode = Constraints[i].Codes[0];
2104 switch (Constraints[i].Type) {
2105 case InlineAsm::isOutput: {
2106 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2107 if (ConstraintCode.size() == 1) // not a physreg name.
2108 CTy = TLI.getConstraintType(ConstraintCode[0]);
2110 if (CTy == TargetLowering::C_Memory) {
2112 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2114 // Check that the operand (the address to store to) isn't a float.
2115 if (!MVT::isInteger(InOperandVal.getValueType()))
2116 assert(0 && "MATCH FAIL!");
2118 if (!Constraints[i].isIndirectOutput)
2119 assert(0 && "MATCH FAIL!");
2121 OpNum++; // Consumes a call operand.
2123 // Extend/truncate to the right pointer type if needed.
2124 MVT::ValueType PtrType = TLI.getPointerTy();
2125 if (InOperandVal.getValueType() < PtrType)
2126 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2127 else if (InOperandVal.getValueType() > PtrType)
2128 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2130 // Add information to the INLINEASM node to know about this output.
2131 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2132 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2133 AsmNodeOperands.push_back(InOperandVal);
2137 // Otherwise, this is a register output.
2138 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2140 // If this is an early-clobber output, or if there is an input
2141 // constraint that matches this, we need to reserve the input register
2142 // so no other inputs allocate to it.
2143 bool UsesInputRegister = false;
2144 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2145 UsesInputRegister = true;
2147 // Copy the output from the appropriate register. Find a register that
2150 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2151 true, UsesInputRegister,
2152 OutputRegs, InputRegs);
2153 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
2155 if (!Constraints[i].isIndirectOutput) {
2156 assert(RetValRegs.Regs.empty() &&
2157 "Cannot have multiple output constraints yet!");
2158 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2161 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2162 I.getOperand(OpNum)));
2163 OpNum++; // Consumes a call operand.
2166 // Add information to the INLINEASM node to know that this register is
2168 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2171 case InlineAsm::isInput: {
2172 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2173 OpNum++; // Consumes a call operand.
2175 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2176 // If this is required to match an output register we have already set,
2177 // just use its register.
2178 unsigned OperandNo = atoi(ConstraintCode.c_str());
2180 // Scan until we find the definition we already emitted of this operand.
2181 // When we find it, create a RegsForValue operand.
2182 unsigned CurOp = 2; // The first operand.
2183 for (; OperandNo; --OperandNo) {
2184 // Advance to the next operand.
2186 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2187 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
2188 (NumOps & 7) == 4 /*MEM*/) &&
2189 "Skipped past definitions?");
2190 CurOp += (NumOps>>3)+1;
2194 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2195 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2196 "Skipped past definitions?");
2198 // Add NumOps>>3 registers to MatchedRegs.
2199 RegsForValue MatchedRegs;
2200 MatchedRegs.ValueVT = InOperandVal.getValueType();
2201 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2202 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2203 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2204 MatchedRegs.Regs.push_back(Reg);
2207 // Use the produced MatchedRegs object to
2208 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag,
2209 TLI.getPointerTy());
2210 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2214 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2215 if (ConstraintCode.size() == 1) // not a physreg name.
2216 CTy = TLI.getConstraintType(ConstraintCode[0]);
2218 if (CTy == TargetLowering::C_Other) {
2219 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
2220 assert(0 && "MATCH FAIL!");
2222 // Add information to the INLINEASM node to know about this input.
2223 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2224 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2225 AsmNodeOperands.push_back(InOperandVal);
2227 } else if (CTy == TargetLowering::C_Memory) {
2230 // Check that the operand isn't a float.
2231 if (!MVT::isInteger(InOperandVal.getValueType()))
2232 assert(0 && "MATCH FAIL!");
2234 // Extend/truncate to the right pointer type if needed.
2235 MVT::ValueType PtrType = TLI.getPointerTy();
2236 if (InOperandVal.getValueType() < PtrType)
2237 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2238 else if (InOperandVal.getValueType() > PtrType)
2239 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2241 // Add information to the INLINEASM node to know about this input.
2242 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2243 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2244 AsmNodeOperands.push_back(InOperandVal);
2248 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2250 // Copy the input into the appropriate registers.
2251 RegsForValue InRegs =
2252 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2253 false, true, OutputRegs, InputRegs);
2254 // FIXME: should be match fail.
2255 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2257 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy());
2259 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2262 case InlineAsm::isClobber: {
2263 RegsForValue ClobberedRegs =
2264 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2265 OutputRegs, InputRegs);
2266 // Add the clobbered value to the operand list, so that the register
2267 // allocator is aware that the physreg got clobbered.
2268 if (!ClobberedRegs.Regs.empty())
2269 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2275 // Finish up input operands.
2276 AsmNodeOperands[0] = Chain;
2277 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2279 std::vector<MVT::ValueType> VTs;
2280 VTs.push_back(MVT::Other);
2281 VTs.push_back(MVT::Flag);
2282 Chain = DAG.getNode(ISD::INLINEASM, VTs, AsmNodeOperands);
2283 Flag = Chain.getValue(1);
2285 // If this asm returns a register value, copy the result from that register
2286 // and set it as the value of the call.
2287 if (!RetValRegs.Regs.empty())
2288 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2290 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2292 // Process indirect outputs, first output all of the flagged copies out of
2294 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2295 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2296 Value *Ptr = IndirectStoresToEmit[i].second;
2297 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2298 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2301 // Emit the non-flagged stores from the physregs.
2302 std::vector<SDOperand> OutChains;
2303 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2304 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
2305 StoresToEmit[i].first,
2306 getValue(StoresToEmit[i].second),
2307 DAG.getSrcValue(StoresToEmit[i].second)));
2308 if (!OutChains.empty())
2309 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
2314 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2315 SDOperand Src = getValue(I.getOperand(0));
2317 MVT::ValueType IntPtr = TLI.getPointerTy();
2319 if (IntPtr < Src.getValueType())
2320 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2321 else if (IntPtr > Src.getValueType())
2322 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2324 // Scale the source by the type size.
2325 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
2326 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2327 Src, getIntPtrConstant(ElementSize));
2329 std::vector<std::pair<SDOperand, const Type*> > Args;
2330 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType()));
2332 std::pair<SDOperand,SDOperand> Result =
2333 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
2334 DAG.getExternalSymbol("malloc", IntPtr),
2336 setValue(&I, Result.first); // Pointers always fit in registers
2337 DAG.setRoot(Result.second);
2340 void SelectionDAGLowering::visitFree(FreeInst &I) {
2341 std::vector<std::pair<SDOperand, const Type*> > Args;
2342 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
2343 TLI.getTargetData()->getIntPtrType()));
2344 MVT::ValueType IntPtr = TLI.getPointerTy();
2345 std::pair<SDOperand,SDOperand> Result =
2346 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
2347 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2348 DAG.setRoot(Result.second);
2351 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2352 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2353 // instructions are special in various ways, which require special support to
2354 // insert. The specified MachineInstr is created but not inserted into any
2355 // basic blocks, and the scheduler passes ownership of it to this method.
2356 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2357 MachineBasicBlock *MBB) {
2358 std::cerr << "If a target marks an instruction with "
2359 "'usesCustomDAGSchedInserter', it must implement "
2360 "TargetLowering::InsertAtEndOfBasicBlock!\n";
2365 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2366 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2367 getValue(I.getOperand(1)),
2368 DAG.getSrcValue(I.getOperand(1))));
2371 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2372 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2373 getValue(I.getOperand(0)),
2374 DAG.getSrcValue(I.getOperand(0)));
2376 DAG.setRoot(V.getValue(1));
2379 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2380 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2381 getValue(I.getOperand(1)),
2382 DAG.getSrcValue(I.getOperand(1))));
2385 void SelectionDAGLowering::visitVACopy(CallInst &I) {
2386 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2387 getValue(I.getOperand(1)),
2388 getValue(I.getOperand(2)),
2389 DAG.getSrcValue(I.getOperand(1)),
2390 DAG.getSrcValue(I.getOperand(2))));
2393 /// TargetLowering::LowerArguments - This is the default LowerArguments
2394 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
2395 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
2396 /// integrated into SDISel.
2397 std::vector<SDOperand>
2398 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2399 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2400 std::vector<SDOperand> Ops;
2401 Ops.push_back(DAG.getRoot());
2402 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2403 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2405 // Add one result value for each formal argument.
2406 std::vector<MVT::ValueType> RetVals;
2407 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2408 MVT::ValueType VT = getValueType(I->getType());
2410 switch (getTypeAction(VT)) {
2411 default: assert(0 && "Unknown type action!");
2413 RetVals.push_back(VT);
2416 RetVals.push_back(getTypeToTransformTo(VT));
2419 if (VT != MVT::Vector) {
2420 // If this is a large integer, it needs to be broken up into small
2421 // integers. Figure out what the destination type is and how many small
2422 // integers it turns into.
2423 MVT::ValueType NVT = getTypeToTransformTo(VT);
2424 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2425 for (unsigned i = 0; i != NumVals; ++i)
2426 RetVals.push_back(NVT);
2428 // Otherwise, this is a vector type. We only support legal vectors
2430 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2431 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2433 // Figure out if there is a Packed type corresponding to this Vector
2434 // type. If so, convert to the packed type.
2435 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2436 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2437 RetVals.push_back(TVT);
2439 assert(0 && "Don't support illegal by-val vector arguments yet!");
2446 RetVals.push_back(MVT::Other);
2449 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals, Ops).Val;
2451 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
2453 // Set up the return result vector.
2456 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2457 MVT::ValueType VT = getValueType(I->getType());
2459 switch (getTypeAction(VT)) {
2460 default: assert(0 && "Unknown type action!");
2462 Ops.push_back(SDOperand(Result, i++));
2465 SDOperand Op(Result, i++);
2466 if (MVT::isInteger(VT)) {
2467 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
2469 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
2470 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2472 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2473 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2479 if (VT != MVT::Vector) {
2480 // If this is a large integer, it needs to be reassembled from small
2481 // integers. Figure out what the source elt type is and how many small
2483 MVT::ValueType NVT = getTypeToTransformTo(VT);
2484 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2486 SDOperand Lo = SDOperand(Result, i++);
2487 SDOperand Hi = SDOperand(Result, i++);
2489 if (!isLittleEndian())
2492 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
2494 // Value scalarized into many values. Unimp for now.
2495 assert(0 && "Cannot expand i64 -> i16 yet!");
2498 // Otherwise, this is a vector type. We only support legal vectors
2500 const PackedType *PTy = cast<PackedType>(I->getType());
2501 unsigned NumElems = PTy->getNumElements();
2502 const Type *EltTy = PTy->getElementType();
2504 // Figure out if there is a Packed type corresponding to this Vector
2505 // type. If so, convert to the packed type.
2506 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2507 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2508 SDOperand N = SDOperand(Result, i++);
2509 // Handle copies from generic vectors to registers.
2510 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
2511 DAG.getConstant(NumElems, MVT::i32),
2512 DAG.getValueType(getValueType(EltTy)));
2515 assert(0 && "Don't support illegal by-val vector arguments yet!");
2526 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
2527 /// implementation, which just inserts an ISD::CALL node, which is later custom
2528 /// lowered by the target to something concrete. FIXME: When all targets are
2529 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
2530 std::pair<SDOperand, SDOperand>
2531 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
2532 unsigned CallingConv, bool isTailCall,
2534 ArgListTy &Args, SelectionDAG &DAG) {
2535 std::vector<SDOperand> Ops;
2536 Ops.push_back(Chain); // Op#0 - Chain
2537 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
2538 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
2539 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
2540 Ops.push_back(Callee);
2542 // Handle all of the outgoing arguments.
2543 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
2544 MVT::ValueType VT = getValueType(Args[i].second);
2545 SDOperand Op = Args[i].first;
2546 bool isSigned = Args[i].second->isSigned();
2547 switch (getTypeAction(VT)) {
2548 default: assert(0 && "Unknown type action!");
2551 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2554 if (MVT::isInteger(VT)) {
2555 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2556 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
2558 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2559 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
2562 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2565 if (VT != MVT::Vector) {
2566 // If this is a large integer, it needs to be broken down into small
2567 // integers. Figure out what the source elt type is and how many small
2569 MVT::ValueType NVT = getTypeToTransformTo(VT);
2570 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2572 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2573 DAG.getConstant(0, getPointerTy()));
2574 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2575 DAG.getConstant(1, getPointerTy()));
2576 if (!isLittleEndian())
2580 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2582 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2584 // Value scalarized into many values. Unimp for now.
2585 assert(0 && "Cannot expand i64 -> i16 yet!");
2588 // Otherwise, this is a vector type. We only support legal vectors
2590 const PackedType *PTy = cast<PackedType>(Args[i].second);
2591 unsigned NumElems = PTy->getNumElements();
2592 const Type *EltTy = PTy->getElementType();
2594 // Figure out if there is a Packed type corresponding to this Vector
2595 // type. If so, convert to the packed type.
2596 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2597 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2598 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
2599 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
2601 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2603 assert(0 && "Don't support illegal by-val vector call args yet!");
2611 // Figure out the result value types.
2612 std::vector<MVT::ValueType> RetTys;
2614 if (RetTy != Type::VoidTy) {
2615 MVT::ValueType VT = getValueType(RetTy);
2616 switch (getTypeAction(VT)) {
2617 default: assert(0 && "Unknown type action!");
2619 RetTys.push_back(VT);
2622 RetTys.push_back(getTypeToTransformTo(VT));
2625 if (VT != MVT::Vector) {
2626 // If this is a large integer, it needs to be reassembled from small
2627 // integers. Figure out what the source elt type is and how many small
2629 MVT::ValueType NVT = getTypeToTransformTo(VT);
2630 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2631 for (unsigned i = 0; i != NumVals; ++i)
2632 RetTys.push_back(NVT);
2634 // Otherwise, this is a vector type. We only support legal vectors
2636 const PackedType *PTy = cast<PackedType>(RetTy);
2637 unsigned NumElems = PTy->getNumElements();
2638 const Type *EltTy = PTy->getElementType();
2640 // Figure out if there is a Packed type corresponding to this Vector
2641 // type. If so, convert to the packed type.
2642 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2643 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2644 RetTys.push_back(TVT);
2646 assert(0 && "Don't support illegal by-val vector call results yet!");
2653 RetTys.push_back(MVT::Other); // Always has a chain.
2655 // Finally, create the CALL node.
2656 SDOperand Res = DAG.getNode(ISD::CALL, RetTys, Ops);
2658 // This returns a pair of operands. The first element is the
2659 // return value for the function (if RetTy is not VoidTy). The second
2660 // element is the outgoing token chain.
2662 if (RetTys.size() != 1) {
2663 MVT::ValueType VT = getValueType(RetTy);
2664 if (RetTys.size() == 2) {
2667 // If this value was promoted, truncate it down.
2668 if (ResVal.getValueType() != VT) {
2669 if (VT == MVT::Vector) {
2670 // Insert a VBITCONVERT to convert from the packed result type to the
2671 // MVT::Vector type.
2672 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
2673 const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
2675 // Figure out if there is a Packed type corresponding to this Vector
2676 // type. If so, convert to the packed type.
2677 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2678 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2679 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
2680 // "N x PTyElementVT" MVT::Vector type.
2681 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
2682 DAG.getConstant(NumElems, MVT::i32),
2683 DAG.getValueType(getValueType(EltTy)));
2687 } else if (MVT::isInteger(VT)) {
2688 unsigned AssertOp = RetTy->isSigned() ?
2689 ISD::AssertSext : ISD::AssertZext;
2690 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
2691 DAG.getValueType(VT));
2692 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
2694 assert(MVT::isFloatingPoint(VT));
2695 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
2698 } else if (RetTys.size() == 3) {
2699 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
2700 Res.getValue(0), Res.getValue(1));
2703 assert(0 && "Case not handled yet!");
2707 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
2712 // It is always conservatively correct for llvm.returnaddress and
2713 // llvm.frameaddress to return 0.
2715 // FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
2716 // expanded to 0 if the target wants.
2717 std::pair<SDOperand, SDOperand>
2718 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
2719 unsigned Depth, SelectionDAG &DAG) {
2720 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
2723 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2724 assert(0 && "LowerOperation not implemented for this target!");
2729 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
2730 SelectionDAG &DAG) {
2731 assert(0 && "CustomPromoteOperation not implemented for this target!");
2736 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
2737 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
2738 std::pair<SDOperand,SDOperand> Result =
2739 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
2740 setValue(&I, Result.first);
2741 DAG.setRoot(Result.second);
2744 /// getMemsetValue - Vectorized representation of the memset value
2746 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
2747 SelectionDAG &DAG) {
2748 MVT::ValueType CurVT = VT;
2749 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2750 uint64_t Val = C->getValue() & 255;
2752 while (CurVT != MVT::i8) {
2753 Val = (Val << Shift) | Val;
2755 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2757 return DAG.getConstant(Val, VT);
2759 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
2761 while (CurVT != MVT::i8) {
2763 DAG.getNode(ISD::OR, VT,
2764 DAG.getNode(ISD::SHL, VT, Value,
2765 DAG.getConstant(Shift, MVT::i8)), Value);
2767 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
2774 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2775 /// used when a memcpy is turned into a memset when the source is a constant
2777 static SDOperand getMemsetStringVal(MVT::ValueType VT,
2778 SelectionDAG &DAG, TargetLowering &TLI,
2779 std::string &Str, unsigned Offset) {
2780 MVT::ValueType CurVT = VT;
2782 unsigned MSB = getSizeInBits(VT) / 8;
2783 if (TLI.isLittleEndian())
2784 Offset = Offset + MSB - 1;
2785 for (unsigned i = 0; i != MSB; ++i) {
2786 Val = (Val << 8) | Str[Offset];
2787 Offset += TLI.isLittleEndian() ? -1 : 1;
2789 return DAG.getConstant(Val, VT);
2792 /// getMemBasePlusOffset - Returns base and offset node for the
2793 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
2794 SelectionDAG &DAG, TargetLowering &TLI) {
2795 MVT::ValueType VT = Base.getValueType();
2796 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
2799 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
2800 /// to replace the memset / memcpy is below the threshold. It also returns the
2801 /// types of the sequence of memory ops to perform memset / memcpy.
2802 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
2803 unsigned Limit, uint64_t Size,
2804 unsigned Align, TargetLowering &TLI) {
2807 if (TLI.allowsUnalignedMemoryAccesses()) {
2810 switch (Align & 7) {
2826 MVT::ValueType LVT = MVT::i64;
2827 while (!TLI.isTypeLegal(LVT))
2828 LVT = (MVT::ValueType)((unsigned)LVT - 1);
2829 assert(MVT::isInteger(LVT));
2834 unsigned NumMemOps = 0;
2836 unsigned VTSize = getSizeInBits(VT) / 8;
2837 while (VTSize > Size) {
2838 VT = (MVT::ValueType)((unsigned)VT - 1);
2841 assert(MVT::isInteger(VT));
2843 if (++NumMemOps > Limit)
2845 MemOps.push_back(VT);
2852 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
2853 SDOperand Op1 = getValue(I.getOperand(1));
2854 SDOperand Op2 = getValue(I.getOperand(2));
2855 SDOperand Op3 = getValue(I.getOperand(3));
2856 SDOperand Op4 = getValue(I.getOperand(4));
2857 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
2858 if (Align == 0) Align = 1;
2860 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
2861 std::vector<MVT::ValueType> MemOps;
2863 // Expand memset / memcpy to a series of load / store ops
2864 // if the size operand falls below a certain threshold.
2865 std::vector<SDOperand> OutChains;
2867 default: break; // Do nothing for now.
2869 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
2870 Size->getValue(), Align, TLI)) {
2871 unsigned NumMemOps = MemOps.size();
2872 unsigned Offset = 0;
2873 for (unsigned i = 0; i < NumMemOps; i++) {
2874 MVT::ValueType VT = MemOps[i];
2875 unsigned VTSize = getSizeInBits(VT) / 8;
2876 SDOperand Value = getMemsetValue(Op2, VT, DAG);
2877 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(),
2879 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
2880 DAG.getSrcValue(I.getOperand(1), Offset));
2881 OutChains.push_back(Store);
2888 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
2889 Size->getValue(), Align, TLI)) {
2890 unsigned NumMemOps = MemOps.size();
2891 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
2892 GlobalAddressSDNode *G = NULL;
2894 bool CopyFromStr = false;
2896 if (Op2.getOpcode() == ISD::GlobalAddress)
2897 G = cast<GlobalAddressSDNode>(Op2);
2898 else if (Op2.getOpcode() == ISD::ADD &&
2899 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
2900 Op2.getOperand(1).getOpcode() == ISD::Constant) {
2901 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
2902 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
2905 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
2907 Str = GV->getStringValue(false);
2915 for (unsigned i = 0; i < NumMemOps; i++) {
2916 MVT::ValueType VT = MemOps[i];
2917 unsigned VTSize = getSizeInBits(VT) / 8;
2918 SDOperand Value, Chain, Store;
2921 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
2924 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2925 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2926 DAG.getSrcValue(I.getOperand(1), DstOff));
2928 Value = DAG.getLoad(VT, getRoot(),
2929 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
2930 DAG.getSrcValue(I.getOperand(2), SrcOff));
2931 Chain = Value.getValue(1);
2933 DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
2934 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2935 DAG.getSrcValue(I.getOperand(1), DstOff));
2937 OutChains.push_back(Store);
2946 if (!OutChains.empty()) {
2947 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
2952 std::vector<SDOperand> Ops;
2953 Ops.push_back(getRoot());
2958 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
2961 //===----------------------------------------------------------------------===//
2962 // SelectionDAGISel code
2963 //===----------------------------------------------------------------------===//
2965 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
2966 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
2969 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
2970 // FIXME: we only modify the CFG to split critical edges. This
2971 // updates dom and loop info.
2975 /// OptimizeNoopCopyExpression - We have determined that the specified cast
2976 /// instruction is a noop copy (e.g. it's casting from one pointer type to
2977 /// another, int->uint, or int->sbyte on PPC.
2979 /// Return true if any changes are made.
2980 static bool OptimizeNoopCopyExpression(CastInst *CI) {
2981 BasicBlock *DefBB = CI->getParent();
2983 /// InsertedCasts - Only insert a cast in each block once.
2984 std::map<BasicBlock*, CastInst*> InsertedCasts;
2986 bool MadeChange = false;
2987 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
2989 Use &TheUse = UI.getUse();
2990 Instruction *User = cast<Instruction>(*UI);
2992 // Figure out which BB this cast is used in. For PHI's this is the
2993 // appropriate predecessor block.
2994 BasicBlock *UserBB = User->getParent();
2995 if (PHINode *PN = dyn_cast<PHINode>(User)) {
2996 unsigned OpVal = UI.getOperandNo()/2;
2997 UserBB = PN->getIncomingBlock(OpVal);
3000 // Preincrement use iterator so we don't invalidate it.
3003 // If this user is in the same block as the cast, don't change the cast.
3004 if (UserBB == DefBB) continue;
3006 // If we have already inserted a cast into this block, use it.
3007 CastInst *&InsertedCast = InsertedCasts[UserBB];
3009 if (!InsertedCast) {
3010 BasicBlock::iterator InsertPt = UserBB->begin();
3011 while (isa<PHINode>(InsertPt)) ++InsertPt;
3014 new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3018 // Replace a use of the cast with a use of the new casat.
3019 TheUse = InsertedCast;
3022 // If we removed all uses, nuke the cast.
3023 if (CI->use_empty())
3024 CI->eraseFromParent();
3029 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
3030 /// casting to the type of GEPI.
3031 static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
3032 Instruction *GEPI, Value *Ptr,
3034 if (V) return V; // Already computed.
3036 BasicBlock::iterator InsertPt;
3037 if (BB == GEPI->getParent()) {
3038 // If insert into the GEP's block, insert right after the GEP.
3042 // Otherwise, insert at the top of BB, after any PHI nodes
3043 InsertPt = BB->begin();
3044 while (isa<PHINode>(InsertPt)) ++InsertPt;
3047 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3048 // BB so that there is only one value live across basic blocks (the cast
3050 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3051 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3052 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3054 // Add the offset, cast it to the right type.
3055 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
3056 return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
3059 /// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3060 /// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
3061 /// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3062 /// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
3063 /// sink PtrOffset into user blocks where doing so will likely allow us to fold
3064 /// the constant add into a load or store instruction. Additionally, if a user
3065 /// is a pointer-pointer cast, we look through it to find its users.
3066 static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3067 Constant *PtrOffset, BasicBlock *DefBB,
3068 GetElementPtrInst *GEPI,
3069 std::map<BasicBlock*,Instruction*> &InsertedExprs) {
3070 while (!RepPtr->use_empty()) {
3071 Instruction *User = cast<Instruction>(RepPtr->use_back());
3073 // If the user is a Pointer-Pointer cast, recurse.
3074 if (isa<CastInst>(User) && isa<PointerType>(User->getType())) {
3075 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3077 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
3078 // could invalidate an iterator.
3079 User->setOperand(0, UndefValue::get(RepPtr->getType()));
3083 // If this is a load of the pointer, or a store through the pointer, emit
3084 // the increment into the load/store block.
3085 Instruction *NewVal;
3086 if (isa<LoadInst>(User) ||
3087 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3088 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3089 User->getParent(), GEPI,
3092 // If this use is not foldable into the addressing mode, use a version
3093 // emitted in the GEP block.
3094 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3098 if (GEPI->getType() != RepPtr->getType()) {
3099 BasicBlock::iterator IP = NewVal;
3101 NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP);
3103 User->replaceUsesOfWith(RepPtr, NewVal);
3108 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3109 /// selection, we want to be a bit careful about some things. In particular, if
3110 /// we have a GEP instruction that is used in a different block than it is
3111 /// defined, the addressing expression of the GEP cannot be folded into loads or
3112 /// stores that use it. In this case, decompose the GEP and move constant
3113 /// indices into blocks that use it.
3114 static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
3115 const TargetData *TD) {
3116 // If this GEP is only used inside the block it is defined in, there is no
3117 // need to rewrite it.
3118 bool isUsedOutsideDefBB = false;
3119 BasicBlock *DefBB = GEPI->getParent();
3120 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3122 if (cast<Instruction>(*UI)->getParent() != DefBB) {
3123 isUsedOutsideDefBB = true;
3127 if (!isUsedOutsideDefBB) return false;
3129 // If this GEP has no non-zero constant indices, there is nothing we can do,
3131 bool hasConstantIndex = false;
3132 bool hasVariableIndex = false;
3133 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3134 E = GEPI->op_end(); OI != E; ++OI) {
3135 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
3136 if (CI->getRawValue()) {
3137 hasConstantIndex = true;
3141 hasVariableIndex = true;
3145 // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3146 if (!hasConstantIndex && !hasVariableIndex) {
3147 Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(),
3148 GEPI->getName(), GEPI);
3149 GEPI->replaceAllUsesWith(NC);
3150 GEPI->eraseFromParent();
3154 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
3155 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3158 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
3159 // constant offset (which we now know is non-zero) and deal with it later.
3160 uint64_t ConstantOffset = 0;
3161 const Type *UIntPtrTy = TD->getIntPtrType();
3162 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3163 const Type *Ty = GEPI->getOperand(0)->getType();
3165 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3166 E = GEPI->op_end(); OI != E; ++OI) {
3168 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3169 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
3171 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
3172 Ty = StTy->getElementType(Field);
3174 Ty = cast<SequentialType>(Ty)->getElementType();
3176 // Handle constant subscripts.
3177 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3178 if (CI->getRawValue() == 0) continue;
3180 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
3181 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
3183 ConstantOffset+=TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
3187 // Ptr = Ptr + Idx * ElementSize;
3189 // Cast Idx to UIntPtrTy if needed.
3190 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
3192 uint64_t ElementSize = TD->getTypeSize(Ty);
3193 // Mask off bits that should not be set.
3194 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3195 Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize);
3197 // Multiply by the element size and add to the base.
3198 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3199 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3203 // Make sure that the offset fits in uintptr_t.
3204 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3205 Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset);
3207 // Okay, we have now emitted all of the variable index parts to the BB that
3208 // the GEP is defined in. Loop over all of the using instructions, inserting
3209 // an "add Ptr, ConstantOffset" into each block that uses it and update the
3210 // instruction to use the newly computed value, making GEPI dead. When the
3211 // user is a load or store instruction address, we emit the add into the user
3212 // block, otherwise we use a canonical version right next to the gep (these
3213 // won't be foldable as addresses, so we might as well share the computation).
3215 std::map<BasicBlock*,Instruction*> InsertedExprs;
3216 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3218 // Finally, the GEP is dead, remove it.
3219 GEPI->eraseFromParent();
3224 bool SelectionDAGISel::runOnFunction(Function &Fn) {
3225 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3226 RegMap = MF.getSSARegMap();
3227 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
3229 // First, split all critical edges for PHI nodes with incoming values that are
3230 // constants, this way the load of the constant into a vreg will not be placed
3231 // into MBBs that are used some other way.
3233 // In this pass we also look for GEP and cast instructions that are used
3234 // across basic blocks and rewrite them to improve basic-block-at-a-time
3238 bool MadeChange = true;
3239 while (MadeChange) {
3241 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
3243 BasicBlock::iterator BBI;
3244 for (BBI = BB->begin(); (PN = dyn_cast<PHINode>(BBI)); ++BBI)
3245 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
3246 if (isa<Constant>(PN->getIncomingValue(i)))
3247 SplitCriticalEdge(PN->getIncomingBlock(i), BB);
3249 for (BasicBlock::iterator E = BB->end(); BBI != E; ) {
3250 Instruction *I = BBI++;
3251 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
3252 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
3253 } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
3254 // If this is a noop copy, sink it into user blocks to reduce the number
3255 // of virtual registers that must be created and coallesced.
3256 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
3257 MVT::ValueType DstVT = TLI.getValueType(CI->getType());
3259 // This is an fp<->int conversion?
3260 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
3263 // If this is an extension, it will be a zero or sign extension, which
3265 if (SrcVT < DstVT) continue;
3267 // If these values will be promoted, find out what they will be promoted
3268 // to. This helps us consider truncates on PPC as noop copies when they
3270 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
3271 SrcVT = TLI.getTypeToTransformTo(SrcVT);
3272 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
3273 DstVT = TLI.getTypeToTransformTo(DstVT);
3275 // If, after promotion, these are the same types, this is a noop copy.
3277 MadeChange |= OptimizeNoopCopyExpression(CI);
3283 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
3285 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
3286 SelectBasicBlock(I, MF, FuncInfo);
3292 SDOperand SelectionDAGISel::
3293 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
3294 SDOperand Op = SDL.getValue(V);
3295 assert((Op.getOpcode() != ISD::CopyFromReg ||
3296 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
3297 "Copy from a reg to the same reg!");
3299 // If this type is not legal, we must make sure to not create an invalid
3301 MVT::ValueType SrcVT = Op.getValueType();
3302 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
3303 SelectionDAG &DAG = SDL.DAG;
3304 if (SrcVT == DestVT) {
3305 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3306 } else if (SrcVT == MVT::Vector) {
3307 // Handle copies from generic vectors to registers.
3308 MVT::ValueType PTyElementVT, PTyLegalElementVT;
3309 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
3310 PTyElementVT, PTyLegalElementVT);
3312 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
3313 // MVT::Vector type.
3314 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
3315 DAG.getConstant(NE, MVT::i32),
3316 DAG.getValueType(PTyElementVT));
3318 // Loop over all of the elements of the resultant vector,
3319 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
3320 // copying them into output registers.
3321 std::vector<SDOperand> OutChains;
3322 SDOperand Root = SDL.getRoot();
3323 for (unsigned i = 0; i != NE; ++i) {
3324 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
3325 Op, DAG.getConstant(i, TLI.getPointerTy()));
3326 if (PTyElementVT == PTyLegalElementVT) {
3327 // Elements are legal.
3328 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3329 } else if (PTyLegalElementVT > PTyElementVT) {
3330 // Elements are promoted.
3331 if (MVT::isFloatingPoint(PTyLegalElementVT))
3332 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
3334 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
3335 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3337 // Elements are expanded.
3338 // The src value is expanded into multiple registers.
3339 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3340 Elt, DAG.getConstant(0, TLI.getPointerTy()));
3341 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3342 Elt, DAG.getConstant(1, TLI.getPointerTy()));
3343 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
3344 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
3347 return DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
3348 } else if (SrcVT < DestVT) {
3349 // The src value is promoted to the register.
3350 if (MVT::isFloatingPoint(SrcVT))
3351 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
3353 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
3354 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3356 // The src value is expanded into multiple registers.
3357 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3358 Op, DAG.getConstant(0, TLI.getPointerTy()));
3359 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3360 Op, DAG.getConstant(1, TLI.getPointerTy()));
3361 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
3362 return DAG.getCopyToReg(Op, Reg+1, Hi);
3366 void SelectionDAGISel::
3367 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
3368 std::vector<SDOperand> &UnorderedChains) {
3369 // If this is the entry block, emit arguments.
3370 Function &F = *BB->getParent();
3371 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
3372 SDOperand OldRoot = SDL.DAG.getRoot();
3373 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
3376 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
3378 if (!AI->use_empty()) {
3379 SDL.setValue(AI, Args[a]);
3381 // If this argument is live outside of the entry block, insert a copy from
3382 // whereever we got it to the vreg that other BB's will reference it as.
3383 if (FuncInfo.ValueMap.count(AI)) {
3385 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
3386 UnorderedChains.push_back(Copy);
3390 // Finally, if the target has anything special to do, allow it to do so.
3391 // FIXME: this should insert code into the DAG!
3392 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
3395 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3396 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
3397 FunctionLoweringInfo &FuncInfo) {
3398 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
3400 std::vector<SDOperand> UnorderedChains;
3402 // Lower any arguments needed in this block if this is the entry block.
3403 if (LLVMBB == &LLVMBB->getParent()->front())
3404 LowerArguments(LLVMBB, SDL, UnorderedChains);
3406 BB = FuncInfo.MBBMap[LLVMBB];
3407 SDL.setCurrentBasicBlock(BB);
3409 // Lower all of the non-terminator instructions.
3410 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3414 // Ensure that all instructions which are used outside of their defining
3415 // blocks are available as virtual registers.
3416 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
3417 if (!I->use_empty() && !isa<PHINode>(I)) {
3418 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
3419 if (VMI != FuncInfo.ValueMap.end())
3420 UnorderedChains.push_back(
3421 CopyValueToVirtualRegister(SDL, I, VMI->second));
3424 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
3425 // ensure constants are generated when needed. Remember the virtual registers
3426 // that need to be added to the Machine PHI nodes as input. We cannot just
3427 // directly add them, because expansion might result in multiple MBB's for one
3428 // BB. As such, the start of the BB might correspond to a different MBB than
3432 // Emit constants only once even if used by multiple PHI nodes.
3433 std::map<Constant*, unsigned> ConstantsOut;
3435 // Check successor nodes PHI nodes that expect a constant to be available from
3437 TerminatorInst *TI = LLVMBB->getTerminator();
3438 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
3439 BasicBlock *SuccBB = TI->getSuccessor(succ);
3440 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
3443 // At this point we know that there is a 1-1 correspondence between LLVM PHI
3444 // nodes and Machine PHI nodes, but the incoming operands have not been
3446 for (BasicBlock::iterator I = SuccBB->begin();
3447 (PN = dyn_cast<PHINode>(I)); ++I)
3448 if (!PN->use_empty()) {
3450 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
3451 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
3452 unsigned &RegOut = ConstantsOut[C];
3454 RegOut = FuncInfo.CreateRegForValue(C);
3455 UnorderedChains.push_back(
3456 CopyValueToVirtualRegister(SDL, C, RegOut));
3460 Reg = FuncInfo.ValueMap[PHIOp];
3462 assert(isa<AllocaInst>(PHIOp) &&
3463 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
3464 "Didn't codegen value into a register!??");
3465 Reg = FuncInfo.CreateRegForValue(PHIOp);
3466 UnorderedChains.push_back(
3467 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
3471 // Remember that this register needs to added to the machine PHI node as
3472 // the input for this MBB.
3473 MVT::ValueType VT = TLI.getValueType(PN->getType());
3474 unsigned NumElements;
3475 if (VT != MVT::Vector)
3476 NumElements = TLI.getNumElements(VT);
3478 MVT::ValueType VT1,VT2;
3480 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
3483 for (unsigned i = 0, e = NumElements; i != e; ++i)
3484 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
3487 ConstantsOut.clear();
3489 // Turn all of the unordered chains into one factored node.
3490 if (!UnorderedChains.empty()) {
3491 SDOperand Root = SDL.getRoot();
3492 if (Root.getOpcode() != ISD::EntryToken) {
3493 unsigned i = 0, e = UnorderedChains.size();
3494 for (; i != e; ++i) {
3495 assert(UnorderedChains[i].Val->getNumOperands() > 1);
3496 if (UnorderedChains[i].Val->getOperand(0) == Root)
3497 break; // Don't add the root if we already indirectly depend on it.
3501 UnorderedChains.push_back(Root);
3503 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
3506 // Lower the terminator after the copies are emitted.
3507 SDL.visit(*LLVMBB->getTerminator());
3509 // Copy over any CaseBlock records that may now exist due to SwitchInst
3510 // lowering, as well as any jump table information.
3511 SwitchCases.clear();
3512 SwitchCases = SDL.SwitchCases;
3515 // Make sure the root of the DAG is up-to-date.
3516 DAG.setRoot(SDL.getRoot());
3519 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
3520 // Run the DAG combiner in pre-legalize mode.
3523 DEBUG(std::cerr << "Lowered selection DAG:\n");
3526 // Second step, hack on the DAG until it only uses operations and types that
3527 // the target supports.
3530 DEBUG(std::cerr << "Legalized selection DAG:\n");
3533 // Run the DAG combiner in post-legalize mode.
3536 if (ViewISelDAGs) DAG.viewGraph();
3538 // Third, instruction select all of the operations to machine code, adding the
3539 // code to the MachineBasicBlock.
3540 InstructionSelectBasicBlock(DAG);
3542 DEBUG(std::cerr << "Selected machine code:\n");
3546 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
3547 FunctionLoweringInfo &FuncInfo) {
3548 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
3550 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3553 // First step, lower LLVM code to some DAG. This DAG may use operations and
3554 // types that are not supported by the target.
3555 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
3557 // Second step, emit the lowered DAG as machine code.
3558 CodeGenAndEmitDAG(DAG);
3561 // Next, now that we know what the last MBB the LLVM BB expanded is, update
3562 // PHI nodes in successors.
3563 if (SwitchCases.empty() && JT.Reg == 0) {
3564 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3565 MachineInstr *PHI = PHINodesToUpdate[i].first;
3566 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3567 "This is not a machine PHI node that we are updating!");
3568 PHI->addRegOperand(PHINodesToUpdate[i].second);
3569 PHI->addMachineBasicBlockOperand(BB);
3574 // If the JumpTable record is filled in, then we need to emit a jump table.
3575 // Updating the PHI nodes is tricky in this case, since we need to determine
3576 // whether the PHI is a successor of the range check MBB or the jump table MBB
3578 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
3579 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3581 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3582 MachineBasicBlock *RangeBB = BB;
3583 // Set the current basic block to the mbb we wish to insert the code into
3585 SDL.setCurrentBasicBlock(BB);
3587 SDL.visitJumpTable(JT);
3588 SDAG.setRoot(SDL.getRoot());
3589 CodeGenAndEmitDAG(SDAG);
3591 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3592 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3593 MachineBasicBlock *PHIBB = PHI->getParent();
3594 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3595 "This is not a machine PHI node that we are updating!");
3596 if (PHIBB == JT.Default) {
3597 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3598 PHI->addMachineBasicBlockOperand(RangeBB);
3600 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
3601 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3602 PHI->addMachineBasicBlockOperand(BB);
3608 // If we generated any switch lowering information, build and codegen any
3609 // additional DAGs necessary.
3610 for(unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
3611 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3613 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
3614 // Set the current basic block to the mbb we wish to insert the code into
3615 BB = SwitchCases[i].ThisBB;
3616 SDL.setCurrentBasicBlock(BB);
3618 SDL.visitSwitchCase(SwitchCases[i]);
3619 SDAG.setRoot(SDL.getRoot());
3620 CodeGenAndEmitDAG(SDAG);
3621 // Iterate over the phi nodes, if there is a phi node in a successor of this
3622 // block (for instance, the default block), then add a pair of operands to
3623 // the phi node for this block, as if we were coming from the original
3624 // BB before switch expansion.
3625 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3626 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3627 MachineBasicBlock *PHIBB = PHI->getParent();
3628 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3629 "This is not a machine PHI node that we are updating!");
3630 if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
3631 PHI->addRegOperand(PHINodesToUpdate[pi].second);
3632 PHI->addMachineBasicBlockOperand(BB);
3639 //===----------------------------------------------------------------------===//
3640 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
3641 /// target node in the graph.
3642 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
3643 if (ViewSchedDAGs) DAG.viewGraph();
3645 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
3649 RegisterScheduler::setDefault(Ctor);
3652 ScheduleDAG *SL = Ctor(this, &DAG, BB);
3658 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
3659 return new HazardRecognizer();
3663 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
3664 /// by tblgen. Others should not call it.
3665 void SelectionDAGISel::
3666 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
3667 std::vector<SDOperand> InOps;
3668 std::swap(InOps, Ops);
3670 Ops.push_back(InOps[0]); // input chain.
3671 Ops.push_back(InOps[1]); // input asm string.
3673 unsigned i = 2, e = InOps.size();
3674 if (InOps[e-1].getValueType() == MVT::Flag)
3675 --e; // Don't process a flag operand if it is here.
3678 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
3679 if ((Flags & 7) != 4 /*MEM*/) {
3680 // Just skip over this operand, copying the operands verbatim.
3681 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
3682 i += (Flags >> 3) + 1;
3684 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
3685 // Otherwise, this is a memory operand. Ask the target to select it.
3686 std::vector<SDOperand> SelOps;
3687 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
3688 std::cerr << "Could not match memory address. Inline asm failure!\n";
3692 // Add this to the output node.
3693 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
3694 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
3699 // Add the flag input back if present.
3700 if (e != InOps.size())
3701 Ops.push_back(InOps.back());