1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/GCStrategy.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/LibCallSemantics.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SelectionDAGISel.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/InlineAsm.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/IntrinsicInst.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/IR/LLVMContext.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/MC/MCAsmInfo.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetIntrinsicInfo.h"
55 #include "llvm/Target/TargetLowering.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "llvm/Target/TargetOptions.h"
58 #include "llvm/Target/TargetRegisterInfo.h"
59 #include "llvm/Target/TargetSubtargetInfo.h"
60 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
64 #define DEBUG_TYPE "isel"
66 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
67 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
68 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
69 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
70 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
71 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
72 STATISTIC(NumFastIselFailLowerArguments,
73 "Number of entry blocks where fast isel failed to lower arguments");
77 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
78 cl::desc("Enable extra verbose messages in the \"fast\" "
79 "instruction selector"));
82 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
83 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
84 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
85 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
86 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
87 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
88 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
90 // Standard binary operators...
91 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
92 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
93 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
94 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
95 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
96 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
97 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
98 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
99 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
100 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
101 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
102 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
104 // Logical operators...
105 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
106 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
107 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
109 // Memory instructions...
110 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
111 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
112 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
113 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
114 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
115 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
116 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
118 // Convert instructions...
119 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
120 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
121 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
122 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
123 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
124 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
125 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
126 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
127 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
128 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
129 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
130 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
132 // Other instructions...
133 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
134 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
135 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
136 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
137 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
138 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
139 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
140 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
141 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
142 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
143 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
144 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
145 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
146 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
147 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
149 // Intrinsic instructions...
150 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
151 STATISTIC(NumFastIselFailSAddWithOverflow,
152 "Fast isel fails on sadd.with.overflow");
153 STATISTIC(NumFastIselFailUAddWithOverflow,
154 "Fast isel fails on uadd.with.overflow");
155 STATISTIC(NumFastIselFailSSubWithOverflow,
156 "Fast isel fails on ssub.with.overflow");
157 STATISTIC(NumFastIselFailUSubWithOverflow,
158 "Fast isel fails on usub.with.overflow");
159 STATISTIC(NumFastIselFailSMulWithOverflow,
160 "Fast isel fails on smul.with.overflow");
161 STATISTIC(NumFastIselFailUMulWithOverflow,
162 "Fast isel fails on umul.with.overflow");
163 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
164 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
165 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
166 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
170 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
171 cl::desc("Enable verbose messages in the \"fast\" "
172 "instruction selector"));
173 static cl::opt<int> EnableFastISelAbort(
174 "fast-isel-abort", cl::Hidden,
175 cl::desc("Enable abort calls when \"fast\" instruction selection "
176 "fails to lower an instruction: 0 disable the abort, 1 will "
177 "abort but for args, calls and terminators, 2 will also "
178 "abort for argument lowering, and 3 will never fallback "
179 "to SelectionDAG."));
183 cl::desc("use Machine Branch Probability Info"),
184 cl::init(true), cl::Hidden);
187 static cl::opt<std::string>
188 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
189 cl::desc("Only display the basic block whose name "
190 "matches this for all view-*-dags options"));
192 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
193 cl::desc("Pop up a window to show dags before the first "
194 "dag combine pass"));
196 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
197 cl::desc("Pop up a window to show dags before legalize types"));
199 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
200 cl::desc("Pop up a window to show dags before legalize"));
202 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
203 cl::desc("Pop up a window to show dags before the second "
204 "dag combine pass"));
206 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
207 cl::desc("Pop up a window to show dags before the post legalize types"
208 " dag combine pass"));
210 ViewISelDAGs("view-isel-dags", cl::Hidden,
211 cl::desc("Pop up a window to show isel dags as they are selected"));
213 ViewSchedDAGs("view-sched-dags", cl::Hidden,
214 cl::desc("Pop up a window to show sched dags as they are processed"));
216 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
217 cl::desc("Pop up a window to show SUnit dags after they are processed"));
219 static const bool ViewDAGCombine1 = false,
220 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
221 ViewDAGCombine2 = false,
222 ViewDAGCombineLT = false,
223 ViewISelDAGs = false, ViewSchedDAGs = false,
224 ViewSUnitDAGs = false;
227 //===---------------------------------------------------------------------===//
229 /// RegisterScheduler class - Track the registration of instruction schedulers.
231 //===---------------------------------------------------------------------===//
232 MachinePassRegistry RegisterScheduler::Registry;
234 //===---------------------------------------------------------------------===//
236 /// ISHeuristic command line option for instruction schedulers.
238 //===---------------------------------------------------------------------===//
239 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
240 RegisterPassParser<RegisterScheduler> >
241 ISHeuristic("pre-RA-sched",
242 cl::init(&createDefaultScheduler), cl::Hidden,
243 cl::desc("Instruction schedulers available (before register"
246 static RegisterScheduler
247 defaultListDAGScheduler("default", "Best scheduler for the target",
248 createDefaultScheduler);
251 //===--------------------------------------------------------------------===//
252 /// \brief This class is used by SelectionDAGISel to temporarily override
253 /// the optimization level on a per-function basis.
254 class OptLevelChanger {
255 SelectionDAGISel &IS;
256 CodeGenOpt::Level SavedOptLevel;
260 OptLevelChanger(SelectionDAGISel &ISel,
261 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
262 SavedOptLevel = IS.OptLevel;
263 if (NewOptLevel == SavedOptLevel)
265 IS.OptLevel = NewOptLevel;
266 IS.TM.setOptLevel(NewOptLevel);
267 SavedFastISel = IS.TM.Options.EnableFastISel;
268 if (NewOptLevel == CodeGenOpt::None)
269 IS.TM.setFastISel(true);
270 DEBUG(dbgs() << "\nChanging optimization level for Function "
271 << IS.MF->getFunction()->getName() << "\n");
272 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
273 << " ; After: -O" << NewOptLevel << "\n");
277 if (IS.OptLevel == SavedOptLevel)
279 DEBUG(dbgs() << "\nRestoring optimization level for Function "
280 << IS.MF->getFunction()->getName() << "\n");
281 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
282 << " ; After: -O" << SavedOptLevel << "\n");
283 IS.OptLevel = SavedOptLevel;
284 IS.TM.setOptLevel(SavedOptLevel);
285 IS.TM.setFastISel(SavedFastISel);
289 //===--------------------------------------------------------------------===//
290 /// createDefaultScheduler - This creates an instruction scheduler appropriate
292 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
293 CodeGenOpt::Level OptLevel) {
294 const TargetLowering *TLI = IS->TLI;
295 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
297 // Try first to see if the Target has its own way of selecting a scheduler
298 if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
299 return SchedulerCtor(IS, OptLevel);
302 if (OptLevel == CodeGenOpt::None ||
303 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
304 TLI->getSchedulingPreference() == Sched::Source)
305 return createSourceListDAGScheduler(IS, OptLevel);
306 if (TLI->getSchedulingPreference() == Sched::RegPressure)
307 return createBURRListDAGScheduler(IS, OptLevel);
308 if (TLI->getSchedulingPreference() == Sched::Hybrid)
309 return createHybridListDAGScheduler(IS, OptLevel);
310 if (TLI->getSchedulingPreference() == Sched::VLIW)
311 return createVLIWDAGScheduler(IS, OptLevel);
312 assert(TLI->getSchedulingPreference() == Sched::ILP &&
313 "Unknown sched type!");
314 return createILPListDAGScheduler(IS, OptLevel);
318 // EmitInstrWithCustomInserter - This method should be implemented by targets
319 // that mark instructions with the 'usesCustomInserter' flag. These
320 // instructions are special in various ways, which require special support to
321 // insert. The specified MachineInstr is created but not inserted into any
322 // basic blocks, and this method is called to expand it into a sequence of
323 // instructions, potentially also creating new basic blocks and control flow.
324 // When new basic blocks are inserted and the edges from MBB to its successors
325 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
328 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
329 MachineBasicBlock *MBB) const {
331 dbgs() << "If a target marks an instruction with "
332 "'usesCustomInserter', it must implement "
333 "TargetLowering::EmitInstrWithCustomInserter!";
335 llvm_unreachable(nullptr);
338 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
339 SDNode *Node) const {
340 assert(!MI->hasPostISelHook() &&
341 "If a target marks an instruction with 'hasPostISelHook', "
342 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
345 //===----------------------------------------------------------------------===//
346 // SelectionDAGISel code
347 //===----------------------------------------------------------------------===//
349 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
350 CodeGenOpt::Level OL) :
351 MachineFunctionPass(ID), TM(tm),
352 FuncInfo(new FunctionLoweringInfo()),
353 CurDAG(new SelectionDAG(tm, OL)),
354 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
358 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
359 initializeBranchProbabilityInfoWrapperPassPass(
360 *PassRegistry::getPassRegistry());
361 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
362 initializeTargetLibraryInfoWrapperPassPass(
363 *PassRegistry::getPassRegistry());
366 SelectionDAGISel::~SelectionDAGISel() {
372 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
373 AU.addRequired<AAResultsWrapperPass>();
374 AU.addRequired<GCModuleInfo>();
375 AU.addPreserved<GCModuleInfo>();
376 AU.addRequired<TargetLibraryInfoWrapperPass>();
377 if (UseMBPI && OptLevel != CodeGenOpt::None)
378 AU.addRequired<BranchProbabilityInfoWrapperPass>();
379 MachineFunctionPass::getAnalysisUsage(AU);
382 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
383 /// may trap on it. In this case we have to split the edge so that the path
384 /// through the predecessor block that doesn't go to the phi block doesn't
385 /// execute the possibly trapping instruction.
387 /// This is required for correctness, so it must be done at -O0.
389 static void SplitCriticalSideEffectEdges(Function &Fn) {
390 // Loop for blocks with phi nodes.
391 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
392 PHINode *PN = dyn_cast<PHINode>(BB->begin());
396 // For each block with a PHI node, check to see if any of the input values
397 // are potentially trapping constant expressions. Constant expressions are
398 // the only potentially trapping value that can occur as the argument to a
400 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
401 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
402 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
403 if (!CE || !CE->canTrap()) continue;
405 // The only case we have to worry about is when the edge is critical.
406 // Since this block has a PHI Node, we assume it has multiple input
407 // edges: check to see if the pred has multiple successors.
408 BasicBlock *Pred = PN->getIncomingBlock(i);
409 if (Pred->getTerminator()->getNumSuccessors() == 1)
412 // Okay, we have to split this edge.
414 Pred->getTerminator(), GetSuccessorNumber(Pred, BB),
415 CriticalEdgeSplittingOptions().setMergeIdenticalEdges());
421 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
422 // Do some sanity-checking on the command-line options.
423 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
424 "-fast-isel-verbose requires -fast-isel");
425 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
426 "-fast-isel-abort > 0 requires -fast-isel");
428 const Function &Fn = *mf.getFunction();
431 // Reset the target options before resetting the optimization
433 // FIXME: This is a horrible hack and should be processed via
434 // codegen looking at the optimization level explicitly when
435 // it wants to look at it.
436 TM.resetTargetOptions(Fn);
437 // Reset OptLevel to None for optnone functions.
438 CodeGenOpt::Level NewOptLevel = OptLevel;
439 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
440 NewOptLevel = CodeGenOpt::None;
441 OptLevelChanger OLC(*this, NewOptLevel);
443 TII = MF->getSubtarget().getInstrInfo();
444 TLI = MF->getSubtarget().getTargetLowering();
445 RegInfo = &MF->getRegInfo();
446 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
447 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
448 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
450 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
452 SplitCriticalSideEffectEdges(const_cast<Function &>(Fn));
455 FuncInfo->set(Fn, *MF, CurDAG);
457 if (UseMBPI && OptLevel != CodeGenOpt::None)
458 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
460 FuncInfo->BPI = nullptr;
462 SDB->init(GFI, *AA, LibInfo);
464 MF->setHasInlineAsm(false);
466 SelectAllBasicBlocks(Fn);
468 // If the first basic block in the function has live ins that need to be
469 // copied into vregs, emit the copies into the top of the block before
470 // emitting the code for the block.
471 MachineBasicBlock *EntryMBB = MF->begin();
472 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
473 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
475 DenseMap<unsigned, unsigned> LiveInMap;
476 if (!FuncInfo->ArgDbgValues.empty())
477 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
478 E = RegInfo->livein_end(); LI != E; ++LI)
480 LiveInMap.insert(std::make_pair(LI->first, LI->second));
482 // Insert DBG_VALUE instructions for function arguments to the entry block.
483 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
484 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
485 bool hasFI = MI->getOperand(0).isFI();
487 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
488 if (TargetRegisterInfo::isPhysicalRegister(Reg))
489 EntryMBB->insert(EntryMBB->begin(), MI);
491 MachineInstr *Def = RegInfo->getVRegDef(Reg);
493 MachineBasicBlock::iterator InsertPos = Def;
494 // FIXME: VR def may not be in entry block.
495 Def->getParent()->insert(std::next(InsertPos), MI);
497 DEBUG(dbgs() << "Dropping debug info for dead vreg"
498 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
501 // If Reg is live-in then update debug info to track its copy in a vreg.
502 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
503 if (LDI != LiveInMap.end()) {
504 assert(!hasFI && "There's no handling of frame pointer updating here yet "
506 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
507 MachineBasicBlock::iterator InsertPos = Def;
508 const MDNode *Variable = MI->getDebugVariable();
509 const MDNode *Expr = MI->getDebugExpression();
510 DebugLoc DL = MI->getDebugLoc();
511 bool IsIndirect = MI->isIndirectDebugValue();
512 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
513 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
514 "Expected inlined-at fields to agree");
515 // Def is never a terminator here, so it is ok to increment InsertPos.
516 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
517 IsIndirect, LDI->second, Offset, Variable, Expr);
519 // If this vreg is directly copied into an exported register then
520 // that COPY instructions also need DBG_VALUE, if it is the only
521 // user of LDI->second.
522 MachineInstr *CopyUseMI = nullptr;
523 for (MachineRegisterInfo::use_instr_iterator
524 UI = RegInfo->use_instr_begin(LDI->second),
525 E = RegInfo->use_instr_end(); UI != E; ) {
526 MachineInstr *UseMI = &*(UI++);
527 if (UseMI->isDebugValue()) continue;
528 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
529 CopyUseMI = UseMI; continue;
531 // Otherwise this is another use or second copy use.
532 CopyUseMI = nullptr; break;
535 // Use MI's debug location, which describes where Variable was
536 // declared, rather than whatever is attached to CopyUseMI.
537 MachineInstr *NewMI =
538 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
539 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
540 MachineBasicBlock::iterator Pos = CopyUseMI;
541 EntryMBB->insertAfter(Pos, NewMI);
546 // Determine if there are any calls in this machine function.
547 MachineFrameInfo *MFI = MF->getFrameInfo();
548 for (const auto &MBB : *MF) {
549 if (MFI->hasCalls() && MF->hasInlineAsm())
552 for (const auto &MI : MBB) {
553 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
554 if ((MCID.isCall() && !MCID.isReturn()) ||
555 MI.isStackAligningInlineAsm()) {
556 MFI->setHasCalls(true);
558 if (MI.isInlineAsm()) {
559 MF->setHasInlineAsm(true);
564 // Determine if there is a call to setjmp in the machine function.
565 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
567 // Replace forward-declared registers with the registers containing
568 // the desired value.
569 MachineRegisterInfo &MRI = MF->getRegInfo();
570 for (DenseMap<unsigned, unsigned>::iterator
571 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
573 unsigned From = I->first;
574 unsigned To = I->second;
575 // If To is also scheduled to be replaced, find what its ultimate
578 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
582 // Make sure the new register has a sufficiently constrained register class.
583 if (TargetRegisterInfo::isVirtualRegister(From) &&
584 TargetRegisterInfo::isVirtualRegister(To))
585 MRI.constrainRegClass(To, MRI.getRegClass(From));
589 // Replacing one register with another won't touch the kill flags.
590 // We need to conservatively clear the kill flags as a kill on the old
591 // register might dominate existing uses of the new register.
592 if (!MRI.use_empty(To))
593 MRI.clearKillFlags(From);
594 MRI.replaceRegWith(From, To);
597 // Freeze the set of reserved registers now that MachineFrameInfo has been
598 // set up. All the information required by getReservedRegs() should be
600 MRI.freezeReservedRegs(*MF);
602 // Release function-specific state. SDB and CurDAG are already cleared
606 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
607 DEBUG(MF->print(dbgs()));
612 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
613 BasicBlock::const_iterator End,
615 // Lower the instructions. If a call is emitted as a tail call, cease emitting
616 // nodes for this block.
617 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
620 // Make sure the root of the DAG is up-to-date.
621 CurDAG->setRoot(SDB->getControlRoot());
622 HadTailCall = SDB->HasTailCall;
625 // Final step, emit the lowered DAG as machine code.
629 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
630 SmallPtrSet<SDNode*, 128> VisitedNodes;
631 SmallVector<SDNode*, 128> Worklist;
633 Worklist.push_back(CurDAG->getRoot().getNode());
639 SDNode *N = Worklist.pop_back_val();
641 // If we've already seen this node, ignore it.
642 if (!VisitedNodes.insert(N).second)
645 // Otherwise, add all chain operands to the worklist.
646 for (const SDValue &Op : N->op_values())
647 if (Op.getValueType() == MVT::Other)
648 Worklist.push_back(Op.getNode());
650 // If this is a CopyToReg with a vreg dest, process it.
651 if (N->getOpcode() != ISD::CopyToReg)
654 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
655 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
658 // Ignore non-scalar or non-integer values.
659 SDValue Src = N->getOperand(2);
660 EVT SrcVT = Src.getValueType();
661 if (!SrcVT.isInteger() || SrcVT.isVector())
664 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
665 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
666 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
667 } while (!Worklist.empty());
670 void SelectionDAGISel::CodeGenAndEmitDAG() {
671 std::string GroupName;
672 if (TimePassesIsEnabled)
673 GroupName = "Instruction Selection and Scheduling";
674 std::string BlockName;
675 int BlockNumber = -1;
677 bool MatchFilterBB = false; (void)MatchFilterBB;
679 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
680 FilterDAGBasicBlockName ==
681 FuncInfo->MBB->getBasicBlock()->getName().str());
684 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
685 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
689 BlockNumber = FuncInfo->MBB->getNumber();
691 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
693 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
694 << " '" << BlockName << "'\n"; CurDAG->dump());
696 if (ViewDAGCombine1 && MatchFilterBB)
697 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
699 // Run the DAG combiner in pre-legalize mode.
701 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
702 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
705 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
706 << " '" << BlockName << "'\n"; CurDAG->dump());
708 // Second step, hack on the DAG until it only uses operations and types that
709 // the target supports.
710 if (ViewLegalizeTypesDAGs && MatchFilterBB)
711 CurDAG->viewGraph("legalize-types input for " + BlockName);
715 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
716 Changed = CurDAG->LegalizeTypes();
719 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
720 << " '" << BlockName << "'\n"; CurDAG->dump());
722 CurDAG->NewNodesMustHaveLegalTypes = true;
725 if (ViewDAGCombineLT && MatchFilterBB)
726 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
728 // Run the DAG combiner in post-type-legalize mode.
730 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
731 TimePassesIsEnabled);
732 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
735 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
736 << " '" << BlockName << "'\n"; CurDAG->dump());
741 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
742 Changed = CurDAG->LegalizeVectors();
747 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
748 CurDAG->LegalizeTypes();
751 if (ViewDAGCombineLT && MatchFilterBB)
752 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
754 // Run the DAG combiner in post-type-legalize mode.
756 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
757 TimePassesIsEnabled);
758 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
761 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
762 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
765 if (ViewLegalizeDAGs && MatchFilterBB)
766 CurDAG->viewGraph("legalize input for " + BlockName);
769 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
773 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
774 << " '" << BlockName << "'\n"; CurDAG->dump());
776 if (ViewDAGCombine2 && MatchFilterBB)
777 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
779 // Run the DAG combiner in post-legalize mode.
781 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
782 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
785 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
786 << " '" << BlockName << "'\n"; CurDAG->dump());
788 if (OptLevel != CodeGenOpt::None)
789 ComputeLiveOutVRegInfo();
791 if (ViewISelDAGs && MatchFilterBB)
792 CurDAG->viewGraph("isel input for " + BlockName);
794 // Third, instruction select all of the operations to machine code, adding the
795 // code to the MachineBasicBlock.
797 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
798 DoInstructionSelection();
801 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
802 << " '" << BlockName << "'\n"; CurDAG->dump());
804 if (ViewSchedDAGs && MatchFilterBB)
805 CurDAG->viewGraph("scheduler input for " + BlockName);
807 // Schedule machine code.
808 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
810 NamedRegionTimer T("Instruction Scheduling", GroupName,
811 TimePassesIsEnabled);
812 Scheduler->Run(CurDAG, FuncInfo->MBB);
815 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
817 // Emit machine code to BB. This can change 'BB' to the last block being
819 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
821 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
823 // FuncInfo->InsertPt is passed by reference and set to the end of the
824 // scheduled instructions.
825 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
828 // If the block was split, make sure we update any references that are used to
829 // update PHI nodes later on.
830 if (FirstMBB != LastMBB)
831 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
833 // Free the scheduler state.
835 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
836 TimePassesIsEnabled);
840 // Free the SelectionDAG state, now that we're finished with it.
845 /// ISelUpdater - helper class to handle updates of the instruction selection
847 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
848 SelectionDAG::allnodes_iterator &ISelPosition;
850 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
851 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
853 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
854 /// deleted is the current ISelPosition node, update ISelPosition.
856 void NodeDeleted(SDNode *N, SDNode *E) override {
857 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
861 } // end anonymous namespace
863 void SelectionDAGISel::DoInstructionSelection() {
864 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
865 << FuncInfo->MBB->getNumber()
866 << " '" << FuncInfo->MBB->getName() << "'\n");
870 // Select target instructions for the DAG.
872 // Number all nodes with a topological order and set DAGSize.
873 DAGSize = CurDAG->AssignTopologicalOrder();
875 // Create a dummy node (which is not added to allnodes), that adds
876 // a reference to the root node, preventing it from being deleted,
877 // and tracking any changes of the root.
878 HandleSDNode Dummy(CurDAG->getRoot());
879 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
882 // Make sure that ISelPosition gets properly updated when nodes are deleted
883 // in calls made from this function.
884 ISelUpdater ISU(*CurDAG, ISelPosition);
886 // The AllNodes list is now topological-sorted. Visit the
887 // nodes by starting at the end of the list (the root of the
888 // graph) and preceding back toward the beginning (the entry
890 while (ISelPosition != CurDAG->allnodes_begin()) {
891 SDNode *Node = --ISelPosition;
892 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
893 // but there are currently some corner cases that it misses. Also, this
894 // makes it theoretically possible to disable the DAGCombiner.
895 if (Node->use_empty())
898 SDNode *ResNode = Select(Node);
900 // FIXME: This is pretty gross. 'Select' should be changed to not return
901 // anything at all and this code should be nuked with a tactical strike.
903 // If node should not be replaced, continue with the next one.
904 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
908 ReplaceUses(Node, ResNode);
911 // If after the replacement this node is not used any more,
912 // remove this dead node.
913 if (Node->use_empty()) // Don't delete EntryToken, etc.
914 CurDAG->RemoveDeadNode(Node);
917 CurDAG->setRoot(Dummy.getValue());
920 DEBUG(dbgs() << "===== Instruction selection ends:\n");
922 PostprocessISelDAG();
925 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
926 /// do other setup for EH landing-pad blocks.
927 bool SelectionDAGISel::PrepareEHLandingPad() {
928 MachineBasicBlock *MBB = FuncInfo->MBB;
930 const TargetRegisterClass *PtrRC =
931 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout()));
933 // Add a label to mark the beginning of the landing pad. Deletion of the
934 // landing pad can thus be detected via the MachineModuleInfo.
935 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
937 // Assign the call site to the landing pad's begin label.
938 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
940 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
941 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
944 // If this is an MSVC-style personality function, we need to split the landing
945 // pad into several BBs.
946 const BasicBlock *LLVMBB = MBB->getBasicBlock();
947 const Constant *Personality = MF->getFunction()->getPersonalityFn();
948 if (const auto *PF = dyn_cast<Function>(Personality->stripPointerCasts()))
949 MF->getMMI().addPersonality(PF);
950 EHPersonality PersonalityType = classifyEHPersonality(Personality);
952 if (isMSVCEHPersonality(PersonalityType)) {
953 SmallVector<MachineBasicBlock *, 4> ClauseBBs;
954 const IntrinsicInst *ActionsCall =
955 dyn_cast<IntrinsicInst>(LLVMBB->getFirstInsertionPt());
956 // Get all invoke BBs that unwind to this landingpad.
957 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
959 if (ActionsCall && ActionsCall->getIntrinsicID() == Intrinsic::eh_actions) {
960 // If this is a call to llvm.eh.actions followed by indirectbr, then we've
961 // run WinEHPrepare, and we should remove this block from the machine CFG.
962 // Mark the targets of the indirectbr as landingpads instead.
963 for (const BasicBlock *LLVMSucc : successors(LLVMBB)) {
964 MachineBasicBlock *ClauseBB = FuncInfo->MBBMap[LLVMSucc];
965 // Add the edge from the invoke to the clause.
966 for (MachineBasicBlock *InvokeBB : InvokeBBs)
967 InvokeBB->addSuccessor(ClauseBB);
969 // Mark the clause as a landing pad or MI passes will delete it.
970 ClauseBB->setIsEHPad();
974 // Remove the edge from the invoke to the lpad.
975 for (MachineBasicBlock *InvokeBB : InvokeBBs)
976 InvokeBB->removeSuccessor(MBB);
978 // Don't select instructions for the landingpad.
982 // Mark exception register as live in.
983 if (unsigned Reg = TLI->getExceptionPointerRegister())
984 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
986 // Mark exception selector register as live in.
987 if (unsigned Reg = TLI->getExceptionSelectorRegister())
988 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
993 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
994 /// side-effect free and is either dead or folded into a generated instruction.
995 /// Return false if it needs to be emitted.
996 static bool isFoldedOrDeadInstruction(const Instruction *I,
997 FunctionLoweringInfo *FuncInfo) {
998 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
999 !isa<TerminatorInst>(I) && // Terminators aren't folded.
1000 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
1001 !I->isEHPad() && // EH pad instructions aren't folded.
1002 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1006 // Collect per Instruction statistics for fast-isel misses. Only those
1007 // instructions that cause the bail are accounted for. It does not account for
1008 // instructions higher in the block. Thus, summing the per instructions stats
1009 // will not add up to what is reported by NumFastIselFailures.
1010 static void collectFailStats(const Instruction *I) {
1011 switch (I->getOpcode()) {
1012 default: assert (0 && "<Invalid operator> ");
1015 case Instruction::Ret: NumFastIselFailRet++; return;
1016 case Instruction::Br: NumFastIselFailBr++; return;
1017 case Instruction::Switch: NumFastIselFailSwitch++; return;
1018 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1019 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1020 case Instruction::Resume: NumFastIselFailResume++; return;
1021 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1023 // Standard binary operators...
1024 case Instruction::Add: NumFastIselFailAdd++; return;
1025 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1026 case Instruction::Sub: NumFastIselFailSub++; return;
1027 case Instruction::FSub: NumFastIselFailFSub++; return;
1028 case Instruction::Mul: NumFastIselFailMul++; return;
1029 case Instruction::FMul: NumFastIselFailFMul++; return;
1030 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1031 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1032 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1033 case Instruction::URem: NumFastIselFailURem++; return;
1034 case Instruction::SRem: NumFastIselFailSRem++; return;
1035 case Instruction::FRem: NumFastIselFailFRem++; return;
1037 // Logical operators...
1038 case Instruction::And: NumFastIselFailAnd++; return;
1039 case Instruction::Or: NumFastIselFailOr++; return;
1040 case Instruction::Xor: NumFastIselFailXor++; return;
1042 // Memory instructions...
1043 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1044 case Instruction::Load: NumFastIselFailLoad++; return;
1045 case Instruction::Store: NumFastIselFailStore++; return;
1046 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1047 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1048 case Instruction::Fence: NumFastIselFailFence++; return;
1049 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1051 // Convert instructions...
1052 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1053 case Instruction::ZExt: NumFastIselFailZExt++; return;
1054 case Instruction::SExt: NumFastIselFailSExt++; return;
1055 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1056 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1057 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1058 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1059 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1060 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1061 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1062 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1063 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1065 // Other instructions...
1066 case Instruction::ICmp: NumFastIselFailICmp++; return;
1067 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1068 case Instruction::PHI: NumFastIselFailPHI++; return;
1069 case Instruction::Select: NumFastIselFailSelect++; return;
1070 case Instruction::Call: {
1071 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1072 switch (Intrinsic->getIntrinsicID()) {
1074 NumFastIselFailIntrinsicCall++; return;
1075 case Intrinsic::sadd_with_overflow:
1076 NumFastIselFailSAddWithOverflow++; return;
1077 case Intrinsic::uadd_with_overflow:
1078 NumFastIselFailUAddWithOverflow++; return;
1079 case Intrinsic::ssub_with_overflow:
1080 NumFastIselFailSSubWithOverflow++; return;
1081 case Intrinsic::usub_with_overflow:
1082 NumFastIselFailUSubWithOverflow++; return;
1083 case Intrinsic::smul_with_overflow:
1084 NumFastIselFailSMulWithOverflow++; return;
1085 case Intrinsic::umul_with_overflow:
1086 NumFastIselFailUMulWithOverflow++; return;
1087 case Intrinsic::frameaddress:
1088 NumFastIselFailFrameaddress++; return;
1089 case Intrinsic::sqrt:
1090 NumFastIselFailSqrt++; return;
1091 case Intrinsic::experimental_stackmap:
1092 NumFastIselFailStackMap++; return;
1093 case Intrinsic::experimental_patchpoint_void: // fall-through
1094 case Intrinsic::experimental_patchpoint_i64:
1095 NumFastIselFailPatchPoint++; return;
1098 NumFastIselFailCall++;
1101 case Instruction::Shl: NumFastIselFailShl++; return;
1102 case Instruction::LShr: NumFastIselFailLShr++; return;
1103 case Instruction::AShr: NumFastIselFailAShr++; return;
1104 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1105 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1106 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1107 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1108 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1109 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1110 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1115 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1116 // Initialize the Fast-ISel state, if needed.
1117 FastISel *FastIS = nullptr;
1118 if (TM.Options.EnableFastISel)
1119 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1121 // Iterate over all basic blocks in the function.
1122 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1123 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1124 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1125 const BasicBlock *LLVMBB = *I;
1127 if (OptLevel != CodeGenOpt::None) {
1128 bool AllPredsVisited = true;
1129 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1131 if (!FuncInfo->VisitedBBs.count(*PI)) {
1132 AllPredsVisited = false;
1137 if (AllPredsVisited) {
1138 for (BasicBlock::const_iterator I = LLVMBB->begin();
1139 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1140 FuncInfo->ComputePHILiveOutRegInfo(PN);
1142 for (BasicBlock::const_iterator I = LLVMBB->begin();
1143 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1144 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1147 FuncInfo->VisitedBBs.insert(LLVMBB);
1150 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1151 BasicBlock::const_iterator const End = LLVMBB->end();
1152 BasicBlock::const_iterator BI = End;
1154 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1156 continue; // Some blocks like catchpads have no code or MBB.
1157 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1159 // Setup an EH landing-pad block.
1160 FuncInfo->ExceptionPointerVirtReg = 0;
1161 FuncInfo->ExceptionSelectorVirtReg = 0;
1162 if (LLVMBB->isLandingPad())
1163 if (!PrepareEHLandingPad())
1167 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1169 FastIS->startNewBlock();
1171 // Emit code for any incoming arguments. This must happen before
1172 // beginning FastISel on the entry block.
1173 if (LLVMBB == &Fn.getEntryBlock()) {
1176 // Lower any arguments needed in this block if this is the entry block.
1177 if (!FastIS->lowerArguments()) {
1178 // Fast isel failed to lower these arguments
1179 ++NumFastIselFailLowerArguments;
1180 if (EnableFastISelAbort > 1)
1181 report_fatal_error("FastISel didn't lower all arguments");
1183 // Use SelectionDAG argument lowering
1185 CurDAG->setRoot(SDB->getControlRoot());
1187 CodeGenAndEmitDAG();
1190 // If we inserted any instructions at the beginning, make a note of
1191 // where they are, so we can be sure to emit subsequent instructions
1193 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1194 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1196 FastIS->setLastLocalValue(nullptr);
1199 unsigned NumFastIselRemaining = std::distance(Begin, End);
1200 // Do FastISel on as many instructions as possible.
1201 for (; BI != Begin; --BI) {
1202 const Instruction *Inst = std::prev(BI);
1204 // If we no longer require this instruction, skip it.
1205 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1206 --NumFastIselRemaining;
1210 // Bottom-up: reset the insert pos at the top, after any local-value
1212 FastIS->recomputeInsertPt();
1214 // Try to select the instruction with FastISel.
1215 if (FastIS->selectInstruction(Inst)) {
1216 --NumFastIselRemaining;
1217 ++NumFastIselSuccess;
1218 // If fast isel succeeded, skip over all the folded instructions, and
1219 // then see if there is a load right before the selected instructions.
1220 // Try to fold the load if so.
1221 const Instruction *BeforeInst = Inst;
1222 while (BeforeInst != Begin) {
1223 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1224 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1227 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1228 BeforeInst->hasOneUse() &&
1229 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1230 // If we succeeded, don't re-select the load.
1231 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1232 --NumFastIselRemaining;
1233 ++NumFastIselSuccess;
1239 if (EnableFastISelVerbose2)
1240 collectFailStats(Inst);
1243 // Then handle certain instructions as single-LLVM-Instruction blocks.
1244 if (isa<CallInst>(Inst)) {
1246 if (EnableFastISelVerbose || EnableFastISelAbort) {
1247 dbgs() << "FastISel missed call: ";
1250 if (EnableFastISelAbort > 2)
1251 // FastISel selector couldn't handle something and bailed.
1252 // For the purpose of debugging, just abort.
1253 report_fatal_error("FastISel didn't select the entire block");
1255 if (!Inst->getType()->isVoidTy() && !Inst->getType()->isTokenTy() &&
1256 !Inst->use_empty()) {
1257 unsigned &R = FuncInfo->ValueMap[Inst];
1259 R = FuncInfo->CreateRegs(Inst->getType());
1262 bool HadTailCall = false;
1263 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1264 SelectBasicBlock(Inst, BI, HadTailCall);
1266 // If the call was emitted as a tail call, we're done with the block.
1267 // We also need to delete any previously emitted instructions.
1269 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1274 // Recompute NumFastIselRemaining as Selection DAG instruction
1275 // selection may have handled the call, input args, etc.
1276 unsigned RemainingNow = std::distance(Begin, BI);
1277 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1278 NumFastIselRemaining = RemainingNow;
1282 bool ShouldAbort = EnableFastISelAbort;
1283 if (EnableFastISelVerbose || EnableFastISelAbort) {
1284 if (isa<TerminatorInst>(Inst)) {
1285 // Use a different message for terminator misses.
1286 dbgs() << "FastISel missed terminator: ";
1287 // Don't abort unless for terminator unless the level is really high
1288 ShouldAbort = (EnableFastISelAbort > 2);
1290 dbgs() << "FastISel miss: ";
1295 // FastISel selector couldn't handle something and bailed.
1296 // For the purpose of debugging, just abort.
1297 report_fatal_error("FastISel didn't select the entire block");
1299 NumFastIselFailures += NumFastIselRemaining;
1303 FastIS->recomputeInsertPt();
1305 // Lower any arguments needed in this block if this is the entry block.
1306 if (LLVMBB == &Fn.getEntryBlock()) {
1315 ++NumFastIselBlocks;
1318 // Run SelectionDAG instruction selection on the remainder of the block
1319 // not handled by FastISel. If FastISel is not run, this is the entire
1322 SelectBasicBlock(Begin, BI, HadTailCall);
1326 FuncInfo->PHINodesToUpdate.clear();
1330 SDB->clearDanglingDebugInfo();
1331 SDB->SPDescriptor.resetPerFunctionState();
1334 /// Given that the input MI is before a partial terminator sequence TSeq, return
1335 /// true if M + TSeq also a partial terminator sequence.
1337 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1338 /// lowering copy vregs into physical registers, which are then passed into
1339 /// terminator instructors so we can satisfy ABI constraints. A partial
1340 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1341 /// may be the whole terminator sequence).
1342 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1343 // If we do not have a copy or an implicit def, we return true if and only if
1344 // MI is a debug value.
1345 if (!MI->isCopy() && !MI->isImplicitDef())
1346 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1347 // physical registers if there is debug info associated with the terminator
1348 // of our mbb. We want to include said debug info in our terminator
1349 // sequence, so we return true in that case.
1350 return MI->isDebugValue();
1352 // We have left the terminator sequence if we are not doing one of the
1355 // 1. Copying a vreg into a physical register.
1356 // 2. Copying a vreg into a vreg.
1357 // 3. Defining a register via an implicit def.
1359 // OPI should always be a register definition...
1360 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1361 if (!OPI->isReg() || !OPI->isDef())
1364 // Defining any register via an implicit def is always ok.
1365 if (MI->isImplicitDef())
1368 // Grab the copy source...
1369 MachineInstr::const_mop_iterator OPI2 = OPI;
1371 assert(OPI2 != MI->operands_end()
1372 && "Should have a copy implying we should have 2 arguments.");
1374 // Make sure that the copy dest is not a vreg when the copy source is a
1375 // physical register.
1376 if (!OPI2->isReg() ||
1377 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1378 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1384 /// Find the split point at which to splice the end of BB into its success stack
1385 /// protector check machine basic block.
1387 /// On many platforms, due to ABI constraints, terminators, even before register
1388 /// allocation, use physical registers. This creates an issue for us since
1389 /// physical registers at this point can not travel across basic
1390 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1391 /// when they enter functions and moves them through a sequence of copies back
1392 /// into the physical registers right before the terminator creating a
1393 /// ``Terminator Sequence''. This function is searching for the beginning of the
1394 /// terminator sequence so that we can ensure that we splice off not just the
1395 /// terminator, but additionally the copies that move the vregs into the
1396 /// physical registers.
1397 static MachineBasicBlock::iterator
1398 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1399 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1401 if (SplitPoint == BB->begin())
1404 MachineBasicBlock::iterator Start = BB->begin();
1405 MachineBasicBlock::iterator Previous = SplitPoint;
1408 while (MIIsInTerminatorSequence(Previous)) {
1409 SplitPoint = Previous;
1410 if (Previous == Start)
1419 SelectionDAGISel::FinishBasicBlock() {
1421 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1422 << FuncInfo->PHINodesToUpdate.size() << "\n";
1423 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1424 dbgs() << "Node " << i << " : ("
1425 << FuncInfo->PHINodesToUpdate[i].first
1426 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1428 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1429 // PHI nodes in successors.
1430 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1431 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1432 assert(PHI->isPHI() &&
1433 "This is not a machine PHI node that we are updating!");
1434 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1436 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1439 // Handle stack protector.
1440 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1441 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1442 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1444 // Find the split point to split the parent mbb. At the same time copy all
1445 // physical registers used in the tail of parent mbb into virtual registers
1446 // before the split point and back into physical registers after the split
1447 // point. This prevents us needing to deal with Live-ins and many other
1448 // register allocation issues caused by us splitting the parent mbb. The
1449 // register allocator will clean up said virtual copies later on.
1450 MachineBasicBlock::iterator SplitPoint =
1451 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1453 // Splice the terminator of ParentMBB into SuccessMBB.
1454 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1458 // Add compare/jump on neq/jump to the parent BB.
1459 FuncInfo->MBB = ParentMBB;
1460 FuncInfo->InsertPt = ParentMBB->end();
1461 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1462 CurDAG->setRoot(SDB->getRoot());
1464 CodeGenAndEmitDAG();
1466 // CodeGen Failure MBB if we have not codegened it yet.
1467 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1468 if (!FailureMBB->size()) {
1469 FuncInfo->MBB = FailureMBB;
1470 FuncInfo->InsertPt = FailureMBB->end();
1471 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1472 CurDAG->setRoot(SDB->getRoot());
1474 CodeGenAndEmitDAG();
1477 // Clear the Per-BB State.
1478 SDB->SPDescriptor.resetPerBBState();
1481 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1482 // Lower header first, if it wasn't already lowered
1483 if (!SDB->BitTestCases[i].Emitted) {
1484 // Set the current basic block to the mbb we wish to insert the code into
1485 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1486 FuncInfo->InsertPt = FuncInfo->MBB->end();
1488 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1489 CurDAG->setRoot(SDB->getRoot());
1491 CodeGenAndEmitDAG();
1494 uint32_t UnhandledWeight = SDB->BitTestCases[i].Weight;
1496 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1497 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1498 // Set the current basic block to the mbb we wish to insert the code into
1499 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1500 FuncInfo->InsertPt = FuncInfo->MBB->end();
1503 // If all cases cover a contiguous range, it is not necessary to jump to
1504 // the default block after the last bit test fails. This is because the
1505 // range check during bit test header creation has guaranteed that every
1506 // case here doesn't go outside the range.
1507 MachineBasicBlock *NextMBB;
1508 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej)
1509 NextMBB = SDB->BitTestCases[i].Cases[j + 1].TargetBB;
1510 else if (j + 1 != ej)
1511 NextMBB = SDB->BitTestCases[i].Cases[j + 1].ThisBB;
1513 NextMBB = SDB->BitTestCases[i].Default;
1515 SDB->visitBitTestCase(SDB->BitTestCases[i],
1518 SDB->BitTestCases[i].Reg,
1519 SDB->BitTestCases[i].Cases[j],
1522 CurDAG->setRoot(SDB->getRoot());
1524 CodeGenAndEmitDAG();
1526 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej)
1531 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1533 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1534 MachineBasicBlock *PHIBB = PHI->getParent();
1535 assert(PHI->isPHI() &&
1536 "This is not a machine PHI node that we are updating!");
1537 // This is "default" BB. We have two jumps to it. From "header" BB and
1538 // from last "case" BB.
1539 if (PHIBB == SDB->BitTestCases[i].Default)
1540 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1541 .addMBB(SDB->BitTestCases[i].Parent)
1542 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1543 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1544 // One of "cases" BB.
1545 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1547 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1548 if (cBB->isSuccessor(PHIBB))
1549 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1553 SDB->BitTestCases.clear();
1555 // If the JumpTable record is filled in, then we need to emit a jump table.
1556 // Updating the PHI nodes is tricky in this case, since we need to determine
1557 // whether the PHI is a successor of the range check MBB or the jump table MBB
1558 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1559 // Lower header first, if it wasn't already lowered
1560 if (!SDB->JTCases[i].first.Emitted) {
1561 // Set the current basic block to the mbb we wish to insert the code into
1562 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1563 FuncInfo->InsertPt = FuncInfo->MBB->end();
1565 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1567 CurDAG->setRoot(SDB->getRoot());
1569 CodeGenAndEmitDAG();
1572 // Set the current basic block to the mbb we wish to insert the code into
1573 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1574 FuncInfo->InsertPt = FuncInfo->MBB->end();
1576 SDB->visitJumpTable(SDB->JTCases[i].second);
1577 CurDAG->setRoot(SDB->getRoot());
1579 CodeGenAndEmitDAG();
1582 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1584 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1585 MachineBasicBlock *PHIBB = PHI->getParent();
1586 assert(PHI->isPHI() &&
1587 "This is not a machine PHI node that we are updating!");
1588 // "default" BB. We can go there only from header BB.
1589 if (PHIBB == SDB->JTCases[i].second.Default)
1590 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1591 .addMBB(SDB->JTCases[i].first.HeaderBB);
1592 // JT BB. Just iterate over successors here
1593 if (FuncInfo->MBB->isSuccessor(PHIBB))
1594 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1597 SDB->JTCases.clear();
1599 // If we generated any switch lowering information, build and codegen any
1600 // additional DAGs necessary.
1601 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1602 // Set the current basic block to the mbb we wish to insert the code into
1603 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1604 FuncInfo->InsertPt = FuncInfo->MBB->end();
1606 // Determine the unique successors.
1607 SmallVector<MachineBasicBlock *, 2> Succs;
1608 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1609 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1610 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1612 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1613 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1614 CurDAG->setRoot(SDB->getRoot());
1616 CodeGenAndEmitDAG();
1618 // Remember the last block, now that any splitting is done, for use in
1619 // populating PHI nodes in successors.
1620 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1622 // Handle any PHI nodes in successors of this chunk, as if we were coming
1623 // from the original BB before switch expansion. Note that PHI nodes can
1624 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1625 // handle them the right number of times.
1626 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1627 FuncInfo->MBB = Succs[i];
1628 FuncInfo->InsertPt = FuncInfo->MBB->end();
1629 // FuncInfo->MBB may have been removed from the CFG if a branch was
1631 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1632 for (MachineBasicBlock::iterator
1633 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1634 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1635 MachineInstrBuilder PHI(*MF, MBBI);
1636 // This value for this PHI node is recorded in PHINodesToUpdate.
1637 for (unsigned pn = 0; ; ++pn) {
1638 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1639 "Didn't find PHI entry!");
1640 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1641 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1649 SDB->SwitchCases.clear();
1653 /// Create the scheduler. If a specific scheduler was specified
1654 /// via the SchedulerRegistry, use it, otherwise select the
1655 /// one preferred by the target.
1657 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1658 return ISHeuristic(this, OptLevel);
1661 //===----------------------------------------------------------------------===//
1662 // Helper functions used by the generated instruction selector.
1663 //===----------------------------------------------------------------------===//
1664 // Calls to these methods are generated by tblgen.
1666 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1667 /// the dag combiner simplified the 255, we still want to match. RHS is the
1668 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1669 /// specified in the .td file (e.g. 255).
1670 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1671 int64_t DesiredMaskS) const {
1672 const APInt &ActualMask = RHS->getAPIntValue();
1673 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1675 // If the actual mask exactly matches, success!
1676 if (ActualMask == DesiredMask)
1679 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1680 if (ActualMask.intersects(~DesiredMask))
1683 // Otherwise, the DAG Combiner may have proven that the value coming in is
1684 // either already zero or is not demanded. Check for known zero input bits.
1685 APInt NeededMask = DesiredMask & ~ActualMask;
1686 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1689 // TODO: check to see if missing bits are just not demanded.
1691 // Otherwise, this pattern doesn't match.
1695 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1696 /// the dag combiner simplified the 255, we still want to match. RHS is the
1697 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1698 /// specified in the .td file (e.g. 255).
1699 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1700 int64_t DesiredMaskS) const {
1701 const APInt &ActualMask = RHS->getAPIntValue();
1702 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1704 // If the actual mask exactly matches, success!
1705 if (ActualMask == DesiredMask)
1708 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1709 if (ActualMask.intersects(~DesiredMask))
1712 // Otherwise, the DAG Combiner may have proven that the value coming in is
1713 // either already zero or is not demanded. Check for known zero input bits.
1714 APInt NeededMask = DesiredMask & ~ActualMask;
1716 APInt KnownZero, KnownOne;
1717 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1719 // If all the missing bits in the or are already known to be set, match!
1720 if ((NeededMask & KnownOne) == NeededMask)
1723 // TODO: check to see if missing bits are just not demanded.
1725 // Otherwise, this pattern doesn't match.
1729 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1730 /// by tblgen. Others should not call it.
1731 void SelectionDAGISel::
1732 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL) {
1733 std::vector<SDValue> InOps;
1734 std::swap(InOps, Ops);
1736 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1737 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1738 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1739 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1741 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1742 if (InOps[e-1].getValueType() == MVT::Glue)
1743 --e; // Don't process a glue operand if it is here.
1746 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1747 if (!InlineAsm::isMemKind(Flags)) {
1748 // Just skip over this operand, copying the operands verbatim.
1749 Ops.insert(Ops.end(), InOps.begin()+i,
1750 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1751 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1753 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1754 "Memory operand with multiple values?");
1756 unsigned TiedToOperand;
1757 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1758 // We need the constraint ID from the operand this is tied to.
1759 unsigned CurOp = InlineAsm::Op_FirstOperand;
1760 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1761 for (; TiedToOperand; --TiedToOperand) {
1762 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1763 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1767 // Otherwise, this is a memory operand. Ask the target to select it.
1768 std::vector<SDValue> SelOps;
1769 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1770 InlineAsm::getMemoryConstraintID(Flags),
1772 report_fatal_error("Could not match memory address. Inline asm"
1775 // Add this to the output node.
1777 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1778 Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32));
1779 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1784 // Add the glue input back if present.
1785 if (e != InOps.size())
1786 Ops.push_back(InOps.back());
1789 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1792 static SDNode *findGlueUse(SDNode *N) {
1793 unsigned FlagResNo = N->getNumValues()-1;
1794 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1795 SDUse &Use = I.getUse();
1796 if (Use.getResNo() == FlagResNo)
1797 return Use.getUser();
1802 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1803 /// This function recursively traverses up the operand chain, ignoring
1805 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1806 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1807 bool IgnoreChains) {
1808 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1809 // greater than all of its (recursive) operands. If we scan to a point where
1810 // 'use' is smaller than the node we're scanning for, then we know we will
1813 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1814 // happen because we scan down to newly selected nodes in the case of glue
1816 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1819 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1820 // won't fail if we scan it again.
1821 if (!Visited.insert(Use).second)
1824 for (const SDValue &Op : Use->op_values()) {
1825 // Ignore chain uses, they are validated by HandleMergeInputChains.
1826 if (Op.getValueType() == MVT::Other && IgnoreChains)
1829 SDNode *N = Op.getNode();
1831 if (Use == ImmedUse || Use == Root)
1832 continue; // We are not looking for immediate use.
1837 // Traverse up the operand chain.
1838 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1844 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1845 /// operand node N of U during instruction selection that starts at Root.
1846 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1847 SDNode *Root) const {
1848 if (OptLevel == CodeGenOpt::None) return false;
1849 return N.hasOneUse();
1852 /// IsLegalToFold - Returns true if the specific operand node N of
1853 /// U can be folded during instruction selection that starts at Root.
1854 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1855 CodeGenOpt::Level OptLevel,
1856 bool IgnoreChains) {
1857 if (OptLevel == CodeGenOpt::None) return false;
1859 // If Root use can somehow reach N through a path that that doesn't contain
1860 // U then folding N would create a cycle. e.g. In the following
1861 // diagram, Root can reach N through X. If N is folded into into Root, then
1862 // X is both a predecessor and a successor of U.
1873 // * indicates nodes to be folded together.
1875 // If Root produces glue, then it gets (even more) interesting. Since it
1876 // will be "glued" together with its glue use in the scheduler, we need to
1877 // check if it might reach N.
1896 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1897 // (call it Fold), then X is a predecessor of GU and a successor of
1898 // Fold. But since Fold and GU are glued together, this will create
1899 // a cycle in the scheduling graph.
1901 // If the node has glue, walk down the graph to the "lowest" node in the
1903 EVT VT = Root->getValueType(Root->getNumValues()-1);
1904 while (VT == MVT::Glue) {
1905 SDNode *GU = findGlueUse(Root);
1909 VT = Root->getValueType(Root->getNumValues()-1);
1911 // If our query node has a glue result with a use, we've walked up it. If
1912 // the user (which has already been selected) has a chain or indirectly uses
1913 // the chain, our WalkChainUsers predicate will not consider it. Because of
1914 // this, we cannot ignore chains in this predicate.
1915 IgnoreChains = false;
1919 SmallPtrSet<SDNode*, 16> Visited;
1920 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1923 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1926 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1927 SelectInlineAsmMemoryOperands(Ops, DL);
1929 const EVT VTs[] = {MVT::Other, MVT::Glue};
1930 SDValue New = CurDAG->getNode(ISD::INLINEASM, DL, VTs, Ops);
1932 return New.getNode();
1936 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1938 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1939 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1941 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0),
1943 SDValue New = CurDAG->getCopyFromReg(
1944 Op->getOperand(0), dl, Reg, Op->getValueType(0));
1946 return New.getNode();
1950 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1952 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1953 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1954 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1955 Op->getOperand(2).getValueType(),
1957 SDValue New = CurDAG->getCopyToReg(
1958 Op->getOperand(0), dl, Reg, Op->getOperand(2));
1960 return New.getNode();
1965 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1966 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1969 /// GetVBR - decode a vbr encoding whose top bit is set.
1970 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline uint64_t
1971 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1972 assert(Val >= 128 && "Not a VBR");
1973 Val &= 127; // Remove first vbr bit.
1978 NextBits = MatcherTable[Idx++];
1979 Val |= (NextBits&127) << Shift;
1981 } while (NextBits & 128);
1987 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1988 /// interior glue and chain results to use the new glue and chain results.
1989 void SelectionDAGISel::
1990 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1991 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1993 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1994 bool isMorphNodeTo) {
1995 SmallVector<SDNode*, 4> NowDeadNodes;
1997 // Now that all the normal results are replaced, we replace the chain and
1998 // glue results if present.
1999 if (!ChainNodesMatched.empty()) {
2000 assert(InputChain.getNode() &&
2001 "Matched input chains but didn't produce a chain");
2002 // Loop over all of the nodes we matched that produced a chain result.
2003 // Replace all the chain results with the final chain we ended up with.
2004 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2005 SDNode *ChainNode = ChainNodesMatched[i];
2007 // If this node was already deleted, don't look at it.
2008 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2011 // Don't replace the results of the root node if we're doing a
2013 if (ChainNode == NodeToMatch && isMorphNodeTo)
2016 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2017 if (ChainVal.getValueType() == MVT::Glue)
2018 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2019 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2020 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2022 // If the node became dead and we haven't already seen it, delete it.
2023 if (ChainNode->use_empty() &&
2024 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2025 NowDeadNodes.push_back(ChainNode);
2029 // If the result produces glue, update any glue results in the matched
2030 // pattern with the glue result.
2031 if (InputGlue.getNode()) {
2032 // Handle any interior nodes explicitly marked.
2033 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2034 SDNode *FRN = GlueResultNodesMatched[i];
2036 // If this node was already deleted, don't look at it.
2037 if (FRN->getOpcode() == ISD::DELETED_NODE)
2040 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2041 "Doesn't have a glue result");
2042 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2045 // If the node became dead and we haven't already seen it, delete it.
2046 if (FRN->use_empty() &&
2047 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2048 NowDeadNodes.push_back(FRN);
2052 if (!NowDeadNodes.empty())
2053 CurDAG->RemoveDeadNodes(NowDeadNodes);
2055 DEBUG(dbgs() << "ISEL: Match complete!\n");
2061 CR_LeadsToInteriorNode
2064 /// WalkChainUsers - Walk down the users of the specified chained node that is
2065 /// part of the pattern we're matching, looking at all of the users we find.
2066 /// This determines whether something is an interior node, whether we have a
2067 /// non-pattern node in between two pattern nodes (which prevent folding because
2068 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2069 /// between pattern nodes (in which case the TF becomes part of the pattern).
2071 /// The walk we do here is guaranteed to be small because we quickly get down to
2072 /// already selected nodes "below" us.
2074 WalkChainUsers(const SDNode *ChainedNode,
2075 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2076 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2077 ChainResult Result = CR_Simple;
2079 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2080 E = ChainedNode->use_end(); UI != E; ++UI) {
2081 // Make sure the use is of the chain, not some other value we produce.
2082 if (UI.getUse().getValueType() != MVT::Other) continue;
2086 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2089 // If we see an already-selected machine node, then we've gone beyond the
2090 // pattern that we're selecting down into the already selected chunk of the
2092 unsigned UserOpcode = User->getOpcode();
2093 if (User->isMachineOpcode() ||
2094 UserOpcode == ISD::CopyToReg ||
2095 UserOpcode == ISD::CopyFromReg ||
2096 UserOpcode == ISD::INLINEASM ||
2097 UserOpcode == ISD::EH_LABEL ||
2098 UserOpcode == ISD::LIFETIME_START ||
2099 UserOpcode == ISD::LIFETIME_END) {
2100 // If their node ID got reset to -1 then they've already been selected.
2101 // Treat them like a MachineOpcode.
2102 if (User->getNodeId() == -1)
2106 // If we have a TokenFactor, we handle it specially.
2107 if (User->getOpcode() != ISD::TokenFactor) {
2108 // If the node isn't a token factor and isn't part of our pattern, then it
2109 // must be a random chained node in between two nodes we're selecting.
2110 // This happens when we have something like:
2115 // Because we structurally match the load/store as a read/modify/write,
2116 // but the call is chained between them. We cannot fold in this case
2117 // because it would induce a cycle in the graph.
2118 if (!std::count(ChainedNodesInPattern.begin(),
2119 ChainedNodesInPattern.end(), User))
2120 return CR_InducesCycle;
2122 // Otherwise we found a node that is part of our pattern. For example in:
2126 // This would happen when we're scanning down from the load and see the
2127 // store as a user. Record that there is a use of ChainedNode that is
2128 // part of the pattern and keep scanning uses.
2129 Result = CR_LeadsToInteriorNode;
2130 InteriorChainedNodes.push_back(User);
2134 // If we found a TokenFactor, there are two cases to consider: first if the
2135 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2136 // uses of the TF are in our pattern) we just want to ignore it. Second,
2137 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2143 // | \ DAG's like cheese
2146 // [TokenFactor] [Op]
2153 // In this case, the TokenFactor becomes part of our match and we rewrite it
2154 // as a new TokenFactor.
2156 // To distinguish these two cases, do a recursive walk down the uses.
2157 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2159 // If the uses of the TokenFactor are just already-selected nodes, ignore
2160 // it, it is "below" our pattern.
2162 case CR_InducesCycle:
2163 // If the uses of the TokenFactor lead to nodes that are not part of our
2164 // pattern that are not selected, folding would turn this into a cycle,
2166 return CR_InducesCycle;
2167 case CR_LeadsToInteriorNode:
2168 break; // Otherwise, keep processing.
2171 // Okay, we know we're in the interesting interior case. The TokenFactor
2172 // is now going to be considered part of the pattern so that we rewrite its
2173 // uses (it may have uses that are not part of the pattern) with the
2174 // ultimate chain result of the generated code. We will also add its chain
2175 // inputs as inputs to the ultimate TokenFactor we create.
2176 Result = CR_LeadsToInteriorNode;
2177 ChainedNodesInPattern.push_back(User);
2178 InteriorChainedNodes.push_back(User);
2185 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2186 /// operation for when the pattern matched at least one node with a chains. The
2187 /// input vector contains a list of all of the chained nodes that we match. We
2188 /// must determine if this is a valid thing to cover (i.e. matching it won't
2189 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2190 /// be used as the input node chain for the generated nodes.
2192 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2193 SelectionDAG *CurDAG) {
2194 // Walk all of the chained nodes we've matched, recursively scanning down the
2195 // users of the chain result. This adds any TokenFactor nodes that are caught
2196 // in between chained nodes to the chained and interior nodes list.
2197 SmallVector<SDNode*, 3> InteriorChainedNodes;
2198 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2199 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2200 InteriorChainedNodes) == CR_InducesCycle)
2201 return SDValue(); // Would induce a cycle.
2204 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2205 // that we are interested in. Form our input TokenFactor node.
2206 SmallVector<SDValue, 3> InputChains;
2207 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2208 // Add the input chain of this node to the InputChains list (which will be
2209 // the operands of the generated TokenFactor) if it's not an interior node.
2210 SDNode *N = ChainNodesMatched[i];
2211 if (N->getOpcode() != ISD::TokenFactor) {
2212 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2215 // Otherwise, add the input chain.
2216 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2217 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2218 InputChains.push_back(InChain);
2222 // If we have a token factor, we want to add all inputs of the token factor
2223 // that are not part of the pattern we're matching.
2224 for (const SDValue &Op : N->op_values()) {
2225 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2227 InputChains.push_back(Op);
2231 if (InputChains.size() == 1)
2232 return InputChains[0];
2233 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2234 MVT::Other, InputChains);
2237 /// MorphNode - Handle morphing a node in place for the selector.
2238 SDNode *SelectionDAGISel::
2239 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2240 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2241 // It is possible we're using MorphNodeTo to replace a node with no
2242 // normal results with one that has a normal result (or we could be
2243 // adding a chain) and the input could have glue and chains as well.
2244 // In this case we need to shift the operands down.
2245 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2246 // than the old isel though.
2247 int OldGlueResultNo = -1, OldChainResultNo = -1;
2249 unsigned NTMNumResults = Node->getNumValues();
2250 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2251 OldGlueResultNo = NTMNumResults-1;
2252 if (NTMNumResults != 1 &&
2253 Node->getValueType(NTMNumResults-2) == MVT::Other)
2254 OldChainResultNo = NTMNumResults-2;
2255 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2256 OldChainResultNo = NTMNumResults-1;
2258 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2259 // that this deletes operands of the old node that become dead.
2260 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2262 // MorphNodeTo can operate in two ways: if an existing node with the
2263 // specified operands exists, it can just return it. Otherwise, it
2264 // updates the node in place to have the requested operands.
2266 // If we updated the node in place, reset the node ID. To the isel,
2267 // this should be just like a newly allocated machine node.
2271 unsigned ResNumResults = Res->getNumValues();
2272 // Move the glue if needed.
2273 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2274 (unsigned)OldGlueResultNo != ResNumResults-1)
2275 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2276 SDValue(Res, ResNumResults-1));
2278 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2281 // Move the chain reference if needed.
2282 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2283 (unsigned)OldChainResultNo != ResNumResults-1)
2284 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2285 SDValue(Res, ResNumResults-1));
2287 // Otherwise, no replacement happened because the node already exists. Replace
2288 // Uses of the old node with the new one.
2290 CurDAG->ReplaceAllUsesWith(Node, Res);
2295 /// CheckSame - Implements OP_CheckSame.
2296 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2297 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2299 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2300 // Accept if it is exactly the same as a previously recorded node.
2301 unsigned RecNo = MatcherTable[MatcherIndex++];
2302 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2303 return N == RecordedNodes[RecNo].first;
2306 /// CheckChildSame - Implements OP_CheckChildXSame.
2307 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2308 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2310 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2312 if (ChildNo >= N.getNumOperands())
2313 return false; // Match fails if out of range child #.
2314 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2318 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2319 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2320 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2321 const SelectionDAGISel &SDISel) {
2322 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2325 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2326 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2327 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2328 const SelectionDAGISel &SDISel, SDNode *N) {
2329 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2332 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2333 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2335 uint16_t Opc = MatcherTable[MatcherIndex++];
2336 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2337 return N->getOpcode() == Opc;
2340 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2341 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
2342 const TargetLowering *TLI, const DataLayout &DL) {
2343 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2344 if (N.getValueType() == VT) return true;
2346 // Handle the case when VT is iPTR.
2347 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(DL);
2350 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2351 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2352 SDValue N, const TargetLowering *TLI, const DataLayout &DL,
2354 if (ChildNo >= N.getNumOperands())
2355 return false; // Match fails if out of range child #.
2356 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI,
2360 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2361 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2363 return cast<CondCodeSDNode>(N)->get() ==
2364 (ISD::CondCode)MatcherTable[MatcherIndex++];
2367 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2368 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2369 SDValue N, const TargetLowering *TLI, const DataLayout &DL) {
2370 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2371 if (cast<VTSDNode>(N)->getVT() == VT)
2374 // Handle the case when VT is iPTR.
2375 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL);
2378 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2379 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2381 int64_t Val = MatcherTable[MatcherIndex++];
2383 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2385 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2386 return C && C->getSExtValue() == Val;
2389 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2390 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2391 SDValue N, unsigned ChildNo) {
2392 if (ChildNo >= N.getNumOperands())
2393 return false; // Match fails if out of range child #.
2394 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2397 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2398 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2399 SDValue N, const SelectionDAGISel &SDISel) {
2400 int64_t Val = MatcherTable[MatcherIndex++];
2402 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2404 if (N->getOpcode() != ISD::AND) return false;
2406 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2407 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2410 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2411 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2412 SDValue N, const SelectionDAGISel &SDISel) {
2413 int64_t Val = MatcherTable[MatcherIndex++];
2415 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2417 if (N->getOpcode() != ISD::OR) return false;
2419 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2420 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2423 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2424 /// scope, evaluate the current node. If the current predicate is known to
2425 /// fail, set Result=true and return anything. If the current predicate is
2426 /// known to pass, set Result=false and return the MatcherIndex to continue
2427 /// with. If the current predicate is unknown, set Result=false and return the
2428 /// MatcherIndex to continue with.
2429 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2430 unsigned Index, SDValue N,
2432 const SelectionDAGISel &SDISel,
2433 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2434 switch (Table[Index++]) {
2437 return Index-1; // Could not evaluate this predicate.
2438 case SelectionDAGISel::OPC_CheckSame:
2439 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2441 case SelectionDAGISel::OPC_CheckChild0Same:
2442 case SelectionDAGISel::OPC_CheckChild1Same:
2443 case SelectionDAGISel::OPC_CheckChild2Same:
2444 case SelectionDAGISel::OPC_CheckChild3Same:
2445 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2446 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2448 case SelectionDAGISel::OPC_CheckPatternPredicate:
2449 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2451 case SelectionDAGISel::OPC_CheckPredicate:
2452 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2454 case SelectionDAGISel::OPC_CheckOpcode:
2455 Result = !::CheckOpcode(Table, Index, N.getNode());
2457 case SelectionDAGISel::OPC_CheckType:
2458 Result = !::CheckType(Table, Index, N, SDISel.TLI,
2459 SDISel.CurDAG->getDataLayout());
2461 case SelectionDAGISel::OPC_CheckChild0Type:
2462 case SelectionDAGISel::OPC_CheckChild1Type:
2463 case SelectionDAGISel::OPC_CheckChild2Type:
2464 case SelectionDAGISel::OPC_CheckChild3Type:
2465 case SelectionDAGISel::OPC_CheckChild4Type:
2466 case SelectionDAGISel::OPC_CheckChild5Type:
2467 case SelectionDAGISel::OPC_CheckChild6Type:
2468 case SelectionDAGISel::OPC_CheckChild7Type:
2469 Result = !::CheckChildType(
2470 Table, Index, N, SDISel.TLI, SDISel.CurDAG->getDataLayout(),
2471 Table[Index - 1] - SelectionDAGISel::OPC_CheckChild0Type);
2473 case SelectionDAGISel::OPC_CheckCondCode:
2474 Result = !::CheckCondCode(Table, Index, N);
2476 case SelectionDAGISel::OPC_CheckValueType:
2477 Result = !::CheckValueType(Table, Index, N, SDISel.TLI,
2478 SDISel.CurDAG->getDataLayout());
2480 case SelectionDAGISel::OPC_CheckInteger:
2481 Result = !::CheckInteger(Table, Index, N);
2483 case SelectionDAGISel::OPC_CheckChild0Integer:
2484 case SelectionDAGISel::OPC_CheckChild1Integer:
2485 case SelectionDAGISel::OPC_CheckChild2Integer:
2486 case SelectionDAGISel::OPC_CheckChild3Integer:
2487 case SelectionDAGISel::OPC_CheckChild4Integer:
2488 Result = !::CheckChildInteger(Table, Index, N,
2489 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2491 case SelectionDAGISel::OPC_CheckAndImm:
2492 Result = !::CheckAndImm(Table, Index, N, SDISel);
2494 case SelectionDAGISel::OPC_CheckOrImm:
2495 Result = !::CheckOrImm(Table, Index, N, SDISel);
2503 /// FailIndex - If this match fails, this is the index to continue with.
2506 /// NodeStack - The node stack when the scope was formed.
2507 SmallVector<SDValue, 4> NodeStack;
2509 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2510 unsigned NumRecordedNodes;
2512 /// NumMatchedMemRefs - The number of matched memref entries.
2513 unsigned NumMatchedMemRefs;
2515 /// InputChain/InputGlue - The current chain/glue
2516 SDValue InputChain, InputGlue;
2518 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2519 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2522 /// \\brief A DAG update listener to keep the matching state
2523 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2524 /// change the DAG while matching. X86 addressing mode matcher is an example
2526 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2528 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2529 SmallVectorImpl<MatchScope> &MatchScopes;
2531 MatchStateUpdater(SelectionDAG &DAG,
2532 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2533 SmallVectorImpl<MatchScope> &MS) :
2534 SelectionDAG::DAGUpdateListener(DAG),
2535 RecordedNodes(RN), MatchScopes(MS) { }
2537 void NodeDeleted(SDNode *N, SDNode *E) override {
2538 // Some early-returns here to avoid the search if we deleted the node or
2539 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2540 // do, so it's unnecessary to update matching state at that point).
2541 // Neither of these can occur currently because we only install this
2542 // update listener during matching a complex patterns.
2543 if (!E || E->isMachineOpcode())
2545 // Performing linear search here does not matter because we almost never
2546 // run this code. You'd have to have a CSE during complex pattern
2548 for (auto &I : RecordedNodes)
2549 if (I.first.getNode() == N)
2552 for (auto &I : MatchScopes)
2553 for (auto &J : I.NodeStack)
2554 if (J.getNode() == N)
2560 SDNode *SelectionDAGISel::
2561 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2562 unsigned TableSize) {
2563 // FIXME: Should these even be selected? Handle these cases in the caller?
2564 switch (NodeToMatch->getOpcode()) {
2567 case ISD::EntryToken: // These nodes remain the same.
2568 case ISD::BasicBlock:
2570 case ISD::RegisterMask:
2571 case ISD::HANDLENODE:
2572 case ISD::MDNODE_SDNODE:
2573 case ISD::TargetConstant:
2574 case ISD::TargetConstantFP:
2575 case ISD::TargetConstantPool:
2576 case ISD::TargetFrameIndex:
2577 case ISD::TargetExternalSymbol:
2579 case ISD::TargetBlockAddress:
2580 case ISD::TargetJumpTable:
2581 case ISD::TargetGlobalTLSAddress:
2582 case ISD::TargetGlobalAddress:
2583 case ISD::TokenFactor:
2584 case ISD::CopyFromReg:
2585 case ISD::CopyToReg:
2587 case ISD::LIFETIME_START:
2588 case ISD::LIFETIME_END:
2589 NodeToMatch->setNodeId(-1); // Mark selected.
2591 case ISD::AssertSext:
2592 case ISD::AssertZext:
2593 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2594 NodeToMatch->getOperand(0));
2596 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2597 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2598 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2599 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2602 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2604 // Set up the node stack with NodeToMatch as the only node on the stack.
2605 SmallVector<SDValue, 8> NodeStack;
2606 SDValue N = SDValue(NodeToMatch, 0);
2607 NodeStack.push_back(N);
2609 // MatchScopes - Scopes used when matching, if a match failure happens, this
2610 // indicates where to continue checking.
2611 SmallVector<MatchScope, 8> MatchScopes;
2613 // RecordedNodes - This is the set of nodes that have been recorded by the
2614 // state machine. The second value is the parent of the node, or null if the
2615 // root is recorded.
2616 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2618 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2620 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2622 // These are the current input chain and glue for use when generating nodes.
2623 // Various Emit operations change these. For example, emitting a copytoreg
2624 // uses and updates these.
2625 SDValue InputChain, InputGlue;
2627 // ChainNodesMatched - If a pattern matches nodes that have input/output
2628 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2629 // which ones they are. The result is captured into this list so that we can
2630 // update the chain results when the pattern is complete.
2631 SmallVector<SDNode*, 3> ChainNodesMatched;
2632 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2634 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2635 NodeToMatch->dump(CurDAG);
2638 // Determine where to start the interpreter. Normally we start at opcode #0,
2639 // but if the state machine starts with an OPC_SwitchOpcode, then we
2640 // accelerate the first lookup (which is guaranteed to be hot) with the
2641 // OpcodeOffset table.
2642 unsigned MatcherIndex = 0;
2644 if (!OpcodeOffset.empty()) {
2645 // Already computed the OpcodeOffset table, just index into it.
2646 if (N.getOpcode() < OpcodeOffset.size())
2647 MatcherIndex = OpcodeOffset[N.getOpcode()];
2648 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2650 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2651 // Otherwise, the table isn't computed, but the state machine does start
2652 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2653 // is the first time we're selecting an instruction.
2656 // Get the size of this case.
2657 unsigned CaseSize = MatcherTable[Idx++];
2659 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2660 if (CaseSize == 0) break;
2662 // Get the opcode, add the index to the table.
2663 uint16_t Opc = MatcherTable[Idx++];
2664 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2665 if (Opc >= OpcodeOffset.size())
2666 OpcodeOffset.resize((Opc+1)*2);
2667 OpcodeOffset[Opc] = Idx;
2671 // Okay, do the lookup for the first opcode.
2672 if (N.getOpcode() < OpcodeOffset.size())
2673 MatcherIndex = OpcodeOffset[N.getOpcode()];
2677 assert(MatcherIndex < TableSize && "Invalid index");
2679 unsigned CurrentOpcodeIndex = MatcherIndex;
2681 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2684 // Okay, the semantics of this operation are that we should push a scope
2685 // then evaluate the first child. However, pushing a scope only to have
2686 // the first check fail (which then pops it) is inefficient. If we can
2687 // determine immediately that the first check (or first several) will
2688 // immediately fail, don't even bother pushing a scope for them.
2692 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2693 if (NumToSkip & 128)
2694 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2695 // Found the end of the scope with no match.
2696 if (NumToSkip == 0) {
2701 FailIndex = MatcherIndex+NumToSkip;
2703 unsigned MatcherIndexOfPredicate = MatcherIndex;
2704 (void)MatcherIndexOfPredicate; // silence warning.
2706 // If we can't evaluate this predicate without pushing a scope (e.g. if
2707 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2708 // push the scope and evaluate the full predicate chain.
2710 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2711 Result, *this, RecordedNodes);
2715 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2716 << "index " << MatcherIndexOfPredicate
2717 << ", continuing at " << FailIndex << "\n");
2718 ++NumDAGIselRetries;
2720 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2721 // move to the next case.
2722 MatcherIndex = FailIndex;
2725 // If the whole scope failed to match, bail.
2726 if (FailIndex == 0) break;
2728 // Push a MatchScope which indicates where to go if the first child fails
2730 MatchScope NewEntry;
2731 NewEntry.FailIndex = FailIndex;
2732 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2733 NewEntry.NumRecordedNodes = RecordedNodes.size();
2734 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2735 NewEntry.InputChain = InputChain;
2736 NewEntry.InputGlue = InputGlue;
2737 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2738 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2739 MatchScopes.push_back(NewEntry);
2742 case OPC_RecordNode: {
2743 // Remember this node, it may end up being an operand in the pattern.
2744 SDNode *Parent = nullptr;
2745 if (NodeStack.size() > 1)
2746 Parent = NodeStack[NodeStack.size()-2].getNode();
2747 RecordedNodes.push_back(std::make_pair(N, Parent));
2751 case OPC_RecordChild0: case OPC_RecordChild1:
2752 case OPC_RecordChild2: case OPC_RecordChild3:
2753 case OPC_RecordChild4: case OPC_RecordChild5:
2754 case OPC_RecordChild6: case OPC_RecordChild7: {
2755 unsigned ChildNo = Opcode-OPC_RecordChild0;
2756 if (ChildNo >= N.getNumOperands())
2757 break; // Match fails if out of range child #.
2759 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2763 case OPC_RecordMemRef:
2764 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2767 case OPC_CaptureGlueInput:
2768 // If the current node has an input glue, capture it in InputGlue.
2769 if (N->getNumOperands() != 0 &&
2770 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2771 InputGlue = N->getOperand(N->getNumOperands()-1);
2774 case OPC_MoveChild: {
2775 unsigned ChildNo = MatcherTable[MatcherIndex++];
2776 if (ChildNo >= N.getNumOperands())
2777 break; // Match fails if out of range child #.
2778 N = N.getOperand(ChildNo);
2779 NodeStack.push_back(N);
2783 case OPC_MoveParent:
2784 // Pop the current node off the NodeStack.
2785 NodeStack.pop_back();
2786 assert(!NodeStack.empty() && "Node stack imbalance!");
2787 N = NodeStack.back();
2791 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2794 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2795 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2796 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2797 Opcode-OPC_CheckChild0Same))
2801 case OPC_CheckPatternPredicate:
2802 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2804 case OPC_CheckPredicate:
2805 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2809 case OPC_CheckComplexPat: {
2810 unsigned CPNum = MatcherTable[MatcherIndex++];
2811 unsigned RecNo = MatcherTable[MatcherIndex++];
2812 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2814 // If target can modify DAG during matching, keep the matching state
2816 std::unique_ptr<MatchStateUpdater> MSU;
2817 if (ComplexPatternFuncMutatesDAG())
2818 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2821 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2822 RecordedNodes[RecNo].first, CPNum,
2827 case OPC_CheckOpcode:
2828 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2832 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI,
2833 CurDAG->getDataLayout()))
2837 case OPC_SwitchOpcode: {
2838 unsigned CurNodeOpcode = N.getOpcode();
2839 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2842 // Get the size of this case.
2843 CaseSize = MatcherTable[MatcherIndex++];
2845 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2846 if (CaseSize == 0) break;
2848 uint16_t Opc = MatcherTable[MatcherIndex++];
2849 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2851 // If the opcode matches, then we will execute this case.
2852 if (CurNodeOpcode == Opc)
2855 // Otherwise, skip over this case.
2856 MatcherIndex += CaseSize;
2859 // If no cases matched, bail out.
2860 if (CaseSize == 0) break;
2862 // Otherwise, execute the case we found.
2863 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2864 << " to " << MatcherIndex << "\n");
2868 case OPC_SwitchType: {
2869 MVT CurNodeVT = N.getSimpleValueType();
2870 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2873 // Get the size of this case.
2874 CaseSize = MatcherTable[MatcherIndex++];
2876 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2877 if (CaseSize == 0) break;
2879 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2880 if (CaseVT == MVT::iPTR)
2881 CaseVT = TLI->getPointerTy(CurDAG->getDataLayout());
2883 // If the VT matches, then we will execute this case.
2884 if (CurNodeVT == CaseVT)
2887 // Otherwise, skip over this case.
2888 MatcherIndex += CaseSize;
2891 // If no cases matched, bail out.
2892 if (CaseSize == 0) break;
2894 // Otherwise, execute the case we found.
2895 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2896 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2899 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2900 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2901 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2902 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2903 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2904 CurDAG->getDataLayout(),
2905 Opcode - OPC_CheckChild0Type))
2908 case OPC_CheckCondCode:
2909 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2911 case OPC_CheckValueType:
2912 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI,
2913 CurDAG->getDataLayout()))
2916 case OPC_CheckInteger:
2917 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2919 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2920 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2921 case OPC_CheckChild4Integer:
2922 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2923 Opcode-OPC_CheckChild0Integer)) break;
2925 case OPC_CheckAndImm:
2926 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2928 case OPC_CheckOrImm:
2929 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2932 case OPC_CheckFoldableChainNode: {
2933 assert(NodeStack.size() != 1 && "No parent node");
2934 // Verify that all intermediate nodes between the root and this one have
2936 bool HasMultipleUses = false;
2937 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2938 if (!NodeStack[i].hasOneUse()) {
2939 HasMultipleUses = true;
2942 if (HasMultipleUses) break;
2944 // Check to see that the target thinks this is profitable to fold and that
2945 // we can fold it without inducing cycles in the graph.
2946 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2948 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2949 NodeToMatch, OptLevel,
2950 true/*We validate our own chains*/))
2955 case OPC_EmitInteger: {
2956 MVT::SimpleValueType VT =
2957 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2958 int64_t Val = MatcherTable[MatcherIndex++];
2960 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2961 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2962 CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch),
2966 case OPC_EmitRegister: {
2967 MVT::SimpleValueType VT =
2968 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2969 unsigned RegNo = MatcherTable[MatcherIndex++];
2970 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2971 CurDAG->getRegister(RegNo, VT), nullptr));
2974 case OPC_EmitRegister2: {
2975 // For targets w/ more than 256 register names, the register enum
2976 // values are stored in two bytes in the matcher table (just like
2978 MVT::SimpleValueType VT =
2979 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2980 unsigned RegNo = MatcherTable[MatcherIndex++];
2981 RegNo |= MatcherTable[MatcherIndex++] << 8;
2982 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2983 CurDAG->getRegister(RegNo, VT), nullptr));
2987 case OPC_EmitConvertToTarget: {
2988 // Convert from IMM/FPIMM to target version.
2989 unsigned RecNo = MatcherTable[MatcherIndex++];
2990 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2991 SDValue Imm = RecordedNodes[RecNo].first;
2993 if (Imm->getOpcode() == ISD::Constant) {
2994 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2995 Imm = CurDAG->getConstant(*Val, SDLoc(NodeToMatch), Imm.getValueType(),
2997 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2998 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2999 Imm = CurDAG->getConstantFP(*Val, SDLoc(NodeToMatch),
3000 Imm.getValueType(), true);
3003 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
3007 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
3008 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
3009 // These are space-optimized forms of OPC_EmitMergeInputChains.
3010 assert(!InputChain.getNode() &&
3011 "EmitMergeInputChains should be the first chain producing node");
3012 assert(ChainNodesMatched.empty() &&
3013 "Should only have one EmitMergeInputChains per match");
3015 // Read all of the chained nodes.
3016 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3017 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3018 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3020 // FIXME: What if other value results of the node have uses not matched
3022 if (ChainNodesMatched.back() != NodeToMatch &&
3023 !RecordedNodes[RecNo].first.hasOneUse()) {
3024 ChainNodesMatched.clear();
3028 // Merge the input chains if they are not intra-pattern references.
3029 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3031 if (!InputChain.getNode())
3032 break; // Failed to merge.
3036 case OPC_EmitMergeInputChains: {
3037 assert(!InputChain.getNode() &&
3038 "EmitMergeInputChains should be the first chain producing node");
3039 // This node gets a list of nodes we matched in the input that have
3040 // chains. We want to token factor all of the input chains to these nodes
3041 // together. However, if any of the input chains is actually one of the
3042 // nodes matched in this pattern, then we have an intra-match reference.
3043 // Ignore these because the newly token factored chain should not refer to
3045 unsigned NumChains = MatcherTable[MatcherIndex++];
3046 assert(NumChains != 0 && "Can't TF zero chains");
3048 assert(ChainNodesMatched.empty() &&
3049 "Should only have one EmitMergeInputChains per match");
3051 // Read all of the chained nodes.
3052 for (unsigned i = 0; i != NumChains; ++i) {
3053 unsigned RecNo = MatcherTable[MatcherIndex++];
3054 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3055 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3057 // FIXME: What if other value results of the node have uses not matched
3059 if (ChainNodesMatched.back() != NodeToMatch &&
3060 !RecordedNodes[RecNo].first.hasOneUse()) {
3061 ChainNodesMatched.clear();
3066 // If the inner loop broke out, the match fails.
3067 if (ChainNodesMatched.empty())
3070 // Merge the input chains if they are not intra-pattern references.
3071 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3073 if (!InputChain.getNode())
3074 break; // Failed to merge.
3079 case OPC_EmitCopyToReg: {
3080 unsigned RecNo = MatcherTable[MatcherIndex++];
3081 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3082 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3084 if (!InputChain.getNode())
3085 InputChain = CurDAG->getEntryNode();
3087 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3088 DestPhysReg, RecordedNodes[RecNo].first,
3091 InputGlue = InputChain.getValue(1);
3095 case OPC_EmitNodeXForm: {
3096 unsigned XFormNo = MatcherTable[MatcherIndex++];
3097 unsigned RecNo = MatcherTable[MatcherIndex++];
3098 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3099 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3100 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3105 case OPC_MorphNodeTo: {
3106 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3107 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3108 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3109 // Get the result VT list.
3110 unsigned NumVTs = MatcherTable[MatcherIndex++];
3111 SmallVector<EVT, 4> VTs;
3112 for (unsigned i = 0; i != NumVTs; ++i) {
3113 MVT::SimpleValueType VT =
3114 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3115 if (VT == MVT::iPTR)
3116 VT = TLI->getPointerTy(CurDAG->getDataLayout()).SimpleTy;
3120 if (EmitNodeInfo & OPFL_Chain)
3121 VTs.push_back(MVT::Other);
3122 if (EmitNodeInfo & OPFL_GlueOutput)
3123 VTs.push_back(MVT::Glue);
3125 // This is hot code, so optimize the two most common cases of 1 and 2
3128 if (VTs.size() == 1)
3129 VTList = CurDAG->getVTList(VTs[0]);
3130 else if (VTs.size() == 2)
3131 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3133 VTList = CurDAG->getVTList(VTs);
3135 // Get the operand list.
3136 unsigned NumOps = MatcherTable[MatcherIndex++];
3137 SmallVector<SDValue, 8> Ops;
3138 for (unsigned i = 0; i != NumOps; ++i) {
3139 unsigned RecNo = MatcherTable[MatcherIndex++];
3141 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3143 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3144 Ops.push_back(RecordedNodes[RecNo].first);
3147 // If there are variadic operands to add, handle them now.
3148 if (EmitNodeInfo & OPFL_VariadicInfo) {
3149 // Determine the start index to copy from.
3150 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3151 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3152 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3153 "Invalid variadic node");
3154 // Copy all of the variadic operands, not including a potential glue
3156 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3158 SDValue V = NodeToMatch->getOperand(i);
3159 if (V.getValueType() == MVT::Glue) break;
3164 // If this has chain/glue inputs, add them.
3165 if (EmitNodeInfo & OPFL_Chain)
3166 Ops.push_back(InputChain);
3167 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3168 Ops.push_back(InputGlue);
3171 SDNode *Res = nullptr;
3172 if (Opcode != OPC_MorphNodeTo) {
3173 // If this is a normal EmitNode command, just create the new node and
3174 // add the results to the RecordedNodes list.
3175 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3178 // Add all the non-glue/non-chain results to the RecordedNodes list.
3179 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3180 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3181 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3185 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3186 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3188 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3189 // We will visit the equivalent node later.
3190 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3194 // If the node had chain/glue results, update our notion of the current
3196 if (EmitNodeInfo & OPFL_GlueOutput) {
3197 InputGlue = SDValue(Res, VTs.size()-1);
3198 if (EmitNodeInfo & OPFL_Chain)
3199 InputChain = SDValue(Res, VTs.size()-2);
3200 } else if (EmitNodeInfo & OPFL_Chain)
3201 InputChain = SDValue(Res, VTs.size()-1);
3203 // If the OPFL_MemRefs glue is set on this node, slap all of the
3204 // accumulated memrefs onto it.
3206 // FIXME: This is vastly incorrect for patterns with multiple outputs
3207 // instructions that access memory and for ComplexPatterns that match
3209 if (EmitNodeInfo & OPFL_MemRefs) {
3210 // Only attach load or store memory operands if the generated
3211 // instruction may load or store.
3212 const MCInstrDesc &MCID = TII->get(TargetOpc);
3213 bool mayLoad = MCID.mayLoad();
3214 bool mayStore = MCID.mayStore();
3216 unsigned NumMemRefs = 0;
3217 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3218 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3219 if ((*I)->isLoad()) {
3222 } else if ((*I)->isStore()) {
3230 MachineSDNode::mmo_iterator MemRefs =
3231 MF->allocateMemRefsArray(NumMemRefs);
3233 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3234 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3235 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3236 if ((*I)->isLoad()) {
3239 } else if ((*I)->isStore()) {
3247 cast<MachineSDNode>(Res)
3248 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3252 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3253 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3255 // If this was a MorphNodeTo then we're completely done!
3256 if (Opcode == OPC_MorphNodeTo) {
3257 // Update chain and glue uses.
3258 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3259 InputGlue, GlueResultNodesMatched, true);
3266 case OPC_MarkGlueResults: {
3267 unsigned NumNodes = MatcherTable[MatcherIndex++];
3269 // Read and remember all the glue-result nodes.
3270 for (unsigned i = 0; i != NumNodes; ++i) {
3271 unsigned RecNo = MatcherTable[MatcherIndex++];
3273 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3275 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3276 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3281 case OPC_CompleteMatch: {
3282 // The match has been completed, and any new nodes (if any) have been
3283 // created. Patch up references to the matched dag to use the newly
3285 unsigned NumResults = MatcherTable[MatcherIndex++];
3287 for (unsigned i = 0; i != NumResults; ++i) {
3288 unsigned ResSlot = MatcherTable[MatcherIndex++];
3290 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3292 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3293 SDValue Res = RecordedNodes[ResSlot].first;
3295 assert(i < NodeToMatch->getNumValues() &&
3296 NodeToMatch->getValueType(i) != MVT::Other &&
3297 NodeToMatch->getValueType(i) != MVT::Glue &&
3298 "Invalid number of results to complete!");
3299 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3300 NodeToMatch->getValueType(i) == MVT::iPTR ||
3301 Res.getValueType() == MVT::iPTR ||
3302 NodeToMatch->getValueType(i).getSizeInBits() ==
3303 Res.getValueType().getSizeInBits()) &&
3304 "invalid replacement");
3305 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3308 // If the root node defines glue, add it to the glue nodes to update list.
3309 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3310 GlueResultNodesMatched.push_back(NodeToMatch);
3312 // Update chain and glue uses.
3313 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3314 InputGlue, GlueResultNodesMatched, false);
3316 assert(NodeToMatch->use_empty() &&
3317 "Didn't replace all uses of the node?");
3319 // FIXME: We just return here, which interacts correctly with SelectRoot
3320 // above. We should fix this to not return an SDNode* anymore.
3325 // If the code reached this point, then the match failed. See if there is
3326 // another child to try in the current 'Scope', otherwise pop it until we
3327 // find a case to check.
3328 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3329 ++NumDAGIselRetries;
3331 if (MatchScopes.empty()) {
3332 CannotYetSelect(NodeToMatch);
3336 // Restore the interpreter state back to the point where the scope was
3338 MatchScope &LastScope = MatchScopes.back();
3339 RecordedNodes.resize(LastScope.NumRecordedNodes);
3341 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3342 N = NodeStack.back();
3344 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3345 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3346 MatcherIndex = LastScope.FailIndex;
3348 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3350 InputChain = LastScope.InputChain;
3351 InputGlue = LastScope.InputGlue;
3352 if (!LastScope.HasChainNodesMatched)
3353 ChainNodesMatched.clear();
3354 if (!LastScope.HasGlueResultNodesMatched)
3355 GlueResultNodesMatched.clear();
3357 // Check to see what the offset is at the new MatcherIndex. If it is zero
3358 // we have reached the end of this scope, otherwise we have another child
3359 // in the current scope to try.
3360 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3361 if (NumToSkip & 128)
3362 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3364 // If we have another child in this scope to match, update FailIndex and
3366 if (NumToSkip != 0) {
3367 LastScope.FailIndex = MatcherIndex+NumToSkip;
3371 // End of this scope, pop it and try the next child in the containing
3373 MatchScopes.pop_back();
3380 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3382 raw_string_ostream Msg(msg);
3383 Msg << "Cannot select: ";
3385 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3386 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3387 N->getOpcode() != ISD::INTRINSIC_VOID) {
3388 N->printrFull(Msg, CurDAG);
3389 Msg << "\nIn function: " << MF->getName();
3391 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3393 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3394 if (iid < Intrinsic::num_intrinsics)
3395 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3396 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3397 Msg << "target intrinsic %" << TII->getName(iid);
3399 Msg << "unknown intrinsic #" << iid;
3401 report_fatal_error(Msg.str());
3404 char SelectionDAGISel::ID = 0;