1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/GCStrategy.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/LibCallSemantics.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SelectionDAGISel.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/InlineAsm.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/IntrinsicInst.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/IR/LLVMContext.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/MC/MCAsmInfo.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetIntrinsicInfo.h"
55 #include "llvm/Target/TargetLowering.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "llvm/Target/TargetOptions.h"
58 #include "llvm/Target/TargetRegisterInfo.h"
59 #include "llvm/Target/TargetSubtargetInfo.h"
60 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
64 #define DEBUG_TYPE "isel"
66 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
67 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
68 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
69 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
70 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
71 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
72 STATISTIC(NumFastIselFailLowerArguments,
73 "Number of entry blocks where fast isel failed to lower arguments");
77 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
78 cl::desc("Enable extra verbose messages in the \"fast\" "
79 "instruction selector"));
82 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
83 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
84 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
85 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
86 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
87 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
88 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
90 // Standard binary operators...
91 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
92 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
93 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
94 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
95 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
96 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
97 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
98 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
99 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
100 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
101 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
102 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
104 // Logical operators...
105 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
106 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
107 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
109 // Memory instructions...
110 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
111 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
112 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
113 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
114 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
115 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
116 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
118 // Convert instructions...
119 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
120 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
121 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
122 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
123 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
124 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
125 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
126 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
127 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
128 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
129 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
130 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
132 // Other instructions...
133 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
134 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
135 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
136 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
137 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
138 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
139 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
140 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
141 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
142 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
143 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
144 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
145 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
146 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
147 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
149 // Intrinsic instructions...
150 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
151 STATISTIC(NumFastIselFailSAddWithOverflow,
152 "Fast isel fails on sadd.with.overflow");
153 STATISTIC(NumFastIselFailUAddWithOverflow,
154 "Fast isel fails on uadd.with.overflow");
155 STATISTIC(NumFastIselFailSSubWithOverflow,
156 "Fast isel fails on ssub.with.overflow");
157 STATISTIC(NumFastIselFailUSubWithOverflow,
158 "Fast isel fails on usub.with.overflow");
159 STATISTIC(NumFastIselFailSMulWithOverflow,
160 "Fast isel fails on smul.with.overflow");
161 STATISTIC(NumFastIselFailUMulWithOverflow,
162 "Fast isel fails on umul.with.overflow");
163 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
164 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
165 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
166 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
170 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
171 cl::desc("Enable verbose messages in the \"fast\" "
172 "instruction selector"));
173 static cl::opt<int> EnableFastISelAbort(
174 "fast-isel-abort", cl::Hidden,
175 cl::desc("Enable abort calls when \"fast\" instruction selection "
176 "fails to lower an instruction: 0 disable the abort, 1 will "
177 "abort but for args, calls and terminators, 2 will also "
178 "abort for argument lowering, and 3 will never fallback "
179 "to SelectionDAG."));
183 cl::desc("use Machine Branch Probability Info"),
184 cl::init(true), cl::Hidden);
187 static cl::opt<std::string>
188 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
189 cl::desc("Only display the basic block whose name "
190 "matches this for all view-*-dags options"));
192 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
193 cl::desc("Pop up a window to show dags before the first "
194 "dag combine pass"));
196 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
197 cl::desc("Pop up a window to show dags before legalize types"));
199 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
200 cl::desc("Pop up a window to show dags before legalize"));
202 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
203 cl::desc("Pop up a window to show dags before the second "
204 "dag combine pass"));
206 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
207 cl::desc("Pop up a window to show dags before the post legalize types"
208 " dag combine pass"));
210 ViewISelDAGs("view-isel-dags", cl::Hidden,
211 cl::desc("Pop up a window to show isel dags as they are selected"));
213 ViewSchedDAGs("view-sched-dags", cl::Hidden,
214 cl::desc("Pop up a window to show sched dags as they are processed"));
216 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
217 cl::desc("Pop up a window to show SUnit dags after they are processed"));
219 static const bool ViewDAGCombine1 = false,
220 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
221 ViewDAGCombine2 = false,
222 ViewDAGCombineLT = false,
223 ViewISelDAGs = false, ViewSchedDAGs = false,
224 ViewSUnitDAGs = false;
227 //===---------------------------------------------------------------------===//
229 /// RegisterScheduler class - Track the registration of instruction schedulers.
231 //===---------------------------------------------------------------------===//
232 MachinePassRegistry RegisterScheduler::Registry;
234 //===---------------------------------------------------------------------===//
236 /// ISHeuristic command line option for instruction schedulers.
238 //===---------------------------------------------------------------------===//
239 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
240 RegisterPassParser<RegisterScheduler> >
241 ISHeuristic("pre-RA-sched",
242 cl::init(&createDefaultScheduler), cl::Hidden,
243 cl::desc("Instruction schedulers available (before register"
246 static RegisterScheduler
247 defaultListDAGScheduler("default", "Best scheduler for the target",
248 createDefaultScheduler);
251 //===--------------------------------------------------------------------===//
252 /// \brief This class is used by SelectionDAGISel to temporarily override
253 /// the optimization level on a per-function basis.
254 class OptLevelChanger {
255 SelectionDAGISel &IS;
256 CodeGenOpt::Level SavedOptLevel;
260 OptLevelChanger(SelectionDAGISel &ISel,
261 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
262 SavedOptLevel = IS.OptLevel;
263 if (NewOptLevel == SavedOptLevel)
265 IS.OptLevel = NewOptLevel;
266 IS.TM.setOptLevel(NewOptLevel);
267 SavedFastISel = IS.TM.Options.EnableFastISel;
268 if (NewOptLevel == CodeGenOpt::None)
269 IS.TM.setFastISel(true);
270 DEBUG(dbgs() << "\nChanging optimization level for Function "
271 << IS.MF->getFunction()->getName() << "\n");
272 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
273 << " ; After: -O" << NewOptLevel << "\n");
277 if (IS.OptLevel == SavedOptLevel)
279 DEBUG(dbgs() << "\nRestoring optimization level for Function "
280 << IS.MF->getFunction()->getName() << "\n");
281 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
282 << " ; After: -O" << SavedOptLevel << "\n");
283 IS.OptLevel = SavedOptLevel;
284 IS.TM.setOptLevel(SavedOptLevel);
285 IS.TM.setFastISel(SavedFastISel);
289 //===--------------------------------------------------------------------===//
290 /// createDefaultScheduler - This creates an instruction scheduler appropriate
292 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
293 CodeGenOpt::Level OptLevel) {
294 const TargetLowering *TLI = IS->TLI;
295 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
297 // Try first to see if the Target has its own way of selecting a scheduler
298 if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
299 return SchedulerCtor(IS, OptLevel);
302 if (OptLevel == CodeGenOpt::None ||
303 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
304 TLI->getSchedulingPreference() == Sched::Source)
305 return createSourceListDAGScheduler(IS, OptLevel);
306 if (TLI->getSchedulingPreference() == Sched::RegPressure)
307 return createBURRListDAGScheduler(IS, OptLevel);
308 if (TLI->getSchedulingPreference() == Sched::Hybrid)
309 return createHybridListDAGScheduler(IS, OptLevel);
310 if (TLI->getSchedulingPreference() == Sched::VLIW)
311 return createVLIWDAGScheduler(IS, OptLevel);
312 assert(TLI->getSchedulingPreference() == Sched::ILP &&
313 "Unknown sched type!");
314 return createILPListDAGScheduler(IS, OptLevel);
318 // EmitInstrWithCustomInserter - This method should be implemented by targets
319 // that mark instructions with the 'usesCustomInserter' flag. These
320 // instructions are special in various ways, which require special support to
321 // insert. The specified MachineInstr is created but not inserted into any
322 // basic blocks, and this method is called to expand it into a sequence of
323 // instructions, potentially also creating new basic blocks and control flow.
324 // When new basic blocks are inserted and the edges from MBB to its successors
325 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
328 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
329 MachineBasicBlock *MBB) const {
331 dbgs() << "If a target marks an instruction with "
332 "'usesCustomInserter', it must implement "
333 "TargetLowering::EmitInstrWithCustomInserter!";
335 llvm_unreachable(nullptr);
338 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
339 SDNode *Node) const {
340 assert(!MI->hasPostISelHook() &&
341 "If a target marks an instruction with 'hasPostISelHook', "
342 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
345 //===----------------------------------------------------------------------===//
346 // SelectionDAGISel code
347 //===----------------------------------------------------------------------===//
349 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
350 CodeGenOpt::Level OL) :
351 MachineFunctionPass(ID), TM(tm),
352 FuncInfo(new FunctionLoweringInfo()),
353 CurDAG(new SelectionDAG(tm, OL)),
354 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
358 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
359 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
360 initializeBranchProbabilityInfoWrapperPassPass(
361 *PassRegistry::getPassRegistry());
362 initializeTargetLibraryInfoWrapperPassPass(
363 *PassRegistry::getPassRegistry());
366 SelectionDAGISel::~SelectionDAGISel() {
372 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
373 AU.addRequired<AliasAnalysis>();
374 AU.addPreserved<AliasAnalysis>();
375 AU.addRequired<GCModuleInfo>();
376 AU.addPreserved<GCModuleInfo>();
377 AU.addRequired<TargetLibraryInfoWrapperPass>();
378 if (UseMBPI && OptLevel != CodeGenOpt::None)
379 AU.addRequired<BranchProbabilityInfoWrapperPass>();
380 MachineFunctionPass::getAnalysisUsage(AU);
383 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
384 /// may trap on it. In this case we have to split the edge so that the path
385 /// through the predecessor block that doesn't go to the phi block doesn't
386 /// execute the possibly trapping instruction.
388 /// This is required for correctness, so it must be done at -O0.
390 static void SplitCriticalSideEffectEdges(Function &Fn) {
391 // Loop for blocks with phi nodes.
392 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
393 PHINode *PN = dyn_cast<PHINode>(BB->begin());
397 // For each block with a PHI node, check to see if any of the input values
398 // are potentially trapping constant expressions. Constant expressions are
399 // the only potentially trapping value that can occur as the argument to a
401 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
402 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
403 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
404 if (!CE || !CE->canTrap()) continue;
406 // The only case we have to worry about is when the edge is critical.
407 // Since this block has a PHI Node, we assume it has multiple input
408 // edges: check to see if the pred has multiple successors.
409 BasicBlock *Pred = PN->getIncomingBlock(i);
410 if (Pred->getTerminator()->getNumSuccessors() == 1)
413 // Okay, we have to split this edge.
415 Pred->getTerminator(), GetSuccessorNumber(Pred, BB),
416 CriticalEdgeSplittingOptions().setMergeIdenticalEdges());
422 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
423 // Do some sanity-checking on the command-line options.
424 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
425 "-fast-isel-verbose requires -fast-isel");
426 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
427 "-fast-isel-abort > 0 requires -fast-isel");
429 const Function &Fn = *mf.getFunction();
432 // Reset the target options before resetting the optimization
434 // FIXME: This is a horrible hack and should be processed via
435 // codegen looking at the optimization level explicitly when
436 // it wants to look at it.
437 TM.resetTargetOptions(Fn);
438 // Reset OptLevel to None for optnone functions.
439 CodeGenOpt::Level NewOptLevel = OptLevel;
440 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
441 NewOptLevel = CodeGenOpt::None;
442 OptLevelChanger OLC(*this, NewOptLevel);
444 TII = MF->getSubtarget().getInstrInfo();
445 TLI = MF->getSubtarget().getTargetLowering();
446 RegInfo = &MF->getRegInfo();
447 AA = &getAnalysis<AliasAnalysis>();
448 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
449 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
451 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
453 SplitCriticalSideEffectEdges(const_cast<Function &>(Fn));
456 FuncInfo->set(Fn, *MF, CurDAG);
458 if (UseMBPI && OptLevel != CodeGenOpt::None)
459 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
461 FuncInfo->BPI = nullptr;
463 SDB->init(GFI, *AA, LibInfo);
465 MF->setHasInlineAsm(false);
467 SelectAllBasicBlocks(Fn);
469 // If the first basic block in the function has live ins that need to be
470 // copied into vregs, emit the copies into the top of the block before
471 // emitting the code for the block.
472 MachineBasicBlock *EntryMBB = MF->begin();
473 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
474 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
476 DenseMap<unsigned, unsigned> LiveInMap;
477 if (!FuncInfo->ArgDbgValues.empty())
478 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
479 E = RegInfo->livein_end(); LI != E; ++LI)
481 LiveInMap.insert(std::make_pair(LI->first, LI->second));
483 // Insert DBG_VALUE instructions for function arguments to the entry block.
484 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
485 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
486 bool hasFI = MI->getOperand(0).isFI();
488 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
489 if (TargetRegisterInfo::isPhysicalRegister(Reg))
490 EntryMBB->insert(EntryMBB->begin(), MI);
492 MachineInstr *Def = RegInfo->getVRegDef(Reg);
494 MachineBasicBlock::iterator InsertPos = Def;
495 // FIXME: VR def may not be in entry block.
496 Def->getParent()->insert(std::next(InsertPos), MI);
498 DEBUG(dbgs() << "Dropping debug info for dead vreg"
499 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
502 // If Reg is live-in then update debug info to track its copy in a vreg.
503 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
504 if (LDI != LiveInMap.end()) {
505 assert(!hasFI && "There's no handling of frame pointer updating here yet "
507 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
508 MachineBasicBlock::iterator InsertPos = Def;
509 const MDNode *Variable = MI->getDebugVariable();
510 const MDNode *Expr = MI->getDebugExpression();
511 DebugLoc DL = MI->getDebugLoc();
512 bool IsIndirect = MI->isIndirectDebugValue();
513 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
514 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
515 "Expected inlined-at fields to agree");
516 // Def is never a terminator here, so it is ok to increment InsertPos.
517 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
518 IsIndirect, LDI->second, Offset, Variable, Expr);
520 // If this vreg is directly copied into an exported register then
521 // that COPY instructions also need DBG_VALUE, if it is the only
522 // user of LDI->second.
523 MachineInstr *CopyUseMI = nullptr;
524 for (MachineRegisterInfo::use_instr_iterator
525 UI = RegInfo->use_instr_begin(LDI->second),
526 E = RegInfo->use_instr_end(); UI != E; ) {
527 MachineInstr *UseMI = &*(UI++);
528 if (UseMI->isDebugValue()) continue;
529 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
530 CopyUseMI = UseMI; continue;
532 // Otherwise this is another use or second copy use.
533 CopyUseMI = nullptr; break;
536 // Use MI's debug location, which describes where Variable was
537 // declared, rather than whatever is attached to CopyUseMI.
538 MachineInstr *NewMI =
539 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
540 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
541 MachineBasicBlock::iterator Pos = CopyUseMI;
542 EntryMBB->insertAfter(Pos, NewMI);
547 // Determine if there are any calls in this machine function.
548 MachineFrameInfo *MFI = MF->getFrameInfo();
549 for (const auto &MBB : *MF) {
550 if (MFI->hasCalls() && MF->hasInlineAsm())
553 for (const auto &MI : MBB) {
554 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
555 if ((MCID.isCall() && !MCID.isReturn()) ||
556 MI.isStackAligningInlineAsm()) {
557 MFI->setHasCalls(true);
559 if (MI.isInlineAsm()) {
560 MF->setHasInlineAsm(true);
565 // Determine if there is a call to setjmp in the machine function.
566 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
568 // Replace forward-declared registers with the registers containing
569 // the desired value.
570 MachineRegisterInfo &MRI = MF->getRegInfo();
571 for (DenseMap<unsigned, unsigned>::iterator
572 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
574 unsigned From = I->first;
575 unsigned To = I->second;
576 // If To is also scheduled to be replaced, find what its ultimate
579 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
583 // Make sure the new register has a sufficiently constrained register class.
584 if (TargetRegisterInfo::isVirtualRegister(From) &&
585 TargetRegisterInfo::isVirtualRegister(To))
586 MRI.constrainRegClass(To, MRI.getRegClass(From));
590 // Replacing one register with another won't touch the kill flags.
591 // We need to conservatively clear the kill flags as a kill on the old
592 // register might dominate existing uses of the new register.
593 if (!MRI.use_empty(To))
594 MRI.clearKillFlags(From);
595 MRI.replaceRegWith(From, To);
598 // Freeze the set of reserved registers now that MachineFrameInfo has been
599 // set up. All the information required by getReservedRegs() should be
601 MRI.freezeReservedRegs(*MF);
603 // Release function-specific state. SDB and CurDAG are already cleared
607 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
608 DEBUG(MF->print(dbgs()));
613 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
614 BasicBlock::const_iterator End,
616 // Lower the instructions. If a call is emitted as a tail call, cease emitting
617 // nodes for this block.
618 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
621 // Make sure the root of the DAG is up-to-date.
622 CurDAG->setRoot(SDB->getControlRoot());
623 HadTailCall = SDB->HasTailCall;
626 // Final step, emit the lowered DAG as machine code.
630 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
631 SmallPtrSet<SDNode*, 128> VisitedNodes;
632 SmallVector<SDNode*, 128> Worklist;
634 Worklist.push_back(CurDAG->getRoot().getNode());
640 SDNode *N = Worklist.pop_back_val();
642 // If we've already seen this node, ignore it.
643 if (!VisitedNodes.insert(N).second)
646 // Otherwise, add all chain operands to the worklist.
647 for (const SDValue &Op : N->op_values())
648 if (Op.getValueType() == MVT::Other)
649 Worklist.push_back(Op.getNode());
651 // If this is a CopyToReg with a vreg dest, process it.
652 if (N->getOpcode() != ISD::CopyToReg)
655 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
656 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
659 // Ignore non-scalar or non-integer values.
660 SDValue Src = N->getOperand(2);
661 EVT SrcVT = Src.getValueType();
662 if (!SrcVT.isInteger() || SrcVT.isVector())
665 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
666 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
667 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
668 } while (!Worklist.empty());
671 void SelectionDAGISel::CodeGenAndEmitDAG() {
672 std::string GroupName;
673 if (TimePassesIsEnabled)
674 GroupName = "Instruction Selection and Scheduling";
675 std::string BlockName;
676 int BlockNumber = -1;
678 bool MatchFilterBB = false; (void)MatchFilterBB;
680 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
681 FilterDAGBasicBlockName ==
682 FuncInfo->MBB->getBasicBlock()->getName().str());
685 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
686 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
690 BlockNumber = FuncInfo->MBB->getNumber();
692 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
694 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
695 << " '" << BlockName << "'\n"; CurDAG->dump());
697 if (ViewDAGCombine1 && MatchFilterBB)
698 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
700 // Run the DAG combiner in pre-legalize mode.
702 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
703 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
706 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
707 << " '" << BlockName << "'\n"; CurDAG->dump());
709 // Second step, hack on the DAG until it only uses operations and types that
710 // the target supports.
711 if (ViewLegalizeTypesDAGs && MatchFilterBB)
712 CurDAG->viewGraph("legalize-types input for " + BlockName);
716 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
717 Changed = CurDAG->LegalizeTypes();
720 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
721 << " '" << BlockName << "'\n"; CurDAG->dump());
723 CurDAG->NewNodesMustHaveLegalTypes = true;
726 if (ViewDAGCombineLT && MatchFilterBB)
727 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
729 // Run the DAG combiner in post-type-legalize mode.
731 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
732 TimePassesIsEnabled);
733 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
736 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
737 << " '" << BlockName << "'\n"; CurDAG->dump());
742 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
743 Changed = CurDAG->LegalizeVectors();
748 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
749 CurDAG->LegalizeTypes();
752 if (ViewDAGCombineLT && MatchFilterBB)
753 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
755 // Run the DAG combiner in post-type-legalize mode.
757 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
758 TimePassesIsEnabled);
759 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
762 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
763 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
766 if (ViewLegalizeDAGs && MatchFilterBB)
767 CurDAG->viewGraph("legalize input for " + BlockName);
770 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
774 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
775 << " '" << BlockName << "'\n"; CurDAG->dump());
777 if (ViewDAGCombine2 && MatchFilterBB)
778 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
780 // Run the DAG combiner in post-legalize mode.
782 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
783 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
786 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
787 << " '" << BlockName << "'\n"; CurDAG->dump());
789 if (OptLevel != CodeGenOpt::None)
790 ComputeLiveOutVRegInfo();
792 if (ViewISelDAGs && MatchFilterBB)
793 CurDAG->viewGraph("isel input for " + BlockName);
795 // Third, instruction select all of the operations to machine code, adding the
796 // code to the MachineBasicBlock.
798 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
799 DoInstructionSelection();
802 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
803 << " '" << BlockName << "'\n"; CurDAG->dump());
805 if (ViewSchedDAGs && MatchFilterBB)
806 CurDAG->viewGraph("scheduler input for " + BlockName);
808 // Schedule machine code.
809 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
811 NamedRegionTimer T("Instruction Scheduling", GroupName,
812 TimePassesIsEnabled);
813 Scheduler->Run(CurDAG, FuncInfo->MBB);
816 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
818 // Emit machine code to BB. This can change 'BB' to the last block being
820 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
822 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
824 // FuncInfo->InsertPt is passed by reference and set to the end of the
825 // scheduled instructions.
826 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
829 // If the block was split, make sure we update any references that are used to
830 // update PHI nodes later on.
831 if (FirstMBB != LastMBB)
832 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
834 // Free the scheduler state.
836 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
837 TimePassesIsEnabled);
841 // Free the SelectionDAG state, now that we're finished with it.
846 /// ISelUpdater - helper class to handle updates of the instruction selection
848 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
849 SelectionDAG::allnodes_iterator &ISelPosition;
851 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
852 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
854 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
855 /// deleted is the current ISelPosition node, update ISelPosition.
857 void NodeDeleted(SDNode *N, SDNode *E) override {
858 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
862 } // end anonymous namespace
864 void SelectionDAGISel::DoInstructionSelection() {
865 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
866 << FuncInfo->MBB->getNumber()
867 << " '" << FuncInfo->MBB->getName() << "'\n");
871 // Select target instructions for the DAG.
873 // Number all nodes with a topological order and set DAGSize.
874 DAGSize = CurDAG->AssignTopologicalOrder();
876 // Create a dummy node (which is not added to allnodes), that adds
877 // a reference to the root node, preventing it from being deleted,
878 // and tracking any changes of the root.
879 HandleSDNode Dummy(CurDAG->getRoot());
880 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
883 // Make sure that ISelPosition gets properly updated when nodes are deleted
884 // in calls made from this function.
885 ISelUpdater ISU(*CurDAG, ISelPosition);
887 // The AllNodes list is now topological-sorted. Visit the
888 // nodes by starting at the end of the list (the root of the
889 // graph) and preceding back toward the beginning (the entry
891 while (ISelPosition != CurDAG->allnodes_begin()) {
892 SDNode *Node = --ISelPosition;
893 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
894 // but there are currently some corner cases that it misses. Also, this
895 // makes it theoretically possible to disable the DAGCombiner.
896 if (Node->use_empty())
899 SDNode *ResNode = Select(Node);
901 // FIXME: This is pretty gross. 'Select' should be changed to not return
902 // anything at all and this code should be nuked with a tactical strike.
904 // If node should not be replaced, continue with the next one.
905 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
909 ReplaceUses(Node, ResNode);
912 // If after the replacement this node is not used any more,
913 // remove this dead node.
914 if (Node->use_empty()) // Don't delete EntryToken, etc.
915 CurDAG->RemoveDeadNode(Node);
918 CurDAG->setRoot(Dummy.getValue());
921 DEBUG(dbgs() << "===== Instruction selection ends:\n");
923 PostprocessISelDAG();
926 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
927 /// do other setup for EH landing-pad blocks.
928 bool SelectionDAGISel::PrepareEHLandingPad() {
929 MachineBasicBlock *MBB = FuncInfo->MBB;
931 const TargetRegisterClass *PtrRC =
932 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout()));
934 // Add a label to mark the beginning of the landing pad. Deletion of the
935 // landing pad can thus be detected via the MachineModuleInfo.
936 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
938 // Assign the call site to the landing pad's begin label.
939 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
941 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
942 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
945 // If this is an MSVC-style personality function, we need to split the landing
946 // pad into several BBs.
947 const BasicBlock *LLVMBB = MBB->getBasicBlock();
948 const LandingPadInst *LPadInst = LLVMBB->getLandingPadInst();
949 MF->getMMI().addPersonality(MBB, cast<Function>(LPadInst->getParent()
952 ->stripPointerCasts()));
953 EHPersonality Personality = MF->getMMI().getPersonalityType();
955 if (isMSVCEHPersonality(Personality)) {
956 SmallVector<MachineBasicBlock *, 4> ClauseBBs;
957 const IntrinsicInst *ActionsCall =
958 dyn_cast<IntrinsicInst>(LLVMBB->getFirstInsertionPt());
959 // Get all invoke BBs that unwind to this landingpad.
960 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
962 if (ActionsCall && ActionsCall->getIntrinsicID() == Intrinsic::eh_actions) {
963 // If this is a call to llvm.eh.actions followed by indirectbr, then we've
964 // run WinEHPrepare, and we should remove this block from the machine CFG.
965 // Mark the targets of the indirectbr as landingpads instead.
966 for (const BasicBlock *LLVMSucc : successors(LLVMBB)) {
967 MachineBasicBlock *ClauseBB = FuncInfo->MBBMap[LLVMSucc];
968 // Add the edge from the invoke to the clause.
969 for (MachineBasicBlock *InvokeBB : InvokeBBs)
970 InvokeBB->addSuccessor(ClauseBB);
972 // Mark the clause as a landing pad or MI passes will delete it.
973 ClauseBB->setIsEHPad();
977 // Remove the edge from the invoke to the lpad.
978 for (MachineBasicBlock *InvokeBB : InvokeBBs)
979 InvokeBB->removeSuccessor(MBB);
981 // Don't select instructions for the landingpad.
985 // Mark exception register as live in.
986 if (unsigned Reg = TLI->getExceptionPointerRegister())
987 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
989 // Mark exception selector register as live in.
990 if (unsigned Reg = TLI->getExceptionSelectorRegister())
991 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
996 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
997 /// side-effect free and is either dead or folded into a generated instruction.
998 /// Return false if it needs to be emitted.
999 static bool isFoldedOrDeadInstruction(const Instruction *I,
1000 FunctionLoweringInfo *FuncInfo) {
1001 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
1002 !isa<TerminatorInst>(I) && // Terminators aren't folded.
1003 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
1004 !I->isEHPad() && // EH pad instructions aren't folded.
1005 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1009 // Collect per Instruction statistics for fast-isel misses. Only those
1010 // instructions that cause the bail are accounted for. It does not account for
1011 // instructions higher in the block. Thus, summing the per instructions stats
1012 // will not add up to what is reported by NumFastIselFailures.
1013 static void collectFailStats(const Instruction *I) {
1014 switch (I->getOpcode()) {
1015 default: assert (0 && "<Invalid operator> ");
1018 case Instruction::Ret: NumFastIselFailRet++; return;
1019 case Instruction::Br: NumFastIselFailBr++; return;
1020 case Instruction::Switch: NumFastIselFailSwitch++; return;
1021 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1022 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1023 case Instruction::Resume: NumFastIselFailResume++; return;
1024 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1026 // Standard binary operators...
1027 case Instruction::Add: NumFastIselFailAdd++; return;
1028 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1029 case Instruction::Sub: NumFastIselFailSub++; return;
1030 case Instruction::FSub: NumFastIselFailFSub++; return;
1031 case Instruction::Mul: NumFastIselFailMul++; return;
1032 case Instruction::FMul: NumFastIselFailFMul++; return;
1033 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1034 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1035 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1036 case Instruction::URem: NumFastIselFailURem++; return;
1037 case Instruction::SRem: NumFastIselFailSRem++; return;
1038 case Instruction::FRem: NumFastIselFailFRem++; return;
1040 // Logical operators...
1041 case Instruction::And: NumFastIselFailAnd++; return;
1042 case Instruction::Or: NumFastIselFailOr++; return;
1043 case Instruction::Xor: NumFastIselFailXor++; return;
1045 // Memory instructions...
1046 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1047 case Instruction::Load: NumFastIselFailLoad++; return;
1048 case Instruction::Store: NumFastIselFailStore++; return;
1049 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1050 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1051 case Instruction::Fence: NumFastIselFailFence++; return;
1052 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1054 // Convert instructions...
1055 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1056 case Instruction::ZExt: NumFastIselFailZExt++; return;
1057 case Instruction::SExt: NumFastIselFailSExt++; return;
1058 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1059 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1060 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1061 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1062 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1063 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1064 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1065 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1066 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1068 // Other instructions...
1069 case Instruction::ICmp: NumFastIselFailICmp++; return;
1070 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1071 case Instruction::PHI: NumFastIselFailPHI++; return;
1072 case Instruction::Select: NumFastIselFailSelect++; return;
1073 case Instruction::Call: {
1074 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1075 switch (Intrinsic->getIntrinsicID()) {
1077 NumFastIselFailIntrinsicCall++; return;
1078 case Intrinsic::sadd_with_overflow:
1079 NumFastIselFailSAddWithOverflow++; return;
1080 case Intrinsic::uadd_with_overflow:
1081 NumFastIselFailUAddWithOverflow++; return;
1082 case Intrinsic::ssub_with_overflow:
1083 NumFastIselFailSSubWithOverflow++; return;
1084 case Intrinsic::usub_with_overflow:
1085 NumFastIselFailUSubWithOverflow++; return;
1086 case Intrinsic::smul_with_overflow:
1087 NumFastIselFailSMulWithOverflow++; return;
1088 case Intrinsic::umul_with_overflow:
1089 NumFastIselFailUMulWithOverflow++; return;
1090 case Intrinsic::frameaddress:
1091 NumFastIselFailFrameaddress++; return;
1092 case Intrinsic::sqrt:
1093 NumFastIselFailSqrt++; return;
1094 case Intrinsic::experimental_stackmap:
1095 NumFastIselFailStackMap++; return;
1096 case Intrinsic::experimental_patchpoint_void: // fall-through
1097 case Intrinsic::experimental_patchpoint_i64:
1098 NumFastIselFailPatchPoint++; return;
1101 NumFastIselFailCall++;
1104 case Instruction::Shl: NumFastIselFailShl++; return;
1105 case Instruction::LShr: NumFastIselFailLShr++; return;
1106 case Instruction::AShr: NumFastIselFailAShr++; return;
1107 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1108 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1109 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1110 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1111 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1112 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1113 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1118 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1119 // Initialize the Fast-ISel state, if needed.
1120 FastISel *FastIS = nullptr;
1121 if (TM.Options.EnableFastISel)
1122 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1124 // Iterate over all basic blocks in the function.
1125 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1126 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1127 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1128 const BasicBlock *LLVMBB = *I;
1130 if (OptLevel != CodeGenOpt::None) {
1131 bool AllPredsVisited = true;
1132 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1134 if (!FuncInfo->VisitedBBs.count(*PI)) {
1135 AllPredsVisited = false;
1140 if (AllPredsVisited) {
1141 for (BasicBlock::const_iterator I = LLVMBB->begin();
1142 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1143 FuncInfo->ComputePHILiveOutRegInfo(PN);
1145 for (BasicBlock::const_iterator I = LLVMBB->begin();
1146 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1147 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1150 FuncInfo->VisitedBBs.insert(LLVMBB);
1153 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1154 BasicBlock::const_iterator const End = LLVMBB->end();
1155 BasicBlock::const_iterator BI = End;
1157 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1158 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1160 // Setup an EH landing-pad block.
1161 FuncInfo->ExceptionPointerVirtReg = 0;
1162 FuncInfo->ExceptionSelectorVirtReg = 0;
1163 if (LLVMBB->isLandingPad())
1164 if (!PrepareEHLandingPad())
1168 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1170 FastIS->startNewBlock();
1172 // Emit code for any incoming arguments. This must happen before
1173 // beginning FastISel on the entry block.
1174 if (LLVMBB == &Fn.getEntryBlock()) {
1177 // Lower any arguments needed in this block if this is the entry block.
1178 if (!FastIS->lowerArguments()) {
1179 // Fast isel failed to lower these arguments
1180 ++NumFastIselFailLowerArguments;
1181 if (EnableFastISelAbort > 1)
1182 report_fatal_error("FastISel didn't lower all arguments");
1184 // Use SelectionDAG argument lowering
1186 CurDAG->setRoot(SDB->getControlRoot());
1188 CodeGenAndEmitDAG();
1191 // If we inserted any instructions at the beginning, make a note of
1192 // where they are, so we can be sure to emit subsequent instructions
1194 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1195 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1197 FastIS->setLastLocalValue(nullptr);
1200 unsigned NumFastIselRemaining = std::distance(Begin, End);
1201 // Do FastISel on as many instructions as possible.
1202 for (; BI != Begin; --BI) {
1203 const Instruction *Inst = std::prev(BI);
1205 // If we no longer require this instruction, skip it.
1206 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1207 --NumFastIselRemaining;
1211 // Bottom-up: reset the insert pos at the top, after any local-value
1213 FastIS->recomputeInsertPt();
1215 // Try to select the instruction with FastISel.
1216 if (FastIS->selectInstruction(Inst)) {
1217 --NumFastIselRemaining;
1218 ++NumFastIselSuccess;
1219 // If fast isel succeeded, skip over all the folded instructions, and
1220 // then see if there is a load right before the selected instructions.
1221 // Try to fold the load if so.
1222 const Instruction *BeforeInst = Inst;
1223 while (BeforeInst != Begin) {
1224 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1225 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1228 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1229 BeforeInst->hasOneUse() &&
1230 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1231 // If we succeeded, don't re-select the load.
1232 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1233 --NumFastIselRemaining;
1234 ++NumFastIselSuccess;
1240 if (EnableFastISelVerbose2)
1241 collectFailStats(Inst);
1244 // Then handle certain instructions as single-LLVM-Instruction blocks.
1245 if (isa<CallInst>(Inst)) {
1247 if (EnableFastISelVerbose || EnableFastISelAbort) {
1248 dbgs() << "FastISel missed call: ";
1251 if (EnableFastISelAbort > 2)
1252 // FastISel selector couldn't handle something and bailed.
1253 // For the purpose of debugging, just abort.
1254 report_fatal_error("FastISel didn't select the entire block");
1256 if (!Inst->getType()->isVoidTy() && !Inst->getType()->isTokenTy() &&
1257 !Inst->use_empty()) {
1258 unsigned &R = FuncInfo->ValueMap[Inst];
1260 R = FuncInfo->CreateRegs(Inst->getType());
1263 bool HadTailCall = false;
1264 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1265 SelectBasicBlock(Inst, BI, HadTailCall);
1267 // If the call was emitted as a tail call, we're done with the block.
1268 // We also need to delete any previously emitted instructions.
1270 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1275 // Recompute NumFastIselRemaining as Selection DAG instruction
1276 // selection may have handled the call, input args, etc.
1277 unsigned RemainingNow = std::distance(Begin, BI);
1278 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1279 NumFastIselRemaining = RemainingNow;
1283 bool ShouldAbort = EnableFastISelAbort;
1284 if (EnableFastISelVerbose || EnableFastISelAbort) {
1285 if (isa<TerminatorInst>(Inst)) {
1286 // Use a different message for terminator misses.
1287 dbgs() << "FastISel missed terminator: ";
1288 // Don't abort unless for terminator unless the level is really high
1289 ShouldAbort = (EnableFastISelAbort > 2);
1291 dbgs() << "FastISel miss: ";
1296 // FastISel selector couldn't handle something and bailed.
1297 // For the purpose of debugging, just abort.
1298 report_fatal_error("FastISel didn't select the entire block");
1300 NumFastIselFailures += NumFastIselRemaining;
1304 FastIS->recomputeInsertPt();
1306 // Lower any arguments needed in this block if this is the entry block.
1307 if (LLVMBB == &Fn.getEntryBlock()) {
1316 ++NumFastIselBlocks;
1319 // Run SelectionDAG instruction selection on the remainder of the block
1320 // not handled by FastISel. If FastISel is not run, this is the entire
1323 SelectBasicBlock(Begin, BI, HadTailCall);
1327 FuncInfo->PHINodesToUpdate.clear();
1331 SDB->clearDanglingDebugInfo();
1332 SDB->SPDescriptor.resetPerFunctionState();
1335 /// Given that the input MI is before a partial terminator sequence TSeq, return
1336 /// true if M + TSeq also a partial terminator sequence.
1338 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1339 /// lowering copy vregs into physical registers, which are then passed into
1340 /// terminator instructors so we can satisfy ABI constraints. A partial
1341 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1342 /// may be the whole terminator sequence).
1343 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1344 // If we do not have a copy or an implicit def, we return true if and only if
1345 // MI is a debug value.
1346 if (!MI->isCopy() && !MI->isImplicitDef())
1347 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1348 // physical registers if there is debug info associated with the terminator
1349 // of our mbb. We want to include said debug info in our terminator
1350 // sequence, so we return true in that case.
1351 return MI->isDebugValue();
1353 // We have left the terminator sequence if we are not doing one of the
1356 // 1. Copying a vreg into a physical register.
1357 // 2. Copying a vreg into a vreg.
1358 // 3. Defining a register via an implicit def.
1360 // OPI should always be a register definition...
1361 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1362 if (!OPI->isReg() || !OPI->isDef())
1365 // Defining any register via an implicit def is always ok.
1366 if (MI->isImplicitDef())
1369 // Grab the copy source...
1370 MachineInstr::const_mop_iterator OPI2 = OPI;
1372 assert(OPI2 != MI->operands_end()
1373 && "Should have a copy implying we should have 2 arguments.");
1375 // Make sure that the copy dest is not a vreg when the copy source is a
1376 // physical register.
1377 if (!OPI2->isReg() ||
1378 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1379 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1385 /// Find the split point at which to splice the end of BB into its success stack
1386 /// protector check machine basic block.
1388 /// On many platforms, due to ABI constraints, terminators, even before register
1389 /// allocation, use physical registers. This creates an issue for us since
1390 /// physical registers at this point can not travel across basic
1391 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1392 /// when they enter functions and moves them through a sequence of copies back
1393 /// into the physical registers right before the terminator creating a
1394 /// ``Terminator Sequence''. This function is searching for the beginning of the
1395 /// terminator sequence so that we can ensure that we splice off not just the
1396 /// terminator, but additionally the copies that move the vregs into the
1397 /// physical registers.
1398 static MachineBasicBlock::iterator
1399 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1400 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1402 if (SplitPoint == BB->begin())
1405 MachineBasicBlock::iterator Start = BB->begin();
1406 MachineBasicBlock::iterator Previous = SplitPoint;
1409 while (MIIsInTerminatorSequence(Previous)) {
1410 SplitPoint = Previous;
1411 if (Previous == Start)
1420 SelectionDAGISel::FinishBasicBlock() {
1422 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1423 << FuncInfo->PHINodesToUpdate.size() << "\n";
1424 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1425 dbgs() << "Node " << i << " : ("
1426 << FuncInfo->PHINodesToUpdate[i].first
1427 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1429 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1430 // PHI nodes in successors.
1431 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1432 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1433 assert(PHI->isPHI() &&
1434 "This is not a machine PHI node that we are updating!");
1435 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1437 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1440 // Handle stack protector.
1441 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1442 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1443 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1445 // Find the split point to split the parent mbb. At the same time copy all
1446 // physical registers used in the tail of parent mbb into virtual registers
1447 // before the split point and back into physical registers after the split
1448 // point. This prevents us needing to deal with Live-ins and many other
1449 // register allocation issues caused by us splitting the parent mbb. The
1450 // register allocator will clean up said virtual copies later on.
1451 MachineBasicBlock::iterator SplitPoint =
1452 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1454 // Splice the terminator of ParentMBB into SuccessMBB.
1455 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1459 // Add compare/jump on neq/jump to the parent BB.
1460 FuncInfo->MBB = ParentMBB;
1461 FuncInfo->InsertPt = ParentMBB->end();
1462 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1463 CurDAG->setRoot(SDB->getRoot());
1465 CodeGenAndEmitDAG();
1467 // CodeGen Failure MBB if we have not codegened it yet.
1468 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1469 if (!FailureMBB->size()) {
1470 FuncInfo->MBB = FailureMBB;
1471 FuncInfo->InsertPt = FailureMBB->end();
1472 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1473 CurDAG->setRoot(SDB->getRoot());
1475 CodeGenAndEmitDAG();
1478 // Clear the Per-BB State.
1479 SDB->SPDescriptor.resetPerBBState();
1482 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1483 // Lower header first, if it wasn't already lowered
1484 if (!SDB->BitTestCases[i].Emitted) {
1485 // Set the current basic block to the mbb we wish to insert the code into
1486 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1487 FuncInfo->InsertPt = FuncInfo->MBB->end();
1489 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1490 CurDAG->setRoot(SDB->getRoot());
1492 CodeGenAndEmitDAG();
1495 uint32_t UnhandledWeight = 0;
1496 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1497 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1499 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1500 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1501 // Set the current basic block to the mbb we wish to insert the code into
1502 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1503 FuncInfo->InsertPt = FuncInfo->MBB->end();
1506 // If all cases cover a contiguous range, it is not necessary to jump to
1507 // the default block after the last bit test fails. This is because the
1508 // range check during bit test header creation has guaranteed that every
1509 // case here doesn't go outside the range.
1510 MachineBasicBlock *NextMBB;
1511 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej)
1512 NextMBB = SDB->BitTestCases[i].Cases[j + 1].TargetBB;
1513 else if (j + 1 != ej)
1514 NextMBB = SDB->BitTestCases[i].Cases[j + 1].ThisBB;
1516 NextMBB = SDB->BitTestCases[i].Default;
1518 SDB->visitBitTestCase(SDB->BitTestCases[i],
1521 SDB->BitTestCases[i].Reg,
1522 SDB->BitTestCases[i].Cases[j],
1525 CurDAG->setRoot(SDB->getRoot());
1527 CodeGenAndEmitDAG();
1529 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej)
1534 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1536 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1537 MachineBasicBlock *PHIBB = PHI->getParent();
1538 assert(PHI->isPHI() &&
1539 "This is not a machine PHI node that we are updating!");
1540 // This is "default" BB. We have two jumps to it. From "header" BB and
1541 // from last "case" BB.
1542 if (PHIBB == SDB->BitTestCases[i].Default)
1543 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1544 .addMBB(SDB->BitTestCases[i].Parent)
1545 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1546 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1547 // One of "cases" BB.
1548 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1550 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1551 if (cBB->isSuccessor(PHIBB))
1552 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1556 SDB->BitTestCases.clear();
1558 // If the JumpTable record is filled in, then we need to emit a jump table.
1559 // Updating the PHI nodes is tricky in this case, since we need to determine
1560 // whether the PHI is a successor of the range check MBB or the jump table MBB
1561 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1562 // Lower header first, if it wasn't already lowered
1563 if (!SDB->JTCases[i].first.Emitted) {
1564 // Set the current basic block to the mbb we wish to insert the code into
1565 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1566 FuncInfo->InsertPt = FuncInfo->MBB->end();
1568 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1570 CurDAG->setRoot(SDB->getRoot());
1572 CodeGenAndEmitDAG();
1575 // Set the current basic block to the mbb we wish to insert the code into
1576 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1577 FuncInfo->InsertPt = FuncInfo->MBB->end();
1579 SDB->visitJumpTable(SDB->JTCases[i].second);
1580 CurDAG->setRoot(SDB->getRoot());
1582 CodeGenAndEmitDAG();
1585 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1587 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1588 MachineBasicBlock *PHIBB = PHI->getParent();
1589 assert(PHI->isPHI() &&
1590 "This is not a machine PHI node that we are updating!");
1591 // "default" BB. We can go there only from header BB.
1592 if (PHIBB == SDB->JTCases[i].second.Default)
1593 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1594 .addMBB(SDB->JTCases[i].first.HeaderBB);
1595 // JT BB. Just iterate over successors here
1596 if (FuncInfo->MBB->isSuccessor(PHIBB))
1597 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1600 SDB->JTCases.clear();
1602 // If we generated any switch lowering information, build and codegen any
1603 // additional DAGs necessary.
1604 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1605 // Set the current basic block to the mbb we wish to insert the code into
1606 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1607 FuncInfo->InsertPt = FuncInfo->MBB->end();
1609 // Determine the unique successors.
1610 SmallVector<MachineBasicBlock *, 2> Succs;
1611 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1612 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1613 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1615 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1616 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1617 CurDAG->setRoot(SDB->getRoot());
1619 CodeGenAndEmitDAG();
1621 // Remember the last block, now that any splitting is done, for use in
1622 // populating PHI nodes in successors.
1623 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1625 // Handle any PHI nodes in successors of this chunk, as if we were coming
1626 // from the original BB before switch expansion. Note that PHI nodes can
1627 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1628 // handle them the right number of times.
1629 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1630 FuncInfo->MBB = Succs[i];
1631 FuncInfo->InsertPt = FuncInfo->MBB->end();
1632 // FuncInfo->MBB may have been removed from the CFG if a branch was
1634 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1635 for (MachineBasicBlock::iterator
1636 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1637 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1638 MachineInstrBuilder PHI(*MF, MBBI);
1639 // This value for this PHI node is recorded in PHINodesToUpdate.
1640 for (unsigned pn = 0; ; ++pn) {
1641 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1642 "Didn't find PHI entry!");
1643 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1644 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1652 SDB->SwitchCases.clear();
1656 /// Create the scheduler. If a specific scheduler was specified
1657 /// via the SchedulerRegistry, use it, otherwise select the
1658 /// one preferred by the target.
1660 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1661 return ISHeuristic(this, OptLevel);
1664 //===----------------------------------------------------------------------===//
1665 // Helper functions used by the generated instruction selector.
1666 //===----------------------------------------------------------------------===//
1667 // Calls to these methods are generated by tblgen.
1669 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1670 /// the dag combiner simplified the 255, we still want to match. RHS is the
1671 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1672 /// specified in the .td file (e.g. 255).
1673 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1674 int64_t DesiredMaskS) const {
1675 const APInt &ActualMask = RHS->getAPIntValue();
1676 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1678 // If the actual mask exactly matches, success!
1679 if (ActualMask == DesiredMask)
1682 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1683 if (ActualMask.intersects(~DesiredMask))
1686 // Otherwise, the DAG Combiner may have proven that the value coming in is
1687 // either already zero or is not demanded. Check for known zero input bits.
1688 APInt NeededMask = DesiredMask & ~ActualMask;
1689 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1692 // TODO: check to see if missing bits are just not demanded.
1694 // Otherwise, this pattern doesn't match.
1698 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1699 /// the dag combiner simplified the 255, we still want to match. RHS is the
1700 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1701 /// specified in the .td file (e.g. 255).
1702 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1703 int64_t DesiredMaskS) const {
1704 const APInt &ActualMask = RHS->getAPIntValue();
1705 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1707 // If the actual mask exactly matches, success!
1708 if (ActualMask == DesiredMask)
1711 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1712 if (ActualMask.intersects(~DesiredMask))
1715 // Otherwise, the DAG Combiner may have proven that the value coming in is
1716 // either already zero or is not demanded. Check for known zero input bits.
1717 APInt NeededMask = DesiredMask & ~ActualMask;
1719 APInt KnownZero, KnownOne;
1720 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1722 // If all the missing bits in the or are already known to be set, match!
1723 if ((NeededMask & KnownOne) == NeededMask)
1726 // TODO: check to see if missing bits are just not demanded.
1728 // Otherwise, this pattern doesn't match.
1732 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1733 /// by tblgen. Others should not call it.
1734 void SelectionDAGISel::
1735 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL) {
1736 std::vector<SDValue> InOps;
1737 std::swap(InOps, Ops);
1739 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1740 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1741 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1742 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1744 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1745 if (InOps[e-1].getValueType() == MVT::Glue)
1746 --e; // Don't process a glue operand if it is here.
1749 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1750 if (!InlineAsm::isMemKind(Flags)) {
1751 // Just skip over this operand, copying the operands verbatim.
1752 Ops.insert(Ops.end(), InOps.begin()+i,
1753 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1754 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1756 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1757 "Memory operand with multiple values?");
1759 unsigned TiedToOperand;
1760 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1761 // We need the constraint ID from the operand this is tied to.
1762 unsigned CurOp = InlineAsm::Op_FirstOperand;
1763 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1764 for (; TiedToOperand; --TiedToOperand) {
1765 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1766 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1770 // Otherwise, this is a memory operand. Ask the target to select it.
1771 std::vector<SDValue> SelOps;
1772 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1773 InlineAsm::getMemoryConstraintID(Flags),
1775 report_fatal_error("Could not match memory address. Inline asm"
1778 // Add this to the output node.
1780 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1781 Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32));
1782 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1787 // Add the glue input back if present.
1788 if (e != InOps.size())
1789 Ops.push_back(InOps.back());
1792 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1795 static SDNode *findGlueUse(SDNode *N) {
1796 unsigned FlagResNo = N->getNumValues()-1;
1797 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1798 SDUse &Use = I.getUse();
1799 if (Use.getResNo() == FlagResNo)
1800 return Use.getUser();
1805 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1806 /// This function recursively traverses up the operand chain, ignoring
1808 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1809 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1810 bool IgnoreChains) {
1811 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1812 // greater than all of its (recursive) operands. If we scan to a point where
1813 // 'use' is smaller than the node we're scanning for, then we know we will
1816 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1817 // happen because we scan down to newly selected nodes in the case of glue
1819 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1822 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1823 // won't fail if we scan it again.
1824 if (!Visited.insert(Use).second)
1827 for (const SDValue &Op : Use->op_values()) {
1828 // Ignore chain uses, they are validated by HandleMergeInputChains.
1829 if (Op.getValueType() == MVT::Other && IgnoreChains)
1832 SDNode *N = Op.getNode();
1834 if (Use == ImmedUse || Use == Root)
1835 continue; // We are not looking for immediate use.
1840 // Traverse up the operand chain.
1841 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1847 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1848 /// operand node N of U during instruction selection that starts at Root.
1849 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1850 SDNode *Root) const {
1851 if (OptLevel == CodeGenOpt::None) return false;
1852 return N.hasOneUse();
1855 /// IsLegalToFold - Returns true if the specific operand node N of
1856 /// U can be folded during instruction selection that starts at Root.
1857 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1858 CodeGenOpt::Level OptLevel,
1859 bool IgnoreChains) {
1860 if (OptLevel == CodeGenOpt::None) return false;
1862 // If Root use can somehow reach N through a path that that doesn't contain
1863 // U then folding N would create a cycle. e.g. In the following
1864 // diagram, Root can reach N through X. If N is folded into into Root, then
1865 // X is both a predecessor and a successor of U.
1876 // * indicates nodes to be folded together.
1878 // If Root produces glue, then it gets (even more) interesting. Since it
1879 // will be "glued" together with its glue use in the scheduler, we need to
1880 // check if it might reach N.
1899 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1900 // (call it Fold), then X is a predecessor of GU and a successor of
1901 // Fold. But since Fold and GU are glued together, this will create
1902 // a cycle in the scheduling graph.
1904 // If the node has glue, walk down the graph to the "lowest" node in the
1906 EVT VT = Root->getValueType(Root->getNumValues()-1);
1907 while (VT == MVT::Glue) {
1908 SDNode *GU = findGlueUse(Root);
1912 VT = Root->getValueType(Root->getNumValues()-1);
1914 // If our query node has a glue result with a use, we've walked up it. If
1915 // the user (which has already been selected) has a chain or indirectly uses
1916 // the chain, our WalkChainUsers predicate will not consider it. Because of
1917 // this, we cannot ignore chains in this predicate.
1918 IgnoreChains = false;
1922 SmallPtrSet<SDNode*, 16> Visited;
1923 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1926 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1929 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1930 SelectInlineAsmMemoryOperands(Ops, DL);
1932 const EVT VTs[] = {MVT::Other, MVT::Glue};
1933 SDValue New = CurDAG->getNode(ISD::INLINEASM, DL, VTs, Ops);
1935 return New.getNode();
1939 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1941 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1942 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1944 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0),
1946 SDValue New = CurDAG->getCopyFromReg(
1947 Op->getOperand(0), dl, Reg, Op->getValueType(0));
1949 return New.getNode();
1953 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1955 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1956 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1957 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1958 Op->getOperand(2).getValueType(),
1960 SDValue New = CurDAG->getCopyToReg(
1961 Op->getOperand(0), dl, Reg, Op->getOperand(2));
1963 return New.getNode();
1968 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1969 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1972 /// GetVBR - decode a vbr encoding whose top bit is set.
1973 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1974 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1975 assert(Val >= 128 && "Not a VBR");
1976 Val &= 127; // Remove first vbr bit.
1981 NextBits = MatcherTable[Idx++];
1982 Val |= (NextBits&127) << Shift;
1984 } while (NextBits & 128);
1990 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1991 /// interior glue and chain results to use the new glue and chain results.
1992 void SelectionDAGISel::
1993 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1994 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1996 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1997 bool isMorphNodeTo) {
1998 SmallVector<SDNode*, 4> NowDeadNodes;
2000 // Now that all the normal results are replaced, we replace the chain and
2001 // glue results if present.
2002 if (!ChainNodesMatched.empty()) {
2003 assert(InputChain.getNode() &&
2004 "Matched input chains but didn't produce a chain");
2005 // Loop over all of the nodes we matched that produced a chain result.
2006 // Replace all the chain results with the final chain we ended up with.
2007 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2008 SDNode *ChainNode = ChainNodesMatched[i];
2010 // If this node was already deleted, don't look at it.
2011 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2014 // Don't replace the results of the root node if we're doing a
2016 if (ChainNode == NodeToMatch && isMorphNodeTo)
2019 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2020 if (ChainVal.getValueType() == MVT::Glue)
2021 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2022 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2023 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2025 // If the node became dead and we haven't already seen it, delete it.
2026 if (ChainNode->use_empty() &&
2027 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2028 NowDeadNodes.push_back(ChainNode);
2032 // If the result produces glue, update any glue results in the matched
2033 // pattern with the glue result.
2034 if (InputGlue.getNode()) {
2035 // Handle any interior nodes explicitly marked.
2036 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2037 SDNode *FRN = GlueResultNodesMatched[i];
2039 // If this node was already deleted, don't look at it.
2040 if (FRN->getOpcode() == ISD::DELETED_NODE)
2043 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2044 "Doesn't have a glue result");
2045 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2048 // If the node became dead and we haven't already seen it, delete it.
2049 if (FRN->use_empty() &&
2050 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2051 NowDeadNodes.push_back(FRN);
2055 if (!NowDeadNodes.empty())
2056 CurDAG->RemoveDeadNodes(NowDeadNodes);
2058 DEBUG(dbgs() << "ISEL: Match complete!\n");
2064 CR_LeadsToInteriorNode
2067 /// WalkChainUsers - Walk down the users of the specified chained node that is
2068 /// part of the pattern we're matching, looking at all of the users we find.
2069 /// This determines whether something is an interior node, whether we have a
2070 /// non-pattern node in between two pattern nodes (which prevent folding because
2071 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2072 /// between pattern nodes (in which case the TF becomes part of the pattern).
2074 /// The walk we do here is guaranteed to be small because we quickly get down to
2075 /// already selected nodes "below" us.
2077 WalkChainUsers(const SDNode *ChainedNode,
2078 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2079 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2080 ChainResult Result = CR_Simple;
2082 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2083 E = ChainedNode->use_end(); UI != E; ++UI) {
2084 // Make sure the use is of the chain, not some other value we produce.
2085 if (UI.getUse().getValueType() != MVT::Other) continue;
2089 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2092 // If we see an already-selected machine node, then we've gone beyond the
2093 // pattern that we're selecting down into the already selected chunk of the
2095 unsigned UserOpcode = User->getOpcode();
2096 if (User->isMachineOpcode() ||
2097 UserOpcode == ISD::CopyToReg ||
2098 UserOpcode == ISD::CopyFromReg ||
2099 UserOpcode == ISD::INLINEASM ||
2100 UserOpcode == ISD::EH_LABEL ||
2101 UserOpcode == ISD::LIFETIME_START ||
2102 UserOpcode == ISD::LIFETIME_END) {
2103 // If their node ID got reset to -1 then they've already been selected.
2104 // Treat them like a MachineOpcode.
2105 if (User->getNodeId() == -1)
2109 // If we have a TokenFactor, we handle it specially.
2110 if (User->getOpcode() != ISD::TokenFactor) {
2111 // If the node isn't a token factor and isn't part of our pattern, then it
2112 // must be a random chained node in between two nodes we're selecting.
2113 // This happens when we have something like:
2118 // Because we structurally match the load/store as a read/modify/write,
2119 // but the call is chained between them. We cannot fold in this case
2120 // because it would induce a cycle in the graph.
2121 if (!std::count(ChainedNodesInPattern.begin(),
2122 ChainedNodesInPattern.end(), User))
2123 return CR_InducesCycle;
2125 // Otherwise we found a node that is part of our pattern. For example in:
2129 // This would happen when we're scanning down from the load and see the
2130 // store as a user. Record that there is a use of ChainedNode that is
2131 // part of the pattern and keep scanning uses.
2132 Result = CR_LeadsToInteriorNode;
2133 InteriorChainedNodes.push_back(User);
2137 // If we found a TokenFactor, there are two cases to consider: first if the
2138 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2139 // uses of the TF are in our pattern) we just want to ignore it. Second,
2140 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2146 // | \ DAG's like cheese
2149 // [TokenFactor] [Op]
2156 // In this case, the TokenFactor becomes part of our match and we rewrite it
2157 // as a new TokenFactor.
2159 // To distinguish these two cases, do a recursive walk down the uses.
2160 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2162 // If the uses of the TokenFactor are just already-selected nodes, ignore
2163 // it, it is "below" our pattern.
2165 case CR_InducesCycle:
2166 // If the uses of the TokenFactor lead to nodes that are not part of our
2167 // pattern that are not selected, folding would turn this into a cycle,
2169 return CR_InducesCycle;
2170 case CR_LeadsToInteriorNode:
2171 break; // Otherwise, keep processing.
2174 // Okay, we know we're in the interesting interior case. The TokenFactor
2175 // is now going to be considered part of the pattern so that we rewrite its
2176 // uses (it may have uses that are not part of the pattern) with the
2177 // ultimate chain result of the generated code. We will also add its chain
2178 // inputs as inputs to the ultimate TokenFactor we create.
2179 Result = CR_LeadsToInteriorNode;
2180 ChainedNodesInPattern.push_back(User);
2181 InteriorChainedNodes.push_back(User);
2188 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2189 /// operation for when the pattern matched at least one node with a chains. The
2190 /// input vector contains a list of all of the chained nodes that we match. We
2191 /// must determine if this is a valid thing to cover (i.e. matching it won't
2192 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2193 /// be used as the input node chain for the generated nodes.
2195 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2196 SelectionDAG *CurDAG) {
2197 // Walk all of the chained nodes we've matched, recursively scanning down the
2198 // users of the chain result. This adds any TokenFactor nodes that are caught
2199 // in between chained nodes to the chained and interior nodes list.
2200 SmallVector<SDNode*, 3> InteriorChainedNodes;
2201 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2202 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2203 InteriorChainedNodes) == CR_InducesCycle)
2204 return SDValue(); // Would induce a cycle.
2207 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2208 // that we are interested in. Form our input TokenFactor node.
2209 SmallVector<SDValue, 3> InputChains;
2210 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2211 // Add the input chain of this node to the InputChains list (which will be
2212 // the operands of the generated TokenFactor) if it's not an interior node.
2213 SDNode *N = ChainNodesMatched[i];
2214 if (N->getOpcode() != ISD::TokenFactor) {
2215 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2218 // Otherwise, add the input chain.
2219 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2220 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2221 InputChains.push_back(InChain);
2225 // If we have a token factor, we want to add all inputs of the token factor
2226 // that are not part of the pattern we're matching.
2227 for (const SDValue &Op : N->op_values()) {
2228 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2230 InputChains.push_back(Op);
2234 if (InputChains.size() == 1)
2235 return InputChains[0];
2236 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2237 MVT::Other, InputChains);
2240 /// MorphNode - Handle morphing a node in place for the selector.
2241 SDNode *SelectionDAGISel::
2242 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2243 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2244 // It is possible we're using MorphNodeTo to replace a node with no
2245 // normal results with one that has a normal result (or we could be
2246 // adding a chain) and the input could have glue and chains as well.
2247 // In this case we need to shift the operands down.
2248 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2249 // than the old isel though.
2250 int OldGlueResultNo = -1, OldChainResultNo = -1;
2252 unsigned NTMNumResults = Node->getNumValues();
2253 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2254 OldGlueResultNo = NTMNumResults-1;
2255 if (NTMNumResults != 1 &&
2256 Node->getValueType(NTMNumResults-2) == MVT::Other)
2257 OldChainResultNo = NTMNumResults-2;
2258 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2259 OldChainResultNo = NTMNumResults-1;
2261 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2262 // that this deletes operands of the old node that become dead.
2263 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2265 // MorphNodeTo can operate in two ways: if an existing node with the
2266 // specified operands exists, it can just return it. Otherwise, it
2267 // updates the node in place to have the requested operands.
2269 // If we updated the node in place, reset the node ID. To the isel,
2270 // this should be just like a newly allocated machine node.
2274 unsigned ResNumResults = Res->getNumValues();
2275 // Move the glue if needed.
2276 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2277 (unsigned)OldGlueResultNo != ResNumResults-1)
2278 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2279 SDValue(Res, ResNumResults-1));
2281 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2284 // Move the chain reference if needed.
2285 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2286 (unsigned)OldChainResultNo != ResNumResults-1)
2287 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2288 SDValue(Res, ResNumResults-1));
2290 // Otherwise, no replacement happened because the node already exists. Replace
2291 // Uses of the old node with the new one.
2293 CurDAG->ReplaceAllUsesWith(Node, Res);
2298 /// CheckSame - Implements OP_CheckSame.
2299 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2300 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2302 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2303 // Accept if it is exactly the same as a previously recorded node.
2304 unsigned RecNo = MatcherTable[MatcherIndex++];
2305 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2306 return N == RecordedNodes[RecNo].first;
2309 /// CheckChildSame - Implements OP_CheckChildXSame.
2310 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2311 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2313 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2315 if (ChildNo >= N.getNumOperands())
2316 return false; // Match fails if out of range child #.
2317 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2321 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2322 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2323 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2324 const SelectionDAGISel &SDISel) {
2325 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2328 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2329 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2330 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2331 const SelectionDAGISel &SDISel, SDNode *N) {
2332 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2335 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2336 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2338 uint16_t Opc = MatcherTable[MatcherIndex++];
2339 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2340 return N->getOpcode() == Opc;
2343 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2344 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
2345 const TargetLowering *TLI, const DataLayout &DL) {
2346 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2347 if (N.getValueType() == VT) return true;
2349 // Handle the case when VT is iPTR.
2350 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(DL);
2353 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2354 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2355 SDValue N, const TargetLowering *TLI, const DataLayout &DL,
2357 if (ChildNo >= N.getNumOperands())
2358 return false; // Match fails if out of range child #.
2359 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI,
2363 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2364 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2366 return cast<CondCodeSDNode>(N)->get() ==
2367 (ISD::CondCode)MatcherTable[MatcherIndex++];
2370 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2371 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2372 SDValue N, const TargetLowering *TLI, const DataLayout &DL) {
2373 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2374 if (cast<VTSDNode>(N)->getVT() == VT)
2377 // Handle the case when VT is iPTR.
2378 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL);
2381 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2382 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2384 int64_t Val = MatcherTable[MatcherIndex++];
2386 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2388 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2389 return C && C->getSExtValue() == Val;
2392 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2393 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2394 SDValue N, unsigned ChildNo) {
2395 if (ChildNo >= N.getNumOperands())
2396 return false; // Match fails if out of range child #.
2397 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2400 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2401 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2402 SDValue N, const SelectionDAGISel &SDISel) {
2403 int64_t Val = MatcherTable[MatcherIndex++];
2405 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2407 if (N->getOpcode() != ISD::AND) return false;
2409 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2410 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2413 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2414 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2415 SDValue N, const SelectionDAGISel &SDISel) {
2416 int64_t Val = MatcherTable[MatcherIndex++];
2418 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2420 if (N->getOpcode() != ISD::OR) return false;
2422 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2423 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2426 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2427 /// scope, evaluate the current node. If the current predicate is known to
2428 /// fail, set Result=true and return anything. If the current predicate is
2429 /// known to pass, set Result=false and return the MatcherIndex to continue
2430 /// with. If the current predicate is unknown, set Result=false and return the
2431 /// MatcherIndex to continue with.
2432 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2433 unsigned Index, SDValue N,
2435 const SelectionDAGISel &SDISel,
2436 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2437 switch (Table[Index++]) {
2440 return Index-1; // Could not evaluate this predicate.
2441 case SelectionDAGISel::OPC_CheckSame:
2442 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2444 case SelectionDAGISel::OPC_CheckChild0Same:
2445 case SelectionDAGISel::OPC_CheckChild1Same:
2446 case SelectionDAGISel::OPC_CheckChild2Same:
2447 case SelectionDAGISel::OPC_CheckChild3Same:
2448 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2449 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2451 case SelectionDAGISel::OPC_CheckPatternPredicate:
2452 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2454 case SelectionDAGISel::OPC_CheckPredicate:
2455 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2457 case SelectionDAGISel::OPC_CheckOpcode:
2458 Result = !::CheckOpcode(Table, Index, N.getNode());
2460 case SelectionDAGISel::OPC_CheckType:
2461 Result = !::CheckType(Table, Index, N, SDISel.TLI,
2462 SDISel.CurDAG->getDataLayout());
2464 case SelectionDAGISel::OPC_CheckChild0Type:
2465 case SelectionDAGISel::OPC_CheckChild1Type:
2466 case SelectionDAGISel::OPC_CheckChild2Type:
2467 case SelectionDAGISel::OPC_CheckChild3Type:
2468 case SelectionDAGISel::OPC_CheckChild4Type:
2469 case SelectionDAGISel::OPC_CheckChild5Type:
2470 case SelectionDAGISel::OPC_CheckChild6Type:
2471 case SelectionDAGISel::OPC_CheckChild7Type:
2472 Result = !::CheckChildType(
2473 Table, Index, N, SDISel.TLI, SDISel.CurDAG->getDataLayout(),
2474 Table[Index - 1] - SelectionDAGISel::OPC_CheckChild0Type);
2476 case SelectionDAGISel::OPC_CheckCondCode:
2477 Result = !::CheckCondCode(Table, Index, N);
2479 case SelectionDAGISel::OPC_CheckValueType:
2480 Result = !::CheckValueType(Table, Index, N, SDISel.TLI,
2481 SDISel.CurDAG->getDataLayout());
2483 case SelectionDAGISel::OPC_CheckInteger:
2484 Result = !::CheckInteger(Table, Index, N);
2486 case SelectionDAGISel::OPC_CheckChild0Integer:
2487 case SelectionDAGISel::OPC_CheckChild1Integer:
2488 case SelectionDAGISel::OPC_CheckChild2Integer:
2489 case SelectionDAGISel::OPC_CheckChild3Integer:
2490 case SelectionDAGISel::OPC_CheckChild4Integer:
2491 Result = !::CheckChildInteger(Table, Index, N,
2492 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2494 case SelectionDAGISel::OPC_CheckAndImm:
2495 Result = !::CheckAndImm(Table, Index, N, SDISel);
2497 case SelectionDAGISel::OPC_CheckOrImm:
2498 Result = !::CheckOrImm(Table, Index, N, SDISel);
2506 /// FailIndex - If this match fails, this is the index to continue with.
2509 /// NodeStack - The node stack when the scope was formed.
2510 SmallVector<SDValue, 4> NodeStack;
2512 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2513 unsigned NumRecordedNodes;
2515 /// NumMatchedMemRefs - The number of matched memref entries.
2516 unsigned NumMatchedMemRefs;
2518 /// InputChain/InputGlue - The current chain/glue
2519 SDValue InputChain, InputGlue;
2521 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2522 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2525 /// \\brief A DAG update listener to keep the matching state
2526 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2527 /// change the DAG while matching. X86 addressing mode matcher is an example
2529 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2531 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2532 SmallVectorImpl<MatchScope> &MatchScopes;
2534 MatchStateUpdater(SelectionDAG &DAG,
2535 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2536 SmallVectorImpl<MatchScope> &MS) :
2537 SelectionDAG::DAGUpdateListener(DAG),
2538 RecordedNodes(RN), MatchScopes(MS) { }
2540 void NodeDeleted(SDNode *N, SDNode *E) override {
2541 // Some early-returns here to avoid the search if we deleted the node or
2542 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2543 // do, so it's unnecessary to update matching state at that point).
2544 // Neither of these can occur currently because we only install this
2545 // update listener during matching a complex patterns.
2546 if (!E || E->isMachineOpcode())
2548 // Performing linear search here does not matter because we almost never
2549 // run this code. You'd have to have a CSE during complex pattern
2551 for (auto &I : RecordedNodes)
2552 if (I.first.getNode() == N)
2555 for (auto &I : MatchScopes)
2556 for (auto &J : I.NodeStack)
2557 if (J.getNode() == N)
2563 SDNode *SelectionDAGISel::
2564 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2565 unsigned TableSize) {
2566 // FIXME: Should these even be selected? Handle these cases in the caller?
2567 switch (NodeToMatch->getOpcode()) {
2570 case ISD::EntryToken: // These nodes remain the same.
2571 case ISD::BasicBlock:
2573 case ISD::RegisterMask:
2574 case ISD::HANDLENODE:
2575 case ISD::MDNODE_SDNODE:
2576 case ISD::TargetConstant:
2577 case ISD::TargetConstantFP:
2578 case ISD::TargetConstantPool:
2579 case ISD::TargetFrameIndex:
2580 case ISD::TargetExternalSymbol:
2582 case ISD::TargetBlockAddress:
2583 case ISD::TargetJumpTable:
2584 case ISD::TargetGlobalTLSAddress:
2585 case ISD::TargetGlobalAddress:
2586 case ISD::TokenFactor:
2587 case ISD::CopyFromReg:
2588 case ISD::CopyToReg:
2590 case ISD::LIFETIME_START:
2591 case ISD::LIFETIME_END:
2592 NodeToMatch->setNodeId(-1); // Mark selected.
2594 case ISD::AssertSext:
2595 case ISD::AssertZext:
2596 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2597 NodeToMatch->getOperand(0));
2599 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2600 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2601 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2602 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2605 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2607 // Set up the node stack with NodeToMatch as the only node on the stack.
2608 SmallVector<SDValue, 8> NodeStack;
2609 SDValue N = SDValue(NodeToMatch, 0);
2610 NodeStack.push_back(N);
2612 // MatchScopes - Scopes used when matching, if a match failure happens, this
2613 // indicates where to continue checking.
2614 SmallVector<MatchScope, 8> MatchScopes;
2616 // RecordedNodes - This is the set of nodes that have been recorded by the
2617 // state machine. The second value is the parent of the node, or null if the
2618 // root is recorded.
2619 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2621 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2623 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2625 // These are the current input chain and glue for use when generating nodes.
2626 // Various Emit operations change these. For example, emitting a copytoreg
2627 // uses and updates these.
2628 SDValue InputChain, InputGlue;
2630 // ChainNodesMatched - If a pattern matches nodes that have input/output
2631 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2632 // which ones they are. The result is captured into this list so that we can
2633 // update the chain results when the pattern is complete.
2634 SmallVector<SDNode*, 3> ChainNodesMatched;
2635 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2637 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2638 NodeToMatch->dump(CurDAG);
2641 // Determine where to start the interpreter. Normally we start at opcode #0,
2642 // but if the state machine starts with an OPC_SwitchOpcode, then we
2643 // accelerate the first lookup (which is guaranteed to be hot) with the
2644 // OpcodeOffset table.
2645 unsigned MatcherIndex = 0;
2647 if (!OpcodeOffset.empty()) {
2648 // Already computed the OpcodeOffset table, just index into it.
2649 if (N.getOpcode() < OpcodeOffset.size())
2650 MatcherIndex = OpcodeOffset[N.getOpcode()];
2651 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2653 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2654 // Otherwise, the table isn't computed, but the state machine does start
2655 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2656 // is the first time we're selecting an instruction.
2659 // Get the size of this case.
2660 unsigned CaseSize = MatcherTable[Idx++];
2662 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2663 if (CaseSize == 0) break;
2665 // Get the opcode, add the index to the table.
2666 uint16_t Opc = MatcherTable[Idx++];
2667 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2668 if (Opc >= OpcodeOffset.size())
2669 OpcodeOffset.resize((Opc+1)*2);
2670 OpcodeOffset[Opc] = Idx;
2674 // Okay, do the lookup for the first opcode.
2675 if (N.getOpcode() < OpcodeOffset.size())
2676 MatcherIndex = OpcodeOffset[N.getOpcode()];
2680 assert(MatcherIndex < TableSize && "Invalid index");
2682 unsigned CurrentOpcodeIndex = MatcherIndex;
2684 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2687 // Okay, the semantics of this operation are that we should push a scope
2688 // then evaluate the first child. However, pushing a scope only to have
2689 // the first check fail (which then pops it) is inefficient. If we can
2690 // determine immediately that the first check (or first several) will
2691 // immediately fail, don't even bother pushing a scope for them.
2695 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2696 if (NumToSkip & 128)
2697 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2698 // Found the end of the scope with no match.
2699 if (NumToSkip == 0) {
2704 FailIndex = MatcherIndex+NumToSkip;
2706 unsigned MatcherIndexOfPredicate = MatcherIndex;
2707 (void)MatcherIndexOfPredicate; // silence warning.
2709 // If we can't evaluate this predicate without pushing a scope (e.g. if
2710 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2711 // push the scope and evaluate the full predicate chain.
2713 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2714 Result, *this, RecordedNodes);
2718 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2719 << "index " << MatcherIndexOfPredicate
2720 << ", continuing at " << FailIndex << "\n");
2721 ++NumDAGIselRetries;
2723 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2724 // move to the next case.
2725 MatcherIndex = FailIndex;
2728 // If the whole scope failed to match, bail.
2729 if (FailIndex == 0) break;
2731 // Push a MatchScope which indicates where to go if the first child fails
2733 MatchScope NewEntry;
2734 NewEntry.FailIndex = FailIndex;
2735 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2736 NewEntry.NumRecordedNodes = RecordedNodes.size();
2737 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2738 NewEntry.InputChain = InputChain;
2739 NewEntry.InputGlue = InputGlue;
2740 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2741 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2742 MatchScopes.push_back(NewEntry);
2745 case OPC_RecordNode: {
2746 // Remember this node, it may end up being an operand in the pattern.
2747 SDNode *Parent = nullptr;
2748 if (NodeStack.size() > 1)
2749 Parent = NodeStack[NodeStack.size()-2].getNode();
2750 RecordedNodes.push_back(std::make_pair(N, Parent));
2754 case OPC_RecordChild0: case OPC_RecordChild1:
2755 case OPC_RecordChild2: case OPC_RecordChild3:
2756 case OPC_RecordChild4: case OPC_RecordChild5:
2757 case OPC_RecordChild6: case OPC_RecordChild7: {
2758 unsigned ChildNo = Opcode-OPC_RecordChild0;
2759 if (ChildNo >= N.getNumOperands())
2760 break; // Match fails if out of range child #.
2762 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2766 case OPC_RecordMemRef:
2767 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2770 case OPC_CaptureGlueInput:
2771 // If the current node has an input glue, capture it in InputGlue.
2772 if (N->getNumOperands() != 0 &&
2773 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2774 InputGlue = N->getOperand(N->getNumOperands()-1);
2777 case OPC_MoveChild: {
2778 unsigned ChildNo = MatcherTable[MatcherIndex++];
2779 if (ChildNo >= N.getNumOperands())
2780 break; // Match fails if out of range child #.
2781 N = N.getOperand(ChildNo);
2782 NodeStack.push_back(N);
2786 case OPC_MoveParent:
2787 // Pop the current node off the NodeStack.
2788 NodeStack.pop_back();
2789 assert(!NodeStack.empty() && "Node stack imbalance!");
2790 N = NodeStack.back();
2794 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2797 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2798 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2799 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2800 Opcode-OPC_CheckChild0Same))
2804 case OPC_CheckPatternPredicate:
2805 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2807 case OPC_CheckPredicate:
2808 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2812 case OPC_CheckComplexPat: {
2813 unsigned CPNum = MatcherTable[MatcherIndex++];
2814 unsigned RecNo = MatcherTable[MatcherIndex++];
2815 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2817 // If target can modify DAG during matching, keep the matching state
2819 std::unique_ptr<MatchStateUpdater> MSU;
2820 if (ComplexPatternFuncMutatesDAG())
2821 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2824 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2825 RecordedNodes[RecNo].first, CPNum,
2830 case OPC_CheckOpcode:
2831 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2835 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI,
2836 CurDAG->getDataLayout()))
2840 case OPC_SwitchOpcode: {
2841 unsigned CurNodeOpcode = N.getOpcode();
2842 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2845 // Get the size of this case.
2846 CaseSize = MatcherTable[MatcherIndex++];
2848 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2849 if (CaseSize == 0) break;
2851 uint16_t Opc = MatcherTable[MatcherIndex++];
2852 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2854 // If the opcode matches, then we will execute this case.
2855 if (CurNodeOpcode == Opc)
2858 // Otherwise, skip over this case.
2859 MatcherIndex += CaseSize;
2862 // If no cases matched, bail out.
2863 if (CaseSize == 0) break;
2865 // Otherwise, execute the case we found.
2866 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2867 << " to " << MatcherIndex << "\n");
2871 case OPC_SwitchType: {
2872 MVT CurNodeVT = N.getSimpleValueType();
2873 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2876 // Get the size of this case.
2877 CaseSize = MatcherTable[MatcherIndex++];
2879 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2880 if (CaseSize == 0) break;
2882 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2883 if (CaseVT == MVT::iPTR)
2884 CaseVT = TLI->getPointerTy(CurDAG->getDataLayout());
2886 // If the VT matches, then we will execute this case.
2887 if (CurNodeVT == CaseVT)
2890 // Otherwise, skip over this case.
2891 MatcherIndex += CaseSize;
2894 // If no cases matched, bail out.
2895 if (CaseSize == 0) break;
2897 // Otherwise, execute the case we found.
2898 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2899 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2902 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2903 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2904 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2905 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2906 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2907 CurDAG->getDataLayout(),
2908 Opcode - OPC_CheckChild0Type))
2911 case OPC_CheckCondCode:
2912 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2914 case OPC_CheckValueType:
2915 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI,
2916 CurDAG->getDataLayout()))
2919 case OPC_CheckInteger:
2920 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2922 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2923 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2924 case OPC_CheckChild4Integer:
2925 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2926 Opcode-OPC_CheckChild0Integer)) break;
2928 case OPC_CheckAndImm:
2929 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2931 case OPC_CheckOrImm:
2932 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2935 case OPC_CheckFoldableChainNode: {
2936 assert(NodeStack.size() != 1 && "No parent node");
2937 // Verify that all intermediate nodes between the root and this one have
2939 bool HasMultipleUses = false;
2940 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2941 if (!NodeStack[i].hasOneUse()) {
2942 HasMultipleUses = true;
2945 if (HasMultipleUses) break;
2947 // Check to see that the target thinks this is profitable to fold and that
2948 // we can fold it without inducing cycles in the graph.
2949 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2951 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2952 NodeToMatch, OptLevel,
2953 true/*We validate our own chains*/))
2958 case OPC_EmitInteger: {
2959 MVT::SimpleValueType VT =
2960 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2961 int64_t Val = MatcherTable[MatcherIndex++];
2963 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2964 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2965 CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch),
2969 case OPC_EmitRegister: {
2970 MVT::SimpleValueType VT =
2971 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2972 unsigned RegNo = MatcherTable[MatcherIndex++];
2973 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2974 CurDAG->getRegister(RegNo, VT), nullptr));
2977 case OPC_EmitRegister2: {
2978 // For targets w/ more than 256 register names, the register enum
2979 // values are stored in two bytes in the matcher table (just like
2981 MVT::SimpleValueType VT =
2982 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2983 unsigned RegNo = MatcherTable[MatcherIndex++];
2984 RegNo |= MatcherTable[MatcherIndex++] << 8;
2985 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2986 CurDAG->getRegister(RegNo, VT), nullptr));
2990 case OPC_EmitConvertToTarget: {
2991 // Convert from IMM/FPIMM to target version.
2992 unsigned RecNo = MatcherTable[MatcherIndex++];
2993 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2994 SDValue Imm = RecordedNodes[RecNo].first;
2996 if (Imm->getOpcode() == ISD::Constant) {
2997 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2998 Imm = CurDAG->getConstant(*Val, SDLoc(NodeToMatch), Imm.getValueType(),
3000 } else if (Imm->getOpcode() == ISD::ConstantFP) {
3001 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
3002 Imm = CurDAG->getConstantFP(*Val, SDLoc(NodeToMatch),
3003 Imm.getValueType(), true);
3006 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
3010 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
3011 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
3012 // These are space-optimized forms of OPC_EmitMergeInputChains.
3013 assert(!InputChain.getNode() &&
3014 "EmitMergeInputChains should be the first chain producing node");
3015 assert(ChainNodesMatched.empty() &&
3016 "Should only have one EmitMergeInputChains per match");
3018 // Read all of the chained nodes.
3019 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3020 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3021 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3023 // FIXME: What if other value results of the node have uses not matched
3025 if (ChainNodesMatched.back() != NodeToMatch &&
3026 !RecordedNodes[RecNo].first.hasOneUse()) {
3027 ChainNodesMatched.clear();
3031 // Merge the input chains if they are not intra-pattern references.
3032 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3034 if (!InputChain.getNode())
3035 break; // Failed to merge.
3039 case OPC_EmitMergeInputChains: {
3040 assert(!InputChain.getNode() &&
3041 "EmitMergeInputChains should be the first chain producing node");
3042 // This node gets a list of nodes we matched in the input that have
3043 // chains. We want to token factor all of the input chains to these nodes
3044 // together. However, if any of the input chains is actually one of the
3045 // nodes matched in this pattern, then we have an intra-match reference.
3046 // Ignore these because the newly token factored chain should not refer to
3048 unsigned NumChains = MatcherTable[MatcherIndex++];
3049 assert(NumChains != 0 && "Can't TF zero chains");
3051 assert(ChainNodesMatched.empty() &&
3052 "Should only have one EmitMergeInputChains per match");
3054 // Read all of the chained nodes.
3055 for (unsigned i = 0; i != NumChains; ++i) {
3056 unsigned RecNo = MatcherTable[MatcherIndex++];
3057 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3058 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3060 // FIXME: What if other value results of the node have uses not matched
3062 if (ChainNodesMatched.back() != NodeToMatch &&
3063 !RecordedNodes[RecNo].first.hasOneUse()) {
3064 ChainNodesMatched.clear();
3069 // If the inner loop broke out, the match fails.
3070 if (ChainNodesMatched.empty())
3073 // Merge the input chains if they are not intra-pattern references.
3074 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3076 if (!InputChain.getNode())
3077 break; // Failed to merge.
3082 case OPC_EmitCopyToReg: {
3083 unsigned RecNo = MatcherTable[MatcherIndex++];
3084 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3085 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3087 if (!InputChain.getNode())
3088 InputChain = CurDAG->getEntryNode();
3090 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3091 DestPhysReg, RecordedNodes[RecNo].first,
3094 InputGlue = InputChain.getValue(1);
3098 case OPC_EmitNodeXForm: {
3099 unsigned XFormNo = MatcherTable[MatcherIndex++];
3100 unsigned RecNo = MatcherTable[MatcherIndex++];
3101 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3102 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3103 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3108 case OPC_MorphNodeTo: {
3109 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3110 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3111 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3112 // Get the result VT list.
3113 unsigned NumVTs = MatcherTable[MatcherIndex++];
3114 SmallVector<EVT, 4> VTs;
3115 for (unsigned i = 0; i != NumVTs; ++i) {
3116 MVT::SimpleValueType VT =
3117 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3118 if (VT == MVT::iPTR)
3119 VT = TLI->getPointerTy(CurDAG->getDataLayout()).SimpleTy;
3123 if (EmitNodeInfo & OPFL_Chain)
3124 VTs.push_back(MVT::Other);
3125 if (EmitNodeInfo & OPFL_GlueOutput)
3126 VTs.push_back(MVT::Glue);
3128 // This is hot code, so optimize the two most common cases of 1 and 2
3131 if (VTs.size() == 1)
3132 VTList = CurDAG->getVTList(VTs[0]);
3133 else if (VTs.size() == 2)
3134 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3136 VTList = CurDAG->getVTList(VTs);
3138 // Get the operand list.
3139 unsigned NumOps = MatcherTable[MatcherIndex++];
3140 SmallVector<SDValue, 8> Ops;
3141 for (unsigned i = 0; i != NumOps; ++i) {
3142 unsigned RecNo = MatcherTable[MatcherIndex++];
3144 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3146 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3147 Ops.push_back(RecordedNodes[RecNo].first);
3150 // If there are variadic operands to add, handle them now.
3151 if (EmitNodeInfo & OPFL_VariadicInfo) {
3152 // Determine the start index to copy from.
3153 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3154 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3155 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3156 "Invalid variadic node");
3157 // Copy all of the variadic operands, not including a potential glue
3159 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3161 SDValue V = NodeToMatch->getOperand(i);
3162 if (V.getValueType() == MVT::Glue) break;
3167 // If this has chain/glue inputs, add them.
3168 if (EmitNodeInfo & OPFL_Chain)
3169 Ops.push_back(InputChain);
3170 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3171 Ops.push_back(InputGlue);
3174 SDNode *Res = nullptr;
3175 if (Opcode != OPC_MorphNodeTo) {
3176 // If this is a normal EmitNode command, just create the new node and
3177 // add the results to the RecordedNodes list.
3178 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3181 // Add all the non-glue/non-chain results to the RecordedNodes list.
3182 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3183 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3184 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3188 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3189 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3191 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3192 // We will visit the equivalent node later.
3193 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3197 // If the node had chain/glue results, update our notion of the current
3199 if (EmitNodeInfo & OPFL_GlueOutput) {
3200 InputGlue = SDValue(Res, VTs.size()-1);
3201 if (EmitNodeInfo & OPFL_Chain)
3202 InputChain = SDValue(Res, VTs.size()-2);
3203 } else if (EmitNodeInfo & OPFL_Chain)
3204 InputChain = SDValue(Res, VTs.size()-1);
3206 // If the OPFL_MemRefs glue is set on this node, slap all of the
3207 // accumulated memrefs onto it.
3209 // FIXME: This is vastly incorrect for patterns with multiple outputs
3210 // instructions that access memory and for ComplexPatterns that match
3212 if (EmitNodeInfo & OPFL_MemRefs) {
3213 // Only attach load or store memory operands if the generated
3214 // instruction may load or store.
3215 const MCInstrDesc &MCID = TII->get(TargetOpc);
3216 bool mayLoad = MCID.mayLoad();
3217 bool mayStore = MCID.mayStore();
3219 unsigned NumMemRefs = 0;
3220 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3221 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3222 if ((*I)->isLoad()) {
3225 } else if ((*I)->isStore()) {
3233 MachineSDNode::mmo_iterator MemRefs =
3234 MF->allocateMemRefsArray(NumMemRefs);
3236 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3237 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3238 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3239 if ((*I)->isLoad()) {
3242 } else if ((*I)->isStore()) {
3250 cast<MachineSDNode>(Res)
3251 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3255 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3256 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3258 // If this was a MorphNodeTo then we're completely done!
3259 if (Opcode == OPC_MorphNodeTo) {
3260 // Update chain and glue uses.
3261 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3262 InputGlue, GlueResultNodesMatched, true);
3269 case OPC_MarkGlueResults: {
3270 unsigned NumNodes = MatcherTable[MatcherIndex++];
3272 // Read and remember all the glue-result nodes.
3273 for (unsigned i = 0; i != NumNodes; ++i) {
3274 unsigned RecNo = MatcherTable[MatcherIndex++];
3276 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3278 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3279 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3284 case OPC_CompleteMatch: {
3285 // The match has been completed, and any new nodes (if any) have been
3286 // created. Patch up references to the matched dag to use the newly
3288 unsigned NumResults = MatcherTable[MatcherIndex++];
3290 for (unsigned i = 0; i != NumResults; ++i) {
3291 unsigned ResSlot = MatcherTable[MatcherIndex++];
3293 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3295 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3296 SDValue Res = RecordedNodes[ResSlot].first;
3298 assert(i < NodeToMatch->getNumValues() &&
3299 NodeToMatch->getValueType(i) != MVT::Other &&
3300 NodeToMatch->getValueType(i) != MVT::Glue &&
3301 "Invalid number of results to complete!");
3302 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3303 NodeToMatch->getValueType(i) == MVT::iPTR ||
3304 Res.getValueType() == MVT::iPTR ||
3305 NodeToMatch->getValueType(i).getSizeInBits() ==
3306 Res.getValueType().getSizeInBits()) &&
3307 "invalid replacement");
3308 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3311 // If the root node defines glue, add it to the glue nodes to update list.
3312 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3313 GlueResultNodesMatched.push_back(NodeToMatch);
3315 // Update chain and glue uses.
3316 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3317 InputGlue, GlueResultNodesMatched, false);
3319 assert(NodeToMatch->use_empty() &&
3320 "Didn't replace all uses of the node?");
3322 // FIXME: We just return here, which interacts correctly with SelectRoot
3323 // above. We should fix this to not return an SDNode* anymore.
3328 // If the code reached this point, then the match failed. See if there is
3329 // another child to try in the current 'Scope', otherwise pop it until we
3330 // find a case to check.
3331 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3332 ++NumDAGIselRetries;
3334 if (MatchScopes.empty()) {
3335 CannotYetSelect(NodeToMatch);
3339 // Restore the interpreter state back to the point where the scope was
3341 MatchScope &LastScope = MatchScopes.back();
3342 RecordedNodes.resize(LastScope.NumRecordedNodes);
3344 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3345 N = NodeStack.back();
3347 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3348 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3349 MatcherIndex = LastScope.FailIndex;
3351 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3353 InputChain = LastScope.InputChain;
3354 InputGlue = LastScope.InputGlue;
3355 if (!LastScope.HasChainNodesMatched)
3356 ChainNodesMatched.clear();
3357 if (!LastScope.HasGlueResultNodesMatched)
3358 GlueResultNodesMatched.clear();
3360 // Check to see what the offset is at the new MatcherIndex. If it is zero
3361 // we have reached the end of this scope, otherwise we have another child
3362 // in the current scope to try.
3363 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3364 if (NumToSkip & 128)
3365 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3367 // If we have another child in this scope to match, update FailIndex and
3369 if (NumToSkip != 0) {
3370 LastScope.FailIndex = MatcherIndex+NumToSkip;
3374 // End of this scope, pop it and try the next child in the containing
3376 MatchScopes.pop_back();
3383 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3385 raw_string_ostream Msg(msg);
3386 Msg << "Cannot select: ";
3388 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3389 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3390 N->getOpcode() != ISD::INTRINSIC_VOID) {
3391 N->printrFull(Msg, CurDAG);
3392 Msg << "\nIn function: " << MF->getName();
3394 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3396 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3397 if (iid < Intrinsic::num_intrinsics)
3398 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3399 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3400 Msg << "target intrinsic %" << TII->getName(iid);
3402 Msg << "unknown intrinsic #" << iid;
3404 report_fatal_error(Msg.str());
3407 char SelectionDAGISel::ID = 0;