1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/GCStrategy.h"
33 #include "llvm/CodeGen/GCMetadata.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineJumpTableInfo.h"
39 #include "llvm/CodeGen/MachineModuleInfo.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
42 #include "llvm/CodeGen/SchedulerRegistry.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/CodeGen/DwarfWriter.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameInfo.h"
48 #include "llvm/Target/TargetIntrinsicInfo.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetLowering.h"
51 #include "llvm/Target/TargetMachine.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/Timer.h"
58 #include "llvm/Support/raw_ostream.h"
63 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
64 cl::desc("Enable verbose messages in the \"fast\" "
65 "instruction selector"));
67 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
68 cl::desc("Enable abort calls when \"fast\" instruction fails"));
70 SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
71 cl::desc("Schedule copies of livein registers"),
76 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
77 cl::desc("Pop up a window to show dags before the first "
80 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before legalize types"));
83 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize"));
86 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before the second "
90 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
91 cl::desc("Pop up a window to show dags before the post legalize types"
92 " dag combine pass"));
94 ViewISelDAGs("view-isel-dags", cl::Hidden,
95 cl::desc("Pop up a window to show isel dags as they are selected"));
97 ViewSchedDAGs("view-sched-dags", cl::Hidden,
98 cl::desc("Pop up a window to show sched dags as they are processed"));
100 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
101 cl::desc("Pop up a window to show SUnit dags after they are processed"));
103 static const bool ViewDAGCombine1 = false,
104 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
105 ViewDAGCombine2 = false,
106 ViewDAGCombineLT = false,
107 ViewISelDAGs = false, ViewSchedDAGs = false,
108 ViewSUnitDAGs = false;
111 //===---------------------------------------------------------------------===//
113 /// RegisterScheduler class - Track the registration of instruction schedulers.
115 //===---------------------------------------------------------------------===//
116 MachinePassRegistry RegisterScheduler::Registry;
118 //===---------------------------------------------------------------------===//
120 /// ISHeuristic command line option for instruction schedulers.
122 //===---------------------------------------------------------------------===//
123 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
124 RegisterPassParser<RegisterScheduler> >
125 ISHeuristic("pre-RA-sched",
126 cl::init(&createDefaultScheduler),
127 cl::desc("Instruction schedulers available (before register"
130 static RegisterScheduler
131 defaultListDAGScheduler("default", "Best scheduler for the target",
132 createDefaultScheduler);
135 //===--------------------------------------------------------------------===//
136 /// createDefaultScheduler - This creates an instruction scheduler appropriate
138 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
139 CodeGenOpt::Level OptLevel) {
140 const TargetLowering &TLI = IS->getTargetLowering();
142 if (OptLevel == CodeGenOpt::None)
143 return createFastDAGScheduler(IS, OptLevel);
144 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
145 return createTDListDAGScheduler(IS, OptLevel);
146 assert(TLI.getSchedulingPreference() ==
147 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
148 return createBURRListDAGScheduler(IS, OptLevel);
152 // EmitInstrWithCustomInserter - This method should be implemented by targets
153 // that mark instructions with the 'usesCustomInserter' flag. These
154 // instructions are special in various ways, which require special support to
155 // insert. The specified MachineInstr is created but not inserted into any
156 // basic blocks, and this method is called to expand it into a sequence of
157 // instructions, potentially also creating new basic blocks and control flow.
158 // When new basic blocks are inserted and the edges from MBB to its successors
159 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
161 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
162 MachineBasicBlock *MBB,
163 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
165 dbgs() << "If a target marks an instruction with "
166 "'usesCustomInserter', it must implement "
167 "TargetLowering::EmitInstrWithCustomInserter!";
173 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
174 /// physical register has only a single copy use, then coalesced the copy
176 static void EmitLiveInCopy(MachineBasicBlock *MBB,
177 MachineBasicBlock::iterator &InsertPos,
178 unsigned VirtReg, unsigned PhysReg,
179 const TargetRegisterClass *RC,
180 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
181 const MachineRegisterInfo &MRI,
182 const TargetRegisterInfo &TRI,
183 const TargetInstrInfo &TII) {
184 unsigned NumUses = 0;
185 MachineInstr *UseMI = NULL;
186 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
187 UE = MRI.use_end(); UI != UE; ++UI) {
193 // If the number of uses is not one, or the use is not a move instruction,
194 // don't coalesce. Also, only coalesce away a virtual register to virtual
196 bool Coalesced = false;
197 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
199 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
200 TargetRegisterInfo::isVirtualRegister(DstReg)) {
205 // Now find an ideal location to insert the copy.
206 MachineBasicBlock::iterator Pos = InsertPos;
207 while (Pos != MBB->begin()) {
208 MachineInstr *PrevMI = prior(Pos);
209 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
210 // copyRegToReg might emit multiple instructions to do a copy.
211 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
212 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
213 // This is what the BB looks like right now:
218 // We want to insert "r1025 = mov r1". Inserting this copy below the
219 // move to r1024 makes it impossible for that move to be coalesced.
226 break; // Woot! Found a good location.
230 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
231 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
234 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
236 if (&*InsertPos == UseMI) ++InsertPos;
241 /// EmitLiveInCopies - If this is the first basic block in the function,
242 /// and if it has live ins that need to be copied into vregs, emit the
243 /// copies into the block.
244 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
245 const MachineRegisterInfo &MRI,
246 const TargetRegisterInfo &TRI,
247 const TargetInstrInfo &TII) {
248 if (SchedLiveInCopies) {
249 // Emit the copies at a heuristically-determined location in the block.
250 DenseMap<MachineInstr*, unsigned> CopyRegMap;
251 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
252 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
253 E = MRI.livein_end(); LI != E; ++LI)
255 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
256 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
257 RC, CopyRegMap, MRI, TRI, TII);
260 // Emit the copies into the top of the block.
261 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
262 E = MRI.livein_end(); LI != E; ++LI)
264 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
265 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
266 LI->second, LI->first, RC, RC);
267 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
273 //===----------------------------------------------------------------------===//
274 // SelectionDAGISel code
275 //===----------------------------------------------------------------------===//
277 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
278 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
279 FuncInfo(new FunctionLoweringInfo(TLI)),
280 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
281 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
287 SelectionDAGISel::~SelectionDAGISel() {
293 unsigned SelectionDAGISel::MakeReg(EVT VT) {
294 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
297 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
298 AU.addRequired<AliasAnalysis>();
299 AU.addPreserved<AliasAnalysis>();
300 AU.addRequired<GCModuleInfo>();
301 AU.addPreserved<GCModuleInfo>();
302 AU.addRequired<DwarfWriter>();
303 AU.addPreserved<DwarfWriter>();
304 MachineFunctionPass::getAnalysisUsage(AU);
307 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
308 Function &Fn = *mf.getFunction();
310 // Do some sanity-checking on the command-line options.
311 assert((!EnableFastISelVerbose || EnableFastISel) &&
312 "-fast-isel-verbose requires -fast-isel");
313 assert((!EnableFastISelAbort || EnableFastISel) &&
314 "-fast-isel-abort requires -fast-isel");
316 // Get alias analysis for load/store combining.
317 AA = &getAnalysis<AliasAnalysis>();
320 const TargetInstrInfo &TII = *TM.getInstrInfo();
321 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
324 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn);
327 RegInfo = &MF->getRegInfo();
328 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
330 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
331 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
332 CurDAG->init(*MF, MMI, DW);
333 FuncInfo->set(Fn, *MF, EnableFastISel);
336 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
337 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
339 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
341 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII);
343 // If the first basic block in the function has live ins that need to be
344 // copied into vregs, emit the copies into the top of the block before
345 // emitting the code for the block.
346 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
348 // Add function live-ins to entry block live-in set.
349 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
350 E = RegInfo->livein_end(); I != E; ++I)
351 MF->begin()->addLiveIn(I->first);
354 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
355 "Not all catch info was assigned to a landing pad!");
363 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
364 /// attached with this instruction.
365 static void SetDebugLoc(unsigned MDDbgKind, Instruction *I,
366 SelectionDAGBuilder *SDB,
367 FastISel *FastIS, MachineFunction *MF) {
368 if (isa<DbgInfoIntrinsic>(I)) return;
370 if (MDNode *Dbg = I->getMetadata(MDDbgKind)) {
371 DILocation DILoc(Dbg);
372 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
374 SDB->setCurDebugLoc(Loc);
377 FastIS->setCurDebugLoc(Loc);
379 // If the function doesn't have a default debug location yet, set
380 // it. This is kind of a hack.
381 if (MF->getDefaultDebugLoc().isUnknown())
382 MF->setDefaultDebugLoc(Loc);
386 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
387 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
388 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc());
390 FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc());
393 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
394 BasicBlock::iterator Begin,
395 BasicBlock::iterator End,
397 SDB->setCurrentBasicBlock(BB);
398 unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg");
400 // Lower all of the non-terminator instructions. If a call is emitted
401 // as a tail call, cease emitting nodes for this block.
402 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
403 SetDebugLoc(MDDbgKind, I, SDB, 0, MF);
405 if (!isa<TerminatorInst>(I)) {
408 // Set the current debug location back to "unknown" so that it doesn't
409 // spuriously apply to subsequent instructions.
410 ResetDebugLoc(SDB, 0);
414 if (!SDB->HasTailCall) {
415 // Ensure that all instructions which are used outside of their defining
416 // blocks are available as virtual registers. Invoke is handled elsewhere.
417 for (BasicBlock::iterator I = Begin; I != End; ++I)
418 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
419 SDB->CopyToExportRegsIfNeeded(I);
421 // Handle PHI nodes in successor blocks.
422 if (End == LLVMBB->end()) {
423 HandlePHINodesInSuccessorBlocks(LLVMBB);
425 // Lower the terminator after the copies are emitted.
426 SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF);
427 SDB->visit(*LLVMBB->getTerminator());
428 ResetDebugLoc(SDB, 0);
432 // Make sure the root of the DAG is up-to-date.
433 CurDAG->setRoot(SDB->getControlRoot());
435 // Final step, emit the lowered DAG as machine code.
437 HadTailCall = SDB->HasTailCall;
442 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
443 /// nodes from the worklist.
444 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
445 SmallVector<SDNode*, 128> &Worklist;
447 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl) : Worklist(wl) {}
449 virtual void NodeDeleted(SDNode *N, SDNode *E) {
450 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N),
454 virtual void NodeUpdated(SDNode *N) {
460 /// TrivialTruncElim - Eliminate some trivial nops that can result from
461 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
462 static bool TrivialTruncElim(SDValue Op,
463 TargetLowering::TargetLoweringOpt &TLO) {
464 SDValue N0 = Op.getOperand(0);
465 EVT VT = Op.getValueType();
466 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
467 N0.getOpcode() == ISD::SIGN_EXTEND ||
468 N0.getOpcode() == ISD::ANY_EXTEND) &&
469 N0.getOperand(0).getValueType() == VT) {
470 return TLO.CombineTo(Op, N0.getOperand(0));
475 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
476 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
477 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
478 void SelectionDAGISel::ShrinkDemandedOps() {
479 SmallVector<SDNode*, 128> Worklist;
481 // Add all the dag nodes to the worklist.
482 Worklist.reserve(CurDAG->allnodes_size());
483 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
484 E = CurDAG->allnodes_end(); I != E; ++I)
485 Worklist.push_back(I);
491 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
492 while (!Worklist.empty()) {
493 SDNode *N = Worklist.pop_back_val();
495 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
496 CurDAG->DeleteNode(N);
500 // Run ShrinkDemandedOp on scalar binary operations.
501 if (N->getNumValues() == 1 &&
502 N->getValueType(0).isSimple() && N->getValueType(0).isInteger()) {
503 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
504 APInt Demanded = APInt::getAllOnesValue(BitWidth);
505 APInt KnownZero, KnownOne;
506 if (TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
507 KnownZero, KnownOne, TLO) ||
508 (N->getOpcode() == ISD::TRUNCATE &&
509 TrivialTruncElim(SDValue(N, 0), TLO))) {
511 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N),
513 Worklist.push_back(N);
515 // Replace the old value with the new one.
516 DEBUG(errs() << "\nReplacing ";
517 TLO.Old.getNode()->dump(CurDAG);
518 errs() << "\nWith: ";
519 TLO.New.getNode()->dump(CurDAG);
522 Worklist.push_back(TLO.New.getNode());
524 SDOPsWorkListRemover DeadNodes(Worklist);
525 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
527 if (TLO.Old.getNode()->use_empty()) {
528 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
530 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
531 if (OpNode->hasOneUse()) {
532 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(),
533 OpNode), Worklist.end());
534 Worklist.push_back(OpNode);
538 Worklist.erase(std::remove(Worklist.begin(), Worklist.end(),
539 TLO.Old.getNode()), Worklist.end());
540 CurDAG->DeleteNode(TLO.Old.getNode());
547 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
548 SmallPtrSet<SDNode*, 128> VisitedNodes;
549 SmallVector<SDNode*, 128> Worklist;
551 Worklist.push_back(CurDAG->getRoot().getNode());
558 SDNode *N = Worklist.pop_back_val();
560 // If we've already seen this node, ignore it.
561 if (!VisitedNodes.insert(N))
564 // Otherwise, add all chain operands to the worklist.
565 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
566 if (N->getOperand(i).getValueType() == MVT::Other)
567 Worklist.push_back(N->getOperand(i).getNode());
569 // If this is a CopyToReg with a vreg dest, process it.
570 if (N->getOpcode() != ISD::CopyToReg)
573 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
574 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
577 // Ignore non-scalar or non-integer values.
578 SDValue Src = N->getOperand(2);
579 EVT SrcVT = Src.getValueType();
580 if (!SrcVT.isInteger() || SrcVT.isVector())
583 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
584 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
585 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
587 // Only install this information if it tells us something.
588 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
589 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
590 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
591 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
592 FunctionLoweringInfo::LiveOutInfo &LOI =
593 FuncInfo->LiveOutRegInfo[DestReg];
594 LOI.NumSignBits = NumSignBits;
595 LOI.KnownOne = KnownOne;
596 LOI.KnownZero = KnownZero;
598 } while (!Worklist.empty());
601 void SelectionDAGISel::CodeGenAndEmitDAG() {
602 std::string GroupName;
603 if (TimePassesIsEnabled)
604 GroupName = "Instruction Selection and Scheduling";
605 std::string BlockName;
606 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
607 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
609 BlockName = MF->getFunction()->getNameStr() + ":" +
610 BB->getBasicBlock()->getNameStr();
612 DEBUG(dbgs() << "Initial selection DAG:\n");
613 DEBUG(CurDAG->dump());
615 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
617 // Run the DAG combiner in pre-legalize mode.
618 if (TimePassesIsEnabled) {
619 NamedRegionTimer T("DAG Combining 1", GroupName);
620 CurDAG->Combine(Unrestricted, *AA, OptLevel);
622 CurDAG->Combine(Unrestricted, *AA, OptLevel);
625 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
626 DEBUG(CurDAG->dump());
628 // Second step, hack on the DAG until it only uses operations and types that
629 // the target supports.
630 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
634 if (TimePassesIsEnabled) {
635 NamedRegionTimer T("Type Legalization", GroupName);
636 Changed = CurDAG->LegalizeTypes();
638 Changed = CurDAG->LegalizeTypes();
641 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
642 DEBUG(CurDAG->dump());
645 if (ViewDAGCombineLT)
646 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
648 // Run the DAG combiner in post-type-legalize mode.
649 if (TimePassesIsEnabled) {
650 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
651 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
653 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
656 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
657 DEBUG(CurDAG->dump());
660 if (TimePassesIsEnabled) {
661 NamedRegionTimer T("Vector Legalization", GroupName);
662 Changed = CurDAG->LegalizeVectors();
664 Changed = CurDAG->LegalizeVectors();
668 if (TimePassesIsEnabled) {
669 NamedRegionTimer T("Type Legalization 2", GroupName);
670 CurDAG->LegalizeTypes();
672 CurDAG->LegalizeTypes();
675 if (ViewDAGCombineLT)
676 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
678 // Run the DAG combiner in post-type-legalize mode.
679 if (TimePassesIsEnabled) {
680 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
681 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
683 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
686 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
687 DEBUG(CurDAG->dump());
690 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
692 if (TimePassesIsEnabled) {
693 NamedRegionTimer T("DAG Legalization", GroupName);
694 CurDAG->Legalize(OptLevel);
696 CurDAG->Legalize(OptLevel);
699 DEBUG(dbgs() << "Legalized selection DAG:\n");
700 DEBUG(CurDAG->dump());
702 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
704 // Run the DAG combiner in post-legalize mode.
705 if (TimePassesIsEnabled) {
706 NamedRegionTimer T("DAG Combining 2", GroupName);
707 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
709 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
712 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
713 DEBUG(CurDAG->dump());
715 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
717 if (OptLevel != CodeGenOpt::None) {
719 ComputeLiveOutVRegInfo();
722 // Third, instruction select all of the operations to machine code, adding the
723 // code to the MachineBasicBlock.
724 if (TimePassesIsEnabled) {
725 NamedRegionTimer T("Instruction Selection", GroupName);
726 DoInstructionSelection();
728 DoInstructionSelection();
731 DEBUG(dbgs() << "Selected selection DAG:\n");
732 DEBUG(CurDAG->dump());
734 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
736 // Schedule machine code.
737 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
738 if (TimePassesIsEnabled) {
739 NamedRegionTimer T("Instruction Scheduling", GroupName);
740 Scheduler->Run(CurDAG, BB, BB->end());
742 Scheduler->Run(CurDAG, BB, BB->end());
745 if (ViewSUnitDAGs) Scheduler->viewGraph();
747 // Emit machine code to BB. This can change 'BB' to the last block being
749 if (TimePassesIsEnabled) {
750 NamedRegionTimer T("Instruction Creation", GroupName);
751 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
753 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
756 // Free the scheduler state.
757 if (TimePassesIsEnabled) {
758 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
764 DEBUG(dbgs() << "Selected machine code:\n");
768 void SelectionDAGISel::DoInstructionSelection() {
769 DEBUG(errs() << "===== Instruction selection begins:\n");
773 // Select target instructions for the DAG.
775 // Number all nodes with a topological order and set DAGSize.
776 DAGSize = CurDAG->AssignTopologicalOrder();
778 // Create a dummy node (which is not added to allnodes), that adds
779 // a reference to the root node, preventing it from being deleted,
780 // and tracking any changes of the root.
781 HandleSDNode Dummy(CurDAG->getRoot());
782 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
785 // The AllNodes list is now topological-sorted. Visit the
786 // nodes by starting at the end of the list (the root of the
787 // graph) and preceding back toward the beginning (the entry
789 while (ISelPosition != CurDAG->allnodes_begin()) {
790 SDNode *Node = --ISelPosition;
791 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
792 // but there are currently some corner cases that it misses. Also, this
793 // makes it theoretically possible to disable the DAGCombiner.
794 if (Node->use_empty())
797 SDNode *ResNode = Select(Node);
799 // FIXME: This is pretty gross. 'Select' should be changed to not return
800 // anything at all and this code should be nuked with a tactical strike.
802 // If node should not be replaced, continue with the next one.
803 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
807 ReplaceUses(Node, ResNode);
809 // If after the replacement this node is not used any more,
810 // remove this dead node.
811 if (Node->use_empty()) { // Don't delete EntryToken, etc.
812 ISelUpdater ISU(ISelPosition);
813 CurDAG->RemoveDeadNode(Node, &ISU);
817 CurDAG->setRoot(Dummy.getValue());
819 DEBUG(errs() << "===== Instruction selection ends:\n");
821 PostprocessISelDAG();
823 // FIXME: This shouldn't be needed, remove it.
824 CurDAG->RemoveDeadNodes();
828 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
830 MachineModuleInfo *MMI,
832 const TargetInstrInfo &TII) {
833 // Initialize the Fast-ISel state, if needed.
834 FastISel *FastIS = 0;
836 FastIS = TLI.createFastISel(MF, MMI, DW,
839 FuncInfo->StaticAllocaMap
841 , FuncInfo->CatchInfoLost
845 unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg");
847 // Iterate over all basic blocks in the function.
848 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
849 BasicBlock *LLVMBB = &*I;
850 BB = FuncInfo->MBBMap[LLVMBB];
852 BasicBlock::iterator const Begin = LLVMBB->begin();
853 BasicBlock::iterator const End = LLVMBB->end();
854 BasicBlock::iterator BI = Begin;
856 // Lower any arguments needed in this block if this is the entry block.
857 bool SuppressFastISel = false;
858 if (LLVMBB == &Fn.getEntryBlock()) {
859 LowerArguments(LLVMBB);
861 // If any of the arguments has the byval attribute, forgo
862 // fast-isel in the entry block.
865 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
867 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
868 if (EnableFastISelVerbose || EnableFastISelAbort)
869 dbgs() << "FastISel skips entry block due to byval argument\n";
870 SuppressFastISel = true;
876 if (MMI && BB->isLandingPad()) {
877 // Add a label to mark the beginning of the landing pad. Deletion of the
878 // landing pad can thus be detected via the MachineModuleInfo.
879 unsigned LabelID = MMI->addLandingPad(BB);
881 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
882 BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID);
884 // Mark exception register as live in.
885 unsigned Reg = TLI.getExceptionAddressRegister();
886 if (Reg) BB->addLiveIn(Reg);
888 // Mark exception selector register as live in.
889 Reg = TLI.getExceptionSelectorRegister();
890 if (Reg) BB->addLiveIn(Reg);
892 // FIXME: Hack around an exception handling flaw (PR1508): the personality
893 // function and list of typeids logically belong to the invoke (or, if you
894 // like, the basic block containing the invoke), and need to be associated
895 // with it in the dwarf exception handling tables. Currently however the
896 // information is provided by an intrinsic (eh.selector) that can be moved
897 // to unexpected places by the optimizers: if the unwind edge is critical,
898 // then breaking it can result in the intrinsics being in the successor of
899 // the landing pad, not the landing pad itself. This results
900 // in exceptions not being caught because no typeids are associated with
901 // the invoke. This may not be the only way things can go wrong, but it
902 // is the only way we try to work around for the moment.
903 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
905 if (Br && Br->isUnconditional()) { // Critical edge?
906 BasicBlock::iterator I, E;
907 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
908 if (isa<EHSelectorInst>(I))
912 // No catch info found - try to extract some from the successor.
913 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
917 // Before doing SelectionDAG ISel, see if FastISel has been requested.
918 if (FastIS && !SuppressFastISel) {
919 // Emit code for any incoming arguments. This must happen before
920 // beginning FastISel on the entry block.
921 if (LLVMBB == &Fn.getEntryBlock()) {
922 CurDAG->setRoot(SDB->getControlRoot());
926 FastIS->startNewBlock(BB);
927 // Do FastISel on as many instructions as possible.
928 for (; BI != End; ++BI) {
929 // Just before the terminator instruction, insert instructions to
930 // feed PHI nodes in successor blocks.
931 if (isa<TerminatorInst>(BI))
932 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
933 ResetDebugLoc(SDB, FastIS);
934 if (EnableFastISelVerbose || EnableFastISelAbort) {
935 dbgs() << "FastISel miss: ";
938 assert(!EnableFastISelAbort &&
939 "FastISel didn't handle a PHI in a successor");
943 SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF);
945 // Try to select the instruction with FastISel.
946 if (FastIS->SelectInstruction(BI)) {
947 ResetDebugLoc(SDB, FastIS);
951 // Clear out the debug location so that it doesn't carry over to
952 // unrelated instructions.
953 ResetDebugLoc(SDB, FastIS);
955 // Then handle certain instructions as single-LLVM-Instruction blocks.
956 if (isa<CallInst>(BI)) {
957 if (EnableFastISelVerbose || EnableFastISelAbort) {
958 dbgs() << "FastISel missed call: ";
962 if (!BI->getType()->isVoidTy()) {
963 unsigned &R = FuncInfo->ValueMap[BI];
965 R = FuncInfo->CreateRegForValue(BI);
968 bool HadTailCall = false;
969 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
971 // If the call was emitted as a tail call, we're done with the block.
977 // If the instruction was codegen'd with multiple blocks,
978 // inform the FastISel object where to resume inserting.
979 FastIS->setCurrentBlock(BB);
983 // Otherwise, give up on FastISel for the rest of the block.
984 // For now, be a little lenient about non-branch terminators.
985 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
986 if (EnableFastISelVerbose || EnableFastISelAbort) {
987 dbgs() << "FastISel miss: ";
990 if (EnableFastISelAbort)
991 // The "fast" selector couldn't handle something and bailed.
992 // For the purpose of debugging, just abort.
993 llvm_unreachable("FastISel didn't select the entire block");
999 // Run SelectionDAG instruction selection on the remainder of the block
1000 // not handled by FastISel. If FastISel is not run, this is the entire
1004 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
1014 SelectionDAGISel::FinishBasicBlock() {
1016 DEBUG(dbgs() << "Target-post-processed machine code:\n");
1019 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1020 << SDB->PHINodesToUpdate.size() << "\n");
1021 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
1022 dbgs() << "Node " << i << " : ("
1023 << SDB->PHINodesToUpdate[i].first
1024 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
1026 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1027 // PHI nodes in successors.
1028 if (SDB->SwitchCases.empty() &&
1029 SDB->JTCases.empty() &&
1030 SDB->BitTestCases.empty()) {
1031 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1032 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1033 assert(PHI->isPHI() &&
1034 "This is not a machine PHI node that we are updating!");
1035 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1037 PHI->addOperand(MachineOperand::CreateMBB(BB));
1039 SDB->PHINodesToUpdate.clear();
1043 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1044 // Lower header first, if it wasn't already lowered
1045 if (!SDB->BitTestCases[i].Emitted) {
1046 // Set the current basic block to the mbb we wish to insert the code into
1047 BB = SDB->BitTestCases[i].Parent;
1048 SDB->setCurrentBasicBlock(BB);
1050 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
1051 CurDAG->setRoot(SDB->getRoot());
1052 CodeGenAndEmitDAG();
1056 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1057 // Set the current basic block to the mbb we wish to insert the code into
1058 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
1059 SDB->setCurrentBasicBlock(BB);
1062 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
1063 SDB->BitTestCases[i].Reg,
1064 SDB->BitTestCases[i].Cases[j]);
1066 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
1067 SDB->BitTestCases[i].Reg,
1068 SDB->BitTestCases[i].Cases[j]);
1071 CurDAG->setRoot(SDB->getRoot());
1072 CodeGenAndEmitDAG();
1077 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1078 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1079 MachineBasicBlock *PHIBB = PHI->getParent();
1080 assert(PHI->isPHI() &&
1081 "This is not a machine PHI node that we are updating!");
1082 // This is "default" BB. We have two jumps to it. From "header" BB and
1083 // from last "case" BB.
1084 if (PHIBB == SDB->BitTestCases[i].Default) {
1085 PHI->addOperand(MachineOperand::
1086 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1087 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1088 PHI->addOperand(MachineOperand::
1089 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1090 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1093 // One of "cases" BB.
1094 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1096 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1097 if (cBB->isSuccessor(PHIBB)) {
1098 PHI->addOperand(MachineOperand::
1099 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1100 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1105 SDB->BitTestCases.clear();
1107 // If the JumpTable record is filled in, then we need to emit a jump table.
1108 // Updating the PHI nodes is tricky in this case, since we need to determine
1109 // whether the PHI is a successor of the range check MBB or the jump table MBB
1110 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1111 // Lower header first, if it wasn't already lowered
1112 if (!SDB->JTCases[i].first.Emitted) {
1113 // Set the current basic block to the mbb we wish to insert the code into
1114 BB = SDB->JTCases[i].first.HeaderBB;
1115 SDB->setCurrentBasicBlock(BB);
1117 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
1118 CurDAG->setRoot(SDB->getRoot());
1119 CodeGenAndEmitDAG();
1123 // Set the current basic block to the mbb we wish to insert the code into
1124 BB = SDB->JTCases[i].second.MBB;
1125 SDB->setCurrentBasicBlock(BB);
1127 SDB->visitJumpTable(SDB->JTCases[i].second);
1128 CurDAG->setRoot(SDB->getRoot());
1129 CodeGenAndEmitDAG();
1133 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1134 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1135 MachineBasicBlock *PHIBB = PHI->getParent();
1136 assert(PHI->isPHI() &&
1137 "This is not a machine PHI node that we are updating!");
1138 // "default" BB. We can go there only from header BB.
1139 if (PHIBB == SDB->JTCases[i].second.Default) {
1141 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1143 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1145 // JT BB. Just iterate over successors here
1146 if (BB->isSuccessor(PHIBB)) {
1148 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1149 PHI->addOperand(MachineOperand::CreateMBB(BB));
1153 SDB->JTCases.clear();
1155 // If the switch block involved a branch to one of the actual successors, we
1156 // need to update PHI nodes in that block.
1157 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1158 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1159 assert(PHI->isPHI() &&
1160 "This is not a machine PHI node that we are updating!");
1161 if (BB->isSuccessor(PHI->getParent())) {
1162 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1164 PHI->addOperand(MachineOperand::CreateMBB(BB));
1168 // If we generated any switch lowering information, build and codegen any
1169 // additional DAGs necessary.
1170 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1171 // Set the current basic block to the mbb we wish to insert the code into
1172 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1173 SDB->setCurrentBasicBlock(BB);
1176 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1177 CurDAG->setRoot(SDB->getRoot());
1178 CodeGenAndEmitDAG();
1180 // Handle any PHI nodes in successors of this chunk, as if we were coming
1181 // from the original BB before switch expansion. Note that PHI nodes can
1182 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1183 // handle them the right number of times.
1184 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1185 // If new BB's are created during scheduling, the edges may have been
1186 // updated. That is, the edge from ThisBB to BB may have been split and
1187 // BB's predecessor is now another block.
1188 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1189 SDB->EdgeMapping.find(BB);
1190 if (EI != SDB->EdgeMapping.end())
1191 ThisBB = EI->second;
1193 // BB may have been removed from the CFG if a branch was constant folded.
1194 if (ThisBB->isSuccessor(BB)) {
1195 for (MachineBasicBlock::iterator Phi = BB->begin();
1196 Phi != BB->end() && Phi->isPHI();
1198 // This value for this PHI node is recorded in PHINodesToUpdate.
1199 for (unsigned pn = 0; ; ++pn) {
1200 assert(pn != SDB->PHINodesToUpdate.size() &&
1201 "Didn't find PHI entry!");
1202 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1203 Phi->addOperand(MachineOperand::
1204 CreateReg(SDB->PHINodesToUpdate[pn].second,
1206 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1213 // Don't process RHS if same block as LHS.
1214 if (BB == SDB->SwitchCases[i].FalseBB)
1215 SDB->SwitchCases[i].FalseBB = 0;
1217 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1218 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1219 SDB->SwitchCases[i].FalseBB = 0;
1221 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1224 SDB->SwitchCases.clear();
1226 SDB->PHINodesToUpdate.clear();
1230 /// Create the scheduler. If a specific scheduler was specified
1231 /// via the SchedulerRegistry, use it, otherwise select the
1232 /// one preferred by the target.
1234 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1235 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1239 RegisterScheduler::setDefault(Ctor);
1242 return Ctor(this, OptLevel);
1245 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1246 return new ScheduleHazardRecognizer();
1249 //===----------------------------------------------------------------------===//
1250 // Helper functions used by the generated instruction selector.
1251 //===----------------------------------------------------------------------===//
1252 // Calls to these methods are generated by tblgen.
1254 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1255 /// the dag combiner simplified the 255, we still want to match. RHS is the
1256 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1257 /// specified in the .td file (e.g. 255).
1258 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1259 int64_t DesiredMaskS) const {
1260 const APInt &ActualMask = RHS->getAPIntValue();
1261 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1263 // If the actual mask exactly matches, success!
1264 if (ActualMask == DesiredMask)
1267 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1268 if (ActualMask.intersects(~DesiredMask))
1271 // Otherwise, the DAG Combiner may have proven that the value coming in is
1272 // either already zero or is not demanded. Check for known zero input bits.
1273 APInt NeededMask = DesiredMask & ~ActualMask;
1274 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1277 // TODO: check to see if missing bits are just not demanded.
1279 // Otherwise, this pattern doesn't match.
1283 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1284 /// the dag combiner simplified the 255, we still want to match. RHS is the
1285 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1286 /// specified in the .td file (e.g. 255).
1287 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1288 int64_t DesiredMaskS) const {
1289 const APInt &ActualMask = RHS->getAPIntValue();
1290 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1292 // If the actual mask exactly matches, success!
1293 if (ActualMask == DesiredMask)
1296 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1297 if (ActualMask.intersects(~DesiredMask))
1300 // Otherwise, the DAG Combiner may have proven that the value coming in is
1301 // either already zero or is not demanded. Check for known zero input bits.
1302 APInt NeededMask = DesiredMask & ~ActualMask;
1304 APInt KnownZero, KnownOne;
1305 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1307 // If all the missing bits in the or are already known to be set, match!
1308 if ((NeededMask & KnownOne) == NeededMask)
1311 // TODO: check to see if missing bits are just not demanded.
1313 // Otherwise, this pattern doesn't match.
1318 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1319 /// by tblgen. Others should not call it.
1320 void SelectionDAGISel::
1321 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1322 std::vector<SDValue> InOps;
1323 std::swap(InOps, Ops);
1325 Ops.push_back(InOps[0]); // input chain.
1326 Ops.push_back(InOps[1]); // input asm string.
1328 unsigned i = 2, e = InOps.size();
1329 if (InOps[e-1].getValueType() == MVT::Flag)
1330 --e; // Don't process a flag operand if it is here.
1333 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1334 if ((Flags & 7) != 4 /*MEM*/) {
1335 // Just skip over this operand, copying the operands verbatim.
1336 Ops.insert(Ops.end(), InOps.begin()+i,
1337 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1338 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1340 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1341 "Memory operand with multiple values?");
1342 // Otherwise, this is a memory operand. Ask the target to select it.
1343 std::vector<SDValue> SelOps;
1344 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
1345 llvm_report_error("Could not match memory address. Inline asm"
1349 // Add this to the output node.
1350 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
1352 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1357 // Add the flag input back if present.
1358 if (e != InOps.size())
1359 Ops.push_back(InOps.back());
1362 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1365 static SDNode *findFlagUse(SDNode *N) {
1366 unsigned FlagResNo = N->getNumValues()-1;
1367 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1368 SDUse &Use = I.getUse();
1369 if (Use.getResNo() == FlagResNo)
1370 return Use.getUser();
1375 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1376 /// This function recursively traverses up the operand chain, ignoring
1378 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1379 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1380 bool IgnoreChains) {
1381 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1382 // greater than all of its (recursive) operands. If we scan to a point where
1383 // 'use' is smaller than the node we're scanning for, then we know we will
1386 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1387 // happen because we scan down to newly selected nodes in the case of flag
1389 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1392 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1393 // won't fail if we scan it again.
1394 if (!Visited.insert(Use))
1397 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1398 // Ignore chain uses, they are validated by HandleMergeInputChains.
1399 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1402 SDNode *N = Use->getOperand(i).getNode();
1404 if (Use == ImmedUse || Use == Root)
1405 continue; // We are not looking for immediate use.
1410 // Traverse up the operand chain.
1411 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1417 /// isNonImmUse - Start searching from Root up the DAG to check is Def can
1418 /// be reached. Return true if that's the case. However, ignore direct uses
1419 /// by ImmedUse (which would be U in the example illustrated in
1420 /// IsLegalToFold) and by Root (which can happen in the store case).
1421 /// FIXME: to be really generic, we should allow direct use by any node
1422 /// that is being folded. But realisticly since we only fold loads which
1423 /// have one non-chain use, we only need to watch out for load/op/store
1424 /// and load/op/cmp case where the root (store / cmp) may reach the load via
1425 /// its chain operand.
1426 static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse,
1427 bool IgnoreChains) {
1428 SmallPtrSet<SDNode*, 16> Visited;
1429 return findNonImmUse(Root, Def, ImmedUse, Root, Visited, IgnoreChains);
1432 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1433 /// operand node N of U during instruction selection that starts at Root.
1434 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1435 SDNode *Root) const {
1436 if (OptLevel == CodeGenOpt::None) return false;
1437 return N.hasOneUse();
1440 /// IsLegalToFold - Returns true if the specific operand node N of
1441 /// U can be folded during instruction selection that starts at Root.
1442 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1443 bool IgnoreChains) const {
1444 if (OptLevel == CodeGenOpt::None) return false;
1446 // If Root use can somehow reach N through a path that that doesn't contain
1447 // U then folding N would create a cycle. e.g. In the following
1448 // diagram, Root can reach N through X. If N is folded into into Root, then
1449 // X is both a predecessor and a successor of U.
1460 // * indicates nodes to be folded together.
1462 // If Root produces a flag, then it gets (even more) interesting. Since it
1463 // will be "glued" together with its flag use in the scheduler, we need to
1464 // check if it might reach N.
1483 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1484 // (call it Fold), then X is a predecessor of FU and a successor of
1485 // Fold. But since Fold and FU are flagged together, this will create
1486 // a cycle in the scheduling graph.
1488 EVT VT = Root->getValueType(Root->getNumValues()-1);
1489 while (VT == MVT::Flag) {
1490 SDNode *FU = findFlagUse(Root);
1494 VT = Root->getValueType(Root->getNumValues()-1);
1497 return !isNonImmUse(Root, N.getNode(), U, IgnoreChains);
1500 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1501 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1502 SelectInlineAsmMemoryOperands(Ops);
1504 std::vector<EVT> VTs;
1505 VTs.push_back(MVT::Other);
1506 VTs.push_back(MVT::Flag);
1507 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1508 VTs, &Ops[0], Ops.size());
1510 return New.getNode();
1513 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1514 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1517 SDNode *SelectionDAGISel::Select_EH_LABEL(SDNode *N) {
1518 SDValue Chain = N->getOperand(0);
1519 unsigned C = cast<LabelSDNode>(N)->getLabelID();
1520 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);
1521 return CurDAG->SelectNodeTo(N, TargetOpcode::EH_LABEL,
1522 MVT::Other, Tmp, Chain);
1525 /// GetVBR - decode a vbr encoding whose top bit is set.
1526 ALWAYS_INLINE static uint64_t
1527 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1528 assert(Val >= 128 && "Not a VBR");
1529 Val &= 127; // Remove first vbr bit.
1534 NextBits = MatcherTable[Idx++];
1535 Val |= (NextBits&127) << Shift;
1537 } while (NextBits & 128);
1543 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1544 /// interior flag and chain results to use the new flag and chain results.
1545 void SelectionDAGISel::
1546 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1547 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1549 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1550 bool isMorphNodeTo) {
1551 SmallVector<SDNode*, 4> NowDeadNodes;
1553 ISelUpdater ISU(ISelPosition);
1555 // Now that all the normal results are replaced, we replace the chain and
1556 // flag results if present.
1557 if (!ChainNodesMatched.empty()) {
1558 assert(InputChain.getNode() != 0 &&
1559 "Matched input chains but didn't produce a chain");
1560 // Loop over all of the nodes we matched that produced a chain result.
1561 // Replace all the chain results with the final chain we ended up with.
1562 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1563 SDNode *ChainNode = ChainNodesMatched[i];
1565 // If this node was already deleted, don't look at it.
1566 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1569 // Don't replace the results of the root node if we're doing a
1571 if (ChainNode == NodeToMatch && isMorphNodeTo)
1574 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1575 if (ChainVal.getValueType() == MVT::Flag)
1576 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1577 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1578 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1580 // If the node became dead, delete it.
1581 if (ChainNode->use_empty())
1582 NowDeadNodes.push_back(ChainNode);
1586 // If the result produces a flag, update any flag results in the matched
1587 // pattern with the flag result.
1588 if (InputFlag.getNode() != 0) {
1589 // Handle any interior nodes explicitly marked.
1590 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1591 SDNode *FRN = FlagResultNodesMatched[i];
1593 // If this node was already deleted, don't look at it.
1594 if (FRN->getOpcode() == ISD::DELETED_NODE)
1597 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1598 "Doesn't have a flag result");
1599 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1602 // If the node became dead, delete it.
1603 if (FRN->use_empty())
1604 NowDeadNodes.push_back(FRN);
1608 if (!NowDeadNodes.empty())
1609 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1611 DEBUG(errs() << "ISEL: Match complete!\n");
1617 CR_LeadsToInteriorNode
1620 /// WalkChainUsers - Walk down the users of the specified chained node that is
1621 /// part of the pattern we're matching, looking at all of the users we find.
1622 /// This determines whether something is an interior node, whether we have a
1623 /// non-pattern node in between two pattern nodes (which prevent folding because
1624 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1625 /// between pattern nodes (in which case the TF becomes part of the pattern).
1627 /// The walk we do here is guaranteed to be small because we quickly get down to
1628 /// already selected nodes "below" us.
1630 WalkChainUsers(SDNode *ChainedNode,
1631 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1632 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1633 ChainResult Result = CR_Simple;
1635 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1636 E = ChainedNode->use_end(); UI != E; ++UI) {
1637 // Make sure the use is of the chain, not some other value we produce.
1638 if (UI.getUse().getValueType() != MVT::Other) continue;
1642 // If we see an already-selected machine node, then we've gone beyond the
1643 // pattern that we're selecting down into the already selected chunk of the
1645 if (User->isMachineOpcode() ||
1646 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1649 if (User->getOpcode() == ISD::CopyToReg ||
1650 User->getOpcode() == ISD::CopyFromReg ||
1651 User->getOpcode() == ISD::INLINEASM) {
1652 // If their node ID got reset to -1 then they've already been selected.
1653 // Treat them like a MachineOpcode.
1654 if (User->getNodeId() == -1)
1658 // If we have a TokenFactor, we handle it specially.
1659 if (User->getOpcode() != ISD::TokenFactor) {
1660 // If the node isn't a token factor and isn't part of our pattern, then it
1661 // must be a random chained node in between two nodes we're selecting.
1662 // This happens when we have something like:
1667 // Because we structurally match the load/store as a read/modify/write,
1668 // but the call is chained between them. We cannot fold in this case
1669 // because it would induce a cycle in the graph.
1670 if (!std::count(ChainedNodesInPattern.begin(),
1671 ChainedNodesInPattern.end(), User))
1672 return CR_InducesCycle;
1674 // Otherwise we found a node that is part of our pattern. For example in:
1678 // This would happen when we're scanning down from the load and see the
1679 // store as a user. Record that there is a use of ChainedNode that is
1680 // part of the pattern and keep scanning uses.
1681 Result = CR_LeadsToInteriorNode;
1682 InteriorChainedNodes.push_back(User);
1686 // If we found a TokenFactor, there are two cases to consider: first if the
1687 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1688 // uses of the TF are in our pattern) we just want to ignore it. Second,
1689 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1695 // | \ DAG's like cheese
1698 // [TokenFactor] [Op]
1705 // In this case, the TokenFactor becomes part of our match and we rewrite it
1706 // as a new TokenFactor.
1708 // To distinguish these two cases, do a recursive walk down the uses.
1709 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1711 // If the uses of the TokenFactor are just already-selected nodes, ignore
1712 // it, it is "below" our pattern.
1714 case CR_InducesCycle:
1715 // If the uses of the TokenFactor lead to nodes that are not part of our
1716 // pattern that are not selected, folding would turn this into a cycle,
1718 return CR_InducesCycle;
1719 case CR_LeadsToInteriorNode:
1720 break; // Otherwise, keep processing.
1723 // Okay, we know we're in the interesting interior case. The TokenFactor
1724 // is now going to be considered part of the pattern so that we rewrite its
1725 // uses (it may have uses that are not part of the pattern) with the
1726 // ultimate chain result of the generated code. We will also add its chain
1727 // inputs as inputs to the ultimate TokenFactor we create.
1728 Result = CR_LeadsToInteriorNode;
1729 ChainedNodesInPattern.push_back(User);
1730 InteriorChainedNodes.push_back(User);
1737 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1738 /// operation for when the pattern matched at least one node with a chains. The
1739 /// input vector contains a list of all of the chained nodes that we match. We
1740 /// must determine if this is a valid thing to cover (i.e. matching it won't
1741 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1742 /// be used as the input node chain for the generated nodes.
1744 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1745 SelectionDAG *CurDAG) {
1746 // Walk all of the chained nodes we've matched, recursively scanning down the
1747 // users of the chain result. This adds any TokenFactor nodes that are caught
1748 // in between chained nodes to the chained and interior nodes list.
1749 SmallVector<SDNode*, 3> InteriorChainedNodes;
1750 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1751 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1752 InteriorChainedNodes) == CR_InducesCycle)
1753 return SDValue(); // Would induce a cycle.
1756 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1757 // that we are interested in. Form our input TokenFactor node.
1758 SmallVector<SDValue, 3> InputChains;
1759 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1760 // Add the input chain of this node to the InputChains list (which will be
1761 // the operands of the generated TokenFactor) if it's not an interior node.
1762 SDNode *N = ChainNodesMatched[i];
1763 if (N->getOpcode() != ISD::TokenFactor) {
1764 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1767 // Otherwise, add the input chain.
1768 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1769 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1770 InputChains.push_back(InChain);
1774 // If we have a token factor, we want to add all inputs of the token factor
1775 // that are not part of the pattern we're matching.
1776 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1777 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1778 N->getOperand(op).getNode()))
1779 InputChains.push_back(N->getOperand(op));
1784 if (InputChains.size() == 1)
1785 return InputChains[0];
1786 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1787 MVT::Other, &InputChains[0], InputChains.size());
1790 /// MorphNode - Handle morphing a node in place for the selector.
1791 SDNode *SelectionDAGISel::
1792 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1793 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1794 // It is possible we're using MorphNodeTo to replace a node with no
1795 // normal results with one that has a normal result (or we could be
1796 // adding a chain) and the input could have flags and chains as well.
1797 // In this case we need to shifting the operands down.
1798 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1799 // than the old isel though. We should sink this into MorphNodeTo.
1800 int OldFlagResultNo = -1, OldChainResultNo = -1;
1802 unsigned NTMNumResults = Node->getNumValues();
1803 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1804 OldFlagResultNo = NTMNumResults-1;
1805 if (NTMNumResults != 1 &&
1806 Node->getValueType(NTMNumResults-2) == MVT::Other)
1807 OldChainResultNo = NTMNumResults-2;
1808 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1809 OldChainResultNo = NTMNumResults-1;
1811 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1812 // that this deletes operands of the old node that become dead.
1813 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1815 // MorphNodeTo can operate in two ways: if an existing node with the
1816 // specified operands exists, it can just return it. Otherwise, it
1817 // updates the node in place to have the requested operands.
1819 // If we updated the node in place, reset the node ID. To the isel,
1820 // this should be just like a newly allocated machine node.
1824 unsigned ResNumResults = Res->getNumValues();
1825 // Move the flag if needed.
1826 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1827 (unsigned)OldFlagResultNo != ResNumResults-1)
1828 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1829 SDValue(Res, ResNumResults-1));
1831 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1834 // Move the chain reference if needed.
1835 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1836 (unsigned)OldChainResultNo != ResNumResults-1)
1837 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1838 SDValue(Res, ResNumResults-1));
1840 // Otherwise, no replacement happened because the node already exists. Replace
1841 // Uses of the old node with the new one.
1843 CurDAG->ReplaceAllUsesWith(Node, Res);
1850 /// FailIndex - If this match fails, this is the index to continue with.
1853 /// NodeStack - The node stack when the scope was formed.
1854 SmallVector<SDValue, 4> NodeStack;
1856 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1857 unsigned NumRecordedNodes;
1859 /// NumMatchedMemRefs - The number of matched memref entries.
1860 unsigned NumMatchedMemRefs;
1862 /// InputChain/InputFlag - The current chain/flag
1863 SDValue InputChain, InputFlag;
1865 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1866 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1869 SDNode *SelectionDAGISel::
1870 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1871 unsigned TableSize) {
1872 // FIXME: Should these even be selected? Handle these cases in the caller?
1873 switch (NodeToMatch->getOpcode()) {
1876 case ISD::EntryToken: // These nodes remain the same.
1877 case ISD::BasicBlock:
1879 case ISD::HANDLENODE:
1880 case ISD::TargetConstant:
1881 case ISD::TargetConstantFP:
1882 case ISD::TargetConstantPool:
1883 case ISD::TargetFrameIndex:
1884 case ISD::TargetExternalSymbol:
1885 case ISD::TargetBlockAddress:
1886 case ISD::TargetJumpTable:
1887 case ISD::TargetGlobalTLSAddress:
1888 case ISD::TargetGlobalAddress:
1889 case ISD::TokenFactor:
1890 case ISD::CopyFromReg:
1891 case ISD::CopyToReg:
1892 NodeToMatch->setNodeId(-1); // Mark selected.
1894 case ISD::AssertSext:
1895 case ISD::AssertZext:
1896 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1897 NodeToMatch->getOperand(0));
1899 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1900 case ISD::EH_LABEL: return Select_EH_LABEL(NodeToMatch);
1901 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1904 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1906 // Set up the node stack with NodeToMatch as the only node on the stack.
1907 SmallVector<SDValue, 8> NodeStack;
1908 SDValue N = SDValue(NodeToMatch, 0);
1909 NodeStack.push_back(N);
1911 // MatchScopes - Scopes used when matching, if a match failure happens, this
1912 // indicates where to continue checking.
1913 SmallVector<MatchScope, 8> MatchScopes;
1915 // RecordedNodes - This is the set of nodes that have been recorded by the
1917 SmallVector<SDValue, 8> RecordedNodes;
1919 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1921 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1923 // These are the current input chain and flag for use when generating nodes.
1924 // Various Emit operations change these. For example, emitting a copytoreg
1925 // uses and updates these.
1926 SDValue InputChain, InputFlag;
1928 // ChainNodesMatched - If a pattern matches nodes that have input/output
1929 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1930 // which ones they are. The result is captured into this list so that we can
1931 // update the chain results when the pattern is complete.
1932 SmallVector<SDNode*, 3> ChainNodesMatched;
1933 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1935 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1936 NodeToMatch->dump(CurDAG);
1939 // Determine where to start the interpreter. Normally we start at opcode #0,
1940 // but if the state machine starts with an OPC_SwitchOpcode, then we
1941 // accelerate the first lookup (which is guaranteed to be hot) with the
1942 // OpcodeOffset table.
1943 unsigned MatcherIndex = 0;
1945 if (!OpcodeOffset.empty()) {
1946 // Already computed the OpcodeOffset table, just index into it.
1947 if (N.getOpcode() < OpcodeOffset.size())
1948 MatcherIndex = OpcodeOffset[N.getOpcode()];
1949 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1951 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1952 // Otherwise, the table isn't computed, but the state machine does start
1953 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1954 // is the first time we're selecting an instruction.
1957 // Get the size of this case.
1958 unsigned CaseSize = MatcherTable[Idx++];
1960 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1961 if (CaseSize == 0) break;
1963 // Get the opcode, add the index to the table.
1964 unsigned Opc = MatcherTable[Idx++];
1965 if (Opc >= OpcodeOffset.size())
1966 OpcodeOffset.resize((Opc+1)*2);
1967 OpcodeOffset[Opc] = Idx;
1971 // Okay, do the lookup for the first opcode.
1972 if (N.getOpcode() < OpcodeOffset.size())
1973 MatcherIndex = OpcodeOffset[N.getOpcode()];
1977 assert(MatcherIndex < TableSize && "Invalid index");
1978 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1981 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1982 if (NumToSkip & 128)
1983 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1984 assert(NumToSkip != 0 &&
1985 "First entry of OPC_Scope shouldn't be 0, scope has no children?");
1987 // Push a MatchScope which indicates where to go if the first child fails
1989 MatchScope NewEntry;
1990 NewEntry.FailIndex = MatcherIndex+NumToSkip;
1991 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
1992 NewEntry.NumRecordedNodes = RecordedNodes.size();
1993 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
1994 NewEntry.InputChain = InputChain;
1995 NewEntry.InputFlag = InputFlag;
1996 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
1997 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
1998 MatchScopes.push_back(NewEntry);
2001 case OPC_RecordNode:
2002 // Remember this node, it may end up being an operand in the pattern.
2003 RecordedNodes.push_back(N);
2006 case OPC_RecordChild0: case OPC_RecordChild1:
2007 case OPC_RecordChild2: case OPC_RecordChild3:
2008 case OPC_RecordChild4: case OPC_RecordChild5:
2009 case OPC_RecordChild6: case OPC_RecordChild7: {
2010 unsigned ChildNo = Opcode-OPC_RecordChild0;
2011 if (ChildNo >= N.getNumOperands())
2012 break; // Match fails if out of range child #.
2014 RecordedNodes.push_back(N->getOperand(ChildNo));
2017 case OPC_RecordMemRef:
2018 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2021 case OPC_CaptureFlagInput:
2022 // If the current node has an input flag, capture it in InputFlag.
2023 if (N->getNumOperands() != 0 &&
2024 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2025 InputFlag = N->getOperand(N->getNumOperands()-1);
2028 case OPC_MoveChild: {
2029 unsigned ChildNo = MatcherTable[MatcherIndex++];
2030 if (ChildNo >= N.getNumOperands())
2031 break; // Match fails if out of range child #.
2032 N = N.getOperand(ChildNo);
2033 NodeStack.push_back(N);
2037 case OPC_MoveParent:
2038 // Pop the current node off the NodeStack.
2039 NodeStack.pop_back();
2040 assert(!NodeStack.empty() && "Node stack imbalance!");
2041 N = NodeStack.back();
2044 case OPC_CheckSame: {
2045 // Accept if it is exactly the same as a previously recorded node.
2046 unsigned RecNo = MatcherTable[MatcherIndex++];
2047 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2048 if (N != RecordedNodes[RecNo]) break;
2051 case OPC_CheckPatternPredicate:
2052 if (!CheckPatternPredicate(MatcherTable[MatcherIndex++])) break;
2054 case OPC_CheckPredicate:
2055 if (!CheckNodePredicate(N.getNode(), MatcherTable[MatcherIndex++])) break;
2057 case OPC_CheckComplexPat:
2058 if (!CheckComplexPattern(NodeToMatch, N,
2059 MatcherTable[MatcherIndex++], RecordedNodes))
2062 case OPC_CheckOpcode:
2063 if (N->getOpcode() != MatcherTable[MatcherIndex++]) break;
2066 case OPC_SwitchOpcode: {
2067 unsigned CurNodeOpcode = N.getOpcode();
2068 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2071 // Get the size of this case.
2072 CaseSize = MatcherTable[MatcherIndex++];
2074 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2075 if (CaseSize == 0) break;
2077 // If the opcode matches, then we will execute this case.
2078 if (CurNodeOpcode == MatcherTable[MatcherIndex++])
2081 // Otherwise, skip over this case.
2082 MatcherIndex += CaseSize;
2085 // If no cases matched, bail out.
2086 if (CaseSize == 0) break;
2088 // Otherwise, execute the case we found.
2089 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2090 << " to " << MatcherIndex << "\n");
2094 case OPC_CheckType: {
2095 MVT::SimpleValueType VT =
2096 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2097 if (N.getValueType() != VT) {
2098 // Handle the case when VT is iPTR.
2099 if (VT != MVT::iPTR || N.getValueType() != TLI.getPointerTy())
2105 case OPC_SwitchType: {
2106 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2107 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2110 // Get the size of this case.
2111 CaseSize = MatcherTable[MatcherIndex++];
2113 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2114 if (CaseSize == 0) break;
2116 MVT::SimpleValueType CaseVT =
2117 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2118 if (CaseVT == MVT::iPTR)
2119 CaseVT = TLI.getPointerTy().SimpleTy;
2121 // If the VT matches, then we will execute this case.
2122 if (CurNodeVT == CaseVT)
2125 // Otherwise, skip over this case.
2126 MatcherIndex += CaseSize;
2129 // If no cases matched, bail out.
2130 if (CaseSize == 0) break;
2132 // Otherwise, execute the case we found.
2133 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2134 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2137 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2138 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2139 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2140 case OPC_CheckChild6Type: case OPC_CheckChild7Type: {
2141 unsigned ChildNo = Opcode-OPC_CheckChild0Type;
2142 if (ChildNo >= N.getNumOperands())
2143 break; // Match fails if out of range child #.
2145 MVT::SimpleValueType VT =
2146 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2147 EVT ChildVT = N.getOperand(ChildNo).getValueType();
2148 if (ChildVT != VT) {
2149 // Handle the case when VT is iPTR.
2150 if (VT != MVT::iPTR || ChildVT != TLI.getPointerTy())
2155 case OPC_CheckCondCode:
2156 if (cast<CondCodeSDNode>(N)->get() !=
2157 (ISD::CondCode)MatcherTable[MatcherIndex++]) break;
2159 case OPC_CheckValueType: {
2160 MVT::SimpleValueType VT =
2161 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2162 if (cast<VTSDNode>(N)->getVT() != VT) {
2163 // Handle the case when VT is iPTR.
2164 if (VT != MVT::iPTR || cast<VTSDNode>(N)->getVT() != TLI.getPointerTy())
2169 case OPC_CheckInteger: {
2170 int64_t Val = MatcherTable[MatcherIndex++];
2172 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2174 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2175 if (C == 0 || C->getSExtValue() != Val)
2179 case OPC_CheckAndImm: {
2180 int64_t Val = MatcherTable[MatcherIndex++];
2182 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2184 if (N->getOpcode() != ISD::AND) break;
2185 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2186 if (C == 0 || !CheckAndMask(N.getOperand(0), C, Val))
2190 case OPC_CheckOrImm: {
2191 int64_t Val = MatcherTable[MatcherIndex++];
2193 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2195 if (N->getOpcode() != ISD::OR) break;
2197 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2198 if (C == 0 || !CheckOrMask(N.getOperand(0), C, Val))
2203 case OPC_CheckFoldableChainNode: {
2204 assert(NodeStack.size() != 1 && "No parent node");
2205 // Verify that all intermediate nodes between the root and this one have
2207 bool HasMultipleUses = false;
2208 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2209 if (!NodeStack[i].hasOneUse()) {
2210 HasMultipleUses = true;
2213 if (HasMultipleUses) break;
2215 // Check to see that the target thinks this is profitable to fold and that
2216 // we can fold it without inducing cycles in the graph.
2217 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2219 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2220 NodeToMatch, true/*We validate our own chains*/))
2225 case OPC_EmitInteger: {
2226 MVT::SimpleValueType VT =
2227 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2228 int64_t Val = MatcherTable[MatcherIndex++];
2230 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2231 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2234 case OPC_EmitRegister: {
2235 MVT::SimpleValueType VT =
2236 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2237 unsigned RegNo = MatcherTable[MatcherIndex++];
2238 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2242 case OPC_EmitConvertToTarget: {
2243 // Convert from IMM/FPIMM to target version.
2244 unsigned RecNo = MatcherTable[MatcherIndex++];
2245 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2246 SDValue Imm = RecordedNodes[RecNo];
2248 if (Imm->getOpcode() == ISD::Constant) {
2249 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2250 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2251 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2252 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2253 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2256 RecordedNodes.push_back(Imm);
2260 case OPC_EmitMergeInputChains: {
2261 assert(InputChain.getNode() == 0 &&
2262 "EmitMergeInputChains should be the first chain producing node");
2263 // This node gets a list of nodes we matched in the input that have
2264 // chains. We want to token factor all of the input chains to these nodes
2265 // together. However, if any of the input chains is actually one of the
2266 // nodes matched in this pattern, then we have an intra-match reference.
2267 // Ignore these because the newly token factored chain should not refer to
2269 unsigned NumChains = MatcherTable[MatcherIndex++];
2270 assert(NumChains != 0 && "Can't TF zero chains");
2272 assert(ChainNodesMatched.empty() &&
2273 "Should only have one EmitMergeInputChains per match");
2275 // Read all of the chained nodes.
2276 for (unsigned i = 0; i != NumChains; ++i) {
2277 unsigned RecNo = MatcherTable[MatcherIndex++];
2278 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2279 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2281 // FIXME: What if other value results of the node have uses not matched
2283 if (ChainNodesMatched.back() != NodeToMatch &&
2284 !RecordedNodes[RecNo].hasOneUse()) {
2285 ChainNodesMatched.clear();
2290 // If the inner loop broke out, the match fails.
2291 if (ChainNodesMatched.empty())
2294 // Merge the input chains if they are not intra-pattern references.
2295 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2297 if (InputChain.getNode() == 0)
2298 break; // Failed to merge.
2303 case OPC_EmitCopyToReg: {
2304 unsigned RecNo = MatcherTable[MatcherIndex++];
2305 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2306 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2308 if (InputChain.getNode() == 0)
2309 InputChain = CurDAG->getEntryNode();
2311 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2312 DestPhysReg, RecordedNodes[RecNo],
2315 InputFlag = InputChain.getValue(1);
2319 case OPC_EmitNodeXForm: {
2320 unsigned XFormNo = MatcherTable[MatcherIndex++];
2321 unsigned RecNo = MatcherTable[MatcherIndex++];
2322 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2323 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2328 case OPC_MorphNodeTo: {
2329 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2330 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2331 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2332 // Get the result VT list.
2333 unsigned NumVTs = MatcherTable[MatcherIndex++];
2334 SmallVector<EVT, 4> VTs;
2335 for (unsigned i = 0; i != NumVTs; ++i) {
2336 MVT::SimpleValueType VT =
2337 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2338 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2342 if (EmitNodeInfo & OPFL_Chain)
2343 VTs.push_back(MVT::Other);
2344 if (EmitNodeInfo & OPFL_FlagOutput)
2345 VTs.push_back(MVT::Flag);
2347 // This is hot code, so optimize the two most common cases of 1 and 2
2350 if (VTs.size() == 1)
2351 VTList = CurDAG->getVTList(VTs[0]);
2352 else if (VTs.size() == 2)
2353 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2355 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2357 // Get the operand list.
2358 unsigned NumOps = MatcherTable[MatcherIndex++];
2359 SmallVector<SDValue, 8> Ops;
2360 for (unsigned i = 0; i != NumOps; ++i) {
2361 unsigned RecNo = MatcherTable[MatcherIndex++];
2363 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2365 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2366 Ops.push_back(RecordedNodes[RecNo]);
2369 // If there are variadic operands to add, handle them now.
2370 if (EmitNodeInfo & OPFL_VariadicInfo) {
2371 // Determine the start index to copy from.
2372 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2373 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2374 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2375 "Invalid variadic node");
2376 // Copy all of the variadic operands, not including a potential flag
2378 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2380 SDValue V = NodeToMatch->getOperand(i);
2381 if (V.getValueType() == MVT::Flag) break;
2386 // If this has chain/flag inputs, add them.
2387 if (EmitNodeInfo & OPFL_Chain)
2388 Ops.push_back(InputChain);
2389 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2390 Ops.push_back(InputFlag);
2394 if (Opcode != OPC_MorphNodeTo) {
2395 // If this is a normal EmitNode command, just create the new node and
2396 // add the results to the RecordedNodes list.
2397 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2398 VTList, Ops.data(), Ops.size());
2400 // Add all the non-flag/non-chain results to the RecordedNodes list.
2401 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2402 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2403 RecordedNodes.push_back(SDValue(Res, i));
2407 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2411 // If the node had chain/flag results, update our notion of the current
2413 if (EmitNodeInfo & OPFL_FlagOutput) {
2414 InputFlag = SDValue(Res, VTs.size()-1);
2415 if (EmitNodeInfo & OPFL_Chain)
2416 InputChain = SDValue(Res, VTs.size()-2);
2417 } else if (EmitNodeInfo & OPFL_Chain)
2418 InputChain = SDValue(Res, VTs.size()-1);
2420 // If the OPFL_MemRefs flag is set on this node, slap all of the
2421 // accumulated memrefs onto it.
2423 // FIXME: This is vastly incorrect for patterns with multiple outputs
2424 // instructions that access memory and for ComplexPatterns that match
2426 if (EmitNodeInfo & OPFL_MemRefs) {
2427 MachineSDNode::mmo_iterator MemRefs =
2428 MF->allocateMemRefsArray(MatchedMemRefs.size());
2429 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2430 cast<MachineSDNode>(Res)
2431 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2435 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2436 << " node: "; Res->dump(CurDAG); errs() << "\n");
2438 // If this was a MorphNodeTo then we're completely done!
2439 if (Opcode == OPC_MorphNodeTo) {
2440 // Update chain and flag uses.
2441 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2442 InputFlag, FlagResultNodesMatched, true);
2449 case OPC_MarkFlagResults: {
2450 unsigned NumNodes = MatcherTable[MatcherIndex++];
2452 // Read and remember all the flag-result nodes.
2453 for (unsigned i = 0; i != NumNodes; ++i) {
2454 unsigned RecNo = MatcherTable[MatcherIndex++];
2456 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2458 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2459 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2464 case OPC_CompleteMatch: {
2465 // The match has been completed, and any new nodes (if any) have been
2466 // created. Patch up references to the matched dag to use the newly
2468 unsigned NumResults = MatcherTable[MatcherIndex++];
2470 for (unsigned i = 0; i != NumResults; ++i) {
2471 unsigned ResSlot = MatcherTable[MatcherIndex++];
2473 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2475 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2476 SDValue Res = RecordedNodes[ResSlot];
2478 // FIXME2: Eliminate this horrible hack by fixing the 'Gen' program
2479 // after (parallel) on input patterns are removed. This would also
2480 // allow us to stop encoding #results in OPC_CompleteMatch's table
2482 if (NodeToMatch->getNumValues() <= i ||
2483 NodeToMatch->getValueType(i) == MVT::Other ||
2484 NodeToMatch->getValueType(i) == MVT::Flag)
2486 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2487 NodeToMatch->getValueType(i) == MVT::iPTR ||
2488 Res.getValueType() == MVT::iPTR ||
2489 NodeToMatch->getValueType(i).getSizeInBits() ==
2490 Res.getValueType().getSizeInBits()) &&
2491 "invalid replacement");
2492 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2495 // If the root node defines a flag, add it to the flag nodes to update
2497 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2498 FlagResultNodesMatched.push_back(NodeToMatch);
2500 // Update chain and flag uses.
2501 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2502 InputFlag, FlagResultNodesMatched, false);
2504 assert(NodeToMatch->use_empty() &&
2505 "Didn't replace all uses of the node?");
2507 // FIXME: We just return here, which interacts correctly with SelectRoot
2508 // above. We should fix this to not return an SDNode* anymore.
2513 // If the code reached this point, then the match failed. See if there is
2514 // another child to try in the current 'Scope', otherwise pop it until we
2515 // find a case to check.
2517 if (MatchScopes.empty()) {
2518 CannotYetSelect(NodeToMatch);
2522 // Restore the interpreter state back to the point where the scope was
2524 MatchScope &LastScope = MatchScopes.back();
2525 RecordedNodes.resize(LastScope.NumRecordedNodes);
2527 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2528 N = NodeStack.back();
2530 DEBUG(errs() << " Match failed at index " << MatcherIndex
2531 << " continuing at " << LastScope.FailIndex << "\n");
2533 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2534 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2535 MatcherIndex = LastScope.FailIndex;
2537 InputChain = LastScope.InputChain;
2538 InputFlag = LastScope.InputFlag;
2539 if (!LastScope.HasChainNodesMatched)
2540 ChainNodesMatched.clear();
2541 if (!LastScope.HasFlagResultNodesMatched)
2542 FlagResultNodesMatched.clear();
2544 // Check to see what the offset is at the new MatcherIndex. If it is zero
2545 // we have reached the end of this scope, otherwise we have another child
2546 // in the current scope to try.
2547 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2548 if (NumToSkip & 128)
2549 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2551 // If we have another child in this scope to match, update FailIndex and
2553 if (NumToSkip != 0) {
2554 LastScope.FailIndex = MatcherIndex+NumToSkip;
2558 // End of this scope, pop it and try the next child in the containing
2560 MatchScopes.pop_back();
2567 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2568 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2569 N->getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2570 N->getOpcode() == ISD::INTRINSIC_VOID)
2571 return CannotYetSelectIntrinsic(N);
2574 raw_string_ostream Msg(msg);
2575 Msg << "Cannot yet select: ";
2576 N->printrFull(Msg, CurDAG);
2577 llvm_report_error(Msg.str());
2580 void SelectionDAGISel::CannotYetSelectIntrinsic(SDNode *N) {
2581 dbgs() << "Cannot yet select: ";
2583 cast<ConstantSDNode>(N->getOperand(N->getOperand(0).getValueType() ==
2584 MVT::Other))->getZExtValue();
2585 if (iid < Intrinsic::num_intrinsics)
2586 llvm_report_error("Cannot yet select: intrinsic %" +
2587 Intrinsic::getName((Intrinsic::ID)iid));
2588 else if (const TargetIntrinsicInfo *tii = TM.getIntrinsicInfo())
2589 llvm_report_error(Twine("Cannot yet select: target intrinsic %") +
2593 char SelectionDAGISel::ID = 0;