1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/Timer.h"
53 EnableValueProp("enable-value-prop", cl::Hidden);
55 EnableLegalizeTypes("enable-legalize-types", cl::Hidden);
57 DisableCorrectBranchFolding("disable-correct-folding", cl::init(false),
63 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
64 cl::desc("Pop up a window to show dags before the first "
67 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
68 cl::desc("Pop up a window to show dags before legalize types"));
70 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
71 cl::desc("Pop up a window to show dags before legalize"));
73 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
74 cl::desc("Pop up a window to show dags before the second "
77 ViewISelDAGs("view-isel-dags", cl::Hidden,
78 cl::desc("Pop up a window to show isel dags as they are selected"));
80 ViewSchedDAGs("view-sched-dags", cl::Hidden,
81 cl::desc("Pop up a window to show sched dags as they are processed"));
83 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
84 cl::desc("Pop up a window to show SUnit dags after they are processed"));
86 static const bool ViewDAGCombine1 = false,
87 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
88 ViewDAGCombine2 = false,
89 ViewISelDAGs = false, ViewSchedDAGs = false,
90 ViewSUnitDAGs = false;
93 //===---------------------------------------------------------------------===//
95 /// RegisterScheduler class - Track the registration of instruction schedulers.
97 //===---------------------------------------------------------------------===//
98 MachinePassRegistry RegisterScheduler::Registry;
100 //===---------------------------------------------------------------------===//
102 /// ISHeuristic command line option for instruction schedulers.
104 //===---------------------------------------------------------------------===//
105 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
106 RegisterPassParser<RegisterScheduler> >
107 ISHeuristic("pre-RA-sched",
108 cl::init(&createDefaultScheduler),
109 cl::desc("Instruction schedulers available (before register"
112 static RegisterScheduler
113 defaultListDAGScheduler("default", " Best scheduler for the target",
114 createDefaultScheduler);
116 namespace { struct SDISelAsmOperandInfo; }
118 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
119 /// insertvalue or extractvalue indices that identify a member, return
120 /// the linearized index of the start of the member.
122 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
123 const unsigned *Indices,
124 const unsigned *IndicesEnd,
125 unsigned CurIndex = 0) {
126 // Base case: We're done.
127 if (Indices && Indices == IndicesEnd)
130 // Given a struct type, recursively traverse the elements.
131 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
132 for (StructType::element_iterator EB = STy->element_begin(),
134 EE = STy->element_end();
136 if (Indices && *Indices == unsigned(EI - EB))
137 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
138 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
141 // Given an array type, recursively traverse the elements.
142 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
143 const Type *EltTy = ATy->getElementType();
144 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
145 if (Indices && *Indices == i)
146 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
147 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
150 // We haven't found the type we're looking for, so keep searching.
154 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
155 /// MVTs that represent all the individual underlying
156 /// non-aggregate types that comprise it.
158 /// If Offsets is non-null, it points to a vector to be filled in
159 /// with the in-memory offsets of each of the individual values.
161 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
162 SmallVectorImpl<MVT> &ValueVTs,
163 SmallVectorImpl<uint64_t> *Offsets = 0,
164 uint64_t StartingOffset = 0) {
165 // Given a struct type, recursively traverse the elements.
166 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
167 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
168 for (StructType::element_iterator EB = STy->element_begin(),
170 EE = STy->element_end();
172 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
173 StartingOffset + SL->getElementOffset(EI - EB));
176 // Given an array type, recursively traverse the elements.
177 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
178 const Type *EltTy = ATy->getElementType();
179 uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
180 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
181 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
182 StartingOffset + i * EltSize);
185 // Base case: we can get an MVT for this LLVM IR type.
186 ValueVTs.push_back(TLI.getValueType(Ty));
188 Offsets->push_back(StartingOffset);
192 /// RegsForValue - This struct represents the registers (physical or virtual)
193 /// that a particular set of values is assigned, and the type information about
194 /// the value. The most common situation is to represent one value at a time,
195 /// but struct or array values are handled element-wise as multiple values.
196 /// The splitting of aggregates is performed recursively, so that we never
197 /// have aggregate-typed registers. The values at this point do not necessarily
198 /// have legal types, so each value may require one or more registers of some
201 struct VISIBILITY_HIDDEN RegsForValue {
202 /// TLI - The TargetLowering object.
204 const TargetLowering *TLI;
206 /// ValueVTs - The value types of the values, which may not be legal, and
207 /// may need be promoted or synthesized from one or more registers.
209 SmallVector<MVT, 4> ValueVTs;
211 /// RegVTs - The value types of the registers. This is the same size as
212 /// ValueVTs and it records, for each value, what the type of the assigned
213 /// register or registers are. (Individual values are never synthesized
214 /// from more than one type of register.)
216 /// With virtual registers, the contents of RegVTs is redundant with TLI's
217 /// getRegisterType member function, however when with physical registers
218 /// it is necessary to have a separate record of the types.
220 SmallVector<MVT, 4> RegVTs;
222 /// Regs - This list holds the registers assigned to the values.
223 /// Each legal or promoted value requires one register, and each
224 /// expanded value requires multiple registers.
226 SmallVector<unsigned, 4> Regs;
228 RegsForValue() : TLI(0) {}
230 RegsForValue(const TargetLowering &tli,
231 const SmallVector<unsigned, 4> ®s,
232 MVT regvt, MVT valuevt)
233 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
234 RegsForValue(const TargetLowering &tli,
235 const SmallVector<unsigned, 4> ®s,
236 const SmallVector<MVT, 4> ®vts,
237 const SmallVector<MVT, 4> &valuevts)
238 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
239 RegsForValue(const TargetLowering &tli,
240 unsigned Reg, const Type *Ty) : TLI(&tli) {
241 ComputeValueVTs(tli, Ty, ValueVTs);
243 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
244 MVT ValueVT = ValueVTs[Value];
245 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
246 MVT RegisterVT = TLI->getRegisterType(ValueVT);
247 for (unsigned i = 0; i != NumRegs; ++i)
248 Regs.push_back(Reg + i);
249 RegVTs.push_back(RegisterVT);
254 /// append - Add the specified values to this one.
255 void append(const RegsForValue &RHS) {
257 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
258 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
259 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
263 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
264 /// this value and returns the result as a ValueVTs value. This uses
265 /// Chain/Flag as the input and updates them for the output Chain/Flag.
266 /// If the Flag pointer is NULL, no flag is used.
267 SDValue getCopyFromRegs(SelectionDAG &DAG,
268 SDValue &Chain, SDValue *Flag) const;
270 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
271 /// specified value into the registers specified by this object. This uses
272 /// Chain/Flag as the input and updates them for the output Chain/Flag.
273 /// If the Flag pointer is NULL, no flag is used.
274 void getCopyToRegs(SDValue Val, SelectionDAG &DAG,
275 SDValue &Chain, SDValue *Flag) const;
277 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
278 /// operand list. This adds the code marker and includes the number of
279 /// values added into it.
280 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
281 std::vector<SDValue> &Ops) const;
286 //===--------------------------------------------------------------------===//
287 /// createDefaultScheduler - This creates an instruction scheduler appropriate
289 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
291 MachineBasicBlock *BB,
293 TargetLowering &TLI = IS->getTargetLowering();
295 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
296 return createTDListDAGScheduler(IS, DAG, BB, Fast);
298 assert(TLI.getSchedulingPreference() ==
299 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
300 return createBURRListDAGScheduler(IS, DAG, BB, Fast);
305 //===--------------------------------------------------------------------===//
306 /// FunctionLoweringInfo - This contains information that is global to a
307 /// function that is used when lowering a region of the function.
308 class FunctionLoweringInfo {
313 MachineRegisterInfo &RegInfo;
315 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
317 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
318 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
320 /// ValueMap - Since we emit code for the function a basic block at a time,
321 /// we must remember which virtual registers hold the values for
322 /// cross-basic-block values.
323 DenseMap<const Value*, unsigned> ValueMap;
325 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
326 /// the entry block. This allows the allocas to be efficiently referenced
327 /// anywhere in the function.
328 std::map<const AllocaInst*, int> StaticAllocaMap;
331 SmallSet<Instruction*, 8> CatchInfoLost;
332 SmallSet<Instruction*, 8> CatchInfoFound;
335 unsigned MakeReg(MVT VT) {
336 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
339 /// isExportedInst - Return true if the specified value is an instruction
340 /// exported from its block.
341 bool isExportedInst(const Value *V) {
342 return ValueMap.count(V);
345 unsigned CreateRegForValue(const Value *V);
347 unsigned InitializeRegForValue(const Value *V) {
348 unsigned &R = ValueMap[V];
349 assert(R == 0 && "Already initialized this value register!");
350 return R = CreateRegForValue(V);
354 unsigned NumSignBits;
355 APInt KnownOne, KnownZero;
356 LiveOutInfo() : NumSignBits(0) {}
359 /// LiveOutRegInfo - Information about live out vregs, indexed by their
360 /// register number offset by 'FirstVirtualRegister'.
361 std::vector<LiveOutInfo> LiveOutRegInfo;
365 /// isSelector - Return true if this instruction is a call to the
366 /// eh.selector intrinsic.
367 static bool isSelector(Instruction *I) {
368 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
369 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
370 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
374 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
375 /// PHI nodes or outside of the basic block that defines it, or used by a
376 /// switch or atomic instruction, which may expand to multiple basic blocks.
377 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
378 if (isa<PHINode>(I)) return true;
379 BasicBlock *BB = I->getParent();
380 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
381 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
382 // FIXME: Remove switchinst special case.
383 isa<SwitchInst>(*UI))
388 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
389 /// entry block, return true. This includes arguments used by switches, since
390 /// the switch may expand into multiple basic blocks.
391 static bool isOnlyUsedInEntryBlock(Argument *A) {
392 BasicBlock *Entry = A->getParent()->begin();
393 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
394 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
395 return false; // Use not in entry block.
399 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
400 Function &fn, MachineFunction &mf)
401 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
403 // Create a vreg for each argument register that is not dead and is used
404 // outside of the entry block for the function.
405 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
407 if (!isOnlyUsedInEntryBlock(AI))
408 InitializeRegForValue(AI);
410 // Initialize the mapping of values to registers. This is only set up for
411 // instruction values that are used outside of the block that defines
413 Function::iterator BB = Fn.begin(), EB = Fn.end();
414 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
415 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
416 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
417 const Type *Ty = AI->getAllocatedType();
418 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
420 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
423 TySize *= CUI->getZExtValue(); // Get total allocated size.
424 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
425 StaticAllocaMap[AI] =
426 MF.getFrameInfo()->CreateStackObject(TySize, Align);
429 for (; BB != EB; ++BB)
430 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
431 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
432 if (!isa<AllocaInst>(I) ||
433 !StaticAllocaMap.count(cast<AllocaInst>(I)))
434 InitializeRegForValue(I);
436 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
437 // also creates the initial PHI MachineInstrs, though none of the input
438 // operands are populated.
439 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
440 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
444 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
447 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
448 if (PN->use_empty()) continue;
450 unsigned PHIReg = ValueMap[PN];
451 assert(PHIReg && "PHI node does not have an assigned virtual register!");
453 SmallVector<MVT, 4> ValueVTs;
454 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
455 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
456 MVT VT = ValueVTs[vti];
457 unsigned NumRegisters = TLI.getNumRegisters(VT);
458 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
459 for (unsigned i = 0; i != NumRegisters; ++i)
460 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
461 PHIReg += NumRegisters;
467 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
468 /// the correctly promoted or expanded types. Assign these registers
469 /// consecutive vreg numbers and return the first assigned number.
471 /// In the case that the given value has struct or array type, this function
472 /// will assign registers for each member or element.
474 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
475 SmallVector<MVT, 4> ValueVTs;
476 ComputeValueVTs(TLI, V->getType(), ValueVTs);
478 unsigned FirstReg = 0;
479 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
480 MVT ValueVT = ValueVTs[Value];
481 MVT RegisterVT = TLI.getRegisterType(ValueVT);
483 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
484 for (unsigned i = 0; i != NumRegs; ++i) {
485 unsigned R = MakeReg(RegisterVT);
486 if (!FirstReg) FirstReg = R;
492 //===----------------------------------------------------------------------===//
493 /// SelectionDAGLowering - This is the common target-independent lowering
494 /// implementation that is parameterized by a TargetLowering object.
495 /// Also, targets can overload any lowering method.
498 class SelectionDAGLowering {
499 MachineBasicBlock *CurMBB;
501 DenseMap<const Value*, SDValue> NodeMap;
503 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
504 /// them up and then emit token factor nodes when possible. This allows us to
505 /// get simple disambiguation between loads without worrying about alias
507 SmallVector<SDValue, 8> PendingLoads;
509 /// PendingExports - CopyToReg nodes that copy values to virtual registers
510 /// for export to other blocks need to be emitted before any terminator
511 /// instruction, but they have no other ordering requirements. We bunch them
512 /// up and the emit a single tokenfactor for them just before terminator
514 std::vector<SDValue> PendingExports;
516 /// Case - A struct to record the Value for a switch case, and the
517 /// case's target basic block.
521 MachineBasicBlock* BB;
523 Case() : Low(0), High(0), BB(0) { }
524 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
525 Low(low), High(high), BB(bb) { }
526 uint64_t size() const {
527 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
528 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
529 return (rHigh - rLow + 1ULL);
535 MachineBasicBlock* BB;
538 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
539 Mask(mask), BB(bb), Bits(bits) { }
542 typedef std::vector<Case> CaseVector;
543 typedef std::vector<CaseBits> CaseBitsVector;
544 typedef CaseVector::iterator CaseItr;
545 typedef std::pair<CaseItr, CaseItr> CaseRange;
547 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
548 /// of conditional branches.
550 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
551 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
553 /// CaseBB - The MBB in which to emit the compare and branch
554 MachineBasicBlock *CaseBB;
555 /// LT, GE - If nonzero, we know the current case value must be less-than or
556 /// greater-than-or-equal-to these Constants.
559 /// Range - A pair of iterators representing the range of case values to be
560 /// processed at this point in the binary search tree.
564 typedef std::vector<CaseRec> CaseRecVector;
566 /// The comparison function for sorting the switch case values in the vector.
567 /// WARNING: Case ranges should be disjoint!
569 bool operator () (const Case& C1, const Case& C2) {
570 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
571 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
572 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
573 return CI1->getValue().slt(CI2->getValue());
578 bool operator () (const CaseBits& C1, const CaseBits& C2) {
579 return C1.Bits > C2.Bits;
583 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
586 // TLI - This is information that describes the available target features we
587 // need for lowering. This indicates when operations are unavailable,
588 // implemented with a libcall, etc.
591 const TargetData *TD;
594 /// SwitchCases - Vector of CaseBlock structures used to communicate
595 /// SwitchInst code generation information.
596 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
597 /// JTCases - Vector of JumpTable structures used to communicate
598 /// SwitchInst code generation information.
599 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
600 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
602 /// FuncInfo - Information about the function as a whole.
604 FunctionLoweringInfo &FuncInfo;
606 /// GCI - Garbage collection metadata for the function.
607 CollectorMetadata *GCI;
609 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
611 FunctionLoweringInfo &funcinfo,
612 CollectorMetadata *gci)
613 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
614 FuncInfo(funcinfo), GCI(gci) {
617 /// getRoot - Return the current virtual root of the Selection DAG,
618 /// flushing any PendingLoad items. This must be done before emitting
619 /// a store or any other node that may need to be ordered after any
620 /// prior load instructions.
623 if (PendingLoads.empty())
624 return DAG.getRoot();
626 if (PendingLoads.size() == 1) {
627 SDValue Root = PendingLoads[0];
629 PendingLoads.clear();
633 // Otherwise, we have to make a token factor node.
634 SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
635 &PendingLoads[0], PendingLoads.size());
636 PendingLoads.clear();
641 /// getControlRoot - Similar to getRoot, but instead of flushing all the
642 /// PendingLoad items, flush all the PendingExports items. It is necessary
643 /// to do this before emitting a terminator instruction.
645 SDValue getControlRoot() {
646 SDValue Root = DAG.getRoot();
648 if (PendingExports.empty())
651 // Turn all of the CopyToReg chains into one factored node.
652 if (Root.getOpcode() != ISD::EntryToken) {
653 unsigned i = 0, e = PendingExports.size();
654 for (; i != e; ++i) {
655 assert(PendingExports[i].Val->getNumOperands() > 1);
656 if (PendingExports[i].Val->getOperand(0) == Root)
657 break; // Don't add the root if we already indirectly depend on it.
661 PendingExports.push_back(Root);
664 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
666 PendingExports.size());
667 PendingExports.clear();
672 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
674 void visit(Instruction &I) { visit(I.getOpcode(), I); }
676 void visit(unsigned Opcode, User &I) {
677 // Note: this doesn't use InstVisitor, because it has to work with
678 // ConstantExpr's in addition to instructions.
680 default: assert(0 && "Unknown instruction type encountered!");
682 // Build the switch statement using the Instruction.def file.
683 #define HANDLE_INST(NUM, OPCODE, CLASS) \
684 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
685 #include "llvm/Instruction.def"
689 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
691 SDValue getValue(const Value *V);
693 void setValue(const Value *V, SDValue NewN) {
694 SDValue &N = NodeMap[V];
695 assert(N.Val == 0 && "Already set a value for this node!");
699 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
700 std::set<unsigned> &OutputRegs,
701 std::set<unsigned> &InputRegs);
703 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
704 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
706 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
707 void ExportFromCurrentBlock(Value *V);
708 void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
709 MachineBasicBlock *LandingPad = NULL);
711 // Terminator instructions.
712 void visitRet(ReturnInst &I);
713 void visitBr(BranchInst &I);
714 void visitSwitch(SwitchInst &I);
715 void visitUnreachable(UnreachableInst &I) { /* noop */ }
717 // Helpers for visitSwitch
718 bool handleSmallSwitchRange(CaseRec& CR,
719 CaseRecVector& WorkList,
721 MachineBasicBlock* Default);
722 bool handleJTSwitchCase(CaseRec& CR,
723 CaseRecVector& WorkList,
725 MachineBasicBlock* Default);
726 bool handleBTSplitSwitchCase(CaseRec& CR,
727 CaseRecVector& WorkList,
729 MachineBasicBlock* Default);
730 bool handleBitTestsSwitchCase(CaseRec& CR,
731 CaseRecVector& WorkList,
733 MachineBasicBlock* Default);
734 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
735 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
736 void visitBitTestCase(MachineBasicBlock* NextMBB,
738 SelectionDAGISel::BitTestCase &B);
739 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
740 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
741 SelectionDAGISel::JumpTableHeader &JTH);
743 // These all get lowered before this pass.
744 void visitInvoke(InvokeInst &I);
745 void visitUnwind(UnwindInst &I);
747 void visitBinary(User &I, unsigned OpCode);
748 void visitShift(User &I, unsigned Opcode);
749 void visitAdd(User &I) {
750 if (I.getType()->isFPOrFPVector())
751 visitBinary(I, ISD::FADD);
753 visitBinary(I, ISD::ADD);
755 void visitSub(User &I);
756 void visitMul(User &I) {
757 if (I.getType()->isFPOrFPVector())
758 visitBinary(I, ISD::FMUL);
760 visitBinary(I, ISD::MUL);
762 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
763 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
764 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
765 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
766 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
767 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
768 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
769 void visitOr (User &I) { visitBinary(I, ISD::OR); }
770 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
771 void visitShl (User &I) { visitShift(I, ISD::SHL); }
772 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
773 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
774 void visitICmp(User &I);
775 void visitFCmp(User &I);
776 void visitVICmp(User &I);
777 void visitVFCmp(User &I);
778 // Visit the conversion instructions
779 void visitTrunc(User &I);
780 void visitZExt(User &I);
781 void visitSExt(User &I);
782 void visitFPTrunc(User &I);
783 void visitFPExt(User &I);
784 void visitFPToUI(User &I);
785 void visitFPToSI(User &I);
786 void visitUIToFP(User &I);
787 void visitSIToFP(User &I);
788 void visitPtrToInt(User &I);
789 void visitIntToPtr(User &I);
790 void visitBitCast(User &I);
792 void visitExtractElement(User &I);
793 void visitInsertElement(User &I);
794 void visitShuffleVector(User &I);
796 void visitExtractValue(ExtractValueInst &I);
797 void visitInsertValue(InsertValueInst &I);
799 void visitGetElementPtr(User &I);
800 void visitSelect(User &I);
802 void visitMalloc(MallocInst &I);
803 void visitFree(FreeInst &I);
804 void visitAlloca(AllocaInst &I);
805 void visitLoad(LoadInst &I);
806 void visitStore(StoreInst &I);
807 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
808 void visitCall(CallInst &I);
809 void visitInlineAsm(CallSite CS);
810 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
811 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
813 void visitVAStart(CallInst &I);
814 void visitVAArg(VAArgInst &I);
815 void visitVAEnd(CallInst &I);
816 void visitVACopy(CallInst &I);
818 void visitUserOp1(Instruction &I) {
819 assert(0 && "UserOp1 should not exist at instruction selection time!");
822 void visitUserOp2(Instruction &I) {
823 assert(0 && "UserOp2 should not exist at instruction selection time!");
828 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
831 } // end namespace llvm
834 /// getCopyFromParts - Create a value that contains the specified legal parts
835 /// combined into the value they represent. If the parts combine to a type
836 /// larger then ValueVT then AssertOp can be used to specify whether the extra
837 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
838 /// (ISD::AssertSext).
839 static SDValue getCopyFromParts(SelectionDAG &DAG,
840 const SDValue *Parts,
844 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
845 assert(NumParts > 0 && "No parts to assemble!");
846 TargetLowering &TLI = DAG.getTargetLoweringInfo();
847 SDValue Val = Parts[0];
850 // Assemble the value from multiple parts.
851 if (!ValueVT.isVector()) {
852 unsigned PartBits = PartVT.getSizeInBits();
853 unsigned ValueBits = ValueVT.getSizeInBits();
855 // Assemble the power of 2 part.
856 unsigned RoundParts = NumParts & (NumParts - 1) ?
857 1 << Log2_32(NumParts) : NumParts;
858 unsigned RoundBits = PartBits * RoundParts;
859 MVT RoundVT = RoundBits == ValueBits ?
860 ValueVT : MVT::getIntegerVT(RoundBits);
863 if (RoundParts > 2) {
864 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
865 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
866 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
872 if (TLI.isBigEndian())
874 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
876 if (RoundParts < NumParts) {
877 // Assemble the trailing non-power-of-2 part.
878 unsigned OddParts = NumParts - RoundParts;
879 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
880 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
882 // Combine the round and odd parts.
884 if (TLI.isBigEndian())
886 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
887 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
888 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
889 DAG.getConstant(Lo.getValueType().getSizeInBits(),
890 TLI.getShiftAmountTy()));
891 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
892 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
895 // Handle a multi-element vector.
896 MVT IntermediateVT, RegisterVT;
897 unsigned NumIntermediates;
899 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
901 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
902 NumParts = NumRegs; // Silence a compiler warning.
903 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
904 assert(RegisterVT == Parts[0].getValueType() &&
905 "Part type doesn't match part!");
907 // Assemble the parts into intermediate operands.
908 SmallVector<SDValue, 8> Ops(NumIntermediates);
909 if (NumIntermediates == NumParts) {
910 // If the register was not expanded, truncate or copy the value,
912 for (unsigned i = 0; i != NumParts; ++i)
913 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
914 PartVT, IntermediateVT);
915 } else if (NumParts > 0) {
916 // If the intermediate type was expanded, build the intermediate operands
918 assert(NumParts % NumIntermediates == 0 &&
919 "Must expand into a divisible number of parts!");
920 unsigned Factor = NumParts / NumIntermediates;
921 for (unsigned i = 0; i != NumIntermediates; ++i)
922 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
923 PartVT, IntermediateVT);
926 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
928 Val = DAG.getNode(IntermediateVT.isVector() ?
929 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
930 ValueVT, &Ops[0], NumIntermediates);
934 // There is now one part, held in Val. Correct it to match ValueVT.
935 PartVT = Val.getValueType();
937 if (PartVT == ValueVT)
940 if (PartVT.isVector()) {
941 assert(ValueVT.isVector() && "Unknown vector conversion!");
942 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
945 if (ValueVT.isVector()) {
946 assert(ValueVT.getVectorElementType() == PartVT &&
947 ValueVT.getVectorNumElements() == 1 &&
948 "Only trivial scalar-to-vector conversions should get here!");
949 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
952 if (PartVT.isInteger() &&
953 ValueVT.isInteger()) {
954 if (ValueVT.bitsLT(PartVT)) {
955 // For a truncate, see if we have any information to
956 // indicate whether the truncated bits will always be
957 // zero or sign-extension.
958 if (AssertOp != ISD::DELETED_NODE)
959 Val = DAG.getNode(AssertOp, PartVT, Val,
960 DAG.getValueType(ValueVT));
961 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
963 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
967 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
968 if (ValueVT.bitsLT(Val.getValueType()))
969 // FP_ROUND's are always exact here.
970 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
971 DAG.getIntPtrConstant(1));
972 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
975 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
976 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
978 assert(0 && "Unknown mismatch!");
982 /// getCopyToParts - Create a series of nodes that contain the specified value
983 /// split into legal parts. If the parts contain more bits than Val, then, for
984 /// integers, ExtendKind can be used to specify how to generate the extra bits.
985 static void getCopyToParts(SelectionDAG &DAG,
990 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
991 TargetLowering &TLI = DAG.getTargetLoweringInfo();
992 MVT PtrVT = TLI.getPointerTy();
993 MVT ValueVT = Val.getValueType();
994 unsigned PartBits = PartVT.getSizeInBits();
995 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
1000 if (!ValueVT.isVector()) {
1001 if (PartVT == ValueVT) {
1002 assert(NumParts == 1 && "No-op copy with multiple parts!");
1007 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
1008 // If the parts cover more bits than the value has, promote the value.
1009 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
1010 assert(NumParts == 1 && "Do not know what to promote to!");
1011 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
1012 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
1013 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1014 Val = DAG.getNode(ExtendKind, ValueVT, Val);
1016 assert(0 && "Unknown mismatch!");
1018 } else if (PartBits == ValueVT.getSizeInBits()) {
1019 // Different types of the same size.
1020 assert(NumParts == 1 && PartVT != ValueVT);
1021 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1022 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
1023 // If the parts cover less bits than value has, truncate the value.
1024 if (PartVT.isInteger() && ValueVT.isInteger()) {
1025 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1026 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1028 assert(0 && "Unknown mismatch!");
1032 // The value may have changed - recompute ValueVT.
1033 ValueVT = Val.getValueType();
1034 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
1035 "Failed to tile the value with PartVT!");
1037 if (NumParts == 1) {
1038 assert(PartVT == ValueVT && "Type conversion failed!");
1043 // Expand the value into multiple parts.
1044 if (NumParts & (NumParts - 1)) {
1045 // The number of parts is not a power of 2. Split off and copy the tail.
1046 assert(PartVT.isInteger() && ValueVT.isInteger() &&
1047 "Do not know what to expand to!");
1048 unsigned RoundParts = 1 << Log2_32(NumParts);
1049 unsigned RoundBits = RoundParts * PartBits;
1050 unsigned OddParts = NumParts - RoundParts;
1051 SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
1052 DAG.getConstant(RoundBits,
1053 TLI.getShiftAmountTy()));
1054 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
1055 if (TLI.isBigEndian())
1056 // The odd parts were reversed by getCopyToParts - unreverse them.
1057 std::reverse(Parts + RoundParts, Parts + NumParts);
1058 NumParts = RoundParts;
1059 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
1060 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1063 // The number of parts is a power of 2. Repeatedly bisect the value using
1065 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
1066 MVT::getIntegerVT(ValueVT.getSizeInBits()),
1068 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
1069 for (unsigned i = 0; i < NumParts; i += StepSize) {
1070 unsigned ThisBits = StepSize * PartBits / 2;
1071 MVT ThisVT = MVT::getIntegerVT (ThisBits);
1072 SDValue &Part0 = Parts[i];
1073 SDValue &Part1 = Parts[i+StepSize/2];
1075 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1076 DAG.getConstant(1, PtrVT));
1077 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
1078 DAG.getConstant(0, PtrVT));
1080 if (ThisBits == PartBits && ThisVT != PartVT) {
1081 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
1082 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
1087 if (TLI.isBigEndian())
1088 std::reverse(Parts, Parts + NumParts);
1094 if (NumParts == 1) {
1095 if (PartVT != ValueVT) {
1096 if (PartVT.isVector()) {
1097 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1099 assert(ValueVT.getVectorElementType() == PartVT &&
1100 ValueVT.getVectorNumElements() == 1 &&
1101 "Only trivial vector-to-scalar conversions should get here!");
1102 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1103 DAG.getConstant(0, PtrVT));
1111 // Handle a multi-element vector.
1112 MVT IntermediateVT, RegisterVT;
1113 unsigned NumIntermediates;
1115 DAG.getTargetLoweringInfo()
1116 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1118 unsigned NumElements = ValueVT.getVectorNumElements();
1120 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1121 NumParts = NumRegs; // Silence a compiler warning.
1122 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1124 // Split the vector into intermediate operands.
1125 SmallVector<SDValue, 8> Ops(NumIntermediates);
1126 for (unsigned i = 0; i != NumIntermediates; ++i)
1127 if (IntermediateVT.isVector())
1128 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1129 IntermediateVT, Val,
1130 DAG.getConstant(i * (NumElements / NumIntermediates),
1133 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1134 IntermediateVT, Val,
1135 DAG.getConstant(i, PtrVT));
1137 // Split the intermediate operands into legal parts.
1138 if (NumParts == NumIntermediates) {
1139 // If the register was not expanded, promote or copy the value,
1141 for (unsigned i = 0; i != NumParts; ++i)
1142 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
1143 } else if (NumParts > 0) {
1144 // If the intermediate type was expanded, split each the value into
1146 assert(NumParts % NumIntermediates == 0 &&
1147 "Must expand into a divisible number of parts!");
1148 unsigned Factor = NumParts / NumIntermediates;
1149 for (unsigned i = 0; i != NumIntermediates; ++i)
1150 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
1155 SDValue SelectionDAGLowering::getValue(const Value *V) {
1156 SDValue &N = NodeMap[V];
1157 if (N.Val) return N;
1159 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
1160 MVT VT = TLI.getValueType(V->getType(), true);
1162 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1163 return N = DAG.getConstant(CI->getValue(), VT);
1165 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
1166 return N = DAG.getGlobalAddress(GV, VT);
1168 if (isa<ConstantPointerNull>(C))
1169 return N = DAG.getConstant(0, TLI.getPointerTy());
1171 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1172 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1174 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
1175 !V->getType()->isAggregateType())
1176 return N = DAG.getNode(ISD::UNDEF, VT);
1178 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1179 visit(CE->getOpcode(), *CE);
1180 SDValue N1 = NodeMap[V];
1181 assert(N1.Val && "visit didn't populate the ValueMap!");
1185 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1186 SmallVector<SDValue, 4> Constants;
1187 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1189 SDNode *Val = getValue(*OI).Val;
1190 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1191 Constants.push_back(SDValue(Val, i));
1193 return DAG.getMergeValues(&Constants[0], Constants.size());
1196 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
1197 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1198 "Unknown struct or array constant!");
1200 SmallVector<MVT, 4> ValueVTs;
1201 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1202 unsigned NumElts = ValueVTs.size();
1204 return SDValue(); // empty struct
1205 SmallVector<SDValue, 4> Constants(NumElts);
1206 for (unsigned i = 0; i != NumElts; ++i) {
1207 MVT EltVT = ValueVTs[i];
1208 if (isa<UndefValue>(C))
1209 Constants[i] = DAG.getNode(ISD::UNDEF, EltVT);
1210 else if (EltVT.isFloatingPoint())
1211 Constants[i] = DAG.getConstantFP(0, EltVT);
1213 Constants[i] = DAG.getConstant(0, EltVT);
1215 return DAG.getMergeValues(&Constants[0], NumElts);
1218 const VectorType *VecTy = cast<VectorType>(V->getType());
1219 unsigned NumElements = VecTy->getNumElements();
1221 // Now that we know the number and type of the elements, get that number of
1222 // elements into the Ops array based on what kind of constant it is.
1223 SmallVector<SDValue, 16> Ops;
1224 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1225 for (unsigned i = 0; i != NumElements; ++i)
1226 Ops.push_back(getValue(CP->getOperand(i)));
1228 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1229 "Unknown vector constant!");
1230 MVT EltVT = TLI.getValueType(VecTy->getElementType());
1233 if (isa<UndefValue>(C))
1234 Op = DAG.getNode(ISD::UNDEF, EltVT);
1235 else if (EltVT.isFloatingPoint())
1236 Op = DAG.getConstantFP(0, EltVT);
1238 Op = DAG.getConstant(0, EltVT);
1239 Ops.assign(NumElements, Op);
1242 // Create a BUILD_VECTOR node.
1243 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1246 // If this is a static alloca, generate it as the frameindex instead of
1248 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1249 std::map<const AllocaInst*, int>::iterator SI =
1250 FuncInfo.StaticAllocaMap.find(AI);
1251 if (SI != FuncInfo.StaticAllocaMap.end())
1252 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1255 unsigned InReg = FuncInfo.ValueMap[V];
1256 assert(InReg && "Value not in map!");
1258 RegsForValue RFV(TLI, InReg, V->getType());
1259 SDValue Chain = DAG.getEntryNode();
1260 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1264 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1265 if (I.getNumOperands() == 0) {
1266 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1270 SmallVector<SDValue, 8> NewValues;
1271 NewValues.push_back(getControlRoot());
1272 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1273 SDValue RetOp = getValue(I.getOperand(i));
1275 SmallVector<MVT, 4> ValueVTs;
1276 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
1277 for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
1278 MVT VT = ValueVTs[j];
1280 // FIXME: C calling convention requires the return type to be promoted to
1281 // at least 32-bit. But this is not necessary for non-C calling conventions.
1282 if (VT.isInteger()) {
1283 MVT MinVT = TLI.getRegisterType(MVT::i32);
1284 if (VT.bitsLT(MinVT))
1288 unsigned NumParts = TLI.getNumRegisters(VT);
1289 MVT PartVT = TLI.getRegisterType(VT);
1290 SmallVector<SDValue, 4> Parts(NumParts);
1291 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1293 const Function *F = I.getParent()->getParent();
1294 if (F->paramHasAttr(0, ParamAttr::SExt))
1295 ExtendKind = ISD::SIGN_EXTEND;
1296 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1297 ExtendKind = ISD::ZERO_EXTEND;
1299 getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j),
1300 &Parts[0], NumParts, PartVT, ExtendKind);
1302 for (unsigned i = 0; i < NumParts; ++i) {
1303 NewValues.push_back(Parts[i]);
1304 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1308 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1309 &NewValues[0], NewValues.size()));
1312 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1313 /// the current basic block, add it to ValueMap now so that we'll get a
1315 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1316 // No need to export constants.
1317 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1319 // Already exported?
1320 if (FuncInfo.isExportedInst(V)) return;
1322 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1323 CopyValueToVirtualRegister(V, Reg);
1326 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1327 const BasicBlock *FromBB) {
1328 // The operands of the setcc have to be in this block. We don't know
1329 // how to export them from some other block.
1330 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1331 // Can export from current BB.
1332 if (VI->getParent() == FromBB)
1335 // Is already exported, noop.
1336 return FuncInfo.isExportedInst(V);
1339 // If this is an argument, we can export it if the BB is the entry block or
1340 // if it is already exported.
1341 if (isa<Argument>(V)) {
1342 if (FromBB == &FromBB->getParent()->getEntryBlock())
1345 // Otherwise, can only export this if it is already exported.
1346 return FuncInfo.isExportedInst(V);
1349 // Otherwise, constants can always be exported.
1353 static bool InBlock(const Value *V, const BasicBlock *BB) {
1354 if (const Instruction *I = dyn_cast<Instruction>(V))
1355 return I->getParent() == BB;
1359 /// FindMergedConditions - If Cond is an expression like
1360 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1361 MachineBasicBlock *TBB,
1362 MachineBasicBlock *FBB,
1363 MachineBasicBlock *CurBB,
1365 // If this node is not part of the or/and tree, emit it as a branch.
1366 Instruction *BOp = dyn_cast<Instruction>(Cond);
1368 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1369 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1370 BOp->getParent() != CurBB->getBasicBlock() ||
1371 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1372 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1373 const BasicBlock *BB = CurBB->getBasicBlock();
1375 // If the leaf of the tree is a comparison, merge the condition into
1377 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1378 // The operands of the cmp have to be in this block. We don't know
1379 // how to export them from some other block. If this is the first block
1380 // of the sequence, no exporting is needed.
1382 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1383 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1384 BOp = cast<Instruction>(Cond);
1385 ISD::CondCode Condition;
1386 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1387 switch (IC->getPredicate()) {
1388 default: assert(0 && "Unknown icmp predicate opcode!");
1389 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1390 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1391 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1392 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1393 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1394 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1395 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1396 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1397 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1398 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1400 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1401 ISD::CondCode FPC, FOC;
1402 switch (FC->getPredicate()) {
1403 default: assert(0 && "Unknown fcmp predicate opcode!");
1404 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1405 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1406 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1407 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1408 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1409 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1410 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1411 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1412 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1413 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1414 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1415 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1416 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1417 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1418 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1419 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1421 if (FiniteOnlyFPMath())
1426 Condition = ISD::SETEQ; // silence warning.
1427 assert(0 && "Unknown compare instruction");
1430 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1431 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1432 SwitchCases.push_back(CB);
1436 // Create a CaseBlock record representing this branch.
1437 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1438 NULL, TBB, FBB, CurBB);
1439 SwitchCases.push_back(CB);
1444 // Create TmpBB after CurBB.
1445 MachineFunction::iterator BBI = CurBB;
1446 MachineFunction &MF = DAG.getMachineFunction();
1447 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1448 CurBB->getParent()->insert(++BBI, TmpBB);
1450 if (Opc == Instruction::Or) {
1451 // Codegen X | Y as:
1459 // Emit the LHS condition.
1460 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1462 // Emit the RHS condition into TmpBB.
1463 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1465 assert(Opc == Instruction::And && "Unknown merge op!");
1466 // Codegen X & Y as:
1473 // This requires creation of TmpBB after CurBB.
1475 // Emit the LHS condition.
1476 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1478 // Emit the RHS condition into TmpBB.
1479 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1483 /// If the set of cases should be emitted as a series of branches, return true.
1484 /// If we should emit this as a bunch of and/or'd together conditions, return
1487 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1488 if (Cases.size() != 2) return true;
1490 // If this is two comparisons of the same values or'd or and'd together, they
1491 // will get folded into a single comparison, so don't emit two blocks.
1492 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1493 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1494 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1495 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1502 void SelectionDAGLowering::visitBr(BranchInst &I) {
1503 // Update machine-CFG edges.
1504 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1506 // Figure out which block is immediately after the current one.
1507 MachineBasicBlock *NextBlock = 0;
1508 MachineFunction::iterator BBI = CurMBB;
1509 if (++BBI != CurMBB->getParent()->end())
1512 if (I.isUnconditional()) {
1513 // Update machine-CFG edges.
1514 CurMBB->addSuccessor(Succ0MBB);
1516 // If this is not a fall-through branch, emit the branch.
1517 if (Succ0MBB != NextBlock)
1518 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1519 DAG.getBasicBlock(Succ0MBB)));
1523 // If this condition is one of the special cases we handle, do special stuff
1525 Value *CondVal = I.getCondition();
1526 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1528 // If this is a series of conditions that are or'd or and'd together, emit
1529 // this as a sequence of branches instead of setcc's with and/or operations.
1530 // For example, instead of something like:
1543 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1544 if (BOp->hasOneUse() &&
1545 (BOp->getOpcode() == Instruction::And ||
1546 BOp->getOpcode() == Instruction::Or)) {
1547 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1548 // If the compares in later blocks need to use values not currently
1549 // exported from this block, export them now. This block should always
1550 // be the first entry.
1551 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1553 // Allow some cases to be rejected.
1554 if (ShouldEmitAsBranches(SwitchCases)) {
1555 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1556 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1557 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1560 // Emit the branch for this block.
1561 visitSwitchCase(SwitchCases[0]);
1562 SwitchCases.erase(SwitchCases.begin());
1566 // Okay, we decided not to do this, remove any inserted MBB's and clear
1568 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1569 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1571 SwitchCases.clear();
1575 // Create a CaseBlock record representing this branch.
1576 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1577 NULL, Succ0MBB, Succ1MBB, CurMBB);
1578 // Use visitSwitchCase to actually insert the fast branch sequence for this
1580 visitSwitchCase(CB);
1583 /// visitSwitchCase - Emits the necessary code to represent a single node in
1584 /// the binary search tree resulting from lowering a switch instruction.
1585 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1587 SDValue CondLHS = getValue(CB.CmpLHS);
1589 // Build the setcc now.
1590 if (CB.CmpMHS == NULL) {
1591 // Fold "(X == true)" to X and "(X == false)" to !X to
1592 // handle common cases produced by branch lowering.
1593 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1595 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1596 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1597 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1599 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1601 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1603 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1604 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1606 SDValue CmpOp = getValue(CB.CmpMHS);
1607 MVT VT = CmpOp.getValueType();
1609 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1610 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1612 SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1613 Cond = DAG.getSetCC(MVT::i1, SUB,
1614 DAG.getConstant(High-Low, VT), ISD::SETULE);
1618 // Update successor info
1619 CurMBB->addSuccessor(CB.TrueBB);
1620 CurMBB->addSuccessor(CB.FalseBB);
1622 // Set NextBlock to be the MBB immediately after the current one, if any.
1623 // This is used to avoid emitting unnecessary branches to the next block.
1624 MachineBasicBlock *NextBlock = 0;
1625 MachineFunction::iterator BBI = CurMBB;
1626 if (++BBI != CurMBB->getParent()->end())
1629 // If the lhs block is the next block, invert the condition so that we can
1630 // fall through to the lhs instead of the rhs block.
1631 if (CB.TrueBB == NextBlock) {
1632 std::swap(CB.TrueBB, CB.FalseBB);
1633 SDValue True = DAG.getConstant(1, Cond.getValueType());
1634 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1636 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1637 DAG.getBasicBlock(CB.TrueBB));
1639 // If the branch was constant folded, fix up the CFG.
1640 if (BrCond.getOpcode() == ISD::BR) {
1641 if (!DisableCorrectBranchFolding)
1642 CurMBB->removeSuccessor(CB.FalseBB);
1643 DAG.setRoot(BrCond);
1645 // Otherwise, go ahead and insert the false branch.
1646 if (BrCond == getControlRoot())
1647 if (!DisableCorrectBranchFolding)
1648 CurMBB->removeSuccessor(CB.TrueBB);
1650 if (CB.FalseBB == NextBlock)
1651 DAG.setRoot(BrCond);
1653 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1654 DAG.getBasicBlock(CB.FalseBB)));
1658 /// visitJumpTable - Emit JumpTable node in the current MBB
1659 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1660 // Emit the code for the jump table
1661 assert(JT.Reg != -1U && "Should lower JT Header first!");
1662 MVT PTy = TLI.getPointerTy();
1663 SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1664 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1665 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1670 /// visitJumpTableHeader - This function emits necessary code to produce index
1671 /// in the JumpTable from switch case.
1672 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1673 SelectionDAGISel::JumpTableHeader &JTH) {
1674 // Subtract the lowest switch case value from the value being switched on
1675 // and conditional branch to default mbb if the result is greater than the
1676 // difference between smallest and largest cases.
1677 SDValue SwitchOp = getValue(JTH.SValue);
1678 MVT VT = SwitchOp.getValueType();
1679 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1680 DAG.getConstant(JTH.First, VT));
1682 // The SDNode we just created, which holds the value being switched on
1683 // minus the the smallest case value, needs to be copied to a virtual
1684 // register so it can be used as an index into the jump table in a
1685 // subsequent basic block. This value may be smaller or larger than the
1686 // target's pointer type, and therefore require extension or truncating.
1687 if (VT.bitsGT(TLI.getPointerTy()))
1688 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1690 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1692 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1693 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1694 JT.Reg = JumpTableReg;
1696 // Emit the range check for the jump table, and branch to the default
1697 // block for the switch statement if the value being switched on exceeds
1698 // the largest case in the switch.
1699 SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1700 DAG.getConstant(JTH.Last-JTH.First,VT),
1703 // Set NextBlock to be the MBB immediately after the current one, if any.
1704 // This is used to avoid emitting unnecessary branches to the next block.
1705 MachineBasicBlock *NextBlock = 0;
1706 MachineFunction::iterator BBI = CurMBB;
1707 if (++BBI != CurMBB->getParent()->end())
1710 SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1711 DAG.getBasicBlock(JT.Default));
1713 if (JT.MBB == NextBlock)
1714 DAG.setRoot(BrCond);
1716 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1717 DAG.getBasicBlock(JT.MBB)));
1722 /// visitBitTestHeader - This function emits necessary code to produce value
1723 /// suitable for "bit tests"
1724 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1725 // Subtract the minimum value
1726 SDValue SwitchOp = getValue(B.SValue);
1727 MVT VT = SwitchOp.getValueType();
1728 SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1729 DAG.getConstant(B.First, VT));
1732 SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1733 DAG.getConstant(B.Range, VT),
1737 if (VT.bitsGT(TLI.getShiftAmountTy()))
1738 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1740 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1742 // Make desired shift
1743 SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1744 DAG.getConstant(1, TLI.getPointerTy()),
1747 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1748 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1751 // Set NextBlock to be the MBB immediately after the current one, if any.
1752 // This is used to avoid emitting unnecessary branches to the next block.
1753 MachineBasicBlock *NextBlock = 0;
1754 MachineFunction::iterator BBI = CurMBB;
1755 if (++BBI != CurMBB->getParent()->end())
1758 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1760 CurMBB->addSuccessor(B.Default);
1761 CurMBB->addSuccessor(MBB);
1763 SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1764 DAG.getBasicBlock(B.Default));
1766 if (MBB == NextBlock)
1767 DAG.setRoot(BrRange);
1769 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1770 DAG.getBasicBlock(MBB)));
1775 /// visitBitTestCase - this function produces one "bit test"
1776 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1778 SelectionDAGISel::BitTestCase &B) {
1779 // Emit bit tests and jumps
1780 SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
1781 TLI.getPointerTy());
1783 SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
1784 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1785 SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1786 DAG.getConstant(0, TLI.getPointerTy()),
1789 CurMBB->addSuccessor(B.TargetBB);
1790 CurMBB->addSuccessor(NextMBB);
1792 SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1793 AndCmp, DAG.getBasicBlock(B.TargetBB));
1795 // Set NextBlock to be the MBB immediately after the current one, if any.
1796 // This is used to avoid emitting unnecessary branches to the next block.
1797 MachineBasicBlock *NextBlock = 0;
1798 MachineFunction::iterator BBI = CurMBB;
1799 if (++BBI != CurMBB->getParent()->end())
1802 if (NextMBB == NextBlock)
1805 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1806 DAG.getBasicBlock(NextMBB)));
1811 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1812 // Retrieve successors.
1813 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1814 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1816 if (isa<InlineAsm>(I.getCalledValue()))
1819 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1821 // If the value of the invoke is used outside of its defining block, make it
1822 // available as a virtual register.
1823 if (!I.use_empty()) {
1824 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1825 if (VMI != FuncInfo.ValueMap.end())
1826 CopyValueToVirtualRegister(&I, VMI->second);
1829 // Update successor info
1830 CurMBB->addSuccessor(Return);
1831 CurMBB->addSuccessor(LandingPad);
1833 // Drop into normal successor.
1834 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1835 DAG.getBasicBlock(Return)));
1838 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1841 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1842 /// small case ranges).
1843 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1844 CaseRecVector& WorkList,
1846 MachineBasicBlock* Default) {
1847 Case& BackCase = *(CR.Range.second-1);
1849 // Size is the number of Cases represented by this range.
1850 unsigned Size = CR.Range.second - CR.Range.first;
1854 // Get the MachineFunction which holds the current MBB. This is used when
1855 // inserting any additional MBBs necessary to represent the switch.
1856 MachineFunction *CurMF = CurMBB->getParent();
1858 // Figure out which block is immediately after the current one.
1859 MachineBasicBlock *NextBlock = 0;
1860 MachineFunction::iterator BBI = CR.CaseBB;
1862 if (++BBI != CurMBB->getParent()->end())
1865 // TODO: If any two of the cases has the same destination, and if one value
1866 // is the same as the other, but has one bit unset that the other has set,
1867 // use bit manipulation to do two compares at once. For example:
1868 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1870 // Rearrange the case blocks so that the last one falls through if possible.
1871 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1872 // The last case block won't fall through into 'NextBlock' if we emit the
1873 // branches in this order. See if rearranging a case value would help.
1874 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1875 if (I->BB == NextBlock) {
1876 std::swap(*I, BackCase);
1882 // Create a CaseBlock record representing a conditional branch to
1883 // the Case's target mbb if the value being switched on SV is equal
1885 MachineBasicBlock *CurBlock = CR.CaseBB;
1886 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1887 MachineBasicBlock *FallThrough;
1889 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1890 CurMF->insert(BBI, FallThrough);
1892 // If the last case doesn't match, go to the default block.
1893 FallThrough = Default;
1896 Value *RHS, *LHS, *MHS;
1898 if (I->High == I->Low) {
1899 // This is just small small case range :) containing exactly 1 case
1901 LHS = SV; RHS = I->High; MHS = NULL;
1904 LHS = I->Low; MHS = SV; RHS = I->High;
1906 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1907 I->BB, FallThrough, CurBlock);
1909 // If emitting the first comparison, just call visitSwitchCase to emit the
1910 // code into the current block. Otherwise, push the CaseBlock onto the
1911 // vector to be later processed by SDISel, and insert the node's MBB
1912 // before the next MBB.
1913 if (CurBlock == CurMBB)
1914 visitSwitchCase(CB);
1916 SwitchCases.push_back(CB);
1918 CurBlock = FallThrough;
1924 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1925 return !DisableJumpTables &&
1926 (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1927 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1930 /// handleJTSwitchCase - Emit jumptable for current switch case range
1931 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1932 CaseRecVector& WorkList,
1934 MachineBasicBlock* Default) {
1935 Case& FrontCase = *CR.Range.first;
1936 Case& BackCase = *(CR.Range.second-1);
1938 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1939 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1942 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1946 if (!areJTsAllowed(TLI) || TSize <= 3)
1949 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1953 DOUT << "Lowering jump table\n"
1954 << "First entry: " << First << ". Last entry: " << Last << "\n"
1955 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1957 // Get the MachineFunction which holds the current MBB. This is used when
1958 // inserting any additional MBBs necessary to represent the switch.
1959 MachineFunction *CurMF = CurMBB->getParent();
1961 // Figure out which block is immediately after the current one.
1962 MachineBasicBlock *NextBlock = 0;
1963 MachineFunction::iterator BBI = CR.CaseBB;
1965 if (++BBI != CurMBB->getParent()->end())
1968 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1970 // Create a new basic block to hold the code for loading the address
1971 // of the jump table, and jumping to it. Update successor information;
1972 // we will either branch to the default case for the switch, or the jump
1974 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1975 CurMF->insert(BBI, JumpTableBB);
1976 CR.CaseBB->addSuccessor(Default);
1977 CR.CaseBB->addSuccessor(JumpTableBB);
1979 // Build a vector of destination BBs, corresponding to each target
1980 // of the jump table. If the value of the jump table slot corresponds to
1981 // a case statement, push the case's BB onto the vector, otherwise, push
1983 std::vector<MachineBasicBlock*> DestBBs;
1984 int64_t TEI = First;
1985 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1986 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1987 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1989 if ((Low <= TEI) && (TEI <= High)) {
1990 DestBBs.push_back(I->BB);
1994 DestBBs.push_back(Default);
1998 // Update successor info. Add one edge to each unique successor.
1999 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2000 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2001 E = DestBBs.end(); I != E; ++I) {
2002 if (!SuccsHandled[(*I)->getNumber()]) {
2003 SuccsHandled[(*I)->getNumber()] = true;
2004 JumpTableBB->addSuccessor(*I);
2008 // Create a jump table index for this jump table, or return an existing
2010 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
2012 // Set the jump table information so that we can codegen it as a second
2013 // MachineBasicBlock
2014 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
2015 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
2016 (CR.CaseBB == CurMBB));
2017 if (CR.CaseBB == CurMBB)
2018 visitJumpTableHeader(JT, JTH);
2020 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
2025 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2027 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
2028 CaseRecVector& WorkList,
2030 MachineBasicBlock* Default) {
2031 // Get the MachineFunction which holds the current MBB. This is used when
2032 // inserting any additional MBBs necessary to represent the switch.
2033 MachineFunction *CurMF = CurMBB->getParent();
2035 // Figure out which block is immediately after the current one.
2036 MachineBasicBlock *NextBlock = 0;
2037 MachineFunction::iterator BBI = CR.CaseBB;
2039 if (++BBI != CurMBB->getParent()->end())
2042 Case& FrontCase = *CR.Range.first;
2043 Case& BackCase = *(CR.Range.second-1);
2044 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2046 // Size is the number of Cases represented by this range.
2047 unsigned Size = CR.Range.second - CR.Range.first;
2049 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
2050 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
2052 CaseItr Pivot = CR.Range.first + Size/2;
2054 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2055 // (heuristically) allow us to emit JumpTable's later.
2057 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2061 uint64_t LSize = FrontCase.size();
2062 uint64_t RSize = TSize-LSize;
2063 DOUT << "Selecting best pivot: \n"
2064 << "First: " << First << ", Last: " << Last <<"\n"
2065 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
2066 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2068 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
2069 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
2070 assert((RBegin-LEnd>=1) && "Invalid case distance");
2071 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
2072 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
2073 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
2074 // Should always split in some non-trivial place
2076 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
2077 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
2078 << "Metric: " << Metric << "\n";
2079 if (FMetric < Metric) {
2082 DOUT << "Current metric set to: " << FMetric << "\n";
2088 if (areJTsAllowed(TLI)) {
2089 // If our case is dense we *really* should handle it earlier!
2090 assert((FMetric > 0) && "Should handle dense range earlier!");
2092 Pivot = CR.Range.first + Size/2;
2095 CaseRange LHSR(CR.Range.first, Pivot);
2096 CaseRange RHSR(Pivot, CR.Range.second);
2097 Constant *C = Pivot->Low;
2098 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2100 // We know that we branch to the LHS if the Value being switched on is
2101 // less than the Pivot value, C. We use this to optimize our binary
2102 // tree a bit, by recognizing that if SV is greater than or equal to the
2103 // LHS's Case Value, and that Case Value is exactly one less than the
2104 // Pivot's Value, then we can branch directly to the LHS's Target,
2105 // rather than creating a leaf node for it.
2106 if ((LHSR.second - LHSR.first) == 1 &&
2107 LHSR.first->High == CR.GE &&
2108 cast<ConstantInt>(C)->getSExtValue() ==
2109 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
2110 TrueBB = LHSR.first->BB;
2112 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2113 CurMF->insert(BBI, TrueBB);
2114 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2117 // Similar to the optimization above, if the Value being switched on is
2118 // known to be less than the Constant CR.LT, and the current Case Value
2119 // is CR.LT - 1, then we can branch directly to the target block for
2120 // the current Case Value, rather than emitting a RHS leaf node for it.
2121 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2122 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
2123 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
2124 FalseBB = RHSR.first->BB;
2126 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2127 CurMF->insert(BBI, FalseBB);
2128 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2131 // Create a CaseBlock record representing a conditional branch to
2132 // the LHS node if the value being switched on SV is less than C.
2133 // Otherwise, branch to LHS.
2134 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
2135 TrueBB, FalseBB, CR.CaseBB);
2137 if (CR.CaseBB == CurMBB)
2138 visitSwitchCase(CB);
2140 SwitchCases.push_back(CB);
2145 /// handleBitTestsSwitchCase - if current case range has few destination and
2146 /// range span less, than machine word bitwidth, encode case range into series
2147 /// of masks and emit bit tests with these masks.
2148 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
2149 CaseRecVector& WorkList,
2151 MachineBasicBlock* Default){
2152 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
2154 Case& FrontCase = *CR.Range.first;
2155 Case& BackCase = *(CR.Range.second-1);
2157 // Get the MachineFunction which holds the current MBB. This is used when
2158 // inserting any additional MBBs necessary to represent the switch.
2159 MachineFunction *CurMF = CurMBB->getParent();
2161 unsigned numCmps = 0;
2162 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2164 // Single case counts one, case range - two.
2165 if (I->Low == I->High)
2171 // Count unique destinations
2172 SmallSet<MachineBasicBlock*, 4> Dests;
2173 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2174 Dests.insert(I->BB);
2175 if (Dests.size() > 3)
2176 // Don't bother the code below, if there are too much unique destinations
2179 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2180 << "Total number of comparisons: " << numCmps << "\n";
2182 // Compute span of values.
2183 Constant* minValue = FrontCase.Low;
2184 Constant* maxValue = BackCase.High;
2185 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2186 cast<ConstantInt>(minValue)->getSExtValue();
2187 DOUT << "Compare range: " << range << "\n"
2188 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2189 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2191 if (range>=IntPtrBits ||
2192 (!(Dests.size() == 1 && numCmps >= 3) &&
2193 !(Dests.size() == 2 && numCmps >= 5) &&
2194 !(Dests.size() >= 3 && numCmps >= 6)))
2197 DOUT << "Emitting bit tests\n";
2198 int64_t lowBound = 0;
2200 // Optimize the case where all the case values fit in a
2201 // word without having to subtract minValue. In this case,
2202 // we can optimize away the subtraction.
2203 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
2204 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
2205 range = cast<ConstantInt>(maxValue)->getSExtValue();
2207 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2210 CaseBitsVector CasesBits;
2211 unsigned i, count = 0;
2213 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2214 MachineBasicBlock* Dest = I->BB;
2215 for (i = 0; i < count; ++i)
2216 if (Dest == CasesBits[i].BB)
2220 assert((count < 3) && "Too much destinations to test!");
2221 CasesBits.push_back(CaseBits(0, Dest, 0));
2225 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2226 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2228 for (uint64_t j = lo; j <= hi; j++) {
2229 CasesBits[i].Mask |= 1ULL << j;
2230 CasesBits[i].Bits++;
2234 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2236 SelectionDAGISel::BitTestInfo BTC;
2238 // Figure out which block is immediately after the current one.
2239 MachineFunction::iterator BBI = CR.CaseBB;
2242 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2245 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2246 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2247 << ", BB: " << CasesBits[i].BB << "\n";
2249 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2250 CurMF->insert(BBI, CaseBB);
2251 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2256 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2257 -1U, (CR.CaseBB == CurMBB),
2258 CR.CaseBB, Default, BTC);
2260 if (CR.CaseBB == CurMBB)
2261 visitBitTestHeader(BTB);
2263 BitTestCases.push_back(BTB);
2269 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2270 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2271 const SwitchInst& SI) {
2272 unsigned numCmps = 0;
2274 // Start with "simple" cases
2275 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2276 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2277 Cases.push_back(Case(SI.getSuccessorValue(i),
2278 SI.getSuccessorValue(i),
2281 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2283 // Merge case into clusters
2284 if (Cases.size()>=2)
2285 // Must recompute end() each iteration because it may be
2286 // invalidated by erase if we hold on to it
2287 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2288 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2289 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2290 MachineBasicBlock* nextBB = J->BB;
2291 MachineBasicBlock* currentBB = I->BB;
2293 // If the two neighboring cases go to the same destination, merge them
2294 // into a single case.
2295 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2303 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2304 if (I->Low != I->High)
2305 // A range counts double, since it requires two compares.
2312 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2313 // Figure out which block is immediately after the current one.
2314 MachineBasicBlock *NextBlock = 0;
2315 MachineFunction::iterator BBI = CurMBB;
2317 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2319 // If there is only the default destination, branch to it if it is not the
2320 // next basic block. Otherwise, just fall through.
2321 if (SI.getNumOperands() == 2) {
2322 // Update machine-CFG edges.
2324 // If this is not a fall-through branch, emit the branch.
2325 CurMBB->addSuccessor(Default);
2326 if (Default != NextBlock)
2327 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2328 DAG.getBasicBlock(Default)));
2333 // If there are any non-default case statements, create a vector of Cases
2334 // representing each one, and sort the vector so that we can efficiently
2335 // create a binary search tree from them.
2337 unsigned numCmps = Clusterify(Cases, SI);
2338 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2339 << ". Total compares: " << numCmps << "\n";
2341 // Get the Value to be switched on and default basic blocks, which will be
2342 // inserted into CaseBlock records, representing basic blocks in the binary
2344 Value *SV = SI.getOperand(0);
2346 // Push the initial CaseRec onto the worklist
2347 CaseRecVector WorkList;
2348 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2350 while (!WorkList.empty()) {
2351 // Grab a record representing a case range to process off the worklist
2352 CaseRec CR = WorkList.back();
2353 WorkList.pop_back();
2355 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2358 // If the range has few cases (two or less) emit a series of specific
2360 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2363 // If the switch has more than 5 blocks, and at least 40% dense, and the
2364 // target supports indirect branches, then emit a jump table rather than
2365 // lowering the switch to a binary tree of conditional branches.
2366 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2369 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2370 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2371 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2376 void SelectionDAGLowering::visitSub(User &I) {
2377 // -0.0 - X --> fneg
2378 const Type *Ty = I.getType();
2379 if (isa<VectorType>(Ty)) {
2380 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2381 const VectorType *DestTy = cast<VectorType>(I.getType());
2382 const Type *ElTy = DestTy->getElementType();
2383 if (ElTy->isFloatingPoint()) {
2384 unsigned VL = DestTy->getNumElements();
2385 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2386 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2388 SDValue Op2 = getValue(I.getOperand(1));
2389 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2395 if (Ty->isFloatingPoint()) {
2396 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2397 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2398 SDValue Op2 = getValue(I.getOperand(1));
2399 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2404 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2407 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2408 SDValue Op1 = getValue(I.getOperand(0));
2409 SDValue Op2 = getValue(I.getOperand(1));
2411 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2414 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2415 SDValue Op1 = getValue(I.getOperand(0));
2416 SDValue Op2 = getValue(I.getOperand(1));
2417 if (!isa<VectorType>(I.getType())) {
2418 if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType()))
2419 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2420 else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2421 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2424 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2427 void SelectionDAGLowering::visitICmp(User &I) {
2428 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2429 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2430 predicate = IC->getPredicate();
2431 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2432 predicate = ICmpInst::Predicate(IC->getPredicate());
2433 SDValue Op1 = getValue(I.getOperand(0));
2434 SDValue Op2 = getValue(I.getOperand(1));
2435 ISD::CondCode Opcode;
2436 switch (predicate) {
2437 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2438 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2439 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2440 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2441 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2442 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2443 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2444 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2445 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2446 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2448 assert(!"Invalid ICmp predicate value");
2449 Opcode = ISD::SETEQ;
2452 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2455 void SelectionDAGLowering::visitFCmp(User &I) {
2456 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2457 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2458 predicate = FC->getPredicate();
2459 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2460 predicate = FCmpInst::Predicate(FC->getPredicate());
2461 SDValue Op1 = getValue(I.getOperand(0));
2462 SDValue Op2 = getValue(I.getOperand(1));
2463 ISD::CondCode Condition, FOC, FPC;
2464 switch (predicate) {
2465 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2466 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2467 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2468 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2469 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2470 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2471 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2472 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2473 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2474 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2475 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2476 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2477 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2478 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2479 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2480 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2482 assert(!"Invalid FCmp predicate value");
2483 FOC = FPC = ISD::SETFALSE;
2486 if (FiniteOnlyFPMath())
2490 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2493 void SelectionDAGLowering::visitVICmp(User &I) {
2494 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2495 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2496 predicate = IC->getPredicate();
2497 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2498 predicate = ICmpInst::Predicate(IC->getPredicate());
2499 SDValue Op1 = getValue(I.getOperand(0));
2500 SDValue Op2 = getValue(I.getOperand(1));
2501 ISD::CondCode Opcode;
2502 switch (predicate) {
2503 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2504 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2505 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2506 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2507 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2508 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2509 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2510 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2511 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2512 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2514 assert(!"Invalid ICmp predicate value");
2515 Opcode = ISD::SETEQ;
2518 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2521 void SelectionDAGLowering::visitVFCmp(User &I) {
2522 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2523 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2524 predicate = FC->getPredicate();
2525 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2526 predicate = FCmpInst::Predicate(FC->getPredicate());
2527 SDValue Op1 = getValue(I.getOperand(0));
2528 SDValue Op2 = getValue(I.getOperand(1));
2529 ISD::CondCode Condition, FOC, FPC;
2530 switch (predicate) {
2531 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2532 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2533 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2534 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2535 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2536 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2537 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2538 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2539 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2540 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2541 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2542 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2543 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2544 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2545 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2546 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2548 assert(!"Invalid VFCmp predicate value");
2549 FOC = FPC = ISD::SETFALSE;
2552 if (FiniteOnlyFPMath())
2557 MVT DestVT = TLI.getValueType(I.getType());
2559 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2562 void SelectionDAGLowering::visitSelect(User &I) {
2563 SDValue Cond = getValue(I.getOperand(0));
2564 SDValue TrueVal = getValue(I.getOperand(1));
2565 SDValue FalseVal = getValue(I.getOperand(2));
2566 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2567 TrueVal, FalseVal));
2571 void SelectionDAGLowering::visitTrunc(User &I) {
2572 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2573 SDValue N = getValue(I.getOperand(0));
2574 MVT DestVT = TLI.getValueType(I.getType());
2575 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2578 void SelectionDAGLowering::visitZExt(User &I) {
2579 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2580 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2581 SDValue N = getValue(I.getOperand(0));
2582 MVT DestVT = TLI.getValueType(I.getType());
2583 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2586 void SelectionDAGLowering::visitSExt(User &I) {
2587 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2588 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2589 SDValue N = getValue(I.getOperand(0));
2590 MVT DestVT = TLI.getValueType(I.getType());
2591 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2594 void SelectionDAGLowering::visitFPTrunc(User &I) {
2595 // FPTrunc is never a no-op cast, no need to check
2596 SDValue N = getValue(I.getOperand(0));
2597 MVT DestVT = TLI.getValueType(I.getType());
2598 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2601 void SelectionDAGLowering::visitFPExt(User &I){
2602 // FPTrunc is never a no-op cast, no need to check
2603 SDValue N = getValue(I.getOperand(0));
2604 MVT DestVT = TLI.getValueType(I.getType());
2605 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2608 void SelectionDAGLowering::visitFPToUI(User &I) {
2609 // FPToUI is never a no-op cast, no need to check
2610 SDValue N = getValue(I.getOperand(0));
2611 MVT DestVT = TLI.getValueType(I.getType());
2612 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2615 void SelectionDAGLowering::visitFPToSI(User &I) {
2616 // FPToSI is never a no-op cast, no need to check
2617 SDValue N = getValue(I.getOperand(0));
2618 MVT DestVT = TLI.getValueType(I.getType());
2619 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2622 void SelectionDAGLowering::visitUIToFP(User &I) {
2623 // UIToFP is never a no-op cast, no need to check
2624 SDValue N = getValue(I.getOperand(0));
2625 MVT DestVT = TLI.getValueType(I.getType());
2626 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2629 void SelectionDAGLowering::visitSIToFP(User &I){
2630 // UIToFP is never a no-op cast, no need to check
2631 SDValue N = getValue(I.getOperand(0));
2632 MVT DestVT = TLI.getValueType(I.getType());
2633 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2636 void SelectionDAGLowering::visitPtrToInt(User &I) {
2637 // What to do depends on the size of the integer and the size of the pointer.
2638 // We can either truncate, zero extend, or no-op, accordingly.
2639 SDValue N = getValue(I.getOperand(0));
2640 MVT SrcVT = N.getValueType();
2641 MVT DestVT = TLI.getValueType(I.getType());
2643 if (DestVT.bitsLT(SrcVT))
2644 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2646 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2647 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2648 setValue(&I, Result);
2651 void SelectionDAGLowering::visitIntToPtr(User &I) {
2652 // What to do depends on the size of the integer and the size of the pointer.
2653 // We can either truncate, zero extend, or no-op, accordingly.
2654 SDValue N = getValue(I.getOperand(0));
2655 MVT SrcVT = N.getValueType();
2656 MVT DestVT = TLI.getValueType(I.getType());
2657 if (DestVT.bitsLT(SrcVT))
2658 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2660 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2661 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2664 void SelectionDAGLowering::visitBitCast(User &I) {
2665 SDValue N = getValue(I.getOperand(0));
2666 MVT DestVT = TLI.getValueType(I.getType());
2668 // BitCast assures us that source and destination are the same size so this
2669 // is either a BIT_CONVERT or a no-op.
2670 if (DestVT != N.getValueType())
2671 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2673 setValue(&I, N); // noop cast.
2676 void SelectionDAGLowering::visitInsertElement(User &I) {
2677 SDValue InVec = getValue(I.getOperand(0));
2678 SDValue InVal = getValue(I.getOperand(1));
2679 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2680 getValue(I.getOperand(2)));
2682 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2683 TLI.getValueType(I.getType()),
2684 InVec, InVal, InIdx));
2687 void SelectionDAGLowering::visitExtractElement(User &I) {
2688 SDValue InVec = getValue(I.getOperand(0));
2689 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2690 getValue(I.getOperand(1)));
2691 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2692 TLI.getValueType(I.getType()), InVec, InIdx));
2695 void SelectionDAGLowering::visitShuffleVector(User &I) {
2696 SDValue V1 = getValue(I.getOperand(0));
2697 SDValue V2 = getValue(I.getOperand(1));
2698 SDValue Mask = getValue(I.getOperand(2));
2700 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2701 TLI.getValueType(I.getType()),
2705 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2706 const Value *Op0 = I.getOperand(0);
2707 const Value *Op1 = I.getOperand(1);
2708 const Type *AggTy = I.getType();
2709 const Type *ValTy = Op1->getType();
2710 bool IntoUndef = isa<UndefValue>(Op0);
2711 bool FromUndef = isa<UndefValue>(Op1);
2713 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2714 I.idx_begin(), I.idx_end());
2716 SmallVector<MVT, 4> AggValueVTs;
2717 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2718 SmallVector<MVT, 4> ValValueVTs;
2719 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2721 unsigned NumAggValues = AggValueVTs.size();
2722 unsigned NumValValues = ValValueVTs.size();
2723 SmallVector<SDValue, 4> Values(NumAggValues);
2725 SDValue Agg = getValue(Op0);
2726 SDValue Val = getValue(Op1);
2728 // Copy the beginning value(s) from the original aggregate.
2729 for (; i != LinearIndex; ++i)
2730 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2731 SDValue(Agg.Val, Agg.ResNo + i);
2732 // Copy values from the inserted value(s).
2733 for (; i != LinearIndex + NumValValues; ++i)
2734 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2735 SDValue(Val.Val, Val.ResNo + i - LinearIndex);
2736 // Copy remaining value(s) from the original aggregate.
2737 for (; i != NumAggValues; ++i)
2738 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
2739 SDValue(Agg.Val, Agg.ResNo + i);
2741 setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
2742 &Values[0], NumAggValues));
2745 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2746 const Value *Op0 = I.getOperand(0);
2747 const Type *AggTy = Op0->getType();
2748 const Type *ValTy = I.getType();
2749 bool OutOfUndef = isa<UndefValue>(Op0);
2751 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2752 I.idx_begin(), I.idx_end());
2754 SmallVector<MVT, 4> ValValueVTs;
2755 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2757 unsigned NumValValues = ValValueVTs.size();
2758 SmallVector<SDValue, 4> Values(NumValValues);
2760 SDValue Agg = getValue(Op0);
2761 // Copy out the selected value(s).
2762 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2763 Values[i - LinearIndex] =
2764 OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
2765 SDValue(Agg.Val, Agg.ResNo + i);
2767 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
2768 &Values[0], NumValValues));
2772 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2773 SDValue N = getValue(I.getOperand(0));
2774 const Type *Ty = I.getOperand(0)->getType();
2776 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2779 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2780 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2783 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2784 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2785 DAG.getIntPtrConstant(Offset));
2787 Ty = StTy->getElementType(Field);
2789 Ty = cast<SequentialType>(Ty)->getElementType();
2791 // If this is a constant subscript, handle it quickly.
2792 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2793 if (CI->getZExtValue() == 0) continue;
2795 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2796 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2797 DAG.getIntPtrConstant(Offs));
2801 // N = N + Idx * ElementSize;
2802 uint64_t ElementSize = TD->getABITypeSize(Ty);
2803 SDValue IdxN = getValue(Idx);
2805 // If the index is smaller or larger than intptr_t, truncate or extend
2807 if (IdxN.getValueType().bitsLT(N.getValueType())) {
2808 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2809 } else if (IdxN.getValueType().bitsGT(N.getValueType()))
2810 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2812 // If this is a multiply by a power of two, turn it into a shl
2813 // immediately. This is a very common case.
2814 if (isPowerOf2_64(ElementSize)) {
2815 unsigned Amt = Log2_64(ElementSize);
2816 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2817 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2818 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2822 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2823 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2824 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2830 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2831 // If this is a fixed sized alloca in the entry block of the function,
2832 // allocate it statically on the stack.
2833 if (FuncInfo.StaticAllocaMap.count(&I))
2834 return; // getValue will auto-populate this.
2836 const Type *Ty = I.getAllocatedType();
2837 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2839 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2842 SDValue AllocSize = getValue(I.getArraySize());
2843 MVT IntPtr = TLI.getPointerTy();
2844 if (IntPtr.bitsLT(AllocSize.getValueType()))
2845 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2846 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2847 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2849 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2850 DAG.getIntPtrConstant(TySize));
2852 // Handle alignment. If the requested alignment is less than or equal to
2853 // the stack alignment, ignore it. If the size is greater than or equal to
2854 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2855 unsigned StackAlign =
2856 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2857 if (Align <= StackAlign)
2860 // Round the size of the allocation up to the stack alignment size
2861 // by add SA-1 to the size.
2862 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2863 DAG.getIntPtrConstant(StackAlign-1));
2864 // Mask out the low bits for alignment purposes.
2865 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2866 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2868 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2869 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2871 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2873 DAG.setRoot(DSA.getValue(1));
2875 // Inform the Frame Information that we have just allocated a variable-sized
2877 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2880 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2881 const Value *SV = I.getOperand(0);
2882 SDValue Ptr = getValue(SV);
2884 const Type *Ty = I.getType();
2885 bool isVolatile = I.isVolatile();
2886 unsigned Alignment = I.getAlignment();
2888 SmallVector<MVT, 4> ValueVTs;
2889 SmallVector<uint64_t, 4> Offsets;
2890 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2891 unsigned NumValues = ValueVTs.size();
2896 bool ConstantMemory = false;
2898 // Serialize volatile loads with other side effects.
2900 else if (AA.pointsToConstantMemory(SV)) {
2901 // Do not serialize (non-volatile) loads of constant memory with anything.
2902 Root = DAG.getEntryNode();
2903 ConstantMemory = true;
2905 // Do not serialize non-volatile loads against each other.
2906 Root = DAG.getRoot();
2909 SmallVector<SDValue, 4> Values(NumValues);
2910 SmallVector<SDValue, 4> Chains(NumValues);
2911 MVT PtrVT = Ptr.getValueType();
2912 for (unsigned i = 0; i != NumValues; ++i) {
2913 SDValue L = DAG.getLoad(ValueVTs[i], Root,
2914 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2915 DAG.getConstant(Offsets[i], PtrVT)),
2917 isVolatile, Alignment);
2919 Chains[i] = L.getValue(1);
2922 if (!ConstantMemory) {
2923 SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2924 &Chains[0], NumValues);
2928 PendingLoads.push_back(Chain);
2931 setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
2932 &Values[0], NumValues));
2936 void SelectionDAGLowering::visitStore(StoreInst &I) {
2937 Value *SrcV = I.getOperand(0);
2938 Value *PtrV = I.getOperand(1);
2940 SmallVector<MVT, 4> ValueVTs;
2941 SmallVector<uint64_t, 4> Offsets;
2942 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2943 unsigned NumValues = ValueVTs.size();
2947 // Get the lowered operands. Note that we do this after
2948 // checking if NumResults is zero, because with zero results
2949 // the operands won't have values in the map.
2950 SDValue Src = getValue(SrcV);
2951 SDValue Ptr = getValue(PtrV);
2953 SDValue Root = getRoot();
2954 SmallVector<SDValue, 4> Chains(NumValues);
2955 MVT PtrVT = Ptr.getValueType();
2956 bool isVolatile = I.isVolatile();
2957 unsigned Alignment = I.getAlignment();
2958 for (unsigned i = 0; i != NumValues; ++i)
2959 Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i),
2960 DAG.getNode(ISD::ADD, PtrVT, Ptr,
2961 DAG.getConstant(Offsets[i], PtrVT)),
2963 isVolatile, Alignment);
2965 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues));
2968 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2970 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2971 unsigned Intrinsic) {
2972 bool HasChain = !I.doesNotAccessMemory();
2973 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2975 // Build the operand list.
2976 SmallVector<SDValue, 8> Ops;
2977 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2979 // We don't need to serialize loads against other loads.
2980 Ops.push_back(DAG.getRoot());
2982 Ops.push_back(getRoot());
2986 // Add the intrinsic ID as an integer operand.
2987 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2989 // Add all operands of the call to the operand list.
2990 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2991 SDValue Op = getValue(I.getOperand(i));
2992 assert(TLI.isTypeLegal(Op.getValueType()) &&
2993 "Intrinsic uses a non-legal type?");
2997 std::vector<MVT> VTs;
2998 if (I.getType() != Type::VoidTy) {
2999 MVT VT = TLI.getValueType(I.getType());
3000 if (VT.isVector()) {
3001 const VectorType *DestTy = cast<VectorType>(I.getType());
3002 MVT EltVT = TLI.getValueType(DestTy->getElementType());
3004 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
3005 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
3008 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
3012 VTs.push_back(MVT::Other);
3014 const MVT *VTList = DAG.getNodeValueTypes(VTs);
3019 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
3020 &Ops[0], Ops.size());
3021 else if (I.getType() != Type::VoidTy)
3022 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
3023 &Ops[0], Ops.size());
3025 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
3026 &Ops[0], Ops.size());
3029 SDValue Chain = Result.getValue(Result.Val->getNumValues()-1);
3031 PendingLoads.push_back(Chain);
3035 if (I.getType() != Type::VoidTy) {
3036 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3037 MVT VT = TLI.getValueType(PTy);
3038 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
3040 setValue(&I, Result);
3044 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3045 static GlobalVariable *ExtractTypeInfo (Value *V) {
3046 V = V->stripPointerCasts();
3047 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3048 assert ((GV || isa<ConstantPointerNull>(V)) &&
3049 "TypeInfo must be a global variable or NULL");
3053 /// addCatchInfo - Extract the personality and type infos from an eh.selector
3054 /// call, and add them to the specified machine basic block.
3055 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3056 MachineBasicBlock *MBB) {
3057 // Inform the MachineModuleInfo of the personality for this landing pad.
3058 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3059 assert(CE->getOpcode() == Instruction::BitCast &&
3060 isa<Function>(CE->getOperand(0)) &&
3061 "Personality should be a function");
3062 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3064 // Gather all the type infos for this landing pad and pass them along to
3065 // MachineModuleInfo.
3066 std::vector<GlobalVariable *> TyInfo;
3067 unsigned N = I.getNumOperands();
3069 for (unsigned i = N - 1; i > 2; --i) {
3070 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3071 unsigned FilterLength = CI->getZExtValue();
3072 unsigned FirstCatch = i + FilterLength + !FilterLength;
3073 assert (FirstCatch <= N && "Invalid filter length");
3075 if (FirstCatch < N) {
3076 TyInfo.reserve(N - FirstCatch);
3077 for (unsigned j = FirstCatch; j < N; ++j)
3078 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3079 MMI->addCatchTypeInfo(MBB, TyInfo);
3083 if (!FilterLength) {
3085 MMI->addCleanup(MBB);
3088 TyInfo.reserve(FilterLength - 1);
3089 for (unsigned j = i + 1; j < FirstCatch; ++j)
3090 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3091 MMI->addFilterTypeInfo(MBB, TyInfo);
3100 TyInfo.reserve(N - 3);
3101 for (unsigned j = 3; j < N; ++j)
3102 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3103 MMI->addCatchTypeInfo(MBB, TyInfo);
3108 /// Inlined utility function to implement binary input atomic intrinsics for
3109 // visitIntrinsicCall: I is a call instruction
3110 // Op is the associated NodeType for I
3112 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3113 SDValue Root = getRoot();
3114 SDValue L = DAG.getAtomic(Op, Root,
3115 getValue(I.getOperand(1)),
3116 getValue(I.getOperand(2)),
3119 DAG.setRoot(L.getValue(1));
3123 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3124 /// we want to emit this as a call to a named external function, return the name
3125 /// otherwise lower it and return null.
3127 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3128 switch (Intrinsic) {
3130 // By default, turn this into a target intrinsic node.
3131 visitTargetIntrinsic(I, Intrinsic);
3133 case Intrinsic::vastart: visitVAStart(I); return 0;
3134 case Intrinsic::vaend: visitVAEnd(I); return 0;
3135 case Intrinsic::vacopy: visitVACopy(I); return 0;
3136 case Intrinsic::returnaddress:
3137 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
3138 getValue(I.getOperand(1))));
3140 case Intrinsic::frameaddress:
3141 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
3142 getValue(I.getOperand(1))));
3144 case Intrinsic::setjmp:
3145 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3147 case Intrinsic::longjmp:
3148 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3150 case Intrinsic::memcpy_i32:
3151 case Intrinsic::memcpy_i64: {
3152 SDValue Op1 = getValue(I.getOperand(1));
3153 SDValue Op2 = getValue(I.getOperand(2));
3154 SDValue Op3 = getValue(I.getOperand(3));
3155 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3156 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3157 I.getOperand(1), 0, I.getOperand(2), 0));
3160 case Intrinsic::memset_i32:
3161 case Intrinsic::memset_i64: {
3162 SDValue Op1 = getValue(I.getOperand(1));
3163 SDValue Op2 = getValue(I.getOperand(2));
3164 SDValue Op3 = getValue(I.getOperand(3));
3165 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3166 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
3167 I.getOperand(1), 0));
3170 case Intrinsic::memmove_i32:
3171 case Intrinsic::memmove_i64: {
3172 SDValue Op1 = getValue(I.getOperand(1));
3173 SDValue Op2 = getValue(I.getOperand(2));
3174 SDValue Op3 = getValue(I.getOperand(3));
3175 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3177 // If the source and destination are known to not be aliases, we can
3178 // lower memmove as memcpy.
3179 uint64_t Size = -1ULL;
3180 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3181 Size = C->getValue();
3182 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3183 AliasAnalysis::NoAlias) {
3184 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
3185 I.getOperand(1), 0, I.getOperand(2), 0));
3189 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
3190 I.getOperand(1), 0, I.getOperand(2), 0));
3193 case Intrinsic::dbg_stoppoint: {
3194 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3195 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3196 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
3197 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
3198 assert(DD && "Not a debug information descriptor");
3199 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3202 cast<CompileUnitDesc>(DD)));
3207 case Intrinsic::dbg_region_start: {
3208 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3209 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3210 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
3211 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
3212 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3217 case Intrinsic::dbg_region_end: {
3218 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3219 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3220 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
3221 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
3222 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
3227 case Intrinsic::dbg_func_start: {
3228 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3230 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3231 Value *SP = FSI.getSubprogram();
3232 if (SP && MMI->Verify(SP)) {
3233 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3234 // what (most?) gdb expects.
3235 DebugInfoDesc *DD = MMI->getDescFor(SP);
3236 assert(DD && "Not a debug information descriptor");
3237 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
3238 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
3239 unsigned SrcFile = MMI->RecordSource(CompileUnit);
3240 // Record the source line but does create a label. It will be emitted
3241 // at asm emission time.
3242 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3247 case Intrinsic::dbg_declare: {
3248 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3249 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3250 Value *Variable = DI.getVariable();
3251 if (MMI && Variable && MMI->Verify(Variable))
3252 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3253 getValue(DI.getAddress()), getValue(Variable)));
3257 case Intrinsic::eh_exception: {
3258 if (!CurMBB->isLandingPad()) {
3259 // FIXME: Mark exception register as live in. Hack for PR1508.
3260 unsigned Reg = TLI.getExceptionAddressRegister();
3261 if (Reg) CurMBB->addLiveIn(Reg);
3263 // Insert the EXCEPTIONADDR instruction.
3264 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3266 Ops[0] = DAG.getRoot();
3267 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3269 DAG.setRoot(Op.getValue(1));
3273 case Intrinsic::eh_selector_i32:
3274 case Intrinsic::eh_selector_i64: {
3275 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3276 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3277 MVT::i32 : MVT::i64);
3280 if (CurMBB->isLandingPad())
3281 addCatchInfo(I, MMI, CurMBB);
3284 FuncInfo.CatchInfoLost.insert(&I);
3286 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3287 unsigned Reg = TLI.getExceptionSelectorRegister();
3288 if (Reg) CurMBB->addLiveIn(Reg);
3291 // Insert the EHSELECTION instruction.
3292 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3294 Ops[0] = getValue(I.getOperand(1));
3296 SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3298 DAG.setRoot(Op.getValue(1));
3300 setValue(&I, DAG.getConstant(0, VT));
3306 case Intrinsic::eh_typeid_for_i32:
3307 case Intrinsic::eh_typeid_for_i64: {
3308 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3309 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3310 MVT::i32 : MVT::i64);
3313 // Find the type id for the given typeinfo.
3314 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3316 unsigned TypeID = MMI->getTypeIDFor(GV);
3317 setValue(&I, DAG.getConstant(TypeID, VT));
3319 // Return something different to eh_selector.
3320 setValue(&I, DAG.getConstant(1, VT));
3326 case Intrinsic::eh_return: {
3327 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3330 MMI->setCallsEHReturn(true);
3331 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3334 getValue(I.getOperand(1)),
3335 getValue(I.getOperand(2))));
3337 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3343 case Intrinsic::eh_unwind_init: {
3344 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3345 MMI->setCallsUnwindInit(true);
3351 case Intrinsic::eh_dwarf_cfa: {
3352 MVT VT = getValue(I.getOperand(1)).getValueType();
3354 if (VT.bitsGT(TLI.getPointerTy()))
3355 CfaArg = DAG.getNode(ISD::TRUNCATE,
3356 TLI.getPointerTy(), getValue(I.getOperand(1)));
3358 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3359 TLI.getPointerTy(), getValue(I.getOperand(1)));
3361 SDValue Offset = DAG.getNode(ISD::ADD,
3363 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3364 TLI.getPointerTy()),
3366 setValue(&I, DAG.getNode(ISD::ADD,
3368 DAG.getNode(ISD::FRAMEADDR,
3371 TLI.getPointerTy())),
3376 case Intrinsic::sqrt:
3377 setValue(&I, DAG.getNode(ISD::FSQRT,
3378 getValue(I.getOperand(1)).getValueType(),
3379 getValue(I.getOperand(1))));
3381 case Intrinsic::powi:
3382 setValue(&I, DAG.getNode(ISD::FPOWI,
3383 getValue(I.getOperand(1)).getValueType(),
3384 getValue(I.getOperand(1)),
3385 getValue(I.getOperand(2))));
3387 case Intrinsic::sin:
3388 setValue(&I, DAG.getNode(ISD::FSIN,
3389 getValue(I.getOperand(1)).getValueType(),
3390 getValue(I.getOperand(1))));
3392 case Intrinsic::cos:
3393 setValue(&I, DAG.getNode(ISD::FCOS,
3394 getValue(I.getOperand(1)).getValueType(),
3395 getValue(I.getOperand(1))));
3397 case Intrinsic::pow:
3398 setValue(&I, DAG.getNode(ISD::FPOW,
3399 getValue(I.getOperand(1)).getValueType(),
3400 getValue(I.getOperand(1)),
3401 getValue(I.getOperand(2))));
3403 case Intrinsic::pcmarker: {
3404 SDValue Tmp = getValue(I.getOperand(1));
3405 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3408 case Intrinsic::readcyclecounter: {
3409 SDValue Op = getRoot();
3410 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3411 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3414 DAG.setRoot(Tmp.getValue(1));
3417 case Intrinsic::part_select: {
3418 // Currently not implemented: just abort
3419 assert(0 && "part_select intrinsic not implemented");
3422 case Intrinsic::part_set: {
3423 // Currently not implemented: just abort
3424 assert(0 && "part_set intrinsic not implemented");
3427 case Intrinsic::bswap:
3428 setValue(&I, DAG.getNode(ISD::BSWAP,
3429 getValue(I.getOperand(1)).getValueType(),
3430 getValue(I.getOperand(1))));
3432 case Intrinsic::cttz: {
3433 SDValue Arg = getValue(I.getOperand(1));
3434 MVT Ty = Arg.getValueType();
3435 SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3436 setValue(&I, result);
3439 case Intrinsic::ctlz: {
3440 SDValue Arg = getValue(I.getOperand(1));
3441 MVT Ty = Arg.getValueType();
3442 SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3443 setValue(&I, result);
3446 case Intrinsic::ctpop: {
3447 SDValue Arg = getValue(I.getOperand(1));
3448 MVT Ty = Arg.getValueType();
3449 SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3450 setValue(&I, result);
3453 case Intrinsic::stacksave: {
3454 SDValue Op = getRoot();
3455 SDValue Tmp = DAG.getNode(ISD::STACKSAVE,
3456 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3458 DAG.setRoot(Tmp.getValue(1));
3461 case Intrinsic::stackrestore: {
3462 SDValue Tmp = getValue(I.getOperand(1));
3463 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3466 case Intrinsic::var_annotation:
3467 // Discard annotate attributes
3470 case Intrinsic::init_trampoline: {
3471 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3475 Ops[1] = getValue(I.getOperand(1));
3476 Ops[2] = getValue(I.getOperand(2));
3477 Ops[3] = getValue(I.getOperand(3));
3478 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3479 Ops[5] = DAG.getSrcValue(F);
3481 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE,
3482 DAG.getNodeValueTypes(TLI.getPointerTy(),
3487 DAG.setRoot(Tmp.getValue(1));
3491 case Intrinsic::gcroot:
3493 Value *Alloca = I.getOperand(1);
3494 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3496 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3497 GCI->addStackRoot(FI->getIndex(), TypeMap);
3501 case Intrinsic::gcread:
3502 case Intrinsic::gcwrite:
3503 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3506 case Intrinsic::flt_rounds: {
3507 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3511 case Intrinsic::trap: {
3512 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3515 case Intrinsic::prefetch: {
3518 Ops[1] = getValue(I.getOperand(1));
3519 Ops[2] = getValue(I.getOperand(2));
3520 Ops[3] = getValue(I.getOperand(3));
3521 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3525 case Intrinsic::memory_barrier: {
3528 for (int x = 1; x < 6; ++x)
3529 Ops[x] = getValue(I.getOperand(x));
3531 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3534 case Intrinsic::atomic_cmp_swap: {
3535 SDValue Root = getRoot();
3536 SDValue L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, Root,
3537 getValue(I.getOperand(1)),
3538 getValue(I.getOperand(2)),
3539 getValue(I.getOperand(3)),
3542 DAG.setRoot(L.getValue(1));
3545 case Intrinsic::atomic_load_add:
3546 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
3547 case Intrinsic::atomic_load_sub:
3548 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
3549 case Intrinsic::atomic_load_and:
3550 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
3551 case Intrinsic::atomic_load_or:
3552 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
3553 case Intrinsic::atomic_load_xor:
3554 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
3555 case Intrinsic::atomic_load_nand:
3556 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
3557 case Intrinsic::atomic_load_min:
3558 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
3559 case Intrinsic::atomic_load_max:
3560 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
3561 case Intrinsic::atomic_load_umin:
3562 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
3563 case Intrinsic::atomic_load_umax:
3564 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
3565 case Intrinsic::atomic_swap:
3566 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
3571 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
3573 MachineBasicBlock *LandingPad) {
3574 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3575 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3576 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3577 unsigned BeginLabel = 0, EndLabel = 0;
3579 TargetLowering::ArgListTy Args;
3580 TargetLowering::ArgListEntry Entry;
3581 Args.reserve(CS.arg_size());
3582 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3584 SDValue ArgNode = getValue(*i);
3585 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3587 unsigned attrInd = i - CS.arg_begin() + 1;
3588 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3589 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3590 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3591 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3592 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3593 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3594 Entry.Alignment = CS.getParamAlignment(attrInd);
3595 Args.push_back(Entry);
3598 if (LandingPad && MMI) {
3599 // Insert a label before the invoke call to mark the try range. This can be
3600 // used to detect deletion of the invoke via the MachineModuleInfo.
3601 BeginLabel = MMI->NextLabelID();
3602 // Both PendingLoads and PendingExports must be flushed here;
3603 // this call might not return.
3605 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
3608 std::pair<SDValue,SDValue> Result =
3609 TLI.LowerCallTo(getRoot(), CS.getType(),
3610 CS.paramHasAttr(0, ParamAttr::SExt),
3611 CS.paramHasAttr(0, ParamAttr::ZExt),
3612 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3614 if (CS.getType() != Type::VoidTy)
3615 setValue(CS.getInstruction(), Result.first);
3616 DAG.setRoot(Result.second);
3618 if (LandingPad && MMI) {
3619 // Insert a label at the end of the invoke call to mark the try range. This
3620 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3621 EndLabel = MMI->NextLabelID();
3622 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
3624 // Inform MachineModuleInfo of range.
3625 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3630 void SelectionDAGLowering::visitCall(CallInst &I) {
3631 const char *RenameFn = 0;
3632 if (Function *F = I.getCalledFunction()) {
3633 if (F->isDeclaration()) {
3634 if (unsigned IID = F->getIntrinsicID()) {
3635 RenameFn = visitIntrinsicCall(I, IID);
3641 // Check for well-known libc/libm calls. If the function is internal, it
3642 // can't be a library call.
3643 unsigned NameLen = F->getNameLen();
3644 if (!F->hasInternalLinkage() && NameLen) {
3645 const char *NameStr = F->getNameStart();
3646 if (NameStr[0] == 'c' &&
3647 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3648 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3649 if (I.getNumOperands() == 3 && // Basic sanity checks.
3650 I.getOperand(1)->getType()->isFloatingPoint() &&
3651 I.getType() == I.getOperand(1)->getType() &&
3652 I.getType() == I.getOperand(2)->getType()) {
3653 SDValue LHS = getValue(I.getOperand(1));
3654 SDValue RHS = getValue(I.getOperand(2));
3655 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3659 } else if (NameStr[0] == 'f' &&
3660 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3661 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3662 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3663 if (I.getNumOperands() == 2 && // Basic sanity checks.
3664 I.getOperand(1)->getType()->isFloatingPoint() &&
3665 I.getType() == I.getOperand(1)->getType()) {
3666 SDValue Tmp = getValue(I.getOperand(1));
3667 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3670 } else if (NameStr[0] == 's' &&
3671 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3672 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3673 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3674 if (I.getNumOperands() == 2 && // Basic sanity checks.
3675 I.getOperand(1)->getType()->isFloatingPoint() &&
3676 I.getType() == I.getOperand(1)->getType()) {
3677 SDValue Tmp = getValue(I.getOperand(1));
3678 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3681 } else if (NameStr[0] == 'c' &&
3682 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3683 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3684 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3685 if (I.getNumOperands() == 2 && // Basic sanity checks.
3686 I.getOperand(1)->getType()->isFloatingPoint() &&
3687 I.getType() == I.getOperand(1)->getType()) {
3688 SDValue Tmp = getValue(I.getOperand(1));
3689 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3694 } else if (isa<InlineAsm>(I.getOperand(0))) {
3701 Callee = getValue(I.getOperand(0));
3703 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3705 LowerCallTo(&I, Callee, I.isTailCall());
3709 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3710 /// this value and returns the result as a ValueVT value. This uses
3711 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3712 /// If the Flag pointer is NULL, no flag is used.
3713 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3715 SDValue *Flag) const {
3716 // Assemble the legal parts into the final values.
3717 SmallVector<SDValue, 4> Values(ValueVTs.size());
3718 SmallVector<SDValue, 8> Parts;
3719 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3720 // Copy the legal parts from the registers.
3721 MVT ValueVT = ValueVTs[Value];
3722 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3723 MVT RegisterVT = RegVTs[Value];
3725 Parts.resize(NumRegs);
3726 for (unsigned i = 0; i != NumRegs; ++i) {
3729 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3731 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
3732 *Flag = P.getValue(2);
3734 Chain = P.getValue(1);
3736 // If the source register was virtual and if we know something about it,
3737 // add an assert node.
3738 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
3739 RegisterVT.isInteger() && !RegisterVT.isVector()) {
3740 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
3741 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
3742 if (FLI.LiveOutRegInfo.size() > SlotNo) {
3743 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
3745 unsigned RegSize = RegisterVT.getSizeInBits();
3746 unsigned NumSignBits = LOI.NumSignBits;
3747 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
3749 // FIXME: We capture more information than the dag can represent. For
3750 // now, just use the tightest assertzext/assertsext possible.
3752 MVT FromVT(MVT::Other);
3753 if (NumSignBits == RegSize)
3754 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
3755 else if (NumZeroBits >= RegSize-1)
3756 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
3757 else if (NumSignBits > RegSize-8)
3758 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
3759 else if (NumZeroBits >= RegSize-9)
3760 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
3761 else if (NumSignBits > RegSize-16)
3762 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
3763 else if (NumZeroBits >= RegSize-17)
3764 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
3765 else if (NumSignBits > RegSize-32)
3766 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
3767 else if (NumZeroBits >= RegSize-33)
3768 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
3770 if (FromVT != MVT::Other) {
3771 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,
3772 RegisterVT, P, DAG.getValueType(FromVT));
3781 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3786 return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3787 &Values[0], ValueVTs.size());
3790 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3791 /// specified value into the registers specified by this object. This uses
3792 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3793 /// If the Flag pointer is NULL, no flag is used.
3794 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
3795 SDValue &Chain, SDValue *Flag) const {
3796 // Get the list of the values's legal parts.
3797 unsigned NumRegs = Regs.size();
3798 SmallVector<SDValue, 8> Parts(NumRegs);
3799 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3800 MVT ValueVT = ValueVTs[Value];
3801 unsigned NumParts = TLI->getNumRegisters(ValueVT);
3802 MVT RegisterVT = RegVTs[Value];
3804 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3805 &Parts[Part], NumParts, RegisterVT);
3809 // Copy the parts into the registers.
3810 SmallVector<SDValue, 8> Chains(NumRegs);
3811 for (unsigned i = 0; i != NumRegs; ++i) {
3814 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3816 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
3817 *Flag = Part.getValue(1);
3819 Chains[i] = Part.getValue(0);
3822 if (NumRegs == 1 || Flag)
3823 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
3824 // flagged to it. That is the CopyToReg nodes and the user are considered
3825 // a single scheduling unit. If we create a TokenFactor and return it as
3826 // chain, then the TokenFactor is both a predecessor (operand) of the
3827 // user as well as a successor (the TF operands are flagged to the user).
3828 // c1, f1 = CopyToReg
3829 // c2, f2 = CopyToReg
3830 // c3 = TokenFactor c1, c2
3833 Chain = Chains[NumRegs-1];
3835 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
3838 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3839 /// operand list. This adds the code marker and includes the number of
3840 /// values added into it.
3841 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3842 std::vector<SDValue> &Ops) const {
3843 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3844 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3845 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
3846 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
3847 MVT RegisterVT = RegVTs[Value];
3848 for (unsigned i = 0; i != NumRegs; ++i)
3849 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
3853 /// isAllocatableRegister - If the specified register is safe to allocate,
3854 /// i.e. it isn't a stack pointer or some other special register, return the
3855 /// register class for the register. Otherwise, return null.
3856 static const TargetRegisterClass *
3857 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3858 const TargetLowering &TLI,
3859 const TargetRegisterInfo *TRI) {
3860 MVT FoundVT = MVT::Other;
3861 const TargetRegisterClass *FoundRC = 0;
3862 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3863 E = TRI->regclass_end(); RCI != E; ++RCI) {
3864 MVT ThisVT = MVT::Other;
3866 const TargetRegisterClass *RC = *RCI;
3867 // If none of the the value types for this register class are valid, we
3868 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3869 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3871 if (TLI.isTypeLegal(*I)) {
3872 // If we have already found this register in a different register class,
3873 // choose the one with the largest VT specified. For example, on
3874 // PowerPC, we favor f64 register classes over f32.
3875 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
3882 if (ThisVT == MVT::Other) continue;
3884 // NOTE: This isn't ideal. In particular, this might allocate the
3885 // frame pointer in functions that need it (due to them not being taken
3886 // out of allocation, because a variable sized allocation hasn't been seen
3887 // yet). This is a slight code pessimization, but should still work.
3888 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3889 E = RC->allocation_order_end(MF); I != E; ++I)
3891 // We found a matching register class. Keep looking at others in case
3892 // we find one with larger registers that this physreg is also in.
3903 /// AsmOperandInfo - This contains information for each constraint that we are
3905 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3906 /// CallOperand - If this is the result output operand or a clobber
3907 /// this is null, otherwise it is the incoming operand to the CallInst.
3908 /// This gets modified as the asm is processed.
3909 SDValue CallOperand;
3911 /// AssignedRegs - If this is a register or register class operand, this
3912 /// contains the set of register corresponding to the operand.
3913 RegsForValue AssignedRegs;
3915 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3916 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3919 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3920 /// busy in OutputRegs/InputRegs.
3921 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3922 std::set<unsigned> &OutputRegs,
3923 std::set<unsigned> &InputRegs,
3924 const TargetRegisterInfo &TRI) const {
3926 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3927 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3930 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3931 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3936 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3938 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3939 const TargetRegisterInfo &TRI) {
3940 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3942 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3943 for (; *Aliases; ++Aliases)
3944 Regs.insert(*Aliases);
3947 } // end anon namespace.
3950 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3951 /// specified operand. We prefer to assign virtual registers, to allow the
3952 /// register allocator handle the assignment process. However, if the asm uses
3953 /// features that we can't model on machineinstrs, we have SDISel do the
3954 /// allocation. This produces generally horrible, but correct, code.
3956 /// OpInfo describes the operand.
3957 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3958 /// or any explicitly clobbered registers.
3959 /// Input and OutputRegs are the set of already allocated physical registers.
3961 void SelectionDAGLowering::
3962 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3963 std::set<unsigned> &OutputRegs,
3964 std::set<unsigned> &InputRegs) {
3965 // Compute whether this value requires an input register, an output register,
3967 bool isOutReg = false;
3968 bool isInReg = false;
3969 switch (OpInfo.Type) {
3970 case InlineAsm::isOutput:
3973 // If this is an early-clobber output, or if there is an input
3974 // constraint that matches this, we need to reserve the input register
3975 // so no other inputs allocate to it.
3976 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3978 case InlineAsm::isInput:
3982 case InlineAsm::isClobber:
3989 MachineFunction &MF = DAG.getMachineFunction();
3990 SmallVector<unsigned, 4> Regs;
3992 // If this is a constraint for a single physreg, or a constraint for a
3993 // register class, find it.
3994 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3995 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3996 OpInfo.ConstraintVT);
3998 unsigned NumRegs = 1;
3999 if (OpInfo.ConstraintVT != MVT::Other)
4000 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4002 MVT ValueVT = OpInfo.ConstraintVT;
4005 // If this is a constraint for a specific physical register, like {r17},
4007 if (PhysReg.first) {
4008 if (OpInfo.ConstraintVT == MVT::Other)
4009 ValueVT = *PhysReg.second->vt_begin();
4011 // Get the actual register value type. This is important, because the user
4012 // may have asked for (e.g.) the AX register in i32 type. We need to
4013 // remember that AX is actually i16 to get the right extension.
4014 RegVT = *PhysReg.second->vt_begin();
4016 // This is a explicit reference to a physical register.
4017 Regs.push_back(PhysReg.first);
4019 // If this is an expanded reference, add the rest of the regs to Regs.
4021 TargetRegisterClass::iterator I = PhysReg.second->begin();
4022 for (; *I != PhysReg.first; ++I)
4023 assert(I != PhysReg.second->end() && "Didn't find reg!");
4025 // Already added the first reg.
4027 for (; NumRegs; --NumRegs, ++I) {
4028 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4032 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4033 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4034 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4038 // Otherwise, if this was a reference to an LLVM register class, create vregs
4039 // for this reference.
4040 std::vector<unsigned> RegClassRegs;
4041 const TargetRegisterClass *RC = PhysReg.second;
4043 // If this is an early clobber or tied register, our regalloc doesn't know
4044 // how to maintain the constraint. If it isn't, go ahead and create vreg
4045 // and let the regalloc do the right thing.
4046 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
4047 // If there is some other early clobber and this is an input register,
4048 // then we are forced to pre-allocate the input reg so it doesn't
4049 // conflict with the earlyclobber.
4050 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
4051 RegVT = *PhysReg.second->vt_begin();
4053 if (OpInfo.ConstraintVT == MVT::Other)
4056 // Create the appropriate number of virtual registers.
4057 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4058 for (; NumRegs; --NumRegs)
4059 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
4061 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4065 // Otherwise, we can't allocate it. Let the code below figure out how to
4066 // maintain these constraints.
4067 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
4070 // This is a reference to a register class that doesn't directly correspond
4071 // to an LLVM register class. Allocate NumRegs consecutive, available,
4072 // registers from the class.
4073 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4074 OpInfo.ConstraintVT);
4077 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4078 unsigned NumAllocated = 0;
4079 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4080 unsigned Reg = RegClassRegs[i];
4081 // See if this register is available.
4082 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4083 (isInReg && InputRegs.count(Reg))) { // Already used.
4084 // Make sure we find consecutive registers.
4089 // Check to see if this register is allocatable (i.e. don't give out the
4092 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4093 if (!RC) { // Couldn't allocate this register.
4094 // Reset NumAllocated to make sure we return consecutive registers.
4100 // Okay, this register is good, we can use it.
4103 // If we allocated enough consecutive registers, succeed.
4104 if (NumAllocated == NumRegs) {
4105 unsigned RegStart = (i-NumAllocated)+1;
4106 unsigned RegEnd = i+1;
4107 // Mark all of the allocated registers used.
4108 for (unsigned i = RegStart; i != RegEnd; ++i)
4109 Regs.push_back(RegClassRegs[i]);
4111 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4112 OpInfo.ConstraintVT);
4113 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4118 // Otherwise, we couldn't allocate enough registers for this.
4122 /// visitInlineAsm - Handle a call to an InlineAsm object.
4124 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
4125 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
4127 /// ConstraintOperands - Information about all of the constraints.
4128 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
4130 SDValue Chain = getRoot();
4133 std::set<unsigned> OutputRegs, InputRegs;
4135 // Do a prepass over the constraints, canonicalizing them, and building up the
4136 // ConstraintOperands list.
4137 std::vector<InlineAsm::ConstraintInfo>
4138 ConstraintInfos = IA->ParseConstraints();
4140 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
4141 // constraint. If so, we can't let the register allocator allocate any input
4142 // registers, because it will not know to avoid the earlyclobbered output reg.
4143 bool SawEarlyClobber = false;
4145 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
4146 unsigned ResNo = 0; // ResNo - The result number of the next output.
4147 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
4148 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
4149 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
4151 MVT OpVT = MVT::Other;
4153 // Compute the value type for each operand.
4154 switch (OpInfo.Type) {
4155 case InlineAsm::isOutput:
4156 // Indirect outputs just consume an argument.
4157 if (OpInfo.isIndirect) {
4158 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4161 // The return value of the call is this value. As such, there is no
4162 // corresponding argument.
4163 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4164 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
4165 OpVT = TLI.getValueType(STy->getElementType(ResNo));
4167 assert(ResNo == 0 && "Asm only has one result!");
4168 OpVT = TLI.getValueType(CS.getType());
4172 case InlineAsm::isInput:
4173 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
4175 case InlineAsm::isClobber:
4180 // If this is an input or an indirect output, process the call argument.
4181 // BasicBlocks are labels, currently appearing only in asm's.
4182 if (OpInfo.CallOperandVal) {
4183 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
4184 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
4186 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
4187 const Type *OpTy = OpInfo.CallOperandVal->getType();
4188 // If this is an indirect operand, the operand is a pointer to the
4190 if (OpInfo.isIndirect)
4191 OpTy = cast<PointerType>(OpTy)->getElementType();
4193 // If OpTy is not a single value, it may be a struct/union that we
4194 // can tile with integers.
4195 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4196 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4204 OpTy = IntegerType::get(BitSize);
4209 OpVT = TLI.getValueType(OpTy, true);
4213 OpInfo.ConstraintVT = OpVT;
4215 // Compute the constraint code and ConstraintType to use.
4216 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
4218 // Keep track of whether we see an earlyclobber.
4219 SawEarlyClobber |= OpInfo.isEarlyClobber;
4221 // If we see a clobber of a register, it is an early clobber.
4222 if (!SawEarlyClobber &&
4223 OpInfo.Type == InlineAsm::isClobber &&
4224 OpInfo.ConstraintType == TargetLowering::C_Register) {
4225 // Note that we want to ignore things that we don't trick here, like
4226 // dirflag, fpsr, flags, etc.
4227 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4228 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4229 OpInfo.ConstraintVT);
4230 if (PhysReg.first || PhysReg.second) {
4231 // This is a register we know of.
4232 SawEarlyClobber = true;
4236 // If this is a memory input, and if the operand is not indirect, do what we
4237 // need to to provide an address for the memory input.
4238 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
4239 !OpInfo.isIndirect) {
4240 assert(OpInfo.Type == InlineAsm::isInput &&
4241 "Can only indirectify direct input operands!");
4243 // Memory operands really want the address of the value. If we don't have
4244 // an indirect input, put it in the constpool if we can, otherwise spill
4245 // it to a stack slot.
4247 // If the operand is a float, integer, or vector constant, spill to a
4248 // constant pool entry to get its address.
4249 Value *OpVal = OpInfo.CallOperandVal;
4250 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
4251 isa<ConstantVector>(OpVal)) {
4252 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
4253 TLI.getPointerTy());
4255 // Otherwise, create a stack slot and emit a store to it before the
4257 const Type *Ty = OpVal->getType();
4258 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
4259 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
4260 MachineFunction &MF = DAG.getMachineFunction();
4261 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
4262 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4263 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4264 OpInfo.CallOperand = StackSlot;
4267 // There is no longer a Value* corresponding to this operand.
4268 OpInfo.CallOperandVal = 0;
4269 // It is now an indirect operand.
4270 OpInfo.isIndirect = true;
4273 // If this constraint is for a specific register, allocate it before
4275 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4276 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4278 ConstraintInfos.clear();
4281 // Second pass - Loop over all of the operands, assigning virtual or physregs
4282 // to registerclass operands.
4283 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4284 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4286 // C_Register operands have already been allocated, Other/Memory don't need
4288 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4289 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4292 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4293 std::vector<SDValue> AsmNodeOperands;
4294 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
4295 AsmNodeOperands.push_back(
4296 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4299 // Loop over all of the inputs, copying the operand values into the
4300 // appropriate registers and processing the output regs.
4301 RegsForValue RetValRegs;
4303 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4304 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4306 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4307 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4309 switch (OpInfo.Type) {
4310 case InlineAsm::isOutput: {
4311 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4312 OpInfo.ConstraintType != TargetLowering::C_Register) {
4313 // Memory output, or 'other' output (e.g. 'X' constraint).
4314 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4316 // Add information to the INLINEASM node to know about this output.
4317 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4318 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4319 TLI.getPointerTy()));
4320 AsmNodeOperands.push_back(OpInfo.CallOperand);
4324 // Otherwise, this is a register or register class output.
4326 // Copy the output from the appropriate register. Find a register that
4328 if (OpInfo.AssignedRegs.Regs.empty()) {
4329 cerr << "Couldn't allocate output reg for constraint '"
4330 << OpInfo.ConstraintCode << "'!\n";
4334 // If this is an indirect operand, store through the pointer after the
4336 if (OpInfo.isIndirect) {
4337 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4338 OpInfo.CallOperandVal));
4340 // This is the result value of the call.
4341 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4342 // Concatenate this output onto the outputs list.
4343 RetValRegs.append(OpInfo.AssignedRegs);
4346 // Add information to the INLINEASM node to know that this register is
4348 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
4352 case InlineAsm::isInput: {
4353 SDValue InOperandVal = OpInfo.CallOperand;
4355 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4356 // If this is required to match an output register we have already set,
4357 // just use its register.
4358 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4360 // Scan until we find the definition we already emitted of this operand.
4361 // When we find it, create a RegsForValue operand.
4362 unsigned CurOp = 2; // The first operand.
4363 for (; OperandNo; --OperandNo) {
4364 // Advance to the next operand.
4366 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4367 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4368 (NumOps & 7) == 4 /*MEM*/) &&
4369 "Skipped past definitions?");
4370 CurOp += (NumOps>>3)+1;
4374 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4375 if ((NumOps & 7) == 2 /*REGDEF*/) {
4376 // Add NumOps>>3 registers to MatchedRegs.
4377 RegsForValue MatchedRegs;
4378 MatchedRegs.TLI = &TLI;
4379 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4380 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4381 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4383 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4384 MatchedRegs.Regs.push_back(Reg);
4387 // Use the produced MatchedRegs object to
4388 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4389 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4392 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
4393 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4394 // Add information to the INLINEASM node to know about this input.
4395 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4396 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4397 TLI.getPointerTy()));
4398 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4403 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4404 assert(!OpInfo.isIndirect &&
4405 "Don't know how to handle indirect other inputs yet!");
4407 std::vector<SDValue> Ops;
4408 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4411 cerr << "Invalid operand for inline asm constraint '"
4412 << OpInfo.ConstraintCode << "'!\n";
4416 // Add information to the INLINEASM node to know about this input.
4417 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4418 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4419 TLI.getPointerTy()));
4420 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4422 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4423 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4424 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4425 "Memory operands expect pointer values");
4427 // Add information to the INLINEASM node to know about this input.
4428 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4429 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4430 TLI.getPointerTy()));
4431 AsmNodeOperands.push_back(InOperandVal);
4435 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4436 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4437 "Unknown constraint type!");
4438 assert(!OpInfo.isIndirect &&
4439 "Don't know how to handle indirect register inputs yet!");
4441 // Copy the input into the appropriate registers.
4442 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4443 "Couldn't allocate input reg!");
4445 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4447 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4451 case InlineAsm::isClobber: {
4452 // Add the clobbered value to the operand list, so that the register
4453 // allocator is aware that the physreg got clobbered.
4454 if (!OpInfo.AssignedRegs.Regs.empty())
4455 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4462 // Finish up input operands.
4463 AsmNodeOperands[0] = Chain;
4464 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4466 Chain = DAG.getNode(ISD::INLINEASM,
4467 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4468 &AsmNodeOperands[0], AsmNodeOperands.size());
4469 Flag = Chain.getValue(1);
4471 // If this asm returns a register value, copy the result from that register
4472 // and set it as the value of the call.
4473 if (!RetValRegs.Regs.empty()) {
4474 SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4476 // If any of the results of the inline asm is a vector, it may have the
4477 // wrong width/num elts. This can happen for register classes that can
4478 // contain multiple different value types. The preg or vreg allocated may
4479 // not have the same VT as was expected. Convert it to the right type with
4481 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4482 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4483 if (Val.Val->getValueType(i).isVector())
4484 Val = DAG.getNode(ISD::BIT_CONVERT,
4485 TLI.getValueType(ResSTy->getElementType(i)), Val);
4488 if (Val.getValueType().isVector())
4489 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4493 setValue(CS.getInstruction(), Val);
4496 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
4498 // Process indirect outputs, first output all of the flagged copies out of
4500 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4501 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4502 Value *Ptr = IndirectStoresToEmit[i].second;
4503 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4504 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4507 // Emit the non-flagged stores from the physregs.
4508 SmallVector<SDValue, 8> OutChains;
4509 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4510 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4511 getValue(StoresToEmit[i].second),
4512 StoresToEmit[i].second, 0));
4513 if (!OutChains.empty())
4514 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4515 &OutChains[0], OutChains.size());
4520 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4521 SDValue Src = getValue(I.getOperand(0));
4523 MVT IntPtr = TLI.getPointerTy();
4525 if (IntPtr.bitsLT(Src.getValueType()))
4526 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4527 else if (IntPtr.bitsGT(Src.getValueType()))
4528 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4530 // Scale the source by the type size.
4531 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4532 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4533 Src, DAG.getIntPtrConstant(ElementSize));
4535 TargetLowering::ArgListTy Args;
4536 TargetLowering::ArgListEntry Entry;
4538 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4539 Args.push_back(Entry);
4541 std::pair<SDValue,SDValue> Result =
4542 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4543 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4544 setValue(&I, Result.first); // Pointers always fit in registers
4545 DAG.setRoot(Result.second);
4548 void SelectionDAGLowering::visitFree(FreeInst &I) {
4549 TargetLowering::ArgListTy Args;
4550 TargetLowering::ArgListEntry Entry;
4551 Entry.Node = getValue(I.getOperand(0));
4552 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4553 Args.push_back(Entry);
4554 MVT IntPtr = TLI.getPointerTy();
4555 std::pair<SDValue,SDValue> Result =
4556 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4557 CallingConv::C, true,
4558 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4559 DAG.setRoot(Result.second);
4562 // EmitInstrWithCustomInserter - This method should be implemented by targets
4563 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4564 // instructions are special in various ways, which require special support to
4565 // insert. The specified MachineInstr is created but not inserted into any
4566 // basic blocks, and the scheduler passes ownership of it to this method.
4567 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4568 MachineBasicBlock *MBB) {
4569 cerr << "If a target marks an instruction with "
4570 << "'usesCustomDAGSchedInserter', it must implement "
4571 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4576 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4577 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4578 getValue(I.getOperand(1)),
4579 DAG.getSrcValue(I.getOperand(1))));
4582 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4583 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4584 getValue(I.getOperand(0)),
4585 DAG.getSrcValue(I.getOperand(0)));
4587 DAG.setRoot(V.getValue(1));
4590 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4591 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4592 getValue(I.getOperand(1)),
4593 DAG.getSrcValue(I.getOperand(1))));
4596 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4597 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4598 getValue(I.getOperand(1)),
4599 getValue(I.getOperand(2)),
4600 DAG.getSrcValue(I.getOperand(1)),
4601 DAG.getSrcValue(I.getOperand(2))));
4604 /// TargetLowering::LowerArguments - This is the default LowerArguments
4605 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4606 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4607 /// integrated into SDISel.
4608 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
4609 SmallVectorImpl<SDValue> &ArgValues) {
4610 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4611 SmallVector<SDValue, 3+16> Ops;
4612 Ops.push_back(DAG.getRoot());
4613 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4614 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4616 // Add one result value for each formal argument.
4617 SmallVector<MVT, 16> RetVals;
4619 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4621 SmallVector<MVT, 4> ValueVTs;
4622 ComputeValueVTs(*this, I->getType(), ValueVTs);
4623 for (unsigned Value = 0, NumValues = ValueVTs.size();
4624 Value != NumValues; ++Value) {
4625 MVT VT = ValueVTs[Value];
4626 const Type *ArgTy = VT.getTypeForMVT();
4627 ISD::ArgFlagsTy Flags;
4628 unsigned OriginalAlignment =
4629 getTargetData()->getABITypeAlignment(ArgTy);
4631 if (F.paramHasAttr(j, ParamAttr::ZExt))
4633 if (F.paramHasAttr(j, ParamAttr::SExt))
4635 if (F.paramHasAttr(j, ParamAttr::InReg))
4637 if (F.paramHasAttr(j, ParamAttr::StructRet))
4639 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4641 const PointerType *Ty = cast<PointerType>(I->getType());
4642 const Type *ElementTy = Ty->getElementType();
4643 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4644 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4645 // For ByVal, alignment should be passed from FE. BE will guess if
4646 // this info is not there but there are cases it cannot get right.
4647 if (F.getParamAlignment(j))
4648 FrameAlign = F.getParamAlignment(j);
4649 Flags.setByValAlign(FrameAlign);
4650 Flags.setByValSize(FrameSize);
4652 if (F.paramHasAttr(j, ParamAttr::Nest))
4654 Flags.setOrigAlign(OriginalAlignment);
4656 MVT RegisterVT = getRegisterType(VT);
4657 unsigned NumRegs = getNumRegisters(VT);
4658 for (unsigned i = 0; i != NumRegs; ++i) {
4659 RetVals.push_back(RegisterVT);
4660 ISD::ArgFlagsTy MyFlags = Flags;
4661 if (NumRegs > 1 && i == 0)
4663 // if it isn't first piece, alignment must be 1
4665 MyFlags.setOrigAlign(1);
4666 Ops.push_back(DAG.getArgFlags(MyFlags));
4671 RetVals.push_back(MVT::Other);
4674 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4675 DAG.getVTList(&RetVals[0], RetVals.size()),
4676 &Ops[0], Ops.size()).Val;
4678 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4679 // allows exposing the loads that may be part of the argument access to the
4680 // first DAGCombiner pass.
4681 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
4683 // The number of results should match up, except that the lowered one may have
4684 // an extra flag result.
4685 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4686 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4687 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4688 && "Lowering produced unexpected number of results!");
4690 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
4691 if (Result != TmpRes.Val && Result->use_empty()) {
4692 HandleSDNode Dummy(DAG.getRoot());
4693 DAG.RemoveDeadNode(Result);
4696 Result = TmpRes.Val;
4698 unsigned NumArgRegs = Result->getNumValues() - 1;
4699 DAG.setRoot(SDValue(Result, NumArgRegs));
4701 // Set up the return result vector.
4704 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4706 SmallVector<MVT, 4> ValueVTs;
4707 ComputeValueVTs(*this, I->getType(), ValueVTs);
4708 for (unsigned Value = 0, NumValues = ValueVTs.size();
4709 Value != NumValues; ++Value) {
4710 MVT VT = ValueVTs[Value];
4711 MVT PartVT = getRegisterType(VT);
4713 unsigned NumParts = getNumRegisters(VT);
4714 SmallVector<SDValue, 4> Parts(NumParts);
4715 for (unsigned j = 0; j != NumParts; ++j)
4716 Parts[j] = SDValue(Result, i++);
4718 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4719 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4720 AssertOp = ISD::AssertSext;
4721 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4722 AssertOp = ISD::AssertZext;
4724 ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4728 assert(i == NumArgRegs && "Argument register count mismatch!");
4732 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4733 /// implementation, which just inserts an ISD::CALL node, which is later custom
4734 /// lowered by the target to something concrete. FIXME: When all targets are
4735 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4736 std::pair<SDValue, SDValue>
4737 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
4738 bool RetSExt, bool RetZExt, bool isVarArg,
4739 unsigned CallingConv, bool isTailCall,
4741 ArgListTy &Args, SelectionDAG &DAG) {
4742 SmallVector<SDValue, 32> Ops;
4743 Ops.push_back(Chain); // Op#0 - Chain
4744 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4745 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4746 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4747 Ops.push_back(Callee);
4749 // Handle all of the outgoing arguments.
4750 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4751 SmallVector<MVT, 4> ValueVTs;
4752 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
4753 for (unsigned Value = 0, NumValues = ValueVTs.size();
4754 Value != NumValues; ++Value) {
4755 MVT VT = ValueVTs[Value];
4756 const Type *ArgTy = VT.getTypeForMVT();
4757 SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value);
4758 ISD::ArgFlagsTy Flags;
4759 unsigned OriginalAlignment =
4760 getTargetData()->getABITypeAlignment(ArgTy);
4766 if (Args[i].isInReg)
4770 if (Args[i].isByVal) {
4772 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4773 const Type *ElementTy = Ty->getElementType();
4774 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4775 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4776 // For ByVal, alignment should come from FE. BE will guess if this
4777 // info is not there but there are cases it cannot get right.
4778 if (Args[i].Alignment)
4779 FrameAlign = Args[i].Alignment;
4780 Flags.setByValAlign(FrameAlign);
4781 Flags.setByValSize(FrameSize);
4785 Flags.setOrigAlign(OriginalAlignment);
4787 MVT PartVT = getRegisterType(VT);
4788 unsigned NumParts = getNumRegisters(VT);
4789 SmallVector<SDValue, 4> Parts(NumParts);
4790 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4793 ExtendKind = ISD::SIGN_EXTEND;
4794 else if (Args[i].isZExt)
4795 ExtendKind = ISD::ZERO_EXTEND;
4797 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4799 for (unsigned i = 0; i != NumParts; ++i) {
4800 // if it isn't first piece, alignment must be 1
4801 ISD::ArgFlagsTy MyFlags = Flags;
4802 if (NumParts > 1 && i == 0)
4805 MyFlags.setOrigAlign(1);
4807 Ops.push_back(Parts[i]);
4808 Ops.push_back(DAG.getArgFlags(MyFlags));
4813 // Figure out the result value types. We start by making a list of
4814 // the potentially illegal return value types.
4815 SmallVector<MVT, 4> LoweredRetTys;
4816 SmallVector<MVT, 4> RetTys;
4817 ComputeValueVTs(*this, RetTy, RetTys);
4819 // Then we translate that to a list of legal types.
4820 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4822 MVT RegisterVT = getRegisterType(VT);
4823 unsigned NumRegs = getNumRegisters(VT);
4824 for (unsigned i = 0; i != NumRegs; ++i)
4825 LoweredRetTys.push_back(RegisterVT);
4828 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4830 // Create the CALL node.
4831 SDValue Res = DAG.getNode(ISD::CALL,
4832 DAG.getVTList(&LoweredRetTys[0],
4833 LoweredRetTys.size()),
4834 &Ops[0], Ops.size());
4835 Chain = Res.getValue(LoweredRetTys.size() - 1);
4837 // Gather up the call result into a single value.
4838 if (RetTy != Type::VoidTy) {
4839 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4842 AssertOp = ISD::AssertSext;
4844 AssertOp = ISD::AssertZext;
4846 SmallVector<SDValue, 4> ReturnValues;
4848 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4850 MVT RegisterVT = getRegisterType(VT);
4851 unsigned NumRegs = getNumRegisters(VT);
4852 unsigned RegNoEnd = NumRegs + RegNo;
4853 SmallVector<SDValue, 4> Results;
4854 for (; RegNo != RegNoEnd; ++RegNo)
4855 Results.push_back(Res.getValue(RegNo));
4856 SDValue ReturnValue =
4857 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4859 ReturnValues.push_back(ReturnValue);
4861 Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()),
4862 &ReturnValues[0], ReturnValues.size());
4865 return std::make_pair(Res, Chain);
4868 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
4869 assert(0 && "LowerOperation not implemented for this target!");
4875 //===----------------------------------------------------------------------===//
4876 // SelectionDAGISel code
4877 //===----------------------------------------------------------------------===//
4879 unsigned SelectionDAGISel::MakeReg(MVT VT) {
4880 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4883 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4884 AU.addRequired<AliasAnalysis>();
4885 AU.addRequired<CollectorModuleMetadata>();
4886 AU.setPreservesAll();
4889 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4890 // Get alias analysis for load/store combining.
4891 AA = &getAnalysis<AliasAnalysis>();
4893 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4894 if (MF.getFunction()->hasCollector())
4895 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4898 RegInfo = &MF.getRegInfo();
4899 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4901 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4903 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4904 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4905 // Mark landing pad.
4906 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4908 SelectAllBasicBlocks(Fn, MF, FuncInfo);
4910 // Add function live-ins to entry block live-in set.
4911 BasicBlock *EntryBB = &Fn.getEntryBlock();
4912 BB = FuncInfo.MBBMap[EntryBB];
4913 if (!RegInfo->livein_empty())
4914 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4915 E = RegInfo->livein_end(); I != E; ++I)
4916 BB->addLiveIn(I->first);
4919 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4920 "Not all catch info was assigned to a landing pad!");
4926 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
4927 SDValue Op = getValue(V);
4928 assert((Op.getOpcode() != ISD::CopyFromReg ||
4929 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4930 "Copy from a reg to the same reg!");
4931 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4933 RegsForValue RFV(TLI, Reg, V->getType());
4934 SDValue Chain = DAG.getEntryNode();
4935 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4936 PendingExports.push_back(Chain);
4939 void SelectionDAGISel::
4940 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4941 // If this is the entry block, emit arguments.
4942 Function &F = *LLVMBB->getParent();
4943 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4944 SDValue OldRoot = SDL.DAG.getRoot();
4945 SmallVector<SDValue, 16> Args;
4946 TLI.LowerArguments(F, SDL.DAG, Args);
4949 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4951 SmallVector<MVT, 4> ValueVTs;
4952 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
4953 unsigned NumValues = ValueVTs.size();
4954 if (!AI->use_empty()) {
4955 SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues));
4956 // If this argument is live outside of the entry block, insert a copy from
4957 // whereever we got it to the vreg that other BB's will reference it as.
4958 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4959 if (VMI != FuncInfo.ValueMap.end()) {
4960 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4966 // Finally, if the target has anything special to do, allow it to do so.
4967 // FIXME: this should insert code into the DAG!
4968 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4971 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4972 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4973 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4974 if (isSelector(I)) {
4975 // Apply the catch info to DestBB.
4976 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4978 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4979 FLI.CatchInfoFound.insert(I);
4984 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
4985 /// whether object offset >= 0.
4987 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
4988 if (!isa<FrameIndexSDNode>(Op)) return false;
4990 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
4991 int FrameIdx = FrameIdxNode->getIndex();
4992 return MFI->isFixedObjectIndex(FrameIdx) &&
4993 MFI->getObjectOffset(FrameIdx) >= 0;
4996 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
4997 /// possibly be overwritten when lowering the outgoing arguments in a tail
4998 /// call. Currently the implementation of this call is very conservative and
4999 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
5000 /// virtual registers would be overwritten by direct lowering.
5001 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
5002 MachineFrameInfo * MFI) {
5003 RegisterSDNode * OpReg = NULL;
5004 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
5005 (Op.getOpcode()== ISD::CopyFromReg &&
5006 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
5007 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
5008 (Op.getOpcode() == ISD::LOAD &&
5009 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
5010 (Op.getOpcode() == ISD::MERGE_VALUES &&
5011 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
5012 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
5018 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
5019 /// DAG and fixes their tailcall attribute operand.
5020 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
5021 TargetLowering& TLI) {
5022 SDNode * Ret = NULL;
5023 SDValue Terminator = DAG.getRoot();
5026 if (Terminator.getOpcode() == ISD::RET) {
5027 Ret = Terminator.Val;
5030 // Fix tail call attribute of CALL nodes.
5031 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
5032 BI = DAG.allnodes_end(); BI != BE; ) {
5034 if (BI->getOpcode() == ISD::CALL) {
5035 SDValue OpRet(Ret, 0);
5036 SDValue OpCall(BI, 0);
5037 bool isMarkedTailCall =
5038 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
5039 // If CALL node has tail call attribute set to true and the call is not
5040 // eligible (no RET or the target rejects) the attribute is fixed to
5041 // false. The TargetLowering::IsEligibleForTailCallOptimization function
5042 // must correctly identify tail call optimizable calls.
5043 if (!isMarkedTailCall) continue;
5045 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
5046 // Not eligible. Mark CALL node as non tail call.
5047 SmallVector<SDValue, 32> Ops;
5049 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
5050 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5054 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
5056 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5058 // Look for tail call clobbered arguments. Emit a series of
5059 // copyto/copyfrom virtual register nodes to protect them.
5060 SmallVector<SDValue, 32> Ops;
5061 SDValue Chain = OpCall.getOperand(0), InFlag;
5063 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
5064 E = OpCall.Val->op_end(); I != E; I++, idx++) {
5066 if (idx > 4 && (idx % 2)) {
5067 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
5068 getArgFlags().isByVal();
5069 MachineFunction &MF = DAG.getMachineFunction();
5070 MachineFrameInfo *MFI = MF.getFrameInfo();
5072 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
5073 MVT VT = Arg.getValueType();
5074 unsigned VReg = MF.getRegInfo().
5075 createVirtualRegister(TLI.getRegClassFor(VT));
5076 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
5077 InFlag = Chain.getValue(1);
5078 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
5079 Chain = Arg.getValue(1);
5080 InFlag = Arg.getValue(2);
5085 // Link in chain of CopyTo/CopyFromReg.
5087 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
5093 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
5094 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
5095 FunctionLoweringInfo &FuncInfo) {
5096 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
5098 // Lower any arguments needed in this block if this is the entry block.
5099 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
5100 LowerArguments(LLVMBB, SDL);
5102 BB = FuncInfo.MBBMap[LLVMBB];
5103 SDL.setCurrentBasicBlock(BB);
5105 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
5107 if (MMI && BB->isLandingPad()) {
5108 // Add a label to mark the beginning of the landing pad. Deletion of the
5109 // landing pad can thus be detected via the MachineModuleInfo.
5110 unsigned LabelID = MMI->addLandingPad(BB);
5111 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID));
5113 // Mark exception register as live in.
5114 unsigned Reg = TLI.getExceptionAddressRegister();
5115 if (Reg) BB->addLiveIn(Reg);
5117 // Mark exception selector register as live in.
5118 Reg = TLI.getExceptionSelectorRegister();
5119 if (Reg) BB->addLiveIn(Reg);
5121 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5122 // function and list of typeids logically belong to the invoke (or, if you
5123 // like, the basic block containing the invoke), and need to be associated
5124 // with it in the dwarf exception handling tables. Currently however the
5125 // information is provided by an intrinsic (eh.selector) that can be moved
5126 // to unexpected places by the optimizers: if the unwind edge is critical,
5127 // then breaking it can result in the intrinsics being in the successor of
5128 // the landing pad, not the landing pad itself. This results in exceptions
5129 // not being caught because no typeids are associated with the invoke.
5130 // This may not be the only way things can go wrong, but it is the only way
5131 // we try to work around for the moment.
5132 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
5134 if (Br && Br->isUnconditional()) { // Critical edge?
5135 BasicBlock::iterator I, E;
5136 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
5141 // No catch info found - try to extract some from the successor.
5142 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
5146 // Lower all of the non-terminator instructions.
5147 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
5151 // Ensure that all instructions which are used outside of their defining
5152 // blocks are available as virtual registers. Invoke is handled elsewhere.
5153 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
5154 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
5155 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
5156 if (VMI != FuncInfo.ValueMap.end())
5157 SDL.CopyValueToVirtualRegister(I, VMI->second);
5160 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5161 // ensure constants are generated when needed. Remember the virtual registers
5162 // that need to be added to the Machine PHI nodes as input. We cannot just
5163 // directly add them, because expansion might result in multiple MBB's for one
5164 // BB. As such, the start of the BB might correspond to a different MBB than
5167 TerminatorInst *TI = LLVMBB->getTerminator();
5169 // Emit constants only once even if used by multiple PHI nodes.
5170 std::map<Constant*, unsigned> ConstantsOut;
5172 // Vector bool would be better, but vector<bool> is really slow.
5173 std::vector<unsigned char> SuccsHandled;
5174 if (TI->getNumSuccessors())
5175 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
5177 // Check successor nodes' PHI nodes that expect a constant to be available
5179 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5180 BasicBlock *SuccBB = TI->getSuccessor(succ);
5181 if (!isa<PHINode>(SuccBB->begin())) continue;
5182 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
5184 // If this terminator has multiple identical successors (common for
5185 // switches), only handle each succ once.
5186 unsigned SuccMBBNo = SuccMBB->getNumber();
5187 if (SuccsHandled[SuccMBBNo]) continue;
5188 SuccsHandled[SuccMBBNo] = true;
5190 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5193 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5194 // nodes and Machine PHI nodes, but the incoming operands have not been
5196 for (BasicBlock::iterator I = SuccBB->begin();
5197 (PN = dyn_cast<PHINode>(I)); ++I) {
5198 // Ignore dead phi's.
5199 if (PN->use_empty()) continue;
5202 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5204 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5205 unsigned &RegOut = ConstantsOut[C];
5207 RegOut = FuncInfo.CreateRegForValue(C);
5208 SDL.CopyValueToVirtualRegister(C, RegOut);
5212 Reg = FuncInfo.ValueMap[PHIOp];
5214 assert(isa<AllocaInst>(PHIOp) &&
5215 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5216 "Didn't codegen value into a register!??");
5217 Reg = FuncInfo.CreateRegForValue(PHIOp);
5218 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
5222 // Remember that this register needs to added to the machine PHI node as
5223 // the input for this MBB.
5224 SmallVector<MVT, 4> ValueVTs;
5225 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5226 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5227 MVT VT = ValueVTs[vti];
5228 unsigned NumRegisters = TLI.getNumRegisters(VT);
5229 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5230 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5231 Reg += NumRegisters;
5235 ConstantsOut.clear();
5237 // Lower the terminator after the copies are emitted.
5238 SDL.visit(*LLVMBB->getTerminator());
5240 // Copy over any CaseBlock records that may now exist due to SwitchInst
5241 // lowering, as well as any jump table information.
5242 SwitchCases.clear();
5243 SwitchCases = SDL.SwitchCases;
5245 JTCases = SDL.JTCases;
5246 BitTestCases.clear();
5247 BitTestCases = SDL.BitTestCases;
5249 // Make sure the root of the DAG is up-to-date.
5250 DAG.setRoot(SDL.getControlRoot());
5252 // Check whether calls in this block are real tail calls. Fix up CALL nodes
5253 // with correct tailcall attribute so that the target can rely on the tailcall
5254 // attribute indicating whether the call is really eligible for tail call
5256 CheckDAGForTailCallsAndFixThem(DAG, TLI);
5259 void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
5260 SmallPtrSet<SDNode*, 128> VisitedNodes;
5261 SmallVector<SDNode*, 128> Worklist;
5263 Worklist.push_back(DAG.getRoot().Val);
5269 while (!Worklist.empty()) {
5270 SDNode *N = Worklist.back();
5271 Worklist.pop_back();
5273 // If we've already seen this node, ignore it.
5274 if (!VisitedNodes.insert(N))
5277 // Otherwise, add all chain operands to the worklist.
5278 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5279 if (N->getOperand(i).getValueType() == MVT::Other)
5280 Worklist.push_back(N->getOperand(i).Val);
5282 // If this is a CopyToReg with a vreg dest, process it.
5283 if (N->getOpcode() != ISD::CopyToReg)
5286 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
5287 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
5290 // Ignore non-scalar or non-integer values.
5291 SDValue Src = N->getOperand(2);
5292 MVT SrcVT = Src.getValueType();
5293 if (!SrcVT.isInteger() || SrcVT.isVector())
5296 unsigned NumSignBits = DAG.ComputeNumSignBits(Src);
5297 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
5298 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
5300 // Only install this information if it tells us something.
5301 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
5302 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
5303 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5304 if (DestReg >= FLI.LiveOutRegInfo.size())
5305 FLI.LiveOutRegInfo.resize(DestReg+1);
5306 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
5307 LOI.NumSignBits = NumSignBits;
5308 LOI.KnownOne = NumSignBits;
5309 LOI.KnownZero = NumSignBits;
5314 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
5315 std::string GroupName;
5316 if (TimePassesIsEnabled)
5317 GroupName = "Instruction Selection and Scheduling";
5318 std::string BlockName;
5319 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
5320 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
5321 BlockName = DAG.getMachineFunction().getFunction()->getName() + ':' +
5322 BB->getBasicBlock()->getName();
5324 DOUT << "Initial selection DAG:\n";
5327 if (ViewDAGCombine1) DAG.viewGraph("dag-combine1 input for " + BlockName);
5329 // Run the DAG combiner in pre-legalize mode.
5330 if (TimePassesIsEnabled) {
5331 NamedRegionTimer T("DAG Combining 1", GroupName);
5332 DAG.Combine(false, *AA);
5334 DAG.Combine(false, *AA);
5337 DOUT << "Optimized lowered selection DAG:\n";
5340 // Second step, hack on the DAG until it only uses operations and types that
5341 // the target supports.
5342 if (EnableLegalizeTypes) {// Enable this some day.
5343 if (ViewLegalizeTypesDAGs) DAG.viewGraph("legalize-types input for " +
5346 if (TimePassesIsEnabled) {
5347 NamedRegionTimer T("Type Legalization", GroupName);
5348 DAG.LegalizeTypes();
5350 DAG.LegalizeTypes();
5353 DOUT << "Type-legalized selection DAG:\n";
5356 // TODO: enable a dag combine pass here.
5359 if (ViewLegalizeDAGs) DAG.viewGraph("legalize input for " + BlockName);
5361 if (TimePassesIsEnabled) {
5362 NamedRegionTimer T("DAG Legalization", GroupName);
5368 DOUT << "Legalized selection DAG:\n";
5371 if (ViewDAGCombine2) DAG.viewGraph("dag-combine2 input for " + BlockName);
5373 // Run the DAG combiner in post-legalize mode.
5374 if (TimePassesIsEnabled) {
5375 NamedRegionTimer T("DAG Combining 2", GroupName);
5376 DAG.Combine(true, *AA);
5378 DAG.Combine(true, *AA);
5381 DOUT << "Optimized legalized selection DAG:\n";
5384 if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName);
5386 if (!FastISel && EnableValueProp)
5387 ComputeLiveOutVRegInfo(DAG);
5389 // Third, instruction select all of the operations to machine code, adding the
5390 // code to the MachineBasicBlock.
5391 if (TimePassesIsEnabled) {
5392 NamedRegionTimer T("Instruction Selection", GroupName);
5393 InstructionSelect(DAG);
5395 InstructionSelect(DAG);
5398 DOUT << "Selected selection DAG:\n";
5401 if (ViewSchedDAGs) DAG.viewGraph("scheduler input for " + BlockName);
5403 // Schedule machine code.
5404 ScheduleDAG *Scheduler;
5405 if (TimePassesIsEnabled) {
5406 NamedRegionTimer T("Instruction Scheduling", GroupName);
5407 Scheduler = Schedule(DAG);
5409 Scheduler = Schedule(DAG);
5412 if (ViewSUnitDAGs) Scheduler->viewGraph();
5414 // Emit machine code to BB. This can change 'BB' to the last block being
5416 if (TimePassesIsEnabled) {
5417 NamedRegionTimer T("Instruction Creation", GroupName);
5418 BB = Scheduler->EmitSchedule();
5420 BB = Scheduler->EmitSchedule();
5423 // Free the scheduler state.
5424 if (TimePassesIsEnabled) {
5425 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
5431 // Perform target specific isel post processing.
5432 if (TimePassesIsEnabled) {
5433 NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
5434 InstructionSelectPostProcessing();
5436 InstructionSelectPostProcessing();
5439 DOUT << "Selected machine code:\n";
5443 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
5444 FunctionLoweringInfo &FuncInfo) {
5445 // Define NodeAllocator here so that memory allocation is reused for
5446 // each basic block.
5447 NodeAllocatorType NodeAllocator;
5449 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
5450 SelectBasicBlock(I, MF, FuncInfo, NodeAllocator);
5454 SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5455 FunctionLoweringInfo &FuncInfo,
5456 NodeAllocatorType &NodeAllocator) {
5457 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
5459 SelectionDAG DAG(TLI, MF, FuncInfo,
5460 getAnalysisToUpdate<MachineModuleInfo>(),
5464 // First step, lower LLVM code to some DAG. This DAG may use operations and
5465 // types that are not supported by the target.
5466 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
5468 // Second step, emit the lowered DAG as machine code.
5469 CodeGenAndEmitDAG(DAG);
5472 DOUT << "Total amount of phi nodes to update: "
5473 << PHINodesToUpdate.size() << "\n";
5474 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
5475 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
5476 << ", " << PHINodesToUpdate[i].second << ")\n";);
5478 // Next, now that we know what the last MBB the LLVM BB expanded is, update
5479 // PHI nodes in successors.
5480 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
5481 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5482 MachineInstr *PHI = PHINodesToUpdate[i].first;
5483 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5484 "This is not a machine PHI node that we are updating!");
5485 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5487 PHI->addOperand(MachineOperand::CreateMBB(BB));
5492 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
5493 // Lower header first, if it wasn't already lowered
5494 if (!BitTestCases[i].Emitted) {
5495 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5496 getAnalysisToUpdate<MachineModuleInfo>(),
5499 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5500 // Set the current basic block to the mbb we wish to insert the code into
5501 BB = BitTestCases[i].Parent;
5502 HSDL.setCurrentBasicBlock(BB);
5504 HSDL.visitBitTestHeader(BitTestCases[i]);
5505 HSDAG.setRoot(HSDL.getRoot());
5506 CodeGenAndEmitDAG(HSDAG);
5509 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5510 SelectionDAG BSDAG(TLI, MF, FuncInfo,
5511 getAnalysisToUpdate<MachineModuleInfo>(),
5514 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
5515 // Set the current basic block to the mbb we wish to insert the code into
5516 BB = BitTestCases[i].Cases[j].ThisBB;
5517 BSDL.setCurrentBasicBlock(BB);
5520 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5521 BitTestCases[i].Reg,
5522 BitTestCases[i].Cases[j]);
5524 BSDL.visitBitTestCase(BitTestCases[i].Default,
5525 BitTestCases[i].Reg,
5526 BitTestCases[i].Cases[j]);
5529 BSDAG.setRoot(BSDL.getRoot());
5530 CodeGenAndEmitDAG(BSDAG);
5534 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5535 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5536 MachineBasicBlock *PHIBB = PHI->getParent();
5537 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5538 "This is not a machine PHI node that we are updating!");
5539 // This is "default" BB. We have two jumps to it. From "header" BB and
5540 // from last "case" BB.
5541 if (PHIBB == BitTestCases[i].Default) {
5542 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5544 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5545 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5547 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5550 // One of "cases" BB.
5551 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5552 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5553 if (cBB->succ_end() !=
5554 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5555 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5557 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5563 // If the JumpTable record is filled in, then we need to emit a jump table.
5564 // Updating the PHI nodes is tricky in this case, since we need to determine
5565 // whether the PHI is a successor of the range check MBB or the jump table MBB
5566 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5567 // Lower header first, if it wasn't already lowered
5568 if (!JTCases[i].first.Emitted) {
5569 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5570 getAnalysisToUpdate<MachineModuleInfo>(),
5573 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5574 // Set the current basic block to the mbb we wish to insert the code into
5575 BB = JTCases[i].first.HeaderBB;
5576 HSDL.setCurrentBasicBlock(BB);
5578 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5579 HSDAG.setRoot(HSDL.getRoot());
5580 CodeGenAndEmitDAG(HSDAG);
5583 SelectionDAG JSDAG(TLI, MF, FuncInfo,
5584 getAnalysisToUpdate<MachineModuleInfo>(),
5587 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5588 // Set the current basic block to the mbb we wish to insert the code into
5589 BB = JTCases[i].second.MBB;
5590 JSDL.setCurrentBasicBlock(BB);
5592 JSDL.visitJumpTable(JTCases[i].second);
5593 JSDAG.setRoot(JSDL.getRoot());
5594 CodeGenAndEmitDAG(JSDAG);
5597 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5598 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5599 MachineBasicBlock *PHIBB = PHI->getParent();
5600 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5601 "This is not a machine PHI node that we are updating!");
5602 // "default" BB. We can go there only from header BB.
5603 if (PHIBB == JTCases[i].second.Default) {
5604 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5606 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5608 // JT BB. Just iterate over successors here
5609 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5610 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5612 PHI->addOperand(MachineOperand::CreateMBB(BB));
5617 // If the switch block involved a branch to one of the actual successors, we
5618 // need to update PHI nodes in that block.
5619 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5620 MachineInstr *PHI = PHINodesToUpdate[i].first;
5621 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5622 "This is not a machine PHI node that we are updating!");
5623 if (BB->isSuccessor(PHI->getParent())) {
5624 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5626 PHI->addOperand(MachineOperand::CreateMBB(BB));
5630 // If we generated any switch lowering information, build and codegen any
5631 // additional DAGs necessary.
5632 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5633 SelectionDAG SDAG(TLI, MF, FuncInfo,
5634 getAnalysisToUpdate<MachineModuleInfo>(),
5637 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5639 // Set the current basic block to the mbb we wish to insert the code into
5640 BB = SwitchCases[i].ThisBB;
5641 SDL.setCurrentBasicBlock(BB);
5644 SDL.visitSwitchCase(SwitchCases[i]);
5645 SDAG.setRoot(SDL.getRoot());
5646 CodeGenAndEmitDAG(SDAG);
5648 // Handle any PHI nodes in successors of this chunk, as if we were coming
5649 // from the original BB before switch expansion. Note that PHI nodes can
5650 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5651 // handle them the right number of times.
5652 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5653 for (MachineBasicBlock::iterator Phi = BB->begin();
5654 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5655 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5656 for (unsigned pn = 0; ; ++pn) {
5657 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5658 if (PHINodesToUpdate[pn].first == Phi) {
5659 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5661 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5667 // Don't process RHS if same block as LHS.
5668 if (BB == SwitchCases[i].FalseBB)
5669 SwitchCases[i].FalseBB = 0;
5671 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5672 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5673 SwitchCases[i].FalseBB = 0;
5675 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5680 /// Schedule - Pick a safe ordering for instructions for each
5681 /// target node in the graph.
5683 ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
5684 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5688 RegisterScheduler::setDefault(Ctor);
5691 ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
5698 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5699 return new HazardRecognizer();
5702 //===----------------------------------------------------------------------===//
5703 // Helper functions used by the generated instruction selector.
5704 //===----------------------------------------------------------------------===//
5705 // Calls to these methods are generated by tblgen.
5707 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5708 /// the dag combiner simplified the 255, we still want to match. RHS is the
5709 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5710 /// specified in the .td file (e.g. 255).
5711 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
5712 int64_t DesiredMaskS) const {
5713 const APInt &ActualMask = RHS->getAPIntValue();
5714 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5716 // If the actual mask exactly matches, success!
5717 if (ActualMask == DesiredMask)
5720 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5721 if (ActualMask.intersects(~DesiredMask))
5724 // Otherwise, the DAG Combiner may have proven that the value coming in is
5725 // either already zero or is not demanded. Check for known zero input bits.
5726 APInt NeededMask = DesiredMask & ~ActualMask;
5727 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5730 // TODO: check to see if missing bits are just not demanded.
5732 // Otherwise, this pattern doesn't match.
5736 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5737 /// the dag combiner simplified the 255, we still want to match. RHS is the
5738 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5739 /// specified in the .td file (e.g. 255).
5740 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
5741 int64_t DesiredMaskS) const {
5742 const APInt &ActualMask = RHS->getAPIntValue();
5743 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5745 // If the actual mask exactly matches, success!
5746 if (ActualMask == DesiredMask)
5749 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5750 if (ActualMask.intersects(~DesiredMask))
5753 // Otherwise, the DAG Combiner may have proven that the value coming in is
5754 // either already zero or is not demanded. Check for known zero input bits.
5755 APInt NeededMask = DesiredMask & ~ActualMask;
5757 APInt KnownZero, KnownOne;
5758 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5760 // If all the missing bits in the or are already known to be set, match!
5761 if ((NeededMask & KnownOne) == NeededMask)
5764 // TODO: check to see if missing bits are just not demanded.
5766 // Otherwise, this pattern doesn't match.
5771 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5772 /// by tblgen. Others should not call it.
5773 void SelectionDAGISel::
5774 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SelectionDAG &DAG) {
5775 std::vector<SDValue> InOps;
5776 std::swap(InOps, Ops);
5778 Ops.push_back(InOps[0]); // input chain.
5779 Ops.push_back(InOps[1]); // input asm string.
5781 unsigned i = 2, e = InOps.size();
5782 if (InOps[e-1].getValueType() == MVT::Flag)
5783 --e; // Don't process a flag operand if it is here.
5786 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5787 if ((Flags & 7) != 4 /*MEM*/) {
5788 // Just skip over this operand, copying the operands verbatim.
5789 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5790 i += (Flags >> 3) + 1;
5792 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5793 // Otherwise, this is a memory operand. Ask the target to select it.
5794 std::vector<SDValue> SelOps;
5795 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5796 cerr << "Could not match memory address. Inline asm failure!\n";
5800 // Add this to the output node.
5801 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5802 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5804 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5809 // Add the flag input back if present.
5810 if (e != InOps.size())
5811 Ops.push_back(InOps.back());
5814 char SelectionDAGISel::ID = 0;