1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/Timer.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/ADT/Statistic.h"
56 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
57 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
58 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
59 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
62 STATISTIC(NumBBWithOutOfOrderLineInfo,
63 "Number of blocks with out of order line number info");
64 STATISTIC(NumMBBWithOutOfOrderLineInfo,
65 "Number of machine blocks with out of order line number info");
69 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
70 cl::desc("Enable verbose messages in the \"fast\" "
71 "instruction selector"));
73 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
74 cl::desc("Enable abort calls when \"fast\" instruction fails"));
78 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the first "
82 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before legalize types"));
85 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
86 cl::desc("Pop up a window to show dags before legalize"));
88 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
89 cl::desc("Pop up a window to show dags before the second "
92 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
93 cl::desc("Pop up a window to show dags before the post legalize types"
94 " dag combine pass"));
96 ViewISelDAGs("view-isel-dags", cl::Hidden,
97 cl::desc("Pop up a window to show isel dags as they are selected"));
99 ViewSchedDAGs("view-sched-dags", cl::Hidden,
100 cl::desc("Pop up a window to show sched dags as they are processed"));
102 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
103 cl::desc("Pop up a window to show SUnit dags after they are processed"));
105 static const bool ViewDAGCombine1 = false,
106 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
107 ViewDAGCombine2 = false,
108 ViewDAGCombineLT = false,
109 ViewISelDAGs = false, ViewSchedDAGs = false,
110 ViewSUnitDAGs = false;
113 //===---------------------------------------------------------------------===//
115 /// RegisterScheduler class - Track the registration of instruction schedulers.
117 //===---------------------------------------------------------------------===//
118 MachinePassRegistry RegisterScheduler::Registry;
120 //===---------------------------------------------------------------------===//
122 /// ISHeuristic command line option for instruction schedulers.
124 //===---------------------------------------------------------------------===//
125 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
126 RegisterPassParser<RegisterScheduler> >
127 ISHeuristic("pre-RA-sched",
128 cl::init(&createDefaultScheduler),
129 cl::desc("Instruction schedulers available (before register"
132 static RegisterScheduler
133 defaultListDAGScheduler("default", "Best scheduler for the target",
134 createDefaultScheduler);
137 //===--------------------------------------------------------------------===//
138 /// createDefaultScheduler - This creates an instruction scheduler appropriate
140 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
141 CodeGenOpt::Level OptLevel) {
142 const TargetLowering &TLI = IS->getTargetLowering();
144 if (OptLevel == CodeGenOpt::None)
145 return createSourceListDAGScheduler(IS, OptLevel);
146 if (TLI.getSchedulingPreference() == Sched::Latency)
147 return createTDListDAGScheduler(IS, OptLevel);
148 if (TLI.getSchedulingPreference() == Sched::RegPressure)
149 return createBURRListDAGScheduler(IS, OptLevel);
150 if (TLI.getSchedulingPreference() == Sched::Hybrid)
151 return createHybridListDAGScheduler(IS, OptLevel);
152 assert(TLI.getSchedulingPreference() == Sched::ILP &&
153 "Unknown sched type!");
154 return createILPListDAGScheduler(IS, OptLevel);
158 // EmitInstrWithCustomInserter - This method should be implemented by targets
159 // that mark instructions with the 'usesCustomInserter' flag. These
160 // instructions are special in various ways, which require special support to
161 // insert. The specified MachineInstr is created but not inserted into any
162 // basic blocks, and this method is called to expand it into a sequence of
163 // instructions, potentially also creating new basic blocks and control flow.
164 // When new basic blocks are inserted and the edges from MBB to its successors
165 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
168 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
169 MachineBasicBlock *MBB) const {
171 dbgs() << "If a target marks an instruction with "
172 "'usesCustomInserter', it must implement "
173 "TargetLowering::EmitInstrWithCustomInserter!";
179 //===----------------------------------------------------------------------===//
180 // SelectionDAGISel code
181 //===----------------------------------------------------------------------===//
183 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
184 CodeGenOpt::Level OL) :
185 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
186 FuncInfo(new FunctionLoweringInfo(TLI)),
187 CurDAG(new SelectionDAG(tm)),
188 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
192 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
193 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
196 SelectionDAGISel::~SelectionDAGISel() {
202 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
203 AU.addRequired<AliasAnalysis>();
204 AU.addPreserved<AliasAnalysis>();
205 AU.addRequired<GCModuleInfo>();
206 AU.addPreserved<GCModuleInfo>();
207 MachineFunctionPass::getAnalysisUsage(AU);
210 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
211 /// other function that gcc recognizes as "returning twice". This is used to
212 /// limit code-gen optimizations on the machine function.
214 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
215 static bool FunctionCallsSetJmp(const Function *F) {
216 const Module *M = F->getParent();
217 static const char *ReturnsTwiceFns[] = {
227 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
229 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
230 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
231 if (!Callee->use_empty())
232 for (Value::const_use_iterator
233 I = Callee->use_begin(), E = Callee->use_end();
235 if (const CallInst *CI = dyn_cast<CallInst>(*I))
236 if (CI->getParent()->getParent() == F)
241 #undef NUM_RETURNS_TWICE_FNS
244 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
245 /// may trap on it. In this case we have to split the edge so that the path
246 /// through the predecessor block that doesn't go to the phi block doesn't
247 /// execute the possibly trapping instruction.
249 /// This is required for correctness, so it must be done at -O0.
251 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
252 // Loop for blocks with phi nodes.
253 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
254 PHINode *PN = dyn_cast<PHINode>(BB->begin());
255 if (PN == 0) continue;
258 // For each block with a PHI node, check to see if any of the input values
259 // are potentially trapping constant expressions. Constant expressions are
260 // the only potentially trapping value that can occur as the argument to a
262 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
263 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
264 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
265 if (CE == 0 || !CE->canTrap()) continue;
267 // The only case we have to worry about is when the edge is critical.
268 // Since this block has a PHI Node, we assume it has multiple input
269 // edges: check to see if the pred has multiple successors.
270 BasicBlock *Pred = PN->getIncomingBlock(i);
271 if (Pred->getTerminator()->getNumSuccessors() == 1)
274 // Okay, we have to split this edge.
275 SplitCriticalEdge(Pred->getTerminator(),
276 GetSuccessorNumber(Pred, BB), SDISel, true);
282 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
283 // Do some sanity-checking on the command-line options.
284 assert((!EnableFastISelVerbose || EnableFastISel) &&
285 "-fast-isel-verbose requires -fast-isel");
286 assert((!EnableFastISelAbort || EnableFastISel) &&
287 "-fast-isel-abort requires -fast-isel");
289 const Function &Fn = *mf.getFunction();
290 const TargetInstrInfo &TII = *TM.getInstrInfo();
291 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
294 RegInfo = &MF->getRegInfo();
295 AA = &getAnalysis<AliasAnalysis>();
296 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
298 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
300 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
303 FuncInfo->set(Fn, *MF);
306 SelectAllBasicBlocks(Fn);
308 // If the first basic block in the function has live ins that need to be
309 // copied into vregs, emit the copies into the top of the block before
310 // emitting the code for the block.
311 MachineBasicBlock *EntryMBB = MF->begin();
312 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
314 DenseMap<unsigned, unsigned> LiveInMap;
315 if (!FuncInfo->ArgDbgValues.empty())
316 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
317 E = RegInfo->livein_end(); LI != E; ++LI)
319 LiveInMap.insert(std::make_pair(LI->first, LI->second));
321 // Insert DBG_VALUE instructions for function arguments to the entry block.
322 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
323 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
324 unsigned Reg = MI->getOperand(0).getReg();
325 if (TargetRegisterInfo::isPhysicalRegister(Reg))
326 EntryMBB->insert(EntryMBB->begin(), MI);
328 MachineInstr *Def = RegInfo->getVRegDef(Reg);
329 MachineBasicBlock::iterator InsertPos = Def;
330 // FIXME: VR def may not be in entry block.
331 Def->getParent()->insert(llvm::next(InsertPos), MI);
334 // If Reg is live-in then update debug info to track its copy in a vreg.
335 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
336 if (LDI != LiveInMap.end()) {
337 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
338 MachineBasicBlock::iterator InsertPos = Def;
339 const MDNode *Variable =
340 MI->getOperand(MI->getNumOperands()-1).getMetadata();
341 unsigned Offset = MI->getOperand(1).getImm();
342 // Def is never a terminator here, so it is ok to increment InsertPos.
343 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
344 TII.get(TargetOpcode::DBG_VALUE))
345 .addReg(LDI->second, RegState::Debug)
346 .addImm(Offset).addMetadata(Variable);
348 // If this vreg is directly copied into an exported register then
349 // that COPY instructions also need DBG_VALUE, if it is the only
350 // user of LDI->second.
351 MachineInstr *CopyUseMI = NULL;
352 for (MachineRegisterInfo::use_iterator
353 UI = RegInfo->use_begin(LDI->second);
354 MachineInstr *UseMI = UI.skipInstruction();) {
355 if (UseMI->isDebugValue()) continue;
356 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
357 CopyUseMI = UseMI; continue;
359 // Otherwise this is another use or second copy use.
360 CopyUseMI = NULL; break;
363 MachineInstr *NewMI =
364 BuildMI(*MF, CopyUseMI->getDebugLoc(),
365 TII.get(TargetOpcode::DBG_VALUE))
366 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
367 .addImm(Offset).addMetadata(Variable);
368 EntryMBB->insertAfter(CopyUseMI, NewMI);
373 // Determine if there are any calls in this machine function.
374 MachineFrameInfo *MFI = MF->getFrameInfo();
375 if (!MFI->hasCalls()) {
376 for (MachineFunction::const_iterator
377 I = MF->begin(), E = MF->end(); I != E; ++I) {
378 const MachineBasicBlock *MBB = I;
379 for (MachineBasicBlock::const_iterator
380 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
381 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
383 if ((TID.isCall() && !TID.isReturn()) ||
384 II->isStackAligningInlineAsm()) {
385 MFI->setHasCalls(true);
393 // Determine if there is a call to setjmp in the machine function.
394 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
396 // Replace forward-declared registers with the registers containing
397 // the desired value.
398 MachineRegisterInfo &MRI = MF->getRegInfo();
399 for (DenseMap<unsigned, unsigned>::iterator
400 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
402 unsigned From = I->first;
403 unsigned To = I->second;
404 // If To is also scheduled to be replaced, find what its ultimate
407 DenseMap<unsigned, unsigned>::iterator J =
408 FuncInfo->RegFixups.find(To);
413 MRI.replaceRegWith(From, To);
416 // Release function-specific state. SDB and CurDAG are already cleared
424 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
425 BasicBlock::const_iterator End,
427 // Lower all of the non-terminator instructions. If a call is emitted
428 // as a tail call, cease emitting nodes for this block. Terminators
429 // are handled below.
430 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
433 // Make sure the root of the DAG is up-to-date.
434 CurDAG->setRoot(SDB->getControlRoot());
435 HadTailCall = SDB->HasTailCall;
438 // Final step, emit the lowered DAG as machine code.
443 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
444 SmallPtrSet<SDNode*, 128> VisitedNodes;
445 SmallVector<SDNode*, 128> Worklist;
447 Worklist.push_back(CurDAG->getRoot().getNode());
454 SDNode *N = Worklist.pop_back_val();
456 // If we've already seen this node, ignore it.
457 if (!VisitedNodes.insert(N))
460 // Otherwise, add all chain operands to the worklist.
461 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
462 if (N->getOperand(i).getValueType() == MVT::Other)
463 Worklist.push_back(N->getOperand(i).getNode());
465 // If this is a CopyToReg with a vreg dest, process it.
466 if (N->getOpcode() != ISD::CopyToReg)
469 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
470 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
473 // Ignore non-scalar or non-integer values.
474 SDValue Src = N->getOperand(2);
475 EVT SrcVT = Src.getValueType();
476 if (!SrcVT.isInteger() || SrcVT.isVector())
479 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
480 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
481 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
483 // Only install this information if it tells us something.
484 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
485 FuncInfo->LiveOutRegInfo.grow(DestReg);
486 FunctionLoweringInfo::LiveOutInfo &LOI =
487 FuncInfo->LiveOutRegInfo[DestReg];
488 LOI.NumSignBits = NumSignBits;
489 LOI.KnownOne = KnownOne;
490 LOI.KnownZero = KnownZero;
492 } while (!Worklist.empty());
495 void SelectionDAGISel::CodeGenAndEmitDAG() {
496 std::string GroupName;
497 if (TimePassesIsEnabled)
498 GroupName = "Instruction Selection and Scheduling";
499 std::string BlockName;
500 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
501 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
503 BlockName = MF->getFunction()->getNameStr() + ":" +
504 FuncInfo->MBB->getBasicBlock()->getNameStr();
506 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
508 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
510 // Run the DAG combiner in pre-legalize mode.
512 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
513 CurDAG->Combine(Unrestricted, *AA, OptLevel);
516 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
518 // Second step, hack on the DAG until it only uses operations and types that
519 // the target supports.
520 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
525 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
526 Changed = CurDAG->LegalizeTypes();
529 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
532 if (ViewDAGCombineLT)
533 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
535 // Run the DAG combiner in post-type-legalize mode.
537 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
538 TimePassesIsEnabled);
539 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
542 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
547 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
548 Changed = CurDAG->LegalizeVectors();
553 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
554 CurDAG->LegalizeTypes();
557 if (ViewDAGCombineLT)
558 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
560 // Run the DAG combiner in post-type-legalize mode.
562 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
563 TimePassesIsEnabled);
564 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
567 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
571 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
574 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
575 CurDAG->Legalize(OptLevel);
578 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
580 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
582 // Run the DAG combiner in post-legalize mode.
584 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
585 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
588 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
590 if (OptLevel != CodeGenOpt::None)
591 ComputeLiveOutVRegInfo();
593 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
595 // Third, instruction select all of the operations to machine code, adding the
596 // code to the MachineBasicBlock.
598 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
599 DoInstructionSelection();
602 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
604 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
606 // Schedule machine code.
607 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
609 NamedRegionTimer T("Instruction Scheduling", GroupName,
610 TimePassesIsEnabled);
611 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
614 if (ViewSUnitDAGs) Scheduler->viewGraph();
616 // Emit machine code to BB. This can change 'BB' to the last block being
618 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
620 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
622 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
623 FuncInfo->InsertPt = Scheduler->InsertPos;
626 // If the block was split, make sure we update any references that are used to
627 // update PHI nodes later on.
628 if (FirstMBB != LastMBB)
629 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
631 // Free the scheduler state.
633 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
634 TimePassesIsEnabled);
638 // Free the SelectionDAG state, now that we're finished with it.
642 void SelectionDAGISel::DoInstructionSelection() {
643 DEBUG(errs() << "===== Instruction selection begins:\n");
647 // Select target instructions for the DAG.
649 // Number all nodes with a topological order and set DAGSize.
650 DAGSize = CurDAG->AssignTopologicalOrder();
652 // Create a dummy node (which is not added to allnodes), that adds
653 // a reference to the root node, preventing it from being deleted,
654 // and tracking any changes of the root.
655 HandleSDNode Dummy(CurDAG->getRoot());
656 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
659 // The AllNodes list is now topological-sorted. Visit the
660 // nodes by starting at the end of the list (the root of the
661 // graph) and preceding back toward the beginning (the entry
663 while (ISelPosition != CurDAG->allnodes_begin()) {
664 SDNode *Node = --ISelPosition;
665 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
666 // but there are currently some corner cases that it misses. Also, this
667 // makes it theoretically possible to disable the DAGCombiner.
668 if (Node->use_empty())
671 SDNode *ResNode = Select(Node);
673 // FIXME: This is pretty gross. 'Select' should be changed to not return
674 // anything at all and this code should be nuked with a tactical strike.
676 // If node should not be replaced, continue with the next one.
677 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
681 ReplaceUses(Node, ResNode);
683 // If after the replacement this node is not used any more,
684 // remove this dead node.
685 if (Node->use_empty()) { // Don't delete EntryToken, etc.
686 ISelUpdater ISU(ISelPosition);
687 CurDAG->RemoveDeadNode(Node, &ISU);
691 CurDAG->setRoot(Dummy.getValue());
694 DEBUG(errs() << "===== Instruction selection ends:\n");
696 PostprocessISelDAG();
699 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
700 /// do other setup for EH landing-pad blocks.
701 void SelectionDAGISel::PrepareEHLandingPad() {
702 // Add a label to mark the beginning of the landing pad. Deletion of the
703 // landing pad can thus be detected via the MachineModuleInfo.
704 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
706 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
707 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
710 // Mark exception register as live in.
711 unsigned Reg = TLI.getExceptionAddressRegister();
712 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
714 // Mark exception selector register as live in.
715 Reg = TLI.getExceptionSelectorRegister();
716 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
718 // FIXME: Hack around an exception handling flaw (PR1508): the personality
719 // function and list of typeids logically belong to the invoke (or, if you
720 // like, the basic block containing the invoke), and need to be associated
721 // with it in the dwarf exception handling tables. Currently however the
722 // information is provided by an intrinsic (eh.selector) that can be moved
723 // to unexpected places by the optimizers: if the unwind edge is critical,
724 // then breaking it can result in the intrinsics being in the successor of
725 // the landing pad, not the landing pad itself. This results
726 // in exceptions not being caught because no typeids are associated with
727 // the invoke. This may not be the only way things can go wrong, but it
728 // is the only way we try to work around for the moment.
729 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
730 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
732 if (Br && Br->isUnconditional()) { // Critical edge?
733 BasicBlock::const_iterator I, E;
734 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
735 if (isa<EHSelectorInst>(I))
739 // No catch info found - try to extract some from the successor.
740 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
747 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
749 // Don't try to fold volatile loads. Target has to deal with alignment
751 if (LI->isVolatile()) return false;
753 // Figure out which vreg this is going into.
754 unsigned LoadReg = FastIS->getRegForValue(LI);
755 assert(LoadReg && "Load isn't already assigned a vreg? ");
757 // Check to see what the uses of this vreg are. If it has no uses, or more
758 // than one use (at the machine instr level) then we can't fold it.
759 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
760 if (RI == RegInfo->reg_end())
763 // See if there is exactly one use of the vreg. If there are multiple uses,
764 // then the instruction got lowered to multiple machine instructions or the
765 // use of the loaded value ended up being multiple operands of the result, in
766 // either case, we can't fold this.
767 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
768 if (PostRI != RegInfo->reg_end())
771 assert(RI.getOperand().isUse() &&
772 "The only use of the vreg must be a use, we haven't emitted the def!");
774 MachineInstr *User = &*RI;
776 // Set the insertion point properly. Folding the load can cause generation of
777 // other random instructions (like sign extends) for addressing modes, make
778 // sure they get inserted in a logical place before the new instruction.
779 FuncInfo->InsertPt = User;
780 FuncInfo->MBB = User->getParent();
782 // Ask the target to try folding the load.
783 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
787 /// CheckLineNumbers - Check if basic block instructions follow source order
789 static void CheckLineNumbers(const BasicBlock *BB) {
792 for (BasicBlock::const_iterator BI = BB->begin(),
793 BE = BB->end(); BI != BE; ++BI) {
794 const DebugLoc DL = BI->getDebugLoc();
795 if (DL.isUnknown()) continue;
796 unsigned L = DL.getLine();
797 unsigned C = DL.getCol();
798 if (L < Line || (L == Line && C < Col)) {
799 ++NumBBWithOutOfOrderLineInfo;
807 /// CheckLineNumbers - Check if machine basic block instructions follow source
809 static void CheckLineNumbers(const MachineBasicBlock *MBB) {
812 for (MachineBasicBlock::const_iterator MBI = MBB->begin(),
813 MBE = MBB->end(); MBI != MBE; ++MBI) {
814 const DebugLoc DL = MBI->getDebugLoc();
815 if (DL.isUnknown()) continue;
816 unsigned L = DL.getLine();
817 unsigned C = DL.getCol();
818 if (L < Line || (L == Line && C < Col)) {
819 ++NumMBBWithOutOfOrderLineInfo;
828 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
829 // Initialize the Fast-ISel state, if needed.
830 FastISel *FastIS = 0;
832 FastIS = TLI.createFastISel(*FuncInfo);
834 // Iterate over all basic blocks in the function.
835 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
836 const BasicBlock *LLVMBB = &*I;
838 CheckLineNumbers(LLVMBB);
840 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
841 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
843 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
844 BasicBlock::const_iterator const End = LLVMBB->end();
845 BasicBlock::const_iterator BI = End;
847 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
849 // Setup an EH landing-pad block.
850 if (FuncInfo->MBB->isLandingPad())
851 PrepareEHLandingPad();
853 // Lower any arguments needed in this block if this is the entry block.
854 if (LLVMBB == &Fn.getEntryBlock())
855 LowerArguments(LLVMBB);
857 // Before doing SelectionDAG ISel, see if FastISel has been requested.
859 FastIS->startNewBlock();
861 // Emit code for any incoming arguments. This must happen before
862 // beginning FastISel on the entry block.
863 if (LLVMBB == &Fn.getEntryBlock()) {
864 CurDAG->setRoot(SDB->getControlRoot());
868 // If we inserted any instructions at the beginning, make a note of
869 // where they are, so we can be sure to emit subsequent instructions
871 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
872 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
874 FastIS->setLastLocalValue(0);
877 // Do FastISel on as many instructions as possible.
878 for (; BI != Begin; --BI) {
879 const Instruction *Inst = llvm::prior(BI);
881 // If we no longer require this instruction, skip it.
882 if (!Inst->mayWriteToMemory() &&
883 !isa<TerminatorInst>(Inst) &&
884 !isa<DbgInfoIntrinsic>(Inst) &&
885 !FuncInfo->isExportedInst(Inst))
888 // Bottom-up: reset the insert pos at the top, after any local-value
890 FastIS->recomputeInsertPt();
892 // Try to select the instruction with FastISel.
893 if (FastIS->SelectInstruction(Inst)) {
894 // If fast isel succeeded, check to see if there is a single-use
895 // non-volatile load right before the selected instruction, and see if
896 // the load is used by the instruction. If so, try to fold it.
897 const Instruction *BeforeInst = 0;
899 BeforeInst = llvm::prior(llvm::prior(BI));
900 if (BeforeInst && isa<LoadInst>(BeforeInst) &&
901 BeforeInst->hasOneUse() && *BeforeInst->use_begin() == Inst &&
902 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), FastIS))
903 --BI; // If we succeeded, don't re-select the load.
907 // Then handle certain instructions as single-LLVM-Instruction blocks.
908 if (isa<CallInst>(Inst)) {
909 ++NumFastIselFailures;
910 if (EnableFastISelVerbose || EnableFastISelAbort) {
911 dbgs() << "FastISel missed call: ";
915 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
916 unsigned &R = FuncInfo->ValueMap[Inst];
918 R = FuncInfo->CreateRegs(Inst->getType());
921 bool HadTailCall = false;
922 SelectBasicBlock(Inst, BI, HadTailCall);
924 // If the call was emitted as a tail call, we're done with the block.
933 // Otherwise, give up on FastISel for the rest of the block.
934 // For now, be a little lenient about non-branch terminators.
935 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) {
936 ++NumFastIselFailures;
937 if (EnableFastISelVerbose || EnableFastISelAbort) {
938 dbgs() << "FastISel miss: ";
941 if (EnableFastISelAbort)
942 // The "fast" selector couldn't handle something and bailed.
943 // For the purpose of debugging, just abort.
944 llvm_unreachable("FastISel didn't select the entire block");
949 FastIS->recomputeInsertPt();
957 // Run SelectionDAG instruction selection on the remainder of the block
958 // not handled by FastISel. If FastISel is not run, this is the entire
961 SelectBasicBlock(Begin, BI, HadTailCall);
964 FuncInfo->PHINodesToUpdate.clear();
969 for (MachineFunction::const_iterator MBI = MF->begin(), MBE = MF->end();
971 CheckLineNumbers(MBI);
976 SelectionDAGISel::FinishBasicBlock() {
978 DEBUG(dbgs() << "Total amount of phi nodes to update: "
979 << FuncInfo->PHINodesToUpdate.size() << "\n";
980 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
981 dbgs() << "Node " << i << " : ("
982 << FuncInfo->PHINodesToUpdate[i].first
983 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
985 // Next, now that we know what the last MBB the LLVM BB expanded is, update
986 // PHI nodes in successors.
987 if (SDB->SwitchCases.empty() &&
988 SDB->JTCases.empty() &&
989 SDB->BitTestCases.empty()) {
990 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
991 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
992 assert(PHI->isPHI() &&
993 "This is not a machine PHI node that we are updating!");
994 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
997 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
998 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1003 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1004 // Lower header first, if it wasn't already lowered
1005 if (!SDB->BitTestCases[i].Emitted) {
1006 // Set the current basic block to the mbb we wish to insert the code into
1007 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1008 FuncInfo->InsertPt = FuncInfo->MBB->end();
1010 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1011 CurDAG->setRoot(SDB->getRoot());
1013 CodeGenAndEmitDAG();
1016 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1017 // Set the current basic block to the mbb we wish to insert the code into
1018 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1019 FuncInfo->InsertPt = FuncInfo->MBB->end();
1022 SDB->visitBitTestCase(SDB->BitTestCases[i],
1023 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1024 SDB->BitTestCases[i].Reg,
1025 SDB->BitTestCases[i].Cases[j],
1028 SDB->visitBitTestCase(SDB->BitTestCases[i],
1029 SDB->BitTestCases[i].Default,
1030 SDB->BitTestCases[i].Reg,
1031 SDB->BitTestCases[i].Cases[j],
1035 CurDAG->setRoot(SDB->getRoot());
1037 CodeGenAndEmitDAG();
1041 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1043 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1044 MachineBasicBlock *PHIBB = PHI->getParent();
1045 assert(PHI->isPHI() &&
1046 "This is not a machine PHI node that we are updating!");
1047 // This is "default" BB. We have two jumps to it. From "header" BB and
1048 // from last "case" BB.
1049 if (PHIBB == SDB->BitTestCases[i].Default) {
1050 PHI->addOperand(MachineOperand::
1051 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1053 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1054 PHI->addOperand(MachineOperand::
1055 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1057 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1060 // One of "cases" BB.
1061 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1063 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1064 if (cBB->isSuccessor(PHIBB)) {
1065 PHI->addOperand(MachineOperand::
1066 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1068 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1073 SDB->BitTestCases.clear();
1075 // If the JumpTable record is filled in, then we need to emit a jump table.
1076 // Updating the PHI nodes is tricky in this case, since we need to determine
1077 // whether the PHI is a successor of the range check MBB or the jump table MBB
1078 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1079 // Lower header first, if it wasn't already lowered
1080 if (!SDB->JTCases[i].first.Emitted) {
1081 // Set the current basic block to the mbb we wish to insert the code into
1082 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1083 FuncInfo->InsertPt = FuncInfo->MBB->end();
1085 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1087 CurDAG->setRoot(SDB->getRoot());
1089 CodeGenAndEmitDAG();
1092 // Set the current basic block to the mbb we wish to insert the code into
1093 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1094 FuncInfo->InsertPt = FuncInfo->MBB->end();
1096 SDB->visitJumpTable(SDB->JTCases[i].second);
1097 CurDAG->setRoot(SDB->getRoot());
1099 CodeGenAndEmitDAG();
1102 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1104 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1105 MachineBasicBlock *PHIBB = PHI->getParent();
1106 assert(PHI->isPHI() &&
1107 "This is not a machine PHI node that we are updating!");
1108 // "default" BB. We can go there only from header BB.
1109 if (PHIBB == SDB->JTCases[i].second.Default) {
1111 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1114 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1116 // JT BB. Just iterate over successors here
1117 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1119 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1121 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1125 SDB->JTCases.clear();
1127 // If the switch block involved a branch to one of the actual successors, we
1128 // need to update PHI nodes in that block.
1129 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1130 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1131 assert(PHI->isPHI() &&
1132 "This is not a machine PHI node that we are updating!");
1133 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1135 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1136 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1140 // If we generated any switch lowering information, build and codegen any
1141 // additional DAGs necessary.
1142 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1143 // Set the current basic block to the mbb we wish to insert the code into
1144 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1145 FuncInfo->InsertPt = FuncInfo->MBB->end();
1147 // Determine the unique successors.
1148 SmallVector<MachineBasicBlock *, 2> Succs;
1149 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1150 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1151 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1153 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1154 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1155 CurDAG->setRoot(SDB->getRoot());
1157 CodeGenAndEmitDAG();
1159 // Remember the last block, now that any splitting is done, for use in
1160 // populating PHI nodes in successors.
1161 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1163 // Handle any PHI nodes in successors of this chunk, as if we were coming
1164 // from the original BB before switch expansion. Note that PHI nodes can
1165 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1166 // handle them the right number of times.
1167 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1168 FuncInfo->MBB = Succs[i];
1169 FuncInfo->InsertPt = FuncInfo->MBB->end();
1170 // FuncInfo->MBB may have been removed from the CFG if a branch was
1172 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1173 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1174 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1176 // This value for this PHI node is recorded in PHINodesToUpdate.
1177 for (unsigned pn = 0; ; ++pn) {
1178 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1179 "Didn't find PHI entry!");
1180 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1181 Phi->addOperand(MachineOperand::
1182 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1184 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1192 SDB->SwitchCases.clear();
1196 /// Create the scheduler. If a specific scheduler was specified
1197 /// via the SchedulerRegistry, use it, otherwise select the
1198 /// one preferred by the target.
1200 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1201 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1205 RegisterScheduler::setDefault(Ctor);
1208 return Ctor(this, OptLevel);
1211 //===----------------------------------------------------------------------===//
1212 // Helper functions used by the generated instruction selector.
1213 //===----------------------------------------------------------------------===//
1214 // Calls to these methods are generated by tblgen.
1216 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1217 /// the dag combiner simplified the 255, we still want to match. RHS is the
1218 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1219 /// specified in the .td file (e.g. 255).
1220 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1221 int64_t DesiredMaskS) const {
1222 const APInt &ActualMask = RHS->getAPIntValue();
1223 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1225 // If the actual mask exactly matches, success!
1226 if (ActualMask == DesiredMask)
1229 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1230 if (ActualMask.intersects(~DesiredMask))
1233 // Otherwise, the DAG Combiner may have proven that the value coming in is
1234 // either already zero or is not demanded. Check for known zero input bits.
1235 APInt NeededMask = DesiredMask & ~ActualMask;
1236 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1239 // TODO: check to see if missing bits are just not demanded.
1241 // Otherwise, this pattern doesn't match.
1245 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1246 /// the dag combiner simplified the 255, we still want to match. RHS is the
1247 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1248 /// specified in the .td file (e.g. 255).
1249 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1250 int64_t DesiredMaskS) const {
1251 const APInt &ActualMask = RHS->getAPIntValue();
1252 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1254 // If the actual mask exactly matches, success!
1255 if (ActualMask == DesiredMask)
1258 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1259 if (ActualMask.intersects(~DesiredMask))
1262 // Otherwise, the DAG Combiner may have proven that the value coming in is
1263 // either already zero or is not demanded. Check for known zero input bits.
1264 APInt NeededMask = DesiredMask & ~ActualMask;
1266 APInt KnownZero, KnownOne;
1267 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1269 // If all the missing bits in the or are already known to be set, match!
1270 if ((NeededMask & KnownOne) == NeededMask)
1273 // TODO: check to see if missing bits are just not demanded.
1275 // Otherwise, this pattern doesn't match.
1280 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1281 /// by tblgen. Others should not call it.
1282 void SelectionDAGISel::
1283 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1284 std::vector<SDValue> InOps;
1285 std::swap(InOps, Ops);
1287 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1288 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1289 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1290 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1292 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1293 if (InOps[e-1].getValueType() == MVT::Glue)
1294 --e; // Don't process a glue operand if it is here.
1297 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1298 if (!InlineAsm::isMemKind(Flags)) {
1299 // Just skip over this operand, copying the operands verbatim.
1300 Ops.insert(Ops.end(), InOps.begin()+i,
1301 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1302 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1304 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1305 "Memory operand with multiple values?");
1306 // Otherwise, this is a memory operand. Ask the target to select it.
1307 std::vector<SDValue> SelOps;
1308 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1309 report_fatal_error("Could not match memory address. Inline asm"
1312 // Add this to the output node.
1314 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1315 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1316 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1321 // Add the glue input back if present.
1322 if (e != InOps.size())
1323 Ops.push_back(InOps.back());
1326 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1329 static SDNode *findGlueUse(SDNode *N) {
1330 unsigned FlagResNo = N->getNumValues()-1;
1331 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1332 SDUse &Use = I.getUse();
1333 if (Use.getResNo() == FlagResNo)
1334 return Use.getUser();
1339 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1340 /// This function recursively traverses up the operand chain, ignoring
1342 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1343 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1344 bool IgnoreChains) {
1345 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1346 // greater than all of its (recursive) operands. If we scan to a point where
1347 // 'use' is smaller than the node we're scanning for, then we know we will
1350 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1351 // happen because we scan down to newly selected nodes in the case of glue
1353 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1356 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1357 // won't fail if we scan it again.
1358 if (!Visited.insert(Use))
1361 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1362 // Ignore chain uses, they are validated by HandleMergeInputChains.
1363 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1366 SDNode *N = Use->getOperand(i).getNode();
1368 if (Use == ImmedUse || Use == Root)
1369 continue; // We are not looking for immediate use.
1374 // Traverse up the operand chain.
1375 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1381 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1382 /// operand node N of U during instruction selection that starts at Root.
1383 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1384 SDNode *Root) const {
1385 if (OptLevel == CodeGenOpt::None) return false;
1386 return N.hasOneUse();
1389 /// IsLegalToFold - Returns true if the specific operand node N of
1390 /// U can be folded during instruction selection that starts at Root.
1391 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1392 CodeGenOpt::Level OptLevel,
1393 bool IgnoreChains) {
1394 if (OptLevel == CodeGenOpt::None) return false;
1396 // If Root use can somehow reach N through a path that that doesn't contain
1397 // U then folding N would create a cycle. e.g. In the following
1398 // diagram, Root can reach N through X. If N is folded into into Root, then
1399 // X is both a predecessor and a successor of U.
1410 // * indicates nodes to be folded together.
1412 // If Root produces glue, then it gets (even more) interesting. Since it
1413 // will be "glued" together with its glue use in the scheduler, we need to
1414 // check if it might reach N.
1433 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1434 // (call it Fold), then X is a predecessor of GU and a successor of
1435 // Fold. But since Fold and GU are glued together, this will create
1436 // a cycle in the scheduling graph.
1438 // If the node has glue, walk down the graph to the "lowest" node in the
1440 EVT VT = Root->getValueType(Root->getNumValues()-1);
1441 while (VT == MVT::Glue) {
1442 SDNode *GU = findGlueUse(Root);
1446 VT = Root->getValueType(Root->getNumValues()-1);
1448 // If our query node has a glue result with a use, we've walked up it. If
1449 // the user (which has already been selected) has a chain or indirectly uses
1450 // the chain, our WalkChainUsers predicate will not consider it. Because of
1451 // this, we cannot ignore chains in this predicate.
1452 IgnoreChains = false;
1456 SmallPtrSet<SDNode*, 16> Visited;
1457 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1460 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1461 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1462 SelectInlineAsmMemoryOperands(Ops);
1464 std::vector<EVT> VTs;
1465 VTs.push_back(MVT::Other);
1466 VTs.push_back(MVT::Glue);
1467 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1468 VTs, &Ops[0], Ops.size());
1470 return New.getNode();
1473 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1474 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1477 /// GetVBR - decode a vbr encoding whose top bit is set.
1478 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1479 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1480 assert(Val >= 128 && "Not a VBR");
1481 Val &= 127; // Remove first vbr bit.
1486 NextBits = MatcherTable[Idx++];
1487 Val |= (NextBits&127) << Shift;
1489 } while (NextBits & 128);
1495 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1496 /// interior glue and chain results to use the new glue and chain results.
1497 void SelectionDAGISel::
1498 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1499 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1501 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1502 bool isMorphNodeTo) {
1503 SmallVector<SDNode*, 4> NowDeadNodes;
1505 ISelUpdater ISU(ISelPosition);
1507 // Now that all the normal results are replaced, we replace the chain and
1508 // glue results if present.
1509 if (!ChainNodesMatched.empty()) {
1510 assert(InputChain.getNode() != 0 &&
1511 "Matched input chains but didn't produce a chain");
1512 // Loop over all of the nodes we matched that produced a chain result.
1513 // Replace all the chain results with the final chain we ended up with.
1514 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1515 SDNode *ChainNode = ChainNodesMatched[i];
1517 // If this node was already deleted, don't look at it.
1518 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1521 // Don't replace the results of the root node if we're doing a
1523 if (ChainNode == NodeToMatch && isMorphNodeTo)
1526 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1527 if (ChainVal.getValueType() == MVT::Glue)
1528 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1529 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1530 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1532 // If the node became dead and we haven't already seen it, delete it.
1533 if (ChainNode->use_empty() &&
1534 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1535 NowDeadNodes.push_back(ChainNode);
1539 // If the result produces glue, update any glue results in the matched
1540 // pattern with the glue result.
1541 if (InputGlue.getNode() != 0) {
1542 // Handle any interior nodes explicitly marked.
1543 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1544 SDNode *FRN = GlueResultNodesMatched[i];
1546 // If this node was already deleted, don't look at it.
1547 if (FRN->getOpcode() == ISD::DELETED_NODE)
1550 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1551 "Doesn't have a glue result");
1552 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1555 // If the node became dead and we haven't already seen it, delete it.
1556 if (FRN->use_empty() &&
1557 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1558 NowDeadNodes.push_back(FRN);
1562 if (!NowDeadNodes.empty())
1563 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1565 DEBUG(errs() << "ISEL: Match complete!\n");
1571 CR_LeadsToInteriorNode
1574 /// WalkChainUsers - Walk down the users of the specified chained node that is
1575 /// part of the pattern we're matching, looking at all of the users we find.
1576 /// This determines whether something is an interior node, whether we have a
1577 /// non-pattern node in between two pattern nodes (which prevent folding because
1578 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1579 /// between pattern nodes (in which case the TF becomes part of the pattern).
1581 /// The walk we do here is guaranteed to be small because we quickly get down to
1582 /// already selected nodes "below" us.
1584 WalkChainUsers(SDNode *ChainedNode,
1585 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1586 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1587 ChainResult Result = CR_Simple;
1589 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1590 E = ChainedNode->use_end(); UI != E; ++UI) {
1591 // Make sure the use is of the chain, not some other value we produce.
1592 if (UI.getUse().getValueType() != MVT::Other) continue;
1596 // If we see an already-selected machine node, then we've gone beyond the
1597 // pattern that we're selecting down into the already selected chunk of the
1599 if (User->isMachineOpcode() ||
1600 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1603 if (User->getOpcode() == ISD::CopyToReg ||
1604 User->getOpcode() == ISD::CopyFromReg ||
1605 User->getOpcode() == ISD::INLINEASM ||
1606 User->getOpcode() == ISD::EH_LABEL) {
1607 // If their node ID got reset to -1 then they've already been selected.
1608 // Treat them like a MachineOpcode.
1609 if (User->getNodeId() == -1)
1613 // If we have a TokenFactor, we handle it specially.
1614 if (User->getOpcode() != ISD::TokenFactor) {
1615 // If the node isn't a token factor and isn't part of our pattern, then it
1616 // must be a random chained node in between two nodes we're selecting.
1617 // This happens when we have something like:
1622 // Because we structurally match the load/store as a read/modify/write,
1623 // but the call is chained between them. We cannot fold in this case
1624 // because it would induce a cycle in the graph.
1625 if (!std::count(ChainedNodesInPattern.begin(),
1626 ChainedNodesInPattern.end(), User))
1627 return CR_InducesCycle;
1629 // Otherwise we found a node that is part of our pattern. For example in:
1633 // This would happen when we're scanning down from the load and see the
1634 // store as a user. Record that there is a use of ChainedNode that is
1635 // part of the pattern and keep scanning uses.
1636 Result = CR_LeadsToInteriorNode;
1637 InteriorChainedNodes.push_back(User);
1641 // If we found a TokenFactor, there are two cases to consider: first if the
1642 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1643 // uses of the TF are in our pattern) we just want to ignore it. Second,
1644 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1650 // | \ DAG's like cheese
1653 // [TokenFactor] [Op]
1660 // In this case, the TokenFactor becomes part of our match and we rewrite it
1661 // as a new TokenFactor.
1663 // To distinguish these two cases, do a recursive walk down the uses.
1664 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1666 // If the uses of the TokenFactor are just already-selected nodes, ignore
1667 // it, it is "below" our pattern.
1669 case CR_InducesCycle:
1670 // If the uses of the TokenFactor lead to nodes that are not part of our
1671 // pattern that are not selected, folding would turn this into a cycle,
1673 return CR_InducesCycle;
1674 case CR_LeadsToInteriorNode:
1675 break; // Otherwise, keep processing.
1678 // Okay, we know we're in the interesting interior case. The TokenFactor
1679 // is now going to be considered part of the pattern so that we rewrite its
1680 // uses (it may have uses that are not part of the pattern) with the
1681 // ultimate chain result of the generated code. We will also add its chain
1682 // inputs as inputs to the ultimate TokenFactor we create.
1683 Result = CR_LeadsToInteriorNode;
1684 ChainedNodesInPattern.push_back(User);
1685 InteriorChainedNodes.push_back(User);
1692 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1693 /// operation for when the pattern matched at least one node with a chains. The
1694 /// input vector contains a list of all of the chained nodes that we match. We
1695 /// must determine if this is a valid thing to cover (i.e. matching it won't
1696 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1697 /// be used as the input node chain for the generated nodes.
1699 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1700 SelectionDAG *CurDAG) {
1701 // Walk all of the chained nodes we've matched, recursively scanning down the
1702 // users of the chain result. This adds any TokenFactor nodes that are caught
1703 // in between chained nodes to the chained and interior nodes list.
1704 SmallVector<SDNode*, 3> InteriorChainedNodes;
1705 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1706 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1707 InteriorChainedNodes) == CR_InducesCycle)
1708 return SDValue(); // Would induce a cycle.
1711 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1712 // that we are interested in. Form our input TokenFactor node.
1713 SmallVector<SDValue, 3> InputChains;
1714 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1715 // Add the input chain of this node to the InputChains list (which will be
1716 // the operands of the generated TokenFactor) if it's not an interior node.
1717 SDNode *N = ChainNodesMatched[i];
1718 if (N->getOpcode() != ISD::TokenFactor) {
1719 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1722 // Otherwise, add the input chain.
1723 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1724 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1725 InputChains.push_back(InChain);
1729 // If we have a token factor, we want to add all inputs of the token factor
1730 // that are not part of the pattern we're matching.
1731 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1732 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1733 N->getOperand(op).getNode()))
1734 InputChains.push_back(N->getOperand(op));
1739 if (InputChains.size() == 1)
1740 return InputChains[0];
1741 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1742 MVT::Other, &InputChains[0], InputChains.size());
1745 /// MorphNode - Handle morphing a node in place for the selector.
1746 SDNode *SelectionDAGISel::
1747 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1748 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1749 // It is possible we're using MorphNodeTo to replace a node with no
1750 // normal results with one that has a normal result (or we could be
1751 // adding a chain) and the input could have glue and chains as well.
1752 // In this case we need to shift the operands down.
1753 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1754 // than the old isel though.
1755 int OldGlueResultNo = -1, OldChainResultNo = -1;
1757 unsigned NTMNumResults = Node->getNumValues();
1758 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1759 OldGlueResultNo = NTMNumResults-1;
1760 if (NTMNumResults != 1 &&
1761 Node->getValueType(NTMNumResults-2) == MVT::Other)
1762 OldChainResultNo = NTMNumResults-2;
1763 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1764 OldChainResultNo = NTMNumResults-1;
1766 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1767 // that this deletes operands of the old node that become dead.
1768 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1770 // MorphNodeTo can operate in two ways: if an existing node with the
1771 // specified operands exists, it can just return it. Otherwise, it
1772 // updates the node in place to have the requested operands.
1774 // If we updated the node in place, reset the node ID. To the isel,
1775 // this should be just like a newly allocated machine node.
1779 unsigned ResNumResults = Res->getNumValues();
1780 // Move the glue if needed.
1781 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1782 (unsigned)OldGlueResultNo != ResNumResults-1)
1783 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1784 SDValue(Res, ResNumResults-1));
1786 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1789 // Move the chain reference if needed.
1790 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1791 (unsigned)OldChainResultNo != ResNumResults-1)
1792 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1793 SDValue(Res, ResNumResults-1));
1795 // Otherwise, no replacement happened because the node already exists. Replace
1796 // Uses of the old node with the new one.
1798 CurDAG->ReplaceAllUsesWith(Node, Res);
1803 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1804 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1805 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1807 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1808 // Accept if it is exactly the same as a previously recorded node.
1809 unsigned RecNo = MatcherTable[MatcherIndex++];
1810 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1811 return N == RecordedNodes[RecNo].first;
1814 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1815 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1816 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1817 SelectionDAGISel &SDISel) {
1818 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1821 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1822 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1823 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1824 SelectionDAGISel &SDISel, SDNode *N) {
1825 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1828 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1829 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1831 uint16_t Opc = MatcherTable[MatcherIndex++];
1832 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1833 return N->getOpcode() == Opc;
1836 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1837 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1838 SDValue N, const TargetLowering &TLI) {
1839 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1840 if (N.getValueType() == VT) return true;
1842 // Handle the case when VT is iPTR.
1843 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1846 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1847 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1848 SDValue N, const TargetLowering &TLI,
1850 if (ChildNo >= N.getNumOperands())
1851 return false; // Match fails if out of range child #.
1852 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1856 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1857 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1859 return cast<CondCodeSDNode>(N)->get() ==
1860 (ISD::CondCode)MatcherTable[MatcherIndex++];
1863 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1864 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1865 SDValue N, const TargetLowering &TLI) {
1866 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1867 if (cast<VTSDNode>(N)->getVT() == VT)
1870 // Handle the case when VT is iPTR.
1871 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1874 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1875 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1877 int64_t Val = MatcherTable[MatcherIndex++];
1879 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1881 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1882 return C != 0 && C->getSExtValue() == Val;
1885 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1886 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1887 SDValue N, SelectionDAGISel &SDISel) {
1888 int64_t Val = MatcherTable[MatcherIndex++];
1890 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1892 if (N->getOpcode() != ISD::AND) return false;
1894 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1895 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1898 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1899 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1900 SDValue N, SelectionDAGISel &SDISel) {
1901 int64_t Val = MatcherTable[MatcherIndex++];
1903 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1905 if (N->getOpcode() != ISD::OR) return false;
1907 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1908 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1911 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1912 /// scope, evaluate the current node. If the current predicate is known to
1913 /// fail, set Result=true and return anything. If the current predicate is
1914 /// known to pass, set Result=false and return the MatcherIndex to continue
1915 /// with. If the current predicate is unknown, set Result=false and return the
1916 /// MatcherIndex to continue with.
1917 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1918 unsigned Index, SDValue N,
1919 bool &Result, SelectionDAGISel &SDISel,
1920 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1921 switch (Table[Index++]) {
1924 return Index-1; // Could not evaluate this predicate.
1925 case SelectionDAGISel::OPC_CheckSame:
1926 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1928 case SelectionDAGISel::OPC_CheckPatternPredicate:
1929 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1931 case SelectionDAGISel::OPC_CheckPredicate:
1932 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1934 case SelectionDAGISel::OPC_CheckOpcode:
1935 Result = !::CheckOpcode(Table, Index, N.getNode());
1937 case SelectionDAGISel::OPC_CheckType:
1938 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1940 case SelectionDAGISel::OPC_CheckChild0Type:
1941 case SelectionDAGISel::OPC_CheckChild1Type:
1942 case SelectionDAGISel::OPC_CheckChild2Type:
1943 case SelectionDAGISel::OPC_CheckChild3Type:
1944 case SelectionDAGISel::OPC_CheckChild4Type:
1945 case SelectionDAGISel::OPC_CheckChild5Type:
1946 case SelectionDAGISel::OPC_CheckChild6Type:
1947 case SelectionDAGISel::OPC_CheckChild7Type:
1948 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1949 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1951 case SelectionDAGISel::OPC_CheckCondCode:
1952 Result = !::CheckCondCode(Table, Index, N);
1954 case SelectionDAGISel::OPC_CheckValueType:
1955 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1957 case SelectionDAGISel::OPC_CheckInteger:
1958 Result = !::CheckInteger(Table, Index, N);
1960 case SelectionDAGISel::OPC_CheckAndImm:
1961 Result = !::CheckAndImm(Table, Index, N, SDISel);
1963 case SelectionDAGISel::OPC_CheckOrImm:
1964 Result = !::CheckOrImm(Table, Index, N, SDISel);
1972 /// FailIndex - If this match fails, this is the index to continue with.
1975 /// NodeStack - The node stack when the scope was formed.
1976 SmallVector<SDValue, 4> NodeStack;
1978 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1979 unsigned NumRecordedNodes;
1981 /// NumMatchedMemRefs - The number of matched memref entries.
1982 unsigned NumMatchedMemRefs;
1984 /// InputChain/InputGlue - The current chain/glue
1985 SDValue InputChain, InputGlue;
1987 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1988 bool HasChainNodesMatched, HasGlueResultNodesMatched;
1993 SDNode *SelectionDAGISel::
1994 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1995 unsigned TableSize) {
1996 // FIXME: Should these even be selected? Handle these cases in the caller?
1997 switch (NodeToMatch->getOpcode()) {
2000 case ISD::EntryToken: // These nodes remain the same.
2001 case ISD::BasicBlock:
2003 //case ISD::VALUETYPE:
2004 //case ISD::CONDCODE:
2005 case ISD::HANDLENODE:
2006 case ISD::MDNODE_SDNODE:
2007 case ISD::TargetConstant:
2008 case ISD::TargetConstantFP:
2009 case ISD::TargetConstantPool:
2010 case ISD::TargetFrameIndex:
2011 case ISD::TargetExternalSymbol:
2012 case ISD::TargetBlockAddress:
2013 case ISD::TargetJumpTable:
2014 case ISD::TargetGlobalTLSAddress:
2015 case ISD::TargetGlobalAddress:
2016 case ISD::TokenFactor:
2017 case ISD::CopyFromReg:
2018 case ISD::CopyToReg:
2020 NodeToMatch->setNodeId(-1); // Mark selected.
2022 case ISD::AssertSext:
2023 case ISD::AssertZext:
2024 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2025 NodeToMatch->getOperand(0));
2027 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2028 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2031 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2033 // Set up the node stack with NodeToMatch as the only node on the stack.
2034 SmallVector<SDValue, 8> NodeStack;
2035 SDValue N = SDValue(NodeToMatch, 0);
2036 NodeStack.push_back(N);
2038 // MatchScopes - Scopes used when matching, if a match failure happens, this
2039 // indicates where to continue checking.
2040 SmallVector<MatchScope, 8> MatchScopes;
2042 // RecordedNodes - This is the set of nodes that have been recorded by the
2043 // state machine. The second value is the parent of the node, or null if the
2044 // root is recorded.
2045 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2047 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2049 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2051 // These are the current input chain and glue for use when generating nodes.
2052 // Various Emit operations change these. For example, emitting a copytoreg
2053 // uses and updates these.
2054 SDValue InputChain, InputGlue;
2056 // ChainNodesMatched - If a pattern matches nodes that have input/output
2057 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2058 // which ones they are. The result is captured into this list so that we can
2059 // update the chain results when the pattern is complete.
2060 SmallVector<SDNode*, 3> ChainNodesMatched;
2061 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2063 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2064 NodeToMatch->dump(CurDAG);
2067 // Determine where to start the interpreter. Normally we start at opcode #0,
2068 // but if the state machine starts with an OPC_SwitchOpcode, then we
2069 // accelerate the first lookup (which is guaranteed to be hot) with the
2070 // OpcodeOffset table.
2071 unsigned MatcherIndex = 0;
2073 if (!OpcodeOffset.empty()) {
2074 // Already computed the OpcodeOffset table, just index into it.
2075 if (N.getOpcode() < OpcodeOffset.size())
2076 MatcherIndex = OpcodeOffset[N.getOpcode()];
2077 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2079 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2080 // Otherwise, the table isn't computed, but the state machine does start
2081 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2082 // is the first time we're selecting an instruction.
2085 // Get the size of this case.
2086 unsigned CaseSize = MatcherTable[Idx++];
2088 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2089 if (CaseSize == 0) break;
2091 // Get the opcode, add the index to the table.
2092 uint16_t Opc = MatcherTable[Idx++];
2093 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2094 if (Opc >= OpcodeOffset.size())
2095 OpcodeOffset.resize((Opc+1)*2);
2096 OpcodeOffset[Opc] = Idx;
2100 // Okay, do the lookup for the first opcode.
2101 if (N.getOpcode() < OpcodeOffset.size())
2102 MatcherIndex = OpcodeOffset[N.getOpcode()];
2106 assert(MatcherIndex < TableSize && "Invalid index");
2108 unsigned CurrentOpcodeIndex = MatcherIndex;
2110 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2113 // Okay, the semantics of this operation are that we should push a scope
2114 // then evaluate the first child. However, pushing a scope only to have
2115 // the first check fail (which then pops it) is inefficient. If we can
2116 // determine immediately that the first check (or first several) will
2117 // immediately fail, don't even bother pushing a scope for them.
2121 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2122 if (NumToSkip & 128)
2123 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2124 // Found the end of the scope with no match.
2125 if (NumToSkip == 0) {
2130 FailIndex = MatcherIndex+NumToSkip;
2132 unsigned MatcherIndexOfPredicate = MatcherIndex;
2133 (void)MatcherIndexOfPredicate; // silence warning.
2135 // If we can't evaluate this predicate without pushing a scope (e.g. if
2136 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2137 // push the scope and evaluate the full predicate chain.
2139 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2140 Result, *this, RecordedNodes);
2144 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2145 << "index " << MatcherIndexOfPredicate
2146 << ", continuing at " << FailIndex << "\n");
2147 ++NumDAGIselRetries;
2149 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2150 // move to the next case.
2151 MatcherIndex = FailIndex;
2154 // If the whole scope failed to match, bail.
2155 if (FailIndex == 0) break;
2157 // Push a MatchScope which indicates where to go if the first child fails
2159 MatchScope NewEntry;
2160 NewEntry.FailIndex = FailIndex;
2161 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2162 NewEntry.NumRecordedNodes = RecordedNodes.size();
2163 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2164 NewEntry.InputChain = InputChain;
2165 NewEntry.InputGlue = InputGlue;
2166 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2167 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2168 MatchScopes.push_back(NewEntry);
2171 case OPC_RecordNode: {
2172 // Remember this node, it may end up being an operand in the pattern.
2174 if (NodeStack.size() > 1)
2175 Parent = NodeStack[NodeStack.size()-2].getNode();
2176 RecordedNodes.push_back(std::make_pair(N, Parent));
2180 case OPC_RecordChild0: case OPC_RecordChild1:
2181 case OPC_RecordChild2: case OPC_RecordChild3:
2182 case OPC_RecordChild4: case OPC_RecordChild5:
2183 case OPC_RecordChild6: case OPC_RecordChild7: {
2184 unsigned ChildNo = Opcode-OPC_RecordChild0;
2185 if (ChildNo >= N.getNumOperands())
2186 break; // Match fails if out of range child #.
2188 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2192 case OPC_RecordMemRef:
2193 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2196 case OPC_CaptureGlueInput:
2197 // If the current node has an input glue, capture it in InputGlue.
2198 if (N->getNumOperands() != 0 &&
2199 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2200 InputGlue = N->getOperand(N->getNumOperands()-1);
2203 case OPC_MoveChild: {
2204 unsigned ChildNo = MatcherTable[MatcherIndex++];
2205 if (ChildNo >= N.getNumOperands())
2206 break; // Match fails if out of range child #.
2207 N = N.getOperand(ChildNo);
2208 NodeStack.push_back(N);
2212 case OPC_MoveParent:
2213 // Pop the current node off the NodeStack.
2214 NodeStack.pop_back();
2215 assert(!NodeStack.empty() && "Node stack imbalance!");
2216 N = NodeStack.back();
2220 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2222 case OPC_CheckPatternPredicate:
2223 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2225 case OPC_CheckPredicate:
2226 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2230 case OPC_CheckComplexPat: {
2231 unsigned CPNum = MatcherTable[MatcherIndex++];
2232 unsigned RecNo = MatcherTable[MatcherIndex++];
2233 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2234 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2235 RecordedNodes[RecNo].first, CPNum,
2240 case OPC_CheckOpcode:
2241 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2245 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2248 case OPC_SwitchOpcode: {
2249 unsigned CurNodeOpcode = N.getOpcode();
2250 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2253 // Get the size of this case.
2254 CaseSize = MatcherTable[MatcherIndex++];
2256 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2257 if (CaseSize == 0) break;
2259 uint16_t Opc = MatcherTable[MatcherIndex++];
2260 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2262 // If the opcode matches, then we will execute this case.
2263 if (CurNodeOpcode == Opc)
2266 // Otherwise, skip over this case.
2267 MatcherIndex += CaseSize;
2270 // If no cases matched, bail out.
2271 if (CaseSize == 0) break;
2273 // Otherwise, execute the case we found.
2274 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2275 << " to " << MatcherIndex << "\n");
2279 case OPC_SwitchType: {
2280 MVT CurNodeVT = N.getValueType().getSimpleVT();
2281 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2284 // Get the size of this case.
2285 CaseSize = MatcherTable[MatcherIndex++];
2287 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2288 if (CaseSize == 0) break;
2290 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2291 if (CaseVT == MVT::iPTR)
2292 CaseVT = TLI.getPointerTy();
2294 // If the VT matches, then we will execute this case.
2295 if (CurNodeVT == CaseVT)
2298 // Otherwise, skip over this case.
2299 MatcherIndex += CaseSize;
2302 // If no cases matched, bail out.
2303 if (CaseSize == 0) break;
2305 // Otherwise, execute the case we found.
2306 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2307 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2310 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2311 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2312 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2313 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2314 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2315 Opcode-OPC_CheckChild0Type))
2318 case OPC_CheckCondCode:
2319 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2321 case OPC_CheckValueType:
2322 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2324 case OPC_CheckInteger:
2325 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2327 case OPC_CheckAndImm:
2328 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2330 case OPC_CheckOrImm:
2331 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2334 case OPC_CheckFoldableChainNode: {
2335 assert(NodeStack.size() != 1 && "No parent node");
2336 // Verify that all intermediate nodes between the root and this one have
2338 bool HasMultipleUses = false;
2339 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2340 if (!NodeStack[i].hasOneUse()) {
2341 HasMultipleUses = true;
2344 if (HasMultipleUses) break;
2346 // Check to see that the target thinks this is profitable to fold and that
2347 // we can fold it without inducing cycles in the graph.
2348 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2350 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2351 NodeToMatch, OptLevel,
2352 true/*We validate our own chains*/))
2357 case OPC_EmitInteger: {
2358 MVT::SimpleValueType VT =
2359 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2360 int64_t Val = MatcherTable[MatcherIndex++];
2362 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2363 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2364 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2367 case OPC_EmitRegister: {
2368 MVT::SimpleValueType VT =
2369 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2370 unsigned RegNo = MatcherTable[MatcherIndex++];
2371 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2372 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2376 case OPC_EmitConvertToTarget: {
2377 // Convert from IMM/FPIMM to target version.
2378 unsigned RecNo = MatcherTable[MatcherIndex++];
2379 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2380 SDValue Imm = RecordedNodes[RecNo].first;
2382 if (Imm->getOpcode() == ISD::Constant) {
2383 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2384 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2385 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2386 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2387 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2390 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2394 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2395 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2396 // These are space-optimized forms of OPC_EmitMergeInputChains.
2397 assert(InputChain.getNode() == 0 &&
2398 "EmitMergeInputChains should be the first chain producing node");
2399 assert(ChainNodesMatched.empty() &&
2400 "Should only have one EmitMergeInputChains per match");
2402 // Read all of the chained nodes.
2403 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2404 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2405 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2407 // FIXME: What if other value results of the node have uses not matched
2409 if (ChainNodesMatched.back() != NodeToMatch &&
2410 !RecordedNodes[RecNo].first.hasOneUse()) {
2411 ChainNodesMatched.clear();
2415 // Merge the input chains if they are not intra-pattern references.
2416 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2418 if (InputChain.getNode() == 0)
2419 break; // Failed to merge.
2423 case OPC_EmitMergeInputChains: {
2424 assert(InputChain.getNode() == 0 &&
2425 "EmitMergeInputChains should be the first chain producing node");
2426 // This node gets a list of nodes we matched in the input that have
2427 // chains. We want to token factor all of the input chains to these nodes
2428 // together. However, if any of the input chains is actually one of the
2429 // nodes matched in this pattern, then we have an intra-match reference.
2430 // Ignore these because the newly token factored chain should not refer to
2432 unsigned NumChains = MatcherTable[MatcherIndex++];
2433 assert(NumChains != 0 && "Can't TF zero chains");
2435 assert(ChainNodesMatched.empty() &&
2436 "Should only have one EmitMergeInputChains per match");
2438 // Read all of the chained nodes.
2439 for (unsigned i = 0; i != NumChains; ++i) {
2440 unsigned RecNo = MatcherTable[MatcherIndex++];
2441 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2442 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2444 // FIXME: What if other value results of the node have uses not matched
2446 if (ChainNodesMatched.back() != NodeToMatch &&
2447 !RecordedNodes[RecNo].first.hasOneUse()) {
2448 ChainNodesMatched.clear();
2453 // If the inner loop broke out, the match fails.
2454 if (ChainNodesMatched.empty())
2457 // Merge the input chains if they are not intra-pattern references.
2458 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2460 if (InputChain.getNode() == 0)
2461 break; // Failed to merge.
2466 case OPC_EmitCopyToReg: {
2467 unsigned RecNo = MatcherTable[MatcherIndex++];
2468 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2469 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2471 if (InputChain.getNode() == 0)
2472 InputChain = CurDAG->getEntryNode();
2474 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2475 DestPhysReg, RecordedNodes[RecNo].first,
2478 InputGlue = InputChain.getValue(1);
2482 case OPC_EmitNodeXForm: {
2483 unsigned XFormNo = MatcherTable[MatcherIndex++];
2484 unsigned RecNo = MatcherTable[MatcherIndex++];
2485 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2486 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2487 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2492 case OPC_MorphNodeTo: {
2493 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2494 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2495 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2496 // Get the result VT list.
2497 unsigned NumVTs = MatcherTable[MatcherIndex++];
2498 SmallVector<EVT, 4> VTs;
2499 for (unsigned i = 0; i != NumVTs; ++i) {
2500 MVT::SimpleValueType VT =
2501 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2502 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2506 if (EmitNodeInfo & OPFL_Chain)
2507 VTs.push_back(MVT::Other);
2508 if (EmitNodeInfo & OPFL_GlueOutput)
2509 VTs.push_back(MVT::Glue);
2511 // This is hot code, so optimize the two most common cases of 1 and 2
2514 if (VTs.size() == 1)
2515 VTList = CurDAG->getVTList(VTs[0]);
2516 else if (VTs.size() == 2)
2517 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2519 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2521 // Get the operand list.
2522 unsigned NumOps = MatcherTable[MatcherIndex++];
2523 SmallVector<SDValue, 8> Ops;
2524 for (unsigned i = 0; i != NumOps; ++i) {
2525 unsigned RecNo = MatcherTable[MatcherIndex++];
2527 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2529 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2530 Ops.push_back(RecordedNodes[RecNo].first);
2533 // If there are variadic operands to add, handle them now.
2534 if (EmitNodeInfo & OPFL_VariadicInfo) {
2535 // Determine the start index to copy from.
2536 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2537 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2538 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2539 "Invalid variadic node");
2540 // Copy all of the variadic operands, not including a potential glue
2542 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2544 SDValue V = NodeToMatch->getOperand(i);
2545 if (V.getValueType() == MVT::Glue) break;
2550 // If this has chain/glue inputs, add them.
2551 if (EmitNodeInfo & OPFL_Chain)
2552 Ops.push_back(InputChain);
2553 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2554 Ops.push_back(InputGlue);
2558 if (Opcode != OPC_MorphNodeTo) {
2559 // If this is a normal EmitNode command, just create the new node and
2560 // add the results to the RecordedNodes list.
2561 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2562 VTList, Ops.data(), Ops.size());
2564 // Add all the non-glue/non-chain results to the RecordedNodes list.
2565 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2566 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2567 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2572 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2576 // If the node had chain/glue results, update our notion of the current
2578 if (EmitNodeInfo & OPFL_GlueOutput) {
2579 InputGlue = SDValue(Res, VTs.size()-1);
2580 if (EmitNodeInfo & OPFL_Chain)
2581 InputChain = SDValue(Res, VTs.size()-2);
2582 } else if (EmitNodeInfo & OPFL_Chain)
2583 InputChain = SDValue(Res, VTs.size()-1);
2585 // If the OPFL_MemRefs glue is set on this node, slap all of the
2586 // accumulated memrefs onto it.
2588 // FIXME: This is vastly incorrect for patterns with multiple outputs
2589 // instructions that access memory and for ComplexPatterns that match
2591 if (EmitNodeInfo & OPFL_MemRefs) {
2592 MachineSDNode::mmo_iterator MemRefs =
2593 MF->allocateMemRefsArray(MatchedMemRefs.size());
2594 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2595 cast<MachineSDNode>(Res)
2596 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2600 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2601 << " node: "; Res->dump(CurDAG); errs() << "\n");
2603 // If this was a MorphNodeTo then we're completely done!
2604 if (Opcode == OPC_MorphNodeTo) {
2605 // Update chain and glue uses.
2606 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2607 InputGlue, GlueResultNodesMatched, true);
2614 case OPC_MarkGlueResults: {
2615 unsigned NumNodes = MatcherTable[MatcherIndex++];
2617 // Read and remember all the glue-result nodes.
2618 for (unsigned i = 0; i != NumNodes; ++i) {
2619 unsigned RecNo = MatcherTable[MatcherIndex++];
2621 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2623 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2624 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2629 case OPC_CompleteMatch: {
2630 // The match has been completed, and any new nodes (if any) have been
2631 // created. Patch up references to the matched dag to use the newly
2633 unsigned NumResults = MatcherTable[MatcherIndex++];
2635 for (unsigned i = 0; i != NumResults; ++i) {
2636 unsigned ResSlot = MatcherTable[MatcherIndex++];
2638 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2640 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2641 SDValue Res = RecordedNodes[ResSlot].first;
2643 assert(i < NodeToMatch->getNumValues() &&
2644 NodeToMatch->getValueType(i) != MVT::Other &&
2645 NodeToMatch->getValueType(i) != MVT::Glue &&
2646 "Invalid number of results to complete!");
2647 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2648 NodeToMatch->getValueType(i) == MVT::iPTR ||
2649 Res.getValueType() == MVT::iPTR ||
2650 NodeToMatch->getValueType(i).getSizeInBits() ==
2651 Res.getValueType().getSizeInBits()) &&
2652 "invalid replacement");
2653 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2656 // If the root node defines glue, add it to the glue nodes to update list.
2657 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2658 GlueResultNodesMatched.push_back(NodeToMatch);
2660 // Update chain and glue uses.
2661 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2662 InputGlue, GlueResultNodesMatched, false);
2664 assert(NodeToMatch->use_empty() &&
2665 "Didn't replace all uses of the node?");
2667 // FIXME: We just return here, which interacts correctly with SelectRoot
2668 // above. We should fix this to not return an SDNode* anymore.
2673 // If the code reached this point, then the match failed. See if there is
2674 // another child to try in the current 'Scope', otherwise pop it until we
2675 // find a case to check.
2676 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2677 ++NumDAGIselRetries;
2679 if (MatchScopes.empty()) {
2680 CannotYetSelect(NodeToMatch);
2684 // Restore the interpreter state back to the point where the scope was
2686 MatchScope &LastScope = MatchScopes.back();
2687 RecordedNodes.resize(LastScope.NumRecordedNodes);
2689 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2690 N = NodeStack.back();
2692 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2693 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2694 MatcherIndex = LastScope.FailIndex;
2696 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2698 InputChain = LastScope.InputChain;
2699 InputGlue = LastScope.InputGlue;
2700 if (!LastScope.HasChainNodesMatched)
2701 ChainNodesMatched.clear();
2702 if (!LastScope.HasGlueResultNodesMatched)
2703 GlueResultNodesMatched.clear();
2705 // Check to see what the offset is at the new MatcherIndex. If it is zero
2706 // we have reached the end of this scope, otherwise we have another child
2707 // in the current scope to try.
2708 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2709 if (NumToSkip & 128)
2710 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2712 // If we have another child in this scope to match, update FailIndex and
2714 if (NumToSkip != 0) {
2715 LastScope.FailIndex = MatcherIndex+NumToSkip;
2719 // End of this scope, pop it and try the next child in the containing
2721 MatchScopes.pop_back();
2728 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2730 raw_string_ostream Msg(msg);
2731 Msg << "Cannot select: ";
2733 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2734 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2735 N->getOpcode() != ISD::INTRINSIC_VOID) {
2736 N->printrFull(Msg, CurDAG);
2738 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2740 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2741 if (iid < Intrinsic::num_intrinsics)
2742 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2743 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2744 Msg << "target intrinsic %" << TII->getName(iid);
2746 Msg << "unknown intrinsic #" << iid;
2748 report_fatal_error(Msg.str());
2751 char SelectionDAGISel::ID = 0;