1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetIntrinsicInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/ADT/Statistic.h"
53 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
54 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
57 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
58 cl::desc("Enable verbose messages in the \"fast\" "
59 "instruction selector"));
61 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
62 cl::desc("Enable abort calls when \"fast\" instruction fails"));
66 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
67 cl::desc("Pop up a window to show dags before the first "
70 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
71 cl::desc("Pop up a window to show dags before legalize types"));
73 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
74 cl::desc("Pop up a window to show dags before legalize"));
76 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
77 cl::desc("Pop up a window to show dags before the second "
80 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before the post legalize types"
82 " dag combine pass"));
84 ViewISelDAGs("view-isel-dags", cl::Hidden,
85 cl::desc("Pop up a window to show isel dags as they are selected"));
87 ViewSchedDAGs("view-sched-dags", cl::Hidden,
88 cl::desc("Pop up a window to show sched dags as they are processed"));
90 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
91 cl::desc("Pop up a window to show SUnit dags after they are processed"));
93 static const bool ViewDAGCombine1 = false,
94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
95 ViewDAGCombine2 = false,
96 ViewDAGCombineLT = false,
97 ViewISelDAGs = false, ViewSchedDAGs = false,
98 ViewSUnitDAGs = false;
101 //===---------------------------------------------------------------------===//
103 /// RegisterScheduler class - Track the registration of instruction schedulers.
105 //===---------------------------------------------------------------------===//
106 MachinePassRegistry RegisterScheduler::Registry;
108 //===---------------------------------------------------------------------===//
110 /// ISHeuristic command line option for instruction schedulers.
112 //===---------------------------------------------------------------------===//
113 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
114 RegisterPassParser<RegisterScheduler> >
115 ISHeuristic("pre-RA-sched",
116 cl::init(&createDefaultScheduler),
117 cl::desc("Instruction schedulers available (before register"
120 static RegisterScheduler
121 defaultListDAGScheduler("default", "Best scheduler for the target",
122 createDefaultScheduler);
125 //===--------------------------------------------------------------------===//
126 /// createDefaultScheduler - This creates an instruction scheduler appropriate
128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
129 CodeGenOpt::Level OptLevel) {
130 const TargetLowering &TLI = IS->getTargetLowering();
132 if (OptLevel == CodeGenOpt::None)
133 return createFastDAGScheduler(IS, OptLevel);
134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
135 return createTDListDAGScheduler(IS, OptLevel);
136 assert(TLI.getSchedulingPreference() ==
137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
138 return createBURRListDAGScheduler(IS, OptLevel);
142 // EmitInstrWithCustomInserter - This method should be implemented by targets
143 // that mark instructions with the 'usesCustomInserter' flag. These
144 // instructions are special in various ways, which require special support to
145 // insert. The specified MachineInstr is created but not inserted into any
146 // basic blocks, and this method is called to expand it into a sequence of
147 // instructions, potentially also creating new basic blocks and control flow.
148 // When new basic blocks are inserted and the edges from MBB to its successors
149 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
151 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
152 MachineBasicBlock *MBB,
153 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
155 dbgs() << "If a target marks an instruction with "
156 "'usesCustomInserter', it must implement "
157 "TargetLowering::EmitInstrWithCustomInserter!";
163 //===----------------------------------------------------------------------===//
164 // SelectionDAGISel code
165 //===----------------------------------------------------------------------===//
167 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
169 FuncInfo(new FunctionLoweringInfo(TLI)),
170 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
171 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
177 SelectionDAGISel::~SelectionDAGISel() {
183 unsigned SelectionDAGISel::MakeReg(EVT VT) {
184 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
187 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
188 AU.addRequired<AliasAnalysis>();
189 AU.addPreserved<AliasAnalysis>();
190 AU.addRequired<GCModuleInfo>();
191 AU.addPreserved<GCModuleInfo>();
192 MachineFunctionPass::getAnalysisUsage(AU);
195 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
196 // Do some sanity-checking on the command-line options.
197 assert((!EnableFastISelVerbose || EnableFastISel) &&
198 "-fast-isel-verbose requires -fast-isel");
199 assert((!EnableFastISelAbort || EnableFastISel) &&
200 "-fast-isel-abort requires -fast-isel");
202 Function &Fn = *mf.getFunction();
203 const TargetInstrInfo &TII = *TM.getInstrInfo();
204 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
207 RegInfo = &MF->getRegInfo();
208 AA = &getAnalysis<AliasAnalysis>();
209 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
211 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
214 FuncInfo->set(Fn, *MF, EnableFastISel);
217 SelectAllBasicBlocks(Fn, *MF, TII);
219 // If the first basic block in the function has live ins that need to be
220 // copied into vregs, emit the copies into the top of the block before
221 // emitting the code for the block.
222 RegInfo->EmitLiveInCopies(MF->begin(), TRI, TII);
225 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
226 "Not all catch info was assigned to a landing pad!");
234 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
235 /// attached with this instruction.
236 static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB,
237 FastISel *FastIS, MachineFunction *MF) {
238 DebugLoc DL = I->getDebugLoc();
239 if (DL.isUnknown()) return;
241 SDB->setCurDebugLoc(DL);
244 FastIS->setCurDebugLoc(DL);
246 // If the function doesn't have a default debug location yet, set
247 // it. This is kind of a hack.
248 if (MF->getDefaultDebugLoc().isUnknown())
249 MF->setDefaultDebugLoc(DL);
252 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
253 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
254 SDB->setCurDebugLoc(DebugLoc());
256 FastIS->setCurDebugLoc(DebugLoc());
259 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
260 BasicBlock::iterator Begin,
261 BasicBlock::iterator End,
263 SDB->setCurrentBasicBlock(BB);
265 // Lower all of the non-terminator instructions. If a call is emitted
266 // as a tail call, cease emitting nodes for this block.
267 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
268 SetDebugLoc(I, SDB, 0, MF);
270 if (!isa<TerminatorInst>(I)) {
273 // Set the current debug location back to "unknown" so that it doesn't
274 // spuriously apply to subsequent instructions.
275 ResetDebugLoc(SDB, 0);
279 if (!SDB->HasTailCall) {
280 // Ensure that all instructions which are used outside of their defining
281 // blocks are available as virtual registers. Invoke is handled elsewhere.
282 for (BasicBlock::iterator I = Begin; I != End; ++I)
283 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
284 SDB->CopyToExportRegsIfNeeded(I);
286 // Handle PHI nodes in successor blocks.
287 if (End == LLVMBB->end()) {
288 HandlePHINodesInSuccessorBlocks(LLVMBB);
290 // Lower the terminator after the copies are emitted.
291 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF);
292 SDB->visit(*LLVMBB->getTerminator());
293 ResetDebugLoc(SDB, 0);
297 // Make sure the root of the DAG is up-to-date.
298 CurDAG->setRoot(SDB->getControlRoot());
300 // Final step, emit the lowered DAG as machine code.
302 HadTailCall = SDB->HasTailCall;
307 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
308 /// nodes from the worklist.
309 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
310 SmallVector<SDNode*, 128> &Worklist;
311 SmallPtrSet<SDNode*, 128> &InWorklist;
313 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
314 SmallPtrSet<SDNode*, 128> &inwl)
315 : Worklist(wl), InWorklist(inwl) {}
317 void RemoveFromWorklist(SDNode *N) {
318 if (!InWorklist.erase(N)) return;
320 SmallVector<SDNode*, 128>::iterator I =
321 std::find(Worklist.begin(), Worklist.end(), N);
322 assert(I != Worklist.end() && "Not in worklist");
324 *I = Worklist.back();
328 virtual void NodeDeleted(SDNode *N, SDNode *E) {
329 RemoveFromWorklist(N);
332 virtual void NodeUpdated(SDNode *N) {
338 /// TrivialTruncElim - Eliminate some trivial nops that can result from
339 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
340 static bool TrivialTruncElim(SDValue Op,
341 TargetLowering::TargetLoweringOpt &TLO) {
342 SDValue N0 = Op.getOperand(0);
343 EVT VT = Op.getValueType();
344 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
345 N0.getOpcode() == ISD::SIGN_EXTEND ||
346 N0.getOpcode() == ISD::ANY_EXTEND) &&
347 N0.getOperand(0).getValueType() == VT) {
348 return TLO.CombineTo(Op, N0.getOperand(0));
353 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
354 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
355 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
356 void SelectionDAGISel::ShrinkDemandedOps() {
357 SmallVector<SDNode*, 128> Worklist;
358 SmallPtrSet<SDNode*, 128> InWorklist;
360 // Add all the dag nodes to the worklist.
361 Worklist.reserve(CurDAG->allnodes_size());
362 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
363 E = CurDAG->allnodes_end(); I != E; ++I) {
364 Worklist.push_back(I);
365 InWorklist.insert(I);
368 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
369 while (!Worklist.empty()) {
370 SDNode *N = Worklist.pop_back_val();
373 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
374 // Deleting this node may make its operands dead, add them to the worklist
375 // if they aren't already there.
376 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
377 if (InWorklist.insert(N->getOperand(i).getNode()))
378 Worklist.push_back(N->getOperand(i).getNode());
380 CurDAG->DeleteNode(N);
384 // Run ShrinkDemandedOp on scalar binary operations.
385 if (N->getNumValues() != 1 ||
386 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
389 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
390 APInt Demanded = APInt::getAllOnesValue(BitWidth);
391 APInt KnownZero, KnownOne;
392 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
393 KnownZero, KnownOne, TLO) &&
394 (N->getOpcode() != ISD::TRUNCATE ||
395 !TrivialTruncElim(SDValue(N, 0), TLO)))
399 assert(!InWorklist.count(N) && "Already in worklist");
400 Worklist.push_back(N);
401 InWorklist.insert(N);
403 // Replace the old value with the new one.
404 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
405 TLO.Old.getNode()->dump(CurDAG);
406 errs() << "\nWith: ";
407 TLO.New.getNode()->dump(CurDAG);
410 if (InWorklist.insert(TLO.New.getNode()))
411 Worklist.push_back(TLO.New.getNode());
413 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
414 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
416 if (!TLO.Old.getNode()->use_empty()) continue;
418 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
420 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
421 if (OpNode->hasOneUse()) {
422 // Add OpNode to the end of the list to revisit.
423 DeadNodes.RemoveFromWorklist(OpNode);
424 Worklist.push_back(OpNode);
425 InWorklist.insert(OpNode);
429 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
430 CurDAG->DeleteNode(TLO.Old.getNode());
434 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
435 SmallPtrSet<SDNode*, 128> VisitedNodes;
436 SmallVector<SDNode*, 128> Worklist;
438 Worklist.push_back(CurDAG->getRoot().getNode());
445 SDNode *N = Worklist.pop_back_val();
447 // If we've already seen this node, ignore it.
448 if (!VisitedNodes.insert(N))
451 // Otherwise, add all chain operands to the worklist.
452 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
453 if (N->getOperand(i).getValueType() == MVT::Other)
454 Worklist.push_back(N->getOperand(i).getNode());
456 // If this is a CopyToReg with a vreg dest, process it.
457 if (N->getOpcode() != ISD::CopyToReg)
460 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
461 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
464 // Ignore non-scalar or non-integer values.
465 SDValue Src = N->getOperand(2);
466 EVT SrcVT = Src.getValueType();
467 if (!SrcVT.isInteger() || SrcVT.isVector())
470 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
471 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
472 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
474 // Only install this information if it tells us something.
475 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
476 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
477 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
478 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
479 FunctionLoweringInfo::LiveOutInfo &LOI =
480 FuncInfo->LiveOutRegInfo[DestReg];
481 LOI.NumSignBits = NumSignBits;
482 LOI.KnownOne = KnownOne;
483 LOI.KnownZero = KnownZero;
485 } while (!Worklist.empty());
488 void SelectionDAGISel::CodeGenAndEmitDAG() {
489 std::string GroupName;
490 if (TimePassesIsEnabled)
491 GroupName = "Instruction Selection and Scheduling";
492 std::string BlockName;
493 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
494 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
496 BlockName = MF->getFunction()->getNameStr() + ":" +
497 BB->getBasicBlock()->getNameStr();
499 DEBUG(dbgs() << "Initial selection DAG:\n");
500 DEBUG(CurDAG->dump());
502 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
504 // Run the DAG combiner in pre-legalize mode.
505 if (TimePassesIsEnabled) {
506 NamedRegionTimer T("DAG Combining 1", GroupName);
507 CurDAG->Combine(Unrestricted, *AA, OptLevel);
509 CurDAG->Combine(Unrestricted, *AA, OptLevel);
512 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
513 DEBUG(CurDAG->dump());
515 // Second step, hack on the DAG until it only uses operations and types that
516 // the target supports.
517 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
521 if (TimePassesIsEnabled) {
522 NamedRegionTimer T("Type Legalization", GroupName);
523 Changed = CurDAG->LegalizeTypes();
525 Changed = CurDAG->LegalizeTypes();
528 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
529 DEBUG(CurDAG->dump());
532 if (ViewDAGCombineLT)
533 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
535 // Run the DAG combiner in post-type-legalize mode.
536 if (TimePassesIsEnabled) {
537 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
538 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
540 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
543 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
544 DEBUG(CurDAG->dump());
547 if (TimePassesIsEnabled) {
548 NamedRegionTimer T("Vector Legalization", GroupName);
549 Changed = CurDAG->LegalizeVectors();
551 Changed = CurDAG->LegalizeVectors();
555 if (TimePassesIsEnabled) {
556 NamedRegionTimer T("Type Legalization 2", GroupName);
557 CurDAG->LegalizeTypes();
559 CurDAG->LegalizeTypes();
562 if (ViewDAGCombineLT)
563 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
565 // Run the DAG combiner in post-type-legalize mode.
566 if (TimePassesIsEnabled) {
567 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
568 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
570 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
573 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
574 DEBUG(CurDAG->dump());
577 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
579 if (TimePassesIsEnabled) {
580 NamedRegionTimer T("DAG Legalization", GroupName);
581 CurDAG->Legalize(OptLevel);
583 CurDAG->Legalize(OptLevel);
586 DEBUG(dbgs() << "Legalized selection DAG:\n");
587 DEBUG(CurDAG->dump());
589 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
591 // Run the DAG combiner in post-legalize mode.
592 if (TimePassesIsEnabled) {
593 NamedRegionTimer T("DAG Combining 2", GroupName);
594 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
596 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
599 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
600 DEBUG(CurDAG->dump());
602 if (OptLevel != CodeGenOpt::None) {
604 ComputeLiveOutVRegInfo();
607 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
609 // Third, instruction select all of the operations to machine code, adding the
610 // code to the MachineBasicBlock.
611 if (TimePassesIsEnabled) {
612 NamedRegionTimer T("Instruction Selection", GroupName);
613 DoInstructionSelection();
615 DoInstructionSelection();
618 DEBUG(dbgs() << "Selected selection DAG:\n");
619 DEBUG(CurDAG->dump());
621 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
623 // Schedule machine code.
624 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
625 if (TimePassesIsEnabled) {
626 NamedRegionTimer T("Instruction Scheduling", GroupName);
627 Scheduler->Run(CurDAG, BB, BB->end());
629 Scheduler->Run(CurDAG, BB, BB->end());
632 if (ViewSUnitDAGs) Scheduler->viewGraph();
634 // Emit machine code to BB. This can change 'BB' to the last block being
636 if (TimePassesIsEnabled) {
637 NamedRegionTimer T("Instruction Creation", GroupName);
638 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
640 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
643 // Free the scheduler state.
644 if (TimePassesIsEnabled) {
645 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
651 DEBUG(dbgs() << "Selected machine code:\n");
655 void SelectionDAGISel::DoInstructionSelection() {
656 DEBUG(errs() << "===== Instruction selection begins:\n");
660 // Select target instructions for the DAG.
662 // Number all nodes with a topological order and set DAGSize.
663 DAGSize = CurDAG->AssignTopologicalOrder();
665 // Create a dummy node (which is not added to allnodes), that adds
666 // a reference to the root node, preventing it from being deleted,
667 // and tracking any changes of the root.
668 HandleSDNode Dummy(CurDAG->getRoot());
669 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
672 // The AllNodes list is now topological-sorted. Visit the
673 // nodes by starting at the end of the list (the root of the
674 // graph) and preceding back toward the beginning (the entry
676 while (ISelPosition != CurDAG->allnodes_begin()) {
677 SDNode *Node = --ISelPosition;
678 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
679 // but there are currently some corner cases that it misses. Also, this
680 // makes it theoretically possible to disable the DAGCombiner.
681 if (Node->use_empty())
684 SDNode *ResNode = Select(Node);
686 // FIXME: This is pretty gross. 'Select' should be changed to not return
687 // anything at all and this code should be nuked with a tactical strike.
689 // If node should not be replaced, continue with the next one.
690 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
694 ReplaceUses(Node, ResNode);
696 // If after the replacement this node is not used any more,
697 // remove this dead node.
698 if (Node->use_empty()) { // Don't delete EntryToken, etc.
699 ISelUpdater ISU(ISelPosition);
700 CurDAG->RemoveDeadNode(Node, &ISU);
704 CurDAG->setRoot(Dummy.getValue());
706 DEBUG(errs() << "===== Instruction selection ends:\n");
708 PostprocessISelDAG();
712 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
714 const TargetInstrInfo &TII) {
715 // Initialize the Fast-ISel state, if needed.
716 FastISel *FastIS = 0;
718 FastIS = TLI.createFastISel(MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
719 FuncInfo->StaticAllocaMap
721 , FuncInfo->CatchInfoLost
725 // Iterate over all basic blocks in the function.
726 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
727 BasicBlock *LLVMBB = &*I;
728 BB = FuncInfo->MBBMap[LLVMBB];
730 BasicBlock::iterator const Begin = LLVMBB->begin();
731 BasicBlock::iterator const End = LLVMBB->end();
732 BasicBlock::iterator BI = Begin;
734 // Lower any arguments needed in this block if this is the entry block.
735 bool SuppressFastISel = false;
736 if (LLVMBB == &Fn.getEntryBlock()) {
737 LowerArguments(LLVMBB);
739 // If any of the arguments has the byval attribute, forgo
740 // fast-isel in the entry block.
743 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
745 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
746 if (EnableFastISelVerbose || EnableFastISelAbort)
747 dbgs() << "FastISel skips entry block due to byval argument\n";
748 SuppressFastISel = true;
754 if (BB->isLandingPad()) {
755 // Add a label to mark the beginning of the landing pad. Deletion of the
756 // landing pad can thus be detected via the MachineModuleInfo.
757 MCSymbol *Label = MF.getMMI().addLandingPad(BB);
759 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
760 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
762 // Mark exception register as live in.
763 unsigned Reg = TLI.getExceptionAddressRegister();
764 if (Reg) BB->addLiveIn(Reg);
766 // Mark exception selector register as live in.
767 Reg = TLI.getExceptionSelectorRegister();
768 if (Reg) BB->addLiveIn(Reg);
770 // FIXME: Hack around an exception handling flaw (PR1508): the personality
771 // function and list of typeids logically belong to the invoke (or, if you
772 // like, the basic block containing the invoke), and need to be associated
773 // with it in the dwarf exception handling tables. Currently however the
774 // information is provided by an intrinsic (eh.selector) that can be moved
775 // to unexpected places by the optimizers: if the unwind edge is critical,
776 // then breaking it can result in the intrinsics being in the successor of
777 // the landing pad, not the landing pad itself. This results
778 // in exceptions not being caught because no typeids are associated with
779 // the invoke. This may not be the only way things can go wrong, but it
780 // is the only way we try to work around for the moment.
781 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
783 if (Br && Br->isUnconditional()) { // Critical edge?
784 BasicBlock::iterator I, E;
785 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
786 if (isa<EHSelectorInst>(I))
790 // No catch info found - try to extract some from the successor.
791 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF.getMMI(), *FuncInfo);
795 // Before doing SelectionDAG ISel, see if FastISel has been requested.
796 if (FastIS && !SuppressFastISel) {
797 // Emit code for any incoming arguments. This must happen before
798 // beginning FastISel on the entry block.
799 if (LLVMBB == &Fn.getEntryBlock()) {
800 CurDAG->setRoot(SDB->getControlRoot());
804 FastIS->startNewBlock(BB);
805 // Do FastISel on as many instructions as possible.
806 for (; BI != End; ++BI) {
807 // Just before the terminator instruction, insert instructions to
808 // feed PHI nodes in successor blocks.
809 if (isa<TerminatorInst>(BI))
810 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
811 ++NumFastIselFailures;
812 ResetDebugLoc(SDB, FastIS);
813 if (EnableFastISelVerbose || EnableFastISelAbort) {
814 dbgs() << "FastISel miss: ";
817 assert(!EnableFastISelAbort &&
818 "FastISel didn't handle a PHI in a successor");
822 SetDebugLoc(BI, SDB, FastIS, &MF);
824 // Try to select the instruction with FastISel.
825 if (FastIS->SelectInstruction(BI)) {
826 ResetDebugLoc(SDB, FastIS);
830 // Clear out the debug location so that it doesn't carry over to
831 // unrelated instructions.
832 ResetDebugLoc(SDB, FastIS);
834 // Then handle certain instructions as single-LLVM-Instruction blocks.
835 if (isa<CallInst>(BI)) {
836 ++NumFastIselFailures;
837 if (EnableFastISelVerbose || EnableFastISelAbort) {
838 dbgs() << "FastISel missed call: ";
842 if (!BI->getType()->isVoidTy()) {
843 unsigned &R = FuncInfo->ValueMap[BI];
845 R = FuncInfo->CreateRegForValue(BI);
848 bool HadTailCall = false;
849 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
851 // If the call was emitted as a tail call, we're done with the block.
857 // If the instruction was codegen'd with multiple blocks,
858 // inform the FastISel object where to resume inserting.
859 FastIS->setCurrentBlock(BB);
863 // Otherwise, give up on FastISel for the rest of the block.
864 // For now, be a little lenient about non-branch terminators.
865 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
866 ++NumFastIselFailures;
867 if (EnableFastISelVerbose || EnableFastISelAbort) {
868 dbgs() << "FastISel miss: ";
871 if (EnableFastISelAbort)
872 // The "fast" selector couldn't handle something and bailed.
873 // For the purpose of debugging, just abort.
874 llvm_unreachable("FastISel didn't select the entire block");
880 // Run SelectionDAG instruction selection on the remainder of the block
881 // not handled by FastISel. If FastISel is not run, this is the entire
885 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
895 SelectionDAGISel::FinishBasicBlock() {
897 DEBUG(dbgs() << "Target-post-processed machine code:\n");
900 DEBUG(dbgs() << "Total amount of phi nodes to update: "
901 << SDB->PHINodesToUpdate.size() << "\n");
902 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
903 dbgs() << "Node " << i << " : ("
904 << SDB->PHINodesToUpdate[i].first
905 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
907 // Next, now that we know what the last MBB the LLVM BB expanded is, update
908 // PHI nodes in successors.
909 if (SDB->SwitchCases.empty() &&
910 SDB->JTCases.empty() &&
911 SDB->BitTestCases.empty()) {
912 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
913 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
914 assert(PHI->isPHI() &&
915 "This is not a machine PHI node that we are updating!");
916 if (!BB->isSuccessor(PHI->getParent()))
918 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
920 PHI->addOperand(MachineOperand::CreateMBB(BB));
922 SDB->PHINodesToUpdate.clear();
926 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
927 // Lower header first, if it wasn't already lowered
928 if (!SDB->BitTestCases[i].Emitted) {
929 // Set the current basic block to the mbb we wish to insert the code into
930 BB = SDB->BitTestCases[i].Parent;
931 SDB->setCurrentBasicBlock(BB);
933 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
934 CurDAG->setRoot(SDB->getRoot());
939 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
940 // Set the current basic block to the mbb we wish to insert the code into
941 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
942 SDB->setCurrentBasicBlock(BB);
945 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
946 SDB->BitTestCases[i].Reg,
947 SDB->BitTestCases[i].Cases[j]);
949 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
950 SDB->BitTestCases[i].Reg,
951 SDB->BitTestCases[i].Cases[j]);
954 CurDAG->setRoot(SDB->getRoot());
960 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
961 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
962 MachineBasicBlock *PHIBB = PHI->getParent();
963 assert(PHI->isPHI() &&
964 "This is not a machine PHI node that we are updating!");
965 // This is "default" BB. We have two jumps to it. From "header" BB and
966 // from last "case" BB.
967 if (PHIBB == SDB->BitTestCases[i].Default) {
968 PHI->addOperand(MachineOperand::
969 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
970 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
971 PHI->addOperand(MachineOperand::
972 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
973 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
976 // One of "cases" BB.
977 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
979 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
980 if (cBB->isSuccessor(PHIBB)) {
981 PHI->addOperand(MachineOperand::
982 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
983 PHI->addOperand(MachineOperand::CreateMBB(cBB));
988 SDB->BitTestCases.clear();
990 // If the JumpTable record is filled in, then we need to emit a jump table.
991 // Updating the PHI nodes is tricky in this case, since we need to determine
992 // whether the PHI is a successor of the range check MBB or the jump table MBB
993 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
994 // Lower header first, if it wasn't already lowered
995 if (!SDB->JTCases[i].first.Emitted) {
996 // Set the current basic block to the mbb we wish to insert the code into
997 BB = SDB->JTCases[i].first.HeaderBB;
998 SDB->setCurrentBasicBlock(BB);
1000 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
1001 CurDAG->setRoot(SDB->getRoot());
1002 CodeGenAndEmitDAG();
1006 // Set the current basic block to the mbb we wish to insert the code into
1007 BB = SDB->JTCases[i].second.MBB;
1008 SDB->setCurrentBasicBlock(BB);
1010 SDB->visitJumpTable(SDB->JTCases[i].second);
1011 CurDAG->setRoot(SDB->getRoot());
1012 CodeGenAndEmitDAG();
1016 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1017 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1018 MachineBasicBlock *PHIBB = PHI->getParent();
1019 assert(PHI->isPHI() &&
1020 "This is not a machine PHI node that we are updating!");
1021 // "default" BB. We can go there only from header BB.
1022 if (PHIBB == SDB->JTCases[i].second.Default) {
1024 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1026 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1028 // JT BB. Just iterate over successors here
1029 if (BB->isSuccessor(PHIBB)) {
1031 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1032 PHI->addOperand(MachineOperand::CreateMBB(BB));
1036 SDB->JTCases.clear();
1038 // If the switch block involved a branch to one of the actual successors, we
1039 // need to update PHI nodes in that block.
1040 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1041 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1042 assert(PHI->isPHI() &&
1043 "This is not a machine PHI node that we are updating!");
1044 if (BB->isSuccessor(PHI->getParent())) {
1045 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1047 PHI->addOperand(MachineOperand::CreateMBB(BB));
1051 // If we generated any switch lowering information, build and codegen any
1052 // additional DAGs necessary.
1053 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1054 // Set the current basic block to the mbb we wish to insert the code into
1055 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1056 SDB->setCurrentBasicBlock(BB);
1059 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1060 CurDAG->setRoot(SDB->getRoot());
1061 CodeGenAndEmitDAG();
1063 // Handle any PHI nodes in successors of this chunk, as if we were coming
1064 // from the original BB before switch expansion. Note that PHI nodes can
1065 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1066 // handle them the right number of times.
1067 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1068 // If new BB's are created during scheduling, the edges may have been
1069 // updated. That is, the edge from ThisBB to BB may have been split and
1070 // BB's predecessor is now another block.
1071 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1072 SDB->EdgeMapping.find(BB);
1073 if (EI != SDB->EdgeMapping.end())
1074 ThisBB = EI->second;
1076 // BB may have been removed from the CFG if a branch was constant folded.
1077 if (ThisBB->isSuccessor(BB)) {
1078 for (MachineBasicBlock::iterator Phi = BB->begin();
1079 Phi != BB->end() && Phi->isPHI();
1081 // This value for this PHI node is recorded in PHINodesToUpdate.
1082 for (unsigned pn = 0; ; ++pn) {
1083 assert(pn != SDB->PHINodesToUpdate.size() &&
1084 "Didn't find PHI entry!");
1085 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1086 Phi->addOperand(MachineOperand::
1087 CreateReg(SDB->PHINodesToUpdate[pn].second,
1089 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1096 // Don't process RHS if same block as LHS.
1097 if (BB == SDB->SwitchCases[i].FalseBB)
1098 SDB->SwitchCases[i].FalseBB = 0;
1100 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1101 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1102 SDB->SwitchCases[i].FalseBB = 0;
1104 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1107 SDB->SwitchCases.clear();
1109 SDB->PHINodesToUpdate.clear();
1113 /// Create the scheduler. If a specific scheduler was specified
1114 /// via the SchedulerRegistry, use it, otherwise select the
1115 /// one preferred by the target.
1117 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1118 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1122 RegisterScheduler::setDefault(Ctor);
1125 return Ctor(this, OptLevel);
1128 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1129 return new ScheduleHazardRecognizer();
1132 //===----------------------------------------------------------------------===//
1133 // Helper functions used by the generated instruction selector.
1134 //===----------------------------------------------------------------------===//
1135 // Calls to these methods are generated by tblgen.
1137 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1138 /// the dag combiner simplified the 255, we still want to match. RHS is the
1139 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1140 /// specified in the .td file (e.g. 255).
1141 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1142 int64_t DesiredMaskS) const {
1143 const APInt &ActualMask = RHS->getAPIntValue();
1144 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1146 // If the actual mask exactly matches, success!
1147 if (ActualMask == DesiredMask)
1150 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1151 if (ActualMask.intersects(~DesiredMask))
1154 // Otherwise, the DAG Combiner may have proven that the value coming in is
1155 // either already zero or is not demanded. Check for known zero input bits.
1156 APInt NeededMask = DesiredMask & ~ActualMask;
1157 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1160 // TODO: check to see if missing bits are just not demanded.
1162 // Otherwise, this pattern doesn't match.
1166 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1167 /// the dag combiner simplified the 255, we still want to match. RHS is the
1168 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1169 /// specified in the .td file (e.g. 255).
1170 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1171 int64_t DesiredMaskS) const {
1172 const APInt &ActualMask = RHS->getAPIntValue();
1173 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1175 // If the actual mask exactly matches, success!
1176 if (ActualMask == DesiredMask)
1179 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1180 if (ActualMask.intersects(~DesiredMask))
1183 // Otherwise, the DAG Combiner may have proven that the value coming in is
1184 // either already zero or is not demanded. Check for known zero input bits.
1185 APInt NeededMask = DesiredMask & ~ActualMask;
1187 APInt KnownZero, KnownOne;
1188 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1190 // If all the missing bits in the or are already known to be set, match!
1191 if ((NeededMask & KnownOne) == NeededMask)
1194 // TODO: check to see if missing bits are just not demanded.
1196 // Otherwise, this pattern doesn't match.
1201 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1202 /// by tblgen. Others should not call it.
1203 void SelectionDAGISel::
1204 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1205 std::vector<SDValue> InOps;
1206 std::swap(InOps, Ops);
1208 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1209 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1210 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1212 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1213 if (InOps[e-1].getValueType() == MVT::Flag)
1214 --e; // Don't process a flag operand if it is here.
1217 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1218 if (!InlineAsm::isMemKind(Flags)) {
1219 // Just skip over this operand, copying the operands verbatim.
1220 Ops.insert(Ops.end(), InOps.begin()+i,
1221 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1222 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1224 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1225 "Memory operand with multiple values?");
1226 // Otherwise, this is a memory operand. Ask the target to select it.
1227 std::vector<SDValue> SelOps;
1228 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1229 report_fatal_error("Could not match memory address. Inline asm"
1232 // Add this to the output node.
1234 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1235 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1236 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1241 // Add the flag input back if present.
1242 if (e != InOps.size())
1243 Ops.push_back(InOps.back());
1246 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1249 static SDNode *findFlagUse(SDNode *N) {
1250 unsigned FlagResNo = N->getNumValues()-1;
1251 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1252 SDUse &Use = I.getUse();
1253 if (Use.getResNo() == FlagResNo)
1254 return Use.getUser();
1259 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1260 /// This function recursively traverses up the operand chain, ignoring
1262 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1263 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1264 bool IgnoreChains) {
1265 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1266 // greater than all of its (recursive) operands. If we scan to a point where
1267 // 'use' is smaller than the node we're scanning for, then we know we will
1270 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1271 // happen because we scan down to newly selected nodes in the case of flag
1273 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1276 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1277 // won't fail if we scan it again.
1278 if (!Visited.insert(Use))
1281 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1282 // Ignore chain uses, they are validated by HandleMergeInputChains.
1283 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1286 SDNode *N = Use->getOperand(i).getNode();
1288 if (Use == ImmedUse || Use == Root)
1289 continue; // We are not looking for immediate use.
1294 // Traverse up the operand chain.
1295 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1301 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1302 /// operand node N of U during instruction selection that starts at Root.
1303 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1304 SDNode *Root) const {
1305 if (OptLevel == CodeGenOpt::None) return false;
1306 return N.hasOneUse();
1309 /// IsLegalToFold - Returns true if the specific operand node N of
1310 /// U can be folded during instruction selection that starts at Root.
1311 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1312 bool IgnoreChains) const {
1313 if (OptLevel == CodeGenOpt::None) return false;
1315 // If Root use can somehow reach N through a path that that doesn't contain
1316 // U then folding N would create a cycle. e.g. In the following
1317 // diagram, Root can reach N through X. If N is folded into into Root, then
1318 // X is both a predecessor and a successor of U.
1329 // * indicates nodes to be folded together.
1331 // If Root produces a flag, then it gets (even more) interesting. Since it
1332 // will be "glued" together with its flag use in the scheduler, we need to
1333 // check if it might reach N.
1352 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1353 // (call it Fold), then X is a predecessor of FU and a successor of
1354 // Fold. But since Fold and FU are flagged together, this will create
1355 // a cycle in the scheduling graph.
1357 // If the node has flags, walk down the graph to the "lowest" node in the
1359 EVT VT = Root->getValueType(Root->getNumValues()-1);
1360 while (VT == MVT::Flag) {
1361 SDNode *FU = findFlagUse(Root);
1365 VT = Root->getValueType(Root->getNumValues()-1);
1367 // If our query node has a flag result with a use, we've walked up it. If
1368 // the user (which has already been selected) has a chain or indirectly uses
1369 // the chain, our WalkChainUsers predicate will not consider it. Because of
1370 // this, we cannot ignore chains in this predicate.
1371 IgnoreChains = false;
1375 SmallPtrSet<SDNode*, 16> Visited;
1376 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1379 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1380 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1381 SelectInlineAsmMemoryOperands(Ops);
1383 std::vector<EVT> VTs;
1384 VTs.push_back(MVT::Other);
1385 VTs.push_back(MVT::Flag);
1386 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1387 VTs, &Ops[0], Ops.size());
1389 return New.getNode();
1392 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1393 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1396 /// GetVBR - decode a vbr encoding whose top bit is set.
1397 ALWAYS_INLINE static uint64_t
1398 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1399 assert(Val >= 128 && "Not a VBR");
1400 Val &= 127; // Remove first vbr bit.
1405 NextBits = MatcherTable[Idx++];
1406 Val |= (NextBits&127) << Shift;
1408 } while (NextBits & 128);
1414 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1415 /// interior flag and chain results to use the new flag and chain results.
1416 void SelectionDAGISel::
1417 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1418 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1420 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1421 bool isMorphNodeTo) {
1422 SmallVector<SDNode*, 4> NowDeadNodes;
1424 ISelUpdater ISU(ISelPosition);
1426 // Now that all the normal results are replaced, we replace the chain and
1427 // flag results if present.
1428 if (!ChainNodesMatched.empty()) {
1429 assert(InputChain.getNode() != 0 &&
1430 "Matched input chains but didn't produce a chain");
1431 // Loop over all of the nodes we matched that produced a chain result.
1432 // Replace all the chain results with the final chain we ended up with.
1433 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1434 SDNode *ChainNode = ChainNodesMatched[i];
1436 // If this node was already deleted, don't look at it.
1437 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1440 // Don't replace the results of the root node if we're doing a
1442 if (ChainNode == NodeToMatch && isMorphNodeTo)
1445 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1446 if (ChainVal.getValueType() == MVT::Flag)
1447 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1448 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1449 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1451 // If the node became dead and we haven't already seen it, delete it.
1452 if (ChainNode->use_empty() &&
1453 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1454 NowDeadNodes.push_back(ChainNode);
1458 // If the result produces a flag, update any flag results in the matched
1459 // pattern with the flag result.
1460 if (InputFlag.getNode() != 0) {
1461 // Handle any interior nodes explicitly marked.
1462 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1463 SDNode *FRN = FlagResultNodesMatched[i];
1465 // If this node was already deleted, don't look at it.
1466 if (FRN->getOpcode() == ISD::DELETED_NODE)
1469 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1470 "Doesn't have a flag result");
1471 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1474 // If the node became dead and we haven't already seen it, delete it.
1475 if (FRN->use_empty() &&
1476 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1477 NowDeadNodes.push_back(FRN);
1481 if (!NowDeadNodes.empty())
1482 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1484 DEBUG(errs() << "ISEL: Match complete!\n");
1490 CR_LeadsToInteriorNode
1493 /// WalkChainUsers - Walk down the users of the specified chained node that is
1494 /// part of the pattern we're matching, looking at all of the users we find.
1495 /// This determines whether something is an interior node, whether we have a
1496 /// non-pattern node in between two pattern nodes (which prevent folding because
1497 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1498 /// between pattern nodes (in which case the TF becomes part of the pattern).
1500 /// The walk we do here is guaranteed to be small because we quickly get down to
1501 /// already selected nodes "below" us.
1503 WalkChainUsers(SDNode *ChainedNode,
1504 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1505 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1506 ChainResult Result = CR_Simple;
1508 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1509 E = ChainedNode->use_end(); UI != E; ++UI) {
1510 // Make sure the use is of the chain, not some other value we produce.
1511 if (UI.getUse().getValueType() != MVT::Other) continue;
1515 // If we see an already-selected machine node, then we've gone beyond the
1516 // pattern that we're selecting down into the already selected chunk of the
1518 if (User->isMachineOpcode() ||
1519 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1522 if (User->getOpcode() == ISD::CopyToReg ||
1523 User->getOpcode() == ISD::CopyFromReg ||
1524 User->getOpcode() == ISD::INLINEASM ||
1525 User->getOpcode() == ISD::EH_LABEL) {
1526 // If their node ID got reset to -1 then they've already been selected.
1527 // Treat them like a MachineOpcode.
1528 if (User->getNodeId() == -1)
1532 // If we have a TokenFactor, we handle it specially.
1533 if (User->getOpcode() != ISD::TokenFactor) {
1534 // If the node isn't a token factor and isn't part of our pattern, then it
1535 // must be a random chained node in between two nodes we're selecting.
1536 // This happens when we have something like:
1541 // Because we structurally match the load/store as a read/modify/write,
1542 // but the call is chained between them. We cannot fold in this case
1543 // because it would induce a cycle in the graph.
1544 if (!std::count(ChainedNodesInPattern.begin(),
1545 ChainedNodesInPattern.end(), User))
1546 return CR_InducesCycle;
1548 // Otherwise we found a node that is part of our pattern. For example in:
1552 // This would happen when we're scanning down from the load and see the
1553 // store as a user. Record that there is a use of ChainedNode that is
1554 // part of the pattern and keep scanning uses.
1555 Result = CR_LeadsToInteriorNode;
1556 InteriorChainedNodes.push_back(User);
1560 // If we found a TokenFactor, there are two cases to consider: first if the
1561 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1562 // uses of the TF are in our pattern) we just want to ignore it. Second,
1563 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1569 // | \ DAG's like cheese
1572 // [TokenFactor] [Op]
1579 // In this case, the TokenFactor becomes part of our match and we rewrite it
1580 // as a new TokenFactor.
1582 // To distinguish these two cases, do a recursive walk down the uses.
1583 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1585 // If the uses of the TokenFactor are just already-selected nodes, ignore
1586 // it, it is "below" our pattern.
1588 case CR_InducesCycle:
1589 // If the uses of the TokenFactor lead to nodes that are not part of our
1590 // pattern that are not selected, folding would turn this into a cycle,
1592 return CR_InducesCycle;
1593 case CR_LeadsToInteriorNode:
1594 break; // Otherwise, keep processing.
1597 // Okay, we know we're in the interesting interior case. The TokenFactor
1598 // is now going to be considered part of the pattern so that we rewrite its
1599 // uses (it may have uses that are not part of the pattern) with the
1600 // ultimate chain result of the generated code. We will also add its chain
1601 // inputs as inputs to the ultimate TokenFactor we create.
1602 Result = CR_LeadsToInteriorNode;
1603 ChainedNodesInPattern.push_back(User);
1604 InteriorChainedNodes.push_back(User);
1611 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1612 /// operation for when the pattern matched at least one node with a chains. The
1613 /// input vector contains a list of all of the chained nodes that we match. We
1614 /// must determine if this is a valid thing to cover (i.e. matching it won't
1615 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1616 /// be used as the input node chain for the generated nodes.
1618 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1619 SelectionDAG *CurDAG) {
1620 // Walk all of the chained nodes we've matched, recursively scanning down the
1621 // users of the chain result. This adds any TokenFactor nodes that are caught
1622 // in between chained nodes to the chained and interior nodes list.
1623 SmallVector<SDNode*, 3> InteriorChainedNodes;
1624 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1625 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1626 InteriorChainedNodes) == CR_InducesCycle)
1627 return SDValue(); // Would induce a cycle.
1630 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1631 // that we are interested in. Form our input TokenFactor node.
1632 SmallVector<SDValue, 3> InputChains;
1633 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1634 // Add the input chain of this node to the InputChains list (which will be
1635 // the operands of the generated TokenFactor) if it's not an interior node.
1636 SDNode *N = ChainNodesMatched[i];
1637 if (N->getOpcode() != ISD::TokenFactor) {
1638 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1641 // Otherwise, add the input chain.
1642 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1643 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1644 InputChains.push_back(InChain);
1648 // If we have a token factor, we want to add all inputs of the token factor
1649 // that are not part of the pattern we're matching.
1650 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1651 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1652 N->getOperand(op).getNode()))
1653 InputChains.push_back(N->getOperand(op));
1658 if (InputChains.size() == 1)
1659 return InputChains[0];
1660 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1661 MVT::Other, &InputChains[0], InputChains.size());
1664 /// MorphNode - Handle morphing a node in place for the selector.
1665 SDNode *SelectionDAGISel::
1666 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1667 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1668 // It is possible we're using MorphNodeTo to replace a node with no
1669 // normal results with one that has a normal result (or we could be
1670 // adding a chain) and the input could have flags and chains as well.
1671 // In this case we need to shift the operands down.
1672 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1673 // than the old isel though.
1674 int OldFlagResultNo = -1, OldChainResultNo = -1;
1676 unsigned NTMNumResults = Node->getNumValues();
1677 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1678 OldFlagResultNo = NTMNumResults-1;
1679 if (NTMNumResults != 1 &&
1680 Node->getValueType(NTMNumResults-2) == MVT::Other)
1681 OldChainResultNo = NTMNumResults-2;
1682 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1683 OldChainResultNo = NTMNumResults-1;
1685 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1686 // that this deletes operands of the old node that become dead.
1687 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1689 // MorphNodeTo can operate in two ways: if an existing node with the
1690 // specified operands exists, it can just return it. Otherwise, it
1691 // updates the node in place to have the requested operands.
1693 // If we updated the node in place, reset the node ID. To the isel,
1694 // this should be just like a newly allocated machine node.
1698 unsigned ResNumResults = Res->getNumValues();
1699 // Move the flag if needed.
1700 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1701 (unsigned)OldFlagResultNo != ResNumResults-1)
1702 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1703 SDValue(Res, ResNumResults-1));
1705 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1708 // Move the chain reference if needed.
1709 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1710 (unsigned)OldChainResultNo != ResNumResults-1)
1711 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1712 SDValue(Res, ResNumResults-1));
1714 // Otherwise, no replacement happened because the node already exists. Replace
1715 // Uses of the old node with the new one.
1717 CurDAG->ReplaceAllUsesWith(Node, Res);
1722 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1723 ALWAYS_INLINE static bool
1724 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1725 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1726 // Accept if it is exactly the same as a previously recorded node.
1727 unsigned RecNo = MatcherTable[MatcherIndex++];
1728 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1729 return N == RecordedNodes[RecNo];
1732 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1733 ALWAYS_INLINE static bool
1734 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1735 SelectionDAGISel &SDISel) {
1736 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1739 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1740 ALWAYS_INLINE static bool
1741 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1742 SelectionDAGISel &SDISel, SDNode *N) {
1743 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1746 ALWAYS_INLINE static bool
1747 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1749 uint16_t Opc = MatcherTable[MatcherIndex++];
1750 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1751 return N->getOpcode() == Opc;
1754 ALWAYS_INLINE static bool
1755 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1756 SDValue N, const TargetLowering &TLI) {
1757 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1758 if (N.getValueType() == VT) return true;
1760 // Handle the case when VT is iPTR.
1761 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1764 ALWAYS_INLINE static bool
1765 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1766 SDValue N, const TargetLowering &TLI,
1768 if (ChildNo >= N.getNumOperands())
1769 return false; // Match fails if out of range child #.
1770 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1774 ALWAYS_INLINE static bool
1775 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1777 return cast<CondCodeSDNode>(N)->get() ==
1778 (ISD::CondCode)MatcherTable[MatcherIndex++];
1781 ALWAYS_INLINE static bool
1782 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1783 SDValue N, const TargetLowering &TLI) {
1784 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1785 if (cast<VTSDNode>(N)->getVT() == VT)
1788 // Handle the case when VT is iPTR.
1789 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1792 ALWAYS_INLINE static bool
1793 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1795 int64_t Val = MatcherTable[MatcherIndex++];
1797 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1799 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1800 return C != 0 && C->getSExtValue() == Val;
1803 ALWAYS_INLINE static bool
1804 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1805 SDValue N, SelectionDAGISel &SDISel) {
1806 int64_t Val = MatcherTable[MatcherIndex++];
1808 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1810 if (N->getOpcode() != ISD::AND) return false;
1812 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1813 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1816 ALWAYS_INLINE static bool
1817 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1818 SDValue N, SelectionDAGISel &SDISel) {
1819 int64_t Val = MatcherTable[MatcherIndex++];
1821 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1823 if (N->getOpcode() != ISD::OR) return false;
1825 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1826 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1829 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1830 /// scope, evaluate the current node. If the current predicate is known to
1831 /// fail, set Result=true and return anything. If the current predicate is
1832 /// known to pass, set Result=false and return the MatcherIndex to continue
1833 /// with. If the current predicate is unknown, set Result=false and return the
1834 /// MatcherIndex to continue with.
1835 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1836 unsigned Index, SDValue N,
1837 bool &Result, SelectionDAGISel &SDISel,
1838 SmallVectorImpl<SDValue> &RecordedNodes){
1839 switch (Table[Index++]) {
1842 return Index-1; // Could not evaluate this predicate.
1843 case SelectionDAGISel::OPC_CheckSame:
1844 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1846 case SelectionDAGISel::OPC_CheckPatternPredicate:
1847 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1849 case SelectionDAGISel::OPC_CheckPredicate:
1850 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1852 case SelectionDAGISel::OPC_CheckOpcode:
1853 Result = !::CheckOpcode(Table, Index, N.getNode());
1855 case SelectionDAGISel::OPC_CheckType:
1856 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1858 case SelectionDAGISel::OPC_CheckChild0Type:
1859 case SelectionDAGISel::OPC_CheckChild1Type:
1860 case SelectionDAGISel::OPC_CheckChild2Type:
1861 case SelectionDAGISel::OPC_CheckChild3Type:
1862 case SelectionDAGISel::OPC_CheckChild4Type:
1863 case SelectionDAGISel::OPC_CheckChild5Type:
1864 case SelectionDAGISel::OPC_CheckChild6Type:
1865 case SelectionDAGISel::OPC_CheckChild7Type:
1866 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1867 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1869 case SelectionDAGISel::OPC_CheckCondCode:
1870 Result = !::CheckCondCode(Table, Index, N);
1872 case SelectionDAGISel::OPC_CheckValueType:
1873 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1875 case SelectionDAGISel::OPC_CheckInteger:
1876 Result = !::CheckInteger(Table, Index, N);
1878 case SelectionDAGISel::OPC_CheckAndImm:
1879 Result = !::CheckAndImm(Table, Index, N, SDISel);
1881 case SelectionDAGISel::OPC_CheckOrImm:
1882 Result = !::CheckOrImm(Table, Index, N, SDISel);
1889 /// FailIndex - If this match fails, this is the index to continue with.
1892 /// NodeStack - The node stack when the scope was formed.
1893 SmallVector<SDValue, 4> NodeStack;
1895 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1896 unsigned NumRecordedNodes;
1898 /// NumMatchedMemRefs - The number of matched memref entries.
1899 unsigned NumMatchedMemRefs;
1901 /// InputChain/InputFlag - The current chain/flag
1902 SDValue InputChain, InputFlag;
1904 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1905 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1908 SDNode *SelectionDAGISel::
1909 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1910 unsigned TableSize) {
1911 // FIXME: Should these even be selected? Handle these cases in the caller?
1912 switch (NodeToMatch->getOpcode()) {
1915 case ISD::EntryToken: // These nodes remain the same.
1916 case ISD::BasicBlock:
1918 //case ISD::VALUETYPE:
1919 //case ISD::CONDCODE:
1920 case ISD::HANDLENODE:
1921 case ISD::MDNODE_SDNODE:
1922 case ISD::TargetConstant:
1923 case ISD::TargetConstantFP:
1924 case ISD::TargetConstantPool:
1925 case ISD::TargetFrameIndex:
1926 case ISD::TargetExternalSymbol:
1927 case ISD::TargetBlockAddress:
1928 case ISD::TargetJumpTable:
1929 case ISD::TargetGlobalTLSAddress:
1930 case ISD::TargetGlobalAddress:
1931 case ISD::TokenFactor:
1932 case ISD::CopyFromReg:
1933 case ISD::CopyToReg:
1935 NodeToMatch->setNodeId(-1); // Mark selected.
1937 case ISD::AssertSext:
1938 case ISD::AssertZext:
1939 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1940 NodeToMatch->getOperand(0));
1942 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1943 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1946 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1948 // Set up the node stack with NodeToMatch as the only node on the stack.
1949 SmallVector<SDValue, 8> NodeStack;
1950 SDValue N = SDValue(NodeToMatch, 0);
1951 NodeStack.push_back(N);
1953 // MatchScopes - Scopes used when matching, if a match failure happens, this
1954 // indicates where to continue checking.
1955 SmallVector<MatchScope, 8> MatchScopes;
1957 // RecordedNodes - This is the set of nodes that have been recorded by the
1959 SmallVector<SDValue, 8> RecordedNodes;
1961 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1963 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1965 // These are the current input chain and flag for use when generating nodes.
1966 // Various Emit operations change these. For example, emitting a copytoreg
1967 // uses and updates these.
1968 SDValue InputChain, InputFlag;
1970 // ChainNodesMatched - If a pattern matches nodes that have input/output
1971 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1972 // which ones they are. The result is captured into this list so that we can
1973 // update the chain results when the pattern is complete.
1974 SmallVector<SDNode*, 3> ChainNodesMatched;
1975 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1977 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1978 NodeToMatch->dump(CurDAG);
1981 // Determine where to start the interpreter. Normally we start at opcode #0,
1982 // but if the state machine starts with an OPC_SwitchOpcode, then we
1983 // accelerate the first lookup (which is guaranteed to be hot) with the
1984 // OpcodeOffset table.
1985 unsigned MatcherIndex = 0;
1987 if (!OpcodeOffset.empty()) {
1988 // Already computed the OpcodeOffset table, just index into it.
1989 if (N.getOpcode() < OpcodeOffset.size())
1990 MatcherIndex = OpcodeOffset[N.getOpcode()];
1991 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1993 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1994 // Otherwise, the table isn't computed, but the state machine does start
1995 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1996 // is the first time we're selecting an instruction.
1999 // Get the size of this case.
2000 unsigned CaseSize = MatcherTable[Idx++];
2002 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2003 if (CaseSize == 0) break;
2005 // Get the opcode, add the index to the table.
2006 uint16_t Opc = MatcherTable[Idx++];
2007 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2008 if (Opc >= OpcodeOffset.size())
2009 OpcodeOffset.resize((Opc+1)*2);
2010 OpcodeOffset[Opc] = Idx;
2014 // Okay, do the lookup for the first opcode.
2015 if (N.getOpcode() < OpcodeOffset.size())
2016 MatcherIndex = OpcodeOffset[N.getOpcode()];
2020 assert(MatcherIndex < TableSize && "Invalid index");
2022 unsigned CurrentOpcodeIndex = MatcherIndex;
2024 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2027 // Okay, the semantics of this operation are that we should push a scope
2028 // then evaluate the first child. However, pushing a scope only to have
2029 // the first check fail (which then pops it) is inefficient. If we can
2030 // determine immediately that the first check (or first several) will
2031 // immediately fail, don't even bother pushing a scope for them.
2035 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2036 if (NumToSkip & 128)
2037 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2038 // Found the end of the scope with no match.
2039 if (NumToSkip == 0) {
2044 FailIndex = MatcherIndex+NumToSkip;
2046 unsigned MatcherIndexOfPredicate = MatcherIndex;
2047 (void)MatcherIndexOfPredicate; // silence warning.
2049 // If we can't evaluate this predicate without pushing a scope (e.g. if
2050 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2051 // push the scope and evaluate the full predicate chain.
2053 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2054 Result, *this, RecordedNodes);
2058 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2059 << "index " << MatcherIndexOfPredicate
2060 << ", continuing at " << FailIndex << "\n");
2061 ++NumDAGIselRetries;
2063 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2064 // move to the next case.
2065 MatcherIndex = FailIndex;
2068 // If the whole scope failed to match, bail.
2069 if (FailIndex == 0) break;
2071 // Push a MatchScope which indicates where to go if the first child fails
2073 MatchScope NewEntry;
2074 NewEntry.FailIndex = FailIndex;
2075 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2076 NewEntry.NumRecordedNodes = RecordedNodes.size();
2077 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2078 NewEntry.InputChain = InputChain;
2079 NewEntry.InputFlag = InputFlag;
2080 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2081 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2082 MatchScopes.push_back(NewEntry);
2085 case OPC_RecordNode:
2086 // Remember this node, it may end up being an operand in the pattern.
2087 RecordedNodes.push_back(N);
2090 case OPC_RecordChild0: case OPC_RecordChild1:
2091 case OPC_RecordChild2: case OPC_RecordChild3:
2092 case OPC_RecordChild4: case OPC_RecordChild5:
2093 case OPC_RecordChild6: case OPC_RecordChild7: {
2094 unsigned ChildNo = Opcode-OPC_RecordChild0;
2095 if (ChildNo >= N.getNumOperands())
2096 break; // Match fails if out of range child #.
2098 RecordedNodes.push_back(N->getOperand(ChildNo));
2101 case OPC_RecordMemRef:
2102 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2105 case OPC_CaptureFlagInput:
2106 // If the current node has an input flag, capture it in InputFlag.
2107 if (N->getNumOperands() != 0 &&
2108 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2109 InputFlag = N->getOperand(N->getNumOperands()-1);
2112 case OPC_MoveChild: {
2113 unsigned ChildNo = MatcherTable[MatcherIndex++];
2114 if (ChildNo >= N.getNumOperands())
2115 break; // Match fails if out of range child #.
2116 N = N.getOperand(ChildNo);
2117 NodeStack.push_back(N);
2121 case OPC_MoveParent:
2122 // Pop the current node off the NodeStack.
2123 NodeStack.pop_back();
2124 assert(!NodeStack.empty() && "Node stack imbalance!");
2125 N = NodeStack.back();
2129 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2131 case OPC_CheckPatternPredicate:
2132 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2134 case OPC_CheckPredicate:
2135 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2139 case OPC_CheckComplexPat: {
2140 unsigned CPNum = MatcherTable[MatcherIndex++];
2141 unsigned RecNo = MatcherTable[MatcherIndex++];
2142 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2143 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2148 case OPC_CheckOpcode:
2149 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2153 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2156 case OPC_SwitchOpcode: {
2157 unsigned CurNodeOpcode = N.getOpcode();
2158 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2161 // Get the size of this case.
2162 CaseSize = MatcherTable[MatcherIndex++];
2164 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2165 if (CaseSize == 0) break;
2167 uint16_t Opc = MatcherTable[MatcherIndex++];
2168 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2170 // If the opcode matches, then we will execute this case.
2171 if (CurNodeOpcode == Opc)
2174 // Otherwise, skip over this case.
2175 MatcherIndex += CaseSize;
2178 // If no cases matched, bail out.
2179 if (CaseSize == 0) break;
2181 // Otherwise, execute the case we found.
2182 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2183 << " to " << MatcherIndex << "\n");
2187 case OPC_SwitchType: {
2188 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2189 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2192 // Get the size of this case.
2193 CaseSize = MatcherTable[MatcherIndex++];
2195 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2196 if (CaseSize == 0) break;
2198 MVT::SimpleValueType CaseVT =
2199 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2200 if (CaseVT == MVT::iPTR)
2201 CaseVT = TLI.getPointerTy().SimpleTy;
2203 // If the VT matches, then we will execute this case.
2204 if (CurNodeVT == CaseVT)
2207 // Otherwise, skip over this case.
2208 MatcherIndex += CaseSize;
2211 // If no cases matched, bail out.
2212 if (CaseSize == 0) break;
2214 // Otherwise, execute the case we found.
2215 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2216 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2219 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2220 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2221 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2222 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2223 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2224 Opcode-OPC_CheckChild0Type))
2227 case OPC_CheckCondCode:
2228 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2230 case OPC_CheckValueType:
2231 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2233 case OPC_CheckInteger:
2234 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2236 case OPC_CheckAndImm:
2237 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2239 case OPC_CheckOrImm:
2240 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2243 case OPC_CheckFoldableChainNode: {
2244 assert(NodeStack.size() != 1 && "No parent node");
2245 // Verify that all intermediate nodes between the root and this one have
2247 bool HasMultipleUses = false;
2248 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2249 if (!NodeStack[i].hasOneUse()) {
2250 HasMultipleUses = true;
2253 if (HasMultipleUses) break;
2255 // Check to see that the target thinks this is profitable to fold and that
2256 // we can fold it without inducing cycles in the graph.
2257 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2259 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2260 NodeToMatch, true/*We validate our own chains*/))
2265 case OPC_EmitInteger: {
2266 MVT::SimpleValueType VT =
2267 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2268 int64_t Val = MatcherTable[MatcherIndex++];
2270 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2271 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2274 case OPC_EmitRegister: {
2275 MVT::SimpleValueType VT =
2276 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2277 unsigned RegNo = MatcherTable[MatcherIndex++];
2278 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2282 case OPC_EmitConvertToTarget: {
2283 // Convert from IMM/FPIMM to target version.
2284 unsigned RecNo = MatcherTable[MatcherIndex++];
2285 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2286 SDValue Imm = RecordedNodes[RecNo];
2288 if (Imm->getOpcode() == ISD::Constant) {
2289 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2290 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2291 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2292 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2293 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2296 RecordedNodes.push_back(Imm);
2300 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2301 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2302 // These are space-optimized forms of OPC_EmitMergeInputChains.
2303 assert(InputChain.getNode() == 0 &&
2304 "EmitMergeInputChains should be the first chain producing node");
2305 assert(ChainNodesMatched.empty() &&
2306 "Should only have one EmitMergeInputChains per match");
2308 // Read all of the chained nodes.
2309 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2310 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2311 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2313 // FIXME: What if other value results of the node have uses not matched
2315 if (ChainNodesMatched.back() != NodeToMatch &&
2316 !RecordedNodes[RecNo].hasOneUse()) {
2317 ChainNodesMatched.clear();
2321 // Merge the input chains if they are not intra-pattern references.
2322 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2324 if (InputChain.getNode() == 0)
2325 break; // Failed to merge.
2329 case OPC_EmitMergeInputChains: {
2330 assert(InputChain.getNode() == 0 &&
2331 "EmitMergeInputChains should be the first chain producing node");
2332 // This node gets a list of nodes we matched in the input that have
2333 // chains. We want to token factor all of the input chains to these nodes
2334 // together. However, if any of the input chains is actually one of the
2335 // nodes matched in this pattern, then we have an intra-match reference.
2336 // Ignore these because the newly token factored chain should not refer to
2338 unsigned NumChains = MatcherTable[MatcherIndex++];
2339 assert(NumChains != 0 && "Can't TF zero chains");
2341 assert(ChainNodesMatched.empty() &&
2342 "Should only have one EmitMergeInputChains per match");
2344 // Read all of the chained nodes.
2345 for (unsigned i = 0; i != NumChains; ++i) {
2346 unsigned RecNo = MatcherTable[MatcherIndex++];
2347 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2348 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2350 // FIXME: What if other value results of the node have uses not matched
2352 if (ChainNodesMatched.back() != NodeToMatch &&
2353 !RecordedNodes[RecNo].hasOneUse()) {
2354 ChainNodesMatched.clear();
2359 // If the inner loop broke out, the match fails.
2360 if (ChainNodesMatched.empty())
2363 // Merge the input chains if they are not intra-pattern references.
2364 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2366 if (InputChain.getNode() == 0)
2367 break; // Failed to merge.
2372 case OPC_EmitCopyToReg: {
2373 unsigned RecNo = MatcherTable[MatcherIndex++];
2374 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2375 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2377 if (InputChain.getNode() == 0)
2378 InputChain = CurDAG->getEntryNode();
2380 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2381 DestPhysReg, RecordedNodes[RecNo],
2384 InputFlag = InputChain.getValue(1);
2388 case OPC_EmitNodeXForm: {
2389 unsigned XFormNo = MatcherTable[MatcherIndex++];
2390 unsigned RecNo = MatcherTable[MatcherIndex++];
2391 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2392 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2397 case OPC_MorphNodeTo: {
2398 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2399 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2400 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2401 // Get the result VT list.
2402 unsigned NumVTs = MatcherTable[MatcherIndex++];
2403 SmallVector<EVT, 4> VTs;
2404 for (unsigned i = 0; i != NumVTs; ++i) {
2405 MVT::SimpleValueType VT =
2406 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2407 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2411 if (EmitNodeInfo & OPFL_Chain)
2412 VTs.push_back(MVT::Other);
2413 if (EmitNodeInfo & OPFL_FlagOutput)
2414 VTs.push_back(MVT::Flag);
2416 // This is hot code, so optimize the two most common cases of 1 and 2
2419 if (VTs.size() == 1)
2420 VTList = CurDAG->getVTList(VTs[0]);
2421 else if (VTs.size() == 2)
2422 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2424 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2426 // Get the operand list.
2427 unsigned NumOps = MatcherTable[MatcherIndex++];
2428 SmallVector<SDValue, 8> Ops;
2429 for (unsigned i = 0; i != NumOps; ++i) {
2430 unsigned RecNo = MatcherTable[MatcherIndex++];
2432 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2434 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2435 Ops.push_back(RecordedNodes[RecNo]);
2438 // If there are variadic operands to add, handle them now.
2439 if (EmitNodeInfo & OPFL_VariadicInfo) {
2440 // Determine the start index to copy from.
2441 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2442 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2443 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2444 "Invalid variadic node");
2445 // Copy all of the variadic operands, not including a potential flag
2447 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2449 SDValue V = NodeToMatch->getOperand(i);
2450 if (V.getValueType() == MVT::Flag) break;
2455 // If this has chain/flag inputs, add them.
2456 if (EmitNodeInfo & OPFL_Chain)
2457 Ops.push_back(InputChain);
2458 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2459 Ops.push_back(InputFlag);
2463 if (Opcode != OPC_MorphNodeTo) {
2464 // If this is a normal EmitNode command, just create the new node and
2465 // add the results to the RecordedNodes list.
2466 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2467 VTList, Ops.data(), Ops.size());
2469 // Add all the non-flag/non-chain results to the RecordedNodes list.
2470 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2471 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2472 RecordedNodes.push_back(SDValue(Res, i));
2476 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2480 // If the node had chain/flag results, update our notion of the current
2482 if (EmitNodeInfo & OPFL_FlagOutput) {
2483 InputFlag = SDValue(Res, VTs.size()-1);
2484 if (EmitNodeInfo & OPFL_Chain)
2485 InputChain = SDValue(Res, VTs.size()-2);
2486 } else if (EmitNodeInfo & OPFL_Chain)
2487 InputChain = SDValue(Res, VTs.size()-1);
2489 // If the OPFL_MemRefs flag is set on this node, slap all of the
2490 // accumulated memrefs onto it.
2492 // FIXME: This is vastly incorrect for patterns with multiple outputs
2493 // instructions that access memory and for ComplexPatterns that match
2495 if (EmitNodeInfo & OPFL_MemRefs) {
2496 MachineSDNode::mmo_iterator MemRefs =
2497 MF->allocateMemRefsArray(MatchedMemRefs.size());
2498 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2499 cast<MachineSDNode>(Res)
2500 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2504 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2505 << " node: "; Res->dump(CurDAG); errs() << "\n");
2507 // If this was a MorphNodeTo then we're completely done!
2508 if (Opcode == OPC_MorphNodeTo) {
2509 // Update chain and flag uses.
2510 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2511 InputFlag, FlagResultNodesMatched, true);
2518 case OPC_MarkFlagResults: {
2519 unsigned NumNodes = MatcherTable[MatcherIndex++];
2521 // Read and remember all the flag-result nodes.
2522 for (unsigned i = 0; i != NumNodes; ++i) {
2523 unsigned RecNo = MatcherTable[MatcherIndex++];
2525 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2527 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2528 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2533 case OPC_CompleteMatch: {
2534 // The match has been completed, and any new nodes (if any) have been
2535 // created. Patch up references to the matched dag to use the newly
2537 unsigned NumResults = MatcherTable[MatcherIndex++];
2539 for (unsigned i = 0; i != NumResults; ++i) {
2540 unsigned ResSlot = MatcherTable[MatcherIndex++];
2542 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2544 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2545 SDValue Res = RecordedNodes[ResSlot];
2547 assert(i < NodeToMatch->getNumValues() &&
2548 NodeToMatch->getValueType(i) != MVT::Other &&
2549 NodeToMatch->getValueType(i) != MVT::Flag &&
2550 "Invalid number of results to complete!");
2551 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2552 NodeToMatch->getValueType(i) == MVT::iPTR ||
2553 Res.getValueType() == MVT::iPTR ||
2554 NodeToMatch->getValueType(i).getSizeInBits() ==
2555 Res.getValueType().getSizeInBits()) &&
2556 "invalid replacement");
2557 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2560 // If the root node defines a flag, add it to the flag nodes to update
2562 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2563 FlagResultNodesMatched.push_back(NodeToMatch);
2565 // Update chain and flag uses.
2566 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2567 InputFlag, FlagResultNodesMatched, false);
2569 assert(NodeToMatch->use_empty() &&
2570 "Didn't replace all uses of the node?");
2572 // FIXME: We just return here, which interacts correctly with SelectRoot
2573 // above. We should fix this to not return an SDNode* anymore.
2578 // If the code reached this point, then the match failed. See if there is
2579 // another child to try in the current 'Scope', otherwise pop it until we
2580 // find a case to check.
2581 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2582 ++NumDAGIselRetries;
2584 if (MatchScopes.empty()) {
2585 CannotYetSelect(NodeToMatch);
2589 // Restore the interpreter state back to the point where the scope was
2591 MatchScope &LastScope = MatchScopes.back();
2592 RecordedNodes.resize(LastScope.NumRecordedNodes);
2594 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2595 N = NodeStack.back();
2597 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2598 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2599 MatcherIndex = LastScope.FailIndex;
2601 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2603 InputChain = LastScope.InputChain;
2604 InputFlag = LastScope.InputFlag;
2605 if (!LastScope.HasChainNodesMatched)
2606 ChainNodesMatched.clear();
2607 if (!LastScope.HasFlagResultNodesMatched)
2608 FlagResultNodesMatched.clear();
2610 // Check to see what the offset is at the new MatcherIndex. If it is zero
2611 // we have reached the end of this scope, otherwise we have another child
2612 // in the current scope to try.
2613 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2614 if (NumToSkip & 128)
2615 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2617 // If we have another child in this scope to match, update FailIndex and
2619 if (NumToSkip != 0) {
2620 LastScope.FailIndex = MatcherIndex+NumToSkip;
2624 // End of this scope, pop it and try the next child in the containing
2626 MatchScopes.pop_back();
2633 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2635 raw_string_ostream Msg(msg);
2636 Msg << "Cannot yet select: ";
2638 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2639 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2640 N->getOpcode() != ISD::INTRINSIC_VOID) {
2641 N->printrFull(Msg, CurDAG);
2643 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2645 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2646 if (iid < Intrinsic::num_intrinsics)
2647 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2648 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2649 Msg << "target intrinsic %" << TII->getName(iid);
2651 Msg << "unknown intrinsic #" << iid;
2653 report_fatal_error(Msg.str());
2656 char SelectionDAGISel::ID = 0;