1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/GCStrategy.h"
33 #include "llvm/CodeGen/GCMetadata.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineJumpTableInfo.h"
39 #include "llvm/CodeGen/MachineModuleInfo.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
42 #include "llvm/CodeGen/SchedulerRegistry.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetFrameInfo.h"
47 #include "llvm/Target/TargetIntrinsicInfo.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetLowering.h"
50 #include "llvm/Target/TargetMachine.h"
51 #include "llvm/Target/TargetOptions.h"
52 #include "llvm/Support/Compiler.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/MathExtras.h"
56 #include "llvm/Support/Timer.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/ADT/Statistic.h"
62 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
63 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
66 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
67 cl::desc("Enable verbose messages in the \"fast\" "
68 "instruction selector"));
70 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
71 cl::desc("Enable abort calls when \"fast\" instruction fails"));
73 SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
74 cl::desc("Schedule copies of livein registers"),
79 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
80 cl::desc("Pop up a window to show dags before the first "
83 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize types"));
86 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before legalize"));
89 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
90 cl::desc("Pop up a window to show dags before the second "
93 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
94 cl::desc("Pop up a window to show dags before the post legalize types"
95 " dag combine pass"));
97 ViewISelDAGs("view-isel-dags", cl::Hidden,
98 cl::desc("Pop up a window to show isel dags as they are selected"));
100 ViewSchedDAGs("view-sched-dags", cl::Hidden,
101 cl::desc("Pop up a window to show sched dags as they are processed"));
103 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
104 cl::desc("Pop up a window to show SUnit dags after they are processed"));
106 static const bool ViewDAGCombine1 = false,
107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
108 ViewDAGCombine2 = false,
109 ViewDAGCombineLT = false,
110 ViewISelDAGs = false, ViewSchedDAGs = false,
111 ViewSUnitDAGs = false;
114 //===---------------------------------------------------------------------===//
116 /// RegisterScheduler class - Track the registration of instruction schedulers.
118 //===---------------------------------------------------------------------===//
119 MachinePassRegistry RegisterScheduler::Registry;
121 //===---------------------------------------------------------------------===//
123 /// ISHeuristic command line option for instruction schedulers.
125 //===---------------------------------------------------------------------===//
126 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
127 RegisterPassParser<RegisterScheduler> >
128 ISHeuristic("pre-RA-sched",
129 cl::init(&createDefaultScheduler),
130 cl::desc("Instruction schedulers available (before register"
133 static RegisterScheduler
134 defaultListDAGScheduler("default", "Best scheduler for the target",
135 createDefaultScheduler);
138 //===--------------------------------------------------------------------===//
139 /// createDefaultScheduler - This creates an instruction scheduler appropriate
141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
142 CodeGenOpt::Level OptLevel) {
143 const TargetLowering &TLI = IS->getTargetLowering();
145 if (OptLevel == CodeGenOpt::None)
146 return createFastDAGScheduler(IS, OptLevel);
147 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
148 return createTDListDAGScheduler(IS, OptLevel);
149 assert(TLI.getSchedulingPreference() ==
150 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
151 return createBURRListDAGScheduler(IS, OptLevel);
155 // EmitInstrWithCustomInserter - This method should be implemented by targets
156 // that mark instructions with the 'usesCustomInserter' flag. These
157 // instructions are special in various ways, which require special support to
158 // insert. The specified MachineInstr is created but not inserted into any
159 // basic blocks, and this method is called to expand it into a sequence of
160 // instructions, potentially also creating new basic blocks and control flow.
161 // When new basic blocks are inserted and the edges from MBB to its successors
162 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
164 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
165 MachineBasicBlock *MBB,
166 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
168 dbgs() << "If a target marks an instruction with "
169 "'usesCustomInserter', it must implement "
170 "TargetLowering::EmitInstrWithCustomInserter!";
176 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
177 /// physical register has only a single copy use, then coalesced the copy
179 static void EmitLiveInCopy(MachineBasicBlock *MBB,
180 MachineBasicBlock::iterator &InsertPos,
181 unsigned VirtReg, unsigned PhysReg,
182 const TargetRegisterClass *RC,
183 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
184 const MachineRegisterInfo &MRI,
185 const TargetRegisterInfo &TRI,
186 const TargetInstrInfo &TII) {
187 unsigned NumUses = 0;
188 MachineInstr *UseMI = NULL;
189 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
190 UE = MRI.use_end(); UI != UE; ++UI) {
196 // If the number of uses is not one, or the use is not a move instruction,
197 // don't coalesce. Also, only coalesce away a virtual register to virtual
199 bool Coalesced = false;
200 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
202 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
203 TargetRegisterInfo::isVirtualRegister(DstReg)) {
208 // Now find an ideal location to insert the copy.
209 MachineBasicBlock::iterator Pos = InsertPos;
210 while (Pos != MBB->begin()) {
211 MachineInstr *PrevMI = prior(Pos);
212 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
213 // copyRegToReg might emit multiple instructions to do a copy.
214 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
215 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
216 // This is what the BB looks like right now:
221 // We want to insert "r1025 = mov r1". Inserting this copy below the
222 // move to r1024 makes it impossible for that move to be coalesced.
229 break; // Woot! Found a good location.
233 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
234 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
237 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
239 if (&*InsertPos == UseMI) ++InsertPos;
244 /// EmitLiveInCopies - If this is the first basic block in the function,
245 /// and if it has live ins that need to be copied into vregs, emit the
246 /// copies into the block.
247 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
248 const MachineRegisterInfo &MRI,
249 const TargetRegisterInfo &TRI,
250 const TargetInstrInfo &TII) {
251 if (SchedLiveInCopies) {
252 // Emit the copies at a heuristically-determined location in the block.
253 DenseMap<MachineInstr*, unsigned> CopyRegMap;
254 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
255 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
256 E = MRI.livein_end(); LI != E; ++LI)
258 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
259 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
260 RC, CopyRegMap, MRI, TRI, TII);
263 // Emit the copies into the top of the block.
264 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
265 E = MRI.livein_end(); LI != E; ++LI)
267 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
268 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
269 LI->second, LI->first, RC, RC);
270 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
276 //===----------------------------------------------------------------------===//
277 // SelectionDAGISel code
278 //===----------------------------------------------------------------------===//
280 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
281 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
282 FuncInfo(new FunctionLoweringInfo(TLI)),
283 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
284 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
290 SelectionDAGISel::~SelectionDAGISel() {
296 unsigned SelectionDAGISel::MakeReg(EVT VT) {
297 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
300 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
301 AU.addRequired<AliasAnalysis>();
302 AU.addPreserved<AliasAnalysis>();
303 AU.addRequired<GCModuleInfo>();
304 AU.addPreserved<GCModuleInfo>();
305 MachineFunctionPass::getAnalysisUsage(AU);
308 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
309 Function &Fn = *mf.getFunction();
311 // Do some sanity-checking on the command-line options.
312 assert((!EnableFastISelVerbose || EnableFastISel) &&
313 "-fast-isel-verbose requires -fast-isel");
314 assert((!EnableFastISelAbort || EnableFastISel) &&
315 "-fast-isel-abort requires -fast-isel");
317 // Get alias analysis for load/store combining.
318 AA = &getAnalysis<AliasAnalysis>();
321 const TargetInstrInfo &TII = *TM.getInstrInfo();
322 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
325 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn);
328 RegInfo = &MF->getRegInfo();
329 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
332 FuncInfo->set(Fn, *MF, EnableFastISel);
335 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
336 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
338 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
340 SelectAllBasicBlocks(Fn, *MF, TII);
342 // If the first basic block in the function has live ins that need to be
343 // copied into vregs, emit the copies into the top of the block before
344 // emitting the code for the block.
345 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
347 // Add function live-ins to entry block live-in set.
348 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
349 E = RegInfo->livein_end(); I != E; ++I)
350 MF->begin()->addLiveIn(I->first);
353 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
354 "Not all catch info was assigned to a landing pad!");
362 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
363 /// attached with this instruction.
364 static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB,
365 FastISel *FastIS, MachineFunction *MF) {
366 DebugLoc DL = I->getDebugLoc();
367 if (DL.isUnknown()) return;
369 SDB->setCurDebugLoc(DL);
372 FastIS->setCurDebugLoc(DL);
374 // If the function doesn't have a default debug location yet, set
375 // it. This is kind of a hack.
376 if (MF->getDefaultDebugLoc().isUnknown())
377 MF->setDefaultDebugLoc(DL);
380 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
381 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
382 SDB->setCurDebugLoc(DebugLoc());
384 FastIS->setCurDebugLoc(DebugLoc());
387 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
388 BasicBlock::iterator Begin,
389 BasicBlock::iterator End,
391 SDB->setCurrentBasicBlock(BB);
393 // Lower all of the non-terminator instructions. If a call is emitted
394 // as a tail call, cease emitting nodes for this block.
395 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
396 SetDebugLoc(I, SDB, 0, MF);
398 if (!isa<TerminatorInst>(I)) {
401 // Set the current debug location back to "unknown" so that it doesn't
402 // spuriously apply to subsequent instructions.
403 ResetDebugLoc(SDB, 0);
407 if (!SDB->HasTailCall) {
408 // Ensure that all instructions which are used outside of their defining
409 // blocks are available as virtual registers. Invoke is handled elsewhere.
410 for (BasicBlock::iterator I = Begin; I != End; ++I)
411 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
412 SDB->CopyToExportRegsIfNeeded(I);
414 // Handle PHI nodes in successor blocks.
415 if (End == LLVMBB->end()) {
416 HandlePHINodesInSuccessorBlocks(LLVMBB);
418 // Lower the terminator after the copies are emitted.
419 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF);
420 SDB->visit(*LLVMBB->getTerminator());
421 ResetDebugLoc(SDB, 0);
425 // Make sure the root of the DAG is up-to-date.
426 CurDAG->setRoot(SDB->getControlRoot());
428 // Final step, emit the lowered DAG as machine code.
430 HadTailCall = SDB->HasTailCall;
435 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
436 /// nodes from the worklist.
437 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
438 SmallVector<SDNode*, 128> &Worklist;
439 SmallPtrSet<SDNode*, 128> &InWorklist;
441 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
442 SmallPtrSet<SDNode*, 128> &inwl)
443 : Worklist(wl), InWorklist(inwl) {}
445 void RemoveFromWorklist(SDNode *N) {
446 if (!InWorklist.erase(N)) return;
448 SmallVector<SDNode*, 128>::iterator I =
449 std::find(Worklist.begin(), Worklist.end(), N);
450 assert(I != Worklist.end() && "Not in worklist");
452 *I = Worklist.back();
456 virtual void NodeDeleted(SDNode *N, SDNode *E) {
457 RemoveFromWorklist(N);
460 virtual void NodeUpdated(SDNode *N) {
466 /// TrivialTruncElim - Eliminate some trivial nops that can result from
467 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
468 static bool TrivialTruncElim(SDValue Op,
469 TargetLowering::TargetLoweringOpt &TLO) {
470 SDValue N0 = Op.getOperand(0);
471 EVT VT = Op.getValueType();
472 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
473 N0.getOpcode() == ISD::SIGN_EXTEND ||
474 N0.getOpcode() == ISD::ANY_EXTEND) &&
475 N0.getOperand(0).getValueType() == VT) {
476 return TLO.CombineTo(Op, N0.getOperand(0));
481 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
482 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
483 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
484 void SelectionDAGISel::ShrinkDemandedOps() {
485 SmallVector<SDNode*, 128> Worklist;
486 SmallPtrSet<SDNode*, 128> InWorklist;
488 // Add all the dag nodes to the worklist.
489 Worklist.reserve(CurDAG->allnodes_size());
490 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
491 E = CurDAG->allnodes_end(); I != E; ++I) {
492 Worklist.push_back(I);
493 InWorklist.insert(I);
496 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
497 while (!Worklist.empty()) {
498 SDNode *N = Worklist.pop_back_val();
501 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
502 // Deleting this node may make its operands dead, add them to the worklist
503 // if they aren't already there.
504 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
505 if (InWorklist.insert(N->getOperand(i).getNode()))
506 Worklist.push_back(N->getOperand(i).getNode());
508 CurDAG->DeleteNode(N);
512 // Run ShrinkDemandedOp on scalar binary operations.
513 if (N->getNumValues() != 1 ||
514 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
517 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
518 APInt Demanded = APInt::getAllOnesValue(BitWidth);
519 APInt KnownZero, KnownOne;
520 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
521 KnownZero, KnownOne, TLO) &&
522 (N->getOpcode() != ISD::TRUNCATE ||
523 !TrivialTruncElim(SDValue(N, 0), TLO)))
527 assert(!InWorklist.count(N) && "Already in worklist");
528 Worklist.push_back(N);
529 InWorklist.insert(N);
531 // Replace the old value with the new one.
532 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
533 TLO.Old.getNode()->dump(CurDAG);
534 errs() << "\nWith: ";
535 TLO.New.getNode()->dump(CurDAG);
538 if (InWorklist.insert(TLO.New.getNode()))
539 Worklist.push_back(TLO.New.getNode());
541 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
542 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
544 if (!TLO.Old.getNode()->use_empty()) continue;
546 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
548 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
549 if (OpNode->hasOneUse()) {
550 // Add OpNode to the end of the list to revisit.
551 DeadNodes.RemoveFromWorklist(OpNode);
552 Worklist.push_back(OpNode);
553 InWorklist.insert(OpNode);
557 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
558 CurDAG->DeleteNode(TLO.Old.getNode());
562 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
563 SmallPtrSet<SDNode*, 128> VisitedNodes;
564 SmallVector<SDNode*, 128> Worklist;
566 Worklist.push_back(CurDAG->getRoot().getNode());
573 SDNode *N = Worklist.pop_back_val();
575 // If we've already seen this node, ignore it.
576 if (!VisitedNodes.insert(N))
579 // Otherwise, add all chain operands to the worklist.
580 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
581 if (N->getOperand(i).getValueType() == MVT::Other)
582 Worklist.push_back(N->getOperand(i).getNode());
584 // If this is a CopyToReg with a vreg dest, process it.
585 if (N->getOpcode() != ISD::CopyToReg)
588 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
589 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
592 // Ignore non-scalar or non-integer values.
593 SDValue Src = N->getOperand(2);
594 EVT SrcVT = Src.getValueType();
595 if (!SrcVT.isInteger() || SrcVT.isVector())
598 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
599 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
600 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
602 // Only install this information if it tells us something.
603 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
604 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
605 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
606 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
607 FunctionLoweringInfo::LiveOutInfo &LOI =
608 FuncInfo->LiveOutRegInfo[DestReg];
609 LOI.NumSignBits = NumSignBits;
610 LOI.KnownOne = KnownOne;
611 LOI.KnownZero = KnownZero;
613 } while (!Worklist.empty());
616 void SelectionDAGISel::CodeGenAndEmitDAG() {
617 std::string GroupName;
618 if (TimePassesIsEnabled)
619 GroupName = "Instruction Selection and Scheduling";
620 std::string BlockName;
621 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
622 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
624 BlockName = MF->getFunction()->getNameStr() + ":" +
625 BB->getBasicBlock()->getNameStr();
627 DEBUG(dbgs() << "Initial selection DAG:\n");
628 DEBUG(CurDAG->dump());
630 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
632 // Run the DAG combiner in pre-legalize mode.
633 if (TimePassesIsEnabled) {
634 NamedRegionTimer T("DAG Combining 1", GroupName);
635 CurDAG->Combine(Unrestricted, *AA, OptLevel);
637 CurDAG->Combine(Unrestricted, *AA, OptLevel);
640 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
641 DEBUG(CurDAG->dump());
643 // Second step, hack on the DAG until it only uses operations and types that
644 // the target supports.
645 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
649 if (TimePassesIsEnabled) {
650 NamedRegionTimer T("Type Legalization", GroupName);
651 Changed = CurDAG->LegalizeTypes();
653 Changed = CurDAG->LegalizeTypes();
656 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
657 DEBUG(CurDAG->dump());
660 if (ViewDAGCombineLT)
661 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
663 // Run the DAG combiner in post-type-legalize mode.
664 if (TimePassesIsEnabled) {
665 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
666 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
668 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
671 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
672 DEBUG(CurDAG->dump());
675 if (TimePassesIsEnabled) {
676 NamedRegionTimer T("Vector Legalization", GroupName);
677 Changed = CurDAG->LegalizeVectors();
679 Changed = CurDAG->LegalizeVectors();
683 if (TimePassesIsEnabled) {
684 NamedRegionTimer T("Type Legalization 2", GroupName);
685 CurDAG->LegalizeTypes();
687 CurDAG->LegalizeTypes();
690 if (ViewDAGCombineLT)
691 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
693 // Run the DAG combiner in post-type-legalize mode.
694 if (TimePassesIsEnabled) {
695 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
696 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
698 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
701 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
702 DEBUG(CurDAG->dump());
705 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
707 if (TimePassesIsEnabled) {
708 NamedRegionTimer T("DAG Legalization", GroupName);
709 CurDAG->Legalize(OptLevel);
711 CurDAG->Legalize(OptLevel);
714 DEBUG(dbgs() << "Legalized selection DAG:\n");
715 DEBUG(CurDAG->dump());
717 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
719 // Run the DAG combiner in post-legalize mode.
720 if (TimePassesIsEnabled) {
721 NamedRegionTimer T("DAG Combining 2", GroupName);
722 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
724 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
727 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
728 DEBUG(CurDAG->dump());
730 if (OptLevel != CodeGenOpt::None) {
732 ComputeLiveOutVRegInfo();
735 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
737 // Third, instruction select all of the operations to machine code, adding the
738 // code to the MachineBasicBlock.
739 if (TimePassesIsEnabled) {
740 NamedRegionTimer T("Instruction Selection", GroupName);
741 DoInstructionSelection();
743 DoInstructionSelection();
746 DEBUG(dbgs() << "Selected selection DAG:\n");
747 DEBUG(CurDAG->dump());
749 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
751 // Schedule machine code.
752 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
753 if (TimePassesIsEnabled) {
754 NamedRegionTimer T("Instruction Scheduling", GroupName);
755 Scheduler->Run(CurDAG, BB, BB->end());
757 Scheduler->Run(CurDAG, BB, BB->end());
760 if (ViewSUnitDAGs) Scheduler->viewGraph();
762 // Emit machine code to BB. This can change 'BB' to the last block being
764 if (TimePassesIsEnabled) {
765 NamedRegionTimer T("Instruction Creation", GroupName);
766 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
768 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
771 // Free the scheduler state.
772 if (TimePassesIsEnabled) {
773 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
779 DEBUG(dbgs() << "Selected machine code:\n");
783 void SelectionDAGISel::DoInstructionSelection() {
784 DEBUG(errs() << "===== Instruction selection begins:\n");
788 // Select target instructions for the DAG.
790 // Number all nodes with a topological order and set DAGSize.
791 DAGSize = CurDAG->AssignTopologicalOrder();
793 // Create a dummy node (which is not added to allnodes), that adds
794 // a reference to the root node, preventing it from being deleted,
795 // and tracking any changes of the root.
796 HandleSDNode Dummy(CurDAG->getRoot());
797 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
800 // The AllNodes list is now topological-sorted. Visit the
801 // nodes by starting at the end of the list (the root of the
802 // graph) and preceding back toward the beginning (the entry
804 while (ISelPosition != CurDAG->allnodes_begin()) {
805 SDNode *Node = --ISelPosition;
806 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
807 // but there are currently some corner cases that it misses. Also, this
808 // makes it theoretically possible to disable the DAGCombiner.
809 if (Node->use_empty())
812 SDNode *ResNode = Select(Node);
814 // FIXME: This is pretty gross. 'Select' should be changed to not return
815 // anything at all and this code should be nuked with a tactical strike.
817 // If node should not be replaced, continue with the next one.
818 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
822 ReplaceUses(Node, ResNode);
824 // If after the replacement this node is not used any more,
825 // remove this dead node.
826 if (Node->use_empty()) { // Don't delete EntryToken, etc.
827 ISelUpdater ISU(ISelPosition);
828 CurDAG->RemoveDeadNode(Node, &ISU);
832 CurDAG->setRoot(Dummy.getValue());
834 DEBUG(errs() << "===== Instruction selection ends:\n");
836 PostprocessISelDAG();
840 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
842 const TargetInstrInfo &TII) {
843 // Initialize the Fast-ISel state, if needed.
844 FastISel *FastIS = 0;
846 FastIS = TLI.createFastISel(MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
847 FuncInfo->StaticAllocaMap
849 , FuncInfo->CatchInfoLost
853 // Iterate over all basic blocks in the function.
854 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
855 BasicBlock *LLVMBB = &*I;
856 BB = FuncInfo->MBBMap[LLVMBB];
858 BasicBlock::iterator const Begin = LLVMBB->begin();
859 BasicBlock::iterator const End = LLVMBB->end();
860 BasicBlock::iterator BI = Begin;
862 // Lower any arguments needed in this block if this is the entry block.
863 bool SuppressFastISel = false;
864 if (LLVMBB == &Fn.getEntryBlock()) {
865 LowerArguments(LLVMBB);
867 // If any of the arguments has the byval attribute, forgo
868 // fast-isel in the entry block.
871 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
873 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
874 if (EnableFastISelVerbose || EnableFastISelAbort)
875 dbgs() << "FastISel skips entry block due to byval argument\n";
876 SuppressFastISel = true;
882 if (BB->isLandingPad()) {
883 // Add a label to mark the beginning of the landing pad. Deletion of the
884 // landing pad can thus be detected via the MachineModuleInfo.
885 MCSymbol *Label = MF.getMMI().addLandingPad(BB);
887 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
888 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
890 // Mark exception register as live in.
891 unsigned Reg = TLI.getExceptionAddressRegister();
892 if (Reg) BB->addLiveIn(Reg);
894 // Mark exception selector register as live in.
895 Reg = TLI.getExceptionSelectorRegister();
896 if (Reg) BB->addLiveIn(Reg);
898 // FIXME: Hack around an exception handling flaw (PR1508): the personality
899 // function and list of typeids logically belong to the invoke (or, if you
900 // like, the basic block containing the invoke), and need to be associated
901 // with it in the dwarf exception handling tables. Currently however the
902 // information is provided by an intrinsic (eh.selector) that can be moved
903 // to unexpected places by the optimizers: if the unwind edge is critical,
904 // then breaking it can result in the intrinsics being in the successor of
905 // the landing pad, not the landing pad itself. This results
906 // in exceptions not being caught because no typeids are associated with
907 // the invoke. This may not be the only way things can go wrong, but it
908 // is the only way we try to work around for the moment.
909 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
911 if (Br && Br->isUnconditional()) { // Critical edge?
912 BasicBlock::iterator I, E;
913 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
914 if (isa<EHSelectorInst>(I))
918 // No catch info found - try to extract some from the successor.
919 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF.getMMI(), *FuncInfo);
923 // Before doing SelectionDAG ISel, see if FastISel has been requested.
924 if (FastIS && !SuppressFastISel) {
925 // Emit code for any incoming arguments. This must happen before
926 // beginning FastISel on the entry block.
927 if (LLVMBB == &Fn.getEntryBlock()) {
928 CurDAG->setRoot(SDB->getControlRoot());
932 FastIS->startNewBlock(BB);
933 // Do FastISel on as many instructions as possible.
934 for (; BI != End; ++BI) {
935 // Just before the terminator instruction, insert instructions to
936 // feed PHI nodes in successor blocks.
937 if (isa<TerminatorInst>(BI))
938 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
939 ++NumFastIselFailures;
940 ResetDebugLoc(SDB, FastIS);
941 if (EnableFastISelVerbose || EnableFastISelAbort) {
942 dbgs() << "FastISel miss: ";
945 assert(!EnableFastISelAbort &&
946 "FastISel didn't handle a PHI in a successor");
950 SetDebugLoc(BI, SDB, FastIS, &MF);
952 // Try to select the instruction with FastISel.
953 if (FastIS->SelectInstruction(BI)) {
954 ResetDebugLoc(SDB, FastIS);
958 // Clear out the debug location so that it doesn't carry over to
959 // unrelated instructions.
960 ResetDebugLoc(SDB, FastIS);
962 // Then handle certain instructions as single-LLVM-Instruction blocks.
963 if (isa<CallInst>(BI)) {
964 ++NumFastIselFailures;
965 if (EnableFastISelVerbose || EnableFastISelAbort) {
966 dbgs() << "FastISel missed call: ";
970 if (!BI->getType()->isVoidTy()) {
971 unsigned &R = FuncInfo->ValueMap[BI];
973 R = FuncInfo->CreateRegForValue(BI);
976 bool HadTailCall = false;
977 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
979 // If the call was emitted as a tail call, we're done with the block.
985 // If the instruction was codegen'd with multiple blocks,
986 // inform the FastISel object where to resume inserting.
987 FastIS->setCurrentBlock(BB);
991 // Otherwise, give up on FastISel for the rest of the block.
992 // For now, be a little lenient about non-branch terminators.
993 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
994 ++NumFastIselFailures;
995 if (EnableFastISelVerbose || EnableFastISelAbort) {
996 dbgs() << "FastISel miss: ";
999 if (EnableFastISelAbort)
1000 // The "fast" selector couldn't handle something and bailed.
1001 // For the purpose of debugging, just abort.
1002 llvm_unreachable("FastISel didn't select the entire block");
1008 // Run SelectionDAG instruction selection on the remainder of the block
1009 // not handled by FastISel. If FastISel is not run, this is the entire
1013 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
1023 SelectionDAGISel::FinishBasicBlock() {
1025 DEBUG(dbgs() << "Target-post-processed machine code:\n");
1028 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1029 << SDB->PHINodesToUpdate.size() << "\n");
1030 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
1031 dbgs() << "Node " << i << " : ("
1032 << SDB->PHINodesToUpdate[i].first
1033 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
1035 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1036 // PHI nodes in successors.
1037 if (SDB->SwitchCases.empty() &&
1038 SDB->JTCases.empty() &&
1039 SDB->BitTestCases.empty()) {
1040 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1041 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1042 assert(PHI->isPHI() &&
1043 "This is not a machine PHI node that we are updating!");
1044 if (!BB->isSuccessor(PHI->getParent()))
1046 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1048 PHI->addOperand(MachineOperand::CreateMBB(BB));
1050 SDB->PHINodesToUpdate.clear();
1054 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1055 // Lower header first, if it wasn't already lowered
1056 if (!SDB->BitTestCases[i].Emitted) {
1057 // Set the current basic block to the mbb we wish to insert the code into
1058 BB = SDB->BitTestCases[i].Parent;
1059 SDB->setCurrentBasicBlock(BB);
1061 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
1062 CurDAG->setRoot(SDB->getRoot());
1063 CodeGenAndEmitDAG();
1067 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1068 // Set the current basic block to the mbb we wish to insert the code into
1069 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
1070 SDB->setCurrentBasicBlock(BB);
1073 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
1074 SDB->BitTestCases[i].Reg,
1075 SDB->BitTestCases[i].Cases[j]);
1077 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
1078 SDB->BitTestCases[i].Reg,
1079 SDB->BitTestCases[i].Cases[j]);
1082 CurDAG->setRoot(SDB->getRoot());
1083 CodeGenAndEmitDAG();
1088 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1089 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1090 MachineBasicBlock *PHIBB = PHI->getParent();
1091 assert(PHI->isPHI() &&
1092 "This is not a machine PHI node that we are updating!");
1093 // This is "default" BB. We have two jumps to it. From "header" BB and
1094 // from last "case" BB.
1095 if (PHIBB == SDB->BitTestCases[i].Default) {
1096 PHI->addOperand(MachineOperand::
1097 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1098 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1099 PHI->addOperand(MachineOperand::
1100 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1101 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1104 // One of "cases" BB.
1105 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1107 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1108 if (cBB->isSuccessor(PHIBB)) {
1109 PHI->addOperand(MachineOperand::
1110 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1111 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1116 SDB->BitTestCases.clear();
1118 // If the JumpTable record is filled in, then we need to emit a jump table.
1119 // Updating the PHI nodes is tricky in this case, since we need to determine
1120 // whether the PHI is a successor of the range check MBB or the jump table MBB
1121 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1122 // Lower header first, if it wasn't already lowered
1123 if (!SDB->JTCases[i].first.Emitted) {
1124 // Set the current basic block to the mbb we wish to insert the code into
1125 BB = SDB->JTCases[i].first.HeaderBB;
1126 SDB->setCurrentBasicBlock(BB);
1128 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
1129 CurDAG->setRoot(SDB->getRoot());
1130 CodeGenAndEmitDAG();
1134 // Set the current basic block to the mbb we wish to insert the code into
1135 BB = SDB->JTCases[i].second.MBB;
1136 SDB->setCurrentBasicBlock(BB);
1138 SDB->visitJumpTable(SDB->JTCases[i].second);
1139 CurDAG->setRoot(SDB->getRoot());
1140 CodeGenAndEmitDAG();
1144 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1145 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1146 MachineBasicBlock *PHIBB = PHI->getParent();
1147 assert(PHI->isPHI() &&
1148 "This is not a machine PHI node that we are updating!");
1149 // "default" BB. We can go there only from header BB.
1150 if (PHIBB == SDB->JTCases[i].second.Default) {
1152 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1154 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1156 // JT BB. Just iterate over successors here
1157 if (BB->isSuccessor(PHIBB)) {
1159 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1160 PHI->addOperand(MachineOperand::CreateMBB(BB));
1164 SDB->JTCases.clear();
1166 // If the switch block involved a branch to one of the actual successors, we
1167 // need to update PHI nodes in that block.
1168 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1169 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1170 assert(PHI->isPHI() &&
1171 "This is not a machine PHI node that we are updating!");
1172 if (BB->isSuccessor(PHI->getParent())) {
1173 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1175 PHI->addOperand(MachineOperand::CreateMBB(BB));
1179 // If we generated any switch lowering information, build and codegen any
1180 // additional DAGs necessary.
1181 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1182 // Set the current basic block to the mbb we wish to insert the code into
1183 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1184 SDB->setCurrentBasicBlock(BB);
1187 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1188 CurDAG->setRoot(SDB->getRoot());
1189 CodeGenAndEmitDAG();
1191 // Handle any PHI nodes in successors of this chunk, as if we were coming
1192 // from the original BB before switch expansion. Note that PHI nodes can
1193 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1194 // handle them the right number of times.
1195 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1196 // If new BB's are created during scheduling, the edges may have been
1197 // updated. That is, the edge from ThisBB to BB may have been split and
1198 // BB's predecessor is now another block.
1199 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1200 SDB->EdgeMapping.find(BB);
1201 if (EI != SDB->EdgeMapping.end())
1202 ThisBB = EI->second;
1204 // BB may have been removed from the CFG if a branch was constant folded.
1205 if (ThisBB->isSuccessor(BB)) {
1206 for (MachineBasicBlock::iterator Phi = BB->begin();
1207 Phi != BB->end() && Phi->isPHI();
1209 // This value for this PHI node is recorded in PHINodesToUpdate.
1210 for (unsigned pn = 0; ; ++pn) {
1211 assert(pn != SDB->PHINodesToUpdate.size() &&
1212 "Didn't find PHI entry!");
1213 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1214 Phi->addOperand(MachineOperand::
1215 CreateReg(SDB->PHINodesToUpdate[pn].second,
1217 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1224 // Don't process RHS if same block as LHS.
1225 if (BB == SDB->SwitchCases[i].FalseBB)
1226 SDB->SwitchCases[i].FalseBB = 0;
1228 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1229 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1230 SDB->SwitchCases[i].FalseBB = 0;
1232 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1235 SDB->SwitchCases.clear();
1237 SDB->PHINodesToUpdate.clear();
1241 /// Create the scheduler. If a specific scheduler was specified
1242 /// via the SchedulerRegistry, use it, otherwise select the
1243 /// one preferred by the target.
1245 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1246 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1250 RegisterScheduler::setDefault(Ctor);
1253 return Ctor(this, OptLevel);
1256 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1257 return new ScheduleHazardRecognizer();
1260 //===----------------------------------------------------------------------===//
1261 // Helper functions used by the generated instruction selector.
1262 //===----------------------------------------------------------------------===//
1263 // Calls to these methods are generated by tblgen.
1265 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1266 /// the dag combiner simplified the 255, we still want to match. RHS is the
1267 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1268 /// specified in the .td file (e.g. 255).
1269 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1270 int64_t DesiredMaskS) const {
1271 const APInt &ActualMask = RHS->getAPIntValue();
1272 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1274 // If the actual mask exactly matches, success!
1275 if (ActualMask == DesiredMask)
1278 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1279 if (ActualMask.intersects(~DesiredMask))
1282 // Otherwise, the DAG Combiner may have proven that the value coming in is
1283 // either already zero or is not demanded. Check for known zero input bits.
1284 APInt NeededMask = DesiredMask & ~ActualMask;
1285 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1288 // TODO: check to see if missing bits are just not demanded.
1290 // Otherwise, this pattern doesn't match.
1294 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1295 /// the dag combiner simplified the 255, we still want to match. RHS is the
1296 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1297 /// specified in the .td file (e.g. 255).
1298 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1299 int64_t DesiredMaskS) const {
1300 const APInt &ActualMask = RHS->getAPIntValue();
1301 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1303 // If the actual mask exactly matches, success!
1304 if (ActualMask == DesiredMask)
1307 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1308 if (ActualMask.intersects(~DesiredMask))
1311 // Otherwise, the DAG Combiner may have proven that the value coming in is
1312 // either already zero or is not demanded. Check for known zero input bits.
1313 APInt NeededMask = DesiredMask & ~ActualMask;
1315 APInt KnownZero, KnownOne;
1316 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1318 // If all the missing bits in the or are already known to be set, match!
1319 if ((NeededMask & KnownOne) == NeededMask)
1322 // TODO: check to see if missing bits are just not demanded.
1324 // Otherwise, this pattern doesn't match.
1329 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1330 /// by tblgen. Others should not call it.
1331 void SelectionDAGISel::
1332 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1333 std::vector<SDValue> InOps;
1334 std::swap(InOps, Ops);
1336 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1337 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1338 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1340 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1341 if (InOps[e-1].getValueType() == MVT::Flag)
1342 --e; // Don't process a flag operand if it is here.
1345 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1346 if (!InlineAsm::isMemKind(Flags)) {
1347 // Just skip over this operand, copying the operands verbatim.
1348 Ops.insert(Ops.end(), InOps.begin()+i,
1349 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1350 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1352 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1353 "Memory operand with multiple values?");
1354 // Otherwise, this is a memory operand. Ask the target to select it.
1355 std::vector<SDValue> SelOps;
1356 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1357 llvm_report_error("Could not match memory address. Inline asm"
1360 // Add this to the output node.
1362 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1363 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1364 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1369 // Add the flag input back if present.
1370 if (e != InOps.size())
1371 Ops.push_back(InOps.back());
1374 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1377 static SDNode *findFlagUse(SDNode *N) {
1378 unsigned FlagResNo = N->getNumValues()-1;
1379 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1380 SDUse &Use = I.getUse();
1381 if (Use.getResNo() == FlagResNo)
1382 return Use.getUser();
1387 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1388 /// This function recursively traverses up the operand chain, ignoring
1390 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1391 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1392 bool IgnoreChains) {
1393 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1394 // greater than all of its (recursive) operands. If we scan to a point where
1395 // 'use' is smaller than the node we're scanning for, then we know we will
1398 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1399 // happen because we scan down to newly selected nodes in the case of flag
1401 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1404 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1405 // won't fail if we scan it again.
1406 if (!Visited.insert(Use))
1409 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1410 // Ignore chain uses, they are validated by HandleMergeInputChains.
1411 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1414 SDNode *N = Use->getOperand(i).getNode();
1416 if (Use == ImmedUse || Use == Root)
1417 continue; // We are not looking for immediate use.
1422 // Traverse up the operand chain.
1423 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1429 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1430 /// operand node N of U during instruction selection that starts at Root.
1431 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1432 SDNode *Root) const {
1433 if (OptLevel == CodeGenOpt::None) return false;
1434 return N.hasOneUse();
1437 /// IsLegalToFold - Returns true if the specific operand node N of
1438 /// U can be folded during instruction selection that starts at Root.
1439 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1440 bool IgnoreChains) const {
1441 if (OptLevel == CodeGenOpt::None) return false;
1443 // If Root use can somehow reach N through a path that that doesn't contain
1444 // U then folding N would create a cycle. e.g. In the following
1445 // diagram, Root can reach N through X. If N is folded into into Root, then
1446 // X is both a predecessor and a successor of U.
1457 // * indicates nodes to be folded together.
1459 // If Root produces a flag, then it gets (even more) interesting. Since it
1460 // will be "glued" together with its flag use in the scheduler, we need to
1461 // check if it might reach N.
1480 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1481 // (call it Fold), then X is a predecessor of FU and a successor of
1482 // Fold. But since Fold and FU are flagged together, this will create
1483 // a cycle in the scheduling graph.
1485 // If the node has flags, walk down the graph to the "lowest" node in the
1487 EVT VT = Root->getValueType(Root->getNumValues()-1);
1488 while (VT == MVT::Flag) {
1489 SDNode *FU = findFlagUse(Root);
1493 VT = Root->getValueType(Root->getNumValues()-1);
1495 // If our query node has a flag result with a use, we've walked up it. If
1496 // the user (which has already been selected) has a chain or indirectly uses
1497 // the chain, our WalkChainUsers predicate will not consider it. Because of
1498 // this, we cannot ignore chains in this predicate.
1499 IgnoreChains = false;
1503 SmallPtrSet<SDNode*, 16> Visited;
1504 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1507 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1508 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1509 SelectInlineAsmMemoryOperands(Ops);
1511 std::vector<EVT> VTs;
1512 VTs.push_back(MVT::Other);
1513 VTs.push_back(MVT::Flag);
1514 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1515 VTs, &Ops[0], Ops.size());
1517 return New.getNode();
1520 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1521 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1524 /// GetVBR - decode a vbr encoding whose top bit is set.
1525 ALWAYS_INLINE static uint64_t
1526 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1527 assert(Val >= 128 && "Not a VBR");
1528 Val &= 127; // Remove first vbr bit.
1533 NextBits = MatcherTable[Idx++];
1534 Val |= (NextBits&127) << Shift;
1536 } while (NextBits & 128);
1542 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1543 /// interior flag and chain results to use the new flag and chain results.
1544 void SelectionDAGISel::
1545 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1546 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1548 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1549 bool isMorphNodeTo) {
1550 SmallVector<SDNode*, 4> NowDeadNodes;
1552 ISelUpdater ISU(ISelPosition);
1554 // Now that all the normal results are replaced, we replace the chain and
1555 // flag results if present.
1556 if (!ChainNodesMatched.empty()) {
1557 assert(InputChain.getNode() != 0 &&
1558 "Matched input chains but didn't produce a chain");
1559 // Loop over all of the nodes we matched that produced a chain result.
1560 // Replace all the chain results with the final chain we ended up with.
1561 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1562 SDNode *ChainNode = ChainNodesMatched[i];
1564 // If this node was already deleted, don't look at it.
1565 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1568 // Don't replace the results of the root node if we're doing a
1570 if (ChainNode == NodeToMatch && isMorphNodeTo)
1573 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1574 if (ChainVal.getValueType() == MVT::Flag)
1575 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1576 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1577 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1579 // If the node became dead and we haven't already seen it, delete it.
1580 if (ChainNode->use_empty() &&
1581 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1582 NowDeadNodes.push_back(ChainNode);
1586 // If the result produces a flag, update any flag results in the matched
1587 // pattern with the flag result.
1588 if (InputFlag.getNode() != 0) {
1589 // Handle any interior nodes explicitly marked.
1590 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1591 SDNode *FRN = FlagResultNodesMatched[i];
1593 // If this node was already deleted, don't look at it.
1594 if (FRN->getOpcode() == ISD::DELETED_NODE)
1597 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1598 "Doesn't have a flag result");
1599 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1602 // If the node became dead and we haven't already seen it, delete it.
1603 if (FRN->use_empty() &&
1604 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1605 NowDeadNodes.push_back(FRN);
1609 if (!NowDeadNodes.empty())
1610 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1612 DEBUG(errs() << "ISEL: Match complete!\n");
1618 CR_LeadsToInteriorNode
1621 /// WalkChainUsers - Walk down the users of the specified chained node that is
1622 /// part of the pattern we're matching, looking at all of the users we find.
1623 /// This determines whether something is an interior node, whether we have a
1624 /// non-pattern node in between two pattern nodes (which prevent folding because
1625 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1626 /// between pattern nodes (in which case the TF becomes part of the pattern).
1628 /// The walk we do here is guaranteed to be small because we quickly get down to
1629 /// already selected nodes "below" us.
1631 WalkChainUsers(SDNode *ChainedNode,
1632 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1633 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1634 ChainResult Result = CR_Simple;
1636 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1637 E = ChainedNode->use_end(); UI != E; ++UI) {
1638 // Make sure the use is of the chain, not some other value we produce.
1639 if (UI.getUse().getValueType() != MVT::Other) continue;
1643 // If we see an already-selected machine node, then we've gone beyond the
1644 // pattern that we're selecting down into the already selected chunk of the
1646 if (User->isMachineOpcode() ||
1647 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1650 if (User->getOpcode() == ISD::CopyToReg ||
1651 User->getOpcode() == ISD::CopyFromReg ||
1652 User->getOpcode() == ISD::INLINEASM ||
1653 User->getOpcode() == ISD::EH_LABEL) {
1654 // If their node ID got reset to -1 then they've already been selected.
1655 // Treat them like a MachineOpcode.
1656 if (User->getNodeId() == -1)
1660 // If we have a TokenFactor, we handle it specially.
1661 if (User->getOpcode() != ISD::TokenFactor) {
1662 // If the node isn't a token factor and isn't part of our pattern, then it
1663 // must be a random chained node in between two nodes we're selecting.
1664 // This happens when we have something like:
1669 // Because we structurally match the load/store as a read/modify/write,
1670 // but the call is chained between them. We cannot fold in this case
1671 // because it would induce a cycle in the graph.
1672 if (!std::count(ChainedNodesInPattern.begin(),
1673 ChainedNodesInPattern.end(), User))
1674 return CR_InducesCycle;
1676 // Otherwise we found a node that is part of our pattern. For example in:
1680 // This would happen when we're scanning down from the load and see the
1681 // store as a user. Record that there is a use of ChainedNode that is
1682 // part of the pattern and keep scanning uses.
1683 Result = CR_LeadsToInteriorNode;
1684 InteriorChainedNodes.push_back(User);
1688 // If we found a TokenFactor, there are two cases to consider: first if the
1689 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1690 // uses of the TF are in our pattern) we just want to ignore it. Second,
1691 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1697 // | \ DAG's like cheese
1700 // [TokenFactor] [Op]
1707 // In this case, the TokenFactor becomes part of our match and we rewrite it
1708 // as a new TokenFactor.
1710 // To distinguish these two cases, do a recursive walk down the uses.
1711 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1713 // If the uses of the TokenFactor are just already-selected nodes, ignore
1714 // it, it is "below" our pattern.
1716 case CR_InducesCycle:
1717 // If the uses of the TokenFactor lead to nodes that are not part of our
1718 // pattern that are not selected, folding would turn this into a cycle,
1720 return CR_InducesCycle;
1721 case CR_LeadsToInteriorNode:
1722 break; // Otherwise, keep processing.
1725 // Okay, we know we're in the interesting interior case. The TokenFactor
1726 // is now going to be considered part of the pattern so that we rewrite its
1727 // uses (it may have uses that are not part of the pattern) with the
1728 // ultimate chain result of the generated code. We will also add its chain
1729 // inputs as inputs to the ultimate TokenFactor we create.
1730 Result = CR_LeadsToInteriorNode;
1731 ChainedNodesInPattern.push_back(User);
1732 InteriorChainedNodes.push_back(User);
1739 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1740 /// operation for when the pattern matched at least one node with a chains. The
1741 /// input vector contains a list of all of the chained nodes that we match. We
1742 /// must determine if this is a valid thing to cover (i.e. matching it won't
1743 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1744 /// be used as the input node chain for the generated nodes.
1746 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1747 SelectionDAG *CurDAG) {
1748 // Walk all of the chained nodes we've matched, recursively scanning down the
1749 // users of the chain result. This adds any TokenFactor nodes that are caught
1750 // in between chained nodes to the chained and interior nodes list.
1751 SmallVector<SDNode*, 3> InteriorChainedNodes;
1752 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1753 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1754 InteriorChainedNodes) == CR_InducesCycle)
1755 return SDValue(); // Would induce a cycle.
1758 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1759 // that we are interested in. Form our input TokenFactor node.
1760 SmallVector<SDValue, 3> InputChains;
1761 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1762 // Add the input chain of this node to the InputChains list (which will be
1763 // the operands of the generated TokenFactor) if it's not an interior node.
1764 SDNode *N = ChainNodesMatched[i];
1765 if (N->getOpcode() != ISD::TokenFactor) {
1766 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1769 // Otherwise, add the input chain.
1770 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1771 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1772 InputChains.push_back(InChain);
1776 // If we have a token factor, we want to add all inputs of the token factor
1777 // that are not part of the pattern we're matching.
1778 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1779 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1780 N->getOperand(op).getNode()))
1781 InputChains.push_back(N->getOperand(op));
1786 if (InputChains.size() == 1)
1787 return InputChains[0];
1788 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1789 MVT::Other, &InputChains[0], InputChains.size());
1792 /// MorphNode - Handle morphing a node in place for the selector.
1793 SDNode *SelectionDAGISel::
1794 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1795 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1796 // It is possible we're using MorphNodeTo to replace a node with no
1797 // normal results with one that has a normal result (or we could be
1798 // adding a chain) and the input could have flags and chains as well.
1799 // In this case we need to shift the operands down.
1800 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1801 // than the old isel though.
1802 int OldFlagResultNo = -1, OldChainResultNo = -1;
1804 unsigned NTMNumResults = Node->getNumValues();
1805 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1806 OldFlagResultNo = NTMNumResults-1;
1807 if (NTMNumResults != 1 &&
1808 Node->getValueType(NTMNumResults-2) == MVT::Other)
1809 OldChainResultNo = NTMNumResults-2;
1810 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1811 OldChainResultNo = NTMNumResults-1;
1813 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1814 // that this deletes operands of the old node that become dead.
1815 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1817 // MorphNodeTo can operate in two ways: if an existing node with the
1818 // specified operands exists, it can just return it. Otherwise, it
1819 // updates the node in place to have the requested operands.
1821 // If we updated the node in place, reset the node ID. To the isel,
1822 // this should be just like a newly allocated machine node.
1826 unsigned ResNumResults = Res->getNumValues();
1827 // Move the flag if needed.
1828 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1829 (unsigned)OldFlagResultNo != ResNumResults-1)
1830 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1831 SDValue(Res, ResNumResults-1));
1833 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1836 // Move the chain reference if needed.
1837 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1838 (unsigned)OldChainResultNo != ResNumResults-1)
1839 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1840 SDValue(Res, ResNumResults-1));
1842 // Otherwise, no replacement happened because the node already exists. Replace
1843 // Uses of the old node with the new one.
1845 CurDAG->ReplaceAllUsesWith(Node, Res);
1850 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1851 ALWAYS_INLINE static bool
1852 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1853 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1854 // Accept if it is exactly the same as a previously recorded node.
1855 unsigned RecNo = MatcherTable[MatcherIndex++];
1856 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1857 return N == RecordedNodes[RecNo];
1860 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1861 ALWAYS_INLINE static bool
1862 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1863 SelectionDAGISel &SDISel) {
1864 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1867 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1868 ALWAYS_INLINE static bool
1869 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1870 SelectionDAGISel &SDISel, SDNode *N) {
1871 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1874 ALWAYS_INLINE static bool
1875 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1877 uint16_t Opc = MatcherTable[MatcherIndex++];
1878 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1879 return N->getOpcode() == Opc;
1882 ALWAYS_INLINE static bool
1883 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1884 SDValue N, const TargetLowering &TLI) {
1885 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1886 if (N.getValueType() == VT) return true;
1888 // Handle the case when VT is iPTR.
1889 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1892 ALWAYS_INLINE static bool
1893 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1894 SDValue N, const TargetLowering &TLI,
1896 if (ChildNo >= N.getNumOperands())
1897 return false; // Match fails if out of range child #.
1898 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1902 ALWAYS_INLINE static bool
1903 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1905 return cast<CondCodeSDNode>(N)->get() ==
1906 (ISD::CondCode)MatcherTable[MatcherIndex++];
1909 ALWAYS_INLINE static bool
1910 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1911 SDValue N, const TargetLowering &TLI) {
1912 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1913 if (cast<VTSDNode>(N)->getVT() == VT)
1916 // Handle the case when VT is iPTR.
1917 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1920 ALWAYS_INLINE static bool
1921 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1923 int64_t Val = MatcherTable[MatcherIndex++];
1925 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1927 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1928 return C != 0 && C->getSExtValue() == Val;
1931 ALWAYS_INLINE static bool
1932 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1933 SDValue N, SelectionDAGISel &SDISel) {
1934 int64_t Val = MatcherTable[MatcherIndex++];
1936 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1938 if (N->getOpcode() != ISD::AND) return false;
1940 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1941 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1944 ALWAYS_INLINE static bool
1945 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1946 SDValue N, SelectionDAGISel &SDISel) {
1947 int64_t Val = MatcherTable[MatcherIndex++];
1949 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1951 if (N->getOpcode() != ISD::OR) return false;
1953 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1954 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1957 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1958 /// scope, evaluate the current node. If the current predicate is known to
1959 /// fail, set Result=true and return anything. If the current predicate is
1960 /// known to pass, set Result=false and return the MatcherIndex to continue
1961 /// with. If the current predicate is unknown, set Result=false and return the
1962 /// MatcherIndex to continue with.
1963 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1964 unsigned Index, SDValue N,
1965 bool &Result, SelectionDAGISel &SDISel,
1966 SmallVectorImpl<SDValue> &RecordedNodes){
1967 switch (Table[Index++]) {
1970 return Index-1; // Could not evaluate this predicate.
1971 case SelectionDAGISel::OPC_CheckSame:
1972 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1974 case SelectionDAGISel::OPC_CheckPatternPredicate:
1975 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1977 case SelectionDAGISel::OPC_CheckPredicate:
1978 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1980 case SelectionDAGISel::OPC_CheckOpcode:
1981 Result = !::CheckOpcode(Table, Index, N.getNode());
1983 case SelectionDAGISel::OPC_CheckType:
1984 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1986 case SelectionDAGISel::OPC_CheckChild0Type:
1987 case SelectionDAGISel::OPC_CheckChild1Type:
1988 case SelectionDAGISel::OPC_CheckChild2Type:
1989 case SelectionDAGISel::OPC_CheckChild3Type:
1990 case SelectionDAGISel::OPC_CheckChild4Type:
1991 case SelectionDAGISel::OPC_CheckChild5Type:
1992 case SelectionDAGISel::OPC_CheckChild6Type:
1993 case SelectionDAGISel::OPC_CheckChild7Type:
1994 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1995 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1997 case SelectionDAGISel::OPC_CheckCondCode:
1998 Result = !::CheckCondCode(Table, Index, N);
2000 case SelectionDAGISel::OPC_CheckValueType:
2001 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2003 case SelectionDAGISel::OPC_CheckInteger:
2004 Result = !::CheckInteger(Table, Index, N);
2006 case SelectionDAGISel::OPC_CheckAndImm:
2007 Result = !::CheckAndImm(Table, Index, N, SDISel);
2009 case SelectionDAGISel::OPC_CheckOrImm:
2010 Result = !::CheckOrImm(Table, Index, N, SDISel);
2017 /// FailIndex - If this match fails, this is the index to continue with.
2020 /// NodeStack - The node stack when the scope was formed.
2021 SmallVector<SDValue, 4> NodeStack;
2023 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2024 unsigned NumRecordedNodes;
2026 /// NumMatchedMemRefs - The number of matched memref entries.
2027 unsigned NumMatchedMemRefs;
2029 /// InputChain/InputFlag - The current chain/flag
2030 SDValue InputChain, InputFlag;
2032 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2033 bool HasChainNodesMatched, HasFlagResultNodesMatched;
2036 SDNode *SelectionDAGISel::
2037 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2038 unsigned TableSize) {
2039 // FIXME: Should these even be selected? Handle these cases in the caller?
2040 switch (NodeToMatch->getOpcode()) {
2043 case ISD::EntryToken: // These nodes remain the same.
2044 case ISD::BasicBlock:
2046 //case ISD::VALUETYPE:
2047 //case ISD::CONDCODE:
2048 case ISD::HANDLENODE:
2049 case ISD::MDNODE_SDNODE:
2050 case ISD::TargetConstant:
2051 case ISD::TargetConstantFP:
2052 case ISD::TargetConstantPool:
2053 case ISD::TargetFrameIndex:
2054 case ISD::TargetExternalSymbol:
2055 case ISD::TargetBlockAddress:
2056 case ISD::TargetJumpTable:
2057 case ISD::TargetGlobalTLSAddress:
2058 case ISD::TargetGlobalAddress:
2059 case ISD::TokenFactor:
2060 case ISD::CopyFromReg:
2061 case ISD::CopyToReg:
2063 NodeToMatch->setNodeId(-1); // Mark selected.
2065 case ISD::AssertSext:
2066 case ISD::AssertZext:
2067 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2068 NodeToMatch->getOperand(0));
2070 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2071 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2074 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2076 // Set up the node stack with NodeToMatch as the only node on the stack.
2077 SmallVector<SDValue, 8> NodeStack;
2078 SDValue N = SDValue(NodeToMatch, 0);
2079 NodeStack.push_back(N);
2081 // MatchScopes - Scopes used when matching, if a match failure happens, this
2082 // indicates where to continue checking.
2083 SmallVector<MatchScope, 8> MatchScopes;
2085 // RecordedNodes - This is the set of nodes that have been recorded by the
2087 SmallVector<SDValue, 8> RecordedNodes;
2089 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2091 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2093 // These are the current input chain and flag for use when generating nodes.
2094 // Various Emit operations change these. For example, emitting a copytoreg
2095 // uses and updates these.
2096 SDValue InputChain, InputFlag;
2098 // ChainNodesMatched - If a pattern matches nodes that have input/output
2099 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2100 // which ones they are. The result is captured into this list so that we can
2101 // update the chain results when the pattern is complete.
2102 SmallVector<SDNode*, 3> ChainNodesMatched;
2103 SmallVector<SDNode*, 3> FlagResultNodesMatched;
2105 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2106 NodeToMatch->dump(CurDAG);
2109 // Determine where to start the interpreter. Normally we start at opcode #0,
2110 // but if the state machine starts with an OPC_SwitchOpcode, then we
2111 // accelerate the first lookup (which is guaranteed to be hot) with the
2112 // OpcodeOffset table.
2113 unsigned MatcherIndex = 0;
2115 if (!OpcodeOffset.empty()) {
2116 // Already computed the OpcodeOffset table, just index into it.
2117 if (N.getOpcode() < OpcodeOffset.size())
2118 MatcherIndex = OpcodeOffset[N.getOpcode()];
2119 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2121 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2122 // Otherwise, the table isn't computed, but the state machine does start
2123 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2124 // is the first time we're selecting an instruction.
2127 // Get the size of this case.
2128 unsigned CaseSize = MatcherTable[Idx++];
2130 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2131 if (CaseSize == 0) break;
2133 // Get the opcode, add the index to the table.
2134 uint16_t Opc = MatcherTable[Idx++];
2135 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2136 if (Opc >= OpcodeOffset.size())
2137 OpcodeOffset.resize((Opc+1)*2);
2138 OpcodeOffset[Opc] = Idx;
2142 // Okay, do the lookup for the first opcode.
2143 if (N.getOpcode() < OpcodeOffset.size())
2144 MatcherIndex = OpcodeOffset[N.getOpcode()];
2148 assert(MatcherIndex < TableSize && "Invalid index");
2150 unsigned CurrentOpcodeIndex = MatcherIndex;
2152 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2155 // Okay, the semantics of this operation are that we should push a scope
2156 // then evaluate the first child. However, pushing a scope only to have
2157 // the first check fail (which then pops it) is inefficient. If we can
2158 // determine immediately that the first check (or first several) will
2159 // immediately fail, don't even bother pushing a scope for them.
2163 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2164 if (NumToSkip & 128)
2165 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2166 // Found the end of the scope with no match.
2167 if (NumToSkip == 0) {
2172 FailIndex = MatcherIndex+NumToSkip;
2174 unsigned MatcherIndexOfPredicate = MatcherIndex;
2175 (void)MatcherIndexOfPredicate; // silence warning.
2177 // If we can't evaluate this predicate without pushing a scope (e.g. if
2178 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2179 // push the scope and evaluate the full predicate chain.
2181 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2182 Result, *this, RecordedNodes);
2186 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2187 << "index " << MatcherIndexOfPredicate
2188 << ", continuing at " << FailIndex << "\n");
2189 ++NumDAGIselRetries;
2191 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2192 // move to the next case.
2193 MatcherIndex = FailIndex;
2196 // If the whole scope failed to match, bail.
2197 if (FailIndex == 0) break;
2199 // Push a MatchScope which indicates where to go if the first child fails
2201 MatchScope NewEntry;
2202 NewEntry.FailIndex = FailIndex;
2203 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2204 NewEntry.NumRecordedNodes = RecordedNodes.size();
2205 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2206 NewEntry.InputChain = InputChain;
2207 NewEntry.InputFlag = InputFlag;
2208 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2209 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2210 MatchScopes.push_back(NewEntry);
2213 case OPC_RecordNode:
2214 // Remember this node, it may end up being an operand in the pattern.
2215 RecordedNodes.push_back(N);
2218 case OPC_RecordChild0: case OPC_RecordChild1:
2219 case OPC_RecordChild2: case OPC_RecordChild3:
2220 case OPC_RecordChild4: case OPC_RecordChild5:
2221 case OPC_RecordChild6: case OPC_RecordChild7: {
2222 unsigned ChildNo = Opcode-OPC_RecordChild0;
2223 if (ChildNo >= N.getNumOperands())
2224 break; // Match fails if out of range child #.
2226 RecordedNodes.push_back(N->getOperand(ChildNo));
2229 case OPC_RecordMemRef:
2230 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2233 case OPC_CaptureFlagInput:
2234 // If the current node has an input flag, capture it in InputFlag.
2235 if (N->getNumOperands() != 0 &&
2236 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2237 InputFlag = N->getOperand(N->getNumOperands()-1);
2240 case OPC_MoveChild: {
2241 unsigned ChildNo = MatcherTable[MatcherIndex++];
2242 if (ChildNo >= N.getNumOperands())
2243 break; // Match fails if out of range child #.
2244 N = N.getOperand(ChildNo);
2245 NodeStack.push_back(N);
2249 case OPC_MoveParent:
2250 // Pop the current node off the NodeStack.
2251 NodeStack.pop_back();
2252 assert(!NodeStack.empty() && "Node stack imbalance!");
2253 N = NodeStack.back();
2257 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2259 case OPC_CheckPatternPredicate:
2260 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2262 case OPC_CheckPredicate:
2263 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2267 case OPC_CheckComplexPat: {
2268 unsigned CPNum = MatcherTable[MatcherIndex++];
2269 unsigned RecNo = MatcherTable[MatcherIndex++];
2270 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2271 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2276 case OPC_CheckOpcode:
2277 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2281 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2284 case OPC_SwitchOpcode: {
2285 unsigned CurNodeOpcode = N.getOpcode();
2286 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2289 // Get the size of this case.
2290 CaseSize = MatcherTable[MatcherIndex++];
2292 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2293 if (CaseSize == 0) break;
2295 uint16_t Opc = MatcherTable[MatcherIndex++];
2296 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2298 // If the opcode matches, then we will execute this case.
2299 if (CurNodeOpcode == Opc)
2302 // Otherwise, skip over this case.
2303 MatcherIndex += CaseSize;
2306 // If no cases matched, bail out.
2307 if (CaseSize == 0) break;
2309 // Otherwise, execute the case we found.
2310 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2311 << " to " << MatcherIndex << "\n");
2315 case OPC_SwitchType: {
2316 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2317 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2320 // Get the size of this case.
2321 CaseSize = MatcherTable[MatcherIndex++];
2323 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2324 if (CaseSize == 0) break;
2326 MVT::SimpleValueType CaseVT =
2327 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2328 if (CaseVT == MVT::iPTR)
2329 CaseVT = TLI.getPointerTy().SimpleTy;
2331 // If the VT matches, then we will execute this case.
2332 if (CurNodeVT == CaseVT)
2335 // Otherwise, skip over this case.
2336 MatcherIndex += CaseSize;
2339 // If no cases matched, bail out.
2340 if (CaseSize == 0) break;
2342 // Otherwise, execute the case we found.
2343 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2344 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2347 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2348 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2349 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2350 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2351 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2352 Opcode-OPC_CheckChild0Type))
2355 case OPC_CheckCondCode:
2356 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2358 case OPC_CheckValueType:
2359 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2361 case OPC_CheckInteger:
2362 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2364 case OPC_CheckAndImm:
2365 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2367 case OPC_CheckOrImm:
2368 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2371 case OPC_CheckFoldableChainNode: {
2372 assert(NodeStack.size() != 1 && "No parent node");
2373 // Verify that all intermediate nodes between the root and this one have
2375 bool HasMultipleUses = false;
2376 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2377 if (!NodeStack[i].hasOneUse()) {
2378 HasMultipleUses = true;
2381 if (HasMultipleUses) break;
2383 // Check to see that the target thinks this is profitable to fold and that
2384 // we can fold it without inducing cycles in the graph.
2385 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2387 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2388 NodeToMatch, true/*We validate our own chains*/))
2393 case OPC_EmitInteger: {
2394 MVT::SimpleValueType VT =
2395 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2396 int64_t Val = MatcherTable[MatcherIndex++];
2398 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2399 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2402 case OPC_EmitRegister: {
2403 MVT::SimpleValueType VT =
2404 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2405 unsigned RegNo = MatcherTable[MatcherIndex++];
2406 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2410 case OPC_EmitConvertToTarget: {
2411 // Convert from IMM/FPIMM to target version.
2412 unsigned RecNo = MatcherTable[MatcherIndex++];
2413 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2414 SDValue Imm = RecordedNodes[RecNo];
2416 if (Imm->getOpcode() == ISD::Constant) {
2417 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2418 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2419 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2420 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2421 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2424 RecordedNodes.push_back(Imm);
2428 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2429 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2430 // These are space-optimized forms of OPC_EmitMergeInputChains.
2431 assert(InputChain.getNode() == 0 &&
2432 "EmitMergeInputChains should be the first chain producing node");
2433 assert(ChainNodesMatched.empty() &&
2434 "Should only have one EmitMergeInputChains per match");
2436 // Read all of the chained nodes.
2437 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2438 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2439 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2441 // FIXME: What if other value results of the node have uses not matched
2443 if (ChainNodesMatched.back() != NodeToMatch &&
2444 !RecordedNodes[RecNo].hasOneUse()) {
2445 ChainNodesMatched.clear();
2449 // Merge the input chains if they are not intra-pattern references.
2450 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2452 if (InputChain.getNode() == 0)
2453 break; // Failed to merge.
2457 case OPC_EmitMergeInputChains: {
2458 assert(InputChain.getNode() == 0 &&
2459 "EmitMergeInputChains should be the first chain producing node");
2460 // This node gets a list of nodes we matched in the input that have
2461 // chains. We want to token factor all of the input chains to these nodes
2462 // together. However, if any of the input chains is actually one of the
2463 // nodes matched in this pattern, then we have an intra-match reference.
2464 // Ignore these because the newly token factored chain should not refer to
2466 unsigned NumChains = MatcherTable[MatcherIndex++];
2467 assert(NumChains != 0 && "Can't TF zero chains");
2469 assert(ChainNodesMatched.empty() &&
2470 "Should only have one EmitMergeInputChains per match");
2472 // Read all of the chained nodes.
2473 for (unsigned i = 0; i != NumChains; ++i) {
2474 unsigned RecNo = MatcherTable[MatcherIndex++];
2475 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2476 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2478 // FIXME: What if other value results of the node have uses not matched
2480 if (ChainNodesMatched.back() != NodeToMatch &&
2481 !RecordedNodes[RecNo].hasOneUse()) {
2482 ChainNodesMatched.clear();
2487 // If the inner loop broke out, the match fails.
2488 if (ChainNodesMatched.empty())
2491 // Merge the input chains if they are not intra-pattern references.
2492 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2494 if (InputChain.getNode() == 0)
2495 break; // Failed to merge.
2500 case OPC_EmitCopyToReg: {
2501 unsigned RecNo = MatcherTable[MatcherIndex++];
2502 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2503 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2505 if (InputChain.getNode() == 0)
2506 InputChain = CurDAG->getEntryNode();
2508 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2509 DestPhysReg, RecordedNodes[RecNo],
2512 InputFlag = InputChain.getValue(1);
2516 case OPC_EmitNodeXForm: {
2517 unsigned XFormNo = MatcherTable[MatcherIndex++];
2518 unsigned RecNo = MatcherTable[MatcherIndex++];
2519 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2520 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2525 case OPC_MorphNodeTo: {
2526 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2527 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2528 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2529 // Get the result VT list.
2530 unsigned NumVTs = MatcherTable[MatcherIndex++];
2531 SmallVector<EVT, 4> VTs;
2532 for (unsigned i = 0; i != NumVTs; ++i) {
2533 MVT::SimpleValueType VT =
2534 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2535 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2539 if (EmitNodeInfo & OPFL_Chain)
2540 VTs.push_back(MVT::Other);
2541 if (EmitNodeInfo & OPFL_FlagOutput)
2542 VTs.push_back(MVT::Flag);
2544 // This is hot code, so optimize the two most common cases of 1 and 2
2547 if (VTs.size() == 1)
2548 VTList = CurDAG->getVTList(VTs[0]);
2549 else if (VTs.size() == 2)
2550 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2552 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2554 // Get the operand list.
2555 unsigned NumOps = MatcherTable[MatcherIndex++];
2556 SmallVector<SDValue, 8> Ops;
2557 for (unsigned i = 0; i != NumOps; ++i) {
2558 unsigned RecNo = MatcherTable[MatcherIndex++];
2560 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2562 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2563 Ops.push_back(RecordedNodes[RecNo]);
2566 // If there are variadic operands to add, handle them now.
2567 if (EmitNodeInfo & OPFL_VariadicInfo) {
2568 // Determine the start index to copy from.
2569 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2570 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2571 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2572 "Invalid variadic node");
2573 // Copy all of the variadic operands, not including a potential flag
2575 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2577 SDValue V = NodeToMatch->getOperand(i);
2578 if (V.getValueType() == MVT::Flag) break;
2583 // If this has chain/flag inputs, add them.
2584 if (EmitNodeInfo & OPFL_Chain)
2585 Ops.push_back(InputChain);
2586 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2587 Ops.push_back(InputFlag);
2591 if (Opcode != OPC_MorphNodeTo) {
2592 // If this is a normal EmitNode command, just create the new node and
2593 // add the results to the RecordedNodes list.
2594 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2595 VTList, Ops.data(), Ops.size());
2597 // Add all the non-flag/non-chain results to the RecordedNodes list.
2598 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2599 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2600 RecordedNodes.push_back(SDValue(Res, i));
2604 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2608 // If the node had chain/flag results, update our notion of the current
2610 if (EmitNodeInfo & OPFL_FlagOutput) {
2611 InputFlag = SDValue(Res, VTs.size()-1);
2612 if (EmitNodeInfo & OPFL_Chain)
2613 InputChain = SDValue(Res, VTs.size()-2);
2614 } else if (EmitNodeInfo & OPFL_Chain)
2615 InputChain = SDValue(Res, VTs.size()-1);
2617 // If the OPFL_MemRefs flag is set on this node, slap all of the
2618 // accumulated memrefs onto it.
2620 // FIXME: This is vastly incorrect for patterns with multiple outputs
2621 // instructions that access memory and for ComplexPatterns that match
2623 if (EmitNodeInfo & OPFL_MemRefs) {
2624 MachineSDNode::mmo_iterator MemRefs =
2625 MF->allocateMemRefsArray(MatchedMemRefs.size());
2626 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2627 cast<MachineSDNode>(Res)
2628 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2632 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2633 << " node: "; Res->dump(CurDAG); errs() << "\n");
2635 // If this was a MorphNodeTo then we're completely done!
2636 if (Opcode == OPC_MorphNodeTo) {
2637 // Update chain and flag uses.
2638 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2639 InputFlag, FlagResultNodesMatched, true);
2646 case OPC_MarkFlagResults: {
2647 unsigned NumNodes = MatcherTable[MatcherIndex++];
2649 // Read and remember all the flag-result nodes.
2650 for (unsigned i = 0; i != NumNodes; ++i) {
2651 unsigned RecNo = MatcherTable[MatcherIndex++];
2653 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2655 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2656 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2661 case OPC_CompleteMatch: {
2662 // The match has been completed, and any new nodes (if any) have been
2663 // created. Patch up references to the matched dag to use the newly
2665 unsigned NumResults = MatcherTable[MatcherIndex++];
2667 for (unsigned i = 0; i != NumResults; ++i) {
2668 unsigned ResSlot = MatcherTable[MatcherIndex++];
2670 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2672 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2673 SDValue Res = RecordedNodes[ResSlot];
2675 assert(i < NodeToMatch->getNumValues() &&
2676 NodeToMatch->getValueType(i) != MVT::Other &&
2677 NodeToMatch->getValueType(i) != MVT::Flag &&
2678 "Invalid number of results to complete!");
2679 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2680 NodeToMatch->getValueType(i) == MVT::iPTR ||
2681 Res.getValueType() == MVT::iPTR ||
2682 NodeToMatch->getValueType(i).getSizeInBits() ==
2683 Res.getValueType().getSizeInBits()) &&
2684 "invalid replacement");
2685 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2688 // If the root node defines a flag, add it to the flag nodes to update
2690 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2691 FlagResultNodesMatched.push_back(NodeToMatch);
2693 // Update chain and flag uses.
2694 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2695 InputFlag, FlagResultNodesMatched, false);
2697 assert(NodeToMatch->use_empty() &&
2698 "Didn't replace all uses of the node?");
2700 // FIXME: We just return here, which interacts correctly with SelectRoot
2701 // above. We should fix this to not return an SDNode* anymore.
2706 // If the code reached this point, then the match failed. See if there is
2707 // another child to try in the current 'Scope', otherwise pop it until we
2708 // find a case to check.
2709 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2710 ++NumDAGIselRetries;
2712 if (MatchScopes.empty()) {
2713 CannotYetSelect(NodeToMatch);
2717 // Restore the interpreter state back to the point where the scope was
2719 MatchScope &LastScope = MatchScopes.back();
2720 RecordedNodes.resize(LastScope.NumRecordedNodes);
2722 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2723 N = NodeStack.back();
2725 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2726 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2727 MatcherIndex = LastScope.FailIndex;
2729 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2731 InputChain = LastScope.InputChain;
2732 InputFlag = LastScope.InputFlag;
2733 if (!LastScope.HasChainNodesMatched)
2734 ChainNodesMatched.clear();
2735 if (!LastScope.HasFlagResultNodesMatched)
2736 FlagResultNodesMatched.clear();
2738 // Check to see what the offset is at the new MatcherIndex. If it is zero
2739 // we have reached the end of this scope, otherwise we have another child
2740 // in the current scope to try.
2741 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2742 if (NumToSkip & 128)
2743 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2745 // If we have another child in this scope to match, update FailIndex and
2747 if (NumToSkip != 0) {
2748 LastScope.FailIndex = MatcherIndex+NumToSkip;
2752 // End of this scope, pop it and try the next child in the containing
2754 MatchScopes.pop_back();
2761 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2763 raw_string_ostream Msg(msg);
2764 Msg << "Cannot yet select: ";
2766 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2767 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2768 N->getOpcode() != ISD::INTRINSIC_VOID) {
2769 N->printrFull(Msg, CurDAG);
2771 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2773 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2774 if (iid < Intrinsic::num_intrinsics)
2775 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2776 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2777 Msg << "target intrinsic %" << TII->getName(iid);
2779 Msg << "unknown intrinsic #" << iid;
2781 llvm_report_error(Msg.str());
2784 char SelectionDAGISel::ID = 0;